[mirror_ubuntu-focal-kernel.git] / drivers / mtd / nand / gpio.c

/*
 * drivers/mtd/nand/gpio.c
 *
 * Updated, and converted to generic GPIO based driver by Russell King.
 *
 * Written by Ben Dooks <ben@simtec.co.uk>
 *   Based on 2.4 version by Mark Whittaker
 *
 * © 2004 Simtec Electronics
 *
 * Device driver for NAND flash that uses a memory mapped interface to
 * read/write the NAND commands and data, and GPIO pins for control signals
 * (the DT binding refers to this as "GPIO assisted NAND flash")
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/gpio/consumer.h>
#include <linux/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/nand-gpio.h>
#include <linux/of.h>
#include <linux/of_address.h>

struct gpiomtd {
	void __iomem		*io_sync;
	struct nand_chip	nand_chip;
	struct gpio_nand_platdata plat;
	struct gpio_desc *nce; /* Optional chip enable */
	struct gpio_desc *cle;
	struct gpio_desc *ale;
	struct gpio_desc *rdy;
	struct gpio_desc *nwp; /* Optional write protection */
};

static inline struct gpiomtd *gpio_nand_getpriv(struct mtd_info *mtd)
{
	return container_of(mtd_to_nand(mtd), struct gpiomtd, nand_chip);
}


#ifdef CONFIG_ARM
/* gpio_nand_dosync()
 *
 * Make sure the GPIO state changes occur in-order with writes to NAND
 * memory region.
 * Needed on PXA due to bus-reordering within the SoC itself (see section on
 * I/O ordering in PXA manual (section 2.3, p35)
 */
static void gpio_nand_dosync(struct gpiomtd *gpiomtd)
{
	unsigned long tmp;

	if (gpiomtd->io_sync) {
		/*
		 * Linux memory barriers don't cater for what's required here.
		 * What's required is what's here - a read from a separate
		 * region with a dependency on that read.
		 */
		tmp = readl(gpiomtd->io_sync);
		asm volatile("mov %1, %0\n" : "=r" (tmp) : "r" (tmp));
	}
}
#else
static inline void gpio_nand_dosync(struct gpiomtd *gpiomtd) {}
#endif

static void gpio_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);

	gpio_nand_dosync(gpiomtd);

	if (ctrl & NAND_CTRL_CHANGE) {
		if (gpiomtd->nce)
			gpiod_set_value(gpiomtd->nce, !(ctrl & NAND_NCE));
		gpiod_set_value(gpiomtd->cle, !!(ctrl & NAND_CLE));
		gpiod_set_value(gpiomtd->ale, !!(ctrl & NAND_ALE));
		gpio_nand_dosync(gpiomtd);
	}
	if (cmd == NAND_CMD_NONE)
		return;

	writeb(cmd, gpiomtd->nand_chip.IO_ADDR_W);
	gpio_nand_dosync(gpiomtd);
}

static int gpio_nand_devready(struct mtd_info *mtd)
{
	struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);

	return gpiod_get_value(gpiomtd->rdy);
}

#ifdef CONFIG_OF
static const struct of_device_id gpio_nand_id_table[] = {
	{ .compatible = "gpio-control-nand" },
	{}
};
MODULE_DEVICE_TABLE(of, gpio_nand_id_table);

static int gpio_nand_get_config_of(const struct device *dev,
				   struct gpio_nand_platdata *plat)
{
	u32 val;

	if (!dev->of_node)
		return -ENODEV;

	if (!of_property_read_u32(dev->of_node, "bank-width", &val)) {
		if (val == 2) {
			plat->options |= NAND_BUSWIDTH_16;
		} else if (val != 1) {
			dev_err(dev, "invalid bank-width %u\n", val);
			return -EINVAL;
		}
	}

	if (!of_property_read_u32(dev->of_node, "chip-delay", &val))
		plat->chip_delay = val;

	return 0;
}

static struct resource *gpio_nand_get_io_sync_of(struct platform_device *pdev)
{
	struct resource *r;
	u64 addr;

	if (of_property_read_u64(pdev->dev.of_node,
				       "gpio-control-nand,io-sync-reg", &addr))
		return NULL;

	r = devm_kzalloc(&pdev->dev, sizeof(*r), GFP_KERNEL);
	if (!r)
		return NULL;

	r->start = addr;
	r->end = r->start + 0x3;
	r->flags = IORESOURCE_MEM;

	return r;
}
#else /* CONFIG_OF */
static inline int gpio_nand_get_config_of(const struct device *dev,
					  struct gpio_nand_platdata *plat)
{
	return -ENOSYS;
}

static inline struct resource *
gpio_nand_get_io_sync_of(struct platform_device *pdev)
{
	return NULL;
}
#endif /* CONFIG_OF */

static inline int gpio_nand_get_config(const struct device *dev,
				       struct gpio_nand_platdata *plat)
{
	int ret = gpio_nand_get_config_of(dev, plat);

	if (!ret)
		return ret;

	if (dev_get_platdata(dev)) {
		memcpy(plat, dev_get_platdata(dev), sizeof(*plat));
		return 0;
	}

	return -EINVAL;
}

static inline struct resource *
gpio_nand_get_io_sync(struct platform_device *pdev)
{
	struct resource *r = gpio_nand_get_io_sync_of(pdev);

	if (r)
		return r;

	return platform_get_resource(pdev, IORESOURCE_MEM, 1);
}

static int gpio_nand_remove(struct platform_device *pdev)
{
	struct gpiomtd *gpiomtd = platform_get_drvdata(pdev);

	nand_release(nand_to_mtd(&gpiomtd->nand_chip));

	/* Enable write protection and disable the chip */
	if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp))
		gpiod_set_value(gpiomtd->nwp, 0);
	if (gpiomtd->nce && !IS_ERR(gpiomtd->nce))
		gpiod_set_value(gpiomtd->nce, 0);

	return 0;
}

static int gpio_nand_probe(struct platform_device *pdev)
{
	struct gpiomtd *gpiomtd;
	struct nand_chip *chip;
	struct mtd_info *mtd;
	struct resource *res;
	struct device *dev = &pdev->dev;
	int ret = 0;

	if (!dev->of_node && !dev_get_platdata(dev))
		return -EINVAL;

	gpiomtd = devm_kzalloc(dev, sizeof(*gpiomtd), GFP_KERNEL);
	if (!gpiomtd)
		return -ENOMEM;

	chip = &gpiomtd->nand_chip;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	chip->IO_ADDR_R = devm_ioremap_resource(dev, res);
	if (IS_ERR(chip->IO_ADDR_R))
		return PTR_ERR(chip->IO_ADDR_R);

	res = gpio_nand_get_io_sync(pdev);
	if (res) {
		gpiomtd->io_sync = devm_ioremap_resource(dev, res);
		if (IS_ERR(gpiomtd->io_sync))
			return PTR_ERR(gpiomtd->io_sync);
	}

	ret = gpio_nand_get_config(dev, &gpiomtd->plat);
	if (ret)
		return ret;

	/* Just enable the chip */
	gpiomtd->nce = devm_gpiod_get_optional(dev, "nce", GPIOD_OUT_HIGH);
	if (IS_ERR(gpiomtd->nce))
		return PTR_ERR(gpiomtd->nce);

	/* We disable write protection once we know probe() will succeed */
	gpiomtd->nwp = devm_gpiod_get_optional(dev, "nwp", GPIOD_OUT_LOW);
	if (IS_ERR(gpiomtd->nwp)) {
		ret = PTR_ERR(gpiomtd->nwp);
		goto out_ce;
	}

	gpiomtd->ale = devm_gpiod_get(dev, "ale", GPIOD_OUT_LOW);
	if (IS_ERR(gpiomtd->ale)) {
		ret = PTR_ERR(gpiomtd->ale);
		goto out_ce;
	}

	gpiomtd->cle = devm_gpiod_get(dev, "cle", GPIOD_OUT_LOW);
	if (IS_ERR(gpiomtd->cle)) {
		ret = PTR_ERR(gpiomtd->cle);
		goto out_ce;
	}

	gpiomtd->rdy = devm_gpiod_get_optional(dev, "rdy", GPIOD_IN);
	if (IS_ERR(gpiomtd->rdy)) {
		ret = PTR_ERR(gpiomtd->rdy);
		goto out_ce;
	}
	/* Using RDY pin */
	if (gpiomtd->rdy)
		chip->dev_ready = gpio_nand_devready;

	nand_set_flash_node(chip, pdev->dev.of_node);
	chip->IO_ADDR_W		= chip->IO_ADDR_R;
	chip->ecc.mode		= NAND_ECC_SOFT;
	chip->ecc.algo		= NAND_ECC_HAMMING;
	chip->options		= gpiomtd->plat.options;
	chip->chip_delay	= gpiomtd->plat.chip_delay;
	chip->cmd_ctrl		= gpio_nand_cmd_ctrl;

	mtd			= nand_to_mtd(chip);
	mtd->dev.parent		= dev;

	platform_set_drvdata(pdev, gpiomtd);

	/* Disable write protection, if wired up */
	if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp))
		gpiod_direction_output(gpiomtd->nwp, 1);

	ret = nand_scan(mtd, 1);
	if (ret)
		goto err_wp;

	if (gpiomtd->plat.adjust_parts)
		gpiomtd->plat.adjust_parts(&gpiomtd->plat, mtd->size);

	ret = mtd_device_register(mtd, gpiomtd->plat.parts,
				  gpiomtd->plat.num_parts);
	if (!ret)
		return 0;

err_wp:
	if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp))
		gpiod_set_value(gpiomtd->nwp, 0);
out_ce:
	if (gpiomtd->nce && !IS_ERR(gpiomtd->nce))
		gpiod_set_value(gpiomtd->nce, 0);

	return ret;
}

static struct platform_driver gpio_nand_driver = {
	.probe		= gpio_nand_probe,
	.remove		= gpio_nand_remove,
	.driver		= {
		.name	= "gpio-nand",
		.of_match_table = of_match_ptr(gpio_nand_id_table),
	},
};

module_platform_driver(gpio_nand_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
MODULE_DESCRIPTION("GPIO NAND Driver");
Commit	Line	Data
aaf7ea20 MR	1	/*
	2	* drivers/mtd/nand/gpio.c
	3	*
	4	* Updated, and converted to generic GPIO based driver by Russell King.
	5	*
	6	* Written by Ben Dooks <ben@simtec.co.uk>
	7	* Based on 2.4 version by Mark Whittaker
	8	*
	9	* © 2004 Simtec Electronics
	10	*
c9d79c4b GS	11	* Device driver for NAND flash that uses a memory mapped interface to
	12	* read/write the NAND commands and data, and GPIO pins for control signals
	13	* (the DT binding refers to this as "GPIO assisted NAND flash")
aaf7ea20 MR	14	*
	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*
	19	*/
	20
	21	#include <linux/kernel.h>
283df420	22	#include <linux/err.h>
aaf7ea20 MR	23	#include <linux/slab.h>
	24	#include <linux/module.h>
	25	#include <linux/platform_device.h>
f3d0d8d9	26	#include <linux/gpio/consumer.h>
aaf7ea20 MR	27	#include <linux/io.h>
aaf7ea20 MR	28	#include <linux/mtd/mtd.h>
d4092d76	29	#include <linux/mtd/rawnand.h>
aaf7ea20 MR	30	#include <linux/mtd/partitions.h>
aaf7ea20 MR	31	#include <linux/mtd/nand-gpio.h>
775c3220 JI	32	#include <linux/of.h>
775c3220 JI	33	#include <linux/of_address.h>
aaf7ea20 MR	34
	35	struct gpiomtd {
	36	void __iomem *io_sync;
aaf7ea20 MR	37	struct nand_chip nand_chip;
aaf7ea20 MR	38	struct gpio_nand_platdata plat;
f3d0d8d9 LW	39	struct gpio_desc nce; / Optional chip enable */
	40	struct gpio_desc *cle;
	41	struct gpio_desc *ale;
	42	struct gpio_desc *rdy;
	43	struct gpio_desc nwp; / Optional write protection */
aaf7ea20 MR	44	};
aaf7ea20 MR	45
dc2948ca BB	46	static inline struct gpiomtd gpio_nand_getpriv(struct mtd_info mtd)
	47	{
	48	return container_of(mtd_to_nand(mtd), struct gpiomtd, nand_chip);
	49	}
aaf7ea20 MR	50
	51
	52	#ifdef CONFIG_ARM
	53	/* gpio_nand_dosync()
	54	*
	55	* Make sure the GPIO state changes occur in-order with writes to NAND
	56	* memory region.
	57	* Needed on PXA due to bus-reordering within the SoC itself (see section on
	58	* I/O ordering in PXA manual (section 2.3, p35)
	59	*/
	60	static void gpio_nand_dosync(struct gpiomtd *gpiomtd)
	61	{
	62	unsigned long tmp;
	63
	64	if (gpiomtd->io_sync) {
	65	/*
	66	* Linux memory barriers don't cater for what's required here.
	67	* What's required is what's here - a read from a separate
	68	* region with a dependency on that read.
	69	*/
	70	tmp = readl(gpiomtd->io_sync);
	71	asm volatile("mov %1, %0\n" : "=r" (tmp) : "r" (tmp));
	72	}
	73	}
	74	#else
	75	static inline void gpio_nand_dosync(struct gpiomtd *gpiomtd) {}
	76	#endif
	77
	78	static void gpio_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
	79	{
	80	struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);
	81
	82	gpio_nand_dosync(gpiomtd);
	83
	84	if (ctrl & NAND_CTRL_CHANGE) {
f3d0d8d9 LW	85	if (gpiomtd->nce)
	86	gpiod_set_value(gpiomtd->nce, !(ctrl & NAND_NCE));
	87	gpiod_set_value(gpiomtd->cle, !!(ctrl & NAND_CLE));
	88	gpiod_set_value(gpiomtd->ale, !!(ctrl & NAND_ALE));
aaf7ea20 MR	89	gpio_nand_dosync(gpiomtd);
	90	}
	91	if (cmd == NAND_CMD_NONE)
	92	return;
	93
	94	writeb(cmd, gpiomtd->nand_chip.IO_ADDR_W);
	95	gpio_nand_dosync(gpiomtd);
	96	}
	97
aaf7ea20 MR	98	static int gpio_nand_devready(struct mtd_info *mtd)
	99	{
	100	struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);
18afbc54	101
f3d0d8d9	102	return gpiod_get_value(gpiomtd->rdy);
aaf7ea20 MR	103	}
aaf7ea20 MR	104
775c3220 JI	105	#ifdef CONFIG_OF
	106	static const struct of_device_id gpio_nand_id_table[] = {
	107	{ .compatible = "gpio-control-nand" },
	108	{}
	109	};
	110	MODULE_DEVICE_TABLE(of, gpio_nand_id_table);
	111
	112	static int gpio_nand_get_config_of(const struct device *dev,
	113	struct gpio_nand_platdata *plat)
	114	{
	115	u32 val;
	116
ee4f3666 AS	117	if (!dev->of_node)
	118	return -ENODEV;
	119
775c3220 JI	120	if (!of_property_read_u32(dev->of_node, "bank-width", &val)) {
	121	if (val == 2) {
	122	plat->options \|= NAND_BUSWIDTH_16;
	123	} else if (val != 1) {
	124	dev_err(dev, "invalid bank-width %u\n", val);
	125	return -EINVAL;
	126	}
	127	}
	128
775c3220 JI	129	if (!of_property_read_u32(dev->of_node, "chip-delay", &val))
	130	plat->chip_delay = val;
	131
	132	return 0;
	133	}
	134
	135	static struct resource gpio_nand_get_io_sync_of(struct platform_device pdev)
	136	{
103cdd85	137	struct resource *r;
775c3220 JI	138	u64 addr;
775c3220 JI	139
103cdd85	140	if (of_property_read_u64(pdev->dev.of_node,
775c3220 JI	141	"gpio-control-nand,io-sync-reg", &addr))
	142	return NULL;
	143
103cdd85 BN	144	r = devm_kzalloc(&pdev->dev, sizeof(*r), GFP_KERNEL);
	145	if (!r)
	146	return NULL;
	147
775c3220 JI	148	r->start = addr;
	149	r->end = r->start + 0x3;
	150	r->flags = IORESOURCE_MEM;
	151
	152	return r;
	153	}
	154	#else /* CONFIG_OF */
775c3220 JI	155	static inline int gpio_nand_get_config_of(const struct device *dev,
	156	struct gpio_nand_platdata *plat)
	157	{
	158	return -ENOSYS;
	159	}
	160
	161	static inline struct resource *
	162	gpio_nand_get_io_sync_of(struct platform_device *pdev)
	163	{
	164	return NULL;
	165	}
	166	#endif /* CONFIG_OF */
	167
	168	static inline int gpio_nand_get_config(const struct device *dev,
	169	struct gpio_nand_platdata *plat)
	170	{
	171	int ret = gpio_nand_get_config_of(dev, plat);
	172
	173	if (!ret)
	174	return ret;
	175
453810b7 JH	176	if (dev_get_platdata(dev)) {
453810b7 JH	177	memcpy(plat, dev_get_platdata(dev), sizeof(*plat));
775c3220 JI	178	return 0;
	179	}
	180
	181	return -EINVAL;
	182	}
	183
	184	static inline struct resource *
	185	gpio_nand_get_io_sync(struct platform_device *pdev)
	186	{
	187	struct resource *r = gpio_nand_get_io_sync_of(pdev);
	188
	189	if (r)
	190	return r;
	191
	192	return platform_get_resource(pdev, IORESOURCE_MEM, 1);
	193	}
	194
f8e81c2b	195	static int gpio_nand_remove(struct platform_device *pdev)
aaf7ea20	196	{
f8e81c2b	197	struct gpiomtd *gpiomtd = platform_get_drvdata(pdev);
aaf7ea20	198
dc2948ca	199	nand_release(nand_to_mtd(&gpiomtd->nand_chip));
aaf7ea20	200
f3d0d8d9 LW	201	/* Enable write protection and disable the chip */
	202	if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp))
	203	gpiod_set_value(gpiomtd->nwp, 0);
	204	if (gpiomtd->nce && !IS_ERR(gpiomtd->nce))
	205	gpiod_set_value(gpiomtd->nce, 0);
aaf7ea20	206
aaf7ea20 MR	207	return 0;
	208	}
	209
f8e81c2b	210	static int gpio_nand_probe(struct platform_device *pdev)
aaf7ea20 MR	211	{
aaf7ea20 MR	212	struct gpiomtd *gpiomtd;
f8e81c2b	213	struct nand_chip *chip;
dc2948ca	214	struct mtd_info *mtd;
283df420	215	struct resource *res;
f3d0d8d9	216	struct device *dev = &pdev->dev;
775c3220	217	int ret = 0;
aaf7ea20	218
f3d0d8d9	219	if (!dev->of_node && !dev_get_platdata(dev))
aaf7ea20 MR	220	return -EINVAL;
aaf7ea20 MR	221
f3d0d8d9	222	gpiomtd = devm_kzalloc(dev, sizeof(*gpiomtd), GFP_KERNEL);
24e9971d	223	if (!gpiomtd)
aaf7ea20	224	return -ENOMEM;
aaf7ea20	225
f8e81c2b	226	chip = &gpiomtd->nand_chip;
aaf7ea20	227
f8e81c2b	228	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
f3d0d8d9	229	chip->IO_ADDR_R = devm_ioremap_resource(dev, res);
f8e81c2b AS	230	if (IS_ERR(chip->IO_ADDR_R))
f8e81c2b AS	231	return PTR_ERR(chip->IO_ADDR_R);
283df420	232
f8e81c2b	233	res = gpio_nand_get_io_sync(pdev);
283df420	234	if (res) {
f3d0d8d9	235	gpiomtd->io_sync = devm_ioremap_resource(dev, res);
283df420 AS	236	if (IS_ERR(gpiomtd->io_sync))
283df420 AS	237	return PTR_ERR(gpiomtd->io_sync);
aaf7ea20 MR	238	}
aaf7ea20 MR	239
f3d0d8d9	240	ret = gpio_nand_get_config(dev, &gpiomtd->plat);
775c3220	241	if (ret)
283df420	242	return ret;
aaf7ea20	243
f3d0d8d9 LW	244	/* Just enable the chip */
	245	gpiomtd->nce = devm_gpiod_get_optional(dev, "nce", GPIOD_OUT_HIGH);
	246	if (IS_ERR(gpiomtd->nce))
	247	return PTR_ERR(gpiomtd->nce);
	248
	249	/* We disable write protection once we know probe() will succeed */
	250	gpiomtd->nwp = devm_gpiod_get_optional(dev, "nwp", GPIOD_OUT_LOW);
	251	if (IS_ERR(gpiomtd->nwp)) {
	252	ret = PTR_ERR(gpiomtd->nwp);
	253	goto out_ce;
44dd1828	254	}
283df420	255
bc2fd1b1 CL	256	gpiomtd->ale = devm_gpiod_get(dev, "ale", GPIOD_OUT_LOW);
	257	if (IS_ERR(gpiomtd->ale)) {
	258	ret = PTR_ERR(gpiomtd->ale);
f3d0d8d9	259	goto out_ce;
aaf7ea20	260	}
283df420	261
f3d0d8d9 LW	262	gpiomtd->cle = devm_gpiod_get(dev, "cle", GPIOD_OUT_LOW);
	263	if (IS_ERR(gpiomtd->cle)) {
	264	ret = PTR_ERR(gpiomtd->cle);
	265	goto out_ce;
	266	}
283df420	267
f3d0d8d9 LW	268	gpiomtd->rdy = devm_gpiod_get_optional(dev, "rdy", GPIOD_IN);
	269	if (IS_ERR(gpiomtd->rdy)) {
	270	ret = PTR_ERR(gpiomtd->rdy);
	271	goto out_ce;
18afbc54	272	}
f3d0d8d9 LW	273	/* Using RDY pin */
	274	if (gpiomtd->rdy)
	275	chip->dev_ready = gpio_nand_devready;
aaf7ea20	276
a61ae81a	277	nand_set_flash_node(chip, pdev->dev.of_node);
f8e81c2b AS	278	chip->IO_ADDR_W = chip->IO_ADDR_R;
f8e81c2b AS	279	chip->ecc.mode = NAND_ECC_SOFT;
050658c8	280	chip->ecc.algo = NAND_ECC_HAMMING;
f8e81c2b AS	281	chip->options = gpiomtd->plat.options;
	282	chip->chip_delay = gpiomtd->plat.chip_delay;
	283	chip->cmd_ctrl = gpio_nand_cmd_ctrl;
aaf7ea20	284
dc2948ca	285	mtd = nand_to_mtd(chip);
f3d0d8d9	286	mtd->dev.parent = dev;
aaf7ea20	287
f8e81c2b	288	platform_set_drvdata(pdev, gpiomtd);
283df420	289
f3d0d8d9 LW	290	/* Disable write protection, if wired up */
	291	if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp))
	292	gpiod_direction_output(gpiomtd->nwp, 1);
283df420	293
408bf51e MY	294	ret = nand_scan(mtd, 1);
408bf51e MY	295	if (ret)
aaf7ea20	296	goto err_wp;
aaf7ea20 MR	297
aaf7ea20 MR	298	if (gpiomtd->plat.adjust_parts)
dc2948ca	299	gpiomtd->plat.adjust_parts(&gpiomtd->plat, mtd->size);
aaf7ea20	300
dc2948ca	301	ret = mtd_device_register(mtd, gpiomtd->plat.parts,
a61ae81a	302	gpiomtd->plat.num_parts);
283df420 AS	303	if (!ret)
283df420 AS	304	return 0;
aaf7ea20 MR	305
aaf7ea20 MR	306	err_wp:
f3d0d8d9 LW	307	if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp))
	308	gpiod_set_value(gpiomtd->nwp, 0);
	309	out_ce:
	310	if (gpiomtd->nce && !IS_ERR(gpiomtd->nce))
	311	gpiod_set_value(gpiomtd->nce, 0);
283df420	312
aaf7ea20 MR	313	return ret;
	314	}
	315
	316	static struct platform_driver gpio_nand_driver = {
	317	.probe = gpio_nand_probe,
	318	.remove = gpio_nand_remove,
	319	.driver = {
	320	.name = "gpio-nand",
b57d43ff	321	.of_match_table = of_match_ptr(gpio_nand_id_table),
aaf7ea20 MR	322	},
	323	};
	324
2fe87aef	325	module_platform_driver(gpio_nand_driver);
aaf7ea20 MR	326
	327	MODULE_LICENSE("GPL");
	328	MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
	329	MODULE_DESCRIPTION("GPIO NAND Driver");