[mirror_ubuntu-eoan-kernel.git] / drivers / mtd / nand / gpio.c

/*
 * drivers/mtd/nand/gpio.c
 *
 * Updated, and converted to generic GPIO based driver by Russell King.
 *
 * Written by Ben Dooks <ben@simtec.co.uk>
 *   Based on 2.4 version by Mark Whittaker
 *
 * © 2004 Simtec Electronics
 *
 * Device driver for NAND connected via GPIO
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/nand-gpio.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_gpio.h>

struct gpiomtd {
	void __iomem		*io_sync;
	struct mtd_info		mtd_info;
	struct nand_chip	nand_chip;
	struct gpio_nand_platdata plat;
};

#define gpio_nand_getpriv(x) container_of(x, struct gpiomtd, mtd_info)


#ifdef CONFIG_ARM
/* gpio_nand_dosync()
 *
 * Make sure the GPIO state changes occur in-order with writes to NAND
 * memory region.
 * Needed on PXA due to bus-reordering within the SoC itself (see section on
 * I/O ordering in PXA manual (section 2.3, p35)
 */
static void gpio_nand_dosync(struct gpiomtd *gpiomtd)
{
	unsigned long tmp;

	if (gpiomtd->io_sync) {
		/*
		 * Linux memory barriers don't cater for what's required here.
		 * What's required is what's here - a read from a separate
		 * region with a dependency on that read.
		 */
		tmp = readl(gpiomtd->io_sync);
		asm volatile("mov %1, %0\n" : "=r" (tmp) : "r" (tmp));
	}
}
#else
static inline void gpio_nand_dosync(struct gpiomtd *gpiomtd) {}
#endif

static void gpio_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);

	gpio_nand_dosync(gpiomtd);

	if (ctrl & NAND_CTRL_CHANGE) {
		gpio_set_value(gpiomtd->plat.gpio_nce, !(ctrl & NAND_NCE));
		gpio_set_value(gpiomtd->plat.gpio_cle, !!(ctrl & NAND_CLE));
		gpio_set_value(gpiomtd->plat.gpio_ale, !!(ctrl & NAND_ALE));
		gpio_nand_dosync(gpiomtd);
	}
	if (cmd == NAND_CMD_NONE)
		return;

	writeb(cmd, gpiomtd->nand_chip.IO_ADDR_W);
	gpio_nand_dosync(gpiomtd);
}

static int gpio_nand_devready(struct mtd_info *mtd)
{
	struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);

	return gpio_get_value(gpiomtd->plat.gpio_rdy);
}

#ifdef CONFIG_OF
static const struct of_device_id gpio_nand_id_table[] = {
	{ .compatible = "gpio-control-nand" },
	{}
};
MODULE_DEVICE_TABLE(of, gpio_nand_id_table);

static int gpio_nand_get_config_of(const struct device *dev,
				   struct gpio_nand_platdata *plat)
{
	u32 val;

	if (!dev->of_node)
		return -ENODEV;

	if (!of_property_read_u32(dev->of_node, "bank-width", &val)) {
		if (val == 2) {
			plat->options |= NAND_BUSWIDTH_16;
		} else if (val != 1) {
			dev_err(dev, "invalid bank-width %u\n", val);
			return -EINVAL;
		}
	}

	plat->gpio_rdy = of_get_gpio(dev->of_node, 0);
	plat->gpio_nce = of_get_gpio(dev->of_node, 1);
	plat->gpio_ale = of_get_gpio(dev->of_node, 2);
	plat->gpio_cle = of_get_gpio(dev->of_node, 3);
	plat->gpio_nwp = of_get_gpio(dev->of_node, 4);

	if (!of_property_read_u32(dev->of_node, "chip-delay", &val))
		plat->chip_delay = val;

	return 0;
}

static struct resource *gpio_nand_get_io_sync_of(struct platform_device *pdev)
{
	struct resource *r = devm_kzalloc(&pdev->dev, sizeof(*r), GFP_KERNEL);
	u64 addr;

	if (!r || of_property_read_u64(pdev->dev.of_node,
				       "gpio-control-nand,io-sync-reg", &addr))
		return NULL;

	r->start = addr;
	r->end = r->start + 0x3;
	r->flags = IORESOURCE_MEM;

	return r;
}
#else /* CONFIG_OF */
static inline int gpio_nand_get_config_of(const struct device *dev,
					  struct gpio_nand_platdata *plat)
{
	return -ENOSYS;
}

static inline struct resource *
gpio_nand_get_io_sync_of(struct platform_device *pdev)
{
	return NULL;
}
#endif /* CONFIG_OF */

static inline int gpio_nand_get_config(const struct device *dev,
				       struct gpio_nand_platdata *plat)
{
	int ret = gpio_nand_get_config_of(dev, plat);

	if (!ret)
		return ret;

	if (dev_get_platdata(dev)) {
		memcpy(plat, dev_get_platdata(dev), sizeof(*plat));
		return 0;
	}

	return -EINVAL;
}

static inline struct resource *
gpio_nand_get_io_sync(struct platform_device *pdev)
{
	struct resource *r = gpio_nand_get_io_sync_of(pdev);

	if (r)
		return r;

	return platform_get_resource(pdev, IORESOURCE_MEM, 1);
}

static int gpio_nand_remove(struct platform_device *pdev)
{
	struct gpiomtd *gpiomtd = platform_get_drvdata(pdev);

	nand_release(&gpiomtd->mtd_info);

	if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
		gpio_set_value(gpiomtd->plat.gpio_nwp, 0);
	gpio_set_value(gpiomtd->plat.gpio_nce, 1);

	return 0;
}

static int gpio_nand_probe(struct platform_device *pdev)
{
	struct gpiomtd *gpiomtd;
	struct nand_chip *chip;
	struct resource *res;
	struct mtd_part_parser_data ppdata = {};
	int ret = 0;

	if (!pdev->dev.of_node && !dev_get_platdata(&pdev->dev))
		return -EINVAL;

	gpiomtd = devm_kzalloc(&pdev->dev, sizeof(*gpiomtd), GFP_KERNEL);
	if (!gpiomtd) {
		dev_err(&pdev->dev, "failed to create NAND MTD\n");
		return -ENOMEM;
	}

	chip = &gpiomtd->nand_chip;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(chip->IO_ADDR_R))
		return PTR_ERR(chip->IO_ADDR_R);

	res = gpio_nand_get_io_sync(pdev);
	if (res) {
		gpiomtd->io_sync = devm_ioremap_resource(&pdev->dev, res);
		if (IS_ERR(gpiomtd->io_sync))
			return PTR_ERR(gpiomtd->io_sync);
	}

	ret = gpio_nand_get_config(&pdev->dev, &gpiomtd->plat);
	if (ret)
		return ret;

	ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_nce, "NAND NCE");
	if (ret)
		return ret;
	gpio_direction_output(gpiomtd->plat.gpio_nce, 1);

	if (gpio_is_valid(gpiomtd->plat.gpio_nwp)) {
		ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_nwp,
					"NAND NWP");
		if (ret)
			return ret;
	}

	ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_ale, "NAND ALE");
	if (ret)
		return ret;
	gpio_direction_output(gpiomtd->plat.gpio_ale, 0);

	ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_cle, "NAND CLE");
	if (ret)
		return ret;
	gpio_direction_output(gpiomtd->plat.gpio_cle, 0);

	if (gpio_is_valid(gpiomtd->plat.gpio_rdy)) {
		ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_rdy,
					"NAND RDY");
		if (ret)
			return ret;
		gpio_direction_input(gpiomtd->plat.gpio_rdy);
		chip->dev_ready = gpio_nand_devready;
	}

	chip->IO_ADDR_W		= chip->IO_ADDR_R;
	chip->ecc.mode		= NAND_ECC_SOFT;
	chip->options		= gpiomtd->plat.options;
	chip->chip_delay	= gpiomtd->plat.chip_delay;
	chip->cmd_ctrl		= gpio_nand_cmd_ctrl;

	gpiomtd->mtd_info.priv	= chip;
	gpiomtd->mtd_info.owner	= THIS_MODULE;

	platform_set_drvdata(pdev, gpiomtd);

	if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
		gpio_direction_output(gpiomtd->plat.gpio_nwp, 1);

	if (nand_scan(&gpiomtd->mtd_info, 1)) {
		ret = -ENXIO;
		goto err_wp;
	}

	if (gpiomtd->plat.adjust_parts)
		gpiomtd->plat.adjust_parts(&gpiomtd->plat,
					   gpiomtd->mtd_info.size);

	ppdata.of_node = pdev->dev.of_node;
	ret = mtd_device_parse_register(&gpiomtd->mtd_info, NULL, &ppdata,
					gpiomtd->plat.parts,
					gpiomtd->plat.num_parts);
	if (!ret)
		return 0;

err_wp:
	if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
		gpio_set_value(gpiomtd->plat.gpio_nwp, 0);

	return ret;
}

static struct platform_driver gpio_nand_driver = {
	.probe		= gpio_nand_probe,
	.remove		= gpio_nand_remove,
	.driver		= {
		.name	= "gpio-nand",
		.owner	= THIS_MODULE,
		.of_match_table = of_match_ptr(gpio_nand_id_table),
	},
};

module_platform_driver(gpio_nand_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
MODULE_DESCRIPTION("GPIO NAND Driver");
Commit	Line	Data
aaf7ea20 MR	1	/*
	2	* drivers/mtd/nand/gpio.c
	3	*
	4	* Updated, and converted to generic GPIO based driver by Russell King.
	5	*
	6	* Written by Ben Dooks <ben@simtec.co.uk>
	7	* Based on 2.4 version by Mark Whittaker
	8	*
	9	* © 2004 Simtec Electronics
	10	*
	11	* Device driver for NAND connected via GPIO
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License version 2 as
	15	* published by the Free Software Foundation.
	16	*
	17	*/
	18
	19	#include <linux/kernel.h>
283df420	20	#include <linux/err.h>
aaf7ea20 MR	21	#include <linux/init.h>
	22	#include <linux/slab.h>
	23	#include <linux/module.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/gpio.h>
	26	#include <linux/io.h>
	27	#include <linux/mtd/mtd.h>
	28	#include <linux/mtd/nand.h>
	29	#include <linux/mtd/partitions.h>
	30	#include <linux/mtd/nand-gpio.h>
775c3220 JI	31	#include <linux/of.h>
	32	#include <linux/of_address.h>
	33	#include <linux/of_gpio.h>
aaf7ea20 MR	34
	35	struct gpiomtd {
	36	void __iomem *io_sync;
	37	struct mtd_info mtd_info;
	38	struct nand_chip nand_chip;
	39	struct gpio_nand_platdata plat;
	40	};
	41
	42	#define gpio_nand_getpriv(x) container_of(x, struct gpiomtd, mtd_info)
	43
	44
	45	#ifdef CONFIG_ARM
	46	/* gpio_nand_dosync()
	47	*
	48	* Make sure the GPIO state changes occur in-order with writes to NAND
	49	* memory region.
	50	* Needed on PXA due to bus-reordering within the SoC itself (see section on
	51	* I/O ordering in PXA manual (section 2.3, p35)
	52	*/
	53	static void gpio_nand_dosync(struct gpiomtd *gpiomtd)
	54	{
	55	unsigned long tmp;
	56
	57	if (gpiomtd->io_sync) {
	58	/*
	59	* Linux memory barriers don't cater for what's required here.
	60	* What's required is what's here - a read from a separate
	61	* region with a dependency on that read.
	62	*/
	63	tmp = readl(gpiomtd->io_sync);
	64	asm volatile("mov %1, %0\n" : "=r" (tmp) : "r" (tmp));
	65	}
	66	}
	67	#else
	68	static inline void gpio_nand_dosync(struct gpiomtd *gpiomtd) {}
	69	#endif
	70
	71	static void gpio_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
	72	{
	73	struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);
	74
	75	gpio_nand_dosync(gpiomtd);
	76
	77	if (ctrl & NAND_CTRL_CHANGE) {
	78	gpio_set_value(gpiomtd->plat.gpio_nce, !(ctrl & NAND_NCE));
	79	gpio_set_value(gpiomtd->plat.gpio_cle, !!(ctrl & NAND_CLE));
	80	gpio_set_value(gpiomtd->plat.gpio_ale, !!(ctrl & NAND_ALE));
	81	gpio_nand_dosync(gpiomtd);
	82	}
	83	if (cmd == NAND_CMD_NONE)
	84	return;
	85
	86	writeb(cmd, gpiomtd->nand_chip.IO_ADDR_W);
	87	gpio_nand_dosync(gpiomtd);
	88	}
	89
aaf7ea20 MR	90	static int gpio_nand_devready(struct mtd_info *mtd)
	91	{
	92	struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);
18afbc54	93
c85d32d5	94	return gpio_get_value(gpiomtd->plat.gpio_rdy);
aaf7ea20 MR	95	}
aaf7ea20 MR	96
775c3220 JI	97	#ifdef CONFIG_OF
	98	static const struct of_device_id gpio_nand_id_table[] = {
	99	{ .compatible = "gpio-control-nand" },
	100	{}
	101	};
	102	MODULE_DEVICE_TABLE(of, gpio_nand_id_table);
	103
	104	static int gpio_nand_get_config_of(const struct device *dev,
	105	struct gpio_nand_platdata *plat)
	106	{
	107	u32 val;
	108
ee4f3666 AS	109	if (!dev->of_node)
	110	return -ENODEV;
	111
775c3220 JI	112	if (!of_property_read_u32(dev->of_node, "bank-width", &val)) {
	113	if (val == 2) {
	114	plat->options \|= NAND_BUSWIDTH_16;
	115	} else if (val != 1) {
	116	dev_err(dev, "invalid bank-width %u\n", val);
	117	return -EINVAL;
	118	}
	119	}
	120
	121	plat->gpio_rdy = of_get_gpio(dev->of_node, 0);
	122	plat->gpio_nce = of_get_gpio(dev->of_node, 1);
	123	plat->gpio_ale = of_get_gpio(dev->of_node, 2);
	124	plat->gpio_cle = of_get_gpio(dev->of_node, 3);
	125	plat->gpio_nwp = of_get_gpio(dev->of_node, 4);
	126
	127	if (!of_property_read_u32(dev->of_node, "chip-delay", &val))
	128	plat->chip_delay = val;
	129
	130	return 0;
	131	}
	132
	133	static struct resource gpio_nand_get_io_sync_of(struct platform_device pdev)
	134	{
	135	struct resource r = devm_kzalloc(&pdev->dev, sizeof(r), GFP_KERNEL);
	136	u64 addr;
	137
	138	if (!r \|\| of_property_read_u64(pdev->dev.of_node,
	139	"gpio-control-nand,io-sync-reg", &addr))
	140	return NULL;
	141
	142	r->start = addr;
	143	r->end = r->start + 0x3;
	144	r->flags = IORESOURCE_MEM;
	145
	146	return r;
	147	}
	148	#else /* CONFIG_OF */
775c3220 JI	149	static inline int gpio_nand_get_config_of(const struct device *dev,
	150	struct gpio_nand_platdata *plat)
	151	{
	152	return -ENOSYS;
	153	}
	154
	155	static inline struct resource *
	156	gpio_nand_get_io_sync_of(struct platform_device *pdev)
	157	{
	158	return NULL;
	159	}
	160	#endif /* CONFIG_OF */
	161
	162	static inline int gpio_nand_get_config(const struct device *dev,
	163	struct gpio_nand_platdata *plat)
	164	{
	165	int ret = gpio_nand_get_config_of(dev, plat);
	166
	167	if (!ret)
	168	return ret;
	169
453810b7 JH	170	if (dev_get_platdata(dev)) {
453810b7 JH	171	memcpy(plat, dev_get_platdata(dev), sizeof(*plat));
775c3220 JI	172	return 0;
	173	}
	174
	175	return -EINVAL;
	176	}
	177
	178	static inline struct resource *
	179	gpio_nand_get_io_sync(struct platform_device *pdev)
	180	{
	181	struct resource *r = gpio_nand_get_io_sync_of(pdev);
	182
	183	if (r)
	184	return r;
	185
	186	return platform_get_resource(pdev, IORESOURCE_MEM, 1);
	187	}
	188
f8e81c2b	189	static int gpio_nand_remove(struct platform_device *pdev)
aaf7ea20	190	{
f8e81c2b	191	struct gpiomtd *gpiomtd = platform_get_drvdata(pdev);
aaf7ea20 MR	192
	193	nand_release(&gpiomtd->mtd_info);
	194
aaf7ea20 MR	195	if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
	196	gpio_set_value(gpiomtd->plat.gpio_nwp, 0);
	197	gpio_set_value(gpiomtd->plat.gpio_nce, 1);
	198
aaf7ea20 MR	199	return 0;
	200	}
	201
f8e81c2b	202	static int gpio_nand_probe(struct platform_device *pdev)
aaf7ea20 MR	203	{
aaf7ea20 MR	204	struct gpiomtd *gpiomtd;
f8e81c2b	205	struct nand_chip *chip;
283df420	206	struct resource *res;
775c3220 JI	207	struct mtd_part_parser_data ppdata = {};
775c3220 JI	208	int ret = 0;
aaf7ea20	209
453810b7	210	if (!pdev->dev.of_node && !dev_get_platdata(&pdev->dev))
aaf7ea20 MR	211	return -EINVAL;
aaf7ea20 MR	212
f8e81c2b	213	gpiomtd = devm_kzalloc(&pdev->dev, sizeof(*gpiomtd), GFP_KERNEL);
283df420	214	if (!gpiomtd) {
f8e81c2b	215	dev_err(&pdev->dev, "failed to create NAND MTD\n");
aaf7ea20 MR	216	return -ENOMEM;
	217	}
	218
f8e81c2b	219	chip = &gpiomtd->nand_chip;
aaf7ea20	220
f8e81c2b AS	221	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	222	chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
	223	if (IS_ERR(chip->IO_ADDR_R))
	224	return PTR_ERR(chip->IO_ADDR_R);
283df420	225
f8e81c2b	226	res = gpio_nand_get_io_sync(pdev);
283df420	227	if (res) {
f8e81c2b	228	gpiomtd->io_sync = devm_ioremap_resource(&pdev->dev, res);
283df420 AS	229	if (IS_ERR(gpiomtd->io_sync))
283df420 AS	230	return PTR_ERR(gpiomtd->io_sync);
aaf7ea20 MR	231	}
aaf7ea20 MR	232
f8e81c2b	233	ret = gpio_nand_get_config(&pdev->dev, &gpiomtd->plat);
775c3220	234	if (ret)
283df420	235	return ret;
aaf7ea20	236
f8e81c2b	237	ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_nce, "NAND NCE");
aaf7ea20	238	if (ret)
283df420	239	return ret;
aaf7ea20	240	gpio_direction_output(gpiomtd->plat.gpio_nce, 1);
283df420	241
aaf7ea20	242	if (gpio_is_valid(gpiomtd->plat.gpio_nwp)) {
f8e81c2b	243	ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_nwp,
283df420	244	"NAND NWP");
aaf7ea20	245	if (ret)
283df420	246	return ret;
aaf7ea20	247	}
283df420	248
f8e81c2b	249	ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_ale, "NAND ALE");
aaf7ea20	250	if (ret)
283df420	251	return ret;
aaf7ea20	252	gpio_direction_output(gpiomtd->plat.gpio_ale, 0);
283df420	253
f8e81c2b	254	ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_cle, "NAND CLE");
aaf7ea20	255	if (ret)
283df420	256	return ret;
aaf7ea20	257	gpio_direction_output(gpiomtd->plat.gpio_cle, 0);
283df420	258
18afbc54	259	if (gpio_is_valid(gpiomtd->plat.gpio_rdy)) {
f8e81c2b	260	ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_rdy,
283df420	261	"NAND RDY");
18afbc54	262	if (ret)
283df420	263	return ret;
18afbc54	264	gpio_direction_input(gpiomtd->plat.gpio_rdy);
f8e81c2b	265	chip->dev_ready = gpio_nand_devready;
18afbc54	266	}
aaf7ea20	267
f8e81c2b AS	268	chip->IO_ADDR_W = chip->IO_ADDR_R;
	269	chip->ecc.mode = NAND_ECC_SOFT;
	270	chip->options = gpiomtd->plat.options;
	271	chip->chip_delay = gpiomtd->plat.chip_delay;
	272	chip->cmd_ctrl = gpio_nand_cmd_ctrl;
aaf7ea20	273
f8e81c2b AS	274	gpiomtd->mtd_info.priv = chip;
f8e81c2b AS	275	gpiomtd->mtd_info.owner = THIS_MODULE;
aaf7ea20	276
f8e81c2b	277	platform_set_drvdata(pdev, gpiomtd);
283df420 AS	278
	279	if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
	280	gpio_direction_output(gpiomtd->plat.gpio_nwp, 1);
	281
aaf7ea20	282	if (nand_scan(&gpiomtd->mtd_info, 1)) {
aaf7ea20 MR	283	ret = -ENXIO;
	284	goto err_wp;
	285	}
	286
	287	if (gpiomtd->plat.adjust_parts)
	288	gpiomtd->plat.adjust_parts(&gpiomtd->plat,
	289	gpiomtd->mtd_info.size);
	290
f8e81c2b	291	ppdata.of_node = pdev->dev.of_node;
775c3220 JI	292	ret = mtd_device_parse_register(&gpiomtd->mtd_info, NULL, &ppdata,
	293	gpiomtd->plat.parts,
	294	gpiomtd->plat.num_parts);
283df420 AS	295	if (!ret)
283df420 AS	296	return 0;
aaf7ea20 MR	297
	298	err_wp:
	299	if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
	300	gpio_set_value(gpiomtd->plat.gpio_nwp, 0);
283df420	301
aaf7ea20 MR	302	return ret;
	303	}
	304
	305	static struct platform_driver gpio_nand_driver = {
	306	.probe = gpio_nand_probe,
	307	.remove = gpio_nand_remove,
	308	.driver = {
	309	.name = "gpio-nand",
65c972af	310	.owner = THIS_MODULE,
b57d43ff	311	.of_match_table = of_match_ptr(gpio_nand_id_table),
aaf7ea20 MR	312	},
	313	};
	314
2fe87aef	315	module_platform_driver(gpio_nand_driver);
aaf7ea20 MR	316
	317	MODULE_LICENSE("GPL");
	318	MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
	319	MODULE_DESCRIPTION("GPIO NAND Driver");