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54f531f6 ZW |
1 | /* |
2 | * Hisilicon NAND Flash controller driver | |
3 | * | |
4 | * Copyright © 2012-2014 HiSilicon Technologies Co., Ltd. | |
5 | * http://www.hisilicon.com | |
6 | * | |
7 | * Author: Zhou Wang <wangzhou.bry@gmail.com> | |
8 | * The initial developer of the original code is Zhiyong Cai | |
9 | * <caizhiyong@huawei.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | */ | |
21 | #include <linux/of.h> | |
22 | #include <linux/of_mtd.h> | |
23 | #include <linux/mtd/mtd.h> | |
24 | #include <linux/sizes.h> | |
25 | #include <linux/clk.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/mtd/nand.h> | |
31 | #include <linux/dma-mapping.h> | |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/mtd/partitions.h> | |
34 | ||
35 | #define HINFC504_MAX_CHIP (4) | |
36 | #define HINFC504_W_LATCH (5) | |
37 | #define HINFC504_R_LATCH (7) | |
38 | #define HINFC504_RW_LATCH (3) | |
39 | ||
40 | #define HINFC504_NFC_TIMEOUT (2 * HZ) | |
41 | #define HINFC504_NFC_PM_TIMEOUT (1 * HZ) | |
42 | #define HINFC504_NFC_DMA_TIMEOUT (5 * HZ) | |
43 | #define HINFC504_CHIP_DELAY (25) | |
44 | ||
45 | #define HINFC504_REG_BASE_ADDRESS_LEN (0x100) | |
46 | #define HINFC504_BUFFER_BASE_ADDRESS_LEN (2048 + 128) | |
47 | ||
48 | #define HINFC504_ADDR_CYCLE_MASK 0x4 | |
49 | ||
50 | #define HINFC504_CON 0x00 | |
51 | #define HINFC504_CON_OP_MODE_NORMAL BIT(0) | |
52 | #define HINFC504_CON_PAGEISZE_SHIFT (1) | |
53 | #define HINFC504_CON_PAGESIZE_MASK (0x07) | |
54 | #define HINFC504_CON_BUS_WIDTH BIT(4) | |
55 | #define HINFC504_CON_READY_BUSY_SEL BIT(8) | |
56 | #define HINFC504_CON_ECCTYPE_SHIFT (9) | |
57 | #define HINFC504_CON_ECCTYPE_MASK (0x07) | |
58 | ||
59 | #define HINFC504_PWIDTH 0x04 | |
60 | #define SET_HINFC504_PWIDTH(_w_lcnt, _r_lcnt, _rw_hcnt) \ | |
61 | ((_w_lcnt) | (((_r_lcnt) & 0x0F) << 4) | (((_rw_hcnt) & 0x0F) << 8)) | |
62 | ||
63 | #define HINFC504_CMD 0x0C | |
64 | #define HINFC504_ADDRL 0x10 | |
65 | #define HINFC504_ADDRH 0x14 | |
66 | #define HINFC504_DATA_NUM 0x18 | |
67 | ||
68 | #define HINFC504_OP 0x1C | |
69 | #define HINFC504_OP_READ_DATA_EN BIT(1) | |
70 | #define HINFC504_OP_WAIT_READY_EN BIT(2) | |
71 | #define HINFC504_OP_CMD2_EN BIT(3) | |
72 | #define HINFC504_OP_WRITE_DATA_EN BIT(4) | |
73 | #define HINFC504_OP_ADDR_EN BIT(5) | |
74 | #define HINFC504_OP_CMD1_EN BIT(6) | |
75 | #define HINFC504_OP_NF_CS_SHIFT (7) | |
76 | #define HINFC504_OP_NF_CS_MASK (3) | |
77 | #define HINFC504_OP_ADDR_CYCLE_SHIFT (9) | |
78 | #define HINFC504_OP_ADDR_CYCLE_MASK (7) | |
79 | ||
80 | #define HINFC504_STATUS 0x20 | |
81 | #define HINFC504_READY BIT(0) | |
82 | ||
83 | #define HINFC504_INTEN 0x24 | |
84 | #define HINFC504_INTEN_DMA BIT(9) | |
85 | #define HINFC504_INTEN_UE BIT(6) | |
86 | #define HINFC504_INTEN_CE BIT(5) | |
87 | ||
88 | #define HINFC504_INTS 0x28 | |
89 | #define HINFC504_INTS_DMA BIT(9) | |
90 | #define HINFC504_INTS_UE BIT(6) | |
91 | #define HINFC504_INTS_CE BIT(5) | |
92 | ||
93 | #define HINFC504_INTCLR 0x2C | |
94 | #define HINFC504_INTCLR_DMA BIT(9) | |
95 | #define HINFC504_INTCLR_UE BIT(6) | |
96 | #define HINFC504_INTCLR_CE BIT(5) | |
97 | ||
98 | #define HINFC504_ECC_STATUS 0x5C | |
99 | #define HINFC504_ECC_16_BIT_SHIFT 12 | |
100 | ||
101 | #define HINFC504_DMA_CTRL 0x60 | |
102 | #define HINFC504_DMA_CTRL_DMA_START BIT(0) | |
103 | #define HINFC504_DMA_CTRL_WE BIT(1) | |
104 | #define HINFC504_DMA_CTRL_DATA_AREA_EN BIT(2) | |
105 | #define HINFC504_DMA_CTRL_OOB_AREA_EN BIT(3) | |
106 | #define HINFC504_DMA_CTRL_BURST4_EN BIT(4) | |
107 | #define HINFC504_DMA_CTRL_BURST8_EN BIT(5) | |
108 | #define HINFC504_DMA_CTRL_BURST16_EN BIT(6) | |
109 | #define HINFC504_DMA_CTRL_ADDR_NUM_SHIFT (7) | |
110 | #define HINFC504_DMA_CTRL_ADDR_NUM_MASK (1) | |
111 | #define HINFC504_DMA_CTRL_CS_SHIFT (8) | |
112 | #define HINFC504_DMA_CTRL_CS_MASK (0x03) | |
113 | ||
114 | #define HINFC504_DMA_ADDR_DATA 0x64 | |
115 | #define HINFC504_DMA_ADDR_OOB 0x68 | |
116 | ||
117 | #define HINFC504_DMA_LEN 0x6C | |
118 | #define HINFC504_DMA_LEN_OOB_SHIFT (16) | |
119 | #define HINFC504_DMA_LEN_OOB_MASK (0xFFF) | |
120 | ||
121 | #define HINFC504_DMA_PARA 0x70 | |
122 | #define HINFC504_DMA_PARA_DATA_RW_EN BIT(0) | |
123 | #define HINFC504_DMA_PARA_OOB_RW_EN BIT(1) | |
124 | #define HINFC504_DMA_PARA_DATA_EDC_EN BIT(2) | |
125 | #define HINFC504_DMA_PARA_OOB_EDC_EN BIT(3) | |
126 | #define HINFC504_DMA_PARA_DATA_ECC_EN BIT(4) | |
127 | #define HINFC504_DMA_PARA_OOB_ECC_EN BIT(5) | |
128 | ||
129 | #define HINFC_VERSION 0x74 | |
130 | #define HINFC504_LOG_READ_ADDR 0x7C | |
131 | #define HINFC504_LOG_READ_LEN 0x80 | |
132 | ||
133 | #define HINFC504_NANDINFO_LEN 0x10 | |
134 | ||
135 | struct hinfc_host { | |
136 | struct nand_chip chip; | |
54f531f6 ZW |
137 | struct device *dev; |
138 | void __iomem *iobase; | |
139 | void __iomem *mmio; | |
140 | struct completion cmd_complete; | |
141 | unsigned int offset; | |
142 | unsigned int command; | |
143 | int chipselect; | |
144 | unsigned int addr_cycle; | |
145 | u32 addr_value[2]; | |
146 | u32 cache_addr_value[2]; | |
147 | char *buffer; | |
148 | dma_addr_t dma_buffer; | |
149 | dma_addr_t dma_oob; | |
150 | int version; | |
151 | unsigned int irq_status; /* interrupt status */ | |
152 | }; | |
153 | ||
154 | static inline unsigned int hinfc_read(struct hinfc_host *host, unsigned int reg) | |
155 | { | |
156 | return readl(host->iobase + reg); | |
157 | } | |
158 | ||
159 | static inline void hinfc_write(struct hinfc_host *host, unsigned int value, | |
160 | unsigned int reg) | |
161 | { | |
162 | writel(value, host->iobase + reg); | |
163 | } | |
164 | ||
165 | static void wait_controller_finished(struct hinfc_host *host) | |
166 | { | |
167 | unsigned long timeout = jiffies + HINFC504_NFC_TIMEOUT; | |
168 | int val; | |
169 | ||
170 | while (time_before(jiffies, timeout)) { | |
171 | val = hinfc_read(host, HINFC504_STATUS); | |
172 | if (host->command == NAND_CMD_ERASE2) { | |
173 | /* nfc is ready */ | |
174 | while (!(val & HINFC504_READY)) { | |
175 | usleep_range(500, 1000); | |
176 | val = hinfc_read(host, HINFC504_STATUS); | |
177 | } | |
178 | return; | |
179 | } | |
180 | ||
181 | if (val & HINFC504_READY) | |
182 | return; | |
183 | } | |
184 | ||
185 | /* wait cmd timeout */ | |
186 | dev_err(host->dev, "Wait NAND controller exec cmd timeout.\n"); | |
187 | } | |
188 | ||
189 | static void hisi_nfc_dma_transfer(struct hinfc_host *host, int todev) | |
190 | { | |
fa100163 BB |
191 | struct nand_chip *chip = &host->chip; |
192 | struct mtd_info *mtd = nand_to_mtd(chip); | |
54f531f6 ZW |
193 | unsigned long val; |
194 | int ret; | |
195 | ||
196 | hinfc_write(host, host->dma_buffer, HINFC504_DMA_ADDR_DATA); | |
197 | hinfc_write(host, host->dma_oob, HINFC504_DMA_ADDR_OOB); | |
198 | ||
199 | if (chip->ecc.mode == NAND_ECC_NONE) { | |
200 | hinfc_write(host, ((mtd->oobsize & HINFC504_DMA_LEN_OOB_MASK) | |
201 | << HINFC504_DMA_LEN_OOB_SHIFT), HINFC504_DMA_LEN); | |
202 | ||
203 | hinfc_write(host, HINFC504_DMA_PARA_DATA_RW_EN | |
204 | | HINFC504_DMA_PARA_OOB_RW_EN, HINFC504_DMA_PARA); | |
205 | } else { | |
206 | if (host->command == NAND_CMD_READOOB) | |
207 | hinfc_write(host, HINFC504_DMA_PARA_OOB_RW_EN | |
208 | | HINFC504_DMA_PARA_OOB_EDC_EN | |
209 | | HINFC504_DMA_PARA_OOB_ECC_EN, HINFC504_DMA_PARA); | |
210 | else | |
211 | hinfc_write(host, HINFC504_DMA_PARA_DATA_RW_EN | |
212 | | HINFC504_DMA_PARA_OOB_RW_EN | |
213 | | HINFC504_DMA_PARA_DATA_EDC_EN | |
214 | | HINFC504_DMA_PARA_OOB_EDC_EN | |
215 | | HINFC504_DMA_PARA_DATA_ECC_EN | |
216 | | HINFC504_DMA_PARA_OOB_ECC_EN, HINFC504_DMA_PARA); | |
217 | ||
218 | } | |
219 | ||
220 | val = (HINFC504_DMA_CTRL_DMA_START | HINFC504_DMA_CTRL_BURST4_EN | |
221 | | HINFC504_DMA_CTRL_BURST8_EN | HINFC504_DMA_CTRL_BURST16_EN | |
222 | | HINFC504_DMA_CTRL_DATA_AREA_EN | HINFC504_DMA_CTRL_OOB_AREA_EN | |
223 | | ((host->addr_cycle == 4 ? 1 : 0) | |
224 | << HINFC504_DMA_CTRL_ADDR_NUM_SHIFT) | |
225 | | ((host->chipselect & HINFC504_DMA_CTRL_CS_MASK) | |
226 | << HINFC504_DMA_CTRL_CS_SHIFT)); | |
227 | ||
228 | if (todev) | |
229 | val |= HINFC504_DMA_CTRL_WE; | |
230 | ||
231 | init_completion(&host->cmd_complete); | |
232 | ||
233 | hinfc_write(host, val, HINFC504_DMA_CTRL); | |
234 | ret = wait_for_completion_timeout(&host->cmd_complete, | |
235 | HINFC504_NFC_DMA_TIMEOUT); | |
236 | ||
237 | if (!ret) { | |
238 | dev_err(host->dev, "DMA operation(irq) timeout!\n"); | |
239 | /* sanity check */ | |
240 | val = hinfc_read(host, HINFC504_DMA_CTRL); | |
241 | if (!(val & HINFC504_DMA_CTRL_DMA_START)) | |
242 | dev_err(host->dev, "DMA is already done but without irq ACK!\n"); | |
243 | else | |
244 | dev_err(host->dev, "DMA is really timeout!\n"); | |
245 | } | |
246 | } | |
247 | ||
248 | static int hisi_nfc_send_cmd_pageprog(struct hinfc_host *host) | |
249 | { | |
250 | host->addr_value[0] &= 0xffff0000; | |
251 | ||
252 | hinfc_write(host, host->addr_value[0], HINFC504_ADDRL); | |
253 | hinfc_write(host, host->addr_value[1], HINFC504_ADDRH); | |
254 | hinfc_write(host, NAND_CMD_PAGEPROG << 8 | NAND_CMD_SEQIN, | |
255 | HINFC504_CMD); | |
256 | ||
257 | hisi_nfc_dma_transfer(host, 1); | |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
262 | static int hisi_nfc_send_cmd_readstart(struct hinfc_host *host) | |
263 | { | |
fa100163 | 264 | struct mtd_info *mtd = nand_to_mtd(&host->chip); |
54f531f6 ZW |
265 | |
266 | if ((host->addr_value[0] == host->cache_addr_value[0]) && | |
267 | (host->addr_value[1] == host->cache_addr_value[1])) | |
268 | return 0; | |
269 | ||
270 | host->addr_value[0] &= 0xffff0000; | |
271 | ||
272 | hinfc_write(host, host->addr_value[0], HINFC504_ADDRL); | |
273 | hinfc_write(host, host->addr_value[1], HINFC504_ADDRH); | |
274 | hinfc_write(host, NAND_CMD_READSTART << 8 | NAND_CMD_READ0, | |
275 | HINFC504_CMD); | |
276 | ||
277 | hinfc_write(host, 0, HINFC504_LOG_READ_ADDR); | |
278 | hinfc_write(host, mtd->writesize + mtd->oobsize, | |
279 | HINFC504_LOG_READ_LEN); | |
280 | ||
281 | hisi_nfc_dma_transfer(host, 0); | |
282 | ||
283 | host->cache_addr_value[0] = host->addr_value[0]; | |
284 | host->cache_addr_value[1] = host->addr_value[1]; | |
285 | ||
286 | return 0; | |
287 | } | |
288 | ||
289 | static int hisi_nfc_send_cmd_erase(struct hinfc_host *host) | |
290 | { | |
291 | hinfc_write(host, host->addr_value[0], HINFC504_ADDRL); | |
292 | hinfc_write(host, (NAND_CMD_ERASE2 << 8) | NAND_CMD_ERASE1, | |
293 | HINFC504_CMD); | |
294 | ||
295 | hinfc_write(host, HINFC504_OP_WAIT_READY_EN | |
296 | | HINFC504_OP_CMD2_EN | |
297 | | HINFC504_OP_CMD1_EN | |
298 | | HINFC504_OP_ADDR_EN | |
299 | | ((host->chipselect & HINFC504_OP_NF_CS_MASK) | |
300 | << HINFC504_OP_NF_CS_SHIFT) | |
301 | | ((host->addr_cycle & HINFC504_OP_ADDR_CYCLE_MASK) | |
302 | << HINFC504_OP_ADDR_CYCLE_SHIFT), | |
303 | HINFC504_OP); | |
304 | ||
305 | wait_controller_finished(host); | |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
310 | static int hisi_nfc_send_cmd_readid(struct hinfc_host *host) | |
311 | { | |
312 | hinfc_write(host, HINFC504_NANDINFO_LEN, HINFC504_DATA_NUM); | |
313 | hinfc_write(host, NAND_CMD_READID, HINFC504_CMD); | |
314 | hinfc_write(host, 0, HINFC504_ADDRL); | |
315 | ||
316 | hinfc_write(host, HINFC504_OP_CMD1_EN | HINFC504_OP_ADDR_EN | |
317 | | HINFC504_OP_READ_DATA_EN | |
318 | | ((host->chipselect & HINFC504_OP_NF_CS_MASK) | |
319 | << HINFC504_OP_NF_CS_SHIFT) | |
320 | | 1 << HINFC504_OP_ADDR_CYCLE_SHIFT, HINFC504_OP); | |
321 | ||
322 | wait_controller_finished(host); | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
327 | static int hisi_nfc_send_cmd_status(struct hinfc_host *host) | |
328 | { | |
329 | hinfc_write(host, HINFC504_NANDINFO_LEN, HINFC504_DATA_NUM); | |
330 | hinfc_write(host, NAND_CMD_STATUS, HINFC504_CMD); | |
331 | hinfc_write(host, HINFC504_OP_CMD1_EN | |
332 | | HINFC504_OP_READ_DATA_EN | |
333 | | ((host->chipselect & HINFC504_OP_NF_CS_MASK) | |
334 | << HINFC504_OP_NF_CS_SHIFT), | |
335 | HINFC504_OP); | |
336 | ||
337 | wait_controller_finished(host); | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
342 | static int hisi_nfc_send_cmd_reset(struct hinfc_host *host, int chipselect) | |
343 | { | |
344 | hinfc_write(host, NAND_CMD_RESET, HINFC504_CMD); | |
345 | ||
346 | hinfc_write(host, HINFC504_OP_CMD1_EN | |
347 | | ((chipselect & HINFC504_OP_NF_CS_MASK) | |
348 | << HINFC504_OP_NF_CS_SHIFT) | |
349 | | HINFC504_OP_WAIT_READY_EN, | |
350 | HINFC504_OP); | |
351 | ||
352 | wait_controller_finished(host); | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
357 | static void hisi_nfc_select_chip(struct mtd_info *mtd, int chipselect) | |
358 | { | |
4bd4ebcc | 359 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 360 | struct hinfc_host *host = nand_get_controller_data(chip); |
54f531f6 ZW |
361 | |
362 | if (chipselect < 0) | |
363 | return; | |
364 | ||
365 | host->chipselect = chipselect; | |
366 | } | |
367 | ||
368 | static uint8_t hisi_nfc_read_byte(struct mtd_info *mtd) | |
369 | { | |
4bd4ebcc | 370 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 371 | struct hinfc_host *host = nand_get_controller_data(chip); |
54f531f6 ZW |
372 | |
373 | if (host->command == NAND_CMD_STATUS) | |
374 | return *(uint8_t *)(host->mmio); | |
375 | ||
376 | host->offset++; | |
377 | ||
378 | if (host->command == NAND_CMD_READID) | |
379 | return *(uint8_t *)(host->mmio + host->offset - 1); | |
380 | ||
381 | return *(uint8_t *)(host->buffer + host->offset - 1); | |
382 | } | |
383 | ||
384 | static u16 hisi_nfc_read_word(struct mtd_info *mtd) | |
385 | { | |
4bd4ebcc | 386 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 387 | struct hinfc_host *host = nand_get_controller_data(chip); |
54f531f6 ZW |
388 | |
389 | host->offset += 2; | |
390 | return *(u16 *)(host->buffer + host->offset - 2); | |
391 | } | |
392 | ||
393 | static void | |
394 | hisi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
395 | { | |
4bd4ebcc | 396 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 397 | struct hinfc_host *host = nand_get_controller_data(chip); |
54f531f6 ZW |
398 | |
399 | memcpy(host->buffer + host->offset, buf, len); | |
400 | host->offset += len; | |
401 | } | |
402 | ||
403 | static void hisi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
404 | { | |
4bd4ebcc | 405 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 406 | struct hinfc_host *host = nand_get_controller_data(chip); |
54f531f6 ZW |
407 | |
408 | memcpy(buf, host->buffer + host->offset, len); | |
409 | host->offset += len; | |
410 | } | |
411 | ||
412 | static void set_addr(struct mtd_info *mtd, int column, int page_addr) | |
413 | { | |
4bd4ebcc | 414 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 415 | struct hinfc_host *host = nand_get_controller_data(chip); |
54f531f6 ZW |
416 | unsigned int command = host->command; |
417 | ||
418 | host->addr_cycle = 0; | |
419 | host->addr_value[0] = 0; | |
420 | host->addr_value[1] = 0; | |
421 | ||
422 | /* Serially input address */ | |
423 | if (column != -1) { | |
424 | /* Adjust columns for 16 bit buswidth */ | |
425 | if (chip->options & NAND_BUSWIDTH_16 && | |
426 | !nand_opcode_8bits(command)) | |
427 | column >>= 1; | |
428 | ||
429 | host->addr_value[0] = column & 0xffff; | |
430 | host->addr_cycle = 2; | |
431 | } | |
432 | if (page_addr != -1) { | |
433 | host->addr_value[0] |= (page_addr & 0xffff) | |
434 | << (host->addr_cycle * 8); | |
435 | host->addr_cycle += 2; | |
436 | /* One more address cycle for devices > 128MiB */ | |
437 | if (chip->chipsize > (128 << 20)) { | |
438 | host->addr_cycle += 1; | |
439 | if (host->command == NAND_CMD_ERASE1) | |
440 | host->addr_value[0] |= ((page_addr >> 16) & 0xff) << 16; | |
441 | else | |
442 | host->addr_value[1] |= ((page_addr >> 16) & 0xff); | |
443 | } | |
444 | } | |
445 | } | |
446 | ||
447 | static void hisi_nfc_cmdfunc(struct mtd_info *mtd, unsigned command, int column, | |
448 | int page_addr) | |
449 | { | |
4bd4ebcc | 450 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 451 | struct hinfc_host *host = nand_get_controller_data(chip); |
54f531f6 ZW |
452 | int is_cache_invalid = 1; |
453 | unsigned int flag = 0; | |
454 | ||
455 | host->command = command; | |
456 | ||
457 | switch (command) { | |
458 | case NAND_CMD_READ0: | |
459 | case NAND_CMD_READOOB: | |
460 | if (command == NAND_CMD_READ0) | |
461 | host->offset = column; | |
462 | else | |
463 | host->offset = column + mtd->writesize; | |
464 | ||
465 | is_cache_invalid = 0; | |
466 | set_addr(mtd, column, page_addr); | |
467 | hisi_nfc_send_cmd_readstart(host); | |
468 | break; | |
469 | ||
470 | case NAND_CMD_SEQIN: | |
471 | host->offset = column; | |
472 | set_addr(mtd, column, page_addr); | |
473 | break; | |
474 | ||
475 | case NAND_CMD_ERASE1: | |
476 | set_addr(mtd, column, page_addr); | |
477 | break; | |
478 | ||
479 | case NAND_CMD_PAGEPROG: | |
480 | hisi_nfc_send_cmd_pageprog(host); | |
481 | break; | |
482 | ||
483 | case NAND_CMD_ERASE2: | |
484 | hisi_nfc_send_cmd_erase(host); | |
485 | break; | |
486 | ||
487 | case NAND_CMD_READID: | |
488 | host->offset = column; | |
489 | memset(host->mmio, 0, 0x10); | |
490 | hisi_nfc_send_cmd_readid(host); | |
491 | break; | |
492 | ||
493 | case NAND_CMD_STATUS: | |
494 | flag = hinfc_read(host, HINFC504_CON); | |
495 | if (chip->ecc.mode == NAND_ECC_HW) | |
496 | hinfc_write(host, | |
dd58d38f | 497 | flag & ~(HINFC504_CON_ECCTYPE_MASK << |
54f531f6 ZW |
498 | HINFC504_CON_ECCTYPE_SHIFT), HINFC504_CON); |
499 | ||
500 | host->offset = 0; | |
501 | memset(host->mmio, 0, 0x10); | |
502 | hisi_nfc_send_cmd_status(host); | |
503 | hinfc_write(host, flag, HINFC504_CON); | |
504 | break; | |
505 | ||
506 | case NAND_CMD_RESET: | |
507 | hisi_nfc_send_cmd_reset(host, host->chipselect); | |
508 | break; | |
509 | ||
510 | default: | |
511 | dev_err(host->dev, "Error: unsupported cmd(cmd=%x, col=%x, page=%x)\n", | |
512 | command, column, page_addr); | |
513 | } | |
514 | ||
515 | if (is_cache_invalid) { | |
516 | host->cache_addr_value[0] = ~0; | |
517 | host->cache_addr_value[1] = ~0; | |
518 | } | |
519 | } | |
520 | ||
521 | static irqreturn_t hinfc_irq_handle(int irq, void *devid) | |
522 | { | |
523 | struct hinfc_host *host = devid; | |
524 | unsigned int flag; | |
525 | ||
526 | flag = hinfc_read(host, HINFC504_INTS); | |
527 | /* store interrupts state */ | |
528 | host->irq_status |= flag; | |
529 | ||
530 | if (flag & HINFC504_INTS_DMA) { | |
531 | hinfc_write(host, HINFC504_INTCLR_DMA, HINFC504_INTCLR); | |
532 | complete(&host->cmd_complete); | |
533 | } else if (flag & HINFC504_INTS_CE) { | |
534 | hinfc_write(host, HINFC504_INTCLR_CE, HINFC504_INTCLR); | |
535 | } else if (flag & HINFC504_INTS_UE) { | |
536 | hinfc_write(host, HINFC504_INTCLR_UE, HINFC504_INTCLR); | |
537 | } | |
538 | ||
539 | return IRQ_HANDLED; | |
540 | } | |
541 | ||
542 | static int hisi_nand_read_page_hwecc(struct mtd_info *mtd, | |
543 | struct nand_chip *chip, uint8_t *buf, int oob_required, int page) | |
544 | { | |
d699ed25 | 545 | struct hinfc_host *host = nand_get_controller_data(chip); |
54f531f6 ZW |
546 | int max_bitflips = 0, stat = 0, stat_max = 0, status_ecc; |
547 | int stat_1, stat_2; | |
548 | ||
549 | chip->read_buf(mtd, buf, mtd->writesize); | |
550 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
551 | ||
552 | /* errors which can not be corrected by ECC */ | |
553 | if (host->irq_status & HINFC504_INTS_UE) { | |
554 | mtd->ecc_stats.failed++; | |
555 | } else if (host->irq_status & HINFC504_INTS_CE) { | |
556 | /* TODO: need add other ECC modes! */ | |
557 | switch (chip->ecc.strength) { | |
558 | case 16: | |
559 | status_ecc = hinfc_read(host, HINFC504_ECC_STATUS) >> | |
560 | HINFC504_ECC_16_BIT_SHIFT & 0x0fff; | |
561 | stat_2 = status_ecc & 0x3f; | |
562 | stat_1 = status_ecc >> 6 & 0x3f; | |
563 | stat = stat_1 + stat_2; | |
564 | stat_max = max_t(int, stat_1, stat_2); | |
565 | } | |
566 | mtd->ecc_stats.corrected += stat; | |
567 | max_bitflips = max_t(int, max_bitflips, stat_max); | |
568 | } | |
569 | host->irq_status = 0; | |
570 | ||
571 | return max_bitflips; | |
572 | } | |
573 | ||
574 | static int hisi_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, | |
575 | int page) | |
576 | { | |
d699ed25 | 577 | struct hinfc_host *host = nand_get_controller_data(chip); |
54f531f6 ZW |
578 | |
579 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
580 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
581 | ||
582 | if (host->irq_status & HINFC504_INTS_UE) { | |
583 | host->irq_status = 0; | |
584 | return -EBADMSG; | |
585 | } | |
586 | ||
587 | host->irq_status = 0; | |
588 | return 0; | |
589 | } | |
590 | ||
591 | static int hisi_nand_write_page_hwecc(struct mtd_info *mtd, | |
45aaeff9 BB |
592 | struct nand_chip *chip, const uint8_t *buf, int oob_required, |
593 | int page) | |
54f531f6 ZW |
594 | { |
595 | chip->write_buf(mtd, buf, mtd->writesize); | |
596 | if (oob_required) | |
597 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
598 | ||
599 | return 0; | |
600 | } | |
601 | ||
602 | static void hisi_nfc_host_init(struct hinfc_host *host) | |
603 | { | |
604 | struct nand_chip *chip = &host->chip; | |
605 | unsigned int flag = 0; | |
606 | ||
607 | host->version = hinfc_read(host, HINFC_VERSION); | |
608 | host->addr_cycle = 0; | |
609 | host->addr_value[0] = 0; | |
610 | host->addr_value[1] = 0; | |
611 | host->cache_addr_value[0] = ~0; | |
612 | host->cache_addr_value[1] = ~0; | |
613 | host->chipselect = 0; | |
614 | ||
615 | /* default page size: 2K, ecc_none. need modify */ | |
616 | flag = HINFC504_CON_OP_MODE_NORMAL | HINFC504_CON_READY_BUSY_SEL | |
617 | | ((0x001 & HINFC504_CON_PAGESIZE_MASK) | |
618 | << HINFC504_CON_PAGEISZE_SHIFT) | |
619 | | ((0x0 & HINFC504_CON_ECCTYPE_MASK) | |
620 | << HINFC504_CON_ECCTYPE_SHIFT) | |
621 | | ((chip->options & NAND_BUSWIDTH_16) ? | |
622 | HINFC504_CON_BUS_WIDTH : 0); | |
623 | hinfc_write(host, flag, HINFC504_CON); | |
624 | ||
625 | memset(host->mmio, 0xff, HINFC504_BUFFER_BASE_ADDRESS_LEN); | |
626 | ||
627 | hinfc_write(host, SET_HINFC504_PWIDTH(HINFC504_W_LATCH, | |
628 | HINFC504_R_LATCH, HINFC504_RW_LATCH), HINFC504_PWIDTH); | |
629 | ||
630 | /* enable DMA irq */ | |
631 | hinfc_write(host, HINFC504_INTEN_DMA, HINFC504_INTEN); | |
632 | } | |
633 | ||
2ca9ec9a BB |
634 | static int hisi_ooblayout_ecc(struct mtd_info *mtd, int section, |
635 | struct mtd_oob_region *oobregion) | |
636 | { | |
637 | /* FIXME: add ECC bytes position */ | |
638 | return -ENOTSUPP; | |
639 | } | |
640 | ||
641 | static int hisi_ooblayout_free(struct mtd_info *mtd, int section, | |
642 | struct mtd_oob_region *oobregion) | |
643 | { | |
644 | if (section) | |
645 | return -ERANGE; | |
646 | ||
647 | oobregion->offset = 2; | |
648 | oobregion->length = 6; | |
649 | ||
650 | return 0; | |
651 | } | |
652 | ||
653 | static const struct mtd_ooblayout_ops hisi_ooblayout_ops = { | |
654 | .ecc = hisi_ooblayout_ecc, | |
655 | .free = hisi_ooblayout_free, | |
54f531f6 ZW |
656 | }; |
657 | ||
658 | static int hisi_nfc_ecc_probe(struct hinfc_host *host) | |
659 | { | |
660 | unsigned int flag; | |
661 | int size, strength, ecc_bits; | |
662 | struct device *dev = host->dev; | |
663 | struct nand_chip *chip = &host->chip; | |
fa100163 | 664 | struct mtd_info *mtd = nand_to_mtd(chip); |
54f531f6 ZW |
665 | struct device_node *np = host->dev->of_node; |
666 | ||
667 | size = of_get_nand_ecc_step_size(np); | |
668 | strength = of_get_nand_ecc_strength(np); | |
669 | if (size != 1024) { | |
670 | dev_err(dev, "error ecc size: %d\n", size); | |
671 | return -EINVAL; | |
672 | } | |
673 | ||
674 | if ((size == 1024) && ((strength != 8) && (strength != 16) && | |
675 | (strength != 24) && (strength != 40))) { | |
676 | dev_err(dev, "ecc size and strength do not match\n"); | |
677 | return -EINVAL; | |
678 | } | |
679 | ||
680 | chip->ecc.size = size; | |
681 | chip->ecc.strength = strength; | |
682 | ||
683 | chip->ecc.read_page = hisi_nand_read_page_hwecc; | |
684 | chip->ecc.read_oob = hisi_nand_read_oob; | |
685 | chip->ecc.write_page = hisi_nand_write_page_hwecc; | |
686 | ||
687 | switch (chip->ecc.strength) { | |
688 | case 16: | |
689 | ecc_bits = 6; | |
690 | if (mtd->writesize == 2048) | |
2ca9ec9a | 691 | mtd_set_ooblayout(mtd, &hisi_ooblayout_ops); |
54f531f6 ZW |
692 | |
693 | /* TODO: add more page size support */ | |
694 | break; | |
695 | ||
696 | /* TODO: add more ecc strength support */ | |
697 | default: | |
698 | dev_err(dev, "not support strength: %d\n", chip->ecc.strength); | |
699 | return -EINVAL; | |
700 | } | |
701 | ||
702 | flag = hinfc_read(host, HINFC504_CON); | |
703 | /* add ecc type configure */ | |
704 | flag |= ((ecc_bits & HINFC504_CON_ECCTYPE_MASK) | |
705 | << HINFC504_CON_ECCTYPE_SHIFT); | |
706 | hinfc_write(host, flag, HINFC504_CON); | |
707 | ||
708 | /* enable ecc irq */ | |
709 | flag = hinfc_read(host, HINFC504_INTEN) & 0xfff; | |
710 | hinfc_write(host, flag | HINFC504_INTEN_UE | HINFC504_INTEN_CE, | |
711 | HINFC504_INTEN); | |
712 | ||
713 | return 0; | |
714 | } | |
715 | ||
716 | static int hisi_nfc_probe(struct platform_device *pdev) | |
717 | { | |
718 | int ret = 0, irq, buswidth, flag, max_chips = HINFC504_MAX_CHIP; | |
719 | struct device *dev = &pdev->dev; | |
720 | struct hinfc_host *host; | |
721 | struct nand_chip *chip; | |
722 | struct mtd_info *mtd; | |
723 | struct resource *res; | |
724 | struct device_node *np = dev->of_node; | |
54f531f6 ZW |
725 | |
726 | host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); | |
727 | if (!host) | |
728 | return -ENOMEM; | |
729 | host->dev = dev; | |
730 | ||
731 | platform_set_drvdata(pdev, host); | |
732 | chip = &host->chip; | |
fa100163 | 733 | mtd = nand_to_mtd(chip); |
54f531f6 ZW |
734 | |
735 | irq = platform_get_irq(pdev, 0); | |
736 | if (irq < 0) { | |
737 | dev_err(dev, "no IRQ resource defined\n"); | |
738 | ret = -ENXIO; | |
739 | goto err_res; | |
740 | } | |
741 | ||
742 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
743 | host->iobase = devm_ioremap_resource(dev, res); | |
744 | if (IS_ERR(host->iobase)) { | |
745 | ret = PTR_ERR(host->iobase); | |
746 | goto err_res; | |
747 | } | |
748 | ||
749 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
750 | host->mmio = devm_ioremap_resource(dev, res); | |
751 | if (IS_ERR(host->mmio)) { | |
752 | ret = PTR_ERR(host->mmio); | |
753 | dev_err(dev, "devm_ioremap_resource[1] fail\n"); | |
754 | goto err_res; | |
755 | } | |
756 | ||
54f531f6 ZW |
757 | mtd->name = "hisi_nand"; |
758 | mtd->dev.parent = &pdev->dev; | |
759 | ||
d699ed25 | 760 | nand_set_controller_data(chip, host); |
a61ae81a | 761 | nand_set_flash_node(chip, np); |
54f531f6 ZW |
762 | chip->cmdfunc = hisi_nfc_cmdfunc; |
763 | chip->select_chip = hisi_nfc_select_chip; | |
764 | chip->read_byte = hisi_nfc_read_byte; | |
765 | chip->read_word = hisi_nfc_read_word; | |
766 | chip->write_buf = hisi_nfc_write_buf; | |
767 | chip->read_buf = hisi_nfc_read_buf; | |
768 | chip->chip_delay = HINFC504_CHIP_DELAY; | |
769 | ||
770 | chip->ecc.mode = of_get_nand_ecc_mode(np); | |
771 | ||
772 | buswidth = of_get_nand_bus_width(np); | |
773 | if (buswidth == 16) | |
774 | chip->options |= NAND_BUSWIDTH_16; | |
775 | ||
776 | hisi_nfc_host_init(host); | |
777 | ||
d8bf368d | 778 | ret = devm_request_irq(dev, irq, hinfc_irq_handle, 0x0, "nandc", host); |
54f531f6 ZW |
779 | if (ret) { |
780 | dev_err(dev, "failed to request IRQ\n"); | |
781 | goto err_res; | |
782 | } | |
783 | ||
784 | ret = nand_scan_ident(mtd, max_chips, NULL); | |
785 | if (ret) { | |
786 | ret = -ENODEV; | |
787 | goto err_res; | |
788 | } | |
789 | ||
790 | host->buffer = dmam_alloc_coherent(dev, mtd->writesize + mtd->oobsize, | |
791 | &host->dma_buffer, GFP_KERNEL); | |
792 | if (!host->buffer) { | |
793 | ret = -ENOMEM; | |
794 | goto err_res; | |
795 | } | |
796 | ||
797 | host->dma_oob = host->dma_buffer + mtd->writesize; | |
798 | memset(host->buffer, 0xff, mtd->writesize + mtd->oobsize); | |
799 | ||
800 | flag = hinfc_read(host, HINFC504_CON); | |
801 | flag &= ~(HINFC504_CON_PAGESIZE_MASK << HINFC504_CON_PAGEISZE_SHIFT); | |
802 | switch (mtd->writesize) { | |
803 | case 2048: | |
804 | flag |= (0x001 << HINFC504_CON_PAGEISZE_SHIFT); break; | |
805 | /* | |
806 | * TODO: add more pagesize support, | |
807 | * default pagesize has been set in hisi_nfc_host_init | |
808 | */ | |
809 | default: | |
810 | dev_err(dev, "NON-2KB page size nand flash\n"); | |
811 | ret = -EINVAL; | |
812 | goto err_res; | |
813 | } | |
814 | hinfc_write(host, flag, HINFC504_CON); | |
815 | ||
816 | if (chip->ecc.mode == NAND_ECC_HW) | |
817 | hisi_nfc_ecc_probe(host); | |
818 | ||
819 | ret = nand_scan_tail(mtd); | |
820 | if (ret) { | |
821 | dev_err(dev, "nand_scan_tail failed: %d\n", ret); | |
822 | goto err_res; | |
823 | } | |
824 | ||
a61ae81a | 825 | ret = mtd_device_register(mtd, NULL, 0); |
54f531f6 ZW |
826 | if (ret) { |
827 | dev_err(dev, "Err MTD partition=%d\n", ret); | |
828 | goto err_mtd; | |
829 | } | |
830 | ||
831 | return 0; | |
832 | ||
833 | err_mtd: | |
834 | nand_release(mtd); | |
835 | err_res: | |
836 | return ret; | |
837 | } | |
838 | ||
839 | static int hisi_nfc_remove(struct platform_device *pdev) | |
840 | { | |
841 | struct hinfc_host *host = platform_get_drvdata(pdev); | |
fa100163 | 842 | struct mtd_info *mtd = nand_to_mtd(&host->chip); |
54f531f6 ZW |
843 | |
844 | nand_release(mtd); | |
845 | ||
846 | return 0; | |
847 | } | |
848 | ||
849 | #ifdef CONFIG_PM_SLEEP | |
850 | static int hisi_nfc_suspend(struct device *dev) | |
851 | { | |
852 | struct hinfc_host *host = dev_get_drvdata(dev); | |
853 | unsigned long timeout = jiffies + HINFC504_NFC_PM_TIMEOUT; | |
854 | ||
855 | while (time_before(jiffies, timeout)) { | |
856 | if (((hinfc_read(host, HINFC504_STATUS) & 0x1) == 0x0) && | |
857 | (hinfc_read(host, HINFC504_DMA_CTRL) & | |
858 | HINFC504_DMA_CTRL_DMA_START)) { | |
859 | cond_resched(); | |
860 | return 0; | |
861 | } | |
862 | } | |
863 | ||
864 | dev_err(host->dev, "nand controller suspend timeout.\n"); | |
865 | ||
866 | return -EAGAIN; | |
867 | } | |
868 | ||
869 | static int hisi_nfc_resume(struct device *dev) | |
870 | { | |
871 | int cs; | |
872 | struct hinfc_host *host = dev_get_drvdata(dev); | |
873 | struct nand_chip *chip = &host->chip; | |
874 | ||
875 | for (cs = 0; cs < chip->numchips; cs++) | |
876 | hisi_nfc_send_cmd_reset(host, cs); | |
877 | hinfc_write(host, SET_HINFC504_PWIDTH(HINFC504_W_LATCH, | |
878 | HINFC504_R_LATCH, HINFC504_RW_LATCH), HINFC504_PWIDTH); | |
879 | ||
880 | return 0; | |
881 | } | |
882 | #endif | |
883 | static SIMPLE_DEV_PM_OPS(hisi_nfc_pm_ops, hisi_nfc_suspend, hisi_nfc_resume); | |
884 | ||
885 | static const struct of_device_id nfc_id_table[] = { | |
886 | { .compatible = "hisilicon,504-nfc" }, | |
887 | {} | |
888 | }; | |
889 | MODULE_DEVICE_TABLE(of, nfc_id_table); | |
890 | ||
891 | static struct platform_driver hisi_nfc_driver = { | |
892 | .driver = { | |
893 | .name = "hisi_nand", | |
894 | .of_match_table = nfc_id_table, | |
895 | .pm = &hisi_nfc_pm_ops, | |
896 | }, | |
897 | .probe = hisi_nfc_probe, | |
898 | .remove = hisi_nfc_remove, | |
899 | }; | |
900 | ||
901 | module_platform_driver(hisi_nfc_driver); | |
902 | ||
903 | MODULE_LICENSE("GPL"); | |
904 | MODULE_AUTHOR("Zhou Wang"); | |
905 | MODULE_AUTHOR("Zhiyong Cai"); | |
906 | MODULE_DESCRIPTION("Hisilicon Nand Flash Controller Driver"); |