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[mirror_ubuntu-artful-kernel.git] / drivers / mtd / nand / mpc5121_nfc.c
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bb315f74
AG		 1/*
2 * Copyright 2004-2008 Freescale Semiconductor, Inc.
3 * Copyright 2009 Semihalf.
4 *
5 * Approved as OSADL project by a majority of OSADL members and funded
6 * by OSADL membership fees in 2009; for details see www.osadl.org.
7 *
8 * Based on original driver from Freescale Semiconductor
9 * written by John Rigby <jrigby@freescale.com> on basis
10 * of drivers/mtd/nand/mxc_nand.c. Reworked and extended
11 * Piotr Ziecik <kosmo@semihalf.com>.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
25 * MA 02110-1301, USA.
26 */
27
28#include <linux/module.h>
29#include <linux/clk.h>
05d71b46 30#include <linux/gfp.h>
bb315f74 31#include <linux/delay.h>
83025c82 32#include <linux/err.h>
bb315f74
AG		 33#include <linux/interrupt.h>
34#include <linux/io.h>
35#include <linux/mtd/mtd.h>
36#include <linux/mtd/nand.h>
37#include <linux/mtd/partitions.h>
5af50730 38#include <linux/of_address.h>
bb315f74 39#include <linux/of_device.h>
5af50730 40#include <linux/of_irq.h>
bb315f74
AG		 41#include <linux/of_platform.h>
42
43#include <asm/mpc5121.h>
44
45/* Addresses for NFC MAIN RAM BUFFER areas */
46#define NFC_MAIN_AREA(n) ((n) * 0x200)
47
48/* Addresses for NFC SPARE BUFFER areas */
49#define NFC_SPARE_BUFFERS 8
50#define NFC_SPARE_LEN 0x40
51#define NFC_SPARE_AREA(n) (0x1000 + ((n) * NFC_SPARE_LEN))
52
53/* MPC5121 NFC registers */
54#define NFC_BUF_ADDR 0x1E04
55#define NFC_FLASH_ADDR 0x1E06
56#define NFC_FLASH_CMD 0x1E08
57#define NFC_CONFIG 0x1E0A
58#define NFC_ECC_STATUS1 0x1E0C
59#define NFC_ECC_STATUS2 0x1E0E
60#define NFC_SPAS 0x1E10
61#define NFC_WRPROT 0x1E12
62#define NFC_NF_WRPRST 0x1E18
63#define NFC_CONFIG1 0x1E1A
64#define NFC_CONFIG2 0x1E1C
65#define NFC_UNLOCKSTART_BLK0 0x1E20
66#define NFC_UNLOCKEND_BLK0 0x1E22
67#define NFC_UNLOCKSTART_BLK1 0x1E24
68#define NFC_UNLOCKEND_BLK1 0x1E26
69#define NFC_UNLOCKSTART_BLK2 0x1E28
70#define NFC_UNLOCKEND_BLK2 0x1E2A
71#define NFC_UNLOCKSTART_BLK3 0x1E2C
72#define NFC_UNLOCKEND_BLK3 0x1E2E
73
74/* Bit Definitions: NFC_BUF_ADDR */
75#define NFC_RBA_MASK (7 << 0)
76#define NFC_ACTIVE_CS_SHIFT 5
77#define NFC_ACTIVE_CS_MASK (3 << NFC_ACTIVE_CS_SHIFT)
78
79/* Bit Definitions: NFC_CONFIG */
80#define NFC_BLS_UNLOCKED (1 << 1)
81
82/* Bit Definitions: NFC_CONFIG1 */
83#define NFC_ECC_4BIT (1 << 0)
84#define NFC_FULL_PAGE_DMA (1 << 1)
85#define NFC_SPARE_ONLY (1 << 2)
86#define NFC_ECC_ENABLE (1 << 3)
87#define NFC_INT_MASK (1 << 4)
88#define NFC_BIG_ENDIAN (1 << 5)
89#define NFC_RESET (1 << 6)
90#define NFC_CE (1 << 7)
91#define NFC_ONE_CYCLE (1 << 8)
92#define NFC_PPB_32 (0 << 9)
93#define NFC_PPB_64 (1 << 9)
94#define NFC_PPB_128 (2 << 9)
95#define NFC_PPB_256 (3 << 9)
96#define NFC_PPB_MASK (3 << 9)
97#define NFC_FULL_PAGE_INT (1 << 11)
98
99/* Bit Definitions: NFC_CONFIG2 */
100#define NFC_COMMAND (1 << 0)
101#define NFC_ADDRESS (1 << 1)
102#define NFC_INPUT (1 << 2)
103#define NFC_OUTPUT (1 << 3)
104#define NFC_ID (1 << 4)
105#define NFC_STATUS (1 << 5)
106#define NFC_CMD_FAIL (1 << 15)
107#define NFC_INT (1 << 15)
108
109/* Bit Definitions: NFC_WRPROT */
110#define NFC_WPC_LOCK_TIGHT (1 << 0)
111#define NFC_WPC_LOCK (1 << 1)
112#define NFC_WPC_UNLOCK (1 << 2)
113
114#define DRV_NAME "mpc5121_nfc"
115
116/* Timeouts */
117#define NFC_RESET_TIMEOUT 1000 /* 1 ms */
118#define NFC_TIMEOUT (HZ / 10) /* 1/10 s */
119
120struct mpc5121_nfc_prv {
121 struct mtd_info mtd;
122 struct nand_chip chip;
123 int irq;
124 void __iomem *regs;
125 struct clk *clk;
126 wait_queue_head_t irq_waitq;
127 uint column;
128 int spareonly;
129 void __iomem *csreg;
130 struct device *dev;
131};
132
133static void mpc5121_nfc_done(struct mtd_info *mtd);
134
bb315f74
AG		 135/* Read NFC register */
136static inline u16 nfc_read(struct mtd_info *mtd, uint reg)
137{
138 struct nand_chip *chip = mtd->priv;
139 struct mpc5121_nfc_prv *prv = chip->priv;
140
141 return in_be16(prv->regs + reg);
142}
143
144/* Write NFC register */
145static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val)
146{
147 struct nand_chip *chip = mtd->priv;
148 struct mpc5121_nfc_prv *prv = chip->priv;
149
150 out_be16(prv->regs + reg, val);
151}
152
153/* Set bits in NFC register */
154static inline void nfc_set(struct mtd_info *mtd, uint reg, u16 bits)
155{
156 nfc_write(mtd, reg, nfc_read(mtd, reg) | bits);
157}
158
159/* Clear bits in NFC register */
160static inline void nfc_clear(struct mtd_info *mtd, uint reg, u16 bits)
161{
162 nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits);
163}
164
165/* Invoke address cycle */
166static inline void mpc5121_nfc_send_addr(struct mtd_info *mtd, u16 addr)
167{
168 nfc_write(mtd, NFC_FLASH_ADDR, addr);
169 nfc_write(mtd, NFC_CONFIG2, NFC_ADDRESS);
170 mpc5121_nfc_done(mtd);
171}
172
173/* Invoke command cycle */
174static inline void mpc5121_nfc_send_cmd(struct mtd_info *mtd, u16 cmd)
175{
176 nfc_write(mtd, NFC_FLASH_CMD, cmd);
177 nfc_write(mtd, NFC_CONFIG2, NFC_COMMAND);
178 mpc5121_nfc_done(mtd);
179}
180
181/* Send data from NFC buffers to NAND flash */
182static inline void mpc5121_nfc_send_prog_page(struct mtd_info *mtd)
183{
184 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
185 nfc_write(mtd, NFC_CONFIG2, NFC_INPUT);
186 mpc5121_nfc_done(mtd);
187}
188
189/* Receive data from NAND flash */
190static inline void mpc5121_nfc_send_read_page(struct mtd_info *mtd)
191{
192 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
193 nfc_write(mtd, NFC_CONFIG2, NFC_OUTPUT);
194 mpc5121_nfc_done(mtd);
195}
196
197/* Receive ID from NAND flash */
198static inline void mpc5121_nfc_send_read_id(struct mtd_info *mtd)
199{
200 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
201 nfc_write(mtd, NFC_CONFIG2, NFC_ID);
202 mpc5121_nfc_done(mtd);
203}
204
205/* Receive status from NAND flash */
206static inline void mpc5121_nfc_send_read_status(struct mtd_info *mtd)
207{
208 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
209 nfc_write(mtd, NFC_CONFIG2, NFC_STATUS);
210 mpc5121_nfc_done(mtd);
211}
212
213/* NFC interrupt handler */
214static irqreturn_t mpc5121_nfc_irq(int irq, void *data)
215{
216 struct mtd_info *mtd = data;
217 struct nand_chip *chip = mtd->priv;
218 struct mpc5121_nfc_prv *prv = chip->priv;
219
220 nfc_set(mtd, NFC_CONFIG1, NFC_INT_MASK);
221 wake_up(&prv->irq_waitq);
222
223 return IRQ_HANDLED;
224}
225
226/* Wait for operation complete */
227static void mpc5121_nfc_done(struct mtd_info *mtd)
228{
229 struct nand_chip *chip = mtd->priv;
230 struct mpc5121_nfc_prv *prv = chip->priv;
231 int rv;
232
233 if ((nfc_read(mtd, NFC_CONFIG2) & NFC_INT) == 0) {
234 nfc_clear(mtd, NFC_CONFIG1, NFC_INT_MASK);
235 rv = wait_event_timeout(prv->irq_waitq,
236 (nfc_read(mtd, NFC_CONFIG2) & NFC_INT), NFC_TIMEOUT);
237
238 if (!rv)
239 dev_warn(prv->dev,
240 "Timeout while waiting for interrupt.\n");
241 }
242
243 nfc_clear(mtd, NFC_CONFIG2, NFC_INT);
244}
245
246/* Do address cycle(s) */
247static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
248{
249 struct nand_chip *chip = mtd->priv;
250 u32 pagemask = chip->pagemask;
251
252 if (column != -1) {
253 mpc5121_nfc_send_addr(mtd, column);
254 if (mtd->writesize > 512)
255 mpc5121_nfc_send_addr(mtd, column >> 8);
256 }
257
258 if (page != -1) {
259 do {
260 mpc5121_nfc_send_addr(mtd, page & 0xFF);
261 page >>= 8;
262 pagemask >>= 8;
263 } while (pagemask);
264 }
265}
266
267/* Control chip select signals */
268static void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
269{
270 if (chip < 0) {
271 nfc_clear(mtd, NFC_CONFIG1, NFC_CE);
272 return;
273 }
274
275 nfc_clear(mtd, NFC_BUF_ADDR, NFC_ACTIVE_CS_MASK);
276 nfc_set(mtd, NFC_BUF_ADDR, (chip << NFC_ACTIVE_CS_SHIFT) &
277 NFC_ACTIVE_CS_MASK);
278 nfc_set(mtd, NFC_CONFIG1, NFC_CE);
279}
280
281/* Init external chip select logic on ADS5121 board */
282static int ads5121_chipselect_init(struct mtd_info *mtd)
283{
284 struct nand_chip *chip = mtd->priv;
285 struct mpc5121_nfc_prv *prv = chip->priv;
286 struct device_node *dn;
287
288 dn = of_find_compatible_node(NULL, NULL, "fsl,mpc5121ads-cpld");
289 if (dn) {
290 prv->csreg = of_iomap(dn, 0);
291 of_node_put(dn);
292 if (!prv->csreg)
293 return -ENOMEM;
294
295 /* CPLD Register 9 controls NAND /CE Lines */
296 prv->csreg += 9;
297 return 0;
298 }
299
300 return -EINVAL;
301}
302
303/* Control chips select signal on ADS5121 board */
304static void ads5121_select_chip(struct mtd_info *mtd, int chip)
305{
306 struct nand_chip *nand = mtd->priv;
307 struct mpc5121_nfc_prv *prv = nand->priv;
308 u8 v;
309
310 v = in_8(prv->csreg);
311 v |= 0x0F;
312
313 if (chip >= 0) {
314 mpc5121_nfc_select_chip(mtd, 0);
315 v &= ~(1 << chip);
316 } else
317 mpc5121_nfc_select_chip(mtd, -1);
318
319 out_8(prv->csreg, v);
320}
321
322/* Read NAND Ready/Busy signal */
323static int mpc5121_nfc_dev_ready(struct mtd_info *mtd)
324{
325 /*
326 * NFC handles ready/busy signal internally. Therefore, this function
327 * always returns status as ready.
328 */
329 return 1;
330}
331
332/* Write command to NAND flash */
333static void mpc5121_nfc_command(struct mtd_info *mtd, unsigned command,
334 int column, int page)
335{
336 struct nand_chip *chip = mtd->priv;
337 struct mpc5121_nfc_prv *prv = chip->priv;
338
339 prv->column = (column >= 0) ? column : 0;
340 prv->spareonly = 0;
341
342 switch (command) {
343 case NAND_CMD_PAGEPROG:
344 mpc5121_nfc_send_prog_page(mtd);
345 break;
346 /*
347 * NFC does not support sub-page reads and writes,
348 * so emulate them using full page transfers.
349 */
350 case NAND_CMD_READ0:
351 column = 0;
352 break;
353
354 case NAND_CMD_READ1:
355 prv->column += 256;
356 command = NAND_CMD_READ0;
357 column = 0;
358 break;
359
360 case NAND_CMD_READOOB:
361 prv->spareonly = 1;
362 command = NAND_CMD_READ0;
363 column = 0;
364 break;
365
366 case NAND_CMD_SEQIN:
367 mpc5121_nfc_command(mtd, NAND_CMD_READ0, column, page);
368 column = 0;
369 break;
370
371 case NAND_CMD_ERASE1:
372 case NAND_CMD_ERASE2:
373 case NAND_CMD_READID:
374 case NAND_CMD_STATUS:
375 break;
376
377 default:
378 return;
379 }
380
381 mpc5121_nfc_send_cmd(mtd, command);
382 mpc5121_nfc_addr_cycle(mtd, column, page);
383
384 switch (command) {
385 case NAND_CMD_READ0:
386 if (mtd->writesize > 512)
387 mpc5121_nfc_send_cmd(mtd, NAND_CMD_READSTART);
388 mpc5121_nfc_send_read_page(mtd);
389 break;
390
391 case NAND_CMD_READID:
392 mpc5121_nfc_send_read_id(mtd);
393 break;
394
395 case NAND_CMD_STATUS:
396 mpc5121_nfc_send_read_status(mtd);
397 if (chip->options & NAND_BUSWIDTH_16)
398 prv->column = 1;
399 else
400 prv->column = 0;
401 break;
402 }
403}
404
405/* Copy data from/to NFC spare buffers. */
406static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset,
407 u8 *buffer, uint size, int wr)
408{
409 struct nand_chip *nand = mtd->priv;
410 struct mpc5121_nfc_prv *prv = nand->priv;
411 uint o, s, sbsize, blksize;
412
413 /*
414 * NAND spare area is available through NFC spare buffers.
415 * The NFC divides spare area into (page_size / 512) chunks.
416 * Each chunk is placed into separate spare memory area, using
417 * first (spare_size / num_of_chunks) bytes of the buffer.
418 *
419 * For NAND device in which the spare area is not divided fully
420 * by the number of chunks, number of used bytes in each spare
421 * buffer is rounded down to the nearest even number of bytes,
422 * and all remaining bytes are added to the last used spare area.
423 *
424 * For more information read section 26.6.10 of MPC5121e
425 * Microcontroller Reference Manual, Rev. 3.
426 */
427
428 /* Calculate number of valid bytes in each spare buffer */
429 sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1;
430
431 while (size) {
432 /* Calculate spare buffer number */
433 s = offset / sbsize;
434 if (s > NFC_SPARE_BUFFERS - 1)
435 s = NFC_SPARE_BUFFERS - 1;
436
437 /*
438 * Calculate offset to requested data block in selected spare
439 * buffer and its size.
440 */
441 o = offset - (s * sbsize);
442 blksize = min(sbsize - o, size);
443
444 if (wr)
445 memcpy_toio(prv->regs + NFC_SPARE_AREA(s) + o,
446 buffer, blksize);
447 else
448 memcpy_fromio(buffer,
449 prv->regs + NFC_SPARE_AREA(s) + o, blksize);
450
451 buffer += blksize;
452 offset += blksize;
453 size -= blksize;
454 };
455}
456
457/* Copy data from/to NFC main and spare buffers */
458static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char *buf, int len,
459 int wr)
460{
461 struct nand_chip *chip = mtd->priv;
462 struct mpc5121_nfc_prv *prv = chip->priv;
463 uint c = prv->column;
464 uint l;
465
466 /* Handle spare area access */
467 if (prv->spareonly || c >= mtd->writesize) {
468 /* Calculate offset from beginning of spare area */
469 if (c >= mtd->writesize)
470 c -= mtd->writesize;
471
472 prv->column += len;
473 mpc5121_nfc_copy_spare(mtd, c, buf, len, wr);
474 return;
475 }
476
477 /*
478 * Handle main area access - limit copy length to prevent
479 * crossing main/spare boundary.
480 */
481 l = min((uint)len, mtd->writesize - c);
482 prv->column += l;
483
484 if (wr)
485 memcpy_toio(prv->regs + NFC_MAIN_AREA(0) + c, buf, l);
486 else
487 memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(0) + c, l);
488
489 /* Handle crossing main/spare boundary */
490 if (l != len) {
491 buf += l;
492 len -= l;
493 mpc5121_nfc_buf_copy(mtd, buf, len, wr);
494 }
495}
496
497/* Read data from NFC buffers */
498static void mpc5121_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
499{
500 mpc5121_nfc_buf_copy(mtd, buf, len, 0);
501}
502
503/* Write data to NFC buffers */
504static void mpc5121_nfc_write_buf(struct mtd_info *mtd,
505 const u_char *buf, int len)
506{
507 mpc5121_nfc_buf_copy(mtd, (u_char *)buf, len, 1);
508}
509
bb315f74
AG		 510/* Read byte from NFC buffers */
511static u8 mpc5121_nfc_read_byte(struct mtd_info *mtd)
512{
513 u8 tmp;
514
515 mpc5121_nfc_read_buf(mtd, &tmp, sizeof(tmp));
516
517 return tmp;
518}
519
520/* Read word from NFC buffers */
521static u16 mpc5121_nfc_read_word(struct mtd_info *mtd)
522{
523 u16 tmp;
524
525 mpc5121_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
526
527 return tmp;
528}
529
530/*
531 * Read NFC configuration from Reset Config Word
532 *
533 * NFC is configured during reset in basis of information stored
534 * in Reset Config Word. There is no other way to set NAND block
535 * size, spare size and bus width.
536 */
537static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd)
538{
539 struct nand_chip *chip = mtd->priv;
540 struct mpc5121_nfc_prv *prv = chip->priv;
541 struct mpc512x_reset_module *rm;
542 struct device_node *rmnode;
543 uint rcw_pagesize = 0;
544 uint rcw_sparesize = 0;
545 uint rcw_width;
546 uint rcwh;
547 uint romloc, ps;
cf363518 548 int ret = 0;
bb315f74
AG		 549
550 rmnode = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset");
551 if (!rmnode) {
552 dev_err(prv->dev, "Missing 'fsl,mpc5121-reset' "
553 "node in device tree!\n");
554 return -ENODEV;
555 }
556
557 rm = of_iomap(rmnode, 0);
558 if (!rm) {
559 dev_err(prv->dev, "Error mapping reset module node!\n");
cf363518
JL		 560 ret = -EBUSY;
561 goto out;
bb315f74
AG		 562 }
563
564 rcwh = in_be32(&rm->rcwhr);
565
566 /* Bit 6: NFC bus width */
567 rcw_width = ((rcwh >> 6) & 0x1) ? 2 : 1;
568
569 /* Bit 7: NFC Page/Spare size */
570 ps = (rcwh >> 7) & 0x1;
571
572 /* Bits [22:21]: ROM Location */
573 romloc = (rcwh >> 21) & 0x3;
574
575 /* Decode RCW bits */
576 switch ((ps << 2) | romloc) {
577 case 0x00:
578 case 0x01:
579 rcw_pagesize = 512;
580 rcw_sparesize = 16;
581 break;
582 case 0x02:
583 case 0x03:
584 rcw_pagesize = 4096;
585 rcw_sparesize = 128;
586 break;
587 case 0x04:
588 case 0x05:
589 rcw_pagesize = 2048;
590 rcw_sparesize = 64;
591 break;
592 case 0x06:
593 case 0x07:
594 rcw_pagesize = 4096;
595 rcw_sparesize = 218;
596 break;
597 }
598
599 mtd->writesize = rcw_pagesize;
600 mtd->oobsize = rcw_sparesize;
601 if (rcw_width == 2)
602 chip->options |= NAND_BUSWIDTH_16;
603
604 dev_notice(prv->dev, "Configured for "
605 "%u-bit NAND, page size %u "
606 "with %u spare.\n",
607 rcw_width * 8, rcw_pagesize,
608 rcw_sparesize);
609 iounmap(rm);
cf363518 610out:
bb315f74 611 of_node_put(rmnode);
cf363518 612 return ret;
bb315f74
AG		 613}
614
615/* Free driver resources */
616static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
617{
618 struct nand_chip *chip = mtd->priv;
619 struct mpc5121_nfc_prv *prv = chip->priv;
620
180890c7
GS		 621 if (prv->clk)
622 clk_disable_unprepare(prv->clk);
bb315f74
AG		 623
624 if (prv->csreg)
625 iounmap(prv->csreg);
626}
627
06f25510 628static int mpc5121_nfc_probe(struct platform_device *op)
bb315f74 629{
14acbbf8 630 struct device_node *rootnode, *dn = op->dev.of_node;
180890c7 631 struct clk *clk;
bb315f74
AG		 632 struct device *dev = &op->dev;
633 struct mpc5121_nfc_prv *prv;
634 struct resource res;
635 struct mtd_info *mtd;
bb315f74
AG		 636 struct nand_chip *chip;
637 unsigned long regs_paddr, regs_size;
766f271a 638 const __be32 *chips_no;
bb315f74
AG		 639 int resettime = 0;
640 int retval = 0;
641 int rev, len;
b3702ea4 642 struct mtd_part_parser_data ppdata;
bb315f74
AG		 643
644 /*
645 * Check SoC revision. This driver supports only NFC
6f1f3d0a 646 * in MPC5121 revision 2 and MPC5123 revision 3.
bb315f74
AG		 647 */
648 rev = (mfspr(SPRN_SVR) >> 4) & 0xF;
6f1f3d0a 649 if ((rev != 2) && (rev != 3)) {
bb315f74
AG		 650 dev_err(dev, "SoC revision %u is not supported!\n", rev);
651 return -ENXIO;
652 }
653
654 prv = devm_kzalloc(dev, sizeof(*prv), GFP_KERNEL);
61a623fe 655 if (!prv)
bb315f74 656 return -ENOMEM;
bb315f74
AG		 657
658 mtd = &prv->mtd;
659 chip = &prv->chip;
660
661 mtd->priv = chip;
662 chip->priv = prv;
663 prv->dev = dev;
664
665 /* Read NFC configuration from Reset Config Word */
666 retval = mpc5121_nfc_read_hw_config(mtd);
667 if (retval) {
668 dev_err(dev, "Unable to read NFC config!\n");
669 return retval;
670 }
671
672 prv->irq = irq_of_parse_and_map(dn, 0);
673 if (prv->irq == NO_IRQ) {
674 dev_err(dev, "Error mapping IRQ!\n");
675 return -EINVAL;
676 }
677
678 retval = of_address_to_resource(dn, 0, &res);
679 if (retval) {
680 dev_err(dev, "Error parsing memory region!\n");
681 return retval;
682 }
683
684 chips_no = of_get_property(dn, "chips", &len);
685 if (!chips_no || len != sizeof(*chips_no)) {
686 dev_err(dev, "Invalid/missing 'chips' property!\n");
687 return -EINVAL;
688 }
689
690 regs_paddr = res.start;
28f65c11 691 regs_size = resource_size(&res);
bb315f74
AG		 692
693 if (!devm_request_mem_region(dev, regs_paddr, regs_size, DRV_NAME)) {
694 dev_err(dev, "Error requesting memory region!\n");
695 return -EBUSY;
696 }
697
698 prv->regs = devm_ioremap(dev, regs_paddr, regs_size);
699 if (!prv->regs) {
700 dev_err(dev, "Error mapping memory region!\n");
701 return -ENOMEM;
702 }
703
704 mtd->name = "MPC5121 NAND";
b3702ea4 705 ppdata.of_node = dn;
bb315f74
AG		 706 chip->dev_ready = mpc5121_nfc_dev_ready;
707 chip->cmdfunc = mpc5121_nfc_command;
708 chip->read_byte = mpc5121_nfc_read_byte;
709 chip->read_word = mpc5121_nfc_read_word;
710 chip->read_buf = mpc5121_nfc_read_buf;
711 chip->write_buf = mpc5121_nfc_write_buf;
bb315f74 712 chip->select_chip = mpc5121_nfc_select_chip;
bb9ebd4e 713 chip->bbt_options = NAND_BBT_USE_FLASH;
bb315f74
AG		 714 chip->ecc.mode = NAND_ECC_SOFT;
715
716 /* Support external chip-select logic on ADS5121 board */
717 rootnode = of_find_node_by_path("/");
718 if (of_device_is_compatible(rootnode, "fsl,mpc5121ads")) {
719 retval = ads5121_chipselect_init(mtd);
720 if (retval) {
721 dev_err(dev, "Chipselect init error!\n");
722 of_node_put(rootnode);
723 return retval;
724 }
725
726 chip->select_chip = ads5121_select_chip;
727 }
728 of_node_put(rootnode);
729
730 /* Enable NFC clock */
10de271f 731 clk = devm_clk_get(dev, "ipg");
180890c7 732 if (IS_ERR(clk)) {
bb315f74 733 dev_err(dev, "Unable to acquire NFC clock!\n");
180890c7 734 retval = PTR_ERR(clk);
bb315f74
AG		 735 goto error;
736 }
180890c7
GS		 737 retval = clk_prepare_enable(clk);
738 if (retval) {
739 dev_err(dev, "Unable to enable NFC clock!\n");
740 goto error;
741 }
742 prv->clk = clk;
bb315f74
AG		 743
744 /* Reset NAND Flash controller */
745 nfc_set(mtd, NFC_CONFIG1, NFC_RESET);
746 while (nfc_read(mtd, NFC_CONFIG1) & NFC_RESET) {
747 if (resettime++ >= NFC_RESET_TIMEOUT) {
748 dev_err(dev, "Timeout while resetting NFC!\n");
749 retval = -EINVAL;
750 goto error;
751 }
752
753 udelay(1);
754 }
755
756 /* Enable write to NFC memory */
757 nfc_write(mtd, NFC_CONFIG, NFC_BLS_UNLOCKED);
758
759 /* Enable write to all NAND pages */
760 nfc_write(mtd, NFC_UNLOCKSTART_BLK0, 0x0000);
761 nfc_write(mtd, NFC_UNLOCKEND_BLK0, 0xFFFF);
762 nfc_write(mtd, NFC_WRPROT, NFC_WPC_UNLOCK);
763
764 /*
765 * Setup NFC:
766 * - Big Endian transfers,
767 * - Interrupt after full page read/write.
768 */
769 nfc_write(mtd, NFC_CONFIG1, NFC_BIG_ENDIAN | NFC_INT_MASK |
770 NFC_FULL_PAGE_INT);
771
772 /* Set spare area size */
773 nfc_write(mtd, NFC_SPAS, mtd->oobsize >> 1);
774
775 init_waitqueue_head(&prv->irq_waitq);
776 retval = devm_request_irq(dev, prv->irq, &mpc5121_nfc_irq, 0, DRV_NAME,
777 mtd);
778 if (retval) {
779 dev_err(dev, "Error requesting IRQ!\n");
780 goto error;
781 }
782
783 /* Detect NAND chips */
766f271a 784 if (nand_scan(mtd, be32_to_cpup(chips_no))) {
bb315f74 785 dev_err(dev, "NAND Flash not found !\n");
bb315f74
AG		 786 retval = -ENXIO;
787 goto error;
788 }
789
790 /* Set erase block size */
791 switch (mtd->erasesize / mtd->writesize) {
792 case 32:
793 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_32);
794 break;
795
796 case 64:
797 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_64);
798 break;
799
800 case 128:
801 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_128);
802 break;
803
804 case 256:
805 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_256);
806 break;
807
808 default:
809 dev_err(dev, "Unsupported NAND flash!\n");
bb315f74
AG		 810 retval = -ENXIO;
811 goto error;
812 }
813
814 dev_set_drvdata(dev, mtd);
815
816 /* Register device in MTD */
a9093f06 817 retval = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
bb315f74
AG		 818 if (retval) {
819 dev_err(dev, "Error adding MTD device!\n");
bb315f74
AG		 820 goto error;
821 }
822
823 return 0;
824error:
825 mpc5121_nfc_free(dev, mtd);
826 return retval;
827}
828
810b7e06 829static int mpc5121_nfc_remove(struct platform_device *op)
bb315f74
AG		 830{
831 struct device *dev = &op->dev;
832 struct mtd_info *mtd = dev_get_drvdata(dev);
bb315f74
AG		 833
834 nand_release(mtd);
bb315f74
AG		 835 mpc5121_nfc_free(dev, mtd);
836
837 return 0;
838}
839
66610443 840static const struct of_device_id mpc5121_nfc_match[] = {
bb315f74
AG		 841 { .compatible = "fsl,mpc5121-nfc", },
842 {},
843};
7446076e 844MODULE_DEVICE_TABLE(of, mpc5121_nfc_match);
bb315f74 845
1c48a5c9 846static struct platform_driver mpc5121_nfc_driver = {
bb315f74 847 .probe = mpc5121_nfc_probe,
5153b88c 848 .remove = mpc5121_nfc_remove,
bb315f74 849 .driver = {
14acbbf8 850 .name = DRV_NAME,
14acbbf8 851 .of_match_table = mpc5121_nfc_match,
bb315f74
AG		 852 },
853};
854
f99640de 855module_platform_driver(mpc5121_nfc_driver);
bb315f74
AG		 856
857MODULE_AUTHOR("Freescale Semiconductor, Inc.");
858MODULE_DESCRIPTION("MPC5121 NAND MTD driver");
859MODULE_LICENSE("GPL");
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