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1d6b1e46 JRO |
1 | /* |
2 | * MTK SDG1 ECC controller | |
3 | * | |
4 | * Copyright (c) 2016 Mediatek | |
5 | * Authors: Xiaolei Li <xiaolei.li@mediatek.com> | |
6 | * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published | |
9 | * by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__ | |
13 | #define __DRIVERS_MTD_NAND_MTK_ECC_H__ | |
14 | ||
15 | #include <linux/types.h> | |
16 | ||
17 | #define ECC_PARITY_BITS (14) | |
18 | ||
19 | enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1}; | |
20 | enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE}; | |
21 | ||
22 | struct device_node; | |
23 | struct mtk_ecc; | |
24 | ||
25 | struct mtk_ecc_stats { | |
26 | u32 corrected; | |
27 | u32 bitflips; | |
28 | u32 failed; | |
29 | }; | |
30 | ||
31 | struct mtk_ecc_config { | |
32 | enum mtk_ecc_operation op; | |
33 | enum mtk_ecc_mode mode; | |
34 | dma_addr_t addr; | |
35 | u32 strength; | |
36 | u32 sectors; | |
37 | u32 len; | |
38 | }; | |
39 | ||
40 | int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32); | |
41 | void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int); | |
42 | int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation); | |
43 | int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *); | |
44 | void mtk_ecc_disable(struct mtk_ecc *); | |
45 | void mtk_ecc_adjust_strength(u32 *); | |
46 | ||
47 | struct mtk_ecc *of_mtk_ecc_get(struct device_node *); | |
48 | void mtk_ecc_release(struct mtk_ecc *); | |
49 | ||
50 | #endif |