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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand.c | |
3 | * | |
4 | * Overview: | |
5 | * This is the generic MTD driver for NAND flash devices. It should be | |
6 | * capable of working with almost all NAND chips currently available. | |
7 | * Basic support for AG-AND chips is provided. | |
61b03bd7 | 8 | * |
1da177e4 | 9 | * Additional technical information is available on |
8b2b403c | 10 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 11 | * |
1da177e4 | 12 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 13 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 14 | * |
ace4dfee | 15 | * Credits: |
61b03bd7 TG |
16 | * David Woodhouse for adding multichip support |
17 | * | |
1da177e4 LT |
18 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
19 | * rework for 2K page size chips | |
20 | * | |
ace4dfee | 21 | * TODO: |
1da177e4 LT |
22 | * Enable cached programming for 2k page size chips |
23 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
7854d3f7 | 24 | * if we have HW ECC support. |
1da177e4 LT |
25 | * The AG-AND chips have nice features for speed improvement, |
26 | * which are not supported yet. Read / program 4 pages in one go. | |
c0b8ba7b | 27 | * BBT table is not serialized, has to be fixed |
1da177e4 | 28 | * |
1da177e4 LT |
29 | * This program is free software; you can redistribute it and/or modify |
30 | * it under the terms of the GNU General Public License version 2 as | |
31 | * published by the Free Software Foundation. | |
32 | * | |
33 | */ | |
34 | ||
552d9205 | 35 | #include <linux/module.h> |
1da177e4 LT |
36 | #include <linux/delay.h> |
37 | #include <linux/errno.h> | |
7aa65bfd | 38 | #include <linux/err.h> |
1da177e4 LT |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
41 | #include <linux/types.h> | |
42 | #include <linux/mtd/mtd.h> | |
43 | #include <linux/mtd/nand.h> | |
44 | #include <linux/mtd/nand_ecc.h> | |
193bd400 | 45 | #include <linux/mtd/nand_bch.h> |
1da177e4 LT |
46 | #include <linux/interrupt.h> |
47 | #include <linux/bitops.h> | |
8fe833c1 | 48 | #include <linux/leds.h> |
7351d3a5 | 49 | #include <linux/io.h> |
1da177e4 | 50 | #include <linux/mtd/partitions.h> |
1da177e4 LT |
51 | |
52 | /* Define default oob placement schemes for large and small page devices */ | |
5bd34c09 | 53 | static struct nand_ecclayout nand_oob_8 = { |
1da177e4 LT |
54 | .eccbytes = 3, |
55 | .eccpos = {0, 1, 2}, | |
5bd34c09 TG |
56 | .oobfree = { |
57 | {.offset = 3, | |
58 | .length = 2}, | |
59 | {.offset = 6, | |
f8ac0414 | 60 | .length = 2} } |
1da177e4 LT |
61 | }; |
62 | ||
5bd34c09 | 63 | static struct nand_ecclayout nand_oob_16 = { |
1da177e4 LT |
64 | .eccbytes = 6, |
65 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
5bd34c09 TG |
66 | .oobfree = { |
67 | {.offset = 8, | |
f8ac0414 | 68 | . length = 8} } |
1da177e4 LT |
69 | }; |
70 | ||
5bd34c09 | 71 | static struct nand_ecclayout nand_oob_64 = { |
1da177e4 LT |
72 | .eccbytes = 24, |
73 | .eccpos = { | |
e0c7d767 DW |
74 | 40, 41, 42, 43, 44, 45, 46, 47, |
75 | 48, 49, 50, 51, 52, 53, 54, 55, | |
76 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
5bd34c09 TG |
77 | .oobfree = { |
78 | {.offset = 2, | |
f8ac0414 | 79 | .length = 38} } |
1da177e4 LT |
80 | }; |
81 | ||
81ec5364 TG |
82 | static struct nand_ecclayout nand_oob_128 = { |
83 | .eccbytes = 48, | |
84 | .eccpos = { | |
85 | 80, 81, 82, 83, 84, 85, 86, 87, | |
86 | 88, 89, 90, 91, 92, 93, 94, 95, | |
87 | 96, 97, 98, 99, 100, 101, 102, 103, | |
88 | 104, 105, 106, 107, 108, 109, 110, 111, | |
89 | 112, 113, 114, 115, 116, 117, 118, 119, | |
90 | 120, 121, 122, 123, 124, 125, 126, 127}, | |
91 | .oobfree = { | |
92 | {.offset = 2, | |
f8ac0414 | 93 | .length = 78} } |
81ec5364 TG |
94 | }; |
95 | ||
6a8214aa | 96 | static int nand_get_device(struct mtd_info *mtd, int new_state); |
1da177e4 | 97 | |
8593fbc6 TG |
98 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
99 | struct mtd_oob_ops *ops); | |
100 | ||
d470a97c | 101 | /* |
8e87d782 | 102 | * For devices which display every fart in the system on a separate LED. Is |
d470a97c TG |
103 | * compiled away when LED support is disabled. |
104 | */ | |
105 | DEFINE_LED_TRIGGER(nand_led_trigger); | |
106 | ||
6fe5a6ac VS |
107 | static int check_offs_len(struct mtd_info *mtd, |
108 | loff_t ofs, uint64_t len) | |
109 | { | |
110 | struct nand_chip *chip = mtd->priv; | |
111 | int ret = 0; | |
112 | ||
113 | /* Start address must align on block boundary */ | |
114 | if (ofs & ((1 << chip->phys_erase_shift) - 1)) { | |
289c0522 | 115 | pr_debug("%s: unaligned address\n", __func__); |
6fe5a6ac VS |
116 | ret = -EINVAL; |
117 | } | |
118 | ||
119 | /* Length must align on block boundary */ | |
120 | if (len & ((1 << chip->phys_erase_shift) - 1)) { | |
289c0522 | 121 | pr_debug("%s: length not block aligned\n", __func__); |
6fe5a6ac VS |
122 | ret = -EINVAL; |
123 | } | |
124 | ||
6fe5a6ac VS |
125 | return ret; |
126 | } | |
127 | ||
1da177e4 LT |
128 | /** |
129 | * nand_release_device - [GENERIC] release chip | |
8b6e50c9 | 130 | * @mtd: MTD device structure |
61b03bd7 | 131 | * |
b0bb6903 | 132 | * Release chip lock and wake up anyone waiting on the device. |
1da177e4 | 133 | */ |
e0c7d767 | 134 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 135 | { |
ace4dfee | 136 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 137 | |
a36ed299 | 138 | /* Release the controller and the chip */ |
ace4dfee TG |
139 | spin_lock(&chip->controller->lock); |
140 | chip->controller->active = NULL; | |
141 | chip->state = FL_READY; | |
142 | wake_up(&chip->controller->wq); | |
143 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
144 | } |
145 | ||
146 | /** | |
147 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
8b6e50c9 | 148 | * @mtd: MTD device structure |
1da177e4 | 149 | * |
7854d3f7 | 150 | * Default read function for 8bit buswidth |
1da177e4 | 151 | */ |
58dd8f2b | 152 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 153 | { |
ace4dfee TG |
154 | struct nand_chip *chip = mtd->priv; |
155 | return readb(chip->IO_ADDR_R); | |
1da177e4 LT |
156 | } |
157 | ||
1da177e4 | 158 | /** |
064a7694 | 159 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
7854d3f7 | 160 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
8b6e50c9 | 161 | * @mtd: MTD device structure |
1da177e4 | 162 | * |
7854d3f7 BN |
163 | * Default read function for 16bit buswidth with endianness conversion. |
164 | * | |
1da177e4 | 165 | */ |
58dd8f2b | 166 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 167 | { |
ace4dfee TG |
168 | struct nand_chip *chip = mtd->priv; |
169 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); | |
1da177e4 LT |
170 | } |
171 | ||
1da177e4 LT |
172 | /** |
173 | * nand_read_word - [DEFAULT] read one word from the chip | |
8b6e50c9 | 174 | * @mtd: MTD device structure |
1da177e4 | 175 | * |
7854d3f7 | 176 | * Default read function for 16bit buswidth without endianness conversion. |
1da177e4 LT |
177 | */ |
178 | static u16 nand_read_word(struct mtd_info *mtd) | |
179 | { | |
ace4dfee TG |
180 | struct nand_chip *chip = mtd->priv; |
181 | return readw(chip->IO_ADDR_R); | |
1da177e4 LT |
182 | } |
183 | ||
1da177e4 LT |
184 | /** |
185 | * nand_select_chip - [DEFAULT] control CE line | |
8b6e50c9 BN |
186 | * @mtd: MTD device structure |
187 | * @chipnr: chipnumber to select, -1 for deselect | |
1da177e4 LT |
188 | * |
189 | * Default select function for 1 chip devices. | |
190 | */ | |
ace4dfee | 191 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 192 | { |
ace4dfee TG |
193 | struct nand_chip *chip = mtd->priv; |
194 | ||
195 | switch (chipnr) { | |
1da177e4 | 196 | case -1: |
ace4dfee | 197 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
198 | break; |
199 | case 0: | |
1da177e4 LT |
200 | break; |
201 | ||
202 | default: | |
203 | BUG(); | |
204 | } | |
205 | } | |
206 | ||
207 | /** | |
208 | * nand_write_buf - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
209 | * @mtd: MTD device structure |
210 | * @buf: data buffer | |
211 | * @len: number of bytes to write | |
1da177e4 | 212 | * |
7854d3f7 | 213 | * Default write function for 8bit buswidth. |
1da177e4 | 214 | */ |
58dd8f2b | 215 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
216 | { |
217 | int i; | |
ace4dfee | 218 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 219 | |
e0c7d767 | 220 | for (i = 0; i < len; i++) |
ace4dfee | 221 | writeb(buf[i], chip->IO_ADDR_W); |
1da177e4 LT |
222 | } |
223 | ||
224 | /** | |
61b03bd7 | 225 | * nand_read_buf - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
226 | * @mtd: MTD device structure |
227 | * @buf: buffer to store date | |
228 | * @len: number of bytes to read | |
1da177e4 | 229 | * |
7854d3f7 | 230 | * Default read function for 8bit buswidth. |
1da177e4 | 231 | */ |
58dd8f2b | 232 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
233 | { |
234 | int i; | |
ace4dfee | 235 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 236 | |
e0c7d767 | 237 | for (i = 0; i < len; i++) |
ace4dfee | 238 | buf[i] = readb(chip->IO_ADDR_R); |
1da177e4 LT |
239 | } |
240 | ||
1da177e4 LT |
241 | /** |
242 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
243 | * @mtd: MTD device structure |
244 | * @buf: data buffer | |
245 | * @len: number of bytes to write | |
1da177e4 | 246 | * |
7854d3f7 | 247 | * Default write function for 16bit buswidth. |
1da177e4 | 248 | */ |
58dd8f2b | 249 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
250 | { |
251 | int i; | |
ace4dfee | 252 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
253 | u16 *p = (u16 *) buf; |
254 | len >>= 1; | |
61b03bd7 | 255 | |
e0c7d767 | 256 | for (i = 0; i < len; i++) |
ace4dfee | 257 | writew(p[i], chip->IO_ADDR_W); |
61b03bd7 | 258 | |
1da177e4 LT |
259 | } |
260 | ||
261 | /** | |
61b03bd7 | 262 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
263 | * @mtd: MTD device structure |
264 | * @buf: buffer to store date | |
265 | * @len: number of bytes to read | |
1da177e4 | 266 | * |
7854d3f7 | 267 | * Default read function for 16bit buswidth. |
1da177e4 | 268 | */ |
58dd8f2b | 269 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
270 | { |
271 | int i; | |
ace4dfee | 272 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
273 | u16 *p = (u16 *) buf; |
274 | len >>= 1; | |
275 | ||
e0c7d767 | 276 | for (i = 0; i < len; i++) |
ace4dfee | 277 | p[i] = readw(chip->IO_ADDR_R); |
1da177e4 LT |
278 | } |
279 | ||
1da177e4 LT |
280 | /** |
281 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
8b6e50c9 BN |
282 | * @mtd: MTD device structure |
283 | * @ofs: offset from device start | |
284 | * @getchip: 0, if the chip is already selected | |
1da177e4 | 285 | * |
61b03bd7 | 286 | * Check, if the block is bad. |
1da177e4 LT |
287 | */ |
288 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) | |
289 | { | |
cdbec050 | 290 | int page, chipnr, res = 0, i = 0; |
ace4dfee | 291 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
292 | u16 bad; |
293 | ||
5fb1549d | 294 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
295 | ofs += mtd->erasesize - mtd->writesize; |
296 | ||
1a12f46a TK |
297 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
298 | ||
1da177e4 | 299 | if (getchip) { |
ace4dfee | 300 | chipnr = (int)(ofs >> chip->chip_shift); |
1da177e4 | 301 | |
6a8214aa | 302 | nand_get_device(mtd, FL_READING); |
1da177e4 LT |
303 | |
304 | /* Select the NAND device */ | |
ace4dfee | 305 | chip->select_chip(mtd, chipnr); |
1a12f46a | 306 | } |
1da177e4 | 307 | |
cdbec050 BN |
308 | do { |
309 | if (chip->options & NAND_BUSWIDTH_16) { | |
310 | chip->cmdfunc(mtd, NAND_CMD_READOOB, | |
311 | chip->badblockpos & 0xFE, page); | |
312 | bad = cpu_to_le16(chip->read_word(mtd)); | |
313 | if (chip->badblockpos & 0x1) | |
314 | bad >>= 8; | |
315 | else | |
316 | bad &= 0xFF; | |
317 | } else { | |
318 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, | |
319 | page); | |
320 | bad = chip->read_byte(mtd); | |
321 | } | |
322 | ||
323 | if (likely(chip->badblockbits == 8)) | |
324 | res = bad != 0xFF; | |
e0b58d0a | 325 | else |
cdbec050 BN |
326 | res = hweight8(bad) < chip->badblockbits; |
327 | ofs += mtd->writesize; | |
328 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; | |
329 | i++; | |
330 | } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); | |
e0b58d0a | 331 | |
b0bb6903 HS |
332 | if (getchip) { |
333 | chip->select_chip(mtd, -1); | |
1da177e4 | 334 | nand_release_device(mtd); |
b0bb6903 | 335 | } |
61b03bd7 | 336 | |
1da177e4 LT |
337 | return res; |
338 | } | |
339 | ||
340 | /** | |
341 | * nand_default_block_markbad - [DEFAULT] mark a block bad | |
8b6e50c9 BN |
342 | * @mtd: MTD device structure |
343 | * @ofs: offset from device start | |
1da177e4 | 344 | * |
8b6e50c9 | 345 | * This is the default implementation, which can be overridden by a hardware |
e2414f4c BN |
346 | * specific driver. We try operations in the following order, according to our |
347 | * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH): | |
348 | * (1) erase the affected block, to allow OOB marker to be written cleanly | |
349 | * (2) update in-memory BBT | |
350 | * (3) write bad block marker to OOB area of affected block | |
351 | * (4) update flash-based BBT | |
352 | * Note that we retain the first error encountered in (3) or (4), finish the | |
353 | * procedures, and dump the error in the end. | |
1da177e4 LT |
354 | */ |
355 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
356 | { | |
ace4dfee | 357 | struct nand_chip *chip = mtd->priv; |
58dd8f2b | 358 | uint8_t buf[2] = { 0, 0 }; |
e2414f4c BN |
359 | int block, res, ret = 0, i = 0; |
360 | int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM); | |
61b03bd7 | 361 | |
e2414f4c | 362 | if (write_oob) { |
00918429 BN |
363 | struct erase_info einfo; |
364 | ||
365 | /* Attempt erase before marking OOB */ | |
366 | memset(&einfo, 0, sizeof(einfo)); | |
367 | einfo.mtd = mtd; | |
368 | einfo.addr = ofs; | |
369 | einfo.len = 1 << chip->phys_erase_shift; | |
370 | nand_erase_nand(mtd, &einfo, 0); | |
371 | } | |
372 | ||
1da177e4 | 373 | /* Get block number */ |
4226b510 | 374 | block = (int)(ofs >> chip->bbt_erase_shift); |
e2414f4c | 375 | /* Mark block bad in memory-based BBT */ |
ace4dfee TG |
376 | if (chip->bbt) |
377 | chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); | |
1da177e4 | 378 | |
e2414f4c BN |
379 | /* Write bad block marker to OOB */ |
380 | if (write_oob) { | |
4a89ff88 | 381 | struct mtd_oob_ops ops; |
df698621 | 382 | loff_t wr_ofs = ofs; |
4a89ff88 | 383 | |
6a8214aa | 384 | nand_get_device(mtd, FL_WRITING); |
f1a28c02 | 385 | |
4a89ff88 BN |
386 | ops.datbuf = NULL; |
387 | ops.oobbuf = buf; | |
85443319 BN |
388 | ops.ooboffs = chip->badblockpos; |
389 | if (chip->options & NAND_BUSWIDTH_16) { | |
390 | ops.ooboffs &= ~0x01; | |
391 | ops.len = ops.ooblen = 2; | |
392 | } else { | |
393 | ops.len = ops.ooblen = 1; | |
394 | } | |
23b1a99b | 395 | ops.mode = MTD_OPS_PLACE_OOB; |
df698621 | 396 | |
e2414f4c | 397 | /* Write to first/last page(s) if necessary */ |
df698621 BN |
398 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
399 | wr_ofs += mtd->erasesize - mtd->writesize; | |
02ed70bb | 400 | do { |
e2414f4c BN |
401 | res = nand_do_write_oob(mtd, wr_ofs, &ops); |
402 | if (!ret) | |
403 | ret = res; | |
02ed70bb | 404 | |
02ed70bb | 405 | i++; |
df698621 | 406 | wr_ofs += mtd->writesize; |
e2414f4c | 407 | } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); |
02ed70bb | 408 | |
c0b8ba7b | 409 | nand_release_device(mtd); |
f1a28c02 | 410 | } |
e2414f4c BN |
411 | |
412 | /* Update flash-based bad block table */ | |
413 | if (chip->bbt_options & NAND_BBT_USE_FLASH) { | |
414 | res = nand_update_bbt(mtd, ofs); | |
415 | if (!ret) | |
416 | ret = res; | |
417 | } | |
418 | ||
f1a28c02 TG |
419 | if (!ret) |
420 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 421 | |
f1a28c02 | 422 | return ret; |
1da177e4 LT |
423 | } |
424 | ||
61b03bd7 | 425 | /** |
1da177e4 | 426 | * nand_check_wp - [GENERIC] check if the chip is write protected |
8b6e50c9 | 427 | * @mtd: MTD device structure |
1da177e4 | 428 | * |
8b6e50c9 BN |
429 | * Check, if the device is write protected. The function expects, that the |
430 | * device is already selected. | |
1da177e4 | 431 | */ |
e0c7d767 | 432 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 433 | { |
ace4dfee | 434 | struct nand_chip *chip = mtd->priv; |
93edbad6 | 435 | |
8b6e50c9 | 436 | /* Broken xD cards report WP despite being writable */ |
93edbad6 ML |
437 | if (chip->options & NAND_BROKEN_XD) |
438 | return 0; | |
439 | ||
1da177e4 | 440 | /* Check the WP bit */ |
ace4dfee TG |
441 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
442 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
443 | } |
444 | ||
445 | /** | |
446 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
8b6e50c9 BN |
447 | * @mtd: MTD device structure |
448 | * @ofs: offset from device start | |
449 | * @getchip: 0, if the chip is already selected | |
450 | * @allowbbt: 1, if its allowed to access the bbt area | |
1da177e4 LT |
451 | * |
452 | * Check, if the block is bad. Either by reading the bad block table or | |
453 | * calling of the scan function. | |
454 | */ | |
2c0a2bed TG |
455 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, |
456 | int allowbbt) | |
1da177e4 | 457 | { |
ace4dfee | 458 | struct nand_chip *chip = mtd->priv; |
61b03bd7 | 459 | |
ace4dfee TG |
460 | if (!chip->bbt) |
461 | return chip->block_bad(mtd, ofs, getchip); | |
61b03bd7 | 462 | |
1da177e4 | 463 | /* Return info from the table */ |
e0c7d767 | 464 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
465 | } |
466 | ||
2af7c653 SK |
467 | /** |
468 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
8b6e50c9 BN |
469 | * @mtd: MTD device structure |
470 | * @timeo: Timeout | |
2af7c653 SK |
471 | * |
472 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
473 | * context. | |
474 | */ | |
475 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
476 | { | |
477 | struct nand_chip *chip = mtd->priv; | |
478 | int i; | |
479 | ||
480 | /* Wait for the device to get ready */ | |
481 | for (i = 0; i < timeo; i++) { | |
482 | if (chip->dev_ready(mtd)) | |
483 | break; | |
484 | touch_softlockup_watchdog(); | |
485 | mdelay(1); | |
486 | } | |
487 | } | |
488 | ||
7854d3f7 | 489 | /* Wait for the ready pin, after a command. The timeout is caught later. */ |
4b648b02 | 490 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 491 | { |
ace4dfee | 492 | struct nand_chip *chip = mtd->priv; |
ca6a2489 | 493 | unsigned long timeo = jiffies + msecs_to_jiffies(20); |
3b88775c | 494 | |
2af7c653 SK |
495 | /* 400ms timeout */ |
496 | if (in_interrupt() || oops_in_progress) | |
497 | return panic_nand_wait_ready(mtd, 400); | |
498 | ||
8fe833c1 | 499 | led_trigger_event(nand_led_trigger, LED_FULL); |
7854d3f7 | 500 | /* Wait until command is processed or timeout occurs */ |
3b88775c | 501 | do { |
ace4dfee | 502 | if (chip->dev_ready(mtd)) |
8fe833c1 | 503 | break; |
8446f1d3 | 504 | touch_softlockup_watchdog(); |
61b03bd7 | 505 | } while (time_before(jiffies, timeo)); |
8fe833c1 | 506 | led_trigger_event(nand_led_trigger, LED_OFF); |
3b88775c | 507 | } |
4b648b02 | 508 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 509 | |
1da177e4 LT |
510 | /** |
511 | * nand_command - [DEFAULT] Send command to NAND device | |
8b6e50c9 BN |
512 | * @mtd: MTD device structure |
513 | * @command: the command to be sent | |
514 | * @column: the column address for this command, -1 if none | |
515 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 516 | * |
8b6e50c9 BN |
517 | * Send command to NAND device. This function is used for small page devices |
518 | * (256/512 Bytes per page). | |
1da177e4 | 519 | */ |
7abd3ef9 TG |
520 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
521 | int column, int page_addr) | |
1da177e4 | 522 | { |
ace4dfee | 523 | register struct nand_chip *chip = mtd->priv; |
7abd3ef9 | 524 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 525 | |
8b6e50c9 | 526 | /* Write out the command to the device */ |
1da177e4 LT |
527 | if (command == NAND_CMD_SEQIN) { |
528 | int readcmd; | |
529 | ||
28318776 | 530 | if (column >= mtd->writesize) { |
1da177e4 | 531 | /* OOB area */ |
28318776 | 532 | column -= mtd->writesize; |
1da177e4 LT |
533 | readcmd = NAND_CMD_READOOB; |
534 | } else if (column < 256) { | |
535 | /* First 256 bytes --> READ0 */ | |
536 | readcmd = NAND_CMD_READ0; | |
537 | } else { | |
538 | column -= 256; | |
539 | readcmd = NAND_CMD_READ1; | |
540 | } | |
ace4dfee | 541 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 542 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 543 | } |
ace4dfee | 544 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 545 | |
8b6e50c9 | 546 | /* Address cycle, when necessary */ |
7abd3ef9 TG |
547 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; |
548 | /* Serially input address */ | |
549 | if (column != -1) { | |
550 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 551 | if (chip->options & NAND_BUSWIDTH_16) |
7abd3ef9 | 552 | column >>= 1; |
ace4dfee | 553 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
554 | ctrl &= ~NAND_CTRL_CHANGE; |
555 | } | |
556 | if (page_addr != -1) { | |
ace4dfee | 557 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 558 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 559 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 560 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
561 | if (chip->chipsize > (32 << 20)) |
562 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 563 | } |
ace4dfee | 564 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
565 | |
566 | /* | |
8b6e50c9 BN |
567 | * Program and erase have their own busy handlers status and sequential |
568 | * in needs no delay | |
e0c7d767 | 569 | */ |
1da177e4 | 570 | switch (command) { |
61b03bd7 | 571 | |
1da177e4 LT |
572 | case NAND_CMD_PAGEPROG: |
573 | case NAND_CMD_ERASE1: | |
574 | case NAND_CMD_ERASE2: | |
575 | case NAND_CMD_SEQIN: | |
576 | case NAND_CMD_STATUS: | |
577 | return; | |
578 | ||
579 | case NAND_CMD_RESET: | |
ace4dfee | 580 | if (chip->dev_ready) |
1da177e4 | 581 | break; |
ace4dfee TG |
582 | udelay(chip->chip_delay); |
583 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 584 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
585 | chip->cmd_ctrl(mtd, |
586 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
587 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
588 | ; | |
1da177e4 LT |
589 | return; |
590 | ||
e0c7d767 | 591 | /* This applies to read commands */ |
1da177e4 | 592 | default: |
61b03bd7 | 593 | /* |
1da177e4 LT |
594 | * If we don't have access to the busy pin, we apply the given |
595 | * command delay | |
e0c7d767 | 596 | */ |
ace4dfee TG |
597 | if (!chip->dev_ready) { |
598 | udelay(chip->chip_delay); | |
1da177e4 | 599 | return; |
61b03bd7 | 600 | } |
1da177e4 | 601 | } |
8b6e50c9 BN |
602 | /* |
603 | * Apply this short delay always to ensure that we do wait tWB in | |
604 | * any case on any machine. | |
605 | */ | |
e0c7d767 | 606 | ndelay(100); |
3b88775c TG |
607 | |
608 | nand_wait_ready(mtd); | |
1da177e4 LT |
609 | } |
610 | ||
611 | /** | |
612 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
8b6e50c9 BN |
613 | * @mtd: MTD device structure |
614 | * @command: the command to be sent | |
615 | * @column: the column address for this command, -1 if none | |
616 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 617 | * |
7abd3ef9 | 618 | * Send command to NAND device. This is the version for the new large page |
7854d3f7 BN |
619 | * devices. We don't have the separate regions as we have in the small page |
620 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 621 | */ |
7abd3ef9 TG |
622 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
623 | int column, int page_addr) | |
1da177e4 | 624 | { |
ace4dfee | 625 | register struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
626 | |
627 | /* Emulate NAND_CMD_READOOB */ | |
628 | if (command == NAND_CMD_READOOB) { | |
28318776 | 629 | column += mtd->writesize; |
1da177e4 LT |
630 | command = NAND_CMD_READ0; |
631 | } | |
61b03bd7 | 632 | |
7abd3ef9 | 633 | /* Command latch cycle */ |
ace4dfee | 634 | chip->cmd_ctrl(mtd, command & 0xff, |
7abd3ef9 | 635 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
636 | |
637 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 638 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
639 | |
640 | /* Serially input address */ | |
641 | if (column != -1) { | |
642 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 643 | if (chip->options & NAND_BUSWIDTH_16) |
1da177e4 | 644 | column >>= 1; |
ace4dfee | 645 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 646 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 647 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 648 | } |
1da177e4 | 649 | if (page_addr != -1) { |
ace4dfee TG |
650 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
651 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 652 | NAND_NCE | NAND_ALE); |
1da177e4 | 653 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
654 | if (chip->chipsize > (128 << 20)) |
655 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 656 | NAND_NCE | NAND_ALE); |
1da177e4 | 657 | } |
1da177e4 | 658 | } |
ace4dfee | 659 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
660 | |
661 | /* | |
8b6e50c9 BN |
662 | * Program and erase have their own busy handlers status, sequential |
663 | * in, and deplete1 need no delay. | |
30f464b7 | 664 | */ |
1da177e4 | 665 | switch (command) { |
61b03bd7 | 666 | |
1da177e4 LT |
667 | case NAND_CMD_CACHEDPROG: |
668 | case NAND_CMD_PAGEPROG: | |
669 | case NAND_CMD_ERASE1: | |
670 | case NAND_CMD_ERASE2: | |
671 | case NAND_CMD_SEQIN: | |
7bc3312b | 672 | case NAND_CMD_RNDIN: |
1da177e4 | 673 | case NAND_CMD_STATUS: |
30f464b7 | 674 | case NAND_CMD_DEPLETE1: |
1da177e4 LT |
675 | return; |
676 | ||
30f464b7 DM |
677 | case NAND_CMD_STATUS_ERROR: |
678 | case NAND_CMD_STATUS_ERROR0: | |
679 | case NAND_CMD_STATUS_ERROR1: | |
680 | case NAND_CMD_STATUS_ERROR2: | |
681 | case NAND_CMD_STATUS_ERROR3: | |
8b6e50c9 | 682 | /* Read error status commands require only a short delay */ |
ace4dfee | 683 | udelay(chip->chip_delay); |
30f464b7 | 684 | return; |
1da177e4 LT |
685 | |
686 | case NAND_CMD_RESET: | |
ace4dfee | 687 | if (chip->dev_ready) |
1da177e4 | 688 | break; |
ace4dfee | 689 | udelay(chip->chip_delay); |
12efdde3 TG |
690 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
691 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
692 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
693 | NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
694 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
695 | ; | |
1da177e4 LT |
696 | return; |
697 | ||
7bc3312b TG |
698 | case NAND_CMD_RNDOUT: |
699 | /* No ready / busy check necessary */ | |
700 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
701 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
702 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
703 | NAND_NCE | NAND_CTRL_CHANGE); | |
704 | return; | |
705 | ||
1da177e4 | 706 | case NAND_CMD_READ0: |
12efdde3 TG |
707 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
708 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
709 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
710 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 711 | |
e0c7d767 | 712 | /* This applies to read commands */ |
1da177e4 | 713 | default: |
61b03bd7 | 714 | /* |
1da177e4 | 715 | * If we don't have access to the busy pin, we apply the given |
8b6e50c9 | 716 | * command delay. |
e0c7d767 | 717 | */ |
ace4dfee TG |
718 | if (!chip->dev_ready) { |
719 | udelay(chip->chip_delay); | |
1da177e4 | 720 | return; |
61b03bd7 | 721 | } |
1da177e4 | 722 | } |
3b88775c | 723 | |
8b6e50c9 BN |
724 | /* |
725 | * Apply this short delay always to ensure that we do wait tWB in | |
726 | * any case on any machine. | |
727 | */ | |
e0c7d767 | 728 | ndelay(100); |
3b88775c TG |
729 | |
730 | nand_wait_ready(mtd); | |
1da177e4 LT |
731 | } |
732 | ||
2af7c653 SK |
733 | /** |
734 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
735 | * @chip: the nand chip descriptor |
736 | * @mtd: MTD device structure | |
737 | * @new_state: the state which is requested | |
2af7c653 SK |
738 | * |
739 | * Used when in panic, no locks are taken. | |
740 | */ | |
741 | static void panic_nand_get_device(struct nand_chip *chip, | |
742 | struct mtd_info *mtd, int new_state) | |
743 | { | |
7854d3f7 | 744 | /* Hardware controller shared among independent devices */ |
2af7c653 SK |
745 | chip->controller->active = chip; |
746 | chip->state = new_state; | |
747 | } | |
748 | ||
1da177e4 LT |
749 | /** |
750 | * nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
751 | * @mtd: MTD device structure |
752 | * @new_state: the state which is requested | |
1da177e4 LT |
753 | * |
754 | * Get the device and lock it for exclusive access | |
755 | */ | |
2c0a2bed | 756 | static int |
6a8214aa | 757 | nand_get_device(struct mtd_info *mtd, int new_state) |
1da177e4 | 758 | { |
6a8214aa | 759 | struct nand_chip *chip = mtd->priv; |
ace4dfee TG |
760 | spinlock_t *lock = &chip->controller->lock; |
761 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 762 | DECLARE_WAITQUEUE(wait, current); |
7351d3a5 | 763 | retry: |
0dfc6246 TG |
764 | spin_lock(lock); |
765 | ||
b8b3ee9a | 766 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
767 | if (!chip->controller->active) |
768 | chip->controller->active = chip; | |
a36ed299 | 769 | |
ace4dfee TG |
770 | if (chip->controller->active == chip && chip->state == FL_READY) { |
771 | chip->state = new_state; | |
0dfc6246 | 772 | spin_unlock(lock); |
962034f4 VW |
773 | return 0; |
774 | } | |
775 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
776 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
777 | chip->state = FL_PM_SUSPENDED; | |
778 | spin_unlock(lock); | |
779 | return 0; | |
6b0d9a84 | 780 | } |
0dfc6246 TG |
781 | } |
782 | set_current_state(TASK_UNINTERRUPTIBLE); | |
783 | add_wait_queue(wq, &wait); | |
784 | spin_unlock(lock); | |
785 | schedule(); | |
786 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
787 | goto retry; |
788 | } | |
789 | ||
2af7c653 | 790 | /** |
8b6e50c9 BN |
791 | * panic_nand_wait - [GENERIC] wait until the command is done |
792 | * @mtd: MTD device structure | |
793 | * @chip: NAND chip structure | |
794 | * @timeo: timeout | |
2af7c653 SK |
795 | * |
796 | * Wait for command done. This is a helper function for nand_wait used when | |
797 | * we are in interrupt context. May happen when in panic and trying to write | |
b595076a | 798 | * an oops through mtdoops. |
2af7c653 SK |
799 | */ |
800 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
801 | unsigned long timeo) | |
802 | { | |
803 | int i; | |
804 | for (i = 0; i < timeo; i++) { | |
805 | if (chip->dev_ready) { | |
806 | if (chip->dev_ready(mtd)) | |
807 | break; | |
808 | } else { | |
809 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
810 | break; | |
811 | } | |
812 | mdelay(1); | |
f8ac0414 | 813 | } |
2af7c653 SK |
814 | } |
815 | ||
1da177e4 | 816 | /** |
8b6e50c9 BN |
817 | * nand_wait - [DEFAULT] wait until the command is done |
818 | * @mtd: MTD device structure | |
819 | * @chip: NAND chip structure | |
1da177e4 | 820 | * |
8b6e50c9 BN |
821 | * Wait for command done. This applies to erase and program only. Erase can |
822 | * take up to 400ms and program up to 20ms according to general NAND and | |
823 | * SmartMedia specs. | |
844d3b42 | 824 | */ |
7bc3312b | 825 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
826 | { |
827 | ||
7bc3312b | 828 | int status, state = chip->state; |
6d2559f8 | 829 | unsigned long timeo = (state == FL_ERASING ? 400 : 20); |
1da177e4 | 830 | |
8fe833c1 RP |
831 | led_trigger_event(nand_led_trigger, LED_FULL); |
832 | ||
8b6e50c9 BN |
833 | /* |
834 | * Apply this short delay always to ensure that we do wait tWB in any | |
835 | * case on any machine. | |
836 | */ | |
e0c7d767 | 837 | ndelay(100); |
1da177e4 | 838 | |
ace4dfee TG |
839 | if ((state == FL_ERASING) && (chip->options & NAND_IS_AND)) |
840 | chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); | |
61b03bd7 | 841 | else |
ace4dfee | 842 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 843 | |
2af7c653 SK |
844 | if (in_interrupt() || oops_in_progress) |
845 | panic_nand_wait(mtd, chip, timeo); | |
846 | else { | |
6d2559f8 | 847 | timeo = jiffies + msecs_to_jiffies(timeo); |
2af7c653 SK |
848 | while (time_before(jiffies, timeo)) { |
849 | if (chip->dev_ready) { | |
850 | if (chip->dev_ready(mtd)) | |
851 | break; | |
852 | } else { | |
853 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
854 | break; | |
855 | } | |
856 | cond_resched(); | |
1da177e4 | 857 | } |
1da177e4 | 858 | } |
8fe833c1 RP |
859 | led_trigger_event(nand_led_trigger, LED_OFF); |
860 | ||
ace4dfee | 861 | status = (int)chip->read_byte(mtd); |
f251b8df MC |
862 | /* This can happen if in case of timeout or buggy dev_ready */ |
863 | WARN_ON(!(status & NAND_STATUS_READY)); | |
1da177e4 LT |
864 | return status; |
865 | } | |
866 | ||
7d70f334 | 867 | /** |
b6d676db | 868 | * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
869 | * @mtd: mtd info |
870 | * @ofs: offset to start unlock from | |
871 | * @len: length to unlock | |
8b6e50c9 BN |
872 | * @invert: when = 0, unlock the range of blocks within the lower and |
873 | * upper boundary address | |
874 | * when = 1, unlock the range of blocks outside the boundaries | |
875 | * of the lower and upper boundary address | |
7d70f334 | 876 | * |
8b6e50c9 | 877 | * Returs unlock status. |
7d70f334 VS |
878 | */ |
879 | static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, | |
880 | uint64_t len, int invert) | |
881 | { | |
882 | int ret = 0; | |
883 | int status, page; | |
884 | struct nand_chip *chip = mtd->priv; | |
885 | ||
886 | /* Submit address of first page to unlock */ | |
887 | page = ofs >> chip->page_shift; | |
888 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); | |
889 | ||
890 | /* Submit address of last page to unlock */ | |
891 | page = (ofs + len) >> chip->page_shift; | |
892 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, | |
893 | (page | invert) & chip->pagemask); | |
894 | ||
895 | /* Call wait ready function */ | |
896 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 897 | /* See if device thinks it succeeded */ |
74830966 | 898 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 899 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
900 | __func__, status); |
901 | ret = -EIO; | |
902 | } | |
903 | ||
904 | return ret; | |
905 | } | |
906 | ||
907 | /** | |
b6d676db | 908 | * nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
909 | * @mtd: mtd info |
910 | * @ofs: offset to start unlock from | |
911 | * @len: length to unlock | |
7d70f334 | 912 | * |
8b6e50c9 | 913 | * Returns unlock status. |
7d70f334 VS |
914 | */ |
915 | int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
916 | { | |
917 | int ret = 0; | |
918 | int chipnr; | |
919 | struct nand_chip *chip = mtd->priv; | |
920 | ||
289c0522 | 921 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
922 | __func__, (unsigned long long)ofs, len); |
923 | ||
924 | if (check_offs_len(mtd, ofs, len)) | |
925 | ret = -EINVAL; | |
926 | ||
927 | /* Align to last block address if size addresses end of the device */ | |
928 | if (ofs + len == mtd->size) | |
929 | len -= mtd->erasesize; | |
930 | ||
6a8214aa | 931 | nand_get_device(mtd, FL_UNLOCKING); |
7d70f334 VS |
932 | |
933 | /* Shift to get chip number */ | |
934 | chipnr = ofs >> chip->chip_shift; | |
935 | ||
936 | chip->select_chip(mtd, chipnr); | |
937 | ||
938 | /* Check, if it is write protected */ | |
939 | if (nand_check_wp(mtd)) { | |
289c0522 | 940 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
941 | __func__); |
942 | ret = -EIO; | |
943 | goto out; | |
944 | } | |
945 | ||
946 | ret = __nand_unlock(mtd, ofs, len, 0); | |
947 | ||
948 | out: | |
b0bb6903 | 949 | chip->select_chip(mtd, -1); |
7d70f334 VS |
950 | nand_release_device(mtd); |
951 | ||
952 | return ret; | |
953 | } | |
7351d3a5 | 954 | EXPORT_SYMBOL(nand_unlock); |
7d70f334 VS |
955 | |
956 | /** | |
b6d676db | 957 | * nand_lock - [REPLACEABLE] locks all blocks present in the device |
b6d676db RD |
958 | * @mtd: mtd info |
959 | * @ofs: offset to start unlock from | |
960 | * @len: length to unlock | |
7d70f334 | 961 | * |
8b6e50c9 BN |
962 | * This feature is not supported in many NAND parts. 'Micron' NAND parts do |
963 | * have this feature, but it allows only to lock all blocks, not for specified | |
964 | * range for block. Implementing 'lock' feature by making use of 'unlock', for | |
965 | * now. | |
7d70f334 | 966 | * |
8b6e50c9 | 967 | * Returns lock status. |
7d70f334 VS |
968 | */ |
969 | int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
970 | { | |
971 | int ret = 0; | |
972 | int chipnr, status, page; | |
973 | struct nand_chip *chip = mtd->priv; | |
974 | ||
289c0522 | 975 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
976 | __func__, (unsigned long long)ofs, len); |
977 | ||
978 | if (check_offs_len(mtd, ofs, len)) | |
979 | ret = -EINVAL; | |
980 | ||
6a8214aa | 981 | nand_get_device(mtd, FL_LOCKING); |
7d70f334 VS |
982 | |
983 | /* Shift to get chip number */ | |
984 | chipnr = ofs >> chip->chip_shift; | |
985 | ||
986 | chip->select_chip(mtd, chipnr); | |
987 | ||
988 | /* Check, if it is write protected */ | |
989 | if (nand_check_wp(mtd)) { | |
289c0522 | 990 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
991 | __func__); |
992 | status = MTD_ERASE_FAILED; | |
993 | ret = -EIO; | |
994 | goto out; | |
995 | } | |
996 | ||
997 | /* Submit address of first page to lock */ | |
998 | page = ofs >> chip->page_shift; | |
999 | chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); | |
1000 | ||
1001 | /* Call wait ready function */ | |
1002 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 1003 | /* See if device thinks it succeeded */ |
74830966 | 1004 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 1005 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
1006 | __func__, status); |
1007 | ret = -EIO; | |
1008 | goto out; | |
1009 | } | |
1010 | ||
1011 | ret = __nand_unlock(mtd, ofs, len, 0x1); | |
1012 | ||
1013 | out: | |
b0bb6903 | 1014 | chip->select_chip(mtd, -1); |
7d70f334 VS |
1015 | nand_release_device(mtd); |
1016 | ||
1017 | return ret; | |
1018 | } | |
7351d3a5 | 1019 | EXPORT_SYMBOL(nand_lock); |
7d70f334 | 1020 | |
8593fbc6 | 1021 | /** |
7854d3f7 | 1022 | * nand_read_page_raw - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1023 | * @mtd: mtd info structure |
1024 | * @chip: nand chip info structure | |
1025 | * @buf: buffer to store read data | |
1fbb938d | 1026 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1027 | * @page: page number to read |
52ff49df | 1028 | * |
7854d3f7 | 1029 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 TG |
1030 | */ |
1031 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1032 | uint8_t *buf, int oob_required, int page) |
8593fbc6 TG |
1033 | { |
1034 | chip->read_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
1035 | if (oob_required) |
1036 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
8593fbc6 TG |
1037 | return 0; |
1038 | } | |
1039 | ||
52ff49df | 1040 | /** |
7854d3f7 | 1041 | * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1042 | * @mtd: mtd info structure |
1043 | * @chip: nand chip info structure | |
1044 | * @buf: buffer to store read data | |
1fbb938d | 1045 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1046 | * @page: page number to read |
52ff49df DB |
1047 | * |
1048 | * We need a special oob layout and handling even when OOB isn't used. | |
1049 | */ | |
7351d3a5 | 1050 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
1051 | struct nand_chip *chip, uint8_t *buf, |
1052 | int oob_required, int page) | |
52ff49df DB |
1053 | { |
1054 | int eccsize = chip->ecc.size; | |
1055 | int eccbytes = chip->ecc.bytes; | |
1056 | uint8_t *oob = chip->oob_poi; | |
1057 | int steps, size; | |
1058 | ||
1059 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1060 | chip->read_buf(mtd, buf, eccsize); | |
1061 | buf += eccsize; | |
1062 | ||
1063 | if (chip->ecc.prepad) { | |
1064 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1065 | oob += chip->ecc.prepad; | |
1066 | } | |
1067 | ||
1068 | chip->read_buf(mtd, oob, eccbytes); | |
1069 | oob += eccbytes; | |
1070 | ||
1071 | if (chip->ecc.postpad) { | |
1072 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1073 | oob += chip->ecc.postpad; | |
1074 | } | |
1075 | } | |
1076 | ||
1077 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1078 | if (size) | |
1079 | chip->read_buf(mtd, oob, size); | |
1080 | ||
1081 | return 0; | |
1082 | } | |
1083 | ||
1da177e4 | 1084 | /** |
7854d3f7 | 1085 | * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function |
8b6e50c9 BN |
1086 | * @mtd: mtd info structure |
1087 | * @chip: nand chip info structure | |
1088 | * @buf: buffer to store read data | |
1fbb938d | 1089 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1090 | * @page: page number to read |
068e3c0a | 1091 | */ |
f5bbdacc | 1092 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1093 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1094 | { |
f5bbdacc TG |
1095 | int i, eccsize = chip->ecc.size; |
1096 | int eccbytes = chip->ecc.bytes; | |
1097 | int eccsteps = chip->ecc.steps; | |
1098 | uint8_t *p = buf; | |
4bf63fcb DW |
1099 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1100 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1101 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1102 | unsigned int max_bitflips = 0; |
f5bbdacc | 1103 | |
1fbb938d | 1104 | chip->ecc.read_page_raw(mtd, chip, buf, 1, page); |
f5bbdacc TG |
1105 | |
1106 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1107 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1108 | ||
1109 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 1110 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
1111 | |
1112 | eccsteps = chip->ecc.steps; | |
1113 | p = buf; | |
1114 | ||
1115 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1116 | int stat; | |
1117 | ||
1118 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
3f91e94f | 1119 | if (stat < 0) { |
f5bbdacc | 1120 | mtd->ecc_stats.failed++; |
3f91e94f | 1121 | } else { |
f5bbdacc | 1122 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1123 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1124 | } | |
f5bbdacc | 1125 | } |
3f91e94f | 1126 | return max_bitflips; |
22c60f5f | 1127 | } |
1da177e4 | 1128 | |
3d459559 | 1129 | /** |
7854d3f7 | 1130 | * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function |
8b6e50c9 BN |
1131 | * @mtd: mtd info structure |
1132 | * @chip: nand chip info structure | |
1133 | * @data_offs: offset of requested data within the page | |
1134 | * @readlen: data length | |
1135 | * @bufpoi: buffer to store read data | |
3d459559 | 1136 | */ |
7351d3a5 FF |
1137 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, |
1138 | uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi) | |
3d459559 AK |
1139 | { |
1140 | int start_step, end_step, num_steps; | |
1141 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1142 | uint8_t *p; | |
1143 | int data_col_addr, i, gaps = 0; | |
1144 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
1145 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
7351d3a5 | 1146 | int index = 0; |
3f91e94f | 1147 | unsigned int max_bitflips = 0; |
3d459559 | 1148 | |
7854d3f7 | 1149 | /* Column address within the page aligned to ECC size (256bytes) */ |
3d459559 AK |
1150 | start_step = data_offs / chip->ecc.size; |
1151 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
1152 | num_steps = end_step - start_step + 1; | |
1153 | ||
8b6e50c9 | 1154 | /* Data size aligned to ECC ecc.size */ |
3d459559 AK |
1155 | datafrag_len = num_steps * chip->ecc.size; |
1156 | eccfrag_len = num_steps * chip->ecc.bytes; | |
1157 | ||
1158 | data_col_addr = start_step * chip->ecc.size; | |
1159 | /* If we read not a page aligned data */ | |
1160 | if (data_col_addr != 0) | |
1161 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); | |
1162 | ||
1163 | p = bufpoi + data_col_addr; | |
1164 | chip->read_buf(mtd, p, datafrag_len); | |
1165 | ||
8b6e50c9 | 1166 | /* Calculate ECC */ |
3d459559 AK |
1167 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) |
1168 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); | |
1169 | ||
8b6e50c9 BN |
1170 | /* |
1171 | * The performance is faster if we position offsets according to | |
7854d3f7 | 1172 | * ecc.pos. Let's make sure that there are no gaps in ECC positions. |
8b6e50c9 | 1173 | */ |
3d459559 AK |
1174 | for (i = 0; i < eccfrag_len - 1; i++) { |
1175 | if (eccpos[i + start_step * chip->ecc.bytes] + 1 != | |
1176 | eccpos[i + start_step * chip->ecc.bytes + 1]) { | |
1177 | gaps = 1; | |
1178 | break; | |
1179 | } | |
1180 | } | |
1181 | if (gaps) { | |
1182 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1183 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1184 | } else { | |
8b6e50c9 | 1185 | /* |
7854d3f7 | 1186 | * Send the command to read the particular ECC bytes take care |
8b6e50c9 BN |
1187 | * about buswidth alignment in read_buf. |
1188 | */ | |
7351d3a5 FF |
1189 | index = start_step * chip->ecc.bytes; |
1190 | ||
1191 | aligned_pos = eccpos[index] & ~(busw - 1); | |
3d459559 | 1192 | aligned_len = eccfrag_len; |
7351d3a5 | 1193 | if (eccpos[index] & (busw - 1)) |
3d459559 | 1194 | aligned_len++; |
7351d3a5 | 1195 | if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1)) |
3d459559 AK |
1196 | aligned_len++; |
1197 | ||
7351d3a5 FF |
1198 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, |
1199 | mtd->writesize + aligned_pos, -1); | |
3d459559 AK |
1200 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); |
1201 | } | |
1202 | ||
1203 | for (i = 0; i < eccfrag_len; i++) | |
7351d3a5 | 1204 | chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]]; |
3d459559 AK |
1205 | |
1206 | p = bufpoi + data_col_addr; | |
1207 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
1208 | int stat; | |
1209 | ||
7351d3a5 FF |
1210 | stat = chip->ecc.correct(mtd, p, |
1211 | &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); | |
3f91e94f | 1212 | if (stat < 0) { |
3d459559 | 1213 | mtd->ecc_stats.failed++; |
3f91e94f | 1214 | } else { |
3d459559 | 1215 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1216 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1217 | } | |
3d459559 | 1218 | } |
3f91e94f | 1219 | return max_bitflips; |
3d459559 AK |
1220 | } |
1221 | ||
068e3c0a | 1222 | /** |
7854d3f7 | 1223 | * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function |
8b6e50c9 BN |
1224 | * @mtd: mtd info structure |
1225 | * @chip: nand chip info structure | |
1226 | * @buf: buffer to store read data | |
1fbb938d | 1227 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1228 | * @page: page number to read |
068e3c0a | 1229 | * |
7854d3f7 | 1230 | * Not for syndrome calculating ECC controllers which need a special oob layout. |
068e3c0a | 1231 | */ |
f5bbdacc | 1232 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1233 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1234 | { |
f5bbdacc TG |
1235 | int i, eccsize = chip->ecc.size; |
1236 | int eccbytes = chip->ecc.bytes; | |
1237 | int eccsteps = chip->ecc.steps; | |
1238 | uint8_t *p = buf; | |
4bf63fcb DW |
1239 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1240 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1241 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1242 | unsigned int max_bitflips = 0; |
f5bbdacc TG |
1243 | |
1244 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1245 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1246 | chip->read_buf(mtd, p, eccsize); | |
1247 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 1248 | } |
f75e5097 | 1249 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 1250 | |
f5bbdacc | 1251 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 1252 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 1253 | |
f5bbdacc TG |
1254 | eccsteps = chip->ecc.steps; |
1255 | p = buf; | |
61b03bd7 | 1256 | |
f5bbdacc TG |
1257 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1258 | int stat; | |
1da177e4 | 1259 | |
f5bbdacc | 1260 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
3f91e94f | 1261 | if (stat < 0) { |
f5bbdacc | 1262 | mtd->ecc_stats.failed++; |
3f91e94f | 1263 | } else { |
f5bbdacc | 1264 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1265 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1266 | } | |
f5bbdacc | 1267 | } |
3f91e94f | 1268 | return max_bitflips; |
f5bbdacc | 1269 | } |
1da177e4 | 1270 | |
6e0cb135 | 1271 | /** |
7854d3f7 | 1272 | * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first |
8b6e50c9 BN |
1273 | * @mtd: mtd info structure |
1274 | * @chip: nand chip info structure | |
1275 | * @buf: buffer to store read data | |
1fbb938d | 1276 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1277 | * @page: page number to read |
6e0cb135 | 1278 | * |
8b6e50c9 BN |
1279 | * Hardware ECC for large page chips, require OOB to be read first. For this |
1280 | * ECC mode, the write_page method is re-used from ECC_HW. These methods | |
1281 | * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with | |
1282 | * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from | |
1283 | * the data area, by overwriting the NAND manufacturer bad block markings. | |
6e0cb135 SN |
1284 | */ |
1285 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1fbb938d | 1286 | struct nand_chip *chip, uint8_t *buf, int oob_required, int page) |
6e0cb135 SN |
1287 | { |
1288 | int i, eccsize = chip->ecc.size; | |
1289 | int eccbytes = chip->ecc.bytes; | |
1290 | int eccsteps = chip->ecc.steps; | |
1291 | uint8_t *p = buf; | |
1292 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1293 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1294 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
3f91e94f | 1295 | unsigned int max_bitflips = 0; |
6e0cb135 SN |
1296 | |
1297 | /* Read the OOB area first */ | |
1298 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1299 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1300 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1301 | ||
1302 | for (i = 0; i < chip->ecc.total; i++) | |
1303 | ecc_code[i] = chip->oob_poi[eccpos[i]]; | |
1304 | ||
1305 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1306 | int stat; | |
1307 | ||
1308 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1309 | chip->read_buf(mtd, p, eccsize); | |
1310 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1311 | ||
1312 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
3f91e94f | 1313 | if (stat < 0) { |
6e0cb135 | 1314 | mtd->ecc_stats.failed++; |
3f91e94f | 1315 | } else { |
6e0cb135 | 1316 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1317 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1318 | } | |
6e0cb135 | 1319 | } |
3f91e94f | 1320 | return max_bitflips; |
6e0cb135 SN |
1321 | } |
1322 | ||
f5bbdacc | 1323 | /** |
7854d3f7 | 1324 | * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read |
8b6e50c9 BN |
1325 | * @mtd: mtd info structure |
1326 | * @chip: nand chip info structure | |
1327 | * @buf: buffer to store read data | |
1fbb938d | 1328 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1329 | * @page: page number to read |
f5bbdacc | 1330 | * |
8b6e50c9 BN |
1331 | * The hw generator calculates the error syndrome automatically. Therefore we |
1332 | * need a special oob layout and handling. | |
f5bbdacc TG |
1333 | */ |
1334 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1335 | uint8_t *buf, int oob_required, int page) |
f5bbdacc TG |
1336 | { |
1337 | int i, eccsize = chip->ecc.size; | |
1338 | int eccbytes = chip->ecc.bytes; | |
1339 | int eccsteps = chip->ecc.steps; | |
1340 | uint8_t *p = buf; | |
f75e5097 | 1341 | uint8_t *oob = chip->oob_poi; |
3f91e94f | 1342 | unsigned int max_bitflips = 0; |
1da177e4 | 1343 | |
f5bbdacc TG |
1344 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1345 | int stat; | |
61b03bd7 | 1346 | |
f5bbdacc TG |
1347 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
1348 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 1349 | |
f5bbdacc TG |
1350 | if (chip->ecc.prepad) { |
1351 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1352 | oob += chip->ecc.prepad; | |
1353 | } | |
1da177e4 | 1354 | |
f5bbdacc TG |
1355 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1356 | chip->read_buf(mtd, oob, eccbytes); | |
1357 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 1358 | |
3f91e94f | 1359 | if (stat < 0) { |
f5bbdacc | 1360 | mtd->ecc_stats.failed++; |
3f91e94f | 1361 | } else { |
f5bbdacc | 1362 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1363 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1364 | } | |
61b03bd7 | 1365 | |
f5bbdacc | 1366 | oob += eccbytes; |
1da177e4 | 1367 | |
f5bbdacc TG |
1368 | if (chip->ecc.postpad) { |
1369 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1370 | oob += chip->ecc.postpad; | |
61b03bd7 | 1371 | } |
f5bbdacc | 1372 | } |
1da177e4 | 1373 | |
f5bbdacc | 1374 | /* Calculate remaining oob bytes */ |
7e4178f9 | 1375 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
1376 | if (i) |
1377 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 1378 | |
3f91e94f | 1379 | return max_bitflips; |
f5bbdacc | 1380 | } |
1da177e4 | 1381 | |
f5bbdacc | 1382 | /** |
7854d3f7 | 1383 | * nand_transfer_oob - [INTERN] Transfer oob to client buffer |
8b6e50c9 BN |
1384 | * @chip: nand chip structure |
1385 | * @oob: oob destination address | |
1386 | * @ops: oob ops structure | |
1387 | * @len: size of oob to transfer | |
8593fbc6 TG |
1388 | */ |
1389 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, | |
7014568b | 1390 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 1391 | { |
f8ac0414 | 1392 | switch (ops->mode) { |
8593fbc6 | 1393 | |
0612b9dd BN |
1394 | case MTD_OPS_PLACE_OOB: |
1395 | case MTD_OPS_RAW: | |
8593fbc6 TG |
1396 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); |
1397 | return oob + len; | |
1398 | ||
0612b9dd | 1399 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 1400 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
1401 | uint32_t boffs = 0, roffs = ops->ooboffs; |
1402 | size_t bytes = 0; | |
8593fbc6 | 1403 | |
f8ac0414 | 1404 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 1405 | /* Read request not from offset 0? */ |
7bc3312b TG |
1406 | if (unlikely(roffs)) { |
1407 | if (roffs >= free->length) { | |
1408 | roffs -= free->length; | |
1409 | continue; | |
1410 | } | |
1411 | boffs = free->offset + roffs; | |
1412 | bytes = min_t(size_t, len, | |
1413 | (free->length - roffs)); | |
1414 | roffs = 0; | |
1415 | } else { | |
1416 | bytes = min_t(size_t, len, free->length); | |
1417 | boffs = free->offset; | |
1418 | } | |
1419 | memcpy(oob, chip->oob_poi + boffs, bytes); | |
8593fbc6 TG |
1420 | oob += bytes; |
1421 | } | |
1422 | return oob; | |
1423 | } | |
1424 | default: | |
1425 | BUG(); | |
1426 | } | |
1427 | return NULL; | |
1428 | } | |
1429 | ||
1430 | /** | |
7854d3f7 | 1431 | * nand_do_read_ops - [INTERN] Read data with ECC |
8b6e50c9 BN |
1432 | * @mtd: MTD device structure |
1433 | * @from: offset to read from | |
1434 | * @ops: oob ops structure | |
f5bbdacc TG |
1435 | * |
1436 | * Internal function. Called with chip held. | |
1437 | */ | |
8593fbc6 TG |
1438 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
1439 | struct mtd_oob_ops *ops) | |
f5bbdacc | 1440 | { |
e47f3db4 | 1441 | int chipnr, page, realpage, col, bytes, aligned, oob_required; |
f5bbdacc TG |
1442 | struct nand_chip *chip = mtd->priv; |
1443 | struct mtd_ecc_stats stats; | |
f5bbdacc | 1444 | int ret = 0; |
8593fbc6 | 1445 | uint32_t readlen = ops->len; |
7014568b | 1446 | uint32_t oobreadlen = ops->ooblen; |
0612b9dd | 1447 | uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ? |
9aca334e ML |
1448 | mtd->oobavail : mtd->oobsize; |
1449 | ||
8593fbc6 | 1450 | uint8_t *bufpoi, *oob, *buf; |
edbc4540 | 1451 | unsigned int max_bitflips = 0; |
1da177e4 | 1452 | |
f5bbdacc | 1453 | stats = mtd->ecc_stats; |
1da177e4 | 1454 | |
f5bbdacc TG |
1455 | chipnr = (int)(from >> chip->chip_shift); |
1456 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 1457 | |
f5bbdacc TG |
1458 | realpage = (int)(from >> chip->page_shift); |
1459 | page = realpage & chip->pagemask; | |
1da177e4 | 1460 | |
f5bbdacc | 1461 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 1462 | |
8593fbc6 TG |
1463 | buf = ops->datbuf; |
1464 | oob = ops->oobbuf; | |
e47f3db4 | 1465 | oob_required = oob ? 1 : 0; |
8593fbc6 | 1466 | |
f8ac0414 | 1467 | while (1) { |
f5bbdacc TG |
1468 | bytes = min(mtd->writesize - col, readlen); |
1469 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 1470 | |
8b6e50c9 | 1471 | /* Is the current page in the buffer? */ |
8593fbc6 | 1472 | if (realpage != chip->pagebuf || oob) { |
4bf63fcb | 1473 | bufpoi = aligned ? buf : chip->buffers->databuf; |
61b03bd7 | 1474 | |
c00a0991 | 1475 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); |
1da177e4 | 1476 | |
edbc4540 MD |
1477 | /* |
1478 | * Now read the page into the buffer. Absent an error, | |
1479 | * the read methods return max bitflips per ecc step. | |
1480 | */ | |
0612b9dd | 1481 | if (unlikely(ops->mode == MTD_OPS_RAW)) |
1fbb938d | 1482 | ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, |
e47f3db4 BN |
1483 | oob_required, |
1484 | page); | |
a5ff4f10 JW |
1485 | else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && |
1486 | !oob) | |
7351d3a5 FF |
1487 | ret = chip->ecc.read_subpage(mtd, chip, |
1488 | col, bytes, bufpoi); | |
956e944c | 1489 | else |
46a8cf2d | 1490 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
e47f3db4 | 1491 | oob_required, page); |
6d77b9d0 BN |
1492 | if (ret < 0) { |
1493 | if (!aligned) | |
1494 | /* Invalidate page cache */ | |
1495 | chip->pagebuf = -1; | |
1da177e4 | 1496 | break; |
6d77b9d0 | 1497 | } |
f5bbdacc | 1498 | |
edbc4540 MD |
1499 | max_bitflips = max_t(unsigned int, max_bitflips, ret); |
1500 | ||
f5bbdacc TG |
1501 | /* Transfer not aligned data */ |
1502 | if (!aligned) { | |
a5ff4f10 | 1503 | if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && |
6d77b9d0 | 1504 | !(mtd->ecc_stats.failed - stats.failed) && |
edbc4540 | 1505 | (ops->mode != MTD_OPS_RAW)) { |
3d459559 | 1506 | chip->pagebuf = realpage; |
edbc4540 MD |
1507 | chip->pagebuf_bitflips = ret; |
1508 | } else { | |
6d77b9d0 BN |
1509 | /* Invalidate page cache */ |
1510 | chip->pagebuf = -1; | |
edbc4540 | 1511 | } |
4bf63fcb | 1512 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
1513 | } |
1514 | ||
8593fbc6 TG |
1515 | buf += bytes; |
1516 | ||
1517 | if (unlikely(oob)) { | |
b64d39d8 ML |
1518 | int toread = min(oobreadlen, max_oobsize); |
1519 | ||
1520 | if (toread) { | |
1521 | oob = nand_transfer_oob(chip, | |
1522 | oob, ops, toread); | |
1523 | oobreadlen -= toread; | |
1524 | } | |
8593fbc6 | 1525 | } |
5bc7c33c BN |
1526 | |
1527 | if (chip->options & NAND_NEED_READRDY) { | |
1528 | /* Apply delay or wait for ready/busy pin */ | |
1529 | if (!chip->dev_ready) | |
1530 | udelay(chip->chip_delay); | |
1531 | else | |
1532 | nand_wait_ready(mtd); | |
1533 | } | |
8593fbc6 | 1534 | } else { |
4bf63fcb | 1535 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 | 1536 | buf += bytes; |
edbc4540 MD |
1537 | max_bitflips = max_t(unsigned int, max_bitflips, |
1538 | chip->pagebuf_bitflips); | |
8593fbc6 | 1539 | } |
1da177e4 | 1540 | |
f5bbdacc | 1541 | readlen -= bytes; |
61b03bd7 | 1542 | |
f5bbdacc | 1543 | if (!readlen) |
61b03bd7 | 1544 | break; |
1da177e4 | 1545 | |
8b6e50c9 | 1546 | /* For subsequent reads align to page boundary */ |
1da177e4 LT |
1547 | col = 0; |
1548 | /* Increment page address */ | |
1549 | realpage++; | |
1550 | ||
ace4dfee | 1551 | page = realpage & chip->pagemask; |
1da177e4 LT |
1552 | /* Check, if we cross a chip boundary */ |
1553 | if (!page) { | |
1554 | chipnr++; | |
ace4dfee TG |
1555 | chip->select_chip(mtd, -1); |
1556 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1557 | } |
1da177e4 | 1558 | } |
b0bb6903 | 1559 | chip->select_chip(mtd, -1); |
1da177e4 | 1560 | |
8593fbc6 | 1561 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
1562 | if (oob) |
1563 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 1564 | |
3f91e94f | 1565 | if (ret < 0) |
f5bbdacc TG |
1566 | return ret; |
1567 | ||
9a1fcdfd TG |
1568 | if (mtd->ecc_stats.failed - stats.failed) |
1569 | return -EBADMSG; | |
1570 | ||
edbc4540 | 1571 | return max_bitflips; |
f5bbdacc TG |
1572 | } |
1573 | ||
1574 | /** | |
25985edc | 1575 | * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc |
8b6e50c9 BN |
1576 | * @mtd: MTD device structure |
1577 | * @from: offset to read from | |
1578 | * @len: number of bytes to read | |
1579 | * @retlen: pointer to variable to store the number of read bytes | |
1580 | * @buf: the databuffer to put data | |
f5bbdacc | 1581 | * |
8b6e50c9 | 1582 | * Get hold of the chip and call nand_do_read. |
f5bbdacc TG |
1583 | */ |
1584 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1585 | size_t *retlen, uint8_t *buf) | |
1586 | { | |
4a89ff88 | 1587 | struct mtd_oob_ops ops; |
f5bbdacc TG |
1588 | int ret; |
1589 | ||
6a8214aa | 1590 | nand_get_device(mtd, FL_READING); |
4a89ff88 BN |
1591 | ops.len = len; |
1592 | ops.datbuf = buf; | |
1593 | ops.oobbuf = NULL; | |
11041ae6 | 1594 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 1595 | ret = nand_do_read_ops(mtd, from, &ops); |
4a89ff88 | 1596 | *retlen = ops.retlen; |
f5bbdacc | 1597 | nand_release_device(mtd); |
f5bbdacc | 1598 | return ret; |
1da177e4 LT |
1599 | } |
1600 | ||
7bc3312b | 1601 | /** |
7854d3f7 | 1602 | * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function |
8b6e50c9 BN |
1603 | * @mtd: mtd info structure |
1604 | * @chip: nand chip info structure | |
1605 | * @page: page number to read | |
7bc3312b TG |
1606 | */ |
1607 | static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1608 | int page) |
7bc3312b | 1609 | { |
5c2ffb11 | 1610 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); |
7bc3312b | 1611 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
5c2ffb11 | 1612 | return 0; |
7bc3312b TG |
1613 | } |
1614 | ||
1615 | /** | |
7854d3f7 | 1616 | * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC |
7bc3312b | 1617 | * with syndromes |
8b6e50c9 BN |
1618 | * @mtd: mtd info structure |
1619 | * @chip: nand chip info structure | |
1620 | * @page: page number to read | |
7bc3312b TG |
1621 | */ |
1622 | static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1623 | int page) |
7bc3312b TG |
1624 | { |
1625 | uint8_t *buf = chip->oob_poi; | |
1626 | int length = mtd->oobsize; | |
1627 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1628 | int eccsize = chip->ecc.size; | |
1629 | uint8_t *bufpoi = buf; | |
1630 | int i, toread, sndrnd = 0, pos; | |
1631 | ||
1632 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
1633 | for (i = 0; i < chip->ecc.steps; i++) { | |
1634 | if (sndrnd) { | |
1635 | pos = eccsize + i * (eccsize + chunk); | |
1636 | if (mtd->writesize > 512) | |
1637 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
1638 | else | |
1639 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
1640 | } else | |
1641 | sndrnd = 1; | |
1642 | toread = min_t(int, length, chunk); | |
1643 | chip->read_buf(mtd, bufpoi, toread); | |
1644 | bufpoi += toread; | |
1645 | length -= toread; | |
1646 | } | |
1647 | if (length > 0) | |
1648 | chip->read_buf(mtd, bufpoi, length); | |
1649 | ||
5c2ffb11 | 1650 | return 0; |
7bc3312b TG |
1651 | } |
1652 | ||
1653 | /** | |
7854d3f7 | 1654 | * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function |
8b6e50c9 BN |
1655 | * @mtd: mtd info structure |
1656 | * @chip: nand chip info structure | |
1657 | * @page: page number to write | |
7bc3312b TG |
1658 | */ |
1659 | static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1660 | int page) | |
1661 | { | |
1662 | int status = 0; | |
1663 | const uint8_t *buf = chip->oob_poi; | |
1664 | int length = mtd->oobsize; | |
1665 | ||
1666 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
1667 | chip->write_buf(mtd, buf, length); | |
1668 | /* Send command to program the OOB data */ | |
1669 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1670 | ||
1671 | status = chip->waitfunc(mtd, chip); | |
1672 | ||
0d420f9d | 1673 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b TG |
1674 | } |
1675 | ||
1676 | /** | |
7854d3f7 | 1677 | * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC |
8b6e50c9 BN |
1678 | * with syndrome - only for large page flash |
1679 | * @mtd: mtd info structure | |
1680 | * @chip: nand chip info structure | |
1681 | * @page: page number to write | |
7bc3312b TG |
1682 | */ |
1683 | static int nand_write_oob_syndrome(struct mtd_info *mtd, | |
1684 | struct nand_chip *chip, int page) | |
1685 | { | |
1686 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1687 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
1688 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
1689 | const uint8_t *bufpoi = chip->oob_poi; | |
1690 | ||
1691 | /* | |
1692 | * data-ecc-data-ecc ... ecc-oob | |
1693 | * or | |
1694 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
1695 | */ | |
1696 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
1697 | pos = steps * (eccsize + chunk); | |
1698 | steps = 0; | |
1699 | } else | |
8b0036ee | 1700 | pos = eccsize; |
7bc3312b TG |
1701 | |
1702 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
1703 | for (i = 0; i < steps; i++) { | |
1704 | if (sndcmd) { | |
1705 | if (mtd->writesize <= 512) { | |
1706 | uint32_t fill = 0xFFFFFFFF; | |
1707 | ||
1708 | len = eccsize; | |
1709 | while (len > 0) { | |
1710 | int num = min_t(int, len, 4); | |
1711 | chip->write_buf(mtd, (uint8_t *)&fill, | |
1712 | num); | |
1713 | len -= num; | |
1714 | } | |
1715 | } else { | |
1716 | pos = eccsize + i * (eccsize + chunk); | |
1717 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
1718 | } | |
1719 | } else | |
1720 | sndcmd = 1; | |
1721 | len = min_t(int, length, chunk); | |
1722 | chip->write_buf(mtd, bufpoi, len); | |
1723 | bufpoi += len; | |
1724 | length -= len; | |
1725 | } | |
1726 | if (length > 0) | |
1727 | chip->write_buf(mtd, bufpoi, length); | |
1728 | ||
1729 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1730 | status = chip->waitfunc(mtd, chip); | |
1731 | ||
1732 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
1733 | } | |
1734 | ||
1da177e4 | 1735 | /** |
7854d3f7 | 1736 | * nand_do_read_oob - [INTERN] NAND read out-of-band |
8b6e50c9 BN |
1737 | * @mtd: MTD device structure |
1738 | * @from: offset to read from | |
1739 | * @ops: oob operations description structure | |
1da177e4 | 1740 | * |
8b6e50c9 | 1741 | * NAND read out-of-band data from the spare area. |
1da177e4 | 1742 | */ |
8593fbc6 TG |
1743 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
1744 | struct mtd_oob_ops *ops) | |
1da177e4 | 1745 | { |
c00a0991 | 1746 | int page, realpage, chipnr; |
ace4dfee | 1747 | struct nand_chip *chip = mtd->priv; |
041e4575 | 1748 | struct mtd_ecc_stats stats; |
7014568b VW |
1749 | int readlen = ops->ooblen; |
1750 | int len; | |
7bc3312b | 1751 | uint8_t *buf = ops->oobbuf; |
1951f2f7 | 1752 | int ret = 0; |
61b03bd7 | 1753 | |
289c0522 | 1754 | pr_debug("%s: from = 0x%08Lx, len = %i\n", |
20d8e248 | 1755 | __func__, (unsigned long long)from, readlen); |
1da177e4 | 1756 | |
041e4575 BN |
1757 | stats = mtd->ecc_stats; |
1758 | ||
0612b9dd | 1759 | if (ops->mode == MTD_OPS_AUTO_OOB) |
7014568b | 1760 | len = chip->ecc.layout->oobavail; |
03736155 AH |
1761 | else |
1762 | len = mtd->oobsize; | |
1763 | ||
1764 | if (unlikely(ops->ooboffs >= len)) { | |
289c0522 BN |
1765 | pr_debug("%s: attempt to start read outside oob\n", |
1766 | __func__); | |
03736155 AH |
1767 | return -EINVAL; |
1768 | } | |
1769 | ||
1770 | /* Do not allow reads past end of device */ | |
1771 | if (unlikely(from >= mtd->size || | |
1772 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
1773 | (from >> chip->page_shift)) * len)) { | |
289c0522 BN |
1774 | pr_debug("%s: attempt to read beyond end of device\n", |
1775 | __func__); | |
03736155 AH |
1776 | return -EINVAL; |
1777 | } | |
7014568b | 1778 | |
7314e9e7 | 1779 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 1780 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1781 | |
7314e9e7 TG |
1782 | /* Shift to get page */ |
1783 | realpage = (int)(from >> chip->page_shift); | |
1784 | page = realpage & chip->pagemask; | |
1da177e4 | 1785 | |
f8ac0414 | 1786 | while (1) { |
0612b9dd | 1787 | if (ops->mode == MTD_OPS_RAW) |
1951f2f7 | 1788 | ret = chip->ecc.read_oob_raw(mtd, chip, page); |
c46f6483 | 1789 | else |
1951f2f7 SL |
1790 | ret = chip->ecc.read_oob(mtd, chip, page); |
1791 | ||
1792 | if (ret < 0) | |
1793 | break; | |
7014568b VW |
1794 | |
1795 | len = min(len, readlen); | |
1796 | buf = nand_transfer_oob(chip, buf, ops, len); | |
8593fbc6 | 1797 | |
5bc7c33c BN |
1798 | if (chip->options & NAND_NEED_READRDY) { |
1799 | /* Apply delay or wait for ready/busy pin */ | |
1800 | if (!chip->dev_ready) | |
1801 | udelay(chip->chip_delay); | |
1802 | else | |
1803 | nand_wait_ready(mtd); | |
1804 | } | |
1805 | ||
7014568b | 1806 | readlen -= len; |
0d420f9d SZ |
1807 | if (!readlen) |
1808 | break; | |
1809 | ||
7314e9e7 TG |
1810 | /* Increment page address */ |
1811 | realpage++; | |
1812 | ||
1813 | page = realpage & chip->pagemask; | |
1814 | /* Check, if we cross a chip boundary */ | |
1815 | if (!page) { | |
1816 | chipnr++; | |
1817 | chip->select_chip(mtd, -1); | |
1818 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
1819 | } |
1820 | } | |
b0bb6903 | 1821 | chip->select_chip(mtd, -1); |
1da177e4 | 1822 | |
1951f2f7 SL |
1823 | ops->oobretlen = ops->ooblen - readlen; |
1824 | ||
1825 | if (ret < 0) | |
1826 | return ret; | |
041e4575 BN |
1827 | |
1828 | if (mtd->ecc_stats.failed - stats.failed) | |
1829 | return -EBADMSG; | |
1830 | ||
1831 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
1da177e4 LT |
1832 | } |
1833 | ||
1834 | /** | |
8593fbc6 | 1835 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
8b6e50c9 BN |
1836 | * @mtd: MTD device structure |
1837 | * @from: offset to read from | |
1838 | * @ops: oob operation description structure | |
1da177e4 | 1839 | * |
8b6e50c9 | 1840 | * NAND read data and/or out-of-band data. |
1da177e4 | 1841 | */ |
8593fbc6 TG |
1842 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
1843 | struct mtd_oob_ops *ops) | |
1da177e4 | 1844 | { |
8593fbc6 TG |
1845 | int ret = -ENOTSUPP; |
1846 | ||
1847 | ops->retlen = 0; | |
1da177e4 LT |
1848 | |
1849 | /* Do not allow reads past end of device */ | |
7014568b | 1850 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
289c0522 BN |
1851 | pr_debug("%s: attempt to read beyond end of device\n", |
1852 | __func__); | |
1da177e4 LT |
1853 | return -EINVAL; |
1854 | } | |
1855 | ||
6a8214aa | 1856 | nand_get_device(mtd, FL_READING); |
1da177e4 | 1857 | |
f8ac0414 | 1858 | switch (ops->mode) { |
0612b9dd BN |
1859 | case MTD_OPS_PLACE_OOB: |
1860 | case MTD_OPS_AUTO_OOB: | |
1861 | case MTD_OPS_RAW: | |
8593fbc6 | 1862 | break; |
1da177e4 | 1863 | |
8593fbc6 TG |
1864 | default: |
1865 | goto out; | |
1866 | } | |
1da177e4 | 1867 | |
8593fbc6 TG |
1868 | if (!ops->datbuf) |
1869 | ret = nand_do_read_oob(mtd, from, ops); | |
1870 | else | |
1871 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 1872 | |
7351d3a5 | 1873 | out: |
8593fbc6 TG |
1874 | nand_release_device(mtd); |
1875 | return ret; | |
1876 | } | |
61b03bd7 | 1877 | |
1da177e4 | 1878 | |
8593fbc6 | 1879 | /** |
7854d3f7 | 1880 | * nand_write_page_raw - [INTERN] raw page write function |
8b6e50c9 BN |
1881 | * @mtd: mtd info structure |
1882 | * @chip: nand chip info structure | |
1883 | * @buf: data buffer | |
1fbb938d | 1884 | * @oob_required: must write chip->oob_poi to OOB |
52ff49df | 1885 | * |
7854d3f7 | 1886 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 | 1887 | */ |
fdbad98d | 1888 | static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1889 | const uint8_t *buf, int oob_required) |
8593fbc6 TG |
1890 | { |
1891 | chip->write_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
1892 | if (oob_required) |
1893 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
1894 | |
1895 | return 0; | |
1da177e4 LT |
1896 | } |
1897 | ||
52ff49df | 1898 | /** |
7854d3f7 | 1899 | * nand_write_page_raw_syndrome - [INTERN] raw page write function |
8b6e50c9 BN |
1900 | * @mtd: mtd info structure |
1901 | * @chip: nand chip info structure | |
1902 | * @buf: data buffer | |
1fbb938d | 1903 | * @oob_required: must write chip->oob_poi to OOB |
52ff49df DB |
1904 | * |
1905 | * We need a special oob layout and handling even when ECC isn't checked. | |
1906 | */ | |
fdbad98d | 1907 | static int nand_write_page_raw_syndrome(struct mtd_info *mtd, |
7351d3a5 | 1908 | struct nand_chip *chip, |
1fbb938d | 1909 | const uint8_t *buf, int oob_required) |
52ff49df DB |
1910 | { |
1911 | int eccsize = chip->ecc.size; | |
1912 | int eccbytes = chip->ecc.bytes; | |
1913 | uint8_t *oob = chip->oob_poi; | |
1914 | int steps, size; | |
1915 | ||
1916 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1917 | chip->write_buf(mtd, buf, eccsize); | |
1918 | buf += eccsize; | |
1919 | ||
1920 | if (chip->ecc.prepad) { | |
1921 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
1922 | oob += chip->ecc.prepad; | |
1923 | } | |
1924 | ||
1925 | chip->read_buf(mtd, oob, eccbytes); | |
1926 | oob += eccbytes; | |
1927 | ||
1928 | if (chip->ecc.postpad) { | |
1929 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
1930 | oob += chip->ecc.postpad; | |
1931 | } | |
1932 | } | |
1933 | ||
1934 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1935 | if (size) | |
1936 | chip->write_buf(mtd, oob, size); | |
fdbad98d JW |
1937 | |
1938 | return 0; | |
52ff49df | 1939 | } |
9223a456 | 1940 | /** |
7854d3f7 | 1941 | * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function |
8b6e50c9 BN |
1942 | * @mtd: mtd info structure |
1943 | * @chip: nand chip info structure | |
1944 | * @buf: data buffer | |
1fbb938d | 1945 | * @oob_required: must write chip->oob_poi to OOB |
9223a456 | 1946 | */ |
fdbad98d | 1947 | static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1948 | const uint8_t *buf, int oob_required) |
9223a456 | 1949 | { |
f75e5097 TG |
1950 | int i, eccsize = chip->ecc.size; |
1951 | int eccbytes = chip->ecc.bytes; | |
1952 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 1953 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 1954 | const uint8_t *p = buf; |
8b099a39 | 1955 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1956 | |
7854d3f7 | 1957 | /* Software ECC calculation */ |
8593fbc6 TG |
1958 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
1959 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 1960 | |
8593fbc6 TG |
1961 | for (i = 0; i < chip->ecc.total; i++) |
1962 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 | 1963 | |
fdbad98d | 1964 | return chip->ecc.write_page_raw(mtd, chip, buf, 1); |
f75e5097 | 1965 | } |
9223a456 | 1966 | |
f75e5097 | 1967 | /** |
7854d3f7 | 1968 | * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function |
8b6e50c9 BN |
1969 | * @mtd: mtd info structure |
1970 | * @chip: nand chip info structure | |
1971 | * @buf: data buffer | |
1fbb938d | 1972 | * @oob_required: must write chip->oob_poi to OOB |
f75e5097 | 1973 | */ |
fdbad98d | 1974 | static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1975 | const uint8_t *buf, int oob_required) |
f75e5097 TG |
1976 | { |
1977 | int i, eccsize = chip->ecc.size; | |
1978 | int eccbytes = chip->ecc.bytes; | |
1979 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 1980 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 1981 | const uint8_t *p = buf; |
8b099a39 | 1982 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1983 | |
f75e5097 TG |
1984 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1985 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 1986 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 1987 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
1988 | } |
1989 | ||
f75e5097 TG |
1990 | for (i = 0; i < chip->ecc.total; i++) |
1991 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
1992 | ||
1993 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
1994 | |
1995 | return 0; | |
9223a456 TG |
1996 | } |
1997 | ||
61b03bd7 | 1998 | /** |
7854d3f7 | 1999 | * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write |
8b6e50c9 BN |
2000 | * @mtd: mtd info structure |
2001 | * @chip: nand chip info structure | |
2002 | * @buf: data buffer | |
1fbb938d | 2003 | * @oob_required: must write chip->oob_poi to OOB |
1da177e4 | 2004 | * |
8b6e50c9 BN |
2005 | * The hw generator calculates the error syndrome automatically. Therefore we |
2006 | * need a special oob layout and handling. | |
f75e5097 | 2007 | */ |
fdbad98d | 2008 | static int nand_write_page_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
2009 | struct nand_chip *chip, |
2010 | const uint8_t *buf, int oob_required) | |
1da177e4 | 2011 | { |
f75e5097 TG |
2012 | int i, eccsize = chip->ecc.size; |
2013 | int eccbytes = chip->ecc.bytes; | |
2014 | int eccsteps = chip->ecc.steps; | |
2015 | const uint8_t *p = buf; | |
2016 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 2017 | |
f75e5097 | 2018 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 2019 | |
f75e5097 TG |
2020 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
2021 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 2022 | |
f75e5097 TG |
2023 | if (chip->ecc.prepad) { |
2024 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2025 | oob += chip->ecc.prepad; | |
2026 | } | |
2027 | ||
2028 | chip->ecc.calculate(mtd, p, oob); | |
2029 | chip->write_buf(mtd, oob, eccbytes); | |
2030 | oob += eccbytes; | |
2031 | ||
2032 | if (chip->ecc.postpad) { | |
2033 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2034 | oob += chip->ecc.postpad; | |
1da177e4 | 2035 | } |
1da177e4 | 2036 | } |
f75e5097 TG |
2037 | |
2038 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 2039 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
2040 | if (i) |
2041 | chip->write_buf(mtd, oob, i); | |
fdbad98d JW |
2042 | |
2043 | return 0; | |
f75e5097 TG |
2044 | } |
2045 | ||
2046 | /** | |
956e944c | 2047 | * nand_write_page - [REPLACEABLE] write one page |
8b6e50c9 BN |
2048 | * @mtd: MTD device structure |
2049 | * @chip: NAND chip descriptor | |
2050 | * @buf: the data to write | |
1fbb938d | 2051 | * @oob_required: must write chip->oob_poi to OOB |
8b6e50c9 BN |
2052 | * @page: page number to write |
2053 | * @cached: cached programming | |
2054 | * @raw: use _raw version of write_page | |
f75e5097 TG |
2055 | */ |
2056 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d BN |
2057 | const uint8_t *buf, int oob_required, int page, |
2058 | int cached, int raw) | |
f75e5097 TG |
2059 | { |
2060 | int status; | |
2061 | ||
2062 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
2063 | ||
956e944c | 2064 | if (unlikely(raw)) |
fdbad98d | 2065 | status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required); |
956e944c | 2066 | else |
fdbad98d JW |
2067 | status = chip->ecc.write_page(mtd, chip, buf, oob_required); |
2068 | ||
2069 | if (status < 0) | |
2070 | return status; | |
f75e5097 TG |
2071 | |
2072 | /* | |
7854d3f7 | 2073 | * Cached progamming disabled for now. Not sure if it's worth the |
8b6e50c9 | 2074 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s). |
f75e5097 TG |
2075 | */ |
2076 | cached = 0; | |
2077 | ||
2078 | if (!cached || !(chip->options & NAND_CACHEPRG)) { | |
2079 | ||
2080 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
7bc3312b | 2081 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2082 | /* |
2083 | * See if operation failed and additional status checks are | |
8b6e50c9 | 2084 | * available. |
f75e5097 TG |
2085 | */ |
2086 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2087 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
2088 | page); | |
2089 | ||
2090 | if (status & NAND_STATUS_FAIL) | |
2091 | return -EIO; | |
2092 | } else { | |
2093 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
7bc3312b | 2094 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2095 | } |
2096 | ||
f75e5097 | 2097 | return 0; |
1da177e4 LT |
2098 | } |
2099 | ||
8593fbc6 | 2100 | /** |
7854d3f7 | 2101 | * nand_fill_oob - [INTERN] Transfer client buffer to oob |
f722013e | 2102 | * @mtd: MTD device structure |
8b6e50c9 BN |
2103 | * @oob: oob data buffer |
2104 | * @len: oob data write length | |
2105 | * @ops: oob ops structure | |
8593fbc6 | 2106 | */ |
f722013e TAA |
2107 | static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, |
2108 | struct mtd_oob_ops *ops) | |
8593fbc6 | 2109 | { |
f722013e TAA |
2110 | struct nand_chip *chip = mtd->priv; |
2111 | ||
2112 | /* | |
2113 | * Initialise to all 0xFF, to avoid the possibility of left over OOB | |
2114 | * data from a previous OOB read. | |
2115 | */ | |
2116 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
2117 | ||
f8ac0414 | 2118 | switch (ops->mode) { |
8593fbc6 | 2119 | |
0612b9dd BN |
2120 | case MTD_OPS_PLACE_OOB: |
2121 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2122 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); |
2123 | return oob + len; | |
2124 | ||
0612b9dd | 2125 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 2126 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
2127 | uint32_t boffs = 0, woffs = ops->ooboffs; |
2128 | size_t bytes = 0; | |
8593fbc6 | 2129 | |
f8ac0414 | 2130 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 2131 | /* Write request not from offset 0? */ |
7bc3312b TG |
2132 | if (unlikely(woffs)) { |
2133 | if (woffs >= free->length) { | |
2134 | woffs -= free->length; | |
2135 | continue; | |
2136 | } | |
2137 | boffs = free->offset + woffs; | |
2138 | bytes = min_t(size_t, len, | |
2139 | (free->length - woffs)); | |
2140 | woffs = 0; | |
2141 | } else { | |
2142 | bytes = min_t(size_t, len, free->length); | |
2143 | boffs = free->offset; | |
2144 | } | |
8b0036ee | 2145 | memcpy(chip->oob_poi + boffs, oob, bytes); |
8593fbc6 TG |
2146 | oob += bytes; |
2147 | } | |
2148 | return oob; | |
2149 | } | |
2150 | default: | |
2151 | BUG(); | |
2152 | } | |
2153 | return NULL; | |
2154 | } | |
2155 | ||
f8ac0414 | 2156 | #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) |
1da177e4 LT |
2157 | |
2158 | /** | |
7854d3f7 | 2159 | * nand_do_write_ops - [INTERN] NAND write with ECC |
8b6e50c9 BN |
2160 | * @mtd: MTD device structure |
2161 | * @to: offset to write to | |
2162 | * @ops: oob operations description structure | |
1da177e4 | 2163 | * |
8b6e50c9 | 2164 | * NAND write with ECC. |
1da177e4 | 2165 | */ |
8593fbc6 TG |
2166 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
2167 | struct mtd_oob_ops *ops) | |
1da177e4 | 2168 | { |
29072b96 | 2169 | int chipnr, realpage, page, blockmask, column; |
ace4dfee | 2170 | struct nand_chip *chip = mtd->priv; |
8593fbc6 | 2171 | uint32_t writelen = ops->len; |
782ce79a ML |
2172 | |
2173 | uint32_t oobwritelen = ops->ooblen; | |
0612b9dd | 2174 | uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ? |
782ce79a ML |
2175 | mtd->oobavail : mtd->oobsize; |
2176 | ||
8593fbc6 TG |
2177 | uint8_t *oob = ops->oobbuf; |
2178 | uint8_t *buf = ops->datbuf; | |
29072b96 | 2179 | int ret, subpage; |
e47f3db4 | 2180 | int oob_required = oob ? 1 : 0; |
1da177e4 | 2181 | |
8593fbc6 | 2182 | ops->retlen = 0; |
29072b96 TG |
2183 | if (!writelen) |
2184 | return 0; | |
1da177e4 | 2185 | |
8b6e50c9 | 2186 | /* Reject writes, which are not page aligned */ |
8593fbc6 | 2187 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
d0370219 BN |
2188 | pr_notice("%s: attempt to write non page aligned data\n", |
2189 | __func__); | |
1da177e4 LT |
2190 | return -EINVAL; |
2191 | } | |
2192 | ||
29072b96 TG |
2193 | column = to & (mtd->writesize - 1); |
2194 | subpage = column || (writelen & (mtd->writesize - 1)); | |
2195 | ||
2196 | if (subpage && oob) | |
2197 | return -EINVAL; | |
1da177e4 | 2198 | |
6a930961 TG |
2199 | chipnr = (int)(to >> chip->chip_shift); |
2200 | chip->select_chip(mtd, chipnr); | |
2201 | ||
1da177e4 | 2202 | /* Check, if it is write protected */ |
b0bb6903 HS |
2203 | if (nand_check_wp(mtd)) { |
2204 | ret = -EIO; | |
2205 | goto err_out; | |
2206 | } | |
1da177e4 | 2207 | |
f75e5097 TG |
2208 | realpage = (int)(to >> chip->page_shift); |
2209 | page = realpage & chip->pagemask; | |
2210 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
2211 | ||
2212 | /* Invalidate the page cache, when we write to the cached page */ | |
2213 | if (to <= (chip->pagebuf << chip->page_shift) && | |
8593fbc6 | 2214 | (chip->pagebuf << chip->page_shift) < (to + ops->len)) |
ace4dfee | 2215 | chip->pagebuf = -1; |
61b03bd7 | 2216 | |
782ce79a | 2217 | /* Don't allow multipage oob writes with offset */ |
b0bb6903 HS |
2218 | if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { |
2219 | ret = -EINVAL; | |
2220 | goto err_out; | |
2221 | } | |
782ce79a | 2222 | |
f8ac0414 | 2223 | while (1) { |
29072b96 | 2224 | int bytes = mtd->writesize; |
f75e5097 | 2225 | int cached = writelen > bytes && page != blockmask; |
29072b96 TG |
2226 | uint8_t *wbuf = buf; |
2227 | ||
8b6e50c9 | 2228 | /* Partial page write? */ |
29072b96 TG |
2229 | if (unlikely(column || writelen < (mtd->writesize - 1))) { |
2230 | cached = 0; | |
2231 | bytes = min_t(int, bytes - column, (int) writelen); | |
2232 | chip->pagebuf = -1; | |
2233 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
2234 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
2235 | wbuf = chip->buffers->databuf; | |
2236 | } | |
1da177e4 | 2237 | |
782ce79a ML |
2238 | if (unlikely(oob)) { |
2239 | size_t len = min(oobwritelen, oobmaxlen); | |
f722013e | 2240 | oob = nand_fill_oob(mtd, oob, len, ops); |
782ce79a | 2241 | oobwritelen -= len; |
f722013e TAA |
2242 | } else { |
2243 | /* We still need to erase leftover OOB data */ | |
2244 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
782ce79a | 2245 | } |
8593fbc6 | 2246 | |
e47f3db4 BN |
2247 | ret = chip->write_page(mtd, chip, wbuf, oob_required, page, |
2248 | cached, (ops->mode == MTD_OPS_RAW)); | |
f75e5097 TG |
2249 | if (ret) |
2250 | break; | |
2251 | ||
2252 | writelen -= bytes; | |
2253 | if (!writelen) | |
2254 | break; | |
2255 | ||
29072b96 | 2256 | column = 0; |
f75e5097 TG |
2257 | buf += bytes; |
2258 | realpage++; | |
2259 | ||
2260 | page = realpage & chip->pagemask; | |
2261 | /* Check, if we cross a chip boundary */ | |
2262 | if (!page) { | |
2263 | chipnr++; | |
2264 | chip->select_chip(mtd, -1); | |
2265 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2266 | } |
2267 | } | |
8593fbc6 | 2268 | |
8593fbc6 | 2269 | ops->retlen = ops->len - writelen; |
7014568b VW |
2270 | if (unlikely(oob)) |
2271 | ops->oobretlen = ops->ooblen; | |
b0bb6903 HS |
2272 | |
2273 | err_out: | |
2274 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
2275 | return ret; |
2276 | } | |
2277 | ||
2af7c653 SK |
2278 | /** |
2279 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
8b6e50c9 BN |
2280 | * @mtd: MTD device structure |
2281 | * @to: offset to write to | |
2282 | * @len: number of bytes to write | |
2283 | * @retlen: pointer to variable to store the number of written bytes | |
2284 | * @buf: the data to write | |
2af7c653 SK |
2285 | * |
2286 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
2287 | * may for example be called by mtdoops when writing an oops while in panic. | |
2288 | */ | |
2289 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
2290 | size_t *retlen, const uint8_t *buf) | |
2291 | { | |
2292 | struct nand_chip *chip = mtd->priv; | |
4a89ff88 | 2293 | struct mtd_oob_ops ops; |
2af7c653 SK |
2294 | int ret; |
2295 | ||
8b6e50c9 | 2296 | /* Wait for the device to get ready */ |
2af7c653 SK |
2297 | panic_nand_wait(mtd, chip, 400); |
2298 | ||
8b6e50c9 | 2299 | /* Grab the device */ |
2af7c653 SK |
2300 | panic_nand_get_device(chip, mtd, FL_WRITING); |
2301 | ||
4a89ff88 BN |
2302 | ops.len = len; |
2303 | ops.datbuf = (uint8_t *)buf; | |
2304 | ops.oobbuf = NULL; | |
11041ae6 | 2305 | ops.mode = MTD_OPS_PLACE_OOB; |
2af7c653 | 2306 | |
4a89ff88 | 2307 | ret = nand_do_write_ops(mtd, to, &ops); |
2af7c653 | 2308 | |
4a89ff88 | 2309 | *retlen = ops.retlen; |
2af7c653 SK |
2310 | return ret; |
2311 | } | |
2312 | ||
f75e5097 | 2313 | /** |
8593fbc6 | 2314 | * nand_write - [MTD Interface] NAND write with ECC |
8b6e50c9 BN |
2315 | * @mtd: MTD device structure |
2316 | * @to: offset to write to | |
2317 | * @len: number of bytes to write | |
2318 | * @retlen: pointer to variable to store the number of written bytes | |
2319 | * @buf: the data to write | |
f75e5097 | 2320 | * |
8b6e50c9 | 2321 | * NAND write with ECC. |
f75e5097 | 2322 | */ |
8593fbc6 TG |
2323 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
2324 | size_t *retlen, const uint8_t *buf) | |
f75e5097 | 2325 | { |
4a89ff88 | 2326 | struct mtd_oob_ops ops; |
f75e5097 TG |
2327 | int ret; |
2328 | ||
6a8214aa | 2329 | nand_get_device(mtd, FL_WRITING); |
4a89ff88 BN |
2330 | ops.len = len; |
2331 | ops.datbuf = (uint8_t *)buf; | |
2332 | ops.oobbuf = NULL; | |
11041ae6 | 2333 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 2334 | ret = nand_do_write_ops(mtd, to, &ops); |
4a89ff88 | 2335 | *retlen = ops.retlen; |
f75e5097 | 2336 | nand_release_device(mtd); |
8593fbc6 | 2337 | return ret; |
f75e5097 | 2338 | } |
7314e9e7 | 2339 | |
1da177e4 | 2340 | /** |
8593fbc6 | 2341 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
8b6e50c9 BN |
2342 | * @mtd: MTD device structure |
2343 | * @to: offset to write to | |
2344 | * @ops: oob operation description structure | |
1da177e4 | 2345 | * |
8b6e50c9 | 2346 | * NAND write out-of-band. |
1da177e4 | 2347 | */ |
8593fbc6 TG |
2348 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
2349 | struct mtd_oob_ops *ops) | |
1da177e4 | 2350 | { |
03736155 | 2351 | int chipnr, page, status, len; |
ace4dfee | 2352 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2353 | |
289c0522 | 2354 | pr_debug("%s: to = 0x%08x, len = %i\n", |
20d8e248 | 2355 | __func__, (unsigned int)to, (int)ops->ooblen); |
1da177e4 | 2356 | |
0612b9dd | 2357 | if (ops->mode == MTD_OPS_AUTO_OOB) |
03736155 AH |
2358 | len = chip->ecc.layout->oobavail; |
2359 | else | |
2360 | len = mtd->oobsize; | |
2361 | ||
1da177e4 | 2362 | /* Do not allow write past end of page */ |
03736155 | 2363 | if ((ops->ooboffs + ops->ooblen) > len) { |
289c0522 BN |
2364 | pr_debug("%s: attempt to write past end of page\n", |
2365 | __func__); | |
1da177e4 LT |
2366 | return -EINVAL; |
2367 | } | |
2368 | ||
03736155 | 2369 | if (unlikely(ops->ooboffs >= len)) { |
289c0522 BN |
2370 | pr_debug("%s: attempt to start write outside oob\n", |
2371 | __func__); | |
03736155 AH |
2372 | return -EINVAL; |
2373 | } | |
2374 | ||
775adc3d | 2375 | /* Do not allow write past end of device */ |
03736155 AH |
2376 | if (unlikely(to >= mtd->size || |
2377 | ops->ooboffs + ops->ooblen > | |
2378 | ((mtd->size >> chip->page_shift) - | |
2379 | (to >> chip->page_shift)) * len)) { | |
289c0522 BN |
2380 | pr_debug("%s: attempt to write beyond end of device\n", |
2381 | __func__); | |
03736155 AH |
2382 | return -EINVAL; |
2383 | } | |
2384 | ||
7314e9e7 | 2385 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 2386 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2387 | |
7314e9e7 TG |
2388 | /* Shift to get page */ |
2389 | page = (int)(to >> chip->page_shift); | |
2390 | ||
2391 | /* | |
2392 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
2393 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
2394 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
2395 | * it in the doc2000 driver in August 1999. dwmw2. | |
2396 | */ | |
ace4dfee | 2397 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
2398 | |
2399 | /* Check, if it is write protected */ | |
b0bb6903 HS |
2400 | if (nand_check_wp(mtd)) { |
2401 | chip->select_chip(mtd, -1); | |
8593fbc6 | 2402 | return -EROFS; |
b0bb6903 | 2403 | } |
61b03bd7 | 2404 | |
1da177e4 | 2405 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
2406 | if (page == chip->pagebuf) |
2407 | chip->pagebuf = -1; | |
1da177e4 | 2408 | |
f722013e | 2409 | nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops); |
9ce244b3 | 2410 | |
0612b9dd | 2411 | if (ops->mode == MTD_OPS_RAW) |
9ce244b3 BN |
2412 | status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask); |
2413 | else | |
2414 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); | |
1da177e4 | 2415 | |
b0bb6903 HS |
2416 | chip->select_chip(mtd, -1); |
2417 | ||
7bc3312b TG |
2418 | if (status) |
2419 | return status; | |
1da177e4 | 2420 | |
7014568b | 2421 | ops->oobretlen = ops->ooblen; |
1da177e4 | 2422 | |
7bc3312b | 2423 | return 0; |
8593fbc6 TG |
2424 | } |
2425 | ||
2426 | /** | |
2427 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
8b6e50c9 BN |
2428 | * @mtd: MTD device structure |
2429 | * @to: offset to write to | |
2430 | * @ops: oob operation description structure | |
8593fbc6 TG |
2431 | */ |
2432 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
2433 | struct mtd_oob_ops *ops) | |
2434 | { | |
8593fbc6 TG |
2435 | int ret = -ENOTSUPP; |
2436 | ||
2437 | ops->retlen = 0; | |
2438 | ||
2439 | /* Do not allow writes past end of device */ | |
7014568b | 2440 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
289c0522 BN |
2441 | pr_debug("%s: attempt to write beyond end of device\n", |
2442 | __func__); | |
8593fbc6 TG |
2443 | return -EINVAL; |
2444 | } | |
2445 | ||
6a8214aa | 2446 | nand_get_device(mtd, FL_WRITING); |
8593fbc6 | 2447 | |
f8ac0414 | 2448 | switch (ops->mode) { |
0612b9dd BN |
2449 | case MTD_OPS_PLACE_OOB: |
2450 | case MTD_OPS_AUTO_OOB: | |
2451 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2452 | break; |
2453 | ||
2454 | default: | |
2455 | goto out; | |
2456 | } | |
2457 | ||
2458 | if (!ops->datbuf) | |
2459 | ret = nand_do_write_oob(mtd, to, ops); | |
2460 | else | |
2461 | ret = nand_do_write_ops(mtd, to, ops); | |
2462 | ||
7351d3a5 | 2463 | out: |
1da177e4 | 2464 | nand_release_device(mtd); |
1da177e4 LT |
2465 | return ret; |
2466 | } | |
2467 | ||
1da177e4 | 2468 | /** |
7854d3f7 | 2469 | * single_erase_cmd - [GENERIC] NAND standard block erase command function |
8b6e50c9 BN |
2470 | * @mtd: MTD device structure |
2471 | * @page: the page address of the block which will be erased | |
1da177e4 | 2472 | * |
8b6e50c9 | 2473 | * Standard erase command for NAND chips. |
1da177e4 | 2474 | */ |
e0c7d767 | 2475 | static void single_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 2476 | { |
ace4dfee | 2477 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2478 | /* Send commands to erase a block */ |
ace4dfee TG |
2479 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
2480 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
2481 | } |
2482 | ||
2483 | /** | |
7854d3f7 | 2484 | * multi_erase_cmd - [GENERIC] AND specific block erase command function |
8b6e50c9 BN |
2485 | * @mtd: MTD device structure |
2486 | * @page: the page address of the block which will be erased | |
1da177e4 | 2487 | * |
8b6e50c9 | 2488 | * AND multi block erase command function. Erase 4 consecutive blocks. |
1da177e4 | 2489 | */ |
e0c7d767 | 2490 | static void multi_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 2491 | { |
ace4dfee | 2492 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2493 | /* Send commands to erase a block */ |
ace4dfee TG |
2494 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); |
2495 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
2496 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
2497 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); | |
2498 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
2499 | } |
2500 | ||
2501 | /** | |
2502 | * nand_erase - [MTD Interface] erase block(s) | |
8b6e50c9 BN |
2503 | * @mtd: MTD device structure |
2504 | * @instr: erase instruction | |
1da177e4 | 2505 | * |
8b6e50c9 | 2506 | * Erase one ore more blocks. |
1da177e4 | 2507 | */ |
e0c7d767 | 2508 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 2509 | { |
e0c7d767 | 2510 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 2511 | } |
61b03bd7 | 2512 | |
30f464b7 | 2513 | #define BBT_PAGE_MASK 0xffffff3f |
1da177e4 | 2514 | /** |
7854d3f7 | 2515 | * nand_erase_nand - [INTERN] erase block(s) |
8b6e50c9 BN |
2516 | * @mtd: MTD device structure |
2517 | * @instr: erase instruction | |
2518 | * @allowbbt: allow erasing the bbt area | |
1da177e4 | 2519 | * |
8b6e50c9 | 2520 | * Erase one ore more blocks. |
1da177e4 | 2521 | */ |
ace4dfee TG |
2522 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
2523 | int allowbbt) | |
1da177e4 | 2524 | { |
69423d99 | 2525 | int page, status, pages_per_block, ret, chipnr; |
ace4dfee | 2526 | struct nand_chip *chip = mtd->priv; |
f8ac0414 | 2527 | loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0}; |
ace4dfee | 2528 | unsigned int bbt_masked_page = 0xffffffff; |
69423d99 | 2529 | loff_t len; |
1da177e4 | 2530 | |
289c0522 BN |
2531 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
2532 | __func__, (unsigned long long)instr->addr, | |
2533 | (unsigned long long)instr->len); | |
1da177e4 | 2534 | |
6fe5a6ac | 2535 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 2536 | return -EINVAL; |
1da177e4 | 2537 | |
1da177e4 | 2538 | /* Grab the lock and see if the device is available */ |
6a8214aa | 2539 | nand_get_device(mtd, FL_ERASING); |
1da177e4 LT |
2540 | |
2541 | /* Shift to get first page */ | |
ace4dfee TG |
2542 | page = (int)(instr->addr >> chip->page_shift); |
2543 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
2544 | |
2545 | /* Calculate pages in each block */ | |
ace4dfee | 2546 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
2547 | |
2548 | /* Select the NAND device */ | |
ace4dfee | 2549 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2550 | |
1da177e4 LT |
2551 | /* Check, if it is write protected */ |
2552 | if (nand_check_wp(mtd)) { | |
289c0522 BN |
2553 | pr_debug("%s: device is write protected!\n", |
2554 | __func__); | |
1da177e4 LT |
2555 | instr->state = MTD_ERASE_FAILED; |
2556 | goto erase_exit; | |
2557 | } | |
2558 | ||
ace4dfee TG |
2559 | /* |
2560 | * If BBT requires refresh, set the BBT page mask to see if the BBT | |
2561 | * should be rewritten. Otherwise the mask is set to 0xffffffff which | |
2562 | * can not be matched. This is also done when the bbt is actually | |
7854d3f7 | 2563 | * erased to avoid recursive updates. |
ace4dfee TG |
2564 | */ |
2565 | if (chip->options & BBT_AUTO_REFRESH && !allowbbt) | |
2566 | bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK; | |
30f464b7 | 2567 | |
1da177e4 LT |
2568 | /* Loop through the pages */ |
2569 | len = instr->len; | |
2570 | ||
2571 | instr->state = MTD_ERASING; | |
2572 | ||
2573 | while (len) { | |
12183a20 | 2574 | /* Check if we have a bad block, we do not erase bad blocks! */ |
ace4dfee TG |
2575 | if (nand_block_checkbad(mtd, ((loff_t) page) << |
2576 | chip->page_shift, 0, allowbbt)) { | |
d0370219 BN |
2577 | pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", |
2578 | __func__, page); | |
1da177e4 LT |
2579 | instr->state = MTD_ERASE_FAILED; |
2580 | goto erase_exit; | |
2581 | } | |
61b03bd7 | 2582 | |
ace4dfee TG |
2583 | /* |
2584 | * Invalidate the page cache, if we erase the block which | |
8b6e50c9 | 2585 | * contains the current cached page. |
ace4dfee TG |
2586 | */ |
2587 | if (page <= chip->pagebuf && chip->pagebuf < | |
2588 | (page + pages_per_block)) | |
2589 | chip->pagebuf = -1; | |
1da177e4 | 2590 | |
ace4dfee | 2591 | chip->erase_cmd(mtd, page & chip->pagemask); |
61b03bd7 | 2592 | |
7bc3312b | 2593 | status = chip->waitfunc(mtd, chip); |
1da177e4 | 2594 | |
ace4dfee TG |
2595 | /* |
2596 | * See if operation failed and additional status checks are | |
2597 | * available | |
2598 | */ | |
2599 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2600 | status = chip->errstat(mtd, chip, FL_ERASING, | |
2601 | status, page); | |
068e3c0a | 2602 | |
1da177e4 | 2603 | /* See if block erase succeeded */ |
a4ab4c5d | 2604 | if (status & NAND_STATUS_FAIL) { |
289c0522 BN |
2605 | pr_debug("%s: failed erase, page 0x%08x\n", |
2606 | __func__, page); | |
1da177e4 | 2607 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
2608 | instr->fail_addr = |
2609 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
2610 | goto erase_exit; |
2611 | } | |
30f464b7 | 2612 | |
ace4dfee TG |
2613 | /* |
2614 | * If BBT requires refresh, set the BBT rewrite flag to the | |
8b6e50c9 | 2615 | * page being erased. |
ace4dfee TG |
2616 | */ |
2617 | if (bbt_masked_page != 0xffffffff && | |
2618 | (page & BBT_PAGE_MASK) == bbt_masked_page) | |
69423d99 AH |
2619 | rewrite_bbt[chipnr] = |
2620 | ((loff_t)page << chip->page_shift); | |
61b03bd7 | 2621 | |
1da177e4 | 2622 | /* Increment page address and decrement length */ |
ace4dfee | 2623 | len -= (1 << chip->phys_erase_shift); |
1da177e4 LT |
2624 | page += pages_per_block; |
2625 | ||
2626 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 2627 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 2628 | chipnr++; |
ace4dfee TG |
2629 | chip->select_chip(mtd, -1); |
2630 | chip->select_chip(mtd, chipnr); | |
30f464b7 | 2631 | |
ace4dfee TG |
2632 | /* |
2633 | * If BBT requires refresh and BBT-PERCHIP, set the BBT | |
8b6e50c9 | 2634 | * page mask to see if this BBT should be rewritten. |
ace4dfee TG |
2635 | */ |
2636 | if (bbt_masked_page != 0xffffffff && | |
2637 | (chip->bbt_td->options & NAND_BBT_PERCHIP)) | |
2638 | bbt_masked_page = chip->bbt_td->pages[chipnr] & | |
2639 | BBT_PAGE_MASK; | |
1da177e4 LT |
2640 | } |
2641 | } | |
2642 | instr->state = MTD_ERASE_DONE; | |
2643 | ||
7351d3a5 | 2644 | erase_exit: |
1da177e4 LT |
2645 | |
2646 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
2647 | |
2648 | /* Deselect and wake up anyone waiting on the device */ | |
b0bb6903 | 2649 | chip->select_chip(mtd, -1); |
1da177e4 LT |
2650 | nand_release_device(mtd); |
2651 | ||
49defc01 DW |
2652 | /* Do call back function */ |
2653 | if (!ret) | |
2654 | mtd_erase_callback(instr); | |
2655 | ||
ace4dfee TG |
2656 | /* |
2657 | * If BBT requires refresh and erase was successful, rewrite any | |
8b6e50c9 | 2658 | * selected bad block tables. |
ace4dfee TG |
2659 | */ |
2660 | if (bbt_masked_page == 0xffffffff || ret) | |
2661 | return ret; | |
2662 | ||
2663 | for (chipnr = 0; chipnr < chip->numchips; chipnr++) { | |
2664 | if (!rewrite_bbt[chipnr]) | |
2665 | continue; | |
8b6e50c9 | 2666 | /* Update the BBT for chip */ |
289c0522 BN |
2667 | pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n", |
2668 | __func__, chipnr, rewrite_bbt[chipnr], | |
2669 | chip->bbt_td->pages[chipnr]); | |
ace4dfee | 2670 | nand_update_bbt(mtd, rewrite_bbt[chipnr]); |
30f464b7 DM |
2671 | } |
2672 | ||
1da177e4 LT |
2673 | /* Return more or less happy */ |
2674 | return ret; | |
2675 | } | |
2676 | ||
2677 | /** | |
2678 | * nand_sync - [MTD Interface] sync | |
8b6e50c9 | 2679 | * @mtd: MTD device structure |
1da177e4 | 2680 | * |
8b6e50c9 | 2681 | * Sync is actually a wait for chip ready function. |
1da177e4 | 2682 | */ |
e0c7d767 | 2683 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 2684 | { |
289c0522 | 2685 | pr_debug("%s: called\n", __func__); |
1da177e4 LT |
2686 | |
2687 | /* Grab the lock and see if the device is available */ | |
6a8214aa | 2688 | nand_get_device(mtd, FL_SYNCING); |
1da177e4 | 2689 | /* Release it and go back */ |
e0c7d767 | 2690 | nand_release_device(mtd); |
1da177e4 LT |
2691 | } |
2692 | ||
1da177e4 | 2693 | /** |
ace4dfee | 2694 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
8b6e50c9 BN |
2695 | * @mtd: MTD device structure |
2696 | * @offs: offset relative to mtd start | |
1da177e4 | 2697 | */ |
ace4dfee | 2698 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 | 2699 | { |
ace4dfee | 2700 | return nand_block_checkbad(mtd, offs, 1, 0); |
1da177e4 LT |
2701 | } |
2702 | ||
2703 | /** | |
ace4dfee | 2704 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
8b6e50c9 BN |
2705 | * @mtd: MTD device structure |
2706 | * @ofs: offset relative to mtd start | |
1da177e4 | 2707 | */ |
e0c7d767 | 2708 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 2709 | { |
ace4dfee | 2710 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
2711 | int ret; |
2712 | ||
f8ac0414 FF |
2713 | ret = nand_block_isbad(mtd, ofs); |
2714 | if (ret) { | |
8b6e50c9 | 2715 | /* If it was bad already, return success and do nothing */ |
1da177e4 LT |
2716 | if (ret > 0) |
2717 | return 0; | |
e0c7d767 DW |
2718 | return ret; |
2719 | } | |
1da177e4 | 2720 | |
ace4dfee | 2721 | return chip->block_markbad(mtd, ofs); |
1da177e4 LT |
2722 | } |
2723 | ||
7db03ecc HS |
2724 | /** |
2725 | * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand | |
2726 | * @mtd: MTD device structure | |
2727 | * @chip: nand chip info structure | |
2728 | * @addr: feature address. | |
2729 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
2730 | */ | |
2731 | static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, | |
2732 | int addr, uint8_t *subfeature_param) | |
2733 | { | |
2734 | int status; | |
2735 | ||
2736 | if (!chip->onfi_version) | |
2737 | return -EINVAL; | |
2738 | ||
2739 | chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1); | |
2740 | chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN); | |
2741 | status = chip->waitfunc(mtd, chip); | |
2742 | if (status & NAND_STATUS_FAIL) | |
2743 | return -EIO; | |
2744 | return 0; | |
2745 | } | |
2746 | ||
2747 | /** | |
2748 | * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand | |
2749 | * @mtd: MTD device structure | |
2750 | * @chip: nand chip info structure | |
2751 | * @addr: feature address. | |
2752 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
2753 | */ | |
2754 | static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, | |
2755 | int addr, uint8_t *subfeature_param) | |
2756 | { | |
2757 | if (!chip->onfi_version) | |
2758 | return -EINVAL; | |
2759 | ||
2760 | /* clear the sub feature parameters */ | |
2761 | memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN); | |
2762 | ||
2763 | chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1); | |
2764 | chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN); | |
2765 | return 0; | |
2766 | } | |
2767 | ||
962034f4 VW |
2768 | /** |
2769 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
8b6e50c9 | 2770 | * @mtd: MTD device structure |
962034f4 VW |
2771 | */ |
2772 | static int nand_suspend(struct mtd_info *mtd) | |
2773 | { | |
6a8214aa | 2774 | return nand_get_device(mtd, FL_PM_SUSPENDED); |
962034f4 VW |
2775 | } |
2776 | ||
2777 | /** | |
2778 | * nand_resume - [MTD Interface] Resume the NAND flash | |
8b6e50c9 | 2779 | * @mtd: MTD device structure |
962034f4 VW |
2780 | */ |
2781 | static void nand_resume(struct mtd_info *mtd) | |
2782 | { | |
ace4dfee | 2783 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2784 | |
ace4dfee | 2785 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
2786 | nand_release_device(mtd); |
2787 | else | |
d0370219 BN |
2788 | pr_err("%s called for a chip which is not in suspended state\n", |
2789 | __func__); | |
962034f4 VW |
2790 | } |
2791 | ||
8b6e50c9 | 2792 | /* Set default functions */ |
ace4dfee | 2793 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 2794 | { |
1da177e4 | 2795 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
2796 | if (!chip->chip_delay) |
2797 | chip->chip_delay = 20; | |
1da177e4 LT |
2798 | |
2799 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
2800 | if (chip->cmdfunc == NULL) |
2801 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
2802 | |
2803 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
2804 | if (chip->waitfunc == NULL) |
2805 | chip->waitfunc = nand_wait; | |
2806 | ||
2807 | if (!chip->select_chip) | |
2808 | chip->select_chip = nand_select_chip; | |
2809 | if (!chip->read_byte) | |
2810 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; | |
2811 | if (!chip->read_word) | |
2812 | chip->read_word = nand_read_word; | |
2813 | if (!chip->block_bad) | |
2814 | chip->block_bad = nand_block_bad; | |
2815 | if (!chip->block_markbad) | |
2816 | chip->block_markbad = nand_default_block_markbad; | |
2817 | if (!chip->write_buf) | |
2818 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; | |
2819 | if (!chip->read_buf) | |
2820 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; | |
ace4dfee TG |
2821 | if (!chip->scan_bbt) |
2822 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
2823 | |
2824 | if (!chip->controller) { | |
2825 | chip->controller = &chip->hwcontrol; | |
2826 | spin_lock_init(&chip->controller->lock); | |
2827 | init_waitqueue_head(&chip->controller->wq); | |
2828 | } | |
2829 | ||
7aa65bfd TG |
2830 | } |
2831 | ||
8b6e50c9 | 2832 | /* Sanitize ONFI strings so we can safely print them */ |
d1e1f4e4 FF |
2833 | static void sanitize_string(uint8_t *s, size_t len) |
2834 | { | |
2835 | ssize_t i; | |
2836 | ||
8b6e50c9 | 2837 | /* Null terminate */ |
d1e1f4e4 FF |
2838 | s[len - 1] = 0; |
2839 | ||
8b6e50c9 | 2840 | /* Remove non printable chars */ |
d1e1f4e4 FF |
2841 | for (i = 0; i < len - 1; i++) { |
2842 | if (s[i] < ' ' || s[i] > 127) | |
2843 | s[i] = '?'; | |
2844 | } | |
2845 | ||
8b6e50c9 | 2846 | /* Remove trailing spaces */ |
d1e1f4e4 FF |
2847 | strim(s); |
2848 | } | |
2849 | ||
2850 | static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) | |
2851 | { | |
2852 | int i; | |
2853 | while (len--) { | |
2854 | crc ^= *p++ << 8; | |
2855 | for (i = 0; i < 8; i++) | |
2856 | crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); | |
2857 | } | |
2858 | ||
2859 | return crc; | |
2860 | } | |
2861 | ||
6fb277ba | 2862 | /* |
8b6e50c9 | 2863 | * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. |
6fb277ba FF |
2864 | */ |
2865 | static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, | |
08c248fb | 2866 | int *busw) |
6fb277ba FF |
2867 | { |
2868 | struct nand_onfi_params *p = &chip->onfi_params; | |
2869 | int i; | |
2870 | int val; | |
2871 | ||
0ce82b7f MC |
2872 | /* ONFI need to be probed in 8 bits mode, and 16 bits should be selected with NAND_BUSWIDTH_AUTO */ |
2873 | if (chip->options & NAND_BUSWIDTH_16) { | |
2874 | pr_err("Trying ONFI probe in 16 bits mode, aborting !\n"); | |
2875 | return 0; | |
2876 | } | |
7854d3f7 | 2877 | /* Try ONFI for unknown chip or LP */ |
6fb277ba FF |
2878 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); |
2879 | if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || | |
2880 | chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') | |
2881 | return 0; | |
2882 | ||
6fb277ba FF |
2883 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); |
2884 | for (i = 0; i < 3; i++) { | |
2885 | chip->read_buf(mtd, (uint8_t *)p, sizeof(*p)); | |
2886 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == | |
2887 | le16_to_cpu(p->crc)) { | |
9a4d4d69 | 2888 | pr_info("ONFI param page %d valid\n", i); |
6fb277ba FF |
2889 | break; |
2890 | } | |
2891 | } | |
2892 | ||
2893 | if (i == 3) | |
2894 | return 0; | |
2895 | ||
8b6e50c9 | 2896 | /* Check version */ |
6fb277ba | 2897 | val = le16_to_cpu(p->revision); |
b7b1a29d BN |
2898 | if (val & (1 << 5)) |
2899 | chip->onfi_version = 23; | |
2900 | else if (val & (1 << 4)) | |
6fb277ba FF |
2901 | chip->onfi_version = 22; |
2902 | else if (val & (1 << 3)) | |
2903 | chip->onfi_version = 21; | |
2904 | else if (val & (1 << 2)) | |
2905 | chip->onfi_version = 20; | |
b7b1a29d | 2906 | else if (val & (1 << 1)) |
6fb277ba | 2907 | chip->onfi_version = 10; |
b7b1a29d BN |
2908 | else |
2909 | chip->onfi_version = 0; | |
2910 | ||
2911 | if (!chip->onfi_version) { | |
d0370219 | 2912 | pr_info("%s: unsupported ONFI version: %d\n", __func__, val); |
b7b1a29d BN |
2913 | return 0; |
2914 | } | |
6fb277ba FF |
2915 | |
2916 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
2917 | sanitize_string(p->model, sizeof(p->model)); | |
2918 | if (!mtd->name) | |
2919 | mtd->name = p->model; | |
2920 | mtd->writesize = le32_to_cpu(p->byte_per_page); | |
2921 | mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize; | |
2922 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); | |
63795755 MC |
2923 | chip->chipsize = le32_to_cpu(p->blocks_per_lun); |
2924 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; | |
08c248fb | 2925 | *busw = 0; |
6fb277ba | 2926 | if (le16_to_cpu(p->features) & 1) |
08c248fb | 2927 | *busw = NAND_BUSWIDTH_16; |
6fb277ba | 2928 | |
d42b5de3 | 2929 | pr_info("ONFI flash detected\n"); |
6fb277ba FF |
2930 | return 1; |
2931 | } | |
2932 | ||
e3b88bd6 BN |
2933 | /* |
2934 | * nand_id_has_period - Check if an ID string has a given wraparound period | |
2935 | * @id_data: the ID string | |
2936 | * @arrlen: the length of the @id_data array | |
2937 | * @period: the period of repitition | |
2938 | * | |
2939 | * Check if an ID string is repeated within a given sequence of bytes at | |
2940 | * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a | |
d4d4f1bf | 2941 | * period of 3). This is a helper function for nand_id_len(). Returns non-zero |
e3b88bd6 BN |
2942 | * if the repetition has a period of @period; otherwise, returns zero. |
2943 | */ | |
2944 | static int nand_id_has_period(u8 *id_data, int arrlen, int period) | |
2945 | { | |
2946 | int i, j; | |
2947 | for (i = 0; i < period; i++) | |
2948 | for (j = i + period; j < arrlen; j += period) | |
2949 | if (id_data[i] != id_data[j]) | |
2950 | return 0; | |
2951 | return 1; | |
2952 | } | |
2953 | ||
2954 | /* | |
2955 | * nand_id_len - Get the length of an ID string returned by CMD_READID | |
2956 | * @id_data: the ID string | |
2957 | * @arrlen: the length of the @id_data array | |
2958 | ||
2959 | * Returns the length of the ID string, according to known wraparound/trailing | |
2960 | * zero patterns. If no pattern exists, returns the length of the array. | |
2961 | */ | |
2962 | static int nand_id_len(u8 *id_data, int arrlen) | |
2963 | { | |
2964 | int last_nonzero, period; | |
2965 | ||
2966 | /* Find last non-zero byte */ | |
2967 | for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) | |
2968 | if (id_data[last_nonzero]) | |
2969 | break; | |
2970 | ||
2971 | /* All zeros */ | |
2972 | if (last_nonzero < 0) | |
2973 | return 0; | |
2974 | ||
2975 | /* Calculate wraparound period */ | |
2976 | for (period = 1; period < arrlen; period++) | |
2977 | if (nand_id_has_period(id_data, arrlen, period)) | |
2978 | break; | |
2979 | ||
2980 | /* There's a repeated pattern */ | |
2981 | if (period < arrlen) | |
2982 | return period; | |
2983 | ||
2984 | /* There are trailing zeros */ | |
2985 | if (last_nonzero < arrlen - 1) | |
2986 | return last_nonzero + 1; | |
2987 | ||
2988 | /* No pattern detected */ | |
2989 | return arrlen; | |
2990 | } | |
2991 | ||
fc09bbc0 BN |
2992 | /* |
2993 | * Many new NAND share similar device ID codes, which represent the size of the | |
2994 | * chip. The rest of the parameters must be decoded according to generic or | |
2995 | * manufacturer-specific "extended ID" decoding patterns. | |
2996 | */ | |
2997 | static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, | |
2998 | u8 id_data[8], int *busw) | |
2999 | { | |
e3b88bd6 | 3000 | int extid, id_len; |
fc09bbc0 BN |
3001 | /* The 3rd id byte holds MLC / multichip data */ |
3002 | chip->cellinfo = id_data[2]; | |
3003 | /* The 4th id byte is the important one */ | |
3004 | extid = id_data[3]; | |
3005 | ||
e3b88bd6 BN |
3006 | id_len = nand_id_len(id_data, 8); |
3007 | ||
fc09bbc0 BN |
3008 | /* |
3009 | * Field definitions are in the following datasheets: | |
3010 | * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) | |
af451af4 | 3011 | * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) |
73ca392f | 3012 | * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) |
fc09bbc0 | 3013 | * |
af451af4 BN |
3014 | * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung |
3015 | * ID to decide what to do. | |
fc09bbc0 | 3016 | */ |
af451af4 | 3017 | if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && |
6924d99f | 3018 | (chip->cellinfo & NAND_CI_CELLTYPE_MSK) && |
af451af4 | 3019 | id_data[5] != 0x00) { |
fc09bbc0 BN |
3020 | /* Calc pagesize */ |
3021 | mtd->writesize = 2048 << (extid & 0x03); | |
3022 | extid >>= 2; | |
3023 | /* Calc oobsize */ | |
e2d3a35e | 3024 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { |
fc09bbc0 BN |
3025 | case 1: |
3026 | mtd->oobsize = 128; | |
3027 | break; | |
3028 | case 2: | |
3029 | mtd->oobsize = 218; | |
3030 | break; | |
3031 | case 3: | |
3032 | mtd->oobsize = 400; | |
3033 | break; | |
e2d3a35e | 3034 | case 4: |
fc09bbc0 BN |
3035 | mtd->oobsize = 436; |
3036 | break; | |
e2d3a35e BN |
3037 | case 5: |
3038 | mtd->oobsize = 512; | |
3039 | break; | |
3040 | case 6: | |
3041 | default: /* Other cases are "reserved" (unknown) */ | |
3042 | mtd->oobsize = 640; | |
3043 | break; | |
fc09bbc0 BN |
3044 | } |
3045 | extid >>= 2; | |
3046 | /* Calc blocksize */ | |
3047 | mtd->erasesize = (128 * 1024) << | |
3048 | (((extid >> 1) & 0x04) | (extid & 0x03)); | |
3049 | *busw = 0; | |
73ca392f BN |
3050 | } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && |
3051 | (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { | |
3052 | unsigned int tmp; | |
3053 | ||
3054 | /* Calc pagesize */ | |
3055 | mtd->writesize = 2048 << (extid & 0x03); | |
3056 | extid >>= 2; | |
3057 | /* Calc oobsize */ | |
3058 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { | |
3059 | case 0: | |
3060 | mtd->oobsize = 128; | |
3061 | break; | |
3062 | case 1: | |
3063 | mtd->oobsize = 224; | |
3064 | break; | |
3065 | case 2: | |
3066 | mtd->oobsize = 448; | |
3067 | break; | |
3068 | case 3: | |
3069 | mtd->oobsize = 64; | |
3070 | break; | |
3071 | case 4: | |
3072 | mtd->oobsize = 32; | |
3073 | break; | |
3074 | case 5: | |
3075 | mtd->oobsize = 16; | |
3076 | break; | |
3077 | default: | |
3078 | mtd->oobsize = 640; | |
3079 | break; | |
3080 | } | |
3081 | extid >>= 2; | |
3082 | /* Calc blocksize */ | |
3083 | tmp = ((extid >> 1) & 0x04) | (extid & 0x03); | |
3084 | if (tmp < 0x03) | |
3085 | mtd->erasesize = (128 * 1024) << tmp; | |
3086 | else if (tmp == 0x03) | |
3087 | mtd->erasesize = 768 * 1024; | |
3088 | else | |
3089 | mtd->erasesize = (64 * 1024) << tmp; | |
3090 | *busw = 0; | |
fc09bbc0 BN |
3091 | } else { |
3092 | /* Calc pagesize */ | |
3093 | mtd->writesize = 1024 << (extid & 0x03); | |
3094 | extid >>= 2; | |
3095 | /* Calc oobsize */ | |
3096 | mtd->oobsize = (8 << (extid & 0x01)) * | |
3097 | (mtd->writesize >> 9); | |
3098 | extid >>= 2; | |
3099 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
3100 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
3101 | extid >>= 2; | |
3102 | /* Get buswidth information */ | |
3103 | *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
3104 | } | |
3105 | } | |
3106 | ||
f23a481c BN |
3107 | /* |
3108 | * Old devices have chip data hardcoded in the device ID table. nand_decode_id | |
3109 | * decodes a matching ID table entry and assigns the MTD size parameters for | |
3110 | * the chip. | |
3111 | */ | |
3112 | static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, | |
3113 | struct nand_flash_dev *type, u8 id_data[8], | |
3114 | int *busw) | |
3115 | { | |
3116 | int maf_id = id_data[0]; | |
3117 | ||
3118 | mtd->erasesize = type->erasesize; | |
3119 | mtd->writesize = type->pagesize; | |
3120 | mtd->oobsize = mtd->writesize / 32; | |
3121 | *busw = type->options & NAND_BUSWIDTH_16; | |
3122 | ||
3123 | /* | |
3124 | * Check for Spansion/AMD ID + repeating 5th, 6th byte since | |
3125 | * some Spansion chips have erasesize that conflicts with size | |
3126 | * listed in nand_ids table. | |
3127 | * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) | |
3128 | */ | |
3129 | if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00 | |
3130 | && id_data[6] == 0x00 && id_data[7] == 0x00 | |
3131 | && mtd->writesize == 512) { | |
3132 | mtd->erasesize = 128 * 1024; | |
3133 | mtd->erasesize <<= ((id_data[3] & 0x03) << 1); | |
3134 | } | |
3135 | } | |
3136 | ||
7e74c2d7 BN |
3137 | /* |
3138 | * Set the bad block marker/indicator (BBM/BBI) patterns according to some | |
3139 | * heuristic patterns using various detected parameters (e.g., manufacturer, | |
3140 | * page size, cell-type information). | |
3141 | */ | |
3142 | static void nand_decode_bbm_options(struct mtd_info *mtd, | |
3143 | struct nand_chip *chip, u8 id_data[8]) | |
3144 | { | |
3145 | int maf_id = id_data[0]; | |
3146 | ||
3147 | /* Set the bad block position */ | |
3148 | if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) | |
3149 | chip->badblockpos = NAND_LARGE_BADBLOCK_POS; | |
3150 | else | |
3151 | chip->badblockpos = NAND_SMALL_BADBLOCK_POS; | |
3152 | ||
3153 | /* | |
3154 | * Bad block marker is stored in the last page of each block on Samsung | |
3155 | * and Hynix MLC devices; stored in first two pages of each block on | |
3156 | * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, | |
3157 | * AMD/Spansion, and Macronix. All others scan only the first page. | |
3158 | */ | |
3159 | if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) && | |
3160 | (maf_id == NAND_MFR_SAMSUNG || | |
3161 | maf_id == NAND_MFR_HYNIX)) | |
3162 | chip->bbt_options |= NAND_BBT_SCANLASTPAGE; | |
3163 | else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) && | |
3164 | (maf_id == NAND_MFR_SAMSUNG || | |
3165 | maf_id == NAND_MFR_HYNIX || | |
3166 | maf_id == NAND_MFR_TOSHIBA || | |
3167 | maf_id == NAND_MFR_AMD || | |
3168 | maf_id == NAND_MFR_MACRONIX)) || | |
3169 | (mtd->writesize == 2048 && | |
3170 | maf_id == NAND_MFR_MICRON)) | |
3171 | chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; | |
3172 | } | |
3173 | ||
7aa65bfd | 3174 | /* |
8b6e50c9 | 3175 | * Get the flash and manufacturer id and lookup if the type is supported. |
7aa65bfd TG |
3176 | */ |
3177 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 3178 | struct nand_chip *chip, |
7351d3a5 FF |
3179 | int busw, |
3180 | int *maf_id, int *dev_id, | |
5e81e88a | 3181 | struct nand_flash_dev *type) |
7aa65bfd | 3182 | { |
d1e1f4e4 | 3183 | int i, maf_idx; |
426c457a | 3184 | u8 id_data[8]; |
1da177e4 LT |
3185 | |
3186 | /* Select the device */ | |
ace4dfee | 3187 | chip->select_chip(mtd, 0); |
1da177e4 | 3188 | |
ef89a880 KB |
3189 | /* |
3190 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
8b6e50c9 | 3191 | * after power-up. |
ef89a880 KB |
3192 | */ |
3193 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
3194 | ||
1da177e4 | 3195 | /* Send the command for reading device ID */ |
ace4dfee | 3196 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
3197 | |
3198 | /* Read manufacturer and device IDs */ | |
ace4dfee | 3199 | *maf_id = chip->read_byte(mtd); |
d1e1f4e4 | 3200 | *dev_id = chip->read_byte(mtd); |
1da177e4 | 3201 | |
8b6e50c9 BN |
3202 | /* |
3203 | * Try again to make sure, as some systems the bus-hold or other | |
ed8165c7 BD |
3204 | * interface concerns can cause random data which looks like a |
3205 | * possibly credible NAND flash to appear. If the two results do | |
3206 | * not match, ignore the device completely. | |
3207 | */ | |
3208 | ||
3209 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
3210 | ||
4aef9b78 BN |
3211 | /* Read entire ID string */ |
3212 | for (i = 0; i < 8; i++) | |
426c457a | 3213 | id_data[i] = chip->read_byte(mtd); |
ed8165c7 | 3214 | |
d1e1f4e4 | 3215 | if (id_data[0] != *maf_id || id_data[1] != *dev_id) { |
9a4d4d69 | 3216 | pr_info("%s: second ID read did not match " |
d0370219 BN |
3217 | "%02x,%02x against %02x,%02x\n", __func__, |
3218 | *maf_id, *dev_id, id_data[0], id_data[1]); | |
ed8165c7 BD |
3219 | return ERR_PTR(-ENODEV); |
3220 | } | |
3221 | ||
7aa65bfd | 3222 | if (!type) |
5e81e88a DW |
3223 | type = nand_flash_ids; |
3224 | ||
3225 | for (; type->name != NULL; type++) | |
d1e1f4e4 | 3226 | if (*dev_id == type->id) |
f8ac0414 | 3227 | break; |
5e81e88a | 3228 | |
d1e1f4e4 FF |
3229 | chip->onfi_version = 0; |
3230 | if (!type->name || !type->pagesize) { | |
6fb277ba | 3231 | /* Check is chip is ONFI compliant */ |
47450b35 | 3232 | if (nand_flash_detect_onfi(mtd, chip, &busw)) |
6fb277ba | 3233 | goto ident_done; |
d1e1f4e4 FF |
3234 | } |
3235 | ||
5e81e88a | 3236 | if (!type->name) |
7aa65bfd TG |
3237 | return ERR_PTR(-ENODEV); |
3238 | ||
ba0251fe TG |
3239 | if (!mtd->name) |
3240 | mtd->name = type->name; | |
3241 | ||
69423d99 | 3242 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd | 3243 | |
12a40a57 | 3244 | if (!type->pagesize && chip->init_size) { |
8b6e50c9 | 3245 | /* Set the pagesize, oobsize, erasesize by the driver */ |
12a40a57 HS |
3246 | busw = chip->init_size(mtd, chip, id_data); |
3247 | } else if (!type->pagesize) { | |
fc09bbc0 BN |
3248 | /* Decode parameters from extended ID */ |
3249 | nand_decode_ext_id(mtd, chip, id_data, &busw); | |
7aa65bfd | 3250 | } else { |
f23a481c | 3251 | nand_decode_id(mtd, chip, type, id_data, &busw); |
7aa65bfd | 3252 | } |
bf7a01bf BN |
3253 | /* Get chip options */ |
3254 | chip->options |= type->options; | |
d1e1f4e4 | 3255 | |
8b6e50c9 BN |
3256 | /* |
3257 | * Check if chip is not a Samsung device. Do not clear the | |
3258 | * options for chips which do not have an extended id. | |
d1e1f4e4 FF |
3259 | */ |
3260 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) | |
3261 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; | |
3262 | ident_done: | |
3263 | ||
7aa65bfd | 3264 | /* Try to identify manufacturer */ |
9a909867 | 3265 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { |
7aa65bfd TG |
3266 | if (nand_manuf_ids[maf_idx].id == *maf_id) |
3267 | break; | |
3268 | } | |
0ea4a755 | 3269 | |
64b37b2a MC |
3270 | if (chip->options & NAND_BUSWIDTH_AUTO) { |
3271 | WARN_ON(chip->options & NAND_BUSWIDTH_16); | |
3272 | chip->options |= busw; | |
3273 | nand_set_defaults(chip, busw); | |
3274 | } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { | |
3275 | /* | |
3276 | * Check, if buswidth is correct. Hardware drivers should set | |
3277 | * chip correct! | |
3278 | */ | |
9a4d4d69 | 3279 | pr_info("NAND device: Manufacturer ID:" |
d0370219 BN |
3280 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, |
3281 | *dev_id, nand_manuf_ids[maf_idx].name, mtd->name); | |
9a4d4d69 | 3282 | pr_warn("NAND bus width %d instead %d bit\n", |
d0370219 BN |
3283 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
3284 | busw ? 16 : 8); | |
7aa65bfd TG |
3285 | return ERR_PTR(-EINVAL); |
3286 | } | |
61b03bd7 | 3287 | |
7e74c2d7 BN |
3288 | nand_decode_bbm_options(mtd, chip, id_data); |
3289 | ||
7aa65bfd | 3290 | /* Calculate the address shift from the page size */ |
ace4dfee | 3291 | chip->page_shift = ffs(mtd->writesize) - 1; |
8b6e50c9 | 3292 | /* Convert chipsize to number of pages per chip -1 */ |
ace4dfee | 3293 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 3294 | |
ace4dfee | 3295 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 3296 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
3297 | if (chip->chipsize & 0xffffffff) |
3298 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
7351d3a5 FF |
3299 | else { |
3300 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); | |
3301 | chip->chip_shift += 32 - 1; | |
3302 | } | |
1da177e4 | 3303 | |
26d9be11 AB |
3304 | chip->badblockbits = 8; |
3305 | ||
7aa65bfd | 3306 | /* Check for AND chips with 4 page planes */ |
ace4dfee TG |
3307 | if (chip->options & NAND_4PAGE_ARRAY) |
3308 | chip->erase_cmd = multi_erase_cmd; | |
7aa65bfd | 3309 | else |
ace4dfee | 3310 | chip->erase_cmd = single_erase_cmd; |
7aa65bfd | 3311 | |
8b6e50c9 | 3312 | /* Do not replace user supplied command function! */ |
ace4dfee TG |
3313 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
3314 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd | 3315 | |
886bd33d | 3316 | pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s)," |
2fd71a29 | 3317 | " %dMiB, page size: %d, OOB size: %d\n", |
886bd33d HS |
3318 | *maf_id, *dev_id, nand_manuf_ids[maf_idx].name, |
3319 | chip->onfi_version ? chip->onfi_params.model : type->name, | |
2fd71a29 | 3320 | (int)(chip->chipsize >> 20), mtd->writesize, mtd->oobsize); |
7aa65bfd TG |
3321 | |
3322 | return type; | |
3323 | } | |
3324 | ||
7aa65bfd | 3325 | /** |
3b85c321 | 3326 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
8b6e50c9 BN |
3327 | * @mtd: MTD device structure |
3328 | * @maxchips: number of chips to scan for | |
3329 | * @table: alternative NAND ID table | |
7aa65bfd | 3330 | * |
8b6e50c9 BN |
3331 | * This is the first phase of the normal nand_scan() function. It reads the |
3332 | * flash ID and sets up MTD fields accordingly. | |
7aa65bfd | 3333 | * |
3b85c321 | 3334 | * The mtd->owner field must be set to the module of the caller. |
7aa65bfd | 3335 | */ |
5e81e88a DW |
3336 | int nand_scan_ident(struct mtd_info *mtd, int maxchips, |
3337 | struct nand_flash_dev *table) | |
7aa65bfd | 3338 | { |
d1e1f4e4 | 3339 | int i, busw, nand_maf_id, nand_dev_id; |
ace4dfee | 3340 | struct nand_chip *chip = mtd->priv; |
7aa65bfd TG |
3341 | struct nand_flash_dev *type; |
3342 | ||
7aa65bfd | 3343 | /* Get buswidth to select the correct functions */ |
ace4dfee | 3344 | busw = chip->options & NAND_BUSWIDTH_16; |
7aa65bfd | 3345 | /* Set the default functions */ |
ace4dfee | 3346 | nand_set_defaults(chip, busw); |
7aa65bfd TG |
3347 | |
3348 | /* Read the flash type */ | |
7351d3a5 FF |
3349 | type = nand_get_flash_type(mtd, chip, busw, |
3350 | &nand_maf_id, &nand_dev_id, table); | |
7aa65bfd TG |
3351 | |
3352 | if (IS_ERR(type)) { | |
b1c6e6db | 3353 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
d0370219 | 3354 | pr_warn("No NAND device found\n"); |
ace4dfee | 3355 | chip->select_chip(mtd, -1); |
7aa65bfd | 3356 | return PTR_ERR(type); |
1da177e4 LT |
3357 | } |
3358 | ||
07300164 HS |
3359 | chip->select_chip(mtd, -1); |
3360 | ||
7aa65bfd | 3361 | /* Check for a chip array */ |
e0c7d767 | 3362 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 3363 | chip->select_chip(mtd, i); |
ef89a880 KB |
3364 | /* See comment in nand_get_flash_type for reset */ |
3365 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1da177e4 | 3366 | /* Send the command for reading device ID */ |
ace4dfee | 3367 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 3368 | /* Read manufacturer and device IDs */ |
ace4dfee | 3369 | if (nand_maf_id != chip->read_byte(mtd) || |
07300164 HS |
3370 | nand_dev_id != chip->read_byte(mtd)) { |
3371 | chip->select_chip(mtd, -1); | |
1da177e4 | 3372 | break; |
07300164 HS |
3373 | } |
3374 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
3375 | } |
3376 | if (i > 1) | |
9a4d4d69 | 3377 | pr_info("%d NAND chips detected\n", i); |
61b03bd7 | 3378 | |
1da177e4 | 3379 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
3380 | chip->numchips = i; |
3381 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 3382 | |
3b85c321 DW |
3383 | return 0; |
3384 | } | |
7351d3a5 | 3385 | EXPORT_SYMBOL(nand_scan_ident); |
3b85c321 DW |
3386 | |
3387 | ||
3388 | /** | |
3389 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
8b6e50c9 | 3390 | * @mtd: MTD device structure |
3b85c321 | 3391 | * |
8b6e50c9 BN |
3392 | * This is the second phase of the normal nand_scan() function. It fills out |
3393 | * all the uninitialized function pointers with the defaults and scans for a | |
3394 | * bad block table if appropriate. | |
3b85c321 DW |
3395 | */ |
3396 | int nand_scan_tail(struct mtd_info *mtd) | |
3397 | { | |
3398 | int i; | |
3399 | struct nand_chip *chip = mtd->priv; | |
3400 | ||
e2414f4c BN |
3401 | /* New bad blocks should be marked in OOB, flash-based BBT, or both */ |
3402 | BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && | |
3403 | !(chip->bbt_options & NAND_BBT_USE_FLASH)); | |
3404 | ||
4bf63fcb DW |
3405 | if (!(chip->options & NAND_OWN_BUFFERS)) |
3406 | chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); | |
3407 | if (!chip->buffers) | |
3408 | return -ENOMEM; | |
3409 | ||
7dcdcbef | 3410 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 3411 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 3412 | |
7aa65bfd | 3413 | /* |
8b6e50c9 | 3414 | * If no default placement scheme is given, select an appropriate one. |
7aa65bfd | 3415 | */ |
193bd400 | 3416 | if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) { |
61b03bd7 | 3417 | switch (mtd->oobsize) { |
1da177e4 | 3418 | case 8: |
5bd34c09 | 3419 | chip->ecc.layout = &nand_oob_8; |
1da177e4 LT |
3420 | break; |
3421 | case 16: | |
5bd34c09 | 3422 | chip->ecc.layout = &nand_oob_16; |
1da177e4 LT |
3423 | break; |
3424 | case 64: | |
5bd34c09 | 3425 | chip->ecc.layout = &nand_oob_64; |
1da177e4 | 3426 | break; |
81ec5364 TG |
3427 | case 128: |
3428 | chip->ecc.layout = &nand_oob_128; | |
3429 | break; | |
1da177e4 | 3430 | default: |
d0370219 BN |
3431 | pr_warn("No oob scheme defined for oobsize %d\n", |
3432 | mtd->oobsize); | |
1da177e4 LT |
3433 | BUG(); |
3434 | } | |
3435 | } | |
61b03bd7 | 3436 | |
956e944c DW |
3437 | if (!chip->write_page) |
3438 | chip->write_page = nand_write_page; | |
3439 | ||
7db03ecc HS |
3440 | /* set for ONFI nand */ |
3441 | if (!chip->onfi_set_features) | |
3442 | chip->onfi_set_features = nand_onfi_set_features; | |
3443 | if (!chip->onfi_get_features) | |
3444 | chip->onfi_get_features = nand_onfi_get_features; | |
3445 | ||
61b03bd7 | 3446 | /* |
8b6e50c9 | 3447 | * Check ECC mode, default to software if 3byte/512byte hardware ECC is |
7aa65bfd | 3448 | * selected and we have 256 byte pagesize fallback to software ECC |
e0c7d767 | 3449 | */ |
956e944c | 3450 | |
ace4dfee | 3451 | switch (chip->ecc.mode) { |
6e0cb135 SN |
3452 | case NAND_ECC_HW_OOB_FIRST: |
3453 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
3454 | if (!chip->ecc.calculate || !chip->ecc.correct || | |
3455 | !chip->ecc.hwctl) { | |
9a4d4d69 | 3456 | pr_warn("No ECC functions supplied; " |
d0370219 | 3457 | "hardware ECC not possible\n"); |
6e0cb135 SN |
3458 | BUG(); |
3459 | } | |
3460 | if (!chip->ecc.read_page) | |
3461 | chip->ecc.read_page = nand_read_page_hwecc_oob_first; | |
3462 | ||
6dfc6d25 | 3463 | case NAND_ECC_HW: |
8b6e50c9 | 3464 | /* Use standard hwecc read page function? */ |
f5bbdacc TG |
3465 | if (!chip->ecc.read_page) |
3466 | chip->ecc.read_page = nand_read_page_hwecc; | |
f75e5097 TG |
3467 | if (!chip->ecc.write_page) |
3468 | chip->ecc.write_page = nand_write_page_hwecc; | |
52ff49df DB |
3469 | if (!chip->ecc.read_page_raw) |
3470 | chip->ecc.read_page_raw = nand_read_page_raw; | |
3471 | if (!chip->ecc.write_page_raw) | |
3472 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b TG |
3473 | if (!chip->ecc.read_oob) |
3474 | chip->ecc.read_oob = nand_read_oob_std; | |
3475 | if (!chip->ecc.write_oob) | |
3476 | chip->ecc.write_oob = nand_write_oob_std; | |
f5bbdacc | 3477 | |
6dfc6d25 | 3478 | case NAND_ECC_HW_SYNDROME: |
78b65179 SW |
3479 | if ((!chip->ecc.calculate || !chip->ecc.correct || |
3480 | !chip->ecc.hwctl) && | |
3481 | (!chip->ecc.read_page || | |
1c45f604 | 3482 | chip->ecc.read_page == nand_read_page_hwecc || |
78b65179 | 3483 | !chip->ecc.write_page || |
1c45f604 | 3484 | chip->ecc.write_page == nand_write_page_hwecc)) { |
9a4d4d69 | 3485 | pr_warn("No ECC functions supplied; " |
d0370219 | 3486 | "hardware ECC not possible\n"); |
6dfc6d25 TG |
3487 | BUG(); |
3488 | } | |
8b6e50c9 | 3489 | /* Use standard syndrome read/write page function? */ |
f5bbdacc TG |
3490 | if (!chip->ecc.read_page) |
3491 | chip->ecc.read_page = nand_read_page_syndrome; | |
f75e5097 TG |
3492 | if (!chip->ecc.write_page) |
3493 | chip->ecc.write_page = nand_write_page_syndrome; | |
52ff49df DB |
3494 | if (!chip->ecc.read_page_raw) |
3495 | chip->ecc.read_page_raw = nand_read_page_raw_syndrome; | |
3496 | if (!chip->ecc.write_page_raw) | |
3497 | chip->ecc.write_page_raw = nand_write_page_raw_syndrome; | |
7bc3312b TG |
3498 | if (!chip->ecc.read_oob) |
3499 | chip->ecc.read_oob = nand_read_oob_syndrome; | |
3500 | if (!chip->ecc.write_oob) | |
3501 | chip->ecc.write_oob = nand_write_oob_syndrome; | |
f5bbdacc | 3502 | |
e2788c98 MD |
3503 | if (mtd->writesize >= chip->ecc.size) { |
3504 | if (!chip->ecc.strength) { | |
3505 | pr_warn("Driver must set ecc.strength when using hardware ECC\n"); | |
3506 | BUG(); | |
3507 | } | |
6dfc6d25 | 3508 | break; |
e2788c98 | 3509 | } |
9a4d4d69 | 3510 | pr_warn("%d byte HW ECC not possible on " |
d0370219 BN |
3511 | "%d byte page size, fallback to SW ECC\n", |
3512 | chip->ecc.size, mtd->writesize); | |
ace4dfee | 3513 | chip->ecc.mode = NAND_ECC_SOFT; |
61b03bd7 | 3514 | |
6dfc6d25 | 3515 | case NAND_ECC_SOFT: |
ace4dfee TG |
3516 | chip->ecc.calculate = nand_calculate_ecc; |
3517 | chip->ecc.correct = nand_correct_data; | |
f5bbdacc | 3518 | chip->ecc.read_page = nand_read_page_swecc; |
3d459559 | 3519 | chip->ecc.read_subpage = nand_read_subpage; |
f75e5097 | 3520 | chip->ecc.write_page = nand_write_page_swecc; |
52ff49df DB |
3521 | chip->ecc.read_page_raw = nand_read_page_raw; |
3522 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b TG |
3523 | chip->ecc.read_oob = nand_read_oob_std; |
3524 | chip->ecc.write_oob = nand_write_oob_std; | |
9a73290d SV |
3525 | if (!chip->ecc.size) |
3526 | chip->ecc.size = 256; | |
ace4dfee | 3527 | chip->ecc.bytes = 3; |
6a918bad | 3528 | chip->ecc.strength = 1; |
1da177e4 | 3529 | break; |
61b03bd7 | 3530 | |
193bd400 ID |
3531 | case NAND_ECC_SOFT_BCH: |
3532 | if (!mtd_nand_has_bch()) { | |
9a4d4d69 | 3533 | pr_warn("CONFIG_MTD_ECC_BCH not enabled\n"); |
193bd400 ID |
3534 | BUG(); |
3535 | } | |
3536 | chip->ecc.calculate = nand_bch_calculate_ecc; | |
3537 | chip->ecc.correct = nand_bch_correct_data; | |
3538 | chip->ecc.read_page = nand_read_page_swecc; | |
3539 | chip->ecc.read_subpage = nand_read_subpage; | |
3540 | chip->ecc.write_page = nand_write_page_swecc; | |
3541 | chip->ecc.read_page_raw = nand_read_page_raw; | |
3542 | chip->ecc.write_page_raw = nand_write_page_raw; | |
3543 | chip->ecc.read_oob = nand_read_oob_std; | |
3544 | chip->ecc.write_oob = nand_write_oob_std; | |
3545 | /* | |
3546 | * Board driver should supply ecc.size and ecc.bytes values to | |
3547 | * select how many bits are correctable; see nand_bch_init() | |
8b6e50c9 BN |
3548 | * for details. Otherwise, default to 4 bits for large page |
3549 | * devices. | |
193bd400 ID |
3550 | */ |
3551 | if (!chip->ecc.size && (mtd->oobsize >= 64)) { | |
3552 | chip->ecc.size = 512; | |
3553 | chip->ecc.bytes = 7; | |
3554 | } | |
3555 | chip->ecc.priv = nand_bch_init(mtd, | |
3556 | chip->ecc.size, | |
3557 | chip->ecc.bytes, | |
3558 | &chip->ecc.layout); | |
3559 | if (!chip->ecc.priv) { | |
9a4d4d69 | 3560 | pr_warn("BCH ECC initialization failed!\n"); |
193bd400 ID |
3561 | BUG(); |
3562 | } | |
6a918bad | 3563 | chip->ecc.strength = |
e2788c98 | 3564 | chip->ecc.bytes * 8 / fls(8 * chip->ecc.size); |
193bd400 ID |
3565 | break; |
3566 | ||
61b03bd7 | 3567 | case NAND_ECC_NONE: |
9a4d4d69 | 3568 | pr_warn("NAND_ECC_NONE selected by board driver. " |
d0370219 | 3569 | "This is not recommended!\n"); |
8593fbc6 TG |
3570 | chip->ecc.read_page = nand_read_page_raw; |
3571 | chip->ecc.write_page = nand_write_page_raw; | |
7bc3312b | 3572 | chip->ecc.read_oob = nand_read_oob_std; |
52ff49df DB |
3573 | chip->ecc.read_page_raw = nand_read_page_raw; |
3574 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b | 3575 | chip->ecc.write_oob = nand_write_oob_std; |
ace4dfee TG |
3576 | chip->ecc.size = mtd->writesize; |
3577 | chip->ecc.bytes = 0; | |
6a918bad | 3578 | chip->ecc.strength = 0; |
1da177e4 | 3579 | break; |
956e944c | 3580 | |
1da177e4 | 3581 | default: |
d0370219 | 3582 | pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode); |
61b03bd7 | 3583 | BUG(); |
1da177e4 | 3584 | } |
61b03bd7 | 3585 | |
9ce244b3 | 3586 | /* For many systems, the standard OOB write also works for raw */ |
c46f6483 BN |
3587 | if (!chip->ecc.read_oob_raw) |
3588 | chip->ecc.read_oob_raw = chip->ecc.read_oob; | |
9ce244b3 BN |
3589 | if (!chip->ecc.write_oob_raw) |
3590 | chip->ecc.write_oob_raw = chip->ecc.write_oob; | |
3591 | ||
5bd34c09 TG |
3592 | /* |
3593 | * The number of bytes available for a client to place data into | |
8b6e50c9 | 3594 | * the out of band area. |
5bd34c09 TG |
3595 | */ |
3596 | chip->ecc.layout->oobavail = 0; | |
81d19b04 DB |
3597 | for (i = 0; chip->ecc.layout->oobfree[i].length |
3598 | && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++) | |
5bd34c09 TG |
3599 | chip->ecc.layout->oobavail += |
3600 | chip->ecc.layout->oobfree[i].length; | |
1f92267c | 3601 | mtd->oobavail = chip->ecc.layout->oobavail; |
5bd34c09 | 3602 | |
7aa65bfd TG |
3603 | /* |
3604 | * Set the number of read / write steps for one page depending on ECC | |
8b6e50c9 | 3605 | * mode. |
7aa65bfd | 3606 | */ |
ace4dfee | 3607 | chip->ecc.steps = mtd->writesize / chip->ecc.size; |
f8ac0414 | 3608 | if (chip->ecc.steps * chip->ecc.size != mtd->writesize) { |
9a4d4d69 | 3609 | pr_warn("Invalid ECC parameters\n"); |
6dfc6d25 | 3610 | BUG(); |
1da177e4 | 3611 | } |
f5bbdacc | 3612 | chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; |
61b03bd7 | 3613 | |
8b6e50c9 | 3614 | /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ |
29072b96 TG |
3615 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && |
3616 | !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { | |
f8ac0414 | 3617 | switch (chip->ecc.steps) { |
29072b96 TG |
3618 | case 2: |
3619 | mtd->subpage_sft = 1; | |
3620 | break; | |
3621 | case 4: | |
3622 | case 8: | |
81ec5364 | 3623 | case 16: |
29072b96 TG |
3624 | mtd->subpage_sft = 2; |
3625 | break; | |
3626 | } | |
3627 | } | |
3628 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
3629 | ||
04bbd0ea | 3630 | /* Initialize state */ |
ace4dfee | 3631 | chip->state = FL_READY; |
1da177e4 | 3632 | |
1da177e4 | 3633 | /* Invalidate the pagebuffer reference */ |
ace4dfee | 3634 | chip->pagebuf = -1; |
1da177e4 | 3635 | |
a5ff4f10 JW |
3636 | /* Large page NAND with SOFT_ECC should support subpage reads */ |
3637 | if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9)) | |
3638 | chip->options |= NAND_SUBPAGE_READ; | |
3639 | ||
1da177e4 LT |
3640 | /* Fill in remaining MTD driver data */ |
3641 | mtd->type = MTD_NANDFLASH; | |
93edbad6 ML |
3642 | mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : |
3643 | MTD_CAP_NANDFLASH; | |
3c3c10bb AB |
3644 | mtd->_erase = nand_erase; |
3645 | mtd->_point = NULL; | |
3646 | mtd->_unpoint = NULL; | |
3647 | mtd->_read = nand_read; | |
3648 | mtd->_write = nand_write; | |
3649 | mtd->_panic_write = panic_nand_write; | |
3650 | mtd->_read_oob = nand_read_oob; | |
3651 | mtd->_write_oob = nand_write_oob; | |
3652 | mtd->_sync = nand_sync; | |
3653 | mtd->_lock = NULL; | |
3654 | mtd->_unlock = NULL; | |
3655 | mtd->_suspend = nand_suspend; | |
3656 | mtd->_resume = nand_resume; | |
3657 | mtd->_block_isbad = nand_block_isbad; | |
3658 | mtd->_block_markbad = nand_block_markbad; | |
cbcab65a | 3659 | mtd->writebufsize = mtd->writesize; |
1da177e4 | 3660 | |
6a918bad | 3661 | /* propagate ecc info to mtd_info */ |
5bd34c09 | 3662 | mtd->ecclayout = chip->ecc.layout; |
86c2072b | 3663 | mtd->ecc_strength = chip->ecc.strength; |
ea3b2ea2 SL |
3664 | /* |
3665 | * Initialize bitflip_threshold to its default prior scan_bbt() call. | |
3666 | * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be | |
3667 | * properly set. | |
3668 | */ | |
3669 | if (!mtd->bitflip_threshold) | |
3670 | mtd->bitflip_threshold = mtd->ecc_strength; | |
1da177e4 | 3671 | |
0040bf38 | 3672 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 3673 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 3674 | return 0; |
1da177e4 LT |
3675 | |
3676 | /* Build bad block table */ | |
ace4dfee | 3677 | return chip->scan_bbt(mtd); |
1da177e4 | 3678 | } |
7351d3a5 | 3679 | EXPORT_SYMBOL(nand_scan_tail); |
1da177e4 | 3680 | |
8b6e50c9 BN |
3681 | /* |
3682 | * is_module_text_address() isn't exported, and it's mostly a pointless | |
7351d3a5 | 3683 | * test if this is a module _anyway_ -- they'd have to try _really_ hard |
8b6e50c9 BN |
3684 | * to call us from in-kernel code if the core NAND support is modular. |
3685 | */ | |
3b85c321 DW |
3686 | #ifdef MODULE |
3687 | #define caller_is_module() (1) | |
3688 | #else | |
3689 | #define caller_is_module() \ | |
a6e6abd5 | 3690 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
3691 | #endif |
3692 | ||
3693 | /** | |
3694 | * nand_scan - [NAND Interface] Scan for the NAND device | |
8b6e50c9 BN |
3695 | * @mtd: MTD device structure |
3696 | * @maxchips: number of chips to scan for | |
3b85c321 | 3697 | * |
8b6e50c9 BN |
3698 | * This fills out all the uninitialized function pointers with the defaults. |
3699 | * The flash ID is read and the mtd/chip structures are filled with the | |
3700 | * appropriate values. The mtd->owner field must be set to the module of the | |
3701 | * caller. | |
3b85c321 DW |
3702 | */ |
3703 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
3704 | { | |
3705 | int ret; | |
3706 | ||
3707 | /* Many callers got this wrong, so check for it for a while... */ | |
3708 | if (!mtd->owner && caller_is_module()) { | |
d0370219 | 3709 | pr_crit("%s called with NULL mtd->owner!\n", __func__); |
3b85c321 DW |
3710 | BUG(); |
3711 | } | |
3712 | ||
5e81e88a | 3713 | ret = nand_scan_ident(mtd, maxchips, NULL); |
3b85c321 DW |
3714 | if (!ret) |
3715 | ret = nand_scan_tail(mtd); | |
3716 | return ret; | |
3717 | } | |
7351d3a5 | 3718 | EXPORT_SYMBOL(nand_scan); |
3b85c321 | 3719 | |
1da177e4 | 3720 | /** |
61b03bd7 | 3721 | * nand_release - [NAND Interface] Free resources held by the NAND device |
8b6e50c9 BN |
3722 | * @mtd: MTD device structure |
3723 | */ | |
e0c7d767 | 3724 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 3725 | { |
ace4dfee | 3726 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 3727 | |
193bd400 ID |
3728 | if (chip->ecc.mode == NAND_ECC_SOFT_BCH) |
3729 | nand_bch_free((struct nand_bch_control *)chip->ecc.priv); | |
3730 | ||
5ffcaf3d | 3731 | mtd_device_unregister(mtd); |
1da177e4 | 3732 | |
fa671646 | 3733 | /* Free bad block table memory */ |
ace4dfee | 3734 | kfree(chip->bbt); |
4bf63fcb DW |
3735 | if (!(chip->options & NAND_OWN_BUFFERS)) |
3736 | kfree(chip->buffers); | |
58373ff0 BN |
3737 | |
3738 | /* Free bad block descriptor memory */ | |
3739 | if (chip->badblock_pattern && chip->badblock_pattern->options | |
3740 | & NAND_BBT_DYNAMICSTRUCT) | |
3741 | kfree(chip->badblock_pattern); | |
1da177e4 | 3742 | } |
e0c7d767 | 3743 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 RP |
3744 | |
3745 | static int __init nand_base_init(void) | |
3746 | { | |
3747 | led_trigger_register_simple("nand-disk", &nand_led_trigger); | |
3748 | return 0; | |
3749 | } | |
3750 | ||
3751 | static void __exit nand_base_exit(void) | |
3752 | { | |
3753 | led_trigger_unregister_simple(nand_led_trigger); | |
3754 | } | |
3755 | ||
3756 | module_init(nand_base_init); | |
3757 | module_exit(nand_base_exit); | |
3758 | ||
e0c7d767 | 3759 | MODULE_LICENSE("GPL"); |
7351d3a5 FF |
3760 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); |
3761 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
e0c7d767 | 3762 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |