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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand.c | |
3 | * | |
4 | * Overview: | |
5 | * This is the generic MTD driver for NAND flash devices. It should be | |
6 | * capable of working with almost all NAND chips currently available. | |
7 | * Basic support for AG-AND chips is provided. | |
61b03bd7 | 8 | * |
1da177e4 LT |
9 | * Additional technical information is available on |
10 | * http://www.linux-mtd.infradead.org/tech/nand.html | |
61b03bd7 | 11 | * |
1da177e4 | 12 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 13 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 14 | * |
ace4dfee | 15 | * Credits: |
61b03bd7 TG |
16 | * David Woodhouse for adding multichip support |
17 | * | |
1da177e4 LT |
18 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
19 | * rework for 2K page size chips | |
20 | * | |
ace4dfee | 21 | * TODO: |
1da177e4 LT |
22 | * Enable cached programming for 2k page size chips |
23 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
24 | * if we have HW ecc support. | |
25 | * The AG-AND chips have nice features for speed improvement, | |
26 | * which are not supported yet. Read / program 4 pages in one go. | |
27 | * | |
1da177e4 LT |
28 | * This program is free software; you can redistribute it and/or modify |
29 | * it under the terms of the GNU General Public License version 2 as | |
30 | * published by the Free Software Foundation. | |
31 | * | |
32 | */ | |
33 | ||
552d9205 | 34 | #include <linux/module.h> |
1da177e4 LT |
35 | #include <linux/delay.h> |
36 | #include <linux/errno.h> | |
7aa65bfd | 37 | #include <linux/err.h> |
1da177e4 LT |
38 | #include <linux/sched.h> |
39 | #include <linux/slab.h> | |
40 | #include <linux/types.h> | |
41 | #include <linux/mtd/mtd.h> | |
42 | #include <linux/mtd/nand.h> | |
43 | #include <linux/mtd/nand_ecc.h> | |
44 | #include <linux/mtd/compatmac.h> | |
45 | #include <linux/interrupt.h> | |
46 | #include <linux/bitops.h> | |
8fe833c1 | 47 | #include <linux/leds.h> |
1da177e4 LT |
48 | #include <asm/io.h> |
49 | ||
50 | #ifdef CONFIG_MTD_PARTITIONS | |
51 | #include <linux/mtd/partitions.h> | |
52 | #endif | |
53 | ||
54 | /* Define default oob placement schemes for large and small page devices */ | |
5bd34c09 | 55 | static struct nand_ecclayout nand_oob_8 = { |
1da177e4 LT |
56 | .eccbytes = 3, |
57 | .eccpos = {0, 1, 2}, | |
5bd34c09 TG |
58 | .oobfree = { |
59 | {.offset = 3, | |
60 | .length = 2}, | |
61 | {.offset = 6, | |
62 | .length = 2}} | |
1da177e4 LT |
63 | }; |
64 | ||
5bd34c09 | 65 | static struct nand_ecclayout nand_oob_16 = { |
1da177e4 LT |
66 | .eccbytes = 6, |
67 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
5bd34c09 TG |
68 | .oobfree = { |
69 | {.offset = 8, | |
70 | . length = 8}} | |
1da177e4 LT |
71 | }; |
72 | ||
5bd34c09 | 73 | static struct nand_ecclayout nand_oob_64 = { |
1da177e4 LT |
74 | .eccbytes = 24, |
75 | .eccpos = { | |
e0c7d767 DW |
76 | 40, 41, 42, 43, 44, 45, 46, 47, |
77 | 48, 49, 50, 51, 52, 53, 54, 55, | |
78 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
5bd34c09 TG |
79 | .oobfree = { |
80 | {.offset = 2, | |
81 | .length = 38}} | |
1da177e4 LT |
82 | }; |
83 | ||
ace4dfee | 84 | static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, |
2c0a2bed | 85 | int new_state); |
1da177e4 | 86 | |
8593fbc6 TG |
87 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
88 | struct mtd_oob_ops *ops); | |
89 | ||
d470a97c TG |
90 | /* |
91 | * For devices which display every fart in the system on a seperate LED. Is | |
92 | * compiled away when LED support is disabled. | |
93 | */ | |
94 | DEFINE_LED_TRIGGER(nand_led_trigger); | |
95 | ||
1da177e4 LT |
96 | /** |
97 | * nand_release_device - [GENERIC] release chip | |
98 | * @mtd: MTD device structure | |
61b03bd7 TG |
99 | * |
100 | * Deselect, release chip lock and wake up anyone waiting on the device | |
1da177e4 | 101 | */ |
e0c7d767 | 102 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 103 | { |
ace4dfee | 104 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
105 | |
106 | /* De-select the NAND device */ | |
ace4dfee | 107 | chip->select_chip(mtd, -1); |
0dfc6246 | 108 | |
a36ed299 | 109 | /* Release the controller and the chip */ |
ace4dfee TG |
110 | spin_lock(&chip->controller->lock); |
111 | chip->controller->active = NULL; | |
112 | chip->state = FL_READY; | |
113 | wake_up(&chip->controller->wq); | |
114 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
115 | } |
116 | ||
117 | /** | |
118 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
119 | * @mtd: MTD device structure | |
120 | * | |
121 | * Default read function for 8bit buswith | |
122 | */ | |
58dd8f2b | 123 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 124 | { |
ace4dfee TG |
125 | struct nand_chip *chip = mtd->priv; |
126 | return readb(chip->IO_ADDR_R); | |
1da177e4 LT |
127 | } |
128 | ||
1da177e4 LT |
129 | /** |
130 | * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip | |
131 | * @mtd: MTD device structure | |
132 | * | |
61b03bd7 | 133 | * Default read function for 16bit buswith with |
1da177e4 LT |
134 | * endianess conversion |
135 | */ | |
58dd8f2b | 136 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 137 | { |
ace4dfee TG |
138 | struct nand_chip *chip = mtd->priv; |
139 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); | |
1da177e4 LT |
140 | } |
141 | ||
1da177e4 LT |
142 | /** |
143 | * nand_read_word - [DEFAULT] read one word from the chip | |
144 | * @mtd: MTD device structure | |
145 | * | |
61b03bd7 | 146 | * Default read function for 16bit buswith without |
1da177e4 LT |
147 | * endianess conversion |
148 | */ | |
149 | static u16 nand_read_word(struct mtd_info *mtd) | |
150 | { | |
ace4dfee TG |
151 | struct nand_chip *chip = mtd->priv; |
152 | return readw(chip->IO_ADDR_R); | |
1da177e4 LT |
153 | } |
154 | ||
1da177e4 LT |
155 | /** |
156 | * nand_select_chip - [DEFAULT] control CE line | |
157 | * @mtd: MTD device structure | |
844d3b42 | 158 | * @chipnr: chipnumber to select, -1 for deselect |
1da177e4 LT |
159 | * |
160 | * Default select function for 1 chip devices. | |
161 | */ | |
ace4dfee | 162 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 163 | { |
ace4dfee TG |
164 | struct nand_chip *chip = mtd->priv; |
165 | ||
166 | switch (chipnr) { | |
1da177e4 | 167 | case -1: |
ace4dfee | 168 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
169 | break; |
170 | case 0: | |
1da177e4 LT |
171 | break; |
172 | ||
173 | default: | |
174 | BUG(); | |
175 | } | |
176 | } | |
177 | ||
178 | /** | |
179 | * nand_write_buf - [DEFAULT] write buffer to chip | |
180 | * @mtd: MTD device structure | |
181 | * @buf: data buffer | |
182 | * @len: number of bytes to write | |
183 | * | |
184 | * Default write function for 8bit buswith | |
185 | */ | |
58dd8f2b | 186 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
187 | { |
188 | int i; | |
ace4dfee | 189 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 190 | |
e0c7d767 | 191 | for (i = 0; i < len; i++) |
ace4dfee | 192 | writeb(buf[i], chip->IO_ADDR_W); |
1da177e4 LT |
193 | } |
194 | ||
195 | /** | |
61b03bd7 | 196 | * nand_read_buf - [DEFAULT] read chip data into buffer |
1da177e4 LT |
197 | * @mtd: MTD device structure |
198 | * @buf: buffer to store date | |
199 | * @len: number of bytes to read | |
200 | * | |
201 | * Default read function for 8bit buswith | |
202 | */ | |
58dd8f2b | 203 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
204 | { |
205 | int i; | |
ace4dfee | 206 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 207 | |
e0c7d767 | 208 | for (i = 0; i < len; i++) |
ace4dfee | 209 | buf[i] = readb(chip->IO_ADDR_R); |
1da177e4 LT |
210 | } |
211 | ||
212 | /** | |
61b03bd7 | 213 | * nand_verify_buf - [DEFAULT] Verify chip data against buffer |
1da177e4 LT |
214 | * @mtd: MTD device structure |
215 | * @buf: buffer containing the data to compare | |
216 | * @len: number of bytes to compare | |
217 | * | |
218 | * Default verify function for 8bit buswith | |
219 | */ | |
58dd8f2b | 220 | static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
221 | { |
222 | int i; | |
ace4dfee | 223 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 224 | |
e0c7d767 | 225 | for (i = 0; i < len; i++) |
ace4dfee | 226 | if (buf[i] != readb(chip->IO_ADDR_R)) |
1da177e4 | 227 | return -EFAULT; |
1da177e4 LT |
228 | return 0; |
229 | } | |
230 | ||
231 | /** | |
232 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
233 | * @mtd: MTD device structure | |
234 | * @buf: data buffer | |
235 | * @len: number of bytes to write | |
236 | * | |
237 | * Default write function for 16bit buswith | |
238 | */ | |
58dd8f2b | 239 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
240 | { |
241 | int i; | |
ace4dfee | 242 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
243 | u16 *p = (u16 *) buf; |
244 | len >>= 1; | |
61b03bd7 | 245 | |
e0c7d767 | 246 | for (i = 0; i < len; i++) |
ace4dfee | 247 | writew(p[i], chip->IO_ADDR_W); |
61b03bd7 | 248 | |
1da177e4 LT |
249 | } |
250 | ||
251 | /** | |
61b03bd7 | 252 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
1da177e4 LT |
253 | * @mtd: MTD device structure |
254 | * @buf: buffer to store date | |
255 | * @len: number of bytes to read | |
256 | * | |
257 | * Default read function for 16bit buswith | |
258 | */ | |
58dd8f2b | 259 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
260 | { |
261 | int i; | |
ace4dfee | 262 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
263 | u16 *p = (u16 *) buf; |
264 | len >>= 1; | |
265 | ||
e0c7d767 | 266 | for (i = 0; i < len; i++) |
ace4dfee | 267 | p[i] = readw(chip->IO_ADDR_R); |
1da177e4 LT |
268 | } |
269 | ||
270 | /** | |
61b03bd7 | 271 | * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer |
1da177e4 LT |
272 | * @mtd: MTD device structure |
273 | * @buf: buffer containing the data to compare | |
274 | * @len: number of bytes to compare | |
275 | * | |
276 | * Default verify function for 16bit buswith | |
277 | */ | |
58dd8f2b | 278 | static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
279 | { |
280 | int i; | |
ace4dfee | 281 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
282 | u16 *p = (u16 *) buf; |
283 | len >>= 1; | |
284 | ||
e0c7d767 | 285 | for (i = 0; i < len; i++) |
ace4dfee | 286 | if (p[i] != readw(chip->IO_ADDR_R)) |
1da177e4 LT |
287 | return -EFAULT; |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
292 | /** | |
293 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
294 | * @mtd: MTD device structure | |
295 | * @ofs: offset from device start | |
296 | * @getchip: 0, if the chip is already selected | |
297 | * | |
61b03bd7 | 298 | * Check, if the block is bad. |
1da177e4 LT |
299 | */ |
300 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) | |
301 | { | |
302 | int page, chipnr, res = 0; | |
ace4dfee | 303 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
304 | u16 bad; |
305 | ||
1a12f46a TK |
306 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
307 | ||
1da177e4 | 308 | if (getchip) { |
ace4dfee | 309 | chipnr = (int)(ofs >> chip->chip_shift); |
1da177e4 | 310 | |
ace4dfee | 311 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 LT |
312 | |
313 | /* Select the NAND device */ | |
ace4dfee | 314 | chip->select_chip(mtd, chipnr); |
1a12f46a | 315 | } |
1da177e4 | 316 | |
ace4dfee TG |
317 | if (chip->options & NAND_BUSWIDTH_16) { |
318 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE, | |
1a12f46a | 319 | page); |
ace4dfee TG |
320 | bad = cpu_to_le16(chip->read_word(mtd)); |
321 | if (chip->badblockpos & 0x1) | |
49196f33 | 322 | bad >>= 8; |
1da177e4 LT |
323 | if ((bad & 0xFF) != 0xff) |
324 | res = 1; | |
325 | } else { | |
1a12f46a | 326 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page); |
ace4dfee | 327 | if (chip->read_byte(mtd) != 0xff) |
1da177e4 LT |
328 | res = 1; |
329 | } | |
61b03bd7 | 330 | |
ace4dfee | 331 | if (getchip) |
1da177e4 | 332 | nand_release_device(mtd); |
61b03bd7 | 333 | |
1da177e4 LT |
334 | return res; |
335 | } | |
336 | ||
337 | /** | |
338 | * nand_default_block_markbad - [DEFAULT] mark a block bad | |
339 | * @mtd: MTD device structure | |
340 | * @ofs: offset from device start | |
341 | * | |
342 | * This is the default implementation, which can be overridden by | |
343 | * a hardware specific driver. | |
344 | */ | |
345 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
346 | { | |
ace4dfee | 347 | struct nand_chip *chip = mtd->priv; |
58dd8f2b | 348 | uint8_t buf[2] = { 0, 0 }; |
f1a28c02 | 349 | int block, ret; |
61b03bd7 | 350 | |
1da177e4 | 351 | /* Get block number */ |
4226b510 | 352 | block = (int)(ofs >> chip->bbt_erase_shift); |
ace4dfee TG |
353 | if (chip->bbt) |
354 | chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); | |
1da177e4 LT |
355 | |
356 | /* Do we have a flash based bad block table ? */ | |
ace4dfee | 357 | if (chip->options & NAND_USE_FLASH_BBT) |
f1a28c02 TG |
358 | ret = nand_update_bbt(mtd, ofs); |
359 | else { | |
360 | /* We write two bytes, so we dont have to mess with 16 bit | |
361 | * access | |
362 | */ | |
363 | ofs += mtd->oobsize; | |
ff0dab64 | 364 | chip->ops.len = chip->ops.ooblen = 2; |
f1a28c02 TG |
365 | chip->ops.datbuf = NULL; |
366 | chip->ops.oobbuf = buf; | |
367 | chip->ops.ooboffs = chip->badblockpos & ~0x01; | |
368 | ||
369 | ret = nand_do_write_oob(mtd, ofs, &chip->ops); | |
370 | } | |
371 | if (!ret) | |
372 | mtd->ecc_stats.badblocks++; | |
373 | return ret; | |
1da177e4 LT |
374 | } |
375 | ||
61b03bd7 | 376 | /** |
1da177e4 LT |
377 | * nand_check_wp - [GENERIC] check if the chip is write protected |
378 | * @mtd: MTD device structure | |
61b03bd7 | 379 | * Check, if the device is write protected |
1da177e4 | 380 | * |
61b03bd7 | 381 | * The function expects, that the device is already selected |
1da177e4 | 382 | */ |
e0c7d767 | 383 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 384 | { |
ace4dfee | 385 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 386 | /* Check the WP bit */ |
ace4dfee TG |
387 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
388 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
389 | } |
390 | ||
391 | /** | |
392 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
393 | * @mtd: MTD device structure | |
394 | * @ofs: offset from device start | |
395 | * @getchip: 0, if the chip is already selected | |
396 | * @allowbbt: 1, if its allowed to access the bbt area | |
397 | * | |
398 | * Check, if the block is bad. Either by reading the bad block table or | |
399 | * calling of the scan function. | |
400 | */ | |
2c0a2bed TG |
401 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, |
402 | int allowbbt) | |
1da177e4 | 403 | { |
ace4dfee | 404 | struct nand_chip *chip = mtd->priv; |
61b03bd7 | 405 | |
ace4dfee TG |
406 | if (!chip->bbt) |
407 | return chip->block_bad(mtd, ofs, getchip); | |
61b03bd7 | 408 | |
1da177e4 | 409 | /* Return info from the table */ |
e0c7d767 | 410 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
411 | } |
412 | ||
61b03bd7 | 413 | /* |
3b88775c TG |
414 | * Wait for the ready pin, after a command |
415 | * The timeout is catched later. | |
416 | */ | |
4b648b02 | 417 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 418 | { |
ace4dfee | 419 | struct nand_chip *chip = mtd->priv; |
e0c7d767 | 420 | unsigned long timeo = jiffies + 2; |
3b88775c | 421 | |
8fe833c1 | 422 | led_trigger_event(nand_led_trigger, LED_FULL); |
3b88775c TG |
423 | /* wait until command is processed or timeout occures */ |
424 | do { | |
ace4dfee | 425 | if (chip->dev_ready(mtd)) |
8fe833c1 | 426 | break; |
8446f1d3 | 427 | touch_softlockup_watchdog(); |
61b03bd7 | 428 | } while (time_before(jiffies, timeo)); |
8fe833c1 | 429 | led_trigger_event(nand_led_trigger, LED_OFF); |
3b88775c | 430 | } |
4b648b02 | 431 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 432 | |
1da177e4 LT |
433 | /** |
434 | * nand_command - [DEFAULT] Send command to NAND device | |
435 | * @mtd: MTD device structure | |
436 | * @command: the command to be sent | |
437 | * @column: the column address for this command, -1 if none | |
438 | * @page_addr: the page address for this command, -1 if none | |
439 | * | |
440 | * Send command to NAND device. This function is used for small page | |
441 | * devices (256/512 Bytes per page) | |
442 | */ | |
7abd3ef9 TG |
443 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
444 | int column, int page_addr) | |
1da177e4 | 445 | { |
ace4dfee | 446 | register struct nand_chip *chip = mtd->priv; |
7abd3ef9 | 447 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 448 | |
1da177e4 LT |
449 | /* |
450 | * Write out the command to the device. | |
451 | */ | |
452 | if (command == NAND_CMD_SEQIN) { | |
453 | int readcmd; | |
454 | ||
28318776 | 455 | if (column >= mtd->writesize) { |
1da177e4 | 456 | /* OOB area */ |
28318776 | 457 | column -= mtd->writesize; |
1da177e4 LT |
458 | readcmd = NAND_CMD_READOOB; |
459 | } else if (column < 256) { | |
460 | /* First 256 bytes --> READ0 */ | |
461 | readcmd = NAND_CMD_READ0; | |
462 | } else { | |
463 | column -= 256; | |
464 | readcmd = NAND_CMD_READ1; | |
465 | } | |
ace4dfee | 466 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 467 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 468 | } |
ace4dfee | 469 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 470 | |
7abd3ef9 TG |
471 | /* |
472 | * Address cycle, when necessary | |
473 | */ | |
474 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; | |
475 | /* Serially input address */ | |
476 | if (column != -1) { | |
477 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 478 | if (chip->options & NAND_BUSWIDTH_16) |
7abd3ef9 | 479 | column >>= 1; |
ace4dfee | 480 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
481 | ctrl &= ~NAND_CTRL_CHANGE; |
482 | } | |
483 | if (page_addr != -1) { | |
ace4dfee | 484 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 485 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 486 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 487 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
488 | if (chip->chipsize > (32 << 20)) |
489 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 490 | } |
ace4dfee | 491 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
492 | |
493 | /* | |
494 | * program and erase have their own busy handlers | |
1da177e4 | 495 | * status and sequential in needs no delay |
e0c7d767 | 496 | */ |
1da177e4 | 497 | switch (command) { |
61b03bd7 | 498 | |
1da177e4 LT |
499 | case NAND_CMD_PAGEPROG: |
500 | case NAND_CMD_ERASE1: | |
501 | case NAND_CMD_ERASE2: | |
502 | case NAND_CMD_SEQIN: | |
503 | case NAND_CMD_STATUS: | |
504 | return; | |
505 | ||
506 | case NAND_CMD_RESET: | |
ace4dfee | 507 | if (chip->dev_ready) |
1da177e4 | 508 | break; |
ace4dfee TG |
509 | udelay(chip->chip_delay); |
510 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 511 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
512 | chip->cmd_ctrl(mtd, |
513 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
ace4dfee | 514 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; |
1da177e4 LT |
515 | return; |
516 | ||
e0c7d767 | 517 | /* This applies to read commands */ |
1da177e4 | 518 | default: |
61b03bd7 | 519 | /* |
1da177e4 LT |
520 | * If we don't have access to the busy pin, we apply the given |
521 | * command delay | |
e0c7d767 | 522 | */ |
ace4dfee TG |
523 | if (!chip->dev_ready) { |
524 | udelay(chip->chip_delay); | |
1da177e4 | 525 | return; |
61b03bd7 | 526 | } |
1da177e4 | 527 | } |
1da177e4 LT |
528 | /* Apply this short delay always to ensure that we do wait tWB in |
529 | * any case on any machine. */ | |
e0c7d767 | 530 | ndelay(100); |
3b88775c TG |
531 | |
532 | nand_wait_ready(mtd); | |
1da177e4 LT |
533 | } |
534 | ||
535 | /** | |
536 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
537 | * @mtd: MTD device structure | |
538 | * @command: the command to be sent | |
539 | * @column: the column address for this command, -1 if none | |
540 | * @page_addr: the page address for this command, -1 if none | |
541 | * | |
7abd3ef9 TG |
542 | * Send command to NAND device. This is the version for the new large page |
543 | * devices We dont have the separate regions as we have in the small page | |
544 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 545 | */ |
7abd3ef9 TG |
546 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
547 | int column, int page_addr) | |
1da177e4 | 548 | { |
ace4dfee | 549 | register struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
550 | |
551 | /* Emulate NAND_CMD_READOOB */ | |
552 | if (command == NAND_CMD_READOOB) { | |
28318776 | 553 | column += mtd->writesize; |
1da177e4 LT |
554 | command = NAND_CMD_READ0; |
555 | } | |
61b03bd7 | 556 | |
7abd3ef9 | 557 | /* Command latch cycle */ |
ace4dfee | 558 | chip->cmd_ctrl(mtd, command & 0xff, |
7abd3ef9 | 559 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
560 | |
561 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 562 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
563 | |
564 | /* Serially input address */ | |
565 | if (column != -1) { | |
566 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 567 | if (chip->options & NAND_BUSWIDTH_16) |
1da177e4 | 568 | column >>= 1; |
ace4dfee | 569 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 570 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 571 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 572 | } |
1da177e4 | 573 | if (page_addr != -1) { |
ace4dfee TG |
574 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
575 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 576 | NAND_NCE | NAND_ALE); |
1da177e4 | 577 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
578 | if (chip->chipsize > (128 << 20)) |
579 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 580 | NAND_NCE | NAND_ALE); |
1da177e4 | 581 | } |
1da177e4 | 582 | } |
ace4dfee | 583 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
584 | |
585 | /* | |
586 | * program and erase have their own busy handlers | |
30f464b7 DM |
587 | * status, sequential in, and deplete1 need no delay |
588 | */ | |
1da177e4 | 589 | switch (command) { |
61b03bd7 | 590 | |
1da177e4 LT |
591 | case NAND_CMD_CACHEDPROG: |
592 | case NAND_CMD_PAGEPROG: | |
593 | case NAND_CMD_ERASE1: | |
594 | case NAND_CMD_ERASE2: | |
595 | case NAND_CMD_SEQIN: | |
7bc3312b | 596 | case NAND_CMD_RNDIN: |
1da177e4 | 597 | case NAND_CMD_STATUS: |
30f464b7 | 598 | case NAND_CMD_DEPLETE1: |
1da177e4 LT |
599 | return; |
600 | ||
e0c7d767 DW |
601 | /* |
602 | * read error status commands require only a short delay | |
603 | */ | |
30f464b7 DM |
604 | case NAND_CMD_STATUS_ERROR: |
605 | case NAND_CMD_STATUS_ERROR0: | |
606 | case NAND_CMD_STATUS_ERROR1: | |
607 | case NAND_CMD_STATUS_ERROR2: | |
608 | case NAND_CMD_STATUS_ERROR3: | |
ace4dfee | 609 | udelay(chip->chip_delay); |
30f464b7 | 610 | return; |
1da177e4 LT |
611 | |
612 | case NAND_CMD_RESET: | |
ace4dfee | 613 | if (chip->dev_ready) |
1da177e4 | 614 | break; |
ace4dfee | 615 | udelay(chip->chip_delay); |
12efdde3 TG |
616 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
617 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
618 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
619 | NAND_NCE | NAND_CTRL_CHANGE); | |
ace4dfee | 620 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; |
1da177e4 LT |
621 | return; |
622 | ||
7bc3312b TG |
623 | case NAND_CMD_RNDOUT: |
624 | /* No ready / busy check necessary */ | |
625 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
626 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
627 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
628 | NAND_NCE | NAND_CTRL_CHANGE); | |
629 | return; | |
630 | ||
1da177e4 | 631 | case NAND_CMD_READ0: |
12efdde3 TG |
632 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
633 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
634 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
635 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 636 | |
e0c7d767 | 637 | /* This applies to read commands */ |
1da177e4 | 638 | default: |
61b03bd7 | 639 | /* |
1da177e4 LT |
640 | * If we don't have access to the busy pin, we apply the given |
641 | * command delay | |
e0c7d767 | 642 | */ |
ace4dfee TG |
643 | if (!chip->dev_ready) { |
644 | udelay(chip->chip_delay); | |
1da177e4 | 645 | return; |
61b03bd7 | 646 | } |
1da177e4 | 647 | } |
3b88775c | 648 | |
1da177e4 LT |
649 | /* Apply this short delay always to ensure that we do wait tWB in |
650 | * any case on any machine. */ | |
e0c7d767 | 651 | ndelay(100); |
3b88775c TG |
652 | |
653 | nand_wait_ready(mtd); | |
1da177e4 LT |
654 | } |
655 | ||
656 | /** | |
657 | * nand_get_device - [GENERIC] Get chip for selected access | |
844d3b42 | 658 | * @chip: the nand chip descriptor |
1da177e4 | 659 | * @mtd: MTD device structure |
61b03bd7 | 660 | * @new_state: the state which is requested |
1da177e4 LT |
661 | * |
662 | * Get the device and lock it for exclusive access | |
663 | */ | |
2c0a2bed | 664 | static int |
ace4dfee | 665 | nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state) |
1da177e4 | 666 | { |
ace4dfee TG |
667 | spinlock_t *lock = &chip->controller->lock; |
668 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 669 | DECLARE_WAITQUEUE(wait, current); |
e0c7d767 | 670 | retry: |
0dfc6246 TG |
671 | spin_lock(lock); |
672 | ||
1da177e4 | 673 | /* Hardware controller shared among independend devices */ |
a36ed299 | 674 | /* Hardware controller shared among independend devices */ |
ace4dfee TG |
675 | if (!chip->controller->active) |
676 | chip->controller->active = chip; | |
a36ed299 | 677 | |
ace4dfee TG |
678 | if (chip->controller->active == chip && chip->state == FL_READY) { |
679 | chip->state = new_state; | |
0dfc6246 | 680 | spin_unlock(lock); |
962034f4 VW |
681 | return 0; |
682 | } | |
683 | if (new_state == FL_PM_SUSPENDED) { | |
684 | spin_unlock(lock); | |
ace4dfee | 685 | return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN; |
0dfc6246 TG |
686 | } |
687 | set_current_state(TASK_UNINTERRUPTIBLE); | |
688 | add_wait_queue(wq, &wait); | |
689 | spin_unlock(lock); | |
690 | schedule(); | |
691 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
692 | goto retry; |
693 | } | |
694 | ||
695 | /** | |
696 | * nand_wait - [DEFAULT] wait until the command is done | |
697 | * @mtd: MTD device structure | |
844d3b42 | 698 | * @chip: NAND chip structure |
1da177e4 LT |
699 | * |
700 | * Wait for command done. This applies to erase and program only | |
61b03bd7 | 701 | * Erase can take up to 400ms and program up to 20ms according to |
1da177e4 | 702 | * general NAND and SmartMedia specs |
844d3b42 | 703 | */ |
7bc3312b | 704 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
705 | { |
706 | ||
e0c7d767 | 707 | unsigned long timeo = jiffies; |
7bc3312b | 708 | int status, state = chip->state; |
61b03bd7 | 709 | |
1da177e4 | 710 | if (state == FL_ERASING) |
e0c7d767 | 711 | timeo += (HZ * 400) / 1000; |
1da177e4 | 712 | else |
e0c7d767 | 713 | timeo += (HZ * 20) / 1000; |
1da177e4 | 714 | |
8fe833c1 RP |
715 | led_trigger_event(nand_led_trigger, LED_FULL); |
716 | ||
1da177e4 LT |
717 | /* Apply this short delay always to ensure that we do wait tWB in |
718 | * any case on any machine. */ | |
e0c7d767 | 719 | ndelay(100); |
1da177e4 | 720 | |
ace4dfee TG |
721 | if ((state == FL_ERASING) && (chip->options & NAND_IS_AND)) |
722 | chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); | |
61b03bd7 | 723 | else |
ace4dfee | 724 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 725 | |
61b03bd7 | 726 | while (time_before(jiffies, timeo)) { |
ace4dfee TG |
727 | if (chip->dev_ready) { |
728 | if (chip->dev_ready(mtd)) | |
61b03bd7 | 729 | break; |
1da177e4 | 730 | } else { |
ace4dfee | 731 | if (chip->read_byte(mtd) & NAND_STATUS_READY) |
1da177e4 LT |
732 | break; |
733 | } | |
20a6c211 | 734 | cond_resched(); |
1da177e4 | 735 | } |
8fe833c1 RP |
736 | led_trigger_event(nand_led_trigger, LED_OFF); |
737 | ||
ace4dfee | 738 | status = (int)chip->read_byte(mtd); |
1da177e4 LT |
739 | return status; |
740 | } | |
741 | ||
8593fbc6 TG |
742 | /** |
743 | * nand_read_page_raw - [Intern] read raw page data without ecc | |
744 | * @mtd: mtd info structure | |
745 | * @chip: nand chip info structure | |
746 | * @buf: buffer to store read data | |
747 | */ | |
748 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
749 | uint8_t *buf) | |
750 | { | |
751 | chip->read_buf(mtd, buf, mtd->writesize); | |
752 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
753 | return 0; | |
754 | } | |
755 | ||
1da177e4 | 756 | /** |
d29ebdbe | 757 | * nand_read_page_swecc - [REPLACABLE] software ecc based page read function |
f5bbdacc TG |
758 | * @mtd: mtd info structure |
759 | * @chip: nand chip info structure | |
760 | * @buf: buffer to store read data | |
068e3c0a | 761 | */ |
f5bbdacc TG |
762 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
763 | uint8_t *buf) | |
1da177e4 | 764 | { |
f5bbdacc TG |
765 | int i, eccsize = chip->ecc.size; |
766 | int eccbytes = chip->ecc.bytes; | |
767 | int eccsteps = chip->ecc.steps; | |
768 | uint8_t *p = buf; | |
4bf63fcb DW |
769 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
770 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 771 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
f5bbdacc | 772 | |
90424de8 | 773 | chip->ecc.read_page_raw(mtd, chip, buf); |
f5bbdacc TG |
774 | |
775 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
776 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
777 | ||
778 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 779 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
780 | |
781 | eccsteps = chip->ecc.steps; | |
782 | p = buf; | |
783 | ||
784 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
785 | int stat; | |
786 | ||
787 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
788 | if (stat == -1) | |
789 | mtd->ecc_stats.failed++; | |
790 | else | |
791 | mtd->ecc_stats.corrected += stat; | |
792 | } | |
793 | return 0; | |
22c60f5f | 794 | } |
1da177e4 | 795 | |
068e3c0a | 796 | /** |
d29ebdbe | 797 | * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function |
f5bbdacc TG |
798 | * @mtd: mtd info structure |
799 | * @chip: nand chip info structure | |
800 | * @buf: buffer to store read data | |
068e3c0a | 801 | * |
f5bbdacc | 802 | * Not for syndrome calculating ecc controllers which need a special oob layout |
068e3c0a | 803 | */ |
f5bbdacc TG |
804 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
805 | uint8_t *buf) | |
1da177e4 | 806 | { |
f5bbdacc TG |
807 | int i, eccsize = chip->ecc.size; |
808 | int eccbytes = chip->ecc.bytes; | |
809 | int eccsteps = chip->ecc.steps; | |
810 | uint8_t *p = buf; | |
4bf63fcb DW |
811 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
812 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 813 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
f5bbdacc TG |
814 | |
815 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
816 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
817 | chip->read_buf(mtd, p, eccsize); | |
818 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 819 | } |
f75e5097 | 820 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 821 | |
f5bbdacc | 822 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 823 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 824 | |
f5bbdacc TG |
825 | eccsteps = chip->ecc.steps; |
826 | p = buf; | |
61b03bd7 | 827 | |
f5bbdacc TG |
828 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
829 | int stat; | |
1da177e4 | 830 | |
f5bbdacc TG |
831 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
832 | if (stat == -1) | |
833 | mtd->ecc_stats.failed++; | |
834 | else | |
835 | mtd->ecc_stats.corrected += stat; | |
836 | } | |
837 | return 0; | |
838 | } | |
1da177e4 | 839 | |
f5bbdacc | 840 | /** |
d29ebdbe | 841 | * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read |
f5bbdacc TG |
842 | * @mtd: mtd info structure |
843 | * @chip: nand chip info structure | |
844 | * @buf: buffer to store read data | |
845 | * | |
846 | * The hw generator calculates the error syndrome automatically. Therefor | |
f75e5097 | 847 | * we need a special oob layout and handling. |
f5bbdacc TG |
848 | */ |
849 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
850 | uint8_t *buf) | |
851 | { | |
852 | int i, eccsize = chip->ecc.size; | |
853 | int eccbytes = chip->ecc.bytes; | |
854 | int eccsteps = chip->ecc.steps; | |
855 | uint8_t *p = buf; | |
f75e5097 | 856 | uint8_t *oob = chip->oob_poi; |
1da177e4 | 857 | |
f5bbdacc TG |
858 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
859 | int stat; | |
61b03bd7 | 860 | |
f5bbdacc TG |
861 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
862 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 863 | |
f5bbdacc TG |
864 | if (chip->ecc.prepad) { |
865 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
866 | oob += chip->ecc.prepad; | |
867 | } | |
1da177e4 | 868 | |
f5bbdacc TG |
869 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
870 | chip->read_buf(mtd, oob, eccbytes); | |
871 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 872 | |
f5bbdacc TG |
873 | if (stat == -1) |
874 | mtd->ecc_stats.failed++; | |
61b03bd7 | 875 | else |
f5bbdacc | 876 | mtd->ecc_stats.corrected += stat; |
61b03bd7 | 877 | |
f5bbdacc | 878 | oob += eccbytes; |
1da177e4 | 879 | |
f5bbdacc TG |
880 | if (chip->ecc.postpad) { |
881 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
882 | oob += chip->ecc.postpad; | |
61b03bd7 | 883 | } |
f5bbdacc | 884 | } |
1da177e4 | 885 | |
f5bbdacc | 886 | /* Calculate remaining oob bytes */ |
7e4178f9 | 887 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
888 | if (i) |
889 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 890 | |
f5bbdacc TG |
891 | return 0; |
892 | } | |
1da177e4 | 893 | |
f5bbdacc | 894 | /** |
8593fbc6 TG |
895 | * nand_transfer_oob - [Internal] Transfer oob to client buffer |
896 | * @chip: nand chip structure | |
844d3b42 | 897 | * @oob: oob destination address |
8593fbc6 | 898 | * @ops: oob ops structure |
7014568b | 899 | * @len: size of oob to transfer |
8593fbc6 TG |
900 | */ |
901 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, | |
7014568b | 902 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 903 | { |
8593fbc6 TG |
904 | switch(ops->mode) { |
905 | ||
906 | case MTD_OOB_PLACE: | |
907 | case MTD_OOB_RAW: | |
908 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); | |
909 | return oob + len; | |
910 | ||
911 | case MTD_OOB_AUTO: { | |
912 | struct nand_oobfree *free = chip->ecc.layout->oobfree; | |
7bc3312b TG |
913 | uint32_t boffs = 0, roffs = ops->ooboffs; |
914 | size_t bytes = 0; | |
8593fbc6 TG |
915 | |
916 | for(; free->length && len; free++, len -= bytes) { | |
7bc3312b TG |
917 | /* Read request not from offset 0 ? */ |
918 | if (unlikely(roffs)) { | |
919 | if (roffs >= free->length) { | |
920 | roffs -= free->length; | |
921 | continue; | |
922 | } | |
923 | boffs = free->offset + roffs; | |
924 | bytes = min_t(size_t, len, | |
925 | (free->length - roffs)); | |
926 | roffs = 0; | |
927 | } else { | |
928 | bytes = min_t(size_t, len, free->length); | |
929 | boffs = free->offset; | |
930 | } | |
931 | memcpy(oob, chip->oob_poi + boffs, bytes); | |
8593fbc6 TG |
932 | oob += bytes; |
933 | } | |
934 | return oob; | |
935 | } | |
936 | default: | |
937 | BUG(); | |
938 | } | |
939 | return NULL; | |
940 | } | |
941 | ||
942 | /** | |
943 | * nand_do_read_ops - [Internal] Read data with ECC | |
f5bbdacc TG |
944 | * |
945 | * @mtd: MTD device structure | |
946 | * @from: offset to read from | |
844d3b42 | 947 | * @ops: oob ops structure |
f5bbdacc TG |
948 | * |
949 | * Internal function. Called with chip held. | |
950 | */ | |
8593fbc6 TG |
951 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
952 | struct mtd_oob_ops *ops) | |
f5bbdacc TG |
953 | { |
954 | int chipnr, page, realpage, col, bytes, aligned; | |
955 | struct nand_chip *chip = mtd->priv; | |
956 | struct mtd_ecc_stats stats; | |
957 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
958 | int sndcmd = 1; | |
959 | int ret = 0; | |
8593fbc6 | 960 | uint32_t readlen = ops->len; |
7014568b | 961 | uint32_t oobreadlen = ops->ooblen; |
8593fbc6 | 962 | uint8_t *bufpoi, *oob, *buf; |
1da177e4 | 963 | |
f5bbdacc | 964 | stats = mtd->ecc_stats; |
1da177e4 | 965 | |
f5bbdacc TG |
966 | chipnr = (int)(from >> chip->chip_shift); |
967 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 968 | |
f5bbdacc TG |
969 | realpage = (int)(from >> chip->page_shift); |
970 | page = realpage & chip->pagemask; | |
1da177e4 | 971 | |
f5bbdacc | 972 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 973 | |
8593fbc6 TG |
974 | buf = ops->datbuf; |
975 | oob = ops->oobbuf; | |
976 | ||
f5bbdacc TG |
977 | while(1) { |
978 | bytes = min(mtd->writesize - col, readlen); | |
979 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 980 | |
f5bbdacc | 981 | /* Is the current page in the buffer ? */ |
8593fbc6 | 982 | if (realpage != chip->pagebuf || oob) { |
4bf63fcb | 983 | bufpoi = aligned ? buf : chip->buffers->databuf; |
61b03bd7 | 984 | |
f5bbdacc TG |
985 | if (likely(sndcmd)) { |
986 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); | |
987 | sndcmd = 0; | |
1da177e4 | 988 | } |
1da177e4 | 989 | |
f5bbdacc | 990 | /* Now read the page into the buffer */ |
956e944c DW |
991 | if (unlikely(ops->mode == MTD_OOB_RAW)) |
992 | ret = chip->ecc.read_page_raw(mtd, chip, bufpoi); | |
993 | else | |
994 | ret = chip->ecc.read_page(mtd, chip, bufpoi); | |
f5bbdacc | 995 | if (ret < 0) |
1da177e4 | 996 | break; |
f5bbdacc TG |
997 | |
998 | /* Transfer not aligned data */ | |
999 | if (!aligned) { | |
1000 | chip->pagebuf = realpage; | |
4bf63fcb | 1001 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
1002 | } |
1003 | ||
8593fbc6 TG |
1004 | buf += bytes; |
1005 | ||
1006 | if (unlikely(oob)) { | |
1007 | /* Raw mode does data:oob:data:oob */ | |
7014568b VW |
1008 | if (ops->mode != MTD_OOB_RAW) { |
1009 | int toread = min(oobreadlen, | |
1010 | chip->ecc.layout->oobavail); | |
1011 | if (toread) { | |
1012 | oob = nand_transfer_oob(chip, | |
1013 | oob, ops, toread); | |
1014 | oobreadlen -= toread; | |
1015 | } | |
1016 | } else | |
1017 | buf = nand_transfer_oob(chip, | |
1018 | buf, ops, mtd->oobsize); | |
8593fbc6 TG |
1019 | } |
1020 | ||
f5bbdacc TG |
1021 | if (!(chip->options & NAND_NO_READRDY)) { |
1022 | /* | |
1023 | * Apply delay or wait for ready/busy pin. Do | |
1024 | * this before the AUTOINCR check, so no | |
1025 | * problems arise if a chip which does auto | |
1026 | * increment is marked as NOAUTOINCR by the | |
1027 | * board driver. | |
1028 | */ | |
1029 | if (!chip->dev_ready) | |
1030 | udelay(chip->chip_delay); | |
1031 | else | |
1032 | nand_wait_ready(mtd); | |
1da177e4 | 1033 | } |
8593fbc6 | 1034 | } else { |
4bf63fcb | 1035 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 TG |
1036 | buf += bytes; |
1037 | } | |
1da177e4 | 1038 | |
f5bbdacc | 1039 | readlen -= bytes; |
61b03bd7 | 1040 | |
f5bbdacc | 1041 | if (!readlen) |
61b03bd7 | 1042 | break; |
1da177e4 LT |
1043 | |
1044 | /* For subsequent reads align to page boundary. */ | |
1045 | col = 0; | |
1046 | /* Increment page address */ | |
1047 | realpage++; | |
1048 | ||
ace4dfee | 1049 | page = realpage & chip->pagemask; |
1da177e4 LT |
1050 | /* Check, if we cross a chip boundary */ |
1051 | if (!page) { | |
1052 | chipnr++; | |
ace4dfee TG |
1053 | chip->select_chip(mtd, -1); |
1054 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1055 | } |
f5bbdacc | 1056 | |
61b03bd7 TG |
1057 | /* Check, if the chip supports auto page increment |
1058 | * or if we have hit a block boundary. | |
e0c7d767 | 1059 | */ |
f5bbdacc | 1060 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) |
61b03bd7 | 1061 | sndcmd = 1; |
1da177e4 LT |
1062 | } |
1063 | ||
8593fbc6 | 1064 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
1065 | if (oob) |
1066 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 1067 | |
f5bbdacc TG |
1068 | if (ret) |
1069 | return ret; | |
1070 | ||
9a1fcdfd TG |
1071 | if (mtd->ecc_stats.failed - stats.failed) |
1072 | return -EBADMSG; | |
1073 | ||
1074 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
f5bbdacc TG |
1075 | } |
1076 | ||
1077 | /** | |
1078 | * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc | |
1079 | * @mtd: MTD device structure | |
1080 | * @from: offset to read from | |
1081 | * @len: number of bytes to read | |
1082 | * @retlen: pointer to variable to store the number of read bytes | |
1083 | * @buf: the databuffer to put data | |
1084 | * | |
1085 | * Get hold of the chip and call nand_do_read | |
1086 | */ | |
1087 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1088 | size_t *retlen, uint8_t *buf) | |
1089 | { | |
8593fbc6 | 1090 | struct nand_chip *chip = mtd->priv; |
f5bbdacc TG |
1091 | int ret; |
1092 | ||
f5bbdacc TG |
1093 | /* Do not allow reads past end of device */ |
1094 | if ((from + len) > mtd->size) | |
1095 | return -EINVAL; | |
1096 | if (!len) | |
1097 | return 0; | |
1098 | ||
8593fbc6 | 1099 | nand_get_device(chip, mtd, FL_READING); |
f5bbdacc | 1100 | |
8593fbc6 TG |
1101 | chip->ops.len = len; |
1102 | chip->ops.datbuf = buf; | |
1103 | chip->ops.oobbuf = NULL; | |
1104 | ||
1105 | ret = nand_do_read_ops(mtd, from, &chip->ops); | |
f5bbdacc | 1106 | |
7fd5aecc RP |
1107 | *retlen = chip->ops.retlen; |
1108 | ||
f5bbdacc TG |
1109 | nand_release_device(mtd); |
1110 | ||
1111 | return ret; | |
1da177e4 LT |
1112 | } |
1113 | ||
7bc3312b TG |
1114 | /** |
1115 | * nand_read_oob_std - [REPLACABLE] the most common OOB data read function | |
1116 | * @mtd: mtd info structure | |
1117 | * @chip: nand chip info structure | |
1118 | * @page: page number to read | |
1119 | * @sndcmd: flag whether to issue read command or not | |
1120 | */ | |
1121 | static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1122 | int page, int sndcmd) | |
1123 | { | |
1124 | if (sndcmd) { | |
1125 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1126 | sndcmd = 0; | |
1127 | } | |
1128 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1129 | return sndcmd; | |
1130 | } | |
1131 | ||
1132 | /** | |
1133 | * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC | |
1134 | * with syndromes | |
1135 | * @mtd: mtd info structure | |
1136 | * @chip: nand chip info structure | |
1137 | * @page: page number to read | |
1138 | * @sndcmd: flag whether to issue read command or not | |
1139 | */ | |
1140 | static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1141 | int page, int sndcmd) | |
1142 | { | |
1143 | uint8_t *buf = chip->oob_poi; | |
1144 | int length = mtd->oobsize; | |
1145 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1146 | int eccsize = chip->ecc.size; | |
1147 | uint8_t *bufpoi = buf; | |
1148 | int i, toread, sndrnd = 0, pos; | |
1149 | ||
1150 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
1151 | for (i = 0; i < chip->ecc.steps; i++) { | |
1152 | if (sndrnd) { | |
1153 | pos = eccsize + i * (eccsize + chunk); | |
1154 | if (mtd->writesize > 512) | |
1155 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
1156 | else | |
1157 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
1158 | } else | |
1159 | sndrnd = 1; | |
1160 | toread = min_t(int, length, chunk); | |
1161 | chip->read_buf(mtd, bufpoi, toread); | |
1162 | bufpoi += toread; | |
1163 | length -= toread; | |
1164 | } | |
1165 | if (length > 0) | |
1166 | chip->read_buf(mtd, bufpoi, length); | |
1167 | ||
1168 | return 1; | |
1169 | } | |
1170 | ||
1171 | /** | |
1172 | * nand_write_oob_std - [REPLACABLE] the most common OOB data write function | |
1173 | * @mtd: mtd info structure | |
1174 | * @chip: nand chip info structure | |
1175 | * @page: page number to write | |
1176 | */ | |
1177 | static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1178 | int page) | |
1179 | { | |
1180 | int status = 0; | |
1181 | const uint8_t *buf = chip->oob_poi; | |
1182 | int length = mtd->oobsize; | |
1183 | ||
1184 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
1185 | chip->write_buf(mtd, buf, length); | |
1186 | /* Send command to program the OOB data */ | |
1187 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1188 | ||
1189 | status = chip->waitfunc(mtd, chip); | |
1190 | ||
0d420f9d | 1191 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b TG |
1192 | } |
1193 | ||
1194 | /** | |
1195 | * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC | |
1196 | * with syndrome - only for large page flash ! | |
1197 | * @mtd: mtd info structure | |
1198 | * @chip: nand chip info structure | |
1199 | * @page: page number to write | |
1200 | */ | |
1201 | static int nand_write_oob_syndrome(struct mtd_info *mtd, | |
1202 | struct nand_chip *chip, int page) | |
1203 | { | |
1204 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1205 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
1206 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
1207 | const uint8_t *bufpoi = chip->oob_poi; | |
1208 | ||
1209 | /* | |
1210 | * data-ecc-data-ecc ... ecc-oob | |
1211 | * or | |
1212 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
1213 | */ | |
1214 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
1215 | pos = steps * (eccsize + chunk); | |
1216 | steps = 0; | |
1217 | } else | |
8b0036ee | 1218 | pos = eccsize; |
7bc3312b TG |
1219 | |
1220 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
1221 | for (i = 0; i < steps; i++) { | |
1222 | if (sndcmd) { | |
1223 | if (mtd->writesize <= 512) { | |
1224 | uint32_t fill = 0xFFFFFFFF; | |
1225 | ||
1226 | len = eccsize; | |
1227 | while (len > 0) { | |
1228 | int num = min_t(int, len, 4); | |
1229 | chip->write_buf(mtd, (uint8_t *)&fill, | |
1230 | num); | |
1231 | len -= num; | |
1232 | } | |
1233 | } else { | |
1234 | pos = eccsize + i * (eccsize + chunk); | |
1235 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
1236 | } | |
1237 | } else | |
1238 | sndcmd = 1; | |
1239 | len = min_t(int, length, chunk); | |
1240 | chip->write_buf(mtd, bufpoi, len); | |
1241 | bufpoi += len; | |
1242 | length -= len; | |
1243 | } | |
1244 | if (length > 0) | |
1245 | chip->write_buf(mtd, bufpoi, length); | |
1246 | ||
1247 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1248 | status = chip->waitfunc(mtd, chip); | |
1249 | ||
1250 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
1251 | } | |
1252 | ||
1da177e4 | 1253 | /** |
8593fbc6 | 1254 | * nand_do_read_oob - [Intern] NAND read out-of-band |
1da177e4 LT |
1255 | * @mtd: MTD device structure |
1256 | * @from: offset to read from | |
8593fbc6 | 1257 | * @ops: oob operations description structure |
1da177e4 LT |
1258 | * |
1259 | * NAND read out-of-band data from the spare area | |
1260 | */ | |
8593fbc6 TG |
1261 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
1262 | struct mtd_oob_ops *ops) | |
1da177e4 | 1263 | { |
7bc3312b | 1264 | int page, realpage, chipnr, sndcmd = 1; |
ace4dfee | 1265 | struct nand_chip *chip = mtd->priv; |
7314e9e7 | 1266 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; |
7014568b VW |
1267 | int readlen = ops->ooblen; |
1268 | int len; | |
7bc3312b | 1269 | uint8_t *buf = ops->oobbuf; |
61b03bd7 | 1270 | |
7e9a0bb0 AM |
1271 | DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n", |
1272 | (unsigned long long)from, readlen); | |
1da177e4 | 1273 | |
03736155 | 1274 | if (ops->mode == MTD_OOB_AUTO) |
7014568b | 1275 | len = chip->ecc.layout->oobavail; |
03736155 AH |
1276 | else |
1277 | len = mtd->oobsize; | |
1278 | ||
1279 | if (unlikely(ops->ooboffs >= len)) { | |
1280 | DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " | |
1281 | "Attempt to start read outside oob\n"); | |
1282 | return -EINVAL; | |
1283 | } | |
1284 | ||
1285 | /* Do not allow reads past end of device */ | |
1286 | if (unlikely(from >= mtd->size || | |
1287 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
1288 | (from >> chip->page_shift)) * len)) { | |
1289 | DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " | |
1290 | "Attempt read beyond end of device\n"); | |
1291 | return -EINVAL; | |
1292 | } | |
7014568b | 1293 | |
7314e9e7 | 1294 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 1295 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1296 | |
7314e9e7 TG |
1297 | /* Shift to get page */ |
1298 | realpage = (int)(from >> chip->page_shift); | |
1299 | page = realpage & chip->pagemask; | |
1da177e4 | 1300 | |
7314e9e7 | 1301 | while(1) { |
7bc3312b | 1302 | sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd); |
7014568b VW |
1303 | |
1304 | len = min(len, readlen); | |
1305 | buf = nand_transfer_oob(chip, buf, ops, len); | |
8593fbc6 | 1306 | |
7314e9e7 TG |
1307 | if (!(chip->options & NAND_NO_READRDY)) { |
1308 | /* | |
1309 | * Apply delay or wait for ready/busy pin. Do this | |
1310 | * before the AUTOINCR check, so no problems arise if a | |
1311 | * chip which does auto increment is marked as | |
1312 | * NOAUTOINCR by the board driver. | |
19870da7 | 1313 | */ |
ace4dfee TG |
1314 | if (!chip->dev_ready) |
1315 | udelay(chip->chip_delay); | |
19870da7 TG |
1316 | else |
1317 | nand_wait_ready(mtd); | |
7314e9e7 | 1318 | } |
19870da7 | 1319 | |
7014568b | 1320 | readlen -= len; |
0d420f9d SZ |
1321 | if (!readlen) |
1322 | break; | |
1323 | ||
7314e9e7 TG |
1324 | /* Increment page address */ |
1325 | realpage++; | |
1326 | ||
1327 | page = realpage & chip->pagemask; | |
1328 | /* Check, if we cross a chip boundary */ | |
1329 | if (!page) { | |
1330 | chipnr++; | |
1331 | chip->select_chip(mtd, -1); | |
1332 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1333 | } |
7314e9e7 TG |
1334 | |
1335 | /* Check, if the chip supports auto page increment | |
1336 | * or if we have hit a block boundary. | |
1337 | */ | |
1338 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) | |
1339 | sndcmd = 1; | |
1da177e4 LT |
1340 | } |
1341 | ||
7014568b | 1342 | ops->oobretlen = ops->ooblen; |
1da177e4 LT |
1343 | return 0; |
1344 | } | |
1345 | ||
1346 | /** | |
8593fbc6 | 1347 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
1da177e4 | 1348 | * @mtd: MTD device structure |
1da177e4 | 1349 | * @from: offset to read from |
8593fbc6 | 1350 | * @ops: oob operation description structure |
1da177e4 | 1351 | * |
8593fbc6 | 1352 | * NAND read data and/or out-of-band data |
1da177e4 | 1353 | */ |
8593fbc6 TG |
1354 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
1355 | struct mtd_oob_ops *ops) | |
1da177e4 | 1356 | { |
ace4dfee | 1357 | struct nand_chip *chip = mtd->priv; |
8593fbc6 TG |
1358 | int ret = -ENOTSUPP; |
1359 | ||
1360 | ops->retlen = 0; | |
1da177e4 LT |
1361 | |
1362 | /* Do not allow reads past end of device */ | |
7014568b | 1363 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
8593fbc6 | 1364 | DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " |
ace4dfee | 1365 | "Attempt read beyond end of device\n"); |
1da177e4 LT |
1366 | return -EINVAL; |
1367 | } | |
1368 | ||
ace4dfee | 1369 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 | 1370 | |
8593fbc6 TG |
1371 | switch(ops->mode) { |
1372 | case MTD_OOB_PLACE: | |
1373 | case MTD_OOB_AUTO: | |
8593fbc6 | 1374 | case MTD_OOB_RAW: |
8593fbc6 | 1375 | break; |
1da177e4 | 1376 | |
8593fbc6 TG |
1377 | default: |
1378 | goto out; | |
1379 | } | |
1da177e4 | 1380 | |
8593fbc6 TG |
1381 | if (!ops->datbuf) |
1382 | ret = nand_do_read_oob(mtd, from, ops); | |
1383 | else | |
1384 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 1385 | |
8593fbc6 TG |
1386 | out: |
1387 | nand_release_device(mtd); | |
1388 | return ret; | |
1389 | } | |
61b03bd7 | 1390 | |
1da177e4 | 1391 | |
8593fbc6 TG |
1392 | /** |
1393 | * nand_write_page_raw - [Intern] raw page write function | |
1394 | * @mtd: mtd info structure | |
1395 | * @chip: nand chip info structure | |
1396 | * @buf: data buffer | |
1397 | */ | |
1398 | static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1399 | const uint8_t *buf) | |
1400 | { | |
1401 | chip->write_buf(mtd, buf, mtd->writesize); | |
1402 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1da177e4 LT |
1403 | } |
1404 | ||
9223a456 | 1405 | /** |
d29ebdbe | 1406 | * nand_write_page_swecc - [REPLACABLE] software ecc based page write function |
f75e5097 TG |
1407 | * @mtd: mtd info structure |
1408 | * @chip: nand chip info structure | |
1409 | * @buf: data buffer | |
9223a456 | 1410 | */ |
f75e5097 TG |
1411 | static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1412 | const uint8_t *buf) | |
9223a456 | 1413 | { |
f75e5097 TG |
1414 | int i, eccsize = chip->ecc.size; |
1415 | int eccbytes = chip->ecc.bytes; | |
1416 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 1417 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 1418 | const uint8_t *p = buf; |
8b099a39 | 1419 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1420 | |
8593fbc6 TG |
1421 | /* Software ecc calculation */ |
1422 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1423 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 1424 | |
8593fbc6 TG |
1425 | for (i = 0; i < chip->ecc.total; i++) |
1426 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 | 1427 | |
90424de8 | 1428 | chip->ecc.write_page_raw(mtd, chip, buf); |
f75e5097 | 1429 | } |
9223a456 | 1430 | |
f75e5097 | 1431 | /** |
d29ebdbe | 1432 | * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function |
f75e5097 TG |
1433 | * @mtd: mtd info structure |
1434 | * @chip: nand chip info structure | |
1435 | * @buf: data buffer | |
1436 | */ | |
1437 | static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, | |
1438 | const uint8_t *buf) | |
1439 | { | |
1440 | int i, eccsize = chip->ecc.size; | |
1441 | int eccbytes = chip->ecc.bytes; | |
1442 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 1443 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 1444 | const uint8_t *p = buf; |
8b099a39 | 1445 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1446 | |
f75e5097 TG |
1447 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1448 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 1449 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 1450 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
1451 | } |
1452 | ||
f75e5097 TG |
1453 | for (i = 0; i < chip->ecc.total; i++) |
1454 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
1455 | ||
1456 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
9223a456 TG |
1457 | } |
1458 | ||
61b03bd7 | 1459 | /** |
d29ebdbe | 1460 | * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write |
f75e5097 TG |
1461 | * @mtd: mtd info structure |
1462 | * @chip: nand chip info structure | |
1463 | * @buf: data buffer | |
1da177e4 | 1464 | * |
f75e5097 TG |
1465 | * The hw generator calculates the error syndrome automatically. Therefor |
1466 | * we need a special oob layout and handling. | |
1467 | */ | |
1468 | static void nand_write_page_syndrome(struct mtd_info *mtd, | |
1469 | struct nand_chip *chip, const uint8_t *buf) | |
1da177e4 | 1470 | { |
f75e5097 TG |
1471 | int i, eccsize = chip->ecc.size; |
1472 | int eccbytes = chip->ecc.bytes; | |
1473 | int eccsteps = chip->ecc.steps; | |
1474 | const uint8_t *p = buf; | |
1475 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 1476 | |
f75e5097 | 1477 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 1478 | |
f75e5097 TG |
1479 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
1480 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 1481 | |
f75e5097 TG |
1482 | if (chip->ecc.prepad) { |
1483 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
1484 | oob += chip->ecc.prepad; | |
1485 | } | |
1486 | ||
1487 | chip->ecc.calculate(mtd, p, oob); | |
1488 | chip->write_buf(mtd, oob, eccbytes); | |
1489 | oob += eccbytes; | |
1490 | ||
1491 | if (chip->ecc.postpad) { | |
1492 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
1493 | oob += chip->ecc.postpad; | |
1da177e4 | 1494 | } |
1da177e4 | 1495 | } |
f75e5097 TG |
1496 | |
1497 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 1498 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
1499 | if (i) |
1500 | chip->write_buf(mtd, oob, i); | |
1501 | } | |
1502 | ||
1503 | /** | |
956e944c | 1504 | * nand_write_page - [REPLACEABLE] write one page |
f75e5097 TG |
1505 | * @mtd: MTD device structure |
1506 | * @chip: NAND chip descriptor | |
1507 | * @buf: the data to write | |
1508 | * @page: page number to write | |
1509 | * @cached: cached programming | |
efbfe96c | 1510 | * @raw: use _raw version of write_page |
f75e5097 TG |
1511 | */ |
1512 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
956e944c | 1513 | const uint8_t *buf, int page, int cached, int raw) |
f75e5097 TG |
1514 | { |
1515 | int status; | |
1516 | ||
1517 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
1518 | ||
956e944c DW |
1519 | if (unlikely(raw)) |
1520 | chip->ecc.write_page_raw(mtd, chip, buf); | |
1521 | else | |
1522 | chip->ecc.write_page(mtd, chip, buf); | |
f75e5097 TG |
1523 | |
1524 | /* | |
1525 | * Cached progamming disabled for now, Not sure if its worth the | |
1526 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s) | |
1527 | */ | |
1528 | cached = 0; | |
1529 | ||
1530 | if (!cached || !(chip->options & NAND_CACHEPRG)) { | |
1531 | ||
1532 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
7bc3312b | 1533 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
1534 | /* |
1535 | * See if operation failed and additional status checks are | |
1536 | * available | |
1537 | */ | |
1538 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
1539 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
1540 | page); | |
1541 | ||
1542 | if (status & NAND_STATUS_FAIL) | |
1543 | return -EIO; | |
1544 | } else { | |
1545 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
7bc3312b | 1546 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
1547 | } |
1548 | ||
1549 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE | |
1550 | /* Send command to read back the data */ | |
1551 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1552 | ||
1553 | if (chip->verify_buf(mtd, buf, mtd->writesize)) | |
1554 | return -EIO; | |
1555 | #endif | |
1556 | return 0; | |
1da177e4 LT |
1557 | } |
1558 | ||
8593fbc6 TG |
1559 | /** |
1560 | * nand_fill_oob - [Internal] Transfer client buffer to oob | |
1561 | * @chip: nand chip structure | |
1562 | * @oob: oob data buffer | |
1563 | * @ops: oob ops structure | |
1564 | */ | |
1565 | static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, | |
1566 | struct mtd_oob_ops *ops) | |
1567 | { | |
1568 | size_t len = ops->ooblen; | |
1569 | ||
1570 | switch(ops->mode) { | |
1571 | ||
1572 | case MTD_OOB_PLACE: | |
1573 | case MTD_OOB_RAW: | |
1574 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); | |
1575 | return oob + len; | |
1576 | ||
1577 | case MTD_OOB_AUTO: { | |
1578 | struct nand_oobfree *free = chip->ecc.layout->oobfree; | |
7bc3312b TG |
1579 | uint32_t boffs = 0, woffs = ops->ooboffs; |
1580 | size_t bytes = 0; | |
8593fbc6 TG |
1581 | |
1582 | for(; free->length && len; free++, len -= bytes) { | |
7bc3312b TG |
1583 | /* Write request not from offset 0 ? */ |
1584 | if (unlikely(woffs)) { | |
1585 | if (woffs >= free->length) { | |
1586 | woffs -= free->length; | |
1587 | continue; | |
1588 | } | |
1589 | boffs = free->offset + woffs; | |
1590 | bytes = min_t(size_t, len, | |
1591 | (free->length - woffs)); | |
1592 | woffs = 0; | |
1593 | } else { | |
1594 | bytes = min_t(size_t, len, free->length); | |
1595 | boffs = free->offset; | |
1596 | } | |
8b0036ee | 1597 | memcpy(chip->oob_poi + boffs, oob, bytes); |
8593fbc6 TG |
1598 | oob += bytes; |
1599 | } | |
1600 | return oob; | |
1601 | } | |
1602 | default: | |
1603 | BUG(); | |
1604 | } | |
1605 | return NULL; | |
1606 | } | |
1607 | ||
29072b96 | 1608 | #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0 |
1da177e4 LT |
1609 | |
1610 | /** | |
8593fbc6 | 1611 | * nand_do_write_ops - [Internal] NAND write with ECC |
1da177e4 LT |
1612 | * @mtd: MTD device structure |
1613 | * @to: offset to write to | |
8593fbc6 | 1614 | * @ops: oob operations description structure |
1da177e4 LT |
1615 | * |
1616 | * NAND write with ECC | |
1617 | */ | |
8593fbc6 TG |
1618 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
1619 | struct mtd_oob_ops *ops) | |
1da177e4 | 1620 | { |
29072b96 | 1621 | int chipnr, realpage, page, blockmask, column; |
ace4dfee | 1622 | struct nand_chip *chip = mtd->priv; |
8593fbc6 TG |
1623 | uint32_t writelen = ops->len; |
1624 | uint8_t *oob = ops->oobbuf; | |
1625 | uint8_t *buf = ops->datbuf; | |
29072b96 | 1626 | int ret, subpage; |
1da177e4 | 1627 | |
8593fbc6 | 1628 | ops->retlen = 0; |
29072b96 TG |
1629 | if (!writelen) |
1630 | return 0; | |
1da177e4 | 1631 | |
61b03bd7 | 1632 | /* reject writes, which are not page aligned */ |
8593fbc6 | 1633 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
f75e5097 TG |
1634 | printk(KERN_NOTICE "nand_write: " |
1635 | "Attempt to write not page aligned data\n"); | |
1da177e4 LT |
1636 | return -EINVAL; |
1637 | } | |
1638 | ||
29072b96 TG |
1639 | column = to & (mtd->writesize - 1); |
1640 | subpage = column || (writelen & (mtd->writesize - 1)); | |
1641 | ||
1642 | if (subpage && oob) | |
1643 | return -EINVAL; | |
1da177e4 | 1644 | |
6a930961 TG |
1645 | chipnr = (int)(to >> chip->chip_shift); |
1646 | chip->select_chip(mtd, chipnr); | |
1647 | ||
1da177e4 LT |
1648 | /* Check, if it is write protected */ |
1649 | if (nand_check_wp(mtd)) | |
8593fbc6 | 1650 | return -EIO; |
1da177e4 | 1651 | |
f75e5097 TG |
1652 | realpage = (int)(to >> chip->page_shift); |
1653 | page = realpage & chip->pagemask; | |
1654 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
1655 | ||
1656 | /* Invalidate the page cache, when we write to the cached page */ | |
1657 | if (to <= (chip->pagebuf << chip->page_shift) && | |
8593fbc6 | 1658 | (chip->pagebuf << chip->page_shift) < (to + ops->len)) |
ace4dfee | 1659 | chip->pagebuf = -1; |
61b03bd7 | 1660 | |
7dcdcbef DW |
1661 | /* If we're not given explicit OOB data, let it be 0xFF */ |
1662 | if (likely(!oob)) | |
1663 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
61b03bd7 | 1664 | |
f75e5097 | 1665 | while(1) { |
29072b96 | 1666 | int bytes = mtd->writesize; |
f75e5097 | 1667 | int cached = writelen > bytes && page != blockmask; |
29072b96 TG |
1668 | uint8_t *wbuf = buf; |
1669 | ||
1670 | /* Partial page write ? */ | |
1671 | if (unlikely(column || writelen < (mtd->writesize - 1))) { | |
1672 | cached = 0; | |
1673 | bytes = min_t(int, bytes - column, (int) writelen); | |
1674 | chip->pagebuf = -1; | |
1675 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
1676 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
1677 | wbuf = chip->buffers->databuf; | |
1678 | } | |
1da177e4 | 1679 | |
8593fbc6 TG |
1680 | if (unlikely(oob)) |
1681 | oob = nand_fill_oob(chip, oob, ops); | |
1682 | ||
29072b96 | 1683 | ret = chip->write_page(mtd, chip, wbuf, page, cached, |
956e944c | 1684 | (ops->mode == MTD_OOB_RAW)); |
f75e5097 TG |
1685 | if (ret) |
1686 | break; | |
1687 | ||
1688 | writelen -= bytes; | |
1689 | if (!writelen) | |
1690 | break; | |
1691 | ||
29072b96 | 1692 | column = 0; |
f75e5097 TG |
1693 | buf += bytes; |
1694 | realpage++; | |
1695 | ||
1696 | page = realpage & chip->pagemask; | |
1697 | /* Check, if we cross a chip boundary */ | |
1698 | if (!page) { | |
1699 | chipnr++; | |
1700 | chip->select_chip(mtd, -1); | |
1701 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
1702 | } |
1703 | } | |
8593fbc6 | 1704 | |
8593fbc6 | 1705 | ops->retlen = ops->len - writelen; |
7014568b VW |
1706 | if (unlikely(oob)) |
1707 | ops->oobretlen = ops->ooblen; | |
1da177e4 LT |
1708 | return ret; |
1709 | } | |
1710 | ||
f75e5097 | 1711 | /** |
8593fbc6 | 1712 | * nand_write - [MTD Interface] NAND write with ECC |
f75e5097 | 1713 | * @mtd: MTD device structure |
f75e5097 TG |
1714 | * @to: offset to write to |
1715 | * @len: number of bytes to write | |
8593fbc6 TG |
1716 | * @retlen: pointer to variable to store the number of written bytes |
1717 | * @buf: the data to write | |
f75e5097 | 1718 | * |
8593fbc6 | 1719 | * NAND write with ECC |
f75e5097 | 1720 | */ |
8593fbc6 TG |
1721 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
1722 | size_t *retlen, const uint8_t *buf) | |
f75e5097 TG |
1723 | { |
1724 | struct nand_chip *chip = mtd->priv; | |
f75e5097 TG |
1725 | int ret; |
1726 | ||
8593fbc6 TG |
1727 | /* Do not allow reads past end of device */ |
1728 | if ((to + len) > mtd->size) | |
f75e5097 | 1729 | return -EINVAL; |
8593fbc6 TG |
1730 | if (!len) |
1731 | return 0; | |
f75e5097 | 1732 | |
7bc3312b | 1733 | nand_get_device(chip, mtd, FL_WRITING); |
f75e5097 | 1734 | |
8593fbc6 TG |
1735 | chip->ops.len = len; |
1736 | chip->ops.datbuf = (uint8_t *)buf; | |
1737 | chip->ops.oobbuf = NULL; | |
f75e5097 | 1738 | |
8593fbc6 | 1739 | ret = nand_do_write_ops(mtd, to, &chip->ops); |
f75e5097 | 1740 | |
7fd5aecc RP |
1741 | *retlen = chip->ops.retlen; |
1742 | ||
f75e5097 | 1743 | nand_release_device(mtd); |
8593fbc6 | 1744 | |
8593fbc6 | 1745 | return ret; |
f75e5097 | 1746 | } |
7314e9e7 | 1747 | |
1da177e4 | 1748 | /** |
8593fbc6 | 1749 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
1da177e4 LT |
1750 | * @mtd: MTD device structure |
1751 | * @to: offset to write to | |
8593fbc6 | 1752 | * @ops: oob operation description structure |
1da177e4 LT |
1753 | * |
1754 | * NAND write out-of-band | |
1755 | */ | |
8593fbc6 TG |
1756 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
1757 | struct mtd_oob_ops *ops) | |
1da177e4 | 1758 | { |
03736155 | 1759 | int chipnr, page, status, len; |
ace4dfee | 1760 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 1761 | |
7314e9e7 | 1762 | DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", |
7014568b | 1763 | (unsigned int)to, (int)ops->ooblen); |
1da177e4 | 1764 | |
03736155 AH |
1765 | if (ops->mode == MTD_OOB_AUTO) |
1766 | len = chip->ecc.layout->oobavail; | |
1767 | else | |
1768 | len = mtd->oobsize; | |
1769 | ||
1da177e4 | 1770 | /* Do not allow write past end of page */ |
03736155 | 1771 | if ((ops->ooboffs + ops->ooblen) > len) { |
7314e9e7 TG |
1772 | DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: " |
1773 | "Attempt to write past end of page\n"); | |
1da177e4 LT |
1774 | return -EINVAL; |
1775 | } | |
1776 | ||
03736155 AH |
1777 | if (unlikely(ops->ooboffs >= len)) { |
1778 | DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " | |
1779 | "Attempt to start write outside oob\n"); | |
1780 | return -EINVAL; | |
1781 | } | |
1782 | ||
1783 | /* Do not allow reads past end of device */ | |
1784 | if (unlikely(to >= mtd->size || | |
1785 | ops->ooboffs + ops->ooblen > | |
1786 | ((mtd->size >> chip->page_shift) - | |
1787 | (to >> chip->page_shift)) * len)) { | |
1788 | DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " | |
1789 | "Attempt write beyond end of device\n"); | |
1790 | return -EINVAL; | |
1791 | } | |
1792 | ||
7314e9e7 | 1793 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 1794 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1795 | |
7314e9e7 TG |
1796 | /* Shift to get page */ |
1797 | page = (int)(to >> chip->page_shift); | |
1798 | ||
1799 | /* | |
1800 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
1801 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
1802 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
1803 | * it in the doc2000 driver in August 1999. dwmw2. | |
1804 | */ | |
ace4dfee | 1805 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
1806 | |
1807 | /* Check, if it is write protected */ | |
1808 | if (nand_check_wp(mtd)) | |
8593fbc6 | 1809 | return -EROFS; |
61b03bd7 | 1810 | |
1da177e4 | 1811 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
1812 | if (page == chip->pagebuf) |
1813 | chip->pagebuf = -1; | |
1da177e4 | 1814 | |
7bc3312b TG |
1815 | memset(chip->oob_poi, 0xff, mtd->oobsize); |
1816 | nand_fill_oob(chip, ops->oobbuf, ops); | |
1817 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); | |
1818 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
1da177e4 | 1819 | |
7bc3312b TG |
1820 | if (status) |
1821 | return status; | |
1da177e4 | 1822 | |
7014568b | 1823 | ops->oobretlen = ops->ooblen; |
1da177e4 | 1824 | |
7bc3312b | 1825 | return 0; |
8593fbc6 TG |
1826 | } |
1827 | ||
1828 | /** | |
1829 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
1830 | * @mtd: MTD device structure | |
844d3b42 | 1831 | * @to: offset to write to |
8593fbc6 TG |
1832 | * @ops: oob operation description structure |
1833 | */ | |
1834 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
1835 | struct mtd_oob_ops *ops) | |
1836 | { | |
8593fbc6 TG |
1837 | struct nand_chip *chip = mtd->priv; |
1838 | int ret = -ENOTSUPP; | |
1839 | ||
1840 | ops->retlen = 0; | |
1841 | ||
1842 | /* Do not allow writes past end of device */ | |
7014568b | 1843 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
8593fbc6 TG |
1844 | DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " |
1845 | "Attempt read beyond end of device\n"); | |
1846 | return -EINVAL; | |
1847 | } | |
1848 | ||
7bc3312b | 1849 | nand_get_device(chip, mtd, FL_WRITING); |
8593fbc6 TG |
1850 | |
1851 | switch(ops->mode) { | |
1852 | case MTD_OOB_PLACE: | |
1853 | case MTD_OOB_AUTO: | |
8593fbc6 | 1854 | case MTD_OOB_RAW: |
8593fbc6 TG |
1855 | break; |
1856 | ||
1857 | default: | |
1858 | goto out; | |
1859 | } | |
1860 | ||
1861 | if (!ops->datbuf) | |
1862 | ret = nand_do_write_oob(mtd, to, ops); | |
1863 | else | |
1864 | ret = nand_do_write_ops(mtd, to, ops); | |
1865 | ||
e0c7d767 | 1866 | out: |
1da177e4 | 1867 | nand_release_device(mtd); |
1da177e4 LT |
1868 | return ret; |
1869 | } | |
1870 | ||
1da177e4 LT |
1871 | /** |
1872 | * single_erease_cmd - [GENERIC] NAND standard block erase command function | |
1873 | * @mtd: MTD device structure | |
1874 | * @page: the page address of the block which will be erased | |
1875 | * | |
1876 | * Standard erase command for NAND chips | |
1877 | */ | |
e0c7d767 | 1878 | static void single_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 1879 | { |
ace4dfee | 1880 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 1881 | /* Send commands to erase a block */ |
ace4dfee TG |
1882 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
1883 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
1884 | } |
1885 | ||
1886 | /** | |
1887 | * multi_erease_cmd - [GENERIC] AND specific block erase command function | |
1888 | * @mtd: MTD device structure | |
1889 | * @page: the page address of the block which will be erased | |
1890 | * | |
1891 | * AND multi block erase command function | |
1892 | * Erase 4 consecutive blocks | |
1893 | */ | |
e0c7d767 | 1894 | static void multi_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 1895 | { |
ace4dfee | 1896 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 1897 | /* Send commands to erase a block */ |
ace4dfee TG |
1898 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); |
1899 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
1900 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
1901 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); | |
1902 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
1903 | } |
1904 | ||
1905 | /** | |
1906 | * nand_erase - [MTD Interface] erase block(s) | |
1907 | * @mtd: MTD device structure | |
1908 | * @instr: erase instruction | |
1909 | * | |
1910 | * Erase one ore more blocks | |
1911 | */ | |
e0c7d767 | 1912 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 1913 | { |
e0c7d767 | 1914 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 1915 | } |
61b03bd7 | 1916 | |
30f464b7 | 1917 | #define BBT_PAGE_MASK 0xffffff3f |
1da177e4 | 1918 | /** |
ace4dfee | 1919 | * nand_erase_nand - [Internal] erase block(s) |
1da177e4 LT |
1920 | * @mtd: MTD device structure |
1921 | * @instr: erase instruction | |
1922 | * @allowbbt: allow erasing the bbt area | |
1923 | * | |
1924 | * Erase one ore more blocks | |
1925 | */ | |
ace4dfee TG |
1926 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
1927 | int allowbbt) | |
1da177e4 LT |
1928 | { |
1929 | int page, len, status, pages_per_block, ret, chipnr; | |
ace4dfee TG |
1930 | struct nand_chip *chip = mtd->priv; |
1931 | int rewrite_bbt[NAND_MAX_CHIPS]={0}; | |
1932 | unsigned int bbt_masked_page = 0xffffffff; | |
1da177e4 | 1933 | |
ace4dfee TG |
1934 | DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n", |
1935 | (unsigned int)instr->addr, (unsigned int)instr->len); | |
1da177e4 LT |
1936 | |
1937 | /* Start address must align on block boundary */ | |
ace4dfee | 1938 | if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) { |
e0c7d767 | 1939 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n"); |
1da177e4 LT |
1940 | return -EINVAL; |
1941 | } | |
1942 | ||
1943 | /* Length must align on block boundary */ | |
ace4dfee TG |
1944 | if (instr->len & ((1 << chip->phys_erase_shift) - 1)) { |
1945 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " | |
1946 | "Length not block aligned\n"); | |
1da177e4 LT |
1947 | return -EINVAL; |
1948 | } | |
1949 | ||
1950 | /* Do not allow erase past end of device */ | |
1951 | if ((instr->len + instr->addr) > mtd->size) { | |
ace4dfee TG |
1952 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " |
1953 | "Erase past end of device\n"); | |
1da177e4 LT |
1954 | return -EINVAL; |
1955 | } | |
1956 | ||
1957 | instr->fail_addr = 0xffffffff; | |
1958 | ||
1959 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 1960 | nand_get_device(chip, mtd, FL_ERASING); |
1da177e4 LT |
1961 | |
1962 | /* Shift to get first page */ | |
ace4dfee TG |
1963 | page = (int)(instr->addr >> chip->page_shift); |
1964 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
1965 | |
1966 | /* Calculate pages in each block */ | |
ace4dfee | 1967 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
1968 | |
1969 | /* Select the NAND device */ | |
ace4dfee | 1970 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1971 | |
1da177e4 LT |
1972 | /* Check, if it is write protected */ |
1973 | if (nand_check_wp(mtd)) { | |
ace4dfee TG |
1974 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " |
1975 | "Device is write protected!!!\n"); | |
1da177e4 LT |
1976 | instr->state = MTD_ERASE_FAILED; |
1977 | goto erase_exit; | |
1978 | } | |
1979 | ||
ace4dfee TG |
1980 | /* |
1981 | * If BBT requires refresh, set the BBT page mask to see if the BBT | |
1982 | * should be rewritten. Otherwise the mask is set to 0xffffffff which | |
1983 | * can not be matched. This is also done when the bbt is actually | |
1984 | * erased to avoid recusrsive updates | |
1985 | */ | |
1986 | if (chip->options & BBT_AUTO_REFRESH && !allowbbt) | |
1987 | bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK; | |
30f464b7 | 1988 | |
1da177e4 LT |
1989 | /* Loop through the pages */ |
1990 | len = instr->len; | |
1991 | ||
1992 | instr->state = MTD_ERASING; | |
1993 | ||
1994 | while (len) { | |
ace4dfee TG |
1995 | /* |
1996 | * heck if we have a bad block, we do not erase bad blocks ! | |
1997 | */ | |
1998 | if (nand_block_checkbad(mtd, ((loff_t) page) << | |
1999 | chip->page_shift, 0, allowbbt)) { | |
2000 | printk(KERN_WARNING "nand_erase: attempt to erase a " | |
2001 | "bad block at page 0x%08x\n", page); | |
1da177e4 LT |
2002 | instr->state = MTD_ERASE_FAILED; |
2003 | goto erase_exit; | |
2004 | } | |
61b03bd7 | 2005 | |
ace4dfee TG |
2006 | /* |
2007 | * Invalidate the page cache, if we erase the block which | |
2008 | * contains the current cached page | |
2009 | */ | |
2010 | if (page <= chip->pagebuf && chip->pagebuf < | |
2011 | (page + pages_per_block)) | |
2012 | chip->pagebuf = -1; | |
1da177e4 | 2013 | |
ace4dfee | 2014 | chip->erase_cmd(mtd, page & chip->pagemask); |
61b03bd7 | 2015 | |
7bc3312b | 2016 | status = chip->waitfunc(mtd, chip); |
1da177e4 | 2017 | |
ace4dfee TG |
2018 | /* |
2019 | * See if operation failed and additional status checks are | |
2020 | * available | |
2021 | */ | |
2022 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2023 | status = chip->errstat(mtd, chip, FL_ERASING, | |
2024 | status, page); | |
068e3c0a | 2025 | |
1da177e4 | 2026 | /* See if block erase succeeded */ |
a4ab4c5d | 2027 | if (status & NAND_STATUS_FAIL) { |
ace4dfee TG |
2028 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " |
2029 | "Failed erase, page 0x%08x\n", page); | |
1da177e4 | 2030 | instr->state = MTD_ERASE_FAILED; |
ace4dfee | 2031 | instr->fail_addr = (page << chip->page_shift); |
1da177e4 LT |
2032 | goto erase_exit; |
2033 | } | |
30f464b7 | 2034 | |
ace4dfee TG |
2035 | /* |
2036 | * If BBT requires refresh, set the BBT rewrite flag to the | |
2037 | * page being erased | |
2038 | */ | |
2039 | if (bbt_masked_page != 0xffffffff && | |
2040 | (page & BBT_PAGE_MASK) == bbt_masked_page) | |
2041 | rewrite_bbt[chipnr] = (page << chip->page_shift); | |
61b03bd7 | 2042 | |
1da177e4 | 2043 | /* Increment page address and decrement length */ |
ace4dfee | 2044 | len -= (1 << chip->phys_erase_shift); |
1da177e4 LT |
2045 | page += pages_per_block; |
2046 | ||
2047 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 2048 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 2049 | chipnr++; |
ace4dfee TG |
2050 | chip->select_chip(mtd, -1); |
2051 | chip->select_chip(mtd, chipnr); | |
30f464b7 | 2052 | |
ace4dfee TG |
2053 | /* |
2054 | * If BBT requires refresh and BBT-PERCHIP, set the BBT | |
2055 | * page mask to see if this BBT should be rewritten | |
2056 | */ | |
2057 | if (bbt_masked_page != 0xffffffff && | |
2058 | (chip->bbt_td->options & NAND_BBT_PERCHIP)) | |
2059 | bbt_masked_page = chip->bbt_td->pages[chipnr] & | |
2060 | BBT_PAGE_MASK; | |
1da177e4 LT |
2061 | } |
2062 | } | |
2063 | instr->state = MTD_ERASE_DONE; | |
2064 | ||
e0c7d767 | 2065 | erase_exit: |
1da177e4 LT |
2066 | |
2067 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
2068 | /* Do call back function */ | |
2069 | if (!ret) | |
2070 | mtd_erase_callback(instr); | |
2071 | ||
2072 | /* Deselect and wake up anyone waiting on the device */ | |
2073 | nand_release_device(mtd); | |
2074 | ||
ace4dfee TG |
2075 | /* |
2076 | * If BBT requires refresh and erase was successful, rewrite any | |
2077 | * selected bad block tables | |
2078 | */ | |
2079 | if (bbt_masked_page == 0xffffffff || ret) | |
2080 | return ret; | |
2081 | ||
2082 | for (chipnr = 0; chipnr < chip->numchips; chipnr++) { | |
2083 | if (!rewrite_bbt[chipnr]) | |
2084 | continue; | |
2085 | /* update the BBT for chip */ | |
2086 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt " | |
2087 | "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr], | |
2088 | chip->bbt_td->pages[chipnr]); | |
2089 | nand_update_bbt(mtd, rewrite_bbt[chipnr]); | |
30f464b7 DM |
2090 | } |
2091 | ||
1da177e4 LT |
2092 | /* Return more or less happy */ |
2093 | return ret; | |
2094 | } | |
2095 | ||
2096 | /** | |
2097 | * nand_sync - [MTD Interface] sync | |
2098 | * @mtd: MTD device structure | |
2099 | * | |
2100 | * Sync is actually a wait for chip ready function | |
2101 | */ | |
e0c7d767 | 2102 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 2103 | { |
ace4dfee | 2104 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2105 | |
e0c7d767 | 2106 | DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n"); |
1da177e4 LT |
2107 | |
2108 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 2109 | nand_get_device(chip, mtd, FL_SYNCING); |
1da177e4 | 2110 | /* Release it and go back */ |
e0c7d767 | 2111 | nand_release_device(mtd); |
1da177e4 LT |
2112 | } |
2113 | ||
1da177e4 | 2114 | /** |
ace4dfee | 2115 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
1da177e4 | 2116 | * @mtd: MTD device structure |
844d3b42 | 2117 | * @offs: offset relative to mtd start |
1da177e4 | 2118 | */ |
ace4dfee | 2119 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 LT |
2120 | { |
2121 | /* Check for invalid offset */ | |
ace4dfee | 2122 | if (offs > mtd->size) |
1da177e4 | 2123 | return -EINVAL; |
61b03bd7 | 2124 | |
ace4dfee | 2125 | return nand_block_checkbad(mtd, offs, 1, 0); |
1da177e4 LT |
2126 | } |
2127 | ||
2128 | /** | |
ace4dfee | 2129 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
1da177e4 LT |
2130 | * @mtd: MTD device structure |
2131 | * @ofs: offset relative to mtd start | |
2132 | */ | |
e0c7d767 | 2133 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 2134 | { |
ace4dfee | 2135 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
2136 | int ret; |
2137 | ||
e0c7d767 DW |
2138 | if ((ret = nand_block_isbad(mtd, ofs))) { |
2139 | /* If it was bad already, return success and do nothing. */ | |
1da177e4 LT |
2140 | if (ret > 0) |
2141 | return 0; | |
e0c7d767 DW |
2142 | return ret; |
2143 | } | |
1da177e4 | 2144 | |
ace4dfee | 2145 | return chip->block_markbad(mtd, ofs); |
1da177e4 LT |
2146 | } |
2147 | ||
962034f4 VW |
2148 | /** |
2149 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
2150 | * @mtd: MTD device structure | |
2151 | */ | |
2152 | static int nand_suspend(struct mtd_info *mtd) | |
2153 | { | |
ace4dfee | 2154 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2155 | |
ace4dfee | 2156 | return nand_get_device(chip, mtd, FL_PM_SUSPENDED); |
962034f4 VW |
2157 | } |
2158 | ||
2159 | /** | |
2160 | * nand_resume - [MTD Interface] Resume the NAND flash | |
2161 | * @mtd: MTD device structure | |
2162 | */ | |
2163 | static void nand_resume(struct mtd_info *mtd) | |
2164 | { | |
ace4dfee | 2165 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2166 | |
ace4dfee | 2167 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
2168 | nand_release_device(mtd); |
2169 | else | |
2c0a2bed TG |
2170 | printk(KERN_ERR "nand_resume() called for a chip which is not " |
2171 | "in suspended state\n"); | |
962034f4 VW |
2172 | } |
2173 | ||
7aa65bfd TG |
2174 | /* |
2175 | * Set default functions | |
2176 | */ | |
ace4dfee | 2177 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 2178 | { |
1da177e4 | 2179 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
2180 | if (!chip->chip_delay) |
2181 | chip->chip_delay = 20; | |
1da177e4 LT |
2182 | |
2183 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
2184 | if (chip->cmdfunc == NULL) |
2185 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
2186 | |
2187 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
2188 | if (chip->waitfunc == NULL) |
2189 | chip->waitfunc = nand_wait; | |
2190 | ||
2191 | if (!chip->select_chip) | |
2192 | chip->select_chip = nand_select_chip; | |
2193 | if (!chip->read_byte) | |
2194 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; | |
2195 | if (!chip->read_word) | |
2196 | chip->read_word = nand_read_word; | |
2197 | if (!chip->block_bad) | |
2198 | chip->block_bad = nand_block_bad; | |
2199 | if (!chip->block_markbad) | |
2200 | chip->block_markbad = nand_default_block_markbad; | |
2201 | if (!chip->write_buf) | |
2202 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; | |
2203 | if (!chip->read_buf) | |
2204 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; | |
2205 | if (!chip->verify_buf) | |
2206 | chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; | |
2207 | if (!chip->scan_bbt) | |
2208 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
2209 | |
2210 | if (!chip->controller) { | |
2211 | chip->controller = &chip->hwcontrol; | |
2212 | spin_lock_init(&chip->controller->lock); | |
2213 | init_waitqueue_head(&chip->controller->wq); | |
2214 | } | |
2215 | ||
7aa65bfd TG |
2216 | } |
2217 | ||
2218 | /* | |
ace4dfee | 2219 | * Get the flash and manufacturer id and lookup if the type is supported |
7aa65bfd TG |
2220 | */ |
2221 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 2222 | struct nand_chip *chip, |
7aa65bfd TG |
2223 | int busw, int *maf_id) |
2224 | { | |
2225 | struct nand_flash_dev *type = NULL; | |
2226 | int i, dev_id, maf_idx; | |
1da177e4 LT |
2227 | |
2228 | /* Select the device */ | |
ace4dfee | 2229 | chip->select_chip(mtd, 0); |
1da177e4 LT |
2230 | |
2231 | /* Send the command for reading device ID */ | |
ace4dfee | 2232 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
2233 | |
2234 | /* Read manufacturer and device IDs */ | |
ace4dfee TG |
2235 | *maf_id = chip->read_byte(mtd); |
2236 | dev_id = chip->read_byte(mtd); | |
1da177e4 | 2237 | |
7aa65bfd | 2238 | /* Lookup the flash id */ |
1da177e4 | 2239 | for (i = 0; nand_flash_ids[i].name != NULL; i++) { |
7aa65bfd TG |
2240 | if (dev_id == nand_flash_ids[i].id) { |
2241 | type = &nand_flash_ids[i]; | |
2242 | break; | |
2243 | } | |
2244 | } | |
61b03bd7 | 2245 | |
7aa65bfd TG |
2246 | if (!type) |
2247 | return ERR_PTR(-ENODEV); | |
2248 | ||
ba0251fe TG |
2249 | if (!mtd->name) |
2250 | mtd->name = type->name; | |
2251 | ||
2252 | chip->chipsize = type->chipsize << 20; | |
7aa65bfd TG |
2253 | |
2254 | /* Newer devices have all the information in additional id bytes */ | |
ba0251fe | 2255 | if (!type->pagesize) { |
7aa65bfd | 2256 | int extid; |
29072b96 TG |
2257 | /* The 3rd id byte holds MLC / multichip data */ |
2258 | chip->cellinfo = chip->read_byte(mtd); | |
7aa65bfd | 2259 | /* The 4th id byte is the important one */ |
ace4dfee | 2260 | extid = chip->read_byte(mtd); |
7aa65bfd | 2261 | /* Calc pagesize */ |
4cbb9b80 | 2262 | mtd->writesize = 1024 << (extid & 0x3); |
7aa65bfd TG |
2263 | extid >>= 2; |
2264 | /* Calc oobsize */ | |
4cbb9b80 | 2265 | mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9); |
7aa65bfd TG |
2266 | extid >>= 2; |
2267 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
2268 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
2269 | extid >>= 2; | |
2270 | /* Get buswidth information */ | |
2271 | busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
61b03bd7 | 2272 | |
7aa65bfd TG |
2273 | } else { |
2274 | /* | |
ace4dfee | 2275 | * Old devices have chip data hardcoded in the device id table |
7aa65bfd | 2276 | */ |
ba0251fe TG |
2277 | mtd->erasesize = type->erasesize; |
2278 | mtd->writesize = type->pagesize; | |
4cbb9b80 | 2279 | mtd->oobsize = mtd->writesize / 32; |
ba0251fe | 2280 | busw = type->options & NAND_BUSWIDTH_16; |
7aa65bfd | 2281 | } |
1da177e4 | 2282 | |
7aa65bfd | 2283 | /* Try to identify manufacturer */ |
9a909867 | 2284 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { |
7aa65bfd TG |
2285 | if (nand_manuf_ids[maf_idx].id == *maf_id) |
2286 | break; | |
2287 | } | |
0ea4a755 | 2288 | |
7aa65bfd TG |
2289 | /* |
2290 | * Check, if buswidth is correct. Hardware drivers should set | |
ace4dfee | 2291 | * chip correct ! |
7aa65bfd | 2292 | */ |
ace4dfee | 2293 | if (busw != (chip->options & NAND_BUSWIDTH_16)) { |
7aa65bfd TG |
2294 | printk(KERN_INFO "NAND device: Manufacturer ID:" |
2295 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, | |
2296 | dev_id, nand_manuf_ids[maf_idx].name, mtd->name); | |
2297 | printk(KERN_WARNING "NAND bus width %d instead %d bit\n", | |
ace4dfee | 2298 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
7aa65bfd TG |
2299 | busw ? 16 : 8); |
2300 | return ERR_PTR(-EINVAL); | |
2301 | } | |
61b03bd7 | 2302 | |
7aa65bfd | 2303 | /* Calculate the address shift from the page size */ |
ace4dfee | 2304 | chip->page_shift = ffs(mtd->writesize) - 1; |
7aa65bfd | 2305 | /* Convert chipsize to number of pages per chip -1. */ |
ace4dfee | 2306 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 2307 | |
ace4dfee | 2308 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 2309 | ffs(mtd->erasesize) - 1; |
ace4dfee | 2310 | chip->chip_shift = ffs(chip->chipsize) - 1; |
1da177e4 | 2311 | |
7aa65bfd | 2312 | /* Set the bad block position */ |
ace4dfee | 2313 | chip->badblockpos = mtd->writesize > 512 ? |
7aa65bfd | 2314 | NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS; |
61b03bd7 | 2315 | |
7aa65bfd | 2316 | /* Get chip options, preserve non chip based options */ |
ace4dfee | 2317 | chip->options &= ~NAND_CHIPOPTIONS_MSK; |
ba0251fe | 2318 | chip->options |= type->options & NAND_CHIPOPTIONS_MSK; |
7aa65bfd TG |
2319 | |
2320 | /* | |
ace4dfee | 2321 | * Set chip as a default. Board drivers can override it, if necessary |
7aa65bfd | 2322 | */ |
ace4dfee | 2323 | chip->options |= NAND_NO_AUTOINCR; |
7aa65bfd | 2324 | |
ace4dfee | 2325 | /* Check if chip is a not a samsung device. Do not clear the |
7aa65bfd TG |
2326 | * options for chips which are not having an extended id. |
2327 | */ | |
ba0251fe | 2328 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) |
ace4dfee | 2329 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; |
7aa65bfd TG |
2330 | |
2331 | /* Check for AND chips with 4 page planes */ | |
ace4dfee TG |
2332 | if (chip->options & NAND_4PAGE_ARRAY) |
2333 | chip->erase_cmd = multi_erase_cmd; | |
7aa65bfd | 2334 | else |
ace4dfee | 2335 | chip->erase_cmd = single_erase_cmd; |
7aa65bfd TG |
2336 | |
2337 | /* Do not replace user supplied command function ! */ | |
ace4dfee TG |
2338 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
2339 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd TG |
2340 | |
2341 | printk(KERN_INFO "NAND device: Manufacturer ID:" | |
2342 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id, | |
2343 | nand_manuf_ids[maf_idx].name, type->name); | |
2344 | ||
2345 | return type; | |
2346 | } | |
2347 | ||
7aa65bfd | 2348 | /** |
3b85c321 DW |
2349 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
2350 | * @mtd: MTD device structure | |
2351 | * @maxchips: Number of chips to scan for | |
7aa65bfd | 2352 | * |
3b85c321 DW |
2353 | * This is the first phase of the normal nand_scan() function. It |
2354 | * reads the flash ID and sets up MTD fields accordingly. | |
7aa65bfd | 2355 | * |
3b85c321 | 2356 | * The mtd->owner field must be set to the module of the caller. |
7aa65bfd | 2357 | */ |
3b85c321 | 2358 | int nand_scan_ident(struct mtd_info *mtd, int maxchips) |
7aa65bfd TG |
2359 | { |
2360 | int i, busw, nand_maf_id; | |
ace4dfee | 2361 | struct nand_chip *chip = mtd->priv; |
7aa65bfd TG |
2362 | struct nand_flash_dev *type; |
2363 | ||
7aa65bfd | 2364 | /* Get buswidth to select the correct functions */ |
ace4dfee | 2365 | busw = chip->options & NAND_BUSWIDTH_16; |
7aa65bfd | 2366 | /* Set the default functions */ |
ace4dfee | 2367 | nand_set_defaults(chip, busw); |
7aa65bfd TG |
2368 | |
2369 | /* Read the flash type */ | |
ace4dfee | 2370 | type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id); |
7aa65bfd TG |
2371 | |
2372 | if (IS_ERR(type)) { | |
e0c7d767 | 2373 | printk(KERN_WARNING "No NAND device found!!!\n"); |
ace4dfee | 2374 | chip->select_chip(mtd, -1); |
7aa65bfd | 2375 | return PTR_ERR(type); |
1da177e4 LT |
2376 | } |
2377 | ||
7aa65bfd | 2378 | /* Check for a chip array */ |
e0c7d767 | 2379 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 2380 | chip->select_chip(mtd, i); |
1da177e4 | 2381 | /* Send the command for reading device ID */ |
ace4dfee | 2382 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 2383 | /* Read manufacturer and device IDs */ |
ace4dfee TG |
2384 | if (nand_maf_id != chip->read_byte(mtd) || |
2385 | type->id != chip->read_byte(mtd)) | |
1da177e4 LT |
2386 | break; |
2387 | } | |
2388 | if (i > 1) | |
2389 | printk(KERN_INFO "%d NAND chips detected\n", i); | |
61b03bd7 | 2390 | |
1da177e4 | 2391 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
2392 | chip->numchips = i; |
2393 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 2394 | |
3b85c321 DW |
2395 | return 0; |
2396 | } | |
2397 | ||
2398 | ||
2399 | /** | |
2400 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
2401 | * @mtd: MTD device structure | |
2402 | * @maxchips: Number of chips to scan for | |
2403 | * | |
2404 | * This is the second phase of the normal nand_scan() function. It | |
2405 | * fills out all the uninitialized function pointers with the defaults | |
2406 | * and scans for a bad block table if appropriate. | |
2407 | */ | |
2408 | int nand_scan_tail(struct mtd_info *mtd) | |
2409 | { | |
2410 | int i; | |
2411 | struct nand_chip *chip = mtd->priv; | |
2412 | ||
4bf63fcb DW |
2413 | if (!(chip->options & NAND_OWN_BUFFERS)) |
2414 | chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); | |
2415 | if (!chip->buffers) | |
2416 | return -ENOMEM; | |
2417 | ||
7dcdcbef | 2418 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 2419 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 2420 | |
7aa65bfd TG |
2421 | /* |
2422 | * If no default placement scheme is given, select an appropriate one | |
2423 | */ | |
5bd34c09 | 2424 | if (!chip->ecc.layout) { |
61b03bd7 | 2425 | switch (mtd->oobsize) { |
1da177e4 | 2426 | case 8: |
5bd34c09 | 2427 | chip->ecc.layout = &nand_oob_8; |
1da177e4 LT |
2428 | break; |
2429 | case 16: | |
5bd34c09 | 2430 | chip->ecc.layout = &nand_oob_16; |
1da177e4 LT |
2431 | break; |
2432 | case 64: | |
5bd34c09 | 2433 | chip->ecc.layout = &nand_oob_64; |
1da177e4 LT |
2434 | break; |
2435 | default: | |
7aa65bfd TG |
2436 | printk(KERN_WARNING "No oob scheme defined for " |
2437 | "oobsize %d\n", mtd->oobsize); | |
1da177e4 LT |
2438 | BUG(); |
2439 | } | |
2440 | } | |
61b03bd7 | 2441 | |
956e944c DW |
2442 | if (!chip->write_page) |
2443 | chip->write_page = nand_write_page; | |
2444 | ||
61b03bd7 | 2445 | /* |
7aa65bfd TG |
2446 | * check ECC mode, default to software if 3byte/512byte hardware ECC is |
2447 | * selected and we have 256 byte pagesize fallback to software ECC | |
e0c7d767 | 2448 | */ |
956e944c DW |
2449 | if (!chip->ecc.read_page_raw) |
2450 | chip->ecc.read_page_raw = nand_read_page_raw; | |
2451 | if (!chip->ecc.write_page_raw) | |
2452 | chip->ecc.write_page_raw = nand_write_page_raw; | |
2453 | ||
ace4dfee | 2454 | switch (chip->ecc.mode) { |
6dfc6d25 | 2455 | case NAND_ECC_HW: |
f5bbdacc TG |
2456 | /* Use standard hwecc read page function ? */ |
2457 | if (!chip->ecc.read_page) | |
2458 | chip->ecc.read_page = nand_read_page_hwecc; | |
f75e5097 TG |
2459 | if (!chip->ecc.write_page) |
2460 | chip->ecc.write_page = nand_write_page_hwecc; | |
7bc3312b TG |
2461 | if (!chip->ecc.read_oob) |
2462 | chip->ecc.read_oob = nand_read_oob_std; | |
2463 | if (!chip->ecc.write_oob) | |
2464 | chip->ecc.write_oob = nand_write_oob_std; | |
f5bbdacc | 2465 | |
6dfc6d25 | 2466 | case NAND_ECC_HW_SYNDROME: |
ace4dfee TG |
2467 | if (!chip->ecc.calculate || !chip->ecc.correct || |
2468 | !chip->ecc.hwctl) { | |
6dfc6d25 TG |
2469 | printk(KERN_WARNING "No ECC functions supplied, " |
2470 | "Hardware ECC not possible\n"); | |
2471 | BUG(); | |
2472 | } | |
f75e5097 | 2473 | /* Use standard syndrome read/write page function ? */ |
f5bbdacc TG |
2474 | if (!chip->ecc.read_page) |
2475 | chip->ecc.read_page = nand_read_page_syndrome; | |
f75e5097 TG |
2476 | if (!chip->ecc.write_page) |
2477 | chip->ecc.write_page = nand_write_page_syndrome; | |
7bc3312b TG |
2478 | if (!chip->ecc.read_oob) |
2479 | chip->ecc.read_oob = nand_read_oob_syndrome; | |
2480 | if (!chip->ecc.write_oob) | |
2481 | chip->ecc.write_oob = nand_write_oob_syndrome; | |
f5bbdacc | 2482 | |
ace4dfee | 2483 | if (mtd->writesize >= chip->ecc.size) |
6dfc6d25 TG |
2484 | break; |
2485 | printk(KERN_WARNING "%d byte HW ECC not possible on " | |
2486 | "%d byte page size, fallback to SW ECC\n", | |
ace4dfee TG |
2487 | chip->ecc.size, mtd->writesize); |
2488 | chip->ecc.mode = NAND_ECC_SOFT; | |
61b03bd7 | 2489 | |
6dfc6d25 | 2490 | case NAND_ECC_SOFT: |
ace4dfee TG |
2491 | chip->ecc.calculate = nand_calculate_ecc; |
2492 | chip->ecc.correct = nand_correct_data; | |
f5bbdacc | 2493 | chip->ecc.read_page = nand_read_page_swecc; |
f75e5097 | 2494 | chip->ecc.write_page = nand_write_page_swecc; |
7bc3312b TG |
2495 | chip->ecc.read_oob = nand_read_oob_std; |
2496 | chip->ecc.write_oob = nand_write_oob_std; | |
ace4dfee TG |
2497 | chip->ecc.size = 256; |
2498 | chip->ecc.bytes = 3; | |
1da177e4 | 2499 | break; |
61b03bd7 TG |
2500 | |
2501 | case NAND_ECC_NONE: | |
7aa65bfd TG |
2502 | printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. " |
2503 | "This is not recommended !!\n"); | |
8593fbc6 TG |
2504 | chip->ecc.read_page = nand_read_page_raw; |
2505 | chip->ecc.write_page = nand_write_page_raw; | |
7bc3312b TG |
2506 | chip->ecc.read_oob = nand_read_oob_std; |
2507 | chip->ecc.write_oob = nand_write_oob_std; | |
ace4dfee TG |
2508 | chip->ecc.size = mtd->writesize; |
2509 | chip->ecc.bytes = 0; | |
1da177e4 | 2510 | break; |
956e944c | 2511 | |
1da177e4 | 2512 | default: |
7aa65bfd | 2513 | printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n", |
ace4dfee | 2514 | chip->ecc.mode); |
61b03bd7 | 2515 | BUG(); |
1da177e4 | 2516 | } |
61b03bd7 | 2517 | |
5bd34c09 TG |
2518 | /* |
2519 | * The number of bytes available for a client to place data into | |
2520 | * the out of band area | |
2521 | */ | |
2522 | chip->ecc.layout->oobavail = 0; | |
2523 | for (i = 0; chip->ecc.layout->oobfree[i].length; i++) | |
2524 | chip->ecc.layout->oobavail += | |
2525 | chip->ecc.layout->oobfree[i].length; | |
1f92267c | 2526 | mtd->oobavail = chip->ecc.layout->oobavail; |
5bd34c09 | 2527 | |
7aa65bfd TG |
2528 | /* |
2529 | * Set the number of read / write steps for one page depending on ECC | |
2530 | * mode | |
2531 | */ | |
ace4dfee TG |
2532 | chip->ecc.steps = mtd->writesize / chip->ecc.size; |
2533 | if(chip->ecc.steps * chip->ecc.size != mtd->writesize) { | |
6dfc6d25 TG |
2534 | printk(KERN_WARNING "Invalid ecc parameters\n"); |
2535 | BUG(); | |
1da177e4 | 2536 | } |
f5bbdacc | 2537 | chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; |
61b03bd7 | 2538 | |
29072b96 TG |
2539 | /* |
2540 | * Allow subpage writes up to ecc.steps. Not possible for MLC | |
2541 | * FLASH. | |
2542 | */ | |
2543 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && | |
2544 | !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { | |
2545 | switch(chip->ecc.steps) { | |
2546 | case 2: | |
2547 | mtd->subpage_sft = 1; | |
2548 | break; | |
2549 | case 4: | |
2550 | case 8: | |
2551 | mtd->subpage_sft = 2; | |
2552 | break; | |
2553 | } | |
2554 | } | |
2555 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
2556 | ||
04bbd0ea | 2557 | /* Initialize state */ |
ace4dfee | 2558 | chip->state = FL_READY; |
1da177e4 LT |
2559 | |
2560 | /* De-select the device */ | |
ace4dfee | 2561 | chip->select_chip(mtd, -1); |
1da177e4 LT |
2562 | |
2563 | /* Invalidate the pagebuffer reference */ | |
ace4dfee | 2564 | chip->pagebuf = -1; |
1da177e4 LT |
2565 | |
2566 | /* Fill in remaining MTD driver data */ | |
2567 | mtd->type = MTD_NANDFLASH; | |
5fa43394 | 2568 | mtd->flags = MTD_CAP_NANDFLASH; |
1da177e4 LT |
2569 | mtd->erase = nand_erase; |
2570 | mtd->point = NULL; | |
2571 | mtd->unpoint = NULL; | |
2572 | mtd->read = nand_read; | |
2573 | mtd->write = nand_write; | |
1da177e4 LT |
2574 | mtd->read_oob = nand_read_oob; |
2575 | mtd->write_oob = nand_write_oob; | |
1da177e4 LT |
2576 | mtd->sync = nand_sync; |
2577 | mtd->lock = NULL; | |
2578 | mtd->unlock = NULL; | |
962034f4 VW |
2579 | mtd->suspend = nand_suspend; |
2580 | mtd->resume = nand_resume; | |
1da177e4 LT |
2581 | mtd->block_isbad = nand_block_isbad; |
2582 | mtd->block_markbad = nand_block_markbad; | |
2583 | ||
5bd34c09 TG |
2584 | /* propagate ecc.layout to mtd_info */ |
2585 | mtd->ecclayout = chip->ecc.layout; | |
1da177e4 | 2586 | |
0040bf38 | 2587 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 2588 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 2589 | return 0; |
1da177e4 LT |
2590 | |
2591 | /* Build bad block table */ | |
ace4dfee | 2592 | return chip->scan_bbt(mtd); |
1da177e4 LT |
2593 | } |
2594 | ||
3b85c321 DW |
2595 | /* module_text_address() isn't exported, and it's mostly a pointless |
2596 | test if this is a module _anyway_ -- they'd have to try _really_ hard | |
2597 | to call us from in-kernel code if the core NAND support is modular. */ | |
2598 | #ifdef MODULE | |
2599 | #define caller_is_module() (1) | |
2600 | #else | |
2601 | #define caller_is_module() \ | |
2602 | module_text_address((unsigned long)__builtin_return_address(0)) | |
2603 | #endif | |
2604 | ||
2605 | /** | |
2606 | * nand_scan - [NAND Interface] Scan for the NAND device | |
2607 | * @mtd: MTD device structure | |
2608 | * @maxchips: Number of chips to scan for | |
2609 | * | |
2610 | * This fills out all the uninitialized function pointers | |
2611 | * with the defaults. | |
2612 | * The flash ID is read and the mtd/chip structures are | |
2613 | * filled with the appropriate values. | |
2614 | * The mtd->owner field must be set to the module of the caller | |
2615 | * | |
2616 | */ | |
2617 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
2618 | { | |
2619 | int ret; | |
2620 | ||
2621 | /* Many callers got this wrong, so check for it for a while... */ | |
2622 | if (!mtd->owner && caller_is_module()) { | |
2623 | printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n"); | |
2624 | BUG(); | |
2625 | } | |
2626 | ||
2627 | ret = nand_scan_ident(mtd, maxchips); | |
2628 | if (!ret) | |
2629 | ret = nand_scan_tail(mtd); | |
2630 | return ret; | |
2631 | } | |
2632 | ||
1da177e4 | 2633 | /** |
61b03bd7 | 2634 | * nand_release - [NAND Interface] Free resources held by the NAND device |
1da177e4 LT |
2635 | * @mtd: MTD device structure |
2636 | */ | |
e0c7d767 | 2637 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 2638 | { |
ace4dfee | 2639 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
2640 | |
2641 | #ifdef CONFIG_MTD_PARTITIONS | |
2642 | /* Deregister partitions */ | |
e0c7d767 | 2643 | del_mtd_partitions(mtd); |
1da177e4 LT |
2644 | #endif |
2645 | /* Deregister the device */ | |
e0c7d767 | 2646 | del_mtd_device(mtd); |
1da177e4 | 2647 | |
fa671646 | 2648 | /* Free bad block table memory */ |
ace4dfee | 2649 | kfree(chip->bbt); |
4bf63fcb DW |
2650 | if (!(chip->options & NAND_OWN_BUFFERS)) |
2651 | kfree(chip->buffers); | |
1da177e4 LT |
2652 | } |
2653 | ||
e0c7d767 | 2654 | EXPORT_SYMBOL_GPL(nand_scan); |
3b85c321 DW |
2655 | EXPORT_SYMBOL_GPL(nand_scan_ident); |
2656 | EXPORT_SYMBOL_GPL(nand_scan_tail); | |
e0c7d767 | 2657 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 RP |
2658 | |
2659 | static int __init nand_base_init(void) | |
2660 | { | |
2661 | led_trigger_register_simple("nand-disk", &nand_led_trigger); | |
2662 | return 0; | |
2663 | } | |
2664 | ||
2665 | static void __exit nand_base_exit(void) | |
2666 | { | |
2667 | led_trigger_unregister_simple(nand_led_trigger); | |
2668 | } | |
2669 | ||
2670 | module_init(nand_base_init); | |
2671 | module_exit(nand_base_exit); | |
2672 | ||
e0c7d767 DW |
2673 | MODULE_LICENSE("GPL"); |
2674 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>"); | |
2675 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |