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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Overview: |
3 | * This is the generic MTD driver for NAND flash devices. It should be | |
4 | * capable of working with almost all NAND chips currently available. | |
61b03bd7 | 5 | * |
1da177e4 | 6 | * Additional technical information is available on |
8b2b403c | 7 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 8 | * |
1da177e4 | 9 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 10 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 11 | * |
ace4dfee | 12 | * Credits: |
61b03bd7 TG |
13 | * David Woodhouse for adding multichip support |
14 | * | |
1da177e4 LT |
15 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
16 | * rework for 2K page size chips | |
17 | * | |
ace4dfee | 18 | * TODO: |
1da177e4 LT |
19 | * Enable cached programming for 2k page size chips |
20 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
7854d3f7 | 21 | * if we have HW ECC support. |
c0b8ba7b | 22 | * BBT table is not serialized, has to be fixed |
1da177e4 | 23 | * |
1da177e4 LT |
24 | * This program is free software; you can redistribute it and/or modify |
25 | * it under the terms of the GNU General Public License version 2 as | |
26 | * published by the Free Software Foundation. | |
27 | * | |
28 | */ | |
29 | ||
20171642 EG |
30 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
31 | ||
552d9205 | 32 | #include <linux/module.h> |
1da177e4 LT |
33 | #include <linux/delay.h> |
34 | #include <linux/errno.h> | |
7aa65bfd | 35 | #include <linux/err.h> |
1da177e4 LT |
36 | #include <linux/sched.h> |
37 | #include <linux/slab.h> | |
66507c7b | 38 | #include <linux/mm.h> |
38b8d208 | 39 | #include <linux/nmi.h> |
1da177e4 LT |
40 | #include <linux/types.h> |
41 | #include <linux/mtd/mtd.h> | |
42 | #include <linux/mtd/nand.h> | |
43 | #include <linux/mtd/nand_ecc.h> | |
193bd400 | 44 | #include <linux/mtd/nand_bch.h> |
1da177e4 LT |
45 | #include <linux/interrupt.h> |
46 | #include <linux/bitops.h> | |
7351d3a5 | 47 | #include <linux/io.h> |
1da177e4 | 48 | #include <linux/mtd/partitions.h> |
d48f62b9 | 49 | #include <linux/of.h> |
1da177e4 | 50 | |
41b207a7 BB |
51 | static int nand_get_device(struct mtd_info *mtd, int new_state); |
52 | ||
53 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, | |
54 | struct mtd_oob_ops *ops); | |
1da177e4 LT |
55 | |
56 | /* Define default oob placement schemes for large and small page devices */ | |
41b207a7 BB |
57 | static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section, |
58 | struct mtd_oob_region *oobregion) | |
59 | { | |
60 | struct nand_chip *chip = mtd_to_nand(mtd); | |
61 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
1da177e4 | 62 | |
41b207a7 BB |
63 | if (section > 1) |
64 | return -ERANGE; | |
1da177e4 | 65 | |
41b207a7 BB |
66 | if (!section) { |
67 | oobregion->offset = 0; | |
f7f8c175 MR |
68 | if (mtd->oobsize == 16) |
69 | oobregion->length = 4; | |
70 | else | |
71 | oobregion->length = 3; | |
41b207a7 | 72 | } else { |
f7f8c175 MR |
73 | if (mtd->oobsize == 8) |
74 | return -ERANGE; | |
75 | ||
41b207a7 BB |
76 | oobregion->offset = 6; |
77 | oobregion->length = ecc->total - 4; | |
78 | } | |
1da177e4 | 79 | |
41b207a7 BB |
80 | return 0; |
81 | } | |
82 | ||
83 | static int nand_ooblayout_free_sp(struct mtd_info *mtd, int section, | |
84 | struct mtd_oob_region *oobregion) | |
85 | { | |
86 | if (section > 1) | |
87 | return -ERANGE; | |
1da177e4 | 88 | |
41b207a7 BB |
89 | if (mtd->oobsize == 16) { |
90 | if (section) | |
91 | return -ERANGE; | |
92 | ||
93 | oobregion->length = 8; | |
94 | oobregion->offset = 8; | |
95 | } else { | |
96 | oobregion->length = 2; | |
97 | if (!section) | |
98 | oobregion->offset = 3; | |
99 | else | |
100 | oobregion->offset = 6; | |
101 | } | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
106 | const struct mtd_ooblayout_ops nand_ooblayout_sp_ops = { | |
107 | .ecc = nand_ooblayout_ecc_sp, | |
108 | .free = nand_ooblayout_free_sp, | |
81ec5364 | 109 | }; |
41b207a7 | 110 | EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops); |
81ec5364 | 111 | |
41b207a7 BB |
112 | static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section, |
113 | struct mtd_oob_region *oobregion) | |
114 | { | |
115 | struct nand_chip *chip = mtd_to_nand(mtd); | |
116 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
1da177e4 | 117 | |
41b207a7 BB |
118 | if (section) |
119 | return -ERANGE; | |
8593fbc6 | 120 | |
41b207a7 BB |
121 | oobregion->length = ecc->total; |
122 | oobregion->offset = mtd->oobsize - oobregion->length; | |
123 | ||
124 | return 0; | |
125 | } | |
126 | ||
127 | static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section, | |
128 | struct mtd_oob_region *oobregion) | |
129 | { | |
130 | struct nand_chip *chip = mtd_to_nand(mtd); | |
131 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
132 | ||
133 | if (section) | |
134 | return -ERANGE; | |
135 | ||
136 | oobregion->length = mtd->oobsize - ecc->total - 2; | |
137 | oobregion->offset = 2; | |
138 | ||
139 | return 0; | |
140 | } | |
141 | ||
142 | const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = { | |
143 | .ecc = nand_ooblayout_ecc_lp, | |
144 | .free = nand_ooblayout_free_lp, | |
145 | }; | |
146 | EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops); | |
d470a97c | 147 | |
6a623e07 AC |
148 | /* |
149 | * Support the old "large page" layout used for 1-bit Hamming ECC where ECC | |
150 | * are placed at a fixed offset. | |
151 | */ | |
152 | static int nand_ooblayout_ecc_lp_hamming(struct mtd_info *mtd, int section, | |
153 | struct mtd_oob_region *oobregion) | |
154 | { | |
155 | struct nand_chip *chip = mtd_to_nand(mtd); | |
156 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
157 | ||
158 | if (section) | |
159 | return -ERANGE; | |
160 | ||
161 | switch (mtd->oobsize) { | |
162 | case 64: | |
163 | oobregion->offset = 40; | |
164 | break; | |
165 | case 128: | |
166 | oobregion->offset = 80; | |
167 | break; | |
168 | default: | |
169 | return -EINVAL; | |
170 | } | |
171 | ||
172 | oobregion->length = ecc->total; | |
173 | if (oobregion->offset + oobregion->length > mtd->oobsize) | |
174 | return -ERANGE; | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
179 | static int nand_ooblayout_free_lp_hamming(struct mtd_info *mtd, int section, | |
180 | struct mtd_oob_region *oobregion) | |
181 | { | |
182 | struct nand_chip *chip = mtd_to_nand(mtd); | |
183 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
184 | int ecc_offset = 0; | |
185 | ||
186 | if (section < 0 || section > 1) | |
187 | return -ERANGE; | |
188 | ||
189 | switch (mtd->oobsize) { | |
190 | case 64: | |
191 | ecc_offset = 40; | |
192 | break; | |
193 | case 128: | |
194 | ecc_offset = 80; | |
195 | break; | |
196 | default: | |
197 | return -EINVAL; | |
198 | } | |
199 | ||
200 | if (section == 0) { | |
201 | oobregion->offset = 2; | |
202 | oobregion->length = ecc_offset - 2; | |
203 | } else { | |
204 | oobregion->offset = ecc_offset + ecc->total; | |
205 | oobregion->length = mtd->oobsize - oobregion->offset; | |
206 | } | |
207 | ||
208 | return 0; | |
209 | } | |
210 | ||
d4ed3b90 | 211 | static const struct mtd_ooblayout_ops nand_ooblayout_lp_hamming_ops = { |
6a623e07 AC |
212 | .ecc = nand_ooblayout_ecc_lp_hamming, |
213 | .free = nand_ooblayout_free_lp_hamming, | |
214 | }; | |
215 | ||
6fe5a6ac VS |
216 | static int check_offs_len(struct mtd_info *mtd, |
217 | loff_t ofs, uint64_t len) | |
218 | { | |
862eba51 | 219 | struct nand_chip *chip = mtd_to_nand(mtd); |
6fe5a6ac VS |
220 | int ret = 0; |
221 | ||
222 | /* Start address must align on block boundary */ | |
daae74ca | 223 | if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 224 | pr_debug("%s: unaligned address\n", __func__); |
6fe5a6ac VS |
225 | ret = -EINVAL; |
226 | } | |
227 | ||
228 | /* Length must align on block boundary */ | |
daae74ca | 229 | if (len & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 230 | pr_debug("%s: length not block aligned\n", __func__); |
6fe5a6ac VS |
231 | ret = -EINVAL; |
232 | } | |
233 | ||
6fe5a6ac VS |
234 | return ret; |
235 | } | |
236 | ||
1da177e4 LT |
237 | /** |
238 | * nand_release_device - [GENERIC] release chip | |
8b6e50c9 | 239 | * @mtd: MTD device structure |
61b03bd7 | 240 | * |
b0bb6903 | 241 | * Release chip lock and wake up anyone waiting on the device. |
1da177e4 | 242 | */ |
e0c7d767 | 243 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 244 | { |
862eba51 | 245 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 246 | |
a36ed299 | 247 | /* Release the controller and the chip */ |
ace4dfee TG |
248 | spin_lock(&chip->controller->lock); |
249 | chip->controller->active = NULL; | |
250 | chip->state = FL_READY; | |
251 | wake_up(&chip->controller->wq); | |
252 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
253 | } |
254 | ||
255 | /** | |
256 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
8b6e50c9 | 257 | * @mtd: MTD device structure |
1da177e4 | 258 | * |
7854d3f7 | 259 | * Default read function for 8bit buswidth |
1da177e4 | 260 | */ |
58dd8f2b | 261 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 262 | { |
862eba51 | 263 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee | 264 | return readb(chip->IO_ADDR_R); |
1da177e4 LT |
265 | } |
266 | ||
1da177e4 | 267 | /** |
7854d3f7 | 268 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
8b6e50c9 | 269 | * @mtd: MTD device structure |
1da177e4 | 270 | * |
7854d3f7 BN |
271 | * Default read function for 16bit buswidth with endianness conversion. |
272 | * | |
1da177e4 | 273 | */ |
58dd8f2b | 274 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 275 | { |
862eba51 | 276 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee | 277 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); |
1da177e4 LT |
278 | } |
279 | ||
1da177e4 LT |
280 | /** |
281 | * nand_read_word - [DEFAULT] read one word from the chip | |
8b6e50c9 | 282 | * @mtd: MTD device structure |
1da177e4 | 283 | * |
7854d3f7 | 284 | * Default read function for 16bit buswidth without endianness conversion. |
1da177e4 LT |
285 | */ |
286 | static u16 nand_read_word(struct mtd_info *mtd) | |
287 | { | |
862eba51 | 288 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee | 289 | return readw(chip->IO_ADDR_R); |
1da177e4 LT |
290 | } |
291 | ||
1da177e4 LT |
292 | /** |
293 | * nand_select_chip - [DEFAULT] control CE line | |
8b6e50c9 BN |
294 | * @mtd: MTD device structure |
295 | * @chipnr: chipnumber to select, -1 for deselect | |
1da177e4 LT |
296 | * |
297 | * Default select function for 1 chip devices. | |
298 | */ | |
ace4dfee | 299 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 300 | { |
862eba51 | 301 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee TG |
302 | |
303 | switch (chipnr) { | |
1da177e4 | 304 | case -1: |
ace4dfee | 305 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
306 | break; |
307 | case 0: | |
1da177e4 LT |
308 | break; |
309 | ||
310 | default: | |
311 | BUG(); | |
312 | } | |
313 | } | |
314 | ||
05f78359 UKK |
315 | /** |
316 | * nand_write_byte - [DEFAULT] write single byte to chip | |
317 | * @mtd: MTD device structure | |
318 | * @byte: value to write | |
319 | * | |
320 | * Default function to write a byte to I/O[7:0] | |
321 | */ | |
322 | static void nand_write_byte(struct mtd_info *mtd, uint8_t byte) | |
323 | { | |
862eba51 | 324 | struct nand_chip *chip = mtd_to_nand(mtd); |
05f78359 UKK |
325 | |
326 | chip->write_buf(mtd, &byte, 1); | |
327 | } | |
328 | ||
329 | /** | |
330 | * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16 | |
331 | * @mtd: MTD device structure | |
332 | * @byte: value to write | |
333 | * | |
334 | * Default function to write a byte to I/O[7:0] on a 16-bit wide chip. | |
335 | */ | |
336 | static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) | |
337 | { | |
862eba51 | 338 | struct nand_chip *chip = mtd_to_nand(mtd); |
05f78359 UKK |
339 | uint16_t word = byte; |
340 | ||
341 | /* | |
342 | * It's not entirely clear what should happen to I/O[15:8] when writing | |
343 | * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads: | |
344 | * | |
345 | * When the host supports a 16-bit bus width, only data is | |
346 | * transferred at the 16-bit width. All address and command line | |
347 | * transfers shall use only the lower 8-bits of the data bus. During | |
348 | * command transfers, the host may place any value on the upper | |
349 | * 8-bits of the data bus. During address transfers, the host shall | |
350 | * set the upper 8-bits of the data bus to 00h. | |
351 | * | |
352 | * One user of the write_byte callback is nand_onfi_set_features. The | |
353 | * four parameters are specified to be written to I/O[7:0], but this is | |
354 | * neither an address nor a command transfer. Let's assume a 0 on the | |
355 | * upper I/O lines is OK. | |
356 | */ | |
357 | chip->write_buf(mtd, (uint8_t *)&word, 2); | |
358 | } | |
359 | ||
1da177e4 LT |
360 | /** |
361 | * nand_write_buf - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
362 | * @mtd: MTD device structure |
363 | * @buf: data buffer | |
364 | * @len: number of bytes to write | |
1da177e4 | 365 | * |
7854d3f7 | 366 | * Default write function for 8bit buswidth. |
1da177e4 | 367 | */ |
58dd8f2b | 368 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 369 | { |
862eba51 | 370 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 371 | |
76413839 | 372 | iowrite8_rep(chip->IO_ADDR_W, buf, len); |
1da177e4 LT |
373 | } |
374 | ||
375 | /** | |
61b03bd7 | 376 | * nand_read_buf - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
377 | * @mtd: MTD device structure |
378 | * @buf: buffer to store date | |
379 | * @len: number of bytes to read | |
1da177e4 | 380 | * |
7854d3f7 | 381 | * Default read function for 8bit buswidth. |
1da177e4 | 382 | */ |
58dd8f2b | 383 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 384 | { |
862eba51 | 385 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 386 | |
76413839 | 387 | ioread8_rep(chip->IO_ADDR_R, buf, len); |
1da177e4 LT |
388 | } |
389 | ||
1da177e4 LT |
390 | /** |
391 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
392 | * @mtd: MTD device structure |
393 | * @buf: data buffer | |
394 | * @len: number of bytes to write | |
1da177e4 | 395 | * |
7854d3f7 | 396 | * Default write function for 16bit buswidth. |
1da177e4 | 397 | */ |
58dd8f2b | 398 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 399 | { |
862eba51 | 400 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 401 | u16 *p = (u16 *) buf; |
61b03bd7 | 402 | |
76413839 | 403 | iowrite16_rep(chip->IO_ADDR_W, p, len >> 1); |
1da177e4 LT |
404 | } |
405 | ||
406 | /** | |
61b03bd7 | 407 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
408 | * @mtd: MTD device structure |
409 | * @buf: buffer to store date | |
410 | * @len: number of bytes to read | |
1da177e4 | 411 | * |
7854d3f7 | 412 | * Default read function for 16bit buswidth. |
1da177e4 | 413 | */ |
58dd8f2b | 414 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 415 | { |
862eba51 | 416 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 417 | u16 *p = (u16 *) buf; |
1da177e4 | 418 | |
76413839 | 419 | ioread16_rep(chip->IO_ADDR_R, p, len >> 1); |
1da177e4 LT |
420 | } |
421 | ||
1da177e4 LT |
422 | /** |
423 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
8b6e50c9 BN |
424 | * @mtd: MTD device structure |
425 | * @ofs: offset from device start | |
1da177e4 | 426 | * |
61b03bd7 | 427 | * Check, if the block is bad. |
1da177e4 | 428 | */ |
9f3e0429 | 429 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 430 | { |
c120e75e | 431 | int page, page_end, res; |
862eba51 | 432 | struct nand_chip *chip = mtd_to_nand(mtd); |
c120e75e | 433 | u8 bad; |
1da177e4 | 434 | |
5fb1549d | 435 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
436 | ofs += mtd->erasesize - mtd->writesize; |
437 | ||
1a12f46a | 438 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
c120e75e | 439 | page_end = page + (chip->bbt_options & NAND_BBT_SCAN2NDPAGE ? 2 : 1); |
1a12f46a | 440 | |
c120e75e MY |
441 | for (; page < page_end; page++) { |
442 | res = chip->ecc.read_oob(mtd, chip, page); | |
443 | if (res) | |
444 | return res; | |
445 | ||
446 | bad = chip->oob_poi[chip->badblockpos]; | |
cdbec050 BN |
447 | |
448 | if (likely(chip->badblockbits == 8)) | |
449 | res = bad != 0xFF; | |
e0b58d0a | 450 | else |
cdbec050 | 451 | res = hweight8(bad) < chip->badblockbits; |
c120e75e MY |
452 | if (res) |
453 | return res; | |
454 | } | |
e0b58d0a | 455 | |
c120e75e | 456 | return 0; |
1da177e4 LT |
457 | } |
458 | ||
459 | /** | |
5a0edb25 | 460 | * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker |
8b6e50c9 BN |
461 | * @mtd: MTD device structure |
462 | * @ofs: offset from device start | |
1da177e4 | 463 | * |
8b6e50c9 | 464 | * This is the default implementation, which can be overridden by a hardware |
5a0edb25 BN |
465 | * specific driver. It provides the details for writing a bad block marker to a |
466 | * block. | |
467 | */ | |
468 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
469 | { | |
862eba51 | 470 | struct nand_chip *chip = mtd_to_nand(mtd); |
5a0edb25 BN |
471 | struct mtd_oob_ops ops; |
472 | uint8_t buf[2] = { 0, 0 }; | |
473 | int ret = 0, res, i = 0; | |
474 | ||
0ec56dc4 | 475 | memset(&ops, 0, sizeof(ops)); |
5a0edb25 BN |
476 | ops.oobbuf = buf; |
477 | ops.ooboffs = chip->badblockpos; | |
478 | if (chip->options & NAND_BUSWIDTH_16) { | |
479 | ops.ooboffs &= ~0x01; | |
480 | ops.len = ops.ooblen = 2; | |
481 | } else { | |
482 | ops.len = ops.ooblen = 1; | |
483 | } | |
484 | ops.mode = MTD_OPS_PLACE_OOB; | |
485 | ||
486 | /* Write to first/last page(s) if necessary */ | |
487 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) | |
488 | ofs += mtd->erasesize - mtd->writesize; | |
489 | do { | |
490 | res = nand_do_write_oob(mtd, ofs, &ops); | |
491 | if (!ret) | |
492 | ret = res; | |
493 | ||
494 | i++; | |
495 | ofs += mtd->writesize; | |
496 | } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); | |
497 | ||
498 | return ret; | |
499 | } | |
500 | ||
501 | /** | |
502 | * nand_block_markbad_lowlevel - mark a block bad | |
503 | * @mtd: MTD device structure | |
504 | * @ofs: offset from device start | |
505 | * | |
506 | * This function performs the generic NAND bad block marking steps (i.e., bad | |
507 | * block table(s) and/or marker(s)). We only allow the hardware driver to | |
508 | * specify how to write bad block markers to OOB (chip->block_markbad). | |
509 | * | |
b32843b7 | 510 | * We try operations in the following order: |
b6f6c294 | 511 | * |
e2414f4c | 512 | * (1) erase the affected block, to allow OOB marker to be written cleanly |
b32843b7 BN |
513 | * (2) write bad block marker to OOB area of affected block (unless flag |
514 | * NAND_BBT_NO_OOB_BBM is present) | |
515 | * (3) update the BBT | |
b6f6c294 | 516 | * |
b32843b7 | 517 | * Note that we retain the first error encountered in (2) or (3), finish the |
e2414f4c | 518 | * procedures, and dump the error in the end. |
1da177e4 | 519 | */ |
5a0edb25 | 520 | static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 521 | { |
862eba51 | 522 | struct nand_chip *chip = mtd_to_nand(mtd); |
b32843b7 | 523 | int res, ret = 0; |
61b03bd7 | 524 | |
b32843b7 | 525 | if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { |
00918429 BN |
526 | struct erase_info einfo; |
527 | ||
528 | /* Attempt erase before marking OOB */ | |
529 | memset(&einfo, 0, sizeof(einfo)); | |
530 | einfo.mtd = mtd; | |
531 | einfo.addr = ofs; | |
daae74ca | 532 | einfo.len = 1ULL << chip->phys_erase_shift; |
00918429 | 533 | nand_erase_nand(mtd, &einfo, 0); |
1da177e4 | 534 | |
b32843b7 | 535 | /* Write bad block marker to OOB */ |
6a8214aa | 536 | nand_get_device(mtd, FL_WRITING); |
5a0edb25 | 537 | ret = chip->block_markbad(mtd, ofs); |
c0b8ba7b | 538 | nand_release_device(mtd); |
f1a28c02 | 539 | } |
e2414f4c | 540 | |
b32843b7 BN |
541 | /* Mark block bad in BBT */ |
542 | if (chip->bbt) { | |
543 | res = nand_markbad_bbt(mtd, ofs); | |
e2414f4c BN |
544 | if (!ret) |
545 | ret = res; | |
546 | } | |
547 | ||
f1a28c02 TG |
548 | if (!ret) |
549 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 550 | |
f1a28c02 | 551 | return ret; |
1da177e4 LT |
552 | } |
553 | ||
61b03bd7 | 554 | /** |
1da177e4 | 555 | * nand_check_wp - [GENERIC] check if the chip is write protected |
8b6e50c9 | 556 | * @mtd: MTD device structure |
1da177e4 | 557 | * |
8b6e50c9 BN |
558 | * Check, if the device is write protected. The function expects, that the |
559 | * device is already selected. | |
1da177e4 | 560 | */ |
e0c7d767 | 561 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 562 | { |
862eba51 | 563 | struct nand_chip *chip = mtd_to_nand(mtd); |
93edbad6 | 564 | |
8b6e50c9 | 565 | /* Broken xD cards report WP despite being writable */ |
93edbad6 ML |
566 | if (chip->options & NAND_BROKEN_XD) |
567 | return 0; | |
568 | ||
1da177e4 | 569 | /* Check the WP bit */ |
ace4dfee TG |
570 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
571 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
572 | } |
573 | ||
8471bb73 | 574 | /** |
c30e1f79 | 575 | * nand_block_isreserved - [GENERIC] Check if a block is marked reserved. |
8471bb73 EG |
576 | * @mtd: MTD device structure |
577 | * @ofs: offset from device start | |
578 | * | |
c30e1f79 | 579 | * Check if the block is marked as reserved. |
8471bb73 EG |
580 | */ |
581 | static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) | |
582 | { | |
862eba51 | 583 | struct nand_chip *chip = mtd_to_nand(mtd); |
8471bb73 EG |
584 | |
585 | if (!chip->bbt) | |
586 | return 0; | |
587 | /* Return info from the table */ | |
588 | return nand_isreserved_bbt(mtd, ofs); | |
589 | } | |
590 | ||
1da177e4 LT |
591 | /** |
592 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
8b6e50c9 BN |
593 | * @mtd: MTD device structure |
594 | * @ofs: offset from device start | |
8b6e50c9 | 595 | * @allowbbt: 1, if its allowed to access the bbt area |
1da177e4 LT |
596 | * |
597 | * Check, if the block is bad. Either by reading the bad block table or | |
598 | * calling of the scan function. | |
599 | */ | |
9f3e0429 | 600 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt) |
1da177e4 | 601 | { |
862eba51 | 602 | struct nand_chip *chip = mtd_to_nand(mtd); |
61b03bd7 | 603 | |
ace4dfee | 604 | if (!chip->bbt) |
9f3e0429 | 605 | return chip->block_bad(mtd, ofs); |
61b03bd7 | 606 | |
1da177e4 | 607 | /* Return info from the table */ |
e0c7d767 | 608 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
609 | } |
610 | ||
2af7c653 SK |
611 | /** |
612 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
8b6e50c9 BN |
613 | * @mtd: MTD device structure |
614 | * @timeo: Timeout | |
2af7c653 SK |
615 | * |
616 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
617 | * context. | |
618 | */ | |
619 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
620 | { | |
862eba51 | 621 | struct nand_chip *chip = mtd_to_nand(mtd); |
2af7c653 SK |
622 | int i; |
623 | ||
624 | /* Wait for the device to get ready */ | |
625 | for (i = 0; i < timeo; i++) { | |
626 | if (chip->dev_ready(mtd)) | |
627 | break; | |
628 | touch_softlockup_watchdog(); | |
629 | mdelay(1); | |
630 | } | |
631 | } | |
632 | ||
b70af9be AS |
633 | /** |
634 | * nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
635 | * @mtd: MTD device structure | |
636 | * | |
637 | * Wait for the ready pin after a command, and warn if a timeout occurs. | |
638 | */ | |
4b648b02 | 639 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 640 | { |
862eba51 | 641 | struct nand_chip *chip = mtd_to_nand(mtd); |
b70af9be | 642 | unsigned long timeo = 400; |
3b88775c | 643 | |
2af7c653 | 644 | if (in_interrupt() || oops_in_progress) |
b70af9be | 645 | return panic_nand_wait_ready(mtd, timeo); |
2af7c653 | 646 | |
7854d3f7 | 647 | /* Wait until command is processed or timeout occurs */ |
b70af9be | 648 | timeo = jiffies + msecs_to_jiffies(timeo); |
3b88775c | 649 | do { |
ace4dfee | 650 | if (chip->dev_ready(mtd)) |
4c7e054f | 651 | return; |
b70af9be | 652 | cond_resched(); |
61b03bd7 | 653 | } while (time_before(jiffies, timeo)); |
b70af9be | 654 | |
9ebfdf5b BN |
655 | if (!chip->dev_ready(mtd)) |
656 | pr_warn_ratelimited("timeout while waiting for chip to become ready\n"); | |
3b88775c | 657 | } |
4b648b02 | 658 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 659 | |
60c70d66 RQ |
660 | /** |
661 | * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands. | |
662 | * @mtd: MTD device structure | |
663 | * @timeo: Timeout in ms | |
664 | * | |
665 | * Wait for status ready (i.e. command done) or timeout. | |
666 | */ | |
667 | static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo) | |
668 | { | |
862eba51 | 669 | register struct nand_chip *chip = mtd_to_nand(mtd); |
60c70d66 RQ |
670 | |
671 | timeo = jiffies + msecs_to_jiffies(timeo); | |
672 | do { | |
673 | if ((chip->read_byte(mtd) & NAND_STATUS_READY)) | |
674 | break; | |
675 | touch_softlockup_watchdog(); | |
676 | } while (time_before(jiffies, timeo)); | |
677 | }; | |
678 | ||
1da177e4 LT |
679 | /** |
680 | * nand_command - [DEFAULT] Send command to NAND device | |
8b6e50c9 BN |
681 | * @mtd: MTD device structure |
682 | * @command: the command to be sent | |
683 | * @column: the column address for this command, -1 if none | |
684 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 685 | * |
8b6e50c9 | 686 | * Send command to NAND device. This function is used for small page devices |
51148f1f | 687 | * (512 Bytes per page). |
1da177e4 | 688 | */ |
7abd3ef9 TG |
689 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
690 | int column, int page_addr) | |
1da177e4 | 691 | { |
862eba51 | 692 | register struct nand_chip *chip = mtd_to_nand(mtd); |
7abd3ef9 | 693 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 694 | |
8b6e50c9 | 695 | /* Write out the command to the device */ |
1da177e4 LT |
696 | if (command == NAND_CMD_SEQIN) { |
697 | int readcmd; | |
698 | ||
28318776 | 699 | if (column >= mtd->writesize) { |
1da177e4 | 700 | /* OOB area */ |
28318776 | 701 | column -= mtd->writesize; |
1da177e4 LT |
702 | readcmd = NAND_CMD_READOOB; |
703 | } else if (column < 256) { | |
704 | /* First 256 bytes --> READ0 */ | |
705 | readcmd = NAND_CMD_READ0; | |
706 | } else { | |
707 | column -= 256; | |
708 | readcmd = NAND_CMD_READ1; | |
709 | } | |
ace4dfee | 710 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 711 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 712 | } |
ace4dfee | 713 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 714 | |
8b6e50c9 | 715 | /* Address cycle, when necessary */ |
7abd3ef9 TG |
716 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; |
717 | /* Serially input address */ | |
718 | if (column != -1) { | |
719 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
720 | if (chip->options & NAND_BUSWIDTH_16 && |
721 | !nand_opcode_8bits(command)) | |
7abd3ef9 | 722 | column >>= 1; |
ace4dfee | 723 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
724 | ctrl &= ~NAND_CTRL_CHANGE; |
725 | } | |
726 | if (page_addr != -1) { | |
ace4dfee | 727 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 728 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 729 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 730 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
731 | if (chip->chipsize > (32 << 20)) |
732 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 733 | } |
ace4dfee | 734 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
735 | |
736 | /* | |
8b6e50c9 BN |
737 | * Program and erase have their own busy handlers status and sequential |
738 | * in needs no delay | |
e0c7d767 | 739 | */ |
1da177e4 | 740 | switch (command) { |
61b03bd7 | 741 | |
1da177e4 LT |
742 | case NAND_CMD_PAGEPROG: |
743 | case NAND_CMD_ERASE1: | |
744 | case NAND_CMD_ERASE2: | |
745 | case NAND_CMD_SEQIN: | |
746 | case NAND_CMD_STATUS: | |
3158fa0e | 747 | case NAND_CMD_READID: |
c5d664aa | 748 | case NAND_CMD_SET_FEATURES: |
1da177e4 LT |
749 | return; |
750 | ||
751 | case NAND_CMD_RESET: | |
ace4dfee | 752 | if (chip->dev_ready) |
1da177e4 | 753 | break; |
ace4dfee TG |
754 | udelay(chip->chip_delay); |
755 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 756 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
757 | chip->cmd_ctrl(mtd, |
758 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
60c70d66 RQ |
759 | /* EZ-NAND can take upto 250ms as per ONFi v4.0 */ |
760 | nand_wait_status_ready(mtd, 250); | |
1da177e4 LT |
761 | return; |
762 | ||
e0c7d767 | 763 | /* This applies to read commands */ |
2165c4a1 BB |
764 | case NAND_CMD_READ0: |
765 | /* | |
766 | * READ0 is sometimes used to exit GET STATUS mode. When this | |
767 | * is the case no address cycles are requested, and we can use | |
768 | * this information to detect that we should not wait for the | |
769 | * device to be ready. | |
770 | */ | |
771 | if (column == -1 && page_addr == -1) | |
772 | return; | |
773 | ||
1da177e4 | 774 | default: |
61b03bd7 | 775 | /* |
1da177e4 LT |
776 | * If we don't have access to the busy pin, we apply the given |
777 | * command delay | |
e0c7d767 | 778 | */ |
ace4dfee TG |
779 | if (!chip->dev_ready) { |
780 | udelay(chip->chip_delay); | |
1da177e4 | 781 | return; |
61b03bd7 | 782 | } |
1da177e4 | 783 | } |
8b6e50c9 BN |
784 | /* |
785 | * Apply this short delay always to ensure that we do wait tWB in | |
786 | * any case on any machine. | |
787 | */ | |
e0c7d767 | 788 | ndelay(100); |
3b88775c TG |
789 | |
790 | nand_wait_ready(mtd); | |
1da177e4 LT |
791 | } |
792 | ||
6ea40a3b BB |
793 | static void nand_ccs_delay(struct nand_chip *chip) |
794 | { | |
795 | /* | |
796 | * The controller already takes care of waiting for tCCS when the RNDIN | |
797 | * or RNDOUT command is sent, return directly. | |
798 | */ | |
799 | if (!(chip->options & NAND_WAIT_TCCS)) | |
800 | return; | |
801 | ||
802 | /* | |
803 | * Wait tCCS_min if it is correctly defined, otherwise wait 500ns | |
804 | * (which should be safe for all NANDs). | |
805 | */ | |
806 | if (chip->data_interface && chip->data_interface->timings.sdr.tCCS_min) | |
807 | ndelay(chip->data_interface->timings.sdr.tCCS_min / 1000); | |
808 | else | |
809 | ndelay(500); | |
810 | } | |
811 | ||
1da177e4 LT |
812 | /** |
813 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
8b6e50c9 BN |
814 | * @mtd: MTD device structure |
815 | * @command: the command to be sent | |
816 | * @column: the column address for this command, -1 if none | |
817 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 818 | * |
7abd3ef9 | 819 | * Send command to NAND device. This is the version for the new large page |
7854d3f7 BN |
820 | * devices. We don't have the separate regions as we have in the small page |
821 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 822 | */ |
7abd3ef9 TG |
823 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
824 | int column, int page_addr) | |
1da177e4 | 825 | { |
862eba51 | 826 | register struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 LT |
827 | |
828 | /* Emulate NAND_CMD_READOOB */ | |
829 | if (command == NAND_CMD_READOOB) { | |
28318776 | 830 | column += mtd->writesize; |
1da177e4 LT |
831 | command = NAND_CMD_READ0; |
832 | } | |
61b03bd7 | 833 | |
7abd3ef9 | 834 | /* Command latch cycle */ |
fb066ada | 835 | chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
836 | |
837 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 838 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
839 | |
840 | /* Serially input address */ | |
841 | if (column != -1) { | |
842 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
843 | if (chip->options & NAND_BUSWIDTH_16 && |
844 | !nand_opcode_8bits(command)) | |
1da177e4 | 845 | column >>= 1; |
ace4dfee | 846 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 847 | ctrl &= ~NAND_CTRL_CHANGE; |
fde85cfd | 848 | |
f5b88de2 | 849 | /* Only output a single addr cycle for 8bits opcodes. */ |
fde85cfd BB |
850 | if (!nand_opcode_8bits(command)) |
851 | chip->cmd_ctrl(mtd, column >> 8, ctrl); | |
61b03bd7 | 852 | } |
1da177e4 | 853 | if (page_addr != -1) { |
ace4dfee TG |
854 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
855 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 856 | NAND_NCE | NAND_ALE); |
1da177e4 | 857 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
858 | if (chip->chipsize > (128 << 20)) |
859 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 860 | NAND_NCE | NAND_ALE); |
1da177e4 | 861 | } |
1da177e4 | 862 | } |
ace4dfee | 863 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
864 | |
865 | /* | |
8b6e50c9 | 866 | * Program and erase have their own busy handlers status, sequential |
7a442f17 | 867 | * in and status need no delay. |
30f464b7 | 868 | */ |
1da177e4 | 869 | switch (command) { |
61b03bd7 | 870 | |
1da177e4 LT |
871 | case NAND_CMD_CACHEDPROG: |
872 | case NAND_CMD_PAGEPROG: | |
873 | case NAND_CMD_ERASE1: | |
874 | case NAND_CMD_ERASE2: | |
875 | case NAND_CMD_SEQIN: | |
876 | case NAND_CMD_STATUS: | |
3158fa0e | 877 | case NAND_CMD_READID: |
c5d664aa | 878 | case NAND_CMD_SET_FEATURES: |
30f464b7 | 879 | return; |
1da177e4 | 880 | |
6ea40a3b BB |
881 | case NAND_CMD_RNDIN: |
882 | nand_ccs_delay(chip); | |
883 | return; | |
884 | ||
1da177e4 | 885 | case NAND_CMD_RESET: |
ace4dfee | 886 | if (chip->dev_ready) |
1da177e4 | 887 | break; |
ace4dfee | 888 | udelay(chip->chip_delay); |
12efdde3 TG |
889 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
890 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
891 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
892 | NAND_NCE | NAND_CTRL_CHANGE); | |
60c70d66 RQ |
893 | /* EZ-NAND can take upto 250ms as per ONFi v4.0 */ |
894 | nand_wait_status_ready(mtd, 250); | |
1da177e4 LT |
895 | return; |
896 | ||
7bc3312b TG |
897 | case NAND_CMD_RNDOUT: |
898 | /* No ready / busy check necessary */ | |
899 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
900 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
901 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
902 | NAND_NCE | NAND_CTRL_CHANGE); | |
6ea40a3b BB |
903 | |
904 | nand_ccs_delay(chip); | |
7bc3312b TG |
905 | return; |
906 | ||
1da177e4 | 907 | case NAND_CMD_READ0: |
2165c4a1 BB |
908 | /* |
909 | * READ0 is sometimes used to exit GET STATUS mode. When this | |
910 | * is the case no address cycles are requested, and we can use | |
911 | * this information to detect that READSTART should not be | |
912 | * issued. | |
913 | */ | |
914 | if (column == -1 && page_addr == -1) | |
915 | return; | |
916 | ||
12efdde3 TG |
917 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
918 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
919 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
920 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 921 | |
e0c7d767 | 922 | /* This applies to read commands */ |
1da177e4 | 923 | default: |
61b03bd7 | 924 | /* |
1da177e4 | 925 | * If we don't have access to the busy pin, we apply the given |
8b6e50c9 | 926 | * command delay. |
e0c7d767 | 927 | */ |
ace4dfee TG |
928 | if (!chip->dev_ready) { |
929 | udelay(chip->chip_delay); | |
1da177e4 | 930 | return; |
61b03bd7 | 931 | } |
1da177e4 | 932 | } |
3b88775c | 933 | |
8b6e50c9 BN |
934 | /* |
935 | * Apply this short delay always to ensure that we do wait tWB in | |
936 | * any case on any machine. | |
937 | */ | |
e0c7d767 | 938 | ndelay(100); |
3b88775c TG |
939 | |
940 | nand_wait_ready(mtd); | |
1da177e4 LT |
941 | } |
942 | ||
2af7c653 SK |
943 | /** |
944 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
945 | * @chip: the nand chip descriptor |
946 | * @mtd: MTD device structure | |
947 | * @new_state: the state which is requested | |
2af7c653 SK |
948 | * |
949 | * Used when in panic, no locks are taken. | |
950 | */ | |
951 | static void panic_nand_get_device(struct nand_chip *chip, | |
952 | struct mtd_info *mtd, int new_state) | |
953 | { | |
7854d3f7 | 954 | /* Hardware controller shared among independent devices */ |
2af7c653 SK |
955 | chip->controller->active = chip; |
956 | chip->state = new_state; | |
957 | } | |
958 | ||
1da177e4 LT |
959 | /** |
960 | * nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
961 | * @mtd: MTD device structure |
962 | * @new_state: the state which is requested | |
1da177e4 LT |
963 | * |
964 | * Get the device and lock it for exclusive access | |
965 | */ | |
2c0a2bed | 966 | static int |
6a8214aa | 967 | nand_get_device(struct mtd_info *mtd, int new_state) |
1da177e4 | 968 | { |
862eba51 | 969 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee TG |
970 | spinlock_t *lock = &chip->controller->lock; |
971 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 972 | DECLARE_WAITQUEUE(wait, current); |
7351d3a5 | 973 | retry: |
0dfc6246 TG |
974 | spin_lock(lock); |
975 | ||
b8b3ee9a | 976 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
977 | if (!chip->controller->active) |
978 | chip->controller->active = chip; | |
a36ed299 | 979 | |
ace4dfee TG |
980 | if (chip->controller->active == chip && chip->state == FL_READY) { |
981 | chip->state = new_state; | |
0dfc6246 | 982 | spin_unlock(lock); |
962034f4 VW |
983 | return 0; |
984 | } | |
985 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
986 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
987 | chip->state = FL_PM_SUSPENDED; | |
988 | spin_unlock(lock); | |
989 | return 0; | |
6b0d9a84 | 990 | } |
0dfc6246 TG |
991 | } |
992 | set_current_state(TASK_UNINTERRUPTIBLE); | |
993 | add_wait_queue(wq, &wait); | |
994 | spin_unlock(lock); | |
995 | schedule(); | |
996 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
997 | goto retry; |
998 | } | |
999 | ||
2af7c653 | 1000 | /** |
8b6e50c9 BN |
1001 | * panic_nand_wait - [GENERIC] wait until the command is done |
1002 | * @mtd: MTD device structure | |
1003 | * @chip: NAND chip structure | |
1004 | * @timeo: timeout | |
2af7c653 SK |
1005 | * |
1006 | * Wait for command done. This is a helper function for nand_wait used when | |
1007 | * we are in interrupt context. May happen when in panic and trying to write | |
b595076a | 1008 | * an oops through mtdoops. |
2af7c653 SK |
1009 | */ |
1010 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
1011 | unsigned long timeo) | |
1012 | { | |
1013 | int i; | |
1014 | for (i = 0; i < timeo; i++) { | |
1015 | if (chip->dev_ready) { | |
1016 | if (chip->dev_ready(mtd)) | |
1017 | break; | |
1018 | } else { | |
1019 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
1020 | break; | |
1021 | } | |
1022 | mdelay(1); | |
f8ac0414 | 1023 | } |
2af7c653 SK |
1024 | } |
1025 | ||
1da177e4 | 1026 | /** |
8b6e50c9 BN |
1027 | * nand_wait - [DEFAULT] wait until the command is done |
1028 | * @mtd: MTD device structure | |
1029 | * @chip: NAND chip structure | |
1da177e4 | 1030 | * |
b70af9be | 1031 | * Wait for command done. This applies to erase and program only. |
844d3b42 | 1032 | */ |
7bc3312b | 1033 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
1034 | { |
1035 | ||
b70af9be AS |
1036 | int status; |
1037 | unsigned long timeo = 400; | |
1da177e4 | 1038 | |
8b6e50c9 BN |
1039 | /* |
1040 | * Apply this short delay always to ensure that we do wait tWB in any | |
1041 | * case on any machine. | |
1042 | */ | |
e0c7d767 | 1043 | ndelay(100); |
1da177e4 | 1044 | |
14c65786 | 1045 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 1046 | |
2af7c653 SK |
1047 | if (in_interrupt() || oops_in_progress) |
1048 | panic_nand_wait(mtd, chip, timeo); | |
1049 | else { | |
6d2559f8 | 1050 | timeo = jiffies + msecs_to_jiffies(timeo); |
b70af9be | 1051 | do { |
2af7c653 SK |
1052 | if (chip->dev_ready) { |
1053 | if (chip->dev_ready(mtd)) | |
1054 | break; | |
1055 | } else { | |
1056 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
1057 | break; | |
1058 | } | |
1059 | cond_resched(); | |
b70af9be | 1060 | } while (time_before(jiffies, timeo)); |
1da177e4 | 1061 | } |
8fe833c1 | 1062 | |
ace4dfee | 1063 | status = (int)chip->read_byte(mtd); |
f251b8df MC |
1064 | /* This can happen if in case of timeout or buggy dev_ready */ |
1065 | WARN_ON(!(status & NAND_STATUS_READY)); | |
1da177e4 LT |
1066 | return status; |
1067 | } | |
1068 | ||
d8e725dd BB |
1069 | /** |
1070 | * nand_reset_data_interface - Reset data interface and timings | |
1071 | * @chip: The NAND chip | |
104e442a | 1072 | * @chipnr: Internal die id |
d8e725dd BB |
1073 | * |
1074 | * Reset the Data interface and timings to ONFI mode 0. | |
1075 | * | |
1076 | * Returns 0 for success or negative error code otherwise. | |
1077 | */ | |
104e442a | 1078 | static int nand_reset_data_interface(struct nand_chip *chip, int chipnr) |
d8e725dd BB |
1079 | { |
1080 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1081 | const struct nand_data_interface *conf; | |
1082 | int ret; | |
1083 | ||
1084 | if (!chip->setup_data_interface) | |
1085 | return 0; | |
1086 | ||
1087 | /* | |
1088 | * The ONFI specification says: | |
1089 | * " | |
1090 | * To transition from NV-DDR or NV-DDR2 to the SDR data | |
1091 | * interface, the host shall use the Reset (FFh) command | |
1092 | * using SDR timing mode 0. A device in any timing mode is | |
1093 | * required to recognize Reset (FFh) command issued in SDR | |
1094 | * timing mode 0. | |
1095 | * " | |
1096 | * | |
1097 | * Configure the data interface in SDR mode and set the | |
1098 | * timings to timing mode 0. | |
1099 | */ | |
1100 | ||
1101 | conf = nand_get_default_data_interface(); | |
104e442a | 1102 | ret = chip->setup_data_interface(mtd, chipnr, conf); |
d8e725dd BB |
1103 | if (ret) |
1104 | pr_err("Failed to configure data interface to SDR timing mode 0\n"); | |
1105 | ||
1106 | return ret; | |
1107 | } | |
1108 | ||
1109 | /** | |
1110 | * nand_setup_data_interface - Setup the best data interface and timings | |
1111 | * @chip: The NAND chip | |
104e442a | 1112 | * @chipnr: Internal die id |
d8e725dd BB |
1113 | * |
1114 | * Find and configure the best data interface and NAND timings supported by | |
1115 | * the chip and the driver. | |
1116 | * First tries to retrieve supported timing modes from ONFI information, | |
1117 | * and if the NAND chip does not support ONFI, relies on the | |
1118 | * ->onfi_timing_mode_default specified in the nand_ids table. | |
1119 | * | |
1120 | * Returns 0 for success or negative error code otherwise. | |
1121 | */ | |
104e442a | 1122 | static int nand_setup_data_interface(struct nand_chip *chip, int chipnr) |
d8e725dd BB |
1123 | { |
1124 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1125 | int ret; | |
1126 | ||
1127 | if (!chip->setup_data_interface || !chip->data_interface) | |
1128 | return 0; | |
1129 | ||
1130 | /* | |
1131 | * Ensure the timing mode has been changed on the chip side | |
1132 | * before changing timings on the controller side. | |
1133 | */ | |
a11bf5ed BB |
1134 | if (chip->onfi_version && |
1135 | (le16_to_cpu(chip->onfi_params.opt_cmd) & | |
1136 | ONFI_OPT_CMD_SET_GET_FEATURES)) { | |
d8e725dd BB |
1137 | u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { |
1138 | chip->onfi_timing_mode_default, | |
1139 | }; | |
1140 | ||
1141 | ret = chip->onfi_set_features(mtd, chip, | |
1142 | ONFI_FEATURE_ADDR_TIMING_MODE, | |
1143 | tmode_param); | |
1144 | if (ret) | |
1145 | goto err; | |
1146 | } | |
1147 | ||
104e442a | 1148 | ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface); |
d8e725dd BB |
1149 | err: |
1150 | return ret; | |
1151 | } | |
1152 | ||
1153 | /** | |
1154 | * nand_init_data_interface - find the best data interface and timings | |
1155 | * @chip: The NAND chip | |
1156 | * | |
1157 | * Find the best data interface and NAND timings supported by the chip | |
1158 | * and the driver. | |
1159 | * First tries to retrieve supported timing modes from ONFI information, | |
1160 | * and if the NAND chip does not support ONFI, relies on the | |
1161 | * ->onfi_timing_mode_default specified in the nand_ids table. After this | |
1162 | * function nand_chip->data_interface is initialized with the best timing mode | |
1163 | * available. | |
1164 | * | |
1165 | * Returns 0 for success or negative error code otherwise. | |
1166 | */ | |
1167 | static int nand_init_data_interface(struct nand_chip *chip) | |
1168 | { | |
1169 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1170 | int modes, mode, ret; | |
1171 | ||
1172 | if (!chip->setup_data_interface) | |
1173 | return 0; | |
1174 | ||
1175 | /* | |
1176 | * First try to identify the best timings from ONFI parameters and | |
1177 | * if the NAND does not support ONFI, fallback to the default ONFI | |
1178 | * timing mode. | |
1179 | */ | |
1180 | modes = onfi_get_async_timing_mode(chip); | |
1181 | if (modes == ONFI_TIMING_MODE_UNKNOWN) { | |
1182 | if (!chip->onfi_timing_mode_default) | |
1183 | return 0; | |
1184 | ||
1185 | modes = GENMASK(chip->onfi_timing_mode_default, 0); | |
1186 | } | |
1187 | ||
1188 | chip->data_interface = kzalloc(sizeof(*chip->data_interface), | |
1189 | GFP_KERNEL); | |
1190 | if (!chip->data_interface) | |
1191 | return -ENOMEM; | |
1192 | ||
1193 | for (mode = fls(modes) - 1; mode >= 0; mode--) { | |
1194 | ret = onfi_init_data_interface(chip, chip->data_interface, | |
1195 | NAND_SDR_IFACE, mode); | |
1196 | if (ret) | |
1197 | continue; | |
1198 | ||
104e442a BB |
1199 | /* Pass -1 to only */ |
1200 | ret = chip->setup_data_interface(mtd, | |
1201 | NAND_DATA_IFACE_CHECK_ONLY, | |
1202 | chip->data_interface); | |
d8e725dd BB |
1203 | if (!ret) { |
1204 | chip->onfi_timing_mode_default = mode; | |
1205 | break; | |
1206 | } | |
1207 | } | |
1208 | ||
1209 | return 0; | |
1210 | } | |
1211 | ||
1212 | static void nand_release_data_interface(struct nand_chip *chip) | |
1213 | { | |
1214 | kfree(chip->data_interface); | |
1215 | } | |
1216 | ||
2f94abfe SH |
1217 | /** |
1218 | * nand_reset - Reset and initialize a NAND device | |
1219 | * @chip: The NAND chip | |
73f907fd | 1220 | * @chipnr: Internal die id |
2f94abfe SH |
1221 | * |
1222 | * Returns 0 for success or negative error code otherwise | |
1223 | */ | |
73f907fd | 1224 | int nand_reset(struct nand_chip *chip, int chipnr) |
2f94abfe SH |
1225 | { |
1226 | struct mtd_info *mtd = nand_to_mtd(chip); | |
d8e725dd BB |
1227 | int ret; |
1228 | ||
104e442a | 1229 | ret = nand_reset_data_interface(chip, chipnr); |
d8e725dd BB |
1230 | if (ret) |
1231 | return ret; | |
2f94abfe | 1232 | |
73f907fd BB |
1233 | /* |
1234 | * The CS line has to be released before we can apply the new NAND | |
1235 | * interface settings, hence this weird ->select_chip() dance. | |
1236 | */ | |
1237 | chip->select_chip(mtd, chipnr); | |
2f94abfe | 1238 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
73f907fd | 1239 | chip->select_chip(mtd, -1); |
2f94abfe | 1240 | |
73f907fd | 1241 | chip->select_chip(mtd, chipnr); |
104e442a | 1242 | ret = nand_setup_data_interface(chip, chipnr); |
73f907fd | 1243 | chip->select_chip(mtd, -1); |
d8e725dd BB |
1244 | if (ret) |
1245 | return ret; | |
1246 | ||
2f94abfe SH |
1247 | return 0; |
1248 | } | |
1249 | ||
7d70f334 | 1250 | /** |
b6d676db | 1251 | * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
1252 | * @mtd: mtd info |
1253 | * @ofs: offset to start unlock from | |
1254 | * @len: length to unlock | |
b6f6c294 MCC |
1255 | * @invert: |
1256 | * - when = 0, unlock the range of blocks within the lower and | |
8b6e50c9 | 1257 | * upper boundary address |
b6f6c294 | 1258 | * - when = 1, unlock the range of blocks outside the boundaries |
8b6e50c9 | 1259 | * of the lower and upper boundary address |
7d70f334 | 1260 | * |
8b6e50c9 | 1261 | * Returs unlock status. |
7d70f334 VS |
1262 | */ |
1263 | static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, | |
1264 | uint64_t len, int invert) | |
1265 | { | |
1266 | int ret = 0; | |
1267 | int status, page; | |
862eba51 | 1268 | struct nand_chip *chip = mtd_to_nand(mtd); |
7d70f334 VS |
1269 | |
1270 | /* Submit address of first page to unlock */ | |
1271 | page = ofs >> chip->page_shift; | |
1272 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); | |
1273 | ||
1274 | /* Submit address of last page to unlock */ | |
1275 | page = (ofs + len) >> chip->page_shift; | |
1276 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, | |
1277 | (page | invert) & chip->pagemask); | |
1278 | ||
1279 | /* Call wait ready function */ | |
1280 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 1281 | /* See if device thinks it succeeded */ |
74830966 | 1282 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 1283 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
1284 | __func__, status); |
1285 | ret = -EIO; | |
1286 | } | |
1287 | ||
1288 | return ret; | |
1289 | } | |
1290 | ||
1291 | /** | |
b6d676db | 1292 | * nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
1293 | * @mtd: mtd info |
1294 | * @ofs: offset to start unlock from | |
1295 | * @len: length to unlock | |
7d70f334 | 1296 | * |
8b6e50c9 | 1297 | * Returns unlock status. |
7d70f334 VS |
1298 | */ |
1299 | int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
1300 | { | |
1301 | int ret = 0; | |
1302 | int chipnr; | |
862eba51 | 1303 | struct nand_chip *chip = mtd_to_nand(mtd); |
7d70f334 | 1304 | |
289c0522 | 1305 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
1306 | __func__, (unsigned long long)ofs, len); |
1307 | ||
1308 | if (check_offs_len(mtd, ofs, len)) | |
b1a2348a | 1309 | return -EINVAL; |
7d70f334 VS |
1310 | |
1311 | /* Align to last block address if size addresses end of the device */ | |
1312 | if (ofs + len == mtd->size) | |
1313 | len -= mtd->erasesize; | |
1314 | ||
6a8214aa | 1315 | nand_get_device(mtd, FL_UNLOCKING); |
7d70f334 VS |
1316 | |
1317 | /* Shift to get chip number */ | |
1318 | chipnr = ofs >> chip->chip_shift; | |
1319 | ||
57d3a9a8 WD |
1320 | /* |
1321 | * Reset the chip. | |
1322 | * If we want to check the WP through READ STATUS and check the bit 7 | |
1323 | * we must reset the chip | |
1324 | * some operation can also clear the bit 7 of status register | |
1325 | * eg. erase/program a locked block | |
1326 | */ | |
73f907fd BB |
1327 | nand_reset(chip, chipnr); |
1328 | ||
1329 | chip->select_chip(mtd, chipnr); | |
57d3a9a8 | 1330 | |
7d70f334 VS |
1331 | /* Check, if it is write protected */ |
1332 | if (nand_check_wp(mtd)) { | |
289c0522 | 1333 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
1334 | __func__); |
1335 | ret = -EIO; | |
1336 | goto out; | |
1337 | } | |
1338 | ||
1339 | ret = __nand_unlock(mtd, ofs, len, 0); | |
1340 | ||
1341 | out: | |
b0bb6903 | 1342 | chip->select_chip(mtd, -1); |
7d70f334 VS |
1343 | nand_release_device(mtd); |
1344 | ||
1345 | return ret; | |
1346 | } | |
7351d3a5 | 1347 | EXPORT_SYMBOL(nand_unlock); |
7d70f334 VS |
1348 | |
1349 | /** | |
b6d676db | 1350 | * nand_lock - [REPLACEABLE] locks all blocks present in the device |
b6d676db RD |
1351 | * @mtd: mtd info |
1352 | * @ofs: offset to start unlock from | |
1353 | * @len: length to unlock | |
7d70f334 | 1354 | * |
8b6e50c9 BN |
1355 | * This feature is not supported in many NAND parts. 'Micron' NAND parts do |
1356 | * have this feature, but it allows only to lock all blocks, not for specified | |
1357 | * range for block. Implementing 'lock' feature by making use of 'unlock', for | |
1358 | * now. | |
7d70f334 | 1359 | * |
8b6e50c9 | 1360 | * Returns lock status. |
7d70f334 VS |
1361 | */ |
1362 | int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
1363 | { | |
1364 | int ret = 0; | |
1365 | int chipnr, status, page; | |
862eba51 | 1366 | struct nand_chip *chip = mtd_to_nand(mtd); |
7d70f334 | 1367 | |
289c0522 | 1368 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
1369 | __func__, (unsigned long long)ofs, len); |
1370 | ||
1371 | if (check_offs_len(mtd, ofs, len)) | |
b1a2348a | 1372 | return -EINVAL; |
7d70f334 | 1373 | |
6a8214aa | 1374 | nand_get_device(mtd, FL_LOCKING); |
7d70f334 VS |
1375 | |
1376 | /* Shift to get chip number */ | |
1377 | chipnr = ofs >> chip->chip_shift; | |
1378 | ||
57d3a9a8 WD |
1379 | /* |
1380 | * Reset the chip. | |
1381 | * If we want to check the WP through READ STATUS and check the bit 7 | |
1382 | * we must reset the chip | |
1383 | * some operation can also clear the bit 7 of status register | |
1384 | * eg. erase/program a locked block | |
1385 | */ | |
73f907fd BB |
1386 | nand_reset(chip, chipnr); |
1387 | ||
1388 | chip->select_chip(mtd, chipnr); | |
57d3a9a8 | 1389 | |
7d70f334 VS |
1390 | /* Check, if it is write protected */ |
1391 | if (nand_check_wp(mtd)) { | |
289c0522 | 1392 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
1393 | __func__); |
1394 | status = MTD_ERASE_FAILED; | |
1395 | ret = -EIO; | |
1396 | goto out; | |
1397 | } | |
1398 | ||
1399 | /* Submit address of first page to lock */ | |
1400 | page = ofs >> chip->page_shift; | |
1401 | chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); | |
1402 | ||
1403 | /* Call wait ready function */ | |
1404 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 1405 | /* See if device thinks it succeeded */ |
74830966 | 1406 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 1407 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
1408 | __func__, status); |
1409 | ret = -EIO; | |
1410 | goto out; | |
1411 | } | |
1412 | ||
1413 | ret = __nand_unlock(mtd, ofs, len, 0x1); | |
1414 | ||
1415 | out: | |
b0bb6903 | 1416 | chip->select_chip(mtd, -1); |
7d70f334 VS |
1417 | nand_release_device(mtd); |
1418 | ||
1419 | return ret; | |
1420 | } | |
7351d3a5 | 1421 | EXPORT_SYMBOL(nand_lock); |
7d70f334 | 1422 | |
730a43fb BB |
1423 | /** |
1424 | * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data | |
1425 | * @buf: buffer to test | |
1426 | * @len: buffer length | |
1427 | * @bitflips_threshold: maximum number of bitflips | |
1428 | * | |
1429 | * Check if a buffer contains only 0xff, which means the underlying region | |
1430 | * has been erased and is ready to be programmed. | |
1431 | * The bitflips_threshold specify the maximum number of bitflips before | |
1432 | * considering the region is not erased. | |
1433 | * Note: The logic of this function has been extracted from the memweight | |
1434 | * implementation, except that nand_check_erased_buf function exit before | |
1435 | * testing the whole buffer if the number of bitflips exceed the | |
1436 | * bitflips_threshold value. | |
1437 | * | |
1438 | * Returns a positive number of bitflips less than or equal to | |
1439 | * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the | |
1440 | * threshold. | |
1441 | */ | |
1442 | static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold) | |
1443 | { | |
1444 | const unsigned char *bitmap = buf; | |
1445 | int bitflips = 0; | |
1446 | int weight; | |
1447 | ||
1448 | for (; len && ((uintptr_t)bitmap) % sizeof(long); | |
1449 | len--, bitmap++) { | |
1450 | weight = hweight8(*bitmap); | |
1451 | bitflips += BITS_PER_BYTE - weight; | |
1452 | if (unlikely(bitflips > bitflips_threshold)) | |
1453 | return -EBADMSG; | |
1454 | } | |
1455 | ||
1456 | for (; len >= sizeof(long); | |
1457 | len -= sizeof(long), bitmap += sizeof(long)) { | |
086567f1 PM |
1458 | unsigned long d = *((unsigned long *)bitmap); |
1459 | if (d == ~0UL) | |
1460 | continue; | |
1461 | weight = hweight_long(d); | |
730a43fb BB |
1462 | bitflips += BITS_PER_LONG - weight; |
1463 | if (unlikely(bitflips > bitflips_threshold)) | |
1464 | return -EBADMSG; | |
1465 | } | |
1466 | ||
1467 | for (; len > 0; len--, bitmap++) { | |
1468 | weight = hweight8(*bitmap); | |
1469 | bitflips += BITS_PER_BYTE - weight; | |
1470 | if (unlikely(bitflips > bitflips_threshold)) | |
1471 | return -EBADMSG; | |
1472 | } | |
1473 | ||
1474 | return bitflips; | |
1475 | } | |
1476 | ||
1477 | /** | |
1478 | * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only | |
1479 | * 0xff data | |
1480 | * @data: data buffer to test | |
1481 | * @datalen: data length | |
1482 | * @ecc: ECC buffer | |
1483 | * @ecclen: ECC length | |
1484 | * @extraoob: extra OOB buffer | |
1485 | * @extraooblen: extra OOB length | |
1486 | * @bitflips_threshold: maximum number of bitflips | |
1487 | * | |
1488 | * Check if a data buffer and its associated ECC and OOB data contains only | |
1489 | * 0xff pattern, which means the underlying region has been erased and is | |
1490 | * ready to be programmed. | |
1491 | * The bitflips_threshold specify the maximum number of bitflips before | |
1492 | * considering the region as not erased. | |
1493 | * | |
1494 | * Note: | |
1495 | * 1/ ECC algorithms are working on pre-defined block sizes which are usually | |
1496 | * different from the NAND page size. When fixing bitflips, ECC engines will | |
1497 | * report the number of errors per chunk, and the NAND core infrastructure | |
1498 | * expect you to return the maximum number of bitflips for the whole page. | |
1499 | * This is why you should always use this function on a single chunk and | |
1500 | * not on the whole page. After checking each chunk you should update your | |
1501 | * max_bitflips value accordingly. | |
1502 | * 2/ When checking for bitflips in erased pages you should not only check | |
1503 | * the payload data but also their associated ECC data, because a user might | |
1504 | * have programmed almost all bits to 1 but a few. In this case, we | |
1505 | * shouldn't consider the chunk as erased, and checking ECC bytes prevent | |
1506 | * this case. | |
1507 | * 3/ The extraoob argument is optional, and should be used if some of your OOB | |
1508 | * data are protected by the ECC engine. | |
1509 | * It could also be used if you support subpages and want to attach some | |
1510 | * extra OOB data to an ECC chunk. | |
1511 | * | |
1512 | * Returns a positive number of bitflips less than or equal to | |
1513 | * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the | |
1514 | * threshold. In case of success, the passed buffers are filled with 0xff. | |
1515 | */ | |
1516 | int nand_check_erased_ecc_chunk(void *data, int datalen, | |
1517 | void *ecc, int ecclen, | |
1518 | void *extraoob, int extraooblen, | |
1519 | int bitflips_threshold) | |
1520 | { | |
1521 | int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0; | |
1522 | ||
1523 | data_bitflips = nand_check_erased_buf(data, datalen, | |
1524 | bitflips_threshold); | |
1525 | if (data_bitflips < 0) | |
1526 | return data_bitflips; | |
1527 | ||
1528 | bitflips_threshold -= data_bitflips; | |
1529 | ||
1530 | ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold); | |
1531 | if (ecc_bitflips < 0) | |
1532 | return ecc_bitflips; | |
1533 | ||
1534 | bitflips_threshold -= ecc_bitflips; | |
1535 | ||
1536 | extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen, | |
1537 | bitflips_threshold); | |
1538 | if (extraoob_bitflips < 0) | |
1539 | return extraoob_bitflips; | |
1540 | ||
1541 | if (data_bitflips) | |
1542 | memset(data, 0xff, datalen); | |
1543 | ||
1544 | if (ecc_bitflips) | |
1545 | memset(ecc, 0xff, ecclen); | |
1546 | ||
1547 | if (extraoob_bitflips) | |
1548 | memset(extraoob, 0xff, extraooblen); | |
1549 | ||
1550 | return data_bitflips + ecc_bitflips + extraoob_bitflips; | |
1551 | } | |
1552 | EXPORT_SYMBOL(nand_check_erased_ecc_chunk); | |
1553 | ||
8593fbc6 | 1554 | /** |
7854d3f7 | 1555 | * nand_read_page_raw - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1556 | * @mtd: mtd info structure |
1557 | * @chip: nand chip info structure | |
1558 | * @buf: buffer to store read data | |
1fbb938d | 1559 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1560 | * @page: page number to read |
52ff49df | 1561 | * |
7854d3f7 | 1562 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 | 1563 | */ |
cc0f51ec TP |
1564 | int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
1565 | uint8_t *buf, int oob_required, int page) | |
8593fbc6 TG |
1566 | { |
1567 | chip->read_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
1568 | if (oob_required) |
1569 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
8593fbc6 TG |
1570 | return 0; |
1571 | } | |
cc0f51ec | 1572 | EXPORT_SYMBOL(nand_read_page_raw); |
8593fbc6 | 1573 | |
52ff49df | 1574 | /** |
7854d3f7 | 1575 | * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1576 | * @mtd: mtd info structure |
1577 | * @chip: nand chip info structure | |
1578 | * @buf: buffer to store read data | |
1fbb938d | 1579 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1580 | * @page: page number to read |
52ff49df DB |
1581 | * |
1582 | * We need a special oob layout and handling even when OOB isn't used. | |
1583 | */ | |
7351d3a5 | 1584 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
1585 | struct nand_chip *chip, uint8_t *buf, |
1586 | int oob_required, int page) | |
52ff49df DB |
1587 | { |
1588 | int eccsize = chip->ecc.size; | |
1589 | int eccbytes = chip->ecc.bytes; | |
1590 | uint8_t *oob = chip->oob_poi; | |
1591 | int steps, size; | |
1592 | ||
1593 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1594 | chip->read_buf(mtd, buf, eccsize); | |
1595 | buf += eccsize; | |
1596 | ||
1597 | if (chip->ecc.prepad) { | |
1598 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1599 | oob += chip->ecc.prepad; | |
1600 | } | |
1601 | ||
1602 | chip->read_buf(mtd, oob, eccbytes); | |
1603 | oob += eccbytes; | |
1604 | ||
1605 | if (chip->ecc.postpad) { | |
1606 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1607 | oob += chip->ecc.postpad; | |
1608 | } | |
1609 | } | |
1610 | ||
1611 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1612 | if (size) | |
1613 | chip->read_buf(mtd, oob, size); | |
1614 | ||
1615 | return 0; | |
1616 | } | |
1617 | ||
1da177e4 | 1618 | /** |
7854d3f7 | 1619 | * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function |
8b6e50c9 BN |
1620 | * @mtd: mtd info structure |
1621 | * @chip: nand chip info structure | |
1622 | * @buf: buffer to store read data | |
1fbb938d | 1623 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1624 | * @page: page number to read |
068e3c0a | 1625 | */ |
f5bbdacc | 1626 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1627 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1628 | { |
846031d3 | 1629 | int i, eccsize = chip->ecc.size, ret; |
f5bbdacc TG |
1630 | int eccbytes = chip->ecc.bytes; |
1631 | int eccsteps = chip->ecc.steps; | |
1632 | uint8_t *p = buf; | |
4bf63fcb DW |
1633 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1634 | uint8_t *ecc_code = chip->buffers->ecccode; | |
3f91e94f | 1635 | unsigned int max_bitflips = 0; |
f5bbdacc | 1636 | |
1fbb938d | 1637 | chip->ecc.read_page_raw(mtd, chip, buf, 1, page); |
f5bbdacc TG |
1638 | |
1639 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1640 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1641 | ||
846031d3 BB |
1642 | ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, |
1643 | chip->ecc.total); | |
1644 | if (ret) | |
1645 | return ret; | |
f5bbdacc TG |
1646 | |
1647 | eccsteps = chip->ecc.steps; | |
1648 | p = buf; | |
1649 | ||
1650 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1651 | int stat; | |
1652 | ||
1653 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
3f91e94f | 1654 | if (stat < 0) { |
f5bbdacc | 1655 | mtd->ecc_stats.failed++; |
3f91e94f | 1656 | } else { |
f5bbdacc | 1657 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1658 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1659 | } | |
f5bbdacc | 1660 | } |
3f91e94f | 1661 | return max_bitflips; |
22c60f5f | 1662 | } |
1da177e4 | 1663 | |
3d459559 | 1664 | /** |
837a6ba4 | 1665 | * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function |
8b6e50c9 BN |
1666 | * @mtd: mtd info structure |
1667 | * @chip: nand chip info structure | |
1668 | * @data_offs: offset of requested data within the page | |
1669 | * @readlen: data length | |
1670 | * @bufpoi: buffer to store read data | |
e004debd | 1671 | * @page: page number to read |
3d459559 | 1672 | */ |
7351d3a5 | 1673 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, |
e004debd HS |
1674 | uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi, |
1675 | int page) | |
3d459559 | 1676 | { |
846031d3 | 1677 | int start_step, end_step, num_steps, ret; |
3d459559 AK |
1678 | uint8_t *p; |
1679 | int data_col_addr, i, gaps = 0; | |
1680 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
1681 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
846031d3 | 1682 | int index, section = 0; |
3f91e94f | 1683 | unsigned int max_bitflips = 0; |
846031d3 | 1684 | struct mtd_oob_region oobregion = { }; |
3d459559 | 1685 | |
7854d3f7 | 1686 | /* Column address within the page aligned to ECC size (256bytes) */ |
3d459559 AK |
1687 | start_step = data_offs / chip->ecc.size; |
1688 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
1689 | num_steps = end_step - start_step + 1; | |
4a4163ca | 1690 | index = start_step * chip->ecc.bytes; |
3d459559 | 1691 | |
8b6e50c9 | 1692 | /* Data size aligned to ECC ecc.size */ |
3d459559 AK |
1693 | datafrag_len = num_steps * chip->ecc.size; |
1694 | eccfrag_len = num_steps * chip->ecc.bytes; | |
1695 | ||
1696 | data_col_addr = start_step * chip->ecc.size; | |
1697 | /* If we read not a page aligned data */ | |
1698 | if (data_col_addr != 0) | |
1699 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); | |
1700 | ||
1701 | p = bufpoi + data_col_addr; | |
1702 | chip->read_buf(mtd, p, datafrag_len); | |
1703 | ||
8b6e50c9 | 1704 | /* Calculate ECC */ |
3d459559 AK |
1705 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) |
1706 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); | |
1707 | ||
8b6e50c9 BN |
1708 | /* |
1709 | * The performance is faster if we position offsets according to | |
7854d3f7 | 1710 | * ecc.pos. Let's make sure that there are no gaps in ECC positions. |
8b6e50c9 | 1711 | */ |
846031d3 BB |
1712 | ret = mtd_ooblayout_find_eccregion(mtd, index, §ion, &oobregion); |
1713 | if (ret) | |
1714 | return ret; | |
1715 | ||
1716 | if (oobregion.length < eccfrag_len) | |
1717 | gaps = 1; | |
1718 | ||
3d459559 AK |
1719 | if (gaps) { |
1720 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1721 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1722 | } else { | |
8b6e50c9 | 1723 | /* |
7854d3f7 | 1724 | * Send the command to read the particular ECC bytes take care |
8b6e50c9 BN |
1725 | * about buswidth alignment in read_buf. |
1726 | */ | |
846031d3 | 1727 | aligned_pos = oobregion.offset & ~(busw - 1); |
3d459559 | 1728 | aligned_len = eccfrag_len; |
846031d3 | 1729 | if (oobregion.offset & (busw - 1)) |
3d459559 | 1730 | aligned_len++; |
846031d3 BB |
1731 | if ((oobregion.offset + (num_steps * chip->ecc.bytes)) & |
1732 | (busw - 1)) | |
3d459559 AK |
1733 | aligned_len++; |
1734 | ||
7351d3a5 | 1735 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, |
846031d3 | 1736 | mtd->writesize + aligned_pos, -1); |
3d459559 AK |
1737 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); |
1738 | } | |
1739 | ||
846031d3 BB |
1740 | ret = mtd_ooblayout_get_eccbytes(mtd, chip->buffers->ecccode, |
1741 | chip->oob_poi, index, eccfrag_len); | |
1742 | if (ret) | |
1743 | return ret; | |
3d459559 AK |
1744 | |
1745 | p = bufpoi + data_col_addr; | |
1746 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
1747 | int stat; | |
1748 | ||
7351d3a5 FF |
1749 | stat = chip->ecc.correct(mtd, p, |
1750 | &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); | |
40cbe6ee BB |
1751 | if (stat == -EBADMSG && |
1752 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
1753 | /* check for empty pages with bitflips */ | |
1754 | stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, | |
1755 | &chip->buffers->ecccode[i], | |
1756 | chip->ecc.bytes, | |
1757 | NULL, 0, | |
1758 | chip->ecc.strength); | |
1759 | } | |
1760 | ||
3f91e94f | 1761 | if (stat < 0) { |
3d459559 | 1762 | mtd->ecc_stats.failed++; |
3f91e94f | 1763 | } else { |
3d459559 | 1764 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1765 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1766 | } | |
3d459559 | 1767 | } |
3f91e94f | 1768 | return max_bitflips; |
3d459559 AK |
1769 | } |
1770 | ||
068e3c0a | 1771 | /** |
7854d3f7 | 1772 | * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function |
8b6e50c9 BN |
1773 | * @mtd: mtd info structure |
1774 | * @chip: nand chip info structure | |
1775 | * @buf: buffer to store read data | |
1fbb938d | 1776 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1777 | * @page: page number to read |
068e3c0a | 1778 | * |
7854d3f7 | 1779 | * Not for syndrome calculating ECC controllers which need a special oob layout. |
068e3c0a | 1780 | */ |
f5bbdacc | 1781 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1782 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1783 | { |
846031d3 | 1784 | int i, eccsize = chip->ecc.size, ret; |
f5bbdacc TG |
1785 | int eccbytes = chip->ecc.bytes; |
1786 | int eccsteps = chip->ecc.steps; | |
1787 | uint8_t *p = buf; | |
4bf63fcb DW |
1788 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1789 | uint8_t *ecc_code = chip->buffers->ecccode; | |
3f91e94f | 1790 | unsigned int max_bitflips = 0; |
f5bbdacc TG |
1791 | |
1792 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1793 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1794 | chip->read_buf(mtd, p, eccsize); | |
1795 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 1796 | } |
f75e5097 | 1797 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 1798 | |
846031d3 BB |
1799 | ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, |
1800 | chip->ecc.total); | |
1801 | if (ret) | |
1802 | return ret; | |
1da177e4 | 1803 | |
f5bbdacc TG |
1804 | eccsteps = chip->ecc.steps; |
1805 | p = buf; | |
61b03bd7 | 1806 | |
f5bbdacc TG |
1807 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1808 | int stat; | |
1da177e4 | 1809 | |
f5bbdacc | 1810 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
40cbe6ee BB |
1811 | if (stat == -EBADMSG && |
1812 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
1813 | /* check for empty pages with bitflips */ | |
1814 | stat = nand_check_erased_ecc_chunk(p, eccsize, | |
1815 | &ecc_code[i], eccbytes, | |
1816 | NULL, 0, | |
1817 | chip->ecc.strength); | |
1818 | } | |
1819 | ||
3f91e94f | 1820 | if (stat < 0) { |
f5bbdacc | 1821 | mtd->ecc_stats.failed++; |
3f91e94f | 1822 | } else { |
f5bbdacc | 1823 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1824 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1825 | } | |
f5bbdacc | 1826 | } |
3f91e94f | 1827 | return max_bitflips; |
f5bbdacc | 1828 | } |
1da177e4 | 1829 | |
6e0cb135 | 1830 | /** |
7854d3f7 | 1831 | * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first |
8b6e50c9 BN |
1832 | * @mtd: mtd info structure |
1833 | * @chip: nand chip info structure | |
1834 | * @buf: buffer to store read data | |
1fbb938d | 1835 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1836 | * @page: page number to read |
6e0cb135 | 1837 | * |
8b6e50c9 BN |
1838 | * Hardware ECC for large page chips, require OOB to be read first. For this |
1839 | * ECC mode, the write_page method is re-used from ECC_HW. These methods | |
1840 | * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with | |
1841 | * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from | |
1842 | * the data area, by overwriting the NAND manufacturer bad block markings. | |
6e0cb135 SN |
1843 | */ |
1844 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1fbb938d | 1845 | struct nand_chip *chip, uint8_t *buf, int oob_required, int page) |
6e0cb135 | 1846 | { |
846031d3 | 1847 | int i, eccsize = chip->ecc.size, ret; |
6e0cb135 SN |
1848 | int eccbytes = chip->ecc.bytes; |
1849 | int eccsteps = chip->ecc.steps; | |
1850 | uint8_t *p = buf; | |
1851 | uint8_t *ecc_code = chip->buffers->ecccode; | |
6e0cb135 | 1852 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
3f91e94f | 1853 | unsigned int max_bitflips = 0; |
6e0cb135 SN |
1854 | |
1855 | /* Read the OOB area first */ | |
1856 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1857 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1858 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1859 | ||
846031d3 BB |
1860 | ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, |
1861 | chip->ecc.total); | |
1862 | if (ret) | |
1863 | return ret; | |
6e0cb135 SN |
1864 | |
1865 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1866 | int stat; | |
1867 | ||
1868 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1869 | chip->read_buf(mtd, p, eccsize); | |
1870 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1871 | ||
1872 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
40cbe6ee BB |
1873 | if (stat == -EBADMSG && |
1874 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
1875 | /* check for empty pages with bitflips */ | |
1876 | stat = nand_check_erased_ecc_chunk(p, eccsize, | |
1877 | &ecc_code[i], eccbytes, | |
1878 | NULL, 0, | |
1879 | chip->ecc.strength); | |
1880 | } | |
1881 | ||
3f91e94f | 1882 | if (stat < 0) { |
6e0cb135 | 1883 | mtd->ecc_stats.failed++; |
3f91e94f | 1884 | } else { |
6e0cb135 | 1885 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1886 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1887 | } | |
6e0cb135 | 1888 | } |
3f91e94f | 1889 | return max_bitflips; |
6e0cb135 SN |
1890 | } |
1891 | ||
f5bbdacc | 1892 | /** |
7854d3f7 | 1893 | * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read |
8b6e50c9 BN |
1894 | * @mtd: mtd info structure |
1895 | * @chip: nand chip info structure | |
1896 | * @buf: buffer to store read data | |
1fbb938d | 1897 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1898 | * @page: page number to read |
f5bbdacc | 1899 | * |
8b6e50c9 BN |
1900 | * The hw generator calculates the error syndrome automatically. Therefore we |
1901 | * need a special oob layout and handling. | |
f5bbdacc TG |
1902 | */ |
1903 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1904 | uint8_t *buf, int oob_required, int page) |
f5bbdacc TG |
1905 | { |
1906 | int i, eccsize = chip->ecc.size; | |
1907 | int eccbytes = chip->ecc.bytes; | |
1908 | int eccsteps = chip->ecc.steps; | |
40cbe6ee | 1909 | int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad; |
f5bbdacc | 1910 | uint8_t *p = buf; |
f75e5097 | 1911 | uint8_t *oob = chip->oob_poi; |
3f91e94f | 1912 | unsigned int max_bitflips = 0; |
1da177e4 | 1913 | |
f5bbdacc TG |
1914 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1915 | int stat; | |
61b03bd7 | 1916 | |
f5bbdacc TG |
1917 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
1918 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 1919 | |
f5bbdacc TG |
1920 | if (chip->ecc.prepad) { |
1921 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1922 | oob += chip->ecc.prepad; | |
1923 | } | |
1da177e4 | 1924 | |
f5bbdacc TG |
1925 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1926 | chip->read_buf(mtd, oob, eccbytes); | |
1927 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 1928 | |
f5bbdacc | 1929 | oob += eccbytes; |
1da177e4 | 1930 | |
f5bbdacc TG |
1931 | if (chip->ecc.postpad) { |
1932 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1933 | oob += chip->ecc.postpad; | |
61b03bd7 | 1934 | } |
40cbe6ee BB |
1935 | |
1936 | if (stat == -EBADMSG && | |
1937 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
1938 | /* check for empty pages with bitflips */ | |
1939 | stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, | |
1940 | oob - eccpadbytes, | |
1941 | eccpadbytes, | |
1942 | NULL, 0, | |
1943 | chip->ecc.strength); | |
1944 | } | |
1945 | ||
1946 | if (stat < 0) { | |
1947 | mtd->ecc_stats.failed++; | |
1948 | } else { | |
1949 | mtd->ecc_stats.corrected += stat; | |
1950 | max_bitflips = max_t(unsigned int, max_bitflips, stat); | |
1951 | } | |
f5bbdacc | 1952 | } |
1da177e4 | 1953 | |
f5bbdacc | 1954 | /* Calculate remaining oob bytes */ |
7e4178f9 | 1955 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
1956 | if (i) |
1957 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 1958 | |
3f91e94f | 1959 | return max_bitflips; |
f5bbdacc | 1960 | } |
1da177e4 | 1961 | |
f5bbdacc | 1962 | /** |
7854d3f7 | 1963 | * nand_transfer_oob - [INTERN] Transfer oob to client buffer |
846031d3 | 1964 | * @mtd: mtd info structure |
8b6e50c9 BN |
1965 | * @oob: oob destination address |
1966 | * @ops: oob ops structure | |
1967 | * @len: size of oob to transfer | |
8593fbc6 | 1968 | */ |
846031d3 | 1969 | static uint8_t *nand_transfer_oob(struct mtd_info *mtd, uint8_t *oob, |
7014568b | 1970 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 1971 | { |
846031d3 BB |
1972 | struct nand_chip *chip = mtd_to_nand(mtd); |
1973 | int ret; | |
1974 | ||
f8ac0414 | 1975 | switch (ops->mode) { |
8593fbc6 | 1976 | |
0612b9dd BN |
1977 | case MTD_OPS_PLACE_OOB: |
1978 | case MTD_OPS_RAW: | |
8593fbc6 TG |
1979 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); |
1980 | return oob + len; | |
1981 | ||
846031d3 BB |
1982 | case MTD_OPS_AUTO_OOB: |
1983 | ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi, | |
1984 | ops->ooboffs, len); | |
1985 | BUG_ON(ret); | |
1986 | return oob + len; | |
1987 | ||
8593fbc6 TG |
1988 | default: |
1989 | BUG(); | |
1990 | } | |
1991 | return NULL; | |
1992 | } | |
1993 | ||
ba84fb59 BN |
1994 | /** |
1995 | * nand_setup_read_retry - [INTERN] Set the READ RETRY mode | |
1996 | * @mtd: MTD device structure | |
1997 | * @retry_mode: the retry mode to use | |
1998 | * | |
1999 | * Some vendors supply a special command to shift the Vt threshold, to be used | |
2000 | * when there are too many bitflips in a page (i.e., ECC error). After setting | |
2001 | * a new threshold, the host should retry reading the page. | |
2002 | */ | |
2003 | static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) | |
2004 | { | |
862eba51 | 2005 | struct nand_chip *chip = mtd_to_nand(mtd); |
ba84fb59 BN |
2006 | |
2007 | pr_debug("setting READ RETRY mode %d\n", retry_mode); | |
2008 | ||
2009 | if (retry_mode >= chip->read_retries) | |
2010 | return -EINVAL; | |
2011 | ||
2012 | if (!chip->setup_read_retry) | |
2013 | return -EOPNOTSUPP; | |
2014 | ||
2015 | return chip->setup_read_retry(mtd, retry_mode); | |
2016 | } | |
2017 | ||
8593fbc6 | 2018 | /** |
7854d3f7 | 2019 | * nand_do_read_ops - [INTERN] Read data with ECC |
8b6e50c9 BN |
2020 | * @mtd: MTD device structure |
2021 | * @from: offset to read from | |
2022 | * @ops: oob ops structure | |
f5bbdacc TG |
2023 | * |
2024 | * Internal function. Called with chip held. | |
2025 | */ | |
8593fbc6 TG |
2026 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
2027 | struct mtd_oob_ops *ops) | |
f5bbdacc | 2028 | { |
e47f3db4 | 2029 | int chipnr, page, realpage, col, bytes, aligned, oob_required; |
862eba51 | 2030 | struct nand_chip *chip = mtd_to_nand(mtd); |
f5bbdacc | 2031 | int ret = 0; |
8593fbc6 | 2032 | uint32_t readlen = ops->len; |
7014568b | 2033 | uint32_t oobreadlen = ops->ooblen; |
29f1058a | 2034 | uint32_t max_oobsize = mtd_oobavail(mtd, ops); |
9aca334e | 2035 | |
8593fbc6 | 2036 | uint8_t *bufpoi, *oob, *buf; |
66507c7b | 2037 | int use_bufpoi; |
edbc4540 | 2038 | unsigned int max_bitflips = 0; |
ba84fb59 | 2039 | int retry_mode = 0; |
b72f3dfb | 2040 | bool ecc_fail = false; |
1da177e4 | 2041 | |
f5bbdacc TG |
2042 | chipnr = (int)(from >> chip->chip_shift); |
2043 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 2044 | |
f5bbdacc TG |
2045 | realpage = (int)(from >> chip->page_shift); |
2046 | page = realpage & chip->pagemask; | |
1da177e4 | 2047 | |
f5bbdacc | 2048 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 2049 | |
8593fbc6 TG |
2050 | buf = ops->datbuf; |
2051 | oob = ops->oobbuf; | |
e47f3db4 | 2052 | oob_required = oob ? 1 : 0; |
8593fbc6 | 2053 | |
f8ac0414 | 2054 | while (1) { |
b72f3dfb BN |
2055 | unsigned int ecc_failures = mtd->ecc_stats.failed; |
2056 | ||
f5bbdacc TG |
2057 | bytes = min(mtd->writesize - col, readlen); |
2058 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 2059 | |
66507c7b KD |
2060 | if (!aligned) |
2061 | use_bufpoi = 1; | |
2062 | else if (chip->options & NAND_USE_BOUNCE_BUFFER) | |
477544c6 MY |
2063 | use_bufpoi = !virt_addr_valid(buf) || |
2064 | !IS_ALIGNED((unsigned long)buf, | |
2065 | chip->buf_align); | |
66507c7b KD |
2066 | else |
2067 | use_bufpoi = 0; | |
2068 | ||
8b6e50c9 | 2069 | /* Is the current page in the buffer? */ |
8593fbc6 | 2070 | if (realpage != chip->pagebuf || oob) { |
66507c7b KD |
2071 | bufpoi = use_bufpoi ? chip->buffers->databuf : buf; |
2072 | ||
2073 | if (use_bufpoi && aligned) | |
2074 | pr_debug("%s: using read bounce buffer for buf@%p\n", | |
2075 | __func__, buf); | |
61b03bd7 | 2076 | |
ba84fb59 | 2077 | read_retry: |
3371d663 MG |
2078 | if (nand_standard_page_accessors(&chip->ecc)) |
2079 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); | |
1da177e4 | 2080 | |
edbc4540 MD |
2081 | /* |
2082 | * Now read the page into the buffer. Absent an error, | |
2083 | * the read methods return max bitflips per ecc step. | |
2084 | */ | |
0612b9dd | 2085 | if (unlikely(ops->mode == MTD_OPS_RAW)) |
1fbb938d | 2086 | ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, |
e47f3db4 BN |
2087 | oob_required, |
2088 | page); | |
a5ff4f10 JW |
2089 | else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && |
2090 | !oob) | |
7351d3a5 | 2091 | ret = chip->ecc.read_subpage(mtd, chip, |
e004debd HS |
2092 | col, bytes, bufpoi, |
2093 | page); | |
956e944c | 2094 | else |
46a8cf2d | 2095 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
e47f3db4 | 2096 | oob_required, page); |
6d77b9d0 | 2097 | if (ret < 0) { |
66507c7b | 2098 | if (use_bufpoi) |
6d77b9d0 BN |
2099 | /* Invalidate page cache */ |
2100 | chip->pagebuf = -1; | |
1da177e4 | 2101 | break; |
6d77b9d0 | 2102 | } |
f5bbdacc TG |
2103 | |
2104 | /* Transfer not aligned data */ | |
66507c7b | 2105 | if (use_bufpoi) { |
a5ff4f10 | 2106 | if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && |
b72f3dfb | 2107 | !(mtd->ecc_stats.failed - ecc_failures) && |
edbc4540 | 2108 | (ops->mode != MTD_OPS_RAW)) { |
3d459559 | 2109 | chip->pagebuf = realpage; |
edbc4540 MD |
2110 | chip->pagebuf_bitflips = ret; |
2111 | } else { | |
6d77b9d0 BN |
2112 | /* Invalidate page cache */ |
2113 | chip->pagebuf = -1; | |
edbc4540 | 2114 | } |
4bf63fcb | 2115 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
2116 | } |
2117 | ||
8593fbc6 | 2118 | if (unlikely(oob)) { |
b64d39d8 ML |
2119 | int toread = min(oobreadlen, max_oobsize); |
2120 | ||
2121 | if (toread) { | |
846031d3 | 2122 | oob = nand_transfer_oob(mtd, |
b64d39d8 ML |
2123 | oob, ops, toread); |
2124 | oobreadlen -= toread; | |
2125 | } | |
8593fbc6 | 2126 | } |
5bc7c33c BN |
2127 | |
2128 | if (chip->options & NAND_NEED_READRDY) { | |
2129 | /* Apply delay or wait for ready/busy pin */ | |
2130 | if (!chip->dev_ready) | |
2131 | udelay(chip->chip_delay); | |
2132 | else | |
2133 | nand_wait_ready(mtd); | |
2134 | } | |
b72f3dfb | 2135 | |
ba84fb59 | 2136 | if (mtd->ecc_stats.failed - ecc_failures) { |
28fa65e6 | 2137 | if (retry_mode + 1 < chip->read_retries) { |
ba84fb59 BN |
2138 | retry_mode++; |
2139 | ret = nand_setup_read_retry(mtd, | |
2140 | retry_mode); | |
2141 | if (ret < 0) | |
2142 | break; | |
2143 | ||
2144 | /* Reset failures; retry */ | |
2145 | mtd->ecc_stats.failed = ecc_failures; | |
2146 | goto read_retry; | |
2147 | } else { | |
2148 | /* No more retry modes; real failure */ | |
2149 | ecc_fail = true; | |
2150 | } | |
2151 | } | |
2152 | ||
2153 | buf += bytes; | |
07604686 | 2154 | max_bitflips = max_t(unsigned int, max_bitflips, ret); |
8593fbc6 | 2155 | } else { |
4bf63fcb | 2156 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 | 2157 | buf += bytes; |
edbc4540 MD |
2158 | max_bitflips = max_t(unsigned int, max_bitflips, |
2159 | chip->pagebuf_bitflips); | |
8593fbc6 | 2160 | } |
1da177e4 | 2161 | |
f5bbdacc | 2162 | readlen -= bytes; |
61b03bd7 | 2163 | |
ba84fb59 BN |
2164 | /* Reset to retry mode 0 */ |
2165 | if (retry_mode) { | |
2166 | ret = nand_setup_read_retry(mtd, 0); | |
2167 | if (ret < 0) | |
2168 | break; | |
2169 | retry_mode = 0; | |
2170 | } | |
2171 | ||
f5bbdacc | 2172 | if (!readlen) |
61b03bd7 | 2173 | break; |
1da177e4 | 2174 | |
8b6e50c9 | 2175 | /* For subsequent reads align to page boundary */ |
1da177e4 LT |
2176 | col = 0; |
2177 | /* Increment page address */ | |
2178 | realpage++; | |
2179 | ||
ace4dfee | 2180 | page = realpage & chip->pagemask; |
1da177e4 LT |
2181 | /* Check, if we cross a chip boundary */ |
2182 | if (!page) { | |
2183 | chipnr++; | |
ace4dfee TG |
2184 | chip->select_chip(mtd, -1); |
2185 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 2186 | } |
1da177e4 | 2187 | } |
b0bb6903 | 2188 | chip->select_chip(mtd, -1); |
1da177e4 | 2189 | |
8593fbc6 | 2190 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
2191 | if (oob) |
2192 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 2193 | |
3f91e94f | 2194 | if (ret < 0) |
f5bbdacc TG |
2195 | return ret; |
2196 | ||
b72f3dfb | 2197 | if (ecc_fail) |
9a1fcdfd TG |
2198 | return -EBADMSG; |
2199 | ||
edbc4540 | 2200 | return max_bitflips; |
f5bbdacc TG |
2201 | } |
2202 | ||
2203 | /** | |
25985edc | 2204 | * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc |
8b6e50c9 BN |
2205 | * @mtd: MTD device structure |
2206 | * @from: offset to read from | |
2207 | * @len: number of bytes to read | |
2208 | * @retlen: pointer to variable to store the number of read bytes | |
2209 | * @buf: the databuffer to put data | |
f5bbdacc | 2210 | * |
8b6e50c9 | 2211 | * Get hold of the chip and call nand_do_read. |
f5bbdacc TG |
2212 | */ |
2213 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
2214 | size_t *retlen, uint8_t *buf) | |
2215 | { | |
4a89ff88 | 2216 | struct mtd_oob_ops ops; |
f5bbdacc TG |
2217 | int ret; |
2218 | ||
6a8214aa | 2219 | nand_get_device(mtd, FL_READING); |
0ec56dc4 | 2220 | memset(&ops, 0, sizeof(ops)); |
4a89ff88 BN |
2221 | ops.len = len; |
2222 | ops.datbuf = buf; | |
11041ae6 | 2223 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 2224 | ret = nand_do_read_ops(mtd, from, &ops); |
4a89ff88 | 2225 | *retlen = ops.retlen; |
f5bbdacc | 2226 | nand_release_device(mtd); |
f5bbdacc | 2227 | return ret; |
1da177e4 LT |
2228 | } |
2229 | ||
7bc3312b | 2230 | /** |
7854d3f7 | 2231 | * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function |
8b6e50c9 BN |
2232 | * @mtd: mtd info structure |
2233 | * @chip: nand chip info structure | |
2234 | * @page: page number to read | |
7bc3312b | 2235 | */ |
9d02fc2a | 2236 | int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page) |
7bc3312b | 2237 | { |
5c2ffb11 | 2238 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); |
7bc3312b | 2239 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
5c2ffb11 | 2240 | return 0; |
7bc3312b | 2241 | } |
9d02fc2a | 2242 | EXPORT_SYMBOL(nand_read_oob_std); |
7bc3312b TG |
2243 | |
2244 | /** | |
7854d3f7 | 2245 | * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC |
7bc3312b | 2246 | * with syndromes |
8b6e50c9 BN |
2247 | * @mtd: mtd info structure |
2248 | * @chip: nand chip info structure | |
2249 | * @page: page number to read | |
7bc3312b | 2250 | */ |
9d02fc2a BB |
2251 | int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, |
2252 | int page) | |
7bc3312b | 2253 | { |
7bc3312b TG |
2254 | int length = mtd->oobsize; |
2255 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
2256 | int eccsize = chip->ecc.size; | |
2ea69d21 | 2257 | uint8_t *bufpoi = chip->oob_poi; |
7bc3312b TG |
2258 | int i, toread, sndrnd = 0, pos; |
2259 | ||
2260 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
2261 | for (i = 0; i < chip->ecc.steps; i++) { | |
2262 | if (sndrnd) { | |
2263 | pos = eccsize + i * (eccsize + chunk); | |
2264 | if (mtd->writesize > 512) | |
2265 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
2266 | else | |
2267 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
2268 | } else | |
2269 | sndrnd = 1; | |
2270 | toread = min_t(int, length, chunk); | |
2271 | chip->read_buf(mtd, bufpoi, toread); | |
2272 | bufpoi += toread; | |
2273 | length -= toread; | |
2274 | } | |
2275 | if (length > 0) | |
2276 | chip->read_buf(mtd, bufpoi, length); | |
2277 | ||
5c2ffb11 | 2278 | return 0; |
7bc3312b | 2279 | } |
9d02fc2a | 2280 | EXPORT_SYMBOL(nand_read_oob_syndrome); |
7bc3312b TG |
2281 | |
2282 | /** | |
7854d3f7 | 2283 | * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function |
8b6e50c9 BN |
2284 | * @mtd: mtd info structure |
2285 | * @chip: nand chip info structure | |
2286 | * @page: page number to write | |
7bc3312b | 2287 | */ |
9d02fc2a | 2288 | int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page) |
7bc3312b TG |
2289 | { |
2290 | int status = 0; | |
2291 | const uint8_t *buf = chip->oob_poi; | |
2292 | int length = mtd->oobsize; | |
2293 | ||
2294 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
2295 | chip->write_buf(mtd, buf, length); | |
2296 | /* Send command to program the OOB data */ | |
2297 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
2298 | ||
2299 | status = chip->waitfunc(mtd, chip); | |
2300 | ||
0d420f9d | 2301 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b | 2302 | } |
9d02fc2a | 2303 | EXPORT_SYMBOL(nand_write_oob_std); |
7bc3312b TG |
2304 | |
2305 | /** | |
7854d3f7 | 2306 | * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC |
8b6e50c9 BN |
2307 | * with syndrome - only for large page flash |
2308 | * @mtd: mtd info structure | |
2309 | * @chip: nand chip info structure | |
2310 | * @page: page number to write | |
7bc3312b | 2311 | */ |
9d02fc2a BB |
2312 | int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, |
2313 | int page) | |
7bc3312b TG |
2314 | { |
2315 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
2316 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
2317 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
2318 | const uint8_t *bufpoi = chip->oob_poi; | |
2319 | ||
2320 | /* | |
2321 | * data-ecc-data-ecc ... ecc-oob | |
2322 | * or | |
2323 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
2324 | */ | |
2325 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
2326 | pos = steps * (eccsize + chunk); | |
2327 | steps = 0; | |
2328 | } else | |
8b0036ee | 2329 | pos = eccsize; |
7bc3312b TG |
2330 | |
2331 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
2332 | for (i = 0; i < steps; i++) { | |
2333 | if (sndcmd) { | |
2334 | if (mtd->writesize <= 512) { | |
2335 | uint32_t fill = 0xFFFFFFFF; | |
2336 | ||
2337 | len = eccsize; | |
2338 | while (len > 0) { | |
2339 | int num = min_t(int, len, 4); | |
2340 | chip->write_buf(mtd, (uint8_t *)&fill, | |
2341 | num); | |
2342 | len -= num; | |
2343 | } | |
2344 | } else { | |
2345 | pos = eccsize + i * (eccsize + chunk); | |
2346 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
2347 | } | |
2348 | } else | |
2349 | sndcmd = 1; | |
2350 | len = min_t(int, length, chunk); | |
2351 | chip->write_buf(mtd, bufpoi, len); | |
2352 | bufpoi += len; | |
2353 | length -= len; | |
2354 | } | |
2355 | if (length > 0) | |
2356 | chip->write_buf(mtd, bufpoi, length); | |
2357 | ||
2358 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
2359 | status = chip->waitfunc(mtd, chip); | |
2360 | ||
2361 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
2362 | } | |
9d02fc2a | 2363 | EXPORT_SYMBOL(nand_write_oob_syndrome); |
7bc3312b | 2364 | |
1da177e4 | 2365 | /** |
7854d3f7 | 2366 | * nand_do_read_oob - [INTERN] NAND read out-of-band |
8b6e50c9 BN |
2367 | * @mtd: MTD device structure |
2368 | * @from: offset to read from | |
2369 | * @ops: oob operations description structure | |
1da177e4 | 2370 | * |
8b6e50c9 | 2371 | * NAND read out-of-band data from the spare area. |
1da177e4 | 2372 | */ |
8593fbc6 TG |
2373 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
2374 | struct mtd_oob_ops *ops) | |
1da177e4 | 2375 | { |
c00a0991 | 2376 | int page, realpage, chipnr; |
862eba51 | 2377 | struct nand_chip *chip = mtd_to_nand(mtd); |
041e4575 | 2378 | struct mtd_ecc_stats stats; |
7014568b VW |
2379 | int readlen = ops->ooblen; |
2380 | int len; | |
7bc3312b | 2381 | uint8_t *buf = ops->oobbuf; |
1951f2f7 | 2382 | int ret = 0; |
61b03bd7 | 2383 | |
289c0522 | 2384 | pr_debug("%s: from = 0x%08Lx, len = %i\n", |
20d8e248 | 2385 | __func__, (unsigned long long)from, readlen); |
1da177e4 | 2386 | |
041e4575 BN |
2387 | stats = mtd->ecc_stats; |
2388 | ||
29f1058a | 2389 | len = mtd_oobavail(mtd, ops); |
03736155 AH |
2390 | |
2391 | if (unlikely(ops->ooboffs >= len)) { | |
289c0522 BN |
2392 | pr_debug("%s: attempt to start read outside oob\n", |
2393 | __func__); | |
03736155 AH |
2394 | return -EINVAL; |
2395 | } | |
2396 | ||
2397 | /* Do not allow reads past end of device */ | |
2398 | if (unlikely(from >= mtd->size || | |
2399 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
2400 | (from >> chip->page_shift)) * len)) { | |
289c0522 BN |
2401 | pr_debug("%s: attempt to read beyond end of device\n", |
2402 | __func__); | |
03736155 AH |
2403 | return -EINVAL; |
2404 | } | |
7014568b | 2405 | |
7314e9e7 | 2406 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 2407 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2408 | |
7314e9e7 TG |
2409 | /* Shift to get page */ |
2410 | realpage = (int)(from >> chip->page_shift); | |
2411 | page = realpage & chip->pagemask; | |
1da177e4 | 2412 | |
f8ac0414 | 2413 | while (1) { |
0612b9dd | 2414 | if (ops->mode == MTD_OPS_RAW) |
1951f2f7 | 2415 | ret = chip->ecc.read_oob_raw(mtd, chip, page); |
c46f6483 | 2416 | else |
1951f2f7 SL |
2417 | ret = chip->ecc.read_oob(mtd, chip, page); |
2418 | ||
2419 | if (ret < 0) | |
2420 | break; | |
7014568b VW |
2421 | |
2422 | len = min(len, readlen); | |
846031d3 | 2423 | buf = nand_transfer_oob(mtd, buf, ops, len); |
8593fbc6 | 2424 | |
5bc7c33c BN |
2425 | if (chip->options & NAND_NEED_READRDY) { |
2426 | /* Apply delay or wait for ready/busy pin */ | |
2427 | if (!chip->dev_ready) | |
2428 | udelay(chip->chip_delay); | |
2429 | else | |
2430 | nand_wait_ready(mtd); | |
2431 | } | |
2432 | ||
7014568b | 2433 | readlen -= len; |
0d420f9d SZ |
2434 | if (!readlen) |
2435 | break; | |
2436 | ||
7314e9e7 TG |
2437 | /* Increment page address */ |
2438 | realpage++; | |
2439 | ||
2440 | page = realpage & chip->pagemask; | |
2441 | /* Check, if we cross a chip boundary */ | |
2442 | if (!page) { | |
2443 | chipnr++; | |
2444 | chip->select_chip(mtd, -1); | |
2445 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2446 | } |
2447 | } | |
b0bb6903 | 2448 | chip->select_chip(mtd, -1); |
1da177e4 | 2449 | |
1951f2f7 SL |
2450 | ops->oobretlen = ops->ooblen - readlen; |
2451 | ||
2452 | if (ret < 0) | |
2453 | return ret; | |
041e4575 BN |
2454 | |
2455 | if (mtd->ecc_stats.failed - stats.failed) | |
2456 | return -EBADMSG; | |
2457 | ||
2458 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
1da177e4 LT |
2459 | } |
2460 | ||
2461 | /** | |
8593fbc6 | 2462 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
8b6e50c9 BN |
2463 | * @mtd: MTD device structure |
2464 | * @from: offset to read from | |
2465 | * @ops: oob operation description structure | |
1da177e4 | 2466 | * |
8b6e50c9 | 2467 | * NAND read data and/or out-of-band data. |
1da177e4 | 2468 | */ |
8593fbc6 TG |
2469 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
2470 | struct mtd_oob_ops *ops) | |
1da177e4 | 2471 | { |
fc6b4d12 | 2472 | int ret; |
8593fbc6 TG |
2473 | |
2474 | ops->retlen = 0; | |
1da177e4 LT |
2475 | |
2476 | /* Do not allow reads past end of device */ | |
7014568b | 2477 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
289c0522 BN |
2478 | pr_debug("%s: attempt to read beyond end of device\n", |
2479 | __func__); | |
1da177e4 LT |
2480 | return -EINVAL; |
2481 | } | |
2482 | ||
fc6b4d12 AS |
2483 | if (ops->mode != MTD_OPS_PLACE_OOB && |
2484 | ops->mode != MTD_OPS_AUTO_OOB && | |
2485 | ops->mode != MTD_OPS_RAW) | |
2486 | return -ENOTSUPP; | |
1da177e4 | 2487 | |
fc6b4d12 | 2488 | nand_get_device(mtd, FL_READING); |
1da177e4 | 2489 | |
8593fbc6 TG |
2490 | if (!ops->datbuf) |
2491 | ret = nand_do_read_oob(mtd, from, ops); | |
2492 | else | |
2493 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 2494 | |
8593fbc6 TG |
2495 | nand_release_device(mtd); |
2496 | return ret; | |
2497 | } | |
61b03bd7 | 2498 | |
1da177e4 | 2499 | |
8593fbc6 | 2500 | /** |
7854d3f7 | 2501 | * nand_write_page_raw - [INTERN] raw page write function |
8b6e50c9 BN |
2502 | * @mtd: mtd info structure |
2503 | * @chip: nand chip info structure | |
2504 | * @buf: data buffer | |
1fbb938d | 2505 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2506 | * @page: page number to write |
52ff49df | 2507 | * |
7854d3f7 | 2508 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 | 2509 | */ |
cc0f51ec TP |
2510 | int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
2511 | const uint8_t *buf, int oob_required, int page) | |
8593fbc6 TG |
2512 | { |
2513 | chip->write_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
2514 | if (oob_required) |
2515 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
2516 | |
2517 | return 0; | |
1da177e4 | 2518 | } |
cc0f51ec | 2519 | EXPORT_SYMBOL(nand_write_page_raw); |
1da177e4 | 2520 | |
52ff49df | 2521 | /** |
7854d3f7 | 2522 | * nand_write_page_raw_syndrome - [INTERN] raw page write function |
8b6e50c9 BN |
2523 | * @mtd: mtd info structure |
2524 | * @chip: nand chip info structure | |
2525 | * @buf: data buffer | |
1fbb938d | 2526 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2527 | * @page: page number to write |
52ff49df DB |
2528 | * |
2529 | * We need a special oob layout and handling even when ECC isn't checked. | |
2530 | */ | |
fdbad98d | 2531 | static int nand_write_page_raw_syndrome(struct mtd_info *mtd, |
7351d3a5 | 2532 | struct nand_chip *chip, |
45aaeff9 BB |
2533 | const uint8_t *buf, int oob_required, |
2534 | int page) | |
52ff49df DB |
2535 | { |
2536 | int eccsize = chip->ecc.size; | |
2537 | int eccbytes = chip->ecc.bytes; | |
2538 | uint8_t *oob = chip->oob_poi; | |
2539 | int steps, size; | |
2540 | ||
2541 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
2542 | chip->write_buf(mtd, buf, eccsize); | |
2543 | buf += eccsize; | |
2544 | ||
2545 | if (chip->ecc.prepad) { | |
2546 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2547 | oob += chip->ecc.prepad; | |
2548 | } | |
2549 | ||
60c3bc1f | 2550 | chip->write_buf(mtd, oob, eccbytes); |
52ff49df DB |
2551 | oob += eccbytes; |
2552 | ||
2553 | if (chip->ecc.postpad) { | |
2554 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2555 | oob += chip->ecc.postpad; | |
2556 | } | |
2557 | } | |
2558 | ||
2559 | size = mtd->oobsize - (oob - chip->oob_poi); | |
2560 | if (size) | |
2561 | chip->write_buf(mtd, oob, size); | |
fdbad98d JW |
2562 | |
2563 | return 0; | |
52ff49df | 2564 | } |
9223a456 | 2565 | /** |
7854d3f7 | 2566 | * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function |
8b6e50c9 BN |
2567 | * @mtd: mtd info structure |
2568 | * @chip: nand chip info structure | |
2569 | * @buf: data buffer | |
1fbb938d | 2570 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2571 | * @page: page number to write |
9223a456 | 2572 | */ |
fdbad98d | 2573 | static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 BB |
2574 | const uint8_t *buf, int oob_required, |
2575 | int page) | |
9223a456 | 2576 | { |
846031d3 | 2577 | int i, eccsize = chip->ecc.size, ret; |
f75e5097 TG |
2578 | int eccbytes = chip->ecc.bytes; |
2579 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2580 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2581 | const uint8_t *p = buf; |
9223a456 | 2582 | |
7854d3f7 | 2583 | /* Software ECC calculation */ |
8593fbc6 TG |
2584 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
2585 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 2586 | |
846031d3 BB |
2587 | ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, |
2588 | chip->ecc.total); | |
2589 | if (ret) | |
2590 | return ret; | |
9223a456 | 2591 | |
45aaeff9 | 2592 | return chip->ecc.write_page_raw(mtd, chip, buf, 1, page); |
f75e5097 | 2593 | } |
9223a456 | 2594 | |
f75e5097 | 2595 | /** |
7854d3f7 | 2596 | * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function |
8b6e50c9 BN |
2597 | * @mtd: mtd info structure |
2598 | * @chip: nand chip info structure | |
2599 | * @buf: data buffer | |
1fbb938d | 2600 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2601 | * @page: page number to write |
f75e5097 | 2602 | */ |
fdbad98d | 2603 | static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 BB |
2604 | const uint8_t *buf, int oob_required, |
2605 | int page) | |
f75e5097 | 2606 | { |
846031d3 | 2607 | int i, eccsize = chip->ecc.size, ret; |
f75e5097 TG |
2608 | int eccbytes = chip->ecc.bytes; |
2609 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2610 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2611 | const uint8_t *p = buf; |
9223a456 | 2612 | |
f75e5097 TG |
2613 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
2614 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 2615 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 2616 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
2617 | } |
2618 | ||
846031d3 BB |
2619 | ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, |
2620 | chip->ecc.total); | |
2621 | if (ret) | |
2622 | return ret; | |
f75e5097 TG |
2623 | |
2624 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
2625 | |
2626 | return 0; | |
9223a456 TG |
2627 | } |
2628 | ||
837a6ba4 GP |
2629 | |
2630 | /** | |
73c8aaf4 | 2631 | * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write |
837a6ba4 GP |
2632 | * @mtd: mtd info structure |
2633 | * @chip: nand chip info structure | |
d6a95080 | 2634 | * @offset: column address of subpage within the page |
837a6ba4 | 2635 | * @data_len: data length |
d6a95080 | 2636 | * @buf: data buffer |
837a6ba4 | 2637 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2638 | * @page: page number to write |
837a6ba4 GP |
2639 | */ |
2640 | static int nand_write_subpage_hwecc(struct mtd_info *mtd, | |
2641 | struct nand_chip *chip, uint32_t offset, | |
d6a95080 | 2642 | uint32_t data_len, const uint8_t *buf, |
45aaeff9 | 2643 | int oob_required, int page) |
837a6ba4 GP |
2644 | { |
2645 | uint8_t *oob_buf = chip->oob_poi; | |
2646 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
2647 | int ecc_size = chip->ecc.size; | |
2648 | int ecc_bytes = chip->ecc.bytes; | |
2649 | int ecc_steps = chip->ecc.steps; | |
837a6ba4 GP |
2650 | uint32_t start_step = offset / ecc_size; |
2651 | uint32_t end_step = (offset + data_len - 1) / ecc_size; | |
2652 | int oob_bytes = mtd->oobsize / ecc_steps; | |
846031d3 | 2653 | int step, ret; |
837a6ba4 GP |
2654 | |
2655 | for (step = 0; step < ecc_steps; step++) { | |
2656 | /* configure controller for WRITE access */ | |
2657 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
2658 | ||
2659 | /* write data (untouched subpages already masked by 0xFF) */ | |
d6a95080 | 2660 | chip->write_buf(mtd, buf, ecc_size); |
837a6ba4 GP |
2661 | |
2662 | /* mask ECC of un-touched subpages by padding 0xFF */ | |
2663 | if ((step < start_step) || (step > end_step)) | |
2664 | memset(ecc_calc, 0xff, ecc_bytes); | |
2665 | else | |
d6a95080 | 2666 | chip->ecc.calculate(mtd, buf, ecc_calc); |
837a6ba4 GP |
2667 | |
2668 | /* mask OOB of un-touched subpages by padding 0xFF */ | |
2669 | /* if oob_required, preserve OOB metadata of written subpage */ | |
2670 | if (!oob_required || (step < start_step) || (step > end_step)) | |
2671 | memset(oob_buf, 0xff, oob_bytes); | |
2672 | ||
d6a95080 | 2673 | buf += ecc_size; |
837a6ba4 GP |
2674 | ecc_calc += ecc_bytes; |
2675 | oob_buf += oob_bytes; | |
2676 | } | |
2677 | ||
2678 | /* copy calculated ECC for whole page to chip->buffer->oob */ | |
2679 | /* this include masked-value(0xFF) for unwritten subpages */ | |
2680 | ecc_calc = chip->buffers->ecccalc; | |
846031d3 BB |
2681 | ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, |
2682 | chip->ecc.total); | |
2683 | if (ret) | |
2684 | return ret; | |
837a6ba4 GP |
2685 | |
2686 | /* write OOB buffer to NAND device */ | |
2687 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
2688 | ||
2689 | return 0; | |
2690 | } | |
2691 | ||
2692 | ||
61b03bd7 | 2693 | /** |
7854d3f7 | 2694 | * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write |
8b6e50c9 BN |
2695 | * @mtd: mtd info structure |
2696 | * @chip: nand chip info structure | |
2697 | * @buf: data buffer | |
1fbb938d | 2698 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2699 | * @page: page number to write |
1da177e4 | 2700 | * |
8b6e50c9 BN |
2701 | * The hw generator calculates the error syndrome automatically. Therefore we |
2702 | * need a special oob layout and handling. | |
f75e5097 | 2703 | */ |
fdbad98d | 2704 | static int nand_write_page_syndrome(struct mtd_info *mtd, |
1fbb938d | 2705 | struct nand_chip *chip, |
45aaeff9 BB |
2706 | const uint8_t *buf, int oob_required, |
2707 | int page) | |
1da177e4 | 2708 | { |
f75e5097 TG |
2709 | int i, eccsize = chip->ecc.size; |
2710 | int eccbytes = chip->ecc.bytes; | |
2711 | int eccsteps = chip->ecc.steps; | |
2712 | const uint8_t *p = buf; | |
2713 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 2714 | |
f75e5097 | 2715 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 2716 | |
f75e5097 TG |
2717 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
2718 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 2719 | |
f75e5097 TG |
2720 | if (chip->ecc.prepad) { |
2721 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2722 | oob += chip->ecc.prepad; | |
2723 | } | |
2724 | ||
2725 | chip->ecc.calculate(mtd, p, oob); | |
2726 | chip->write_buf(mtd, oob, eccbytes); | |
2727 | oob += eccbytes; | |
2728 | ||
2729 | if (chip->ecc.postpad) { | |
2730 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2731 | oob += chip->ecc.postpad; | |
1da177e4 | 2732 | } |
1da177e4 | 2733 | } |
f75e5097 TG |
2734 | |
2735 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 2736 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
2737 | if (i) |
2738 | chip->write_buf(mtd, oob, i); | |
fdbad98d JW |
2739 | |
2740 | return 0; | |
f75e5097 TG |
2741 | } |
2742 | ||
2743 | /** | |
f107d7a4 | 2744 | * nand_write_page - write one page |
8b6e50c9 BN |
2745 | * @mtd: MTD device structure |
2746 | * @chip: NAND chip descriptor | |
837a6ba4 GP |
2747 | * @offset: address offset within the page |
2748 | * @data_len: length of actual data to be written | |
8b6e50c9 | 2749 | * @buf: the data to write |
1fbb938d | 2750 | * @oob_required: must write chip->oob_poi to OOB |
8b6e50c9 | 2751 | * @page: page number to write |
8b6e50c9 | 2752 | * @raw: use _raw version of write_page |
f75e5097 TG |
2753 | */ |
2754 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
837a6ba4 | 2755 | uint32_t offset, int data_len, const uint8_t *buf, |
0b4773fd | 2756 | int oob_required, int page, int raw) |
f75e5097 | 2757 | { |
837a6ba4 GP |
2758 | int status, subpage; |
2759 | ||
2760 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && | |
2761 | chip->ecc.write_subpage) | |
2762 | subpage = offset || (data_len < mtd->writesize); | |
2763 | else | |
2764 | subpage = 0; | |
f75e5097 | 2765 | |
3371d663 MG |
2766 | if (nand_standard_page_accessors(&chip->ecc)) |
2767 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
f75e5097 | 2768 | |
956e944c | 2769 | if (unlikely(raw)) |
837a6ba4 | 2770 | status = chip->ecc.write_page_raw(mtd, chip, buf, |
45aaeff9 | 2771 | oob_required, page); |
837a6ba4 GP |
2772 | else if (subpage) |
2773 | status = chip->ecc.write_subpage(mtd, chip, offset, data_len, | |
45aaeff9 | 2774 | buf, oob_required, page); |
956e944c | 2775 | else |
45aaeff9 BB |
2776 | status = chip->ecc.write_page(mtd, chip, buf, oob_required, |
2777 | page); | |
fdbad98d JW |
2778 | |
2779 | if (status < 0) | |
2780 | return status; | |
f75e5097 | 2781 | |
41145649 | 2782 | if (nand_standard_page_accessors(&chip->ecc)) { |
0b4773fd | 2783 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); |
f75e5097 | 2784 | |
7bc3312b | 2785 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2786 | if (status & NAND_STATUS_FAIL) |
2787 | return -EIO; | |
f75e5097 TG |
2788 | } |
2789 | ||
f75e5097 | 2790 | return 0; |
1da177e4 LT |
2791 | } |
2792 | ||
8593fbc6 | 2793 | /** |
7854d3f7 | 2794 | * nand_fill_oob - [INTERN] Transfer client buffer to oob |
f722013e | 2795 | * @mtd: MTD device structure |
8b6e50c9 BN |
2796 | * @oob: oob data buffer |
2797 | * @len: oob data write length | |
2798 | * @ops: oob ops structure | |
8593fbc6 | 2799 | */ |
f722013e TAA |
2800 | static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, |
2801 | struct mtd_oob_ops *ops) | |
8593fbc6 | 2802 | { |
862eba51 | 2803 | struct nand_chip *chip = mtd_to_nand(mtd); |
846031d3 | 2804 | int ret; |
f722013e TAA |
2805 | |
2806 | /* | |
2807 | * Initialise to all 0xFF, to avoid the possibility of left over OOB | |
2808 | * data from a previous OOB read. | |
2809 | */ | |
2810 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
2811 | ||
f8ac0414 | 2812 | switch (ops->mode) { |
8593fbc6 | 2813 | |
0612b9dd BN |
2814 | case MTD_OPS_PLACE_OOB: |
2815 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2816 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); |
2817 | return oob + len; | |
2818 | ||
846031d3 BB |
2819 | case MTD_OPS_AUTO_OOB: |
2820 | ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi, | |
2821 | ops->ooboffs, len); | |
2822 | BUG_ON(ret); | |
2823 | return oob + len; | |
2824 | ||
8593fbc6 TG |
2825 | default: |
2826 | BUG(); | |
2827 | } | |
2828 | return NULL; | |
2829 | } | |
2830 | ||
f8ac0414 | 2831 | #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) |
1da177e4 LT |
2832 | |
2833 | /** | |
7854d3f7 | 2834 | * nand_do_write_ops - [INTERN] NAND write with ECC |
8b6e50c9 BN |
2835 | * @mtd: MTD device structure |
2836 | * @to: offset to write to | |
2837 | * @ops: oob operations description structure | |
1da177e4 | 2838 | * |
8b6e50c9 | 2839 | * NAND write with ECC. |
1da177e4 | 2840 | */ |
8593fbc6 TG |
2841 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
2842 | struct mtd_oob_ops *ops) | |
1da177e4 | 2843 | { |
29072b96 | 2844 | int chipnr, realpage, page, blockmask, column; |
862eba51 | 2845 | struct nand_chip *chip = mtd_to_nand(mtd); |
8593fbc6 | 2846 | uint32_t writelen = ops->len; |
782ce79a ML |
2847 | |
2848 | uint32_t oobwritelen = ops->ooblen; | |
29f1058a | 2849 | uint32_t oobmaxlen = mtd_oobavail(mtd, ops); |
782ce79a | 2850 | |
8593fbc6 TG |
2851 | uint8_t *oob = ops->oobbuf; |
2852 | uint8_t *buf = ops->datbuf; | |
837a6ba4 | 2853 | int ret; |
e47f3db4 | 2854 | int oob_required = oob ? 1 : 0; |
1da177e4 | 2855 | |
8593fbc6 | 2856 | ops->retlen = 0; |
29072b96 TG |
2857 | if (!writelen) |
2858 | return 0; | |
1da177e4 | 2859 | |
8b6e50c9 | 2860 | /* Reject writes, which are not page aligned */ |
8593fbc6 | 2861 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
d0370219 BN |
2862 | pr_notice("%s: attempt to write non page aligned data\n", |
2863 | __func__); | |
1da177e4 LT |
2864 | return -EINVAL; |
2865 | } | |
2866 | ||
29072b96 | 2867 | column = to & (mtd->writesize - 1); |
1da177e4 | 2868 | |
6a930961 TG |
2869 | chipnr = (int)(to >> chip->chip_shift); |
2870 | chip->select_chip(mtd, chipnr); | |
2871 | ||
1da177e4 | 2872 | /* Check, if it is write protected */ |
b0bb6903 HS |
2873 | if (nand_check_wp(mtd)) { |
2874 | ret = -EIO; | |
2875 | goto err_out; | |
2876 | } | |
1da177e4 | 2877 | |
f75e5097 TG |
2878 | realpage = (int)(to >> chip->page_shift); |
2879 | page = realpage & chip->pagemask; | |
2880 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
2881 | ||
2882 | /* Invalidate the page cache, when we write to the cached page */ | |
537ab1bd BN |
2883 | if (to <= ((loff_t)chip->pagebuf << chip->page_shift) && |
2884 | ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len)) | |
ace4dfee | 2885 | chip->pagebuf = -1; |
61b03bd7 | 2886 | |
782ce79a | 2887 | /* Don't allow multipage oob writes with offset */ |
b0bb6903 HS |
2888 | if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { |
2889 | ret = -EINVAL; | |
2890 | goto err_out; | |
2891 | } | |
782ce79a | 2892 | |
f8ac0414 | 2893 | while (1) { |
29072b96 | 2894 | int bytes = mtd->writesize; |
29072b96 | 2895 | uint8_t *wbuf = buf; |
66507c7b | 2896 | int use_bufpoi; |
144f4c98 | 2897 | int part_pagewr = (column || writelen < mtd->writesize); |
66507c7b KD |
2898 | |
2899 | if (part_pagewr) | |
2900 | use_bufpoi = 1; | |
2901 | else if (chip->options & NAND_USE_BOUNCE_BUFFER) | |
477544c6 MY |
2902 | use_bufpoi = !virt_addr_valid(buf) || |
2903 | !IS_ALIGNED((unsigned long)buf, | |
2904 | chip->buf_align); | |
66507c7b KD |
2905 | else |
2906 | use_bufpoi = 0; | |
29072b96 | 2907 | |
66507c7b KD |
2908 | /* Partial page write?, or need to use bounce buffer */ |
2909 | if (use_bufpoi) { | |
2910 | pr_debug("%s: using write bounce buffer for buf@%p\n", | |
2911 | __func__, buf); | |
66507c7b KD |
2912 | if (part_pagewr) |
2913 | bytes = min_t(int, bytes - column, writelen); | |
29072b96 TG |
2914 | chip->pagebuf = -1; |
2915 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
2916 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
2917 | wbuf = chip->buffers->databuf; | |
2918 | } | |
1da177e4 | 2919 | |
782ce79a ML |
2920 | if (unlikely(oob)) { |
2921 | size_t len = min(oobwritelen, oobmaxlen); | |
f722013e | 2922 | oob = nand_fill_oob(mtd, oob, len, ops); |
782ce79a | 2923 | oobwritelen -= len; |
f722013e TAA |
2924 | } else { |
2925 | /* We still need to erase leftover OOB data */ | |
2926 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
782ce79a | 2927 | } |
f107d7a4 BB |
2928 | |
2929 | ret = nand_write_page(mtd, chip, column, bytes, wbuf, | |
0b4773fd | 2930 | oob_required, page, |
f107d7a4 | 2931 | (ops->mode == MTD_OPS_RAW)); |
f75e5097 TG |
2932 | if (ret) |
2933 | break; | |
2934 | ||
2935 | writelen -= bytes; | |
2936 | if (!writelen) | |
2937 | break; | |
2938 | ||
29072b96 | 2939 | column = 0; |
f75e5097 TG |
2940 | buf += bytes; |
2941 | realpage++; | |
2942 | ||
2943 | page = realpage & chip->pagemask; | |
2944 | /* Check, if we cross a chip boundary */ | |
2945 | if (!page) { | |
2946 | chipnr++; | |
2947 | chip->select_chip(mtd, -1); | |
2948 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2949 | } |
2950 | } | |
8593fbc6 | 2951 | |
8593fbc6 | 2952 | ops->retlen = ops->len - writelen; |
7014568b VW |
2953 | if (unlikely(oob)) |
2954 | ops->oobretlen = ops->ooblen; | |
b0bb6903 HS |
2955 | |
2956 | err_out: | |
2957 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
2958 | return ret; |
2959 | } | |
2960 | ||
2af7c653 SK |
2961 | /** |
2962 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
8b6e50c9 BN |
2963 | * @mtd: MTD device structure |
2964 | * @to: offset to write to | |
2965 | * @len: number of bytes to write | |
2966 | * @retlen: pointer to variable to store the number of written bytes | |
2967 | * @buf: the data to write | |
2af7c653 SK |
2968 | * |
2969 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
2970 | * may for example be called by mtdoops when writing an oops while in panic. | |
2971 | */ | |
2972 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
2973 | size_t *retlen, const uint8_t *buf) | |
2974 | { | |
862eba51 | 2975 | struct nand_chip *chip = mtd_to_nand(mtd); |
4a89ff88 | 2976 | struct mtd_oob_ops ops; |
2af7c653 SK |
2977 | int ret; |
2978 | ||
8b6e50c9 | 2979 | /* Wait for the device to get ready */ |
2af7c653 SK |
2980 | panic_nand_wait(mtd, chip, 400); |
2981 | ||
8b6e50c9 | 2982 | /* Grab the device */ |
2af7c653 SK |
2983 | panic_nand_get_device(chip, mtd, FL_WRITING); |
2984 | ||
0ec56dc4 | 2985 | memset(&ops, 0, sizeof(ops)); |
4a89ff88 BN |
2986 | ops.len = len; |
2987 | ops.datbuf = (uint8_t *)buf; | |
11041ae6 | 2988 | ops.mode = MTD_OPS_PLACE_OOB; |
2af7c653 | 2989 | |
4a89ff88 | 2990 | ret = nand_do_write_ops(mtd, to, &ops); |
2af7c653 | 2991 | |
4a89ff88 | 2992 | *retlen = ops.retlen; |
2af7c653 SK |
2993 | return ret; |
2994 | } | |
2995 | ||
f75e5097 | 2996 | /** |
8593fbc6 | 2997 | * nand_write - [MTD Interface] NAND write with ECC |
8b6e50c9 BN |
2998 | * @mtd: MTD device structure |
2999 | * @to: offset to write to | |
3000 | * @len: number of bytes to write | |
3001 | * @retlen: pointer to variable to store the number of written bytes | |
3002 | * @buf: the data to write | |
f75e5097 | 3003 | * |
8b6e50c9 | 3004 | * NAND write with ECC. |
f75e5097 | 3005 | */ |
8593fbc6 TG |
3006 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
3007 | size_t *retlen, const uint8_t *buf) | |
f75e5097 | 3008 | { |
4a89ff88 | 3009 | struct mtd_oob_ops ops; |
f75e5097 TG |
3010 | int ret; |
3011 | ||
6a8214aa | 3012 | nand_get_device(mtd, FL_WRITING); |
0ec56dc4 | 3013 | memset(&ops, 0, sizeof(ops)); |
4a89ff88 BN |
3014 | ops.len = len; |
3015 | ops.datbuf = (uint8_t *)buf; | |
11041ae6 | 3016 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 3017 | ret = nand_do_write_ops(mtd, to, &ops); |
4a89ff88 | 3018 | *retlen = ops.retlen; |
f75e5097 | 3019 | nand_release_device(mtd); |
8593fbc6 | 3020 | return ret; |
f75e5097 | 3021 | } |
7314e9e7 | 3022 | |
1da177e4 | 3023 | /** |
8593fbc6 | 3024 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
8b6e50c9 BN |
3025 | * @mtd: MTD device structure |
3026 | * @to: offset to write to | |
3027 | * @ops: oob operation description structure | |
1da177e4 | 3028 | * |
8b6e50c9 | 3029 | * NAND write out-of-band. |
1da177e4 | 3030 | */ |
8593fbc6 TG |
3031 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
3032 | struct mtd_oob_ops *ops) | |
1da177e4 | 3033 | { |
03736155 | 3034 | int chipnr, page, status, len; |
862eba51 | 3035 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 3036 | |
289c0522 | 3037 | pr_debug("%s: to = 0x%08x, len = %i\n", |
20d8e248 | 3038 | __func__, (unsigned int)to, (int)ops->ooblen); |
1da177e4 | 3039 | |
29f1058a | 3040 | len = mtd_oobavail(mtd, ops); |
03736155 | 3041 | |
1da177e4 | 3042 | /* Do not allow write past end of page */ |
03736155 | 3043 | if ((ops->ooboffs + ops->ooblen) > len) { |
289c0522 BN |
3044 | pr_debug("%s: attempt to write past end of page\n", |
3045 | __func__); | |
1da177e4 LT |
3046 | return -EINVAL; |
3047 | } | |
3048 | ||
03736155 | 3049 | if (unlikely(ops->ooboffs >= len)) { |
289c0522 BN |
3050 | pr_debug("%s: attempt to start write outside oob\n", |
3051 | __func__); | |
03736155 AH |
3052 | return -EINVAL; |
3053 | } | |
3054 | ||
775adc3d | 3055 | /* Do not allow write past end of device */ |
03736155 AH |
3056 | if (unlikely(to >= mtd->size || |
3057 | ops->ooboffs + ops->ooblen > | |
3058 | ((mtd->size >> chip->page_shift) - | |
3059 | (to >> chip->page_shift)) * len)) { | |
289c0522 BN |
3060 | pr_debug("%s: attempt to write beyond end of device\n", |
3061 | __func__); | |
03736155 AH |
3062 | return -EINVAL; |
3063 | } | |
3064 | ||
7314e9e7 | 3065 | chipnr = (int)(to >> chip->chip_shift); |
7314e9e7 TG |
3066 | |
3067 | /* | |
3068 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
3069 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
3070 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
3071 | * it in the doc2000 driver in August 1999. dwmw2. | |
3072 | */ | |
73f907fd BB |
3073 | nand_reset(chip, chipnr); |
3074 | ||
3075 | chip->select_chip(mtd, chipnr); | |
3076 | ||
3077 | /* Shift to get page */ | |
3078 | page = (int)(to >> chip->page_shift); | |
1da177e4 LT |
3079 | |
3080 | /* Check, if it is write protected */ | |
b0bb6903 HS |
3081 | if (nand_check_wp(mtd)) { |
3082 | chip->select_chip(mtd, -1); | |
8593fbc6 | 3083 | return -EROFS; |
b0bb6903 | 3084 | } |
61b03bd7 | 3085 | |
1da177e4 | 3086 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
3087 | if (page == chip->pagebuf) |
3088 | chip->pagebuf = -1; | |
1da177e4 | 3089 | |
f722013e | 3090 | nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops); |
9ce244b3 | 3091 | |
0612b9dd | 3092 | if (ops->mode == MTD_OPS_RAW) |
9ce244b3 BN |
3093 | status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask); |
3094 | else | |
3095 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); | |
1da177e4 | 3096 | |
b0bb6903 HS |
3097 | chip->select_chip(mtd, -1); |
3098 | ||
7bc3312b TG |
3099 | if (status) |
3100 | return status; | |
1da177e4 | 3101 | |
7014568b | 3102 | ops->oobretlen = ops->ooblen; |
1da177e4 | 3103 | |
7bc3312b | 3104 | return 0; |
8593fbc6 TG |
3105 | } |
3106 | ||
3107 | /** | |
3108 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
8b6e50c9 BN |
3109 | * @mtd: MTD device structure |
3110 | * @to: offset to write to | |
3111 | * @ops: oob operation description structure | |
8593fbc6 TG |
3112 | */ |
3113 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
3114 | struct mtd_oob_ops *ops) | |
3115 | { | |
8593fbc6 TG |
3116 | int ret = -ENOTSUPP; |
3117 | ||
3118 | ops->retlen = 0; | |
3119 | ||
3120 | /* Do not allow writes past end of device */ | |
7014568b | 3121 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
289c0522 BN |
3122 | pr_debug("%s: attempt to write beyond end of device\n", |
3123 | __func__); | |
8593fbc6 TG |
3124 | return -EINVAL; |
3125 | } | |
3126 | ||
6a8214aa | 3127 | nand_get_device(mtd, FL_WRITING); |
8593fbc6 | 3128 | |
f8ac0414 | 3129 | switch (ops->mode) { |
0612b9dd BN |
3130 | case MTD_OPS_PLACE_OOB: |
3131 | case MTD_OPS_AUTO_OOB: | |
3132 | case MTD_OPS_RAW: | |
8593fbc6 TG |
3133 | break; |
3134 | ||
3135 | default: | |
3136 | goto out; | |
3137 | } | |
3138 | ||
3139 | if (!ops->datbuf) | |
3140 | ret = nand_do_write_oob(mtd, to, ops); | |
3141 | else | |
3142 | ret = nand_do_write_ops(mtd, to, ops); | |
3143 | ||
7351d3a5 | 3144 | out: |
1da177e4 | 3145 | nand_release_device(mtd); |
1da177e4 LT |
3146 | return ret; |
3147 | } | |
3148 | ||
1da177e4 | 3149 | /** |
49c50b97 | 3150 | * single_erase - [GENERIC] NAND standard block erase command function |
8b6e50c9 BN |
3151 | * @mtd: MTD device structure |
3152 | * @page: the page address of the block which will be erased | |
1da177e4 | 3153 | * |
49c50b97 | 3154 | * Standard erase command for NAND chips. Returns NAND status. |
1da177e4 | 3155 | */ |
49c50b97 | 3156 | static int single_erase(struct mtd_info *mtd, int page) |
1da177e4 | 3157 | { |
862eba51 | 3158 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 3159 | /* Send commands to erase a block */ |
ace4dfee TG |
3160 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
3161 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
49c50b97 BN |
3162 | |
3163 | return chip->waitfunc(mtd, chip); | |
1da177e4 LT |
3164 | } |
3165 | ||
1da177e4 LT |
3166 | /** |
3167 | * nand_erase - [MTD Interface] erase block(s) | |
8b6e50c9 BN |
3168 | * @mtd: MTD device structure |
3169 | * @instr: erase instruction | |
1da177e4 | 3170 | * |
8b6e50c9 | 3171 | * Erase one ore more blocks. |
1da177e4 | 3172 | */ |
e0c7d767 | 3173 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 3174 | { |
e0c7d767 | 3175 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 3176 | } |
61b03bd7 | 3177 | |
1da177e4 | 3178 | /** |
7854d3f7 | 3179 | * nand_erase_nand - [INTERN] erase block(s) |
8b6e50c9 BN |
3180 | * @mtd: MTD device structure |
3181 | * @instr: erase instruction | |
3182 | * @allowbbt: allow erasing the bbt area | |
1da177e4 | 3183 | * |
8b6e50c9 | 3184 | * Erase one ore more blocks. |
1da177e4 | 3185 | */ |
ace4dfee TG |
3186 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
3187 | int allowbbt) | |
1da177e4 | 3188 | { |
69423d99 | 3189 | int page, status, pages_per_block, ret, chipnr; |
862eba51 | 3190 | struct nand_chip *chip = mtd_to_nand(mtd); |
69423d99 | 3191 | loff_t len; |
1da177e4 | 3192 | |
289c0522 BN |
3193 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
3194 | __func__, (unsigned long long)instr->addr, | |
3195 | (unsigned long long)instr->len); | |
1da177e4 | 3196 | |
6fe5a6ac | 3197 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 3198 | return -EINVAL; |
1da177e4 | 3199 | |
1da177e4 | 3200 | /* Grab the lock and see if the device is available */ |
6a8214aa | 3201 | nand_get_device(mtd, FL_ERASING); |
1da177e4 LT |
3202 | |
3203 | /* Shift to get first page */ | |
ace4dfee TG |
3204 | page = (int)(instr->addr >> chip->page_shift); |
3205 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
3206 | |
3207 | /* Calculate pages in each block */ | |
ace4dfee | 3208 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
3209 | |
3210 | /* Select the NAND device */ | |
ace4dfee | 3211 | chip->select_chip(mtd, chipnr); |
1da177e4 | 3212 | |
1da177e4 LT |
3213 | /* Check, if it is write protected */ |
3214 | if (nand_check_wp(mtd)) { | |
289c0522 BN |
3215 | pr_debug("%s: device is write protected!\n", |
3216 | __func__); | |
1da177e4 LT |
3217 | instr->state = MTD_ERASE_FAILED; |
3218 | goto erase_exit; | |
3219 | } | |
3220 | ||
3221 | /* Loop through the pages */ | |
3222 | len = instr->len; | |
3223 | ||
3224 | instr->state = MTD_ERASING; | |
3225 | ||
3226 | while (len) { | |
12183a20 | 3227 | /* Check if we have a bad block, we do not erase bad blocks! */ |
ace4dfee | 3228 | if (nand_block_checkbad(mtd, ((loff_t) page) << |
9f3e0429 | 3229 | chip->page_shift, allowbbt)) { |
d0370219 BN |
3230 | pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", |
3231 | __func__, page); | |
1da177e4 LT |
3232 | instr->state = MTD_ERASE_FAILED; |
3233 | goto erase_exit; | |
3234 | } | |
61b03bd7 | 3235 | |
ace4dfee TG |
3236 | /* |
3237 | * Invalidate the page cache, if we erase the block which | |
8b6e50c9 | 3238 | * contains the current cached page. |
ace4dfee TG |
3239 | */ |
3240 | if (page <= chip->pagebuf && chip->pagebuf < | |
3241 | (page + pages_per_block)) | |
3242 | chip->pagebuf = -1; | |
1da177e4 | 3243 | |
49c50b97 | 3244 | status = chip->erase(mtd, page & chip->pagemask); |
1da177e4 LT |
3245 | |
3246 | /* See if block erase succeeded */ | |
a4ab4c5d | 3247 | if (status & NAND_STATUS_FAIL) { |
289c0522 BN |
3248 | pr_debug("%s: failed erase, page 0x%08x\n", |
3249 | __func__, page); | |
1da177e4 | 3250 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
3251 | instr->fail_addr = |
3252 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
3253 | goto erase_exit; |
3254 | } | |
30f464b7 | 3255 | |
1da177e4 | 3256 | /* Increment page address and decrement length */ |
daae74ca | 3257 | len -= (1ULL << chip->phys_erase_shift); |
1da177e4 LT |
3258 | page += pages_per_block; |
3259 | ||
3260 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 3261 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 3262 | chipnr++; |
ace4dfee TG |
3263 | chip->select_chip(mtd, -1); |
3264 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
3265 | } |
3266 | } | |
3267 | instr->state = MTD_ERASE_DONE; | |
3268 | ||
7351d3a5 | 3269 | erase_exit: |
1da177e4 LT |
3270 | |
3271 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
3272 | |
3273 | /* Deselect and wake up anyone waiting on the device */ | |
b0bb6903 | 3274 | chip->select_chip(mtd, -1); |
1da177e4 LT |
3275 | nand_release_device(mtd); |
3276 | ||
49defc01 DW |
3277 | /* Do call back function */ |
3278 | if (!ret) | |
3279 | mtd_erase_callback(instr); | |
3280 | ||
1da177e4 LT |
3281 | /* Return more or less happy */ |
3282 | return ret; | |
3283 | } | |
3284 | ||
3285 | /** | |
3286 | * nand_sync - [MTD Interface] sync | |
8b6e50c9 | 3287 | * @mtd: MTD device structure |
1da177e4 | 3288 | * |
8b6e50c9 | 3289 | * Sync is actually a wait for chip ready function. |
1da177e4 | 3290 | */ |
e0c7d767 | 3291 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 3292 | { |
289c0522 | 3293 | pr_debug("%s: called\n", __func__); |
1da177e4 LT |
3294 | |
3295 | /* Grab the lock and see if the device is available */ | |
6a8214aa | 3296 | nand_get_device(mtd, FL_SYNCING); |
1da177e4 | 3297 | /* Release it and go back */ |
e0c7d767 | 3298 | nand_release_device(mtd); |
1da177e4 LT |
3299 | } |
3300 | ||
1da177e4 | 3301 | /** |
ace4dfee | 3302 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
8b6e50c9 BN |
3303 | * @mtd: MTD device structure |
3304 | * @offs: offset relative to mtd start | |
1da177e4 | 3305 | */ |
ace4dfee | 3306 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 | 3307 | { |
9f3e0429 AT |
3308 | struct nand_chip *chip = mtd_to_nand(mtd); |
3309 | int chipnr = (int)(offs >> chip->chip_shift); | |
3310 | int ret; | |
3311 | ||
3312 | /* Select the NAND device */ | |
3313 | nand_get_device(mtd, FL_READING); | |
3314 | chip->select_chip(mtd, chipnr); | |
3315 | ||
3316 | ret = nand_block_checkbad(mtd, offs, 0); | |
3317 | ||
3318 | chip->select_chip(mtd, -1); | |
3319 | nand_release_device(mtd); | |
3320 | ||
3321 | return ret; | |
1da177e4 LT |
3322 | } |
3323 | ||
3324 | /** | |
ace4dfee | 3325 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
8b6e50c9 BN |
3326 | * @mtd: MTD device structure |
3327 | * @ofs: offset relative to mtd start | |
1da177e4 | 3328 | */ |
e0c7d767 | 3329 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 3330 | { |
1da177e4 LT |
3331 | int ret; |
3332 | ||
f8ac0414 FF |
3333 | ret = nand_block_isbad(mtd, ofs); |
3334 | if (ret) { | |
8b6e50c9 | 3335 | /* If it was bad already, return success and do nothing */ |
1da177e4 LT |
3336 | if (ret > 0) |
3337 | return 0; | |
e0c7d767 DW |
3338 | return ret; |
3339 | } | |
1da177e4 | 3340 | |
5a0edb25 | 3341 | return nand_block_markbad_lowlevel(mtd, ofs); |
1da177e4 LT |
3342 | } |
3343 | ||
5671842f ZB |
3344 | /** |
3345 | * nand_max_bad_blocks - [MTD Interface] Max number of bad blocks for an mtd | |
3346 | * @mtd: MTD device structure | |
3347 | * @ofs: offset relative to mtd start | |
3348 | * @len: length of mtd | |
3349 | */ | |
3350 | static int nand_max_bad_blocks(struct mtd_info *mtd, loff_t ofs, size_t len) | |
3351 | { | |
3352 | struct nand_chip *chip = mtd_to_nand(mtd); | |
3353 | u32 part_start_block; | |
3354 | u32 part_end_block; | |
3355 | u32 part_start_die; | |
3356 | u32 part_end_die; | |
3357 | ||
3358 | /* | |
3359 | * max_bb_per_die and blocks_per_die used to determine | |
3360 | * the maximum bad block count. | |
3361 | */ | |
3362 | if (!chip->max_bb_per_die || !chip->blocks_per_die) | |
3363 | return -ENOTSUPP; | |
3364 | ||
3365 | /* Get the start and end of the partition in erase blocks. */ | |
3366 | part_start_block = mtd_div_by_eb(ofs, mtd); | |
3367 | part_end_block = mtd_div_by_eb(len, mtd) + part_start_block - 1; | |
3368 | ||
3369 | /* Get the start and end LUNs of the partition. */ | |
3370 | part_start_die = part_start_block / chip->blocks_per_die; | |
3371 | part_end_die = part_end_block / chip->blocks_per_die; | |
3372 | ||
3373 | /* | |
3374 | * Look up the bad blocks per unit and multiply by the number of units | |
3375 | * that the partition spans. | |
3376 | */ | |
3377 | return chip->max_bb_per_die * (part_end_die - part_start_die + 1); | |
3378 | } | |
3379 | ||
7db03ecc HS |
3380 | /** |
3381 | * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand | |
3382 | * @mtd: MTD device structure | |
3383 | * @chip: nand chip info structure | |
3384 | * @addr: feature address. | |
3385 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
3386 | */ | |
3387 | static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, | |
3388 | int addr, uint8_t *subfeature_param) | |
3389 | { | |
3390 | int status; | |
05f78359 | 3391 | int i; |
7db03ecc | 3392 | |
d914c932 DM |
3393 | if (!chip->onfi_version || |
3394 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
3395 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
3396 | return -EINVAL; |
3397 | ||
3398 | chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1); | |
05f78359 UKK |
3399 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
3400 | chip->write_byte(mtd, subfeature_param[i]); | |
3401 | ||
7db03ecc HS |
3402 | status = chip->waitfunc(mtd, chip); |
3403 | if (status & NAND_STATUS_FAIL) | |
3404 | return -EIO; | |
3405 | return 0; | |
3406 | } | |
3407 | ||
3408 | /** | |
3409 | * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand | |
3410 | * @mtd: MTD device structure | |
3411 | * @chip: nand chip info structure | |
3412 | * @addr: feature address. | |
3413 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
3414 | */ | |
3415 | static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, | |
3416 | int addr, uint8_t *subfeature_param) | |
3417 | { | |
05f78359 UKK |
3418 | int i; |
3419 | ||
d914c932 DM |
3420 | if (!chip->onfi_version || |
3421 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
3422 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
3423 | return -EINVAL; |
3424 | ||
7db03ecc | 3425 | chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1); |
05f78359 UKK |
3426 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
3427 | *subfeature_param++ = chip->read_byte(mtd); | |
7db03ecc HS |
3428 | return 0; |
3429 | } | |
3430 | ||
4a78cc64 BB |
3431 | /** |
3432 | * nand_onfi_get_set_features_notsupp - set/get features stub returning | |
3433 | * -ENOTSUPP | |
3434 | * @mtd: MTD device structure | |
3435 | * @chip: nand chip info structure | |
3436 | * @addr: feature address. | |
3437 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
3438 | * | |
3439 | * Should be used by NAND controller drivers that do not support the SET/GET | |
3440 | * FEATURES operations. | |
3441 | */ | |
3442 | int nand_onfi_get_set_features_notsupp(struct mtd_info *mtd, | |
3443 | struct nand_chip *chip, int addr, | |
3444 | u8 *subfeature_param) | |
3445 | { | |
3446 | return -ENOTSUPP; | |
3447 | } | |
3448 | EXPORT_SYMBOL(nand_onfi_get_set_features_notsupp); | |
3449 | ||
962034f4 VW |
3450 | /** |
3451 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
8b6e50c9 | 3452 | * @mtd: MTD device structure |
962034f4 VW |
3453 | */ |
3454 | static int nand_suspend(struct mtd_info *mtd) | |
3455 | { | |
6a8214aa | 3456 | return nand_get_device(mtd, FL_PM_SUSPENDED); |
962034f4 VW |
3457 | } |
3458 | ||
3459 | /** | |
3460 | * nand_resume - [MTD Interface] Resume the NAND flash | |
8b6e50c9 | 3461 | * @mtd: MTD device structure |
962034f4 VW |
3462 | */ |
3463 | static void nand_resume(struct mtd_info *mtd) | |
3464 | { | |
862eba51 | 3465 | struct nand_chip *chip = mtd_to_nand(mtd); |
962034f4 | 3466 | |
ace4dfee | 3467 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
3468 | nand_release_device(mtd); |
3469 | else | |
d0370219 BN |
3470 | pr_err("%s called for a chip which is not in suspended state\n", |
3471 | __func__); | |
962034f4 VW |
3472 | } |
3473 | ||
72ea4036 SB |
3474 | /** |
3475 | * nand_shutdown - [MTD Interface] Finish the current NAND operation and | |
3476 | * prevent further operations | |
3477 | * @mtd: MTD device structure | |
3478 | */ | |
3479 | static void nand_shutdown(struct mtd_info *mtd) | |
3480 | { | |
9ca641b0 | 3481 | nand_get_device(mtd, FL_PM_SUSPENDED); |
72ea4036 SB |
3482 | } |
3483 | ||
8b6e50c9 | 3484 | /* Set default functions */ |
29a198a1 | 3485 | static void nand_set_defaults(struct nand_chip *chip) |
7aa65bfd | 3486 | { |
29a198a1 BB |
3487 | unsigned int busw = chip->options & NAND_BUSWIDTH_16; |
3488 | ||
1da177e4 | 3489 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
3490 | if (!chip->chip_delay) |
3491 | chip->chip_delay = 20; | |
1da177e4 LT |
3492 | |
3493 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
3494 | if (chip->cmdfunc == NULL) |
3495 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
3496 | |
3497 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
3498 | if (chip->waitfunc == NULL) |
3499 | chip->waitfunc = nand_wait; | |
3500 | ||
3501 | if (!chip->select_chip) | |
3502 | chip->select_chip = nand_select_chip; | |
68e80780 | 3503 | |
4204cccd HS |
3504 | /* set for ONFI nand */ |
3505 | if (!chip->onfi_set_features) | |
3506 | chip->onfi_set_features = nand_onfi_set_features; | |
3507 | if (!chip->onfi_get_features) | |
3508 | chip->onfi_get_features = nand_onfi_get_features; | |
3509 | ||
68e80780 BN |
3510 | /* If called twice, pointers that depend on busw may need to be reset */ |
3511 | if (!chip->read_byte || chip->read_byte == nand_read_byte) | |
ace4dfee TG |
3512 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; |
3513 | if (!chip->read_word) | |
3514 | chip->read_word = nand_read_word; | |
3515 | if (!chip->block_bad) | |
3516 | chip->block_bad = nand_block_bad; | |
3517 | if (!chip->block_markbad) | |
3518 | chip->block_markbad = nand_default_block_markbad; | |
68e80780 | 3519 | if (!chip->write_buf || chip->write_buf == nand_write_buf) |
ace4dfee | 3520 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; |
05f78359 UKK |
3521 | if (!chip->write_byte || chip->write_byte == nand_write_byte) |
3522 | chip->write_byte = busw ? nand_write_byte16 : nand_write_byte; | |
68e80780 | 3523 | if (!chip->read_buf || chip->read_buf == nand_read_buf) |
ace4dfee | 3524 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; |
ace4dfee TG |
3525 | if (!chip->scan_bbt) |
3526 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
3527 | |
3528 | if (!chip->controller) { | |
3529 | chip->controller = &chip->hwcontrol; | |
d45bc58d | 3530 | nand_hw_control_init(chip->controller); |
f75e5097 TG |
3531 | } |
3532 | ||
477544c6 MY |
3533 | if (!chip->buf_align) |
3534 | chip->buf_align = 1; | |
7aa65bfd TG |
3535 | } |
3536 | ||
8b6e50c9 | 3537 | /* Sanitize ONFI strings so we can safely print them */ |
d1e1f4e4 FF |
3538 | static void sanitize_string(uint8_t *s, size_t len) |
3539 | { | |
3540 | ssize_t i; | |
3541 | ||
8b6e50c9 | 3542 | /* Null terminate */ |
d1e1f4e4 FF |
3543 | s[len - 1] = 0; |
3544 | ||
8b6e50c9 | 3545 | /* Remove non printable chars */ |
d1e1f4e4 FF |
3546 | for (i = 0; i < len - 1; i++) { |
3547 | if (s[i] < ' ' || s[i] > 127) | |
3548 | s[i] = '?'; | |
3549 | } | |
3550 | ||
8b6e50c9 | 3551 | /* Remove trailing spaces */ |
d1e1f4e4 FF |
3552 | strim(s); |
3553 | } | |
3554 | ||
3555 | static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) | |
3556 | { | |
3557 | int i; | |
3558 | while (len--) { | |
3559 | crc ^= *p++ << 8; | |
3560 | for (i = 0; i < 8; i++) | |
3561 | crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); | |
3562 | } | |
3563 | ||
3564 | return crc; | |
3565 | } | |
3566 | ||
6dcbe0cd | 3567 | /* Parse the Extended Parameter Page. */ |
cbe435a1 BB |
3568 | static int nand_flash_detect_ext_param_page(struct nand_chip *chip, |
3569 | struct nand_onfi_params *p) | |
6dcbe0cd | 3570 | { |
cbe435a1 | 3571 | struct mtd_info *mtd = nand_to_mtd(chip); |
6dcbe0cd HS |
3572 | struct onfi_ext_param_page *ep; |
3573 | struct onfi_ext_section *s; | |
3574 | struct onfi_ext_ecc_info *ecc; | |
3575 | uint8_t *cursor; | |
3576 | int ret = -EINVAL; | |
3577 | int len; | |
3578 | int i; | |
3579 | ||
3580 | len = le16_to_cpu(p->ext_param_page_length) * 16; | |
3581 | ep = kmalloc(len, GFP_KERNEL); | |
5cb13271 BN |
3582 | if (!ep) |
3583 | return -ENOMEM; | |
6dcbe0cd HS |
3584 | |
3585 | /* Send our own NAND_CMD_PARAM. */ | |
3586 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); | |
3587 | ||
3588 | /* Use the Change Read Column command to skip the ONFI param pages. */ | |
3589 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, | |
3590 | sizeof(*p) * p->num_of_param_pages , -1); | |
3591 | ||
3592 | /* Read out the Extended Parameter Page. */ | |
3593 | chip->read_buf(mtd, (uint8_t *)ep, len); | |
3594 | if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2) | |
3595 | != le16_to_cpu(ep->crc))) { | |
3596 | pr_debug("fail in the CRC.\n"); | |
3597 | goto ext_out; | |
3598 | } | |
3599 | ||
3600 | /* | |
3601 | * Check the signature. | |
3602 | * Do not strictly follow the ONFI spec, maybe changed in future. | |
3603 | */ | |
3604 | if (strncmp(ep->sig, "EPPS", 4)) { | |
3605 | pr_debug("The signature is invalid.\n"); | |
3606 | goto ext_out; | |
3607 | } | |
3608 | ||
3609 | /* find the ECC section. */ | |
3610 | cursor = (uint8_t *)(ep + 1); | |
3611 | for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) { | |
3612 | s = ep->sections + i; | |
3613 | if (s->type == ONFI_SECTION_TYPE_2) | |
3614 | break; | |
3615 | cursor += s->length * 16; | |
3616 | } | |
3617 | if (i == ONFI_EXT_SECTION_MAX) { | |
3618 | pr_debug("We can not find the ECC section.\n"); | |
3619 | goto ext_out; | |
3620 | } | |
3621 | ||
3622 | /* get the info we want. */ | |
3623 | ecc = (struct onfi_ext_ecc_info *)cursor; | |
3624 | ||
4ae7d228 BN |
3625 | if (!ecc->codeword_size) { |
3626 | pr_debug("Invalid codeword size\n"); | |
3627 | goto ext_out; | |
6dcbe0cd HS |
3628 | } |
3629 | ||
4ae7d228 BN |
3630 | chip->ecc_strength_ds = ecc->ecc_bits; |
3631 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
5cb13271 | 3632 | ret = 0; |
6dcbe0cd HS |
3633 | |
3634 | ext_out: | |
3635 | kfree(ep); | |
3636 | return ret; | |
3637 | } | |
3638 | ||
6fb277ba | 3639 | /* |
8b6e50c9 | 3640 | * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. |
6fb277ba | 3641 | */ |
29a198a1 | 3642 | static int nand_flash_detect_onfi(struct nand_chip *chip) |
6fb277ba | 3643 | { |
cbe435a1 | 3644 | struct mtd_info *mtd = nand_to_mtd(chip); |
6fb277ba | 3645 | struct nand_onfi_params *p = &chip->onfi_params; |
bd9c6e99 | 3646 | int i, j; |
6fb277ba FF |
3647 | int val; |
3648 | ||
7854d3f7 | 3649 | /* Try ONFI for unknown chip or LP */ |
6fb277ba FF |
3650 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); |
3651 | if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || | |
3652 | chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') | |
3653 | return 0; | |
3654 | ||
6fb277ba FF |
3655 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); |
3656 | for (i = 0; i < 3; i++) { | |
bd9c6e99 BN |
3657 | for (j = 0; j < sizeof(*p); j++) |
3658 | ((uint8_t *)p)[j] = chip->read_byte(mtd); | |
6fb277ba FF |
3659 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == |
3660 | le16_to_cpu(p->crc)) { | |
6fb277ba FF |
3661 | break; |
3662 | } | |
3663 | } | |
3664 | ||
c7f23a70 BN |
3665 | if (i == 3) { |
3666 | pr_err("Could not find valid ONFI parameter page; aborting\n"); | |
6fb277ba | 3667 | return 0; |
c7f23a70 | 3668 | } |
6fb277ba | 3669 | |
8b6e50c9 | 3670 | /* Check version */ |
6fb277ba | 3671 | val = le16_to_cpu(p->revision); |
b7b1a29d BN |
3672 | if (val & (1 << 5)) |
3673 | chip->onfi_version = 23; | |
3674 | else if (val & (1 << 4)) | |
6fb277ba FF |
3675 | chip->onfi_version = 22; |
3676 | else if (val & (1 << 3)) | |
3677 | chip->onfi_version = 21; | |
3678 | else if (val & (1 << 2)) | |
3679 | chip->onfi_version = 20; | |
b7b1a29d | 3680 | else if (val & (1 << 1)) |
6fb277ba | 3681 | chip->onfi_version = 10; |
b7b1a29d BN |
3682 | |
3683 | if (!chip->onfi_version) { | |
20171642 | 3684 | pr_info("unsupported ONFI version: %d\n", val); |
b7b1a29d BN |
3685 | return 0; |
3686 | } | |
6fb277ba FF |
3687 | |
3688 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3689 | sanitize_string(p->model, sizeof(p->model)); | |
3690 | if (!mtd->name) | |
3691 | mtd->name = p->model; | |
4355b70c | 3692 | |
6fb277ba | 3693 | mtd->writesize = le32_to_cpu(p->byte_per_page); |
4355b70c BN |
3694 | |
3695 | /* | |
3696 | * pages_per_block and blocks_per_lun may not be a power-of-2 size | |
3697 | * (don't ask me who thought of this...). MTD assumes that these | |
3698 | * dimensions will be power-of-2, so just truncate the remaining area. | |
3699 | */ | |
3700 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3701 | mtd->erasesize *= mtd->writesize; | |
3702 | ||
6fb277ba | 3703 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); |
4355b70c BN |
3704 | |
3705 | /* See erasesize comment */ | |
3706 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
63795755 | 3707 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; |
13fbd179 | 3708 | chip->bits_per_cell = p->bits_per_cell; |
e2985fc1 | 3709 | |
34da5f5f ZB |
3710 | chip->max_bb_per_die = le16_to_cpu(p->bb_per_lun); |
3711 | chip->blocks_per_die = le32_to_cpu(p->blocks_per_lun); | |
3712 | ||
e2985fc1 | 3713 | if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) |
29a198a1 | 3714 | chip->options |= NAND_BUSWIDTH_16; |
6fb277ba | 3715 | |
10c86bab HS |
3716 | if (p->ecc_bits != 0xff) { |
3717 | chip->ecc_strength_ds = p->ecc_bits; | |
3718 | chip->ecc_step_ds = 512; | |
6dcbe0cd HS |
3719 | } else if (chip->onfi_version >= 21 && |
3720 | (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) { | |
3721 | ||
3722 | /* | |
3723 | * The nand_flash_detect_ext_param_page() uses the | |
3724 | * Change Read Column command which maybe not supported | |
3725 | * by the chip->cmdfunc. So try to update the chip->cmdfunc | |
3726 | * now. We do not replace user supplied command function. | |
3727 | */ | |
3728 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) | |
3729 | chip->cmdfunc = nand_command_lp; | |
3730 | ||
3731 | /* The Extended Parameter Page is supported since ONFI 2.1. */ | |
cbe435a1 | 3732 | if (nand_flash_detect_ext_param_page(chip, p)) |
c7f23a70 BN |
3733 | pr_warn("Failed to detect ONFI extended param page\n"); |
3734 | } else { | |
3735 | pr_warn("Could not retrieve ONFI ECC requirements\n"); | |
10c86bab HS |
3736 | } |
3737 | ||
6fb277ba FF |
3738 | return 1; |
3739 | } | |
3740 | ||
91361818 HS |
3741 | /* |
3742 | * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise. | |
3743 | */ | |
29a198a1 | 3744 | static int nand_flash_detect_jedec(struct nand_chip *chip) |
91361818 | 3745 | { |
cbe435a1 | 3746 | struct mtd_info *mtd = nand_to_mtd(chip); |
91361818 HS |
3747 | struct nand_jedec_params *p = &chip->jedec_params; |
3748 | struct jedec_ecc_info *ecc; | |
3749 | int val; | |
3750 | int i, j; | |
3751 | ||
3752 | /* Try JEDEC for unknown chip or LP */ | |
3753 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1); | |
3754 | if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' || | |
3755 | chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' || | |
3756 | chip->read_byte(mtd) != 'C') | |
3757 | return 0; | |
3758 | ||
3759 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1); | |
3760 | for (i = 0; i < 3; i++) { | |
3761 | for (j = 0; j < sizeof(*p); j++) | |
3762 | ((uint8_t *)p)[j] = chip->read_byte(mtd); | |
3763 | ||
3764 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) == | |
3765 | le16_to_cpu(p->crc)) | |
3766 | break; | |
3767 | } | |
3768 | ||
3769 | if (i == 3) { | |
3770 | pr_err("Could not find valid JEDEC parameter page; aborting\n"); | |
3771 | return 0; | |
3772 | } | |
3773 | ||
3774 | /* Check version */ | |
3775 | val = le16_to_cpu(p->revision); | |
3776 | if (val & (1 << 2)) | |
3777 | chip->jedec_version = 10; | |
3778 | else if (val & (1 << 1)) | |
3779 | chip->jedec_version = 1; /* vendor specific version */ | |
3780 | ||
3781 | if (!chip->jedec_version) { | |
3782 | pr_info("unsupported JEDEC version: %d\n", val); | |
3783 | return 0; | |
3784 | } | |
3785 | ||
3786 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3787 | sanitize_string(p->model, sizeof(p->model)); | |
3788 | if (!mtd->name) | |
3789 | mtd->name = p->model; | |
3790 | ||
3791 | mtd->writesize = le32_to_cpu(p->byte_per_page); | |
3792 | ||
3793 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
3794 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3795 | mtd->erasesize *= mtd->writesize; | |
3796 | ||
3797 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); | |
3798 | ||
3799 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
3800 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
3801 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; | |
3802 | chip->bits_per_cell = p->bits_per_cell; | |
3803 | ||
3804 | if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS) | |
29a198a1 | 3805 | chip->options |= NAND_BUSWIDTH_16; |
91361818 HS |
3806 | |
3807 | /* ECC info */ | |
3808 | ecc = &p->ecc_info[0]; | |
3809 | ||
3810 | if (ecc->codeword_size >= 9) { | |
3811 | chip->ecc_strength_ds = ecc->ecc_bits; | |
3812 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
3813 | } else { | |
3814 | pr_warn("Invalid codeword size\n"); | |
3815 | } | |
3816 | ||
3817 | return 1; | |
3818 | } | |
3819 | ||
e3b88bd6 BN |
3820 | /* |
3821 | * nand_id_has_period - Check if an ID string has a given wraparound period | |
3822 | * @id_data: the ID string | |
3823 | * @arrlen: the length of the @id_data array | |
3824 | * @period: the period of repitition | |
3825 | * | |
3826 | * Check if an ID string is repeated within a given sequence of bytes at | |
3827 | * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a | |
d4d4f1bf | 3828 | * period of 3). This is a helper function for nand_id_len(). Returns non-zero |
e3b88bd6 BN |
3829 | * if the repetition has a period of @period; otherwise, returns zero. |
3830 | */ | |
3831 | static int nand_id_has_period(u8 *id_data, int arrlen, int period) | |
3832 | { | |
3833 | int i, j; | |
3834 | for (i = 0; i < period; i++) | |
3835 | for (j = i + period; j < arrlen; j += period) | |
3836 | if (id_data[i] != id_data[j]) | |
3837 | return 0; | |
3838 | return 1; | |
3839 | } | |
3840 | ||
3841 | /* | |
3842 | * nand_id_len - Get the length of an ID string returned by CMD_READID | |
3843 | * @id_data: the ID string | |
3844 | * @arrlen: the length of the @id_data array | |
3845 | ||
3846 | * Returns the length of the ID string, according to known wraparound/trailing | |
3847 | * zero patterns. If no pattern exists, returns the length of the array. | |
3848 | */ | |
3849 | static int nand_id_len(u8 *id_data, int arrlen) | |
3850 | { | |
3851 | int last_nonzero, period; | |
3852 | ||
3853 | /* Find last non-zero byte */ | |
3854 | for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) | |
3855 | if (id_data[last_nonzero]) | |
3856 | break; | |
3857 | ||
3858 | /* All zeros */ | |
3859 | if (last_nonzero < 0) | |
3860 | return 0; | |
3861 | ||
3862 | /* Calculate wraparound period */ | |
3863 | for (period = 1; period < arrlen; period++) | |
3864 | if (nand_id_has_period(id_data, arrlen, period)) | |
3865 | break; | |
3866 | ||
3867 | /* There's a repeated pattern */ | |
3868 | if (period < arrlen) | |
3869 | return period; | |
3870 | ||
3871 | /* There are trailing zeros */ | |
3872 | if (last_nonzero < arrlen - 1) | |
3873 | return last_nonzero + 1; | |
3874 | ||
3875 | /* No pattern detected */ | |
3876 | return arrlen; | |
3877 | } | |
3878 | ||
7db906b7 HS |
3879 | /* Extract the bits of per cell from the 3rd byte of the extended ID */ |
3880 | static int nand_get_bits_per_cell(u8 cellinfo) | |
3881 | { | |
3882 | int bits; | |
3883 | ||
3884 | bits = cellinfo & NAND_CI_CELLTYPE_MSK; | |
3885 | bits >>= NAND_CI_CELLTYPE_SHIFT; | |
3886 | return bits + 1; | |
3887 | } | |
3888 | ||
fc09bbc0 BN |
3889 | /* |
3890 | * Many new NAND share similar device ID codes, which represent the size of the | |
3891 | * chip. The rest of the parameters must be decoded according to generic or | |
3892 | * manufacturer-specific "extended ID" decoding patterns. | |
3893 | */ | |
abbe26d1 | 3894 | void nand_decode_ext_id(struct nand_chip *chip) |
fc09bbc0 | 3895 | { |
cbe435a1 | 3896 | struct mtd_info *mtd = nand_to_mtd(chip); |
9b2d61f8 | 3897 | int extid; |
7f501f0a | 3898 | u8 *id_data = chip->id.data; |
fc09bbc0 | 3899 | /* The 3rd id byte holds MLC / multichip data */ |
7db906b7 | 3900 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
fc09bbc0 BN |
3901 | /* The 4th id byte is the important one */ |
3902 | extid = id_data[3]; | |
3903 | ||
01389b6b BB |
3904 | /* Calc pagesize */ |
3905 | mtd->writesize = 1024 << (extid & 0x03); | |
3906 | extid >>= 2; | |
3907 | /* Calc oobsize */ | |
3908 | mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9); | |
3909 | extid >>= 2; | |
3910 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
3911 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
3912 | extid >>= 2; | |
3913 | /* Get buswidth information */ | |
3914 | if (extid & 0x1) | |
3915 | chip->options |= NAND_BUSWIDTH_16; | |
fc09bbc0 | 3916 | } |
abbe26d1 | 3917 | EXPORT_SYMBOL_GPL(nand_decode_ext_id); |
fc09bbc0 | 3918 | |
f23a481c BN |
3919 | /* |
3920 | * Old devices have chip data hardcoded in the device ID table. nand_decode_id | |
3921 | * decodes a matching ID table entry and assigns the MTD size parameters for | |
3922 | * the chip. | |
3923 | */ | |
29a198a1 | 3924 | static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type) |
f23a481c | 3925 | { |
cbe435a1 | 3926 | struct mtd_info *mtd = nand_to_mtd(chip); |
f23a481c BN |
3927 | |
3928 | mtd->erasesize = type->erasesize; | |
3929 | mtd->writesize = type->pagesize; | |
3930 | mtd->oobsize = mtd->writesize / 32; | |
f23a481c | 3931 | |
1c195e90 HS |
3932 | /* All legacy ID NAND are small-page, SLC */ |
3933 | chip->bits_per_cell = 1; | |
f23a481c BN |
3934 | } |
3935 | ||
7e74c2d7 BN |
3936 | /* |
3937 | * Set the bad block marker/indicator (BBM/BBI) patterns according to some | |
3938 | * heuristic patterns using various detected parameters (e.g., manufacturer, | |
3939 | * page size, cell-type information). | |
3940 | */ | |
7f501f0a | 3941 | static void nand_decode_bbm_options(struct nand_chip *chip) |
7e74c2d7 | 3942 | { |
cbe435a1 | 3943 | struct mtd_info *mtd = nand_to_mtd(chip); |
7e74c2d7 BN |
3944 | |
3945 | /* Set the bad block position */ | |
3946 | if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) | |
3947 | chip->badblockpos = NAND_LARGE_BADBLOCK_POS; | |
3948 | else | |
3949 | chip->badblockpos = NAND_SMALL_BADBLOCK_POS; | |
7e74c2d7 BN |
3950 | } |
3951 | ||
ec6e87e3 HS |
3952 | static inline bool is_full_id_nand(struct nand_flash_dev *type) |
3953 | { | |
3954 | return type->id_len; | |
3955 | } | |
3956 | ||
cbe435a1 | 3957 | static bool find_full_id_nand(struct nand_chip *chip, |
29a198a1 | 3958 | struct nand_flash_dev *type) |
ec6e87e3 | 3959 | { |
cbe435a1 | 3960 | struct mtd_info *mtd = nand_to_mtd(chip); |
7f501f0a | 3961 | u8 *id_data = chip->id.data; |
cbe435a1 | 3962 | |
ec6e87e3 HS |
3963 | if (!strncmp(type->id, id_data, type->id_len)) { |
3964 | mtd->writesize = type->pagesize; | |
3965 | mtd->erasesize = type->erasesize; | |
3966 | mtd->oobsize = type->oobsize; | |
3967 | ||
7db906b7 | 3968 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
ec6e87e3 HS |
3969 | chip->chipsize = (uint64_t)type->chipsize << 20; |
3970 | chip->options |= type->options; | |
57219342 HS |
3971 | chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); |
3972 | chip->ecc_step_ds = NAND_ECC_STEP(type); | |
57a94e24 BB |
3973 | chip->onfi_timing_mode_default = |
3974 | type->onfi_timing_mode_default; | |
ec6e87e3 | 3975 | |
092b6a1d CZ |
3976 | if (!mtd->name) |
3977 | mtd->name = type->name; | |
3978 | ||
ec6e87e3 HS |
3979 | return true; |
3980 | } | |
3981 | return false; | |
3982 | } | |
3983 | ||
abbe26d1 BB |
3984 | /* |
3985 | * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC | |
3986 | * compliant and does not have a full-id or legacy-id entry in the nand_ids | |
3987 | * table. | |
3988 | */ | |
3989 | static void nand_manufacturer_detect(struct nand_chip *chip) | |
3990 | { | |
3991 | /* | |
3992 | * Try manufacturer detection if available and use | |
3993 | * nand_decode_ext_id() otherwise. | |
3994 | */ | |
3995 | if (chip->manufacturer.desc && chip->manufacturer.desc->ops && | |
3996 | chip->manufacturer.desc->ops->detect) | |
3997 | chip->manufacturer.desc->ops->detect(chip); | |
3998 | else | |
3999 | nand_decode_ext_id(chip); | |
4000 | } | |
4001 | ||
4002 | /* | |
4003 | * Manufacturer initialization. This function is called for all NANDs including | |
4004 | * ONFI and JEDEC compliant ones. | |
4005 | * Manufacturer drivers should put all their specific initialization code in | |
4006 | * their ->init() hook. | |
4007 | */ | |
4008 | static int nand_manufacturer_init(struct nand_chip *chip) | |
4009 | { | |
4010 | if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops || | |
4011 | !chip->manufacturer.desc->ops->init) | |
4012 | return 0; | |
4013 | ||
4014 | return chip->manufacturer.desc->ops->init(chip); | |
4015 | } | |
4016 | ||
4017 | /* | |
4018 | * Manufacturer cleanup. This function is called for all NANDs including | |
4019 | * ONFI and JEDEC compliant ones. | |
4020 | * Manufacturer drivers should put all their specific cleanup code in their | |
4021 | * ->cleanup() hook. | |
4022 | */ | |
4023 | static void nand_manufacturer_cleanup(struct nand_chip *chip) | |
4024 | { | |
4025 | /* Release manufacturer private data */ | |
4026 | if (chip->manufacturer.desc && chip->manufacturer.desc->ops && | |
4027 | chip->manufacturer.desc->ops->cleanup) | |
4028 | chip->manufacturer.desc->ops->cleanup(chip); | |
4029 | } | |
4030 | ||
7aa65bfd | 4031 | /* |
8b6e50c9 | 4032 | * Get the flash and manufacturer id and lookup if the type is supported. |
7aa65bfd | 4033 | */ |
7bb42799 | 4034 | static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type) |
7aa65bfd | 4035 | { |
bcc678c2 | 4036 | const struct nand_manufacturer *manufacturer; |
cbe435a1 | 4037 | struct mtd_info *mtd = nand_to_mtd(chip); |
bb77082f | 4038 | int busw; |
abbe26d1 | 4039 | int i, ret; |
7f501f0a BB |
4040 | u8 *id_data = chip->id.data; |
4041 | u8 maf_id, dev_id; | |
1da177e4 | 4042 | |
ef89a880 KB |
4043 | /* |
4044 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
8b6e50c9 | 4045 | * after power-up. |
ef89a880 | 4046 | */ |
73f907fd BB |
4047 | nand_reset(chip, 0); |
4048 | ||
4049 | /* Select the device */ | |
4050 | chip->select_chip(mtd, 0); | |
ef89a880 | 4051 | |
1da177e4 | 4052 | /* Send the command for reading device ID */ |
ace4dfee | 4053 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
4054 | |
4055 | /* Read manufacturer and device IDs */ | |
7f501f0a BB |
4056 | maf_id = chip->read_byte(mtd); |
4057 | dev_id = chip->read_byte(mtd); | |
1da177e4 | 4058 | |
8b6e50c9 BN |
4059 | /* |
4060 | * Try again to make sure, as some systems the bus-hold or other | |
ed8165c7 BD |
4061 | * interface concerns can cause random data which looks like a |
4062 | * possibly credible NAND flash to appear. If the two results do | |
4063 | * not match, ignore the device completely. | |
4064 | */ | |
4065 | ||
4066 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
4067 | ||
4aef9b78 BN |
4068 | /* Read entire ID string */ |
4069 | for (i = 0; i < 8; i++) | |
426c457a | 4070 | id_data[i] = chip->read_byte(mtd); |
ed8165c7 | 4071 | |
7f501f0a | 4072 | if (id_data[0] != maf_id || id_data[1] != dev_id) { |
20171642 | 4073 | pr_info("second ID read did not match %02x,%02x against %02x,%02x\n", |
7f501f0a | 4074 | maf_id, dev_id, id_data[0], id_data[1]); |
4722c0e9 | 4075 | return -ENODEV; |
ed8165c7 BD |
4076 | } |
4077 | ||
7f501f0a BB |
4078 | chip->id.len = nand_id_len(id_data, 8); |
4079 | ||
abbe26d1 BB |
4080 | /* Try to identify manufacturer */ |
4081 | manufacturer = nand_get_manufacturer(maf_id); | |
4082 | chip->manufacturer.desc = manufacturer; | |
4083 | ||
7aa65bfd | 4084 | if (!type) |
5e81e88a DW |
4085 | type = nand_flash_ids; |
4086 | ||
29a198a1 BB |
4087 | /* |
4088 | * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic | |
4089 | * override it. | |
4090 | * This is required to make sure initial NAND bus width set by the | |
4091 | * NAND controller driver is coherent with the real NAND bus width | |
4092 | * (extracted by auto-detection code). | |
4093 | */ | |
4094 | busw = chip->options & NAND_BUSWIDTH_16; | |
4095 | ||
4096 | /* | |
4097 | * The flag is only set (never cleared), reset it to its default value | |
4098 | * before starting auto-detection. | |
4099 | */ | |
4100 | chip->options &= ~NAND_BUSWIDTH_16; | |
4101 | ||
ec6e87e3 HS |
4102 | for (; type->name != NULL; type++) { |
4103 | if (is_full_id_nand(type)) { | |
29a198a1 | 4104 | if (find_full_id_nand(chip, type)) |
ec6e87e3 | 4105 | goto ident_done; |
7f501f0a | 4106 | } else if (dev_id == type->dev_id) { |
db5b09f6 | 4107 | break; |
ec6e87e3 HS |
4108 | } |
4109 | } | |
5e81e88a | 4110 | |
d1e1f4e4 FF |
4111 | chip->onfi_version = 0; |
4112 | if (!type->name || !type->pagesize) { | |
35fc5195 | 4113 | /* Check if the chip is ONFI compliant */ |
29a198a1 | 4114 | if (nand_flash_detect_onfi(chip)) |
6fb277ba | 4115 | goto ident_done; |
91361818 HS |
4116 | |
4117 | /* Check if the chip is JEDEC compliant */ | |
29a198a1 | 4118 | if (nand_flash_detect_jedec(chip)) |
91361818 | 4119 | goto ident_done; |
d1e1f4e4 FF |
4120 | } |
4121 | ||
5e81e88a | 4122 | if (!type->name) |
4722c0e9 | 4123 | return -ENODEV; |
7aa65bfd | 4124 | |
ba0251fe TG |
4125 | if (!mtd->name) |
4126 | mtd->name = type->name; | |
4127 | ||
69423d99 | 4128 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd | 4129 | |
abbe26d1 BB |
4130 | if (!type->pagesize) |
4131 | nand_manufacturer_detect(chip); | |
4132 | else | |
29a198a1 | 4133 | nand_decode_id(chip, type); |
abbe26d1 | 4134 | |
bf7a01bf BN |
4135 | /* Get chip options */ |
4136 | chip->options |= type->options; | |
d1e1f4e4 | 4137 | |
d1e1f4e4 FF |
4138 | ident_done: |
4139 | ||
64b37b2a | 4140 | if (chip->options & NAND_BUSWIDTH_AUTO) { |
29a198a1 BB |
4141 | WARN_ON(busw & NAND_BUSWIDTH_16); |
4142 | nand_set_defaults(chip); | |
64b37b2a MC |
4143 | } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { |
4144 | /* | |
4145 | * Check, if buswidth is correct. Hardware drivers should set | |
4146 | * chip correct! | |
4147 | */ | |
20171642 | 4148 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
7f501f0a | 4149 | maf_id, dev_id); |
bcc678c2 BB |
4150 | pr_info("%s %s\n", nand_manufacturer_name(manufacturer), |
4151 | mtd->name); | |
29a198a1 BB |
4152 | pr_warn("bus width %d instead of %d bits\n", busw ? 16 : 8, |
4153 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8); | |
4722c0e9 | 4154 | return -EINVAL; |
7aa65bfd | 4155 | } |
61b03bd7 | 4156 | |
7f501f0a | 4157 | nand_decode_bbm_options(chip); |
7e74c2d7 | 4158 | |
7aa65bfd | 4159 | /* Calculate the address shift from the page size */ |
ace4dfee | 4160 | chip->page_shift = ffs(mtd->writesize) - 1; |
8b6e50c9 | 4161 | /* Convert chipsize to number of pages per chip -1 */ |
ace4dfee | 4162 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 4163 | |
ace4dfee | 4164 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 4165 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
4166 | if (chip->chipsize & 0xffffffff) |
4167 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
7351d3a5 FF |
4168 | else { |
4169 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); | |
4170 | chip->chip_shift += 32 - 1; | |
4171 | } | |
1da177e4 | 4172 | |
26d9be11 | 4173 | chip->badblockbits = 8; |
49c50b97 | 4174 | chip->erase = single_erase; |
7aa65bfd | 4175 | |
8b6e50c9 | 4176 | /* Do not replace user supplied command function! */ |
ace4dfee TG |
4177 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
4178 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd | 4179 | |
abbe26d1 BB |
4180 | ret = nand_manufacturer_init(chip); |
4181 | if (ret) | |
4182 | return ret; | |
4183 | ||
20171642 | 4184 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
7f501f0a | 4185 | maf_id, dev_id); |
ffdac6cd HS |
4186 | |
4187 | if (chip->onfi_version) | |
bcc678c2 BB |
4188 | pr_info("%s %s\n", nand_manufacturer_name(manufacturer), |
4189 | chip->onfi_params.model); | |
ffdac6cd | 4190 | else if (chip->jedec_version) |
bcc678c2 BB |
4191 | pr_info("%s %s\n", nand_manufacturer_name(manufacturer), |
4192 | chip->jedec_params.model); | |
ffdac6cd | 4193 | else |
bcc678c2 BB |
4194 | pr_info("%s %s\n", nand_manufacturer_name(manufacturer), |
4195 | type->name); | |
ffdac6cd | 4196 | |
3755a991 | 4197 | pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n", |
3723e93c | 4198 | (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", |
3755a991 | 4199 | mtd->erasesize >> 10, mtd->writesize, mtd->oobsize); |
4722c0e9 | 4200 | return 0; |
7aa65bfd TG |
4201 | } |
4202 | ||
d48f62b9 BB |
4203 | static const char * const nand_ecc_modes[] = { |
4204 | [NAND_ECC_NONE] = "none", | |
4205 | [NAND_ECC_SOFT] = "soft", | |
4206 | [NAND_ECC_HW] = "hw", | |
4207 | [NAND_ECC_HW_SYNDROME] = "hw_syndrome", | |
4208 | [NAND_ECC_HW_OOB_FIRST] = "hw_oob_first", | |
785818fa | 4209 | [NAND_ECC_ON_DIE] = "on-die", |
d48f62b9 BB |
4210 | }; |
4211 | ||
4212 | static int of_get_nand_ecc_mode(struct device_node *np) | |
4213 | { | |
4214 | const char *pm; | |
4215 | int err, i; | |
4216 | ||
4217 | err = of_property_read_string(np, "nand-ecc-mode", &pm); | |
4218 | if (err < 0) | |
4219 | return err; | |
4220 | ||
4221 | for (i = 0; i < ARRAY_SIZE(nand_ecc_modes); i++) | |
4222 | if (!strcasecmp(pm, nand_ecc_modes[i])) | |
4223 | return i; | |
4224 | ||
ae211bcf RM |
4225 | /* |
4226 | * For backward compatibility we support few obsoleted values that don't | |
4227 | * have their mappings into nand_ecc_modes_t anymore (they were merged | |
4228 | * with other enums). | |
4229 | */ | |
4230 | if (!strcasecmp(pm, "soft_bch")) | |
4231 | return NAND_ECC_SOFT; | |
4232 | ||
d48f62b9 BB |
4233 | return -ENODEV; |
4234 | } | |
4235 | ||
ba4f46b2 RM |
4236 | static const char * const nand_ecc_algos[] = { |
4237 | [NAND_ECC_HAMMING] = "hamming", | |
4238 | [NAND_ECC_BCH] = "bch", | |
4239 | }; | |
4240 | ||
d48f62b9 BB |
4241 | static int of_get_nand_ecc_algo(struct device_node *np) |
4242 | { | |
4243 | const char *pm; | |
ba4f46b2 | 4244 | int err, i; |
d48f62b9 | 4245 | |
ba4f46b2 RM |
4246 | err = of_property_read_string(np, "nand-ecc-algo", &pm); |
4247 | if (!err) { | |
4248 | for (i = NAND_ECC_HAMMING; i < ARRAY_SIZE(nand_ecc_algos); i++) | |
4249 | if (!strcasecmp(pm, nand_ecc_algos[i])) | |
4250 | return i; | |
4251 | return -ENODEV; | |
4252 | } | |
d48f62b9 BB |
4253 | |
4254 | /* | |
4255 | * For backward compatibility we also read "nand-ecc-mode" checking | |
4256 | * for some obsoleted values that were specifying ECC algorithm. | |
4257 | */ | |
4258 | err = of_property_read_string(np, "nand-ecc-mode", &pm); | |
4259 | if (err < 0) | |
4260 | return err; | |
4261 | ||
4262 | if (!strcasecmp(pm, "soft")) | |
4263 | return NAND_ECC_HAMMING; | |
4264 | else if (!strcasecmp(pm, "soft_bch")) | |
4265 | return NAND_ECC_BCH; | |
4266 | ||
4267 | return -ENODEV; | |
4268 | } | |
4269 | ||
4270 | static int of_get_nand_ecc_step_size(struct device_node *np) | |
4271 | { | |
4272 | int ret; | |
4273 | u32 val; | |
4274 | ||
4275 | ret = of_property_read_u32(np, "nand-ecc-step-size", &val); | |
4276 | return ret ? ret : val; | |
4277 | } | |
4278 | ||
4279 | static int of_get_nand_ecc_strength(struct device_node *np) | |
4280 | { | |
4281 | int ret; | |
4282 | u32 val; | |
4283 | ||
4284 | ret = of_property_read_u32(np, "nand-ecc-strength", &val); | |
4285 | return ret ? ret : val; | |
4286 | } | |
4287 | ||
4288 | static int of_get_nand_bus_width(struct device_node *np) | |
4289 | { | |
4290 | u32 val; | |
4291 | ||
4292 | if (of_property_read_u32(np, "nand-bus-width", &val)) | |
4293 | return 8; | |
4294 | ||
4295 | switch (val) { | |
4296 | case 8: | |
4297 | case 16: | |
4298 | return val; | |
4299 | default: | |
4300 | return -EIO; | |
4301 | } | |
4302 | } | |
4303 | ||
4304 | static bool of_get_nand_on_flash_bbt(struct device_node *np) | |
4305 | { | |
4306 | return of_property_read_bool(np, "nand-on-flash-bbt"); | |
4307 | } | |
4308 | ||
7194a29a | 4309 | static int nand_dt_init(struct nand_chip *chip) |
5844feea | 4310 | { |
7194a29a | 4311 | struct device_node *dn = nand_get_flash_node(chip); |
79082457 | 4312 | int ecc_mode, ecc_algo, ecc_strength, ecc_step; |
5844feea | 4313 | |
7194a29a BB |
4314 | if (!dn) |
4315 | return 0; | |
4316 | ||
5844feea BN |
4317 | if (of_get_nand_bus_width(dn) == 16) |
4318 | chip->options |= NAND_BUSWIDTH_16; | |
4319 | ||
4320 | if (of_get_nand_on_flash_bbt(dn)) | |
4321 | chip->bbt_options |= NAND_BBT_USE_FLASH; | |
4322 | ||
4323 | ecc_mode = of_get_nand_ecc_mode(dn); | |
79082457 | 4324 | ecc_algo = of_get_nand_ecc_algo(dn); |
5844feea BN |
4325 | ecc_strength = of_get_nand_ecc_strength(dn); |
4326 | ecc_step = of_get_nand_ecc_step_size(dn); | |
4327 | ||
5844feea BN |
4328 | if (ecc_mode >= 0) |
4329 | chip->ecc.mode = ecc_mode; | |
4330 | ||
79082457 RM |
4331 | if (ecc_algo >= 0) |
4332 | chip->ecc.algo = ecc_algo; | |
4333 | ||
5844feea BN |
4334 | if (ecc_strength >= 0) |
4335 | chip->ecc.strength = ecc_strength; | |
4336 | ||
4337 | if (ecc_step > 0) | |
4338 | chip->ecc.size = ecc_step; | |
4339 | ||
ba78ee00 BB |
4340 | if (of_property_read_bool(dn, "nand-ecc-maximize")) |
4341 | chip->ecc.options |= NAND_ECC_MAXIMIZE; | |
4342 | ||
5844feea BN |
4343 | return 0; |
4344 | } | |
4345 | ||
7aa65bfd | 4346 | /** |
3b85c321 | 4347 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
8b6e50c9 BN |
4348 | * @mtd: MTD device structure |
4349 | * @maxchips: number of chips to scan for | |
4350 | * @table: alternative NAND ID table | |
7aa65bfd | 4351 | * |
8b6e50c9 BN |
4352 | * This is the first phase of the normal nand_scan() function. It reads the |
4353 | * flash ID and sets up MTD fields accordingly. | |
7aa65bfd TG |
4354 | * |
4355 | */ | |
5e81e88a DW |
4356 | int nand_scan_ident(struct mtd_info *mtd, int maxchips, |
4357 | struct nand_flash_dev *table) | |
7aa65bfd | 4358 | { |
bb77082f | 4359 | int i, nand_maf_id, nand_dev_id; |
862eba51 | 4360 | struct nand_chip *chip = mtd_to_nand(mtd); |
5844feea BN |
4361 | int ret; |
4362 | ||
7194a29a BB |
4363 | ret = nand_dt_init(chip); |
4364 | if (ret) | |
4365 | return ret; | |
7aa65bfd | 4366 | |
f7a8e38f BN |
4367 | if (!mtd->name && mtd->dev.parent) |
4368 | mtd->name = dev_name(mtd->dev.parent); | |
4369 | ||
76fe334f AS |
4370 | if ((!chip->cmdfunc || !chip->select_chip) && !chip->cmd_ctrl) { |
4371 | /* | |
4372 | * Default functions assigned for chip_select() and | |
4373 | * cmdfunc() both expect cmd_ctrl() to be populated, | |
4374 | * so we need to check that that's the case | |
4375 | */ | |
4376 | pr_err("chip.cmd_ctrl() callback is not provided"); | |
4377 | return -EINVAL; | |
4378 | } | |
7aa65bfd | 4379 | /* Set the default functions */ |
29a198a1 | 4380 | nand_set_defaults(chip); |
7aa65bfd TG |
4381 | |
4382 | /* Read the flash type */ | |
7bb42799 | 4383 | ret = nand_detect(chip, table); |
4722c0e9 | 4384 | if (ret) { |
b1c6e6db | 4385 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
d0370219 | 4386 | pr_warn("No NAND device found\n"); |
ace4dfee | 4387 | chip->select_chip(mtd, -1); |
4722c0e9 | 4388 | return ret; |
1da177e4 LT |
4389 | } |
4390 | ||
73f907fd | 4391 | /* Initialize the ->data_interface field. */ |
d8e725dd BB |
4392 | ret = nand_init_data_interface(chip); |
4393 | if (ret) | |
78771049 | 4394 | goto err_nand_init; |
d8e725dd | 4395 | |
73f907fd BB |
4396 | /* |
4397 | * Setup the data interface correctly on the chip and controller side. | |
4398 | * This explicit call to nand_setup_data_interface() is only required | |
4399 | * for the first die, because nand_reset() has been called before | |
4400 | * ->data_interface and ->default_onfi_timing_mode were set. | |
4401 | * For the other dies, nand_reset() will automatically switch to the | |
4402 | * best mode for us. | |
4403 | */ | |
104e442a | 4404 | ret = nand_setup_data_interface(chip, 0); |
73f907fd | 4405 | if (ret) |
78771049 | 4406 | goto err_nand_init; |
73f907fd | 4407 | |
7f501f0a BB |
4408 | nand_maf_id = chip->id.data[0]; |
4409 | nand_dev_id = chip->id.data[1]; | |
4410 | ||
07300164 HS |
4411 | chip->select_chip(mtd, -1); |
4412 | ||
7aa65bfd | 4413 | /* Check for a chip array */ |
e0c7d767 | 4414 | for (i = 1; i < maxchips; i++) { |
ef89a880 | 4415 | /* See comment in nand_get_flash_type for reset */ |
73f907fd BB |
4416 | nand_reset(chip, i); |
4417 | ||
4418 | chip->select_chip(mtd, i); | |
1da177e4 | 4419 | /* Send the command for reading device ID */ |
ace4dfee | 4420 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 4421 | /* Read manufacturer and device IDs */ |
ace4dfee | 4422 | if (nand_maf_id != chip->read_byte(mtd) || |
07300164 HS |
4423 | nand_dev_id != chip->read_byte(mtd)) { |
4424 | chip->select_chip(mtd, -1); | |
1da177e4 | 4425 | break; |
07300164 HS |
4426 | } |
4427 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
4428 | } |
4429 | if (i > 1) | |
20171642 | 4430 | pr_info("%d chips detected\n", i); |
61b03bd7 | 4431 | |
1da177e4 | 4432 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
4433 | chip->numchips = i; |
4434 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 4435 | |
3b85c321 | 4436 | return 0; |
78771049 BN |
4437 | |
4438 | err_nand_init: | |
4439 | /* Free manufacturer priv data. */ | |
4440 | nand_manufacturer_cleanup(chip); | |
4441 | ||
4442 | return ret; | |
3b85c321 | 4443 | } |
7351d3a5 | 4444 | EXPORT_SYMBOL(nand_scan_ident); |
3b85c321 | 4445 | |
06f384c9 RM |
4446 | static int nand_set_ecc_soft_ops(struct mtd_info *mtd) |
4447 | { | |
4448 | struct nand_chip *chip = mtd_to_nand(mtd); | |
4449 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
4450 | ||
e4225ae8 | 4451 | if (WARN_ON(ecc->mode != NAND_ECC_SOFT)) |
06f384c9 RM |
4452 | return -EINVAL; |
4453 | ||
4454 | switch (ecc->algo) { | |
4455 | case NAND_ECC_HAMMING: | |
4456 | ecc->calculate = nand_calculate_ecc; | |
4457 | ecc->correct = nand_correct_data; | |
4458 | ecc->read_page = nand_read_page_swecc; | |
4459 | ecc->read_subpage = nand_read_subpage; | |
4460 | ecc->write_page = nand_write_page_swecc; | |
4461 | ecc->read_page_raw = nand_read_page_raw; | |
4462 | ecc->write_page_raw = nand_write_page_raw; | |
4463 | ecc->read_oob = nand_read_oob_std; | |
4464 | ecc->write_oob = nand_write_oob_std; | |
4465 | if (!ecc->size) | |
4466 | ecc->size = 256; | |
4467 | ecc->bytes = 3; | |
4468 | ecc->strength = 1; | |
4469 | return 0; | |
4470 | case NAND_ECC_BCH: | |
4471 | if (!mtd_nand_has_bch()) { | |
4472 | WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n"); | |
4473 | return -EINVAL; | |
4474 | } | |
4475 | ecc->calculate = nand_bch_calculate_ecc; | |
4476 | ecc->correct = nand_bch_correct_data; | |
4477 | ecc->read_page = nand_read_page_swecc; | |
4478 | ecc->read_subpage = nand_read_subpage; | |
4479 | ecc->write_page = nand_write_page_swecc; | |
4480 | ecc->read_page_raw = nand_read_page_raw; | |
4481 | ecc->write_page_raw = nand_write_page_raw; | |
4482 | ecc->read_oob = nand_read_oob_std; | |
4483 | ecc->write_oob = nand_write_oob_std; | |
8bbba481 | 4484 | |
06f384c9 RM |
4485 | /* |
4486 | * Board driver should supply ecc.size and ecc.strength | |
4487 | * values to select how many bits are correctable. | |
4488 | * Otherwise, default to 4 bits for large page devices. | |
4489 | */ | |
4490 | if (!ecc->size && (mtd->oobsize >= 64)) { | |
4491 | ecc->size = 512; | |
4492 | ecc->strength = 4; | |
4493 | } | |
4494 | ||
4495 | /* | |
4496 | * if no ecc placement scheme was provided pickup the default | |
4497 | * large page one. | |
4498 | */ | |
4499 | if (!mtd->ooblayout) { | |
4500 | /* handle large page devices only */ | |
4501 | if (mtd->oobsize < 64) { | |
4502 | WARN(1, "OOB layout is required when using software BCH on small pages\n"); | |
4503 | return -EINVAL; | |
4504 | } | |
4505 | ||
4506 | mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops); | |
8bbba481 BB |
4507 | |
4508 | } | |
4509 | ||
4510 | /* | |
4511 | * We can only maximize ECC config when the default layout is | |
4512 | * used, otherwise we don't know how many bytes can really be | |
4513 | * used. | |
4514 | */ | |
4515 | if (mtd->ooblayout == &nand_ooblayout_lp_ops && | |
4516 | ecc->options & NAND_ECC_MAXIMIZE) { | |
4517 | int steps, bytes; | |
4518 | ||
4519 | /* Always prefer 1k blocks over 512bytes ones */ | |
4520 | ecc->size = 1024; | |
4521 | steps = mtd->writesize / ecc->size; | |
4522 | ||
4523 | /* Reserve 2 bytes for the BBM */ | |
4524 | bytes = (mtd->oobsize - 2) / steps; | |
4525 | ecc->strength = bytes * 8 / fls(8 * ecc->size); | |
06f384c9 RM |
4526 | } |
4527 | ||
4528 | /* See nand_bch_init() for details. */ | |
4529 | ecc->bytes = 0; | |
4530 | ecc->priv = nand_bch_init(mtd); | |
4531 | if (!ecc->priv) { | |
4532 | WARN(1, "BCH ECC initialization failed!\n"); | |
4533 | return -EINVAL; | |
4534 | } | |
4535 | return 0; | |
4536 | default: | |
4537 | WARN(1, "Unsupported ECC algorithm!\n"); | |
4538 | return -EINVAL; | |
4539 | } | |
4540 | } | |
4541 | ||
2c8f8afa MY |
4542 | /** |
4543 | * nand_check_ecc_caps - check the sanity of preset ECC settings | |
4544 | * @chip: nand chip info structure | |
4545 | * @caps: ECC caps info structure | |
4546 | * @oobavail: OOB size that the ECC engine can use | |
4547 | * | |
4548 | * When ECC step size and strength are already set, check if they are supported | |
4549 | * by the controller and the calculated ECC bytes fit within the chip's OOB. | |
4550 | * On success, the calculated ECC bytes is set. | |
4551 | */ | |
4552 | int nand_check_ecc_caps(struct nand_chip *chip, | |
4553 | const struct nand_ecc_caps *caps, int oobavail) | |
4554 | { | |
4555 | struct mtd_info *mtd = nand_to_mtd(chip); | |
4556 | const struct nand_ecc_step_info *stepinfo; | |
4557 | int preset_step = chip->ecc.size; | |
4558 | int preset_strength = chip->ecc.strength; | |
4559 | int nsteps, ecc_bytes; | |
4560 | int i, j; | |
4561 | ||
4562 | if (WARN_ON(oobavail < 0)) | |
4563 | return -EINVAL; | |
4564 | ||
4565 | if (!preset_step || !preset_strength) | |
4566 | return -ENODATA; | |
4567 | ||
4568 | nsteps = mtd->writesize / preset_step; | |
4569 | ||
4570 | for (i = 0; i < caps->nstepinfos; i++) { | |
4571 | stepinfo = &caps->stepinfos[i]; | |
4572 | ||
4573 | if (stepinfo->stepsize != preset_step) | |
4574 | continue; | |
4575 | ||
4576 | for (j = 0; j < stepinfo->nstrengths; j++) { | |
4577 | if (stepinfo->strengths[j] != preset_strength) | |
4578 | continue; | |
4579 | ||
4580 | ecc_bytes = caps->calc_ecc_bytes(preset_step, | |
4581 | preset_strength); | |
4582 | if (WARN_ON_ONCE(ecc_bytes < 0)) | |
4583 | return ecc_bytes; | |
4584 | ||
4585 | if (ecc_bytes * nsteps > oobavail) { | |
4586 | pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB", | |
4587 | preset_step, preset_strength); | |
4588 | return -ENOSPC; | |
4589 | } | |
4590 | ||
4591 | chip->ecc.bytes = ecc_bytes; | |
4592 | ||
4593 | return 0; | |
4594 | } | |
4595 | } | |
4596 | ||
4597 | pr_err("ECC (step, strength) = (%d, %d) not supported on this controller", | |
4598 | preset_step, preset_strength); | |
4599 | ||
4600 | return -ENOTSUPP; | |
4601 | } | |
4602 | EXPORT_SYMBOL_GPL(nand_check_ecc_caps); | |
4603 | ||
4604 | /** | |
4605 | * nand_match_ecc_req - meet the chip's requirement with least ECC bytes | |
4606 | * @chip: nand chip info structure | |
4607 | * @caps: ECC engine caps info structure | |
4608 | * @oobavail: OOB size that the ECC engine can use | |
4609 | * | |
4610 | * If a chip's ECC requirement is provided, try to meet it with the least | |
4611 | * number of ECC bytes (i.e. with the largest number of OOB-free bytes). | |
4612 | * On success, the chosen ECC settings are set. | |
4613 | */ | |
4614 | int nand_match_ecc_req(struct nand_chip *chip, | |
4615 | const struct nand_ecc_caps *caps, int oobavail) | |
4616 | { | |
4617 | struct mtd_info *mtd = nand_to_mtd(chip); | |
4618 | const struct nand_ecc_step_info *stepinfo; | |
4619 | int req_step = chip->ecc_step_ds; | |
4620 | int req_strength = chip->ecc_strength_ds; | |
4621 | int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total; | |
4622 | int best_step, best_strength, best_ecc_bytes; | |
4623 | int best_ecc_bytes_total = INT_MAX; | |
4624 | int i, j; | |
4625 | ||
4626 | if (WARN_ON(oobavail < 0)) | |
4627 | return -EINVAL; | |
4628 | ||
4629 | /* No information provided by the NAND chip */ | |
4630 | if (!req_step || !req_strength) | |
4631 | return -ENOTSUPP; | |
4632 | ||
4633 | /* number of correctable bits the chip requires in a page */ | |
4634 | req_corr = mtd->writesize / req_step * req_strength; | |
4635 | ||
4636 | for (i = 0; i < caps->nstepinfos; i++) { | |
4637 | stepinfo = &caps->stepinfos[i]; | |
4638 | step_size = stepinfo->stepsize; | |
4639 | ||
4640 | for (j = 0; j < stepinfo->nstrengths; j++) { | |
4641 | strength = stepinfo->strengths[j]; | |
4642 | ||
4643 | /* | |
4644 | * If both step size and strength are smaller than the | |
4645 | * chip's requirement, it is not easy to compare the | |
4646 | * resulted reliability. | |
4647 | */ | |
4648 | if (step_size < req_step && strength < req_strength) | |
4649 | continue; | |
4650 | ||
4651 | if (mtd->writesize % step_size) | |
4652 | continue; | |
4653 | ||
4654 | nsteps = mtd->writesize / step_size; | |
4655 | ||
4656 | ecc_bytes = caps->calc_ecc_bytes(step_size, strength); | |
4657 | if (WARN_ON_ONCE(ecc_bytes < 0)) | |
4658 | continue; | |
4659 | ecc_bytes_total = ecc_bytes * nsteps; | |
4660 | ||
4661 | if (ecc_bytes_total > oobavail || | |
4662 | strength * nsteps < req_corr) | |
4663 | continue; | |
4664 | ||
4665 | /* | |
4666 | * We assume the best is to meet the chip's requrement | |
4667 | * with the least number of ECC bytes. | |
4668 | */ | |
4669 | if (ecc_bytes_total < best_ecc_bytes_total) { | |
4670 | best_ecc_bytes_total = ecc_bytes_total; | |
4671 | best_step = step_size; | |
4672 | best_strength = strength; | |
4673 | best_ecc_bytes = ecc_bytes; | |
4674 | } | |
4675 | } | |
4676 | } | |
4677 | ||
4678 | if (best_ecc_bytes_total == INT_MAX) | |
4679 | return -ENOTSUPP; | |
4680 | ||
4681 | chip->ecc.size = best_step; | |
4682 | chip->ecc.strength = best_strength; | |
4683 | chip->ecc.bytes = best_ecc_bytes; | |
4684 | ||
4685 | return 0; | |
4686 | } | |
4687 | EXPORT_SYMBOL_GPL(nand_match_ecc_req); | |
4688 | ||
4689 | /** | |
4690 | * nand_maximize_ecc - choose the max ECC strength available | |
4691 | * @chip: nand chip info structure | |
4692 | * @caps: ECC engine caps info structure | |
4693 | * @oobavail: OOB size that the ECC engine can use | |
4694 | * | |
4695 | * Choose the max ECC strength that is supported on the controller, and can fit | |
4696 | * within the chip's OOB. On success, the chosen ECC settings are set. | |
4697 | */ | |
4698 | int nand_maximize_ecc(struct nand_chip *chip, | |
4699 | const struct nand_ecc_caps *caps, int oobavail) | |
4700 | { | |
4701 | struct mtd_info *mtd = nand_to_mtd(chip); | |
4702 | const struct nand_ecc_step_info *stepinfo; | |
4703 | int step_size, strength, nsteps, ecc_bytes, corr; | |
4704 | int best_corr = 0; | |
4705 | int best_step = 0; | |
4706 | int best_strength, best_ecc_bytes; | |
4707 | int i, j; | |
4708 | ||
4709 | if (WARN_ON(oobavail < 0)) | |
4710 | return -EINVAL; | |
4711 | ||
4712 | for (i = 0; i < caps->nstepinfos; i++) { | |
4713 | stepinfo = &caps->stepinfos[i]; | |
4714 | step_size = stepinfo->stepsize; | |
4715 | ||
4716 | /* If chip->ecc.size is already set, respect it */ | |
4717 | if (chip->ecc.size && step_size != chip->ecc.size) | |
4718 | continue; | |
4719 | ||
4720 | for (j = 0; j < stepinfo->nstrengths; j++) { | |
4721 | strength = stepinfo->strengths[j]; | |
4722 | ||
4723 | if (mtd->writesize % step_size) | |
4724 | continue; | |
4725 | ||
4726 | nsteps = mtd->writesize / step_size; | |
4727 | ||
4728 | ecc_bytes = caps->calc_ecc_bytes(step_size, strength); | |
4729 | if (WARN_ON_ONCE(ecc_bytes < 0)) | |
4730 | continue; | |
4731 | ||
4732 | if (ecc_bytes * nsteps > oobavail) | |
4733 | continue; | |
4734 | ||
4735 | corr = strength * nsteps; | |
4736 | ||
4737 | /* | |
4738 | * If the number of correctable bits is the same, | |
4739 | * bigger step_size has more reliability. | |
4740 | */ | |
4741 | if (corr > best_corr || | |
4742 | (corr == best_corr && step_size > best_step)) { | |
4743 | best_corr = corr; | |
4744 | best_step = step_size; | |
4745 | best_strength = strength; | |
4746 | best_ecc_bytes = ecc_bytes; | |
4747 | } | |
4748 | } | |
4749 | } | |
4750 | ||
4751 | if (!best_corr) | |
4752 | return -ENOTSUPP; | |
4753 | ||
4754 | chip->ecc.size = best_step; | |
4755 | chip->ecc.strength = best_strength; | |
4756 | chip->ecc.bytes = best_ecc_bytes; | |
4757 | ||
4758 | return 0; | |
4759 | } | |
4760 | EXPORT_SYMBOL_GPL(nand_maximize_ecc); | |
4761 | ||
67a9ad9b EG |
4762 | /* |
4763 | * Check if the chip configuration meet the datasheet requirements. | |
4764 | ||
4765 | * If our configuration corrects A bits per B bytes and the minimum | |
4766 | * required correction level is X bits per Y bytes, then we must ensure | |
4767 | * both of the following are true: | |
4768 | * | |
4769 | * (1) A / B >= X / Y | |
4770 | * (2) A >= X | |
4771 | * | |
4772 | * Requirement (1) ensures we can correct for the required bitflip density. | |
4773 | * Requirement (2) ensures we can correct even when all bitflips are clumped | |
4774 | * in the same sector. | |
4775 | */ | |
4776 | static bool nand_ecc_strength_good(struct mtd_info *mtd) | |
4777 | { | |
862eba51 | 4778 | struct nand_chip *chip = mtd_to_nand(mtd); |
67a9ad9b EG |
4779 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
4780 | int corr, ds_corr; | |
4781 | ||
4782 | if (ecc->size == 0 || chip->ecc_step_ds == 0) | |
4783 | /* Not enough information */ | |
4784 | return true; | |
4785 | ||
4786 | /* | |
4787 | * We get the number of corrected bits per page to compare | |
4788 | * the correction density. | |
4789 | */ | |
4790 | corr = (mtd->writesize * ecc->strength) / ecc->size; | |
4791 | ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds; | |
4792 | ||
4793 | return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds; | |
4794 | } | |
3b85c321 | 4795 | |
3371d663 MG |
4796 | static bool invalid_ecc_page_accessors(struct nand_chip *chip) |
4797 | { | |
4798 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
4799 | ||
4800 | if (nand_standard_page_accessors(ecc)) | |
4801 | return false; | |
4802 | ||
4803 | /* | |
4804 | * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND | |
4805 | * controller driver implements all the page accessors because | |
4806 | * default helpers are not suitable when the core does not | |
4807 | * send the READ0/PAGEPROG commands. | |
4808 | */ | |
4809 | return (!ecc->read_page || !ecc->write_page || | |
4810 | !ecc->read_page_raw || !ecc->write_page_raw || | |
4811 | (NAND_HAS_SUBPAGE_READ(chip) && !ecc->read_subpage) || | |
4812 | (NAND_HAS_SUBPAGE_WRITE(chip) && !ecc->write_subpage && | |
4813 | ecc->hwctl && ecc->calculate)); | |
4814 | } | |
4815 | ||
3b85c321 DW |
4816 | /** |
4817 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
8b6e50c9 | 4818 | * @mtd: MTD device structure |
3b85c321 | 4819 | * |
8b6e50c9 BN |
4820 | * This is the second phase of the normal nand_scan() function. It fills out |
4821 | * all the uninitialized function pointers with the defaults and scans for a | |
4822 | * bad block table if appropriate. | |
3b85c321 DW |
4823 | */ |
4824 | int nand_scan_tail(struct mtd_info *mtd) | |
4825 | { | |
862eba51 | 4826 | struct nand_chip *chip = mtd_to_nand(mtd); |
97de79e0 | 4827 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
3deb9979 | 4828 | struct nand_buffers *nbuf = NULL; |
11eaf6df | 4829 | int ret; |
3b85c321 | 4830 | |
e2414f4c | 4831 | /* New bad blocks should be marked in OOB, flash-based BBT, or both */ |
11eaf6df | 4832 | if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && |
78771049 BN |
4833 | !(chip->bbt_options & NAND_BBT_USE_FLASH))) { |
4834 | ret = -EINVAL; | |
4835 | goto err_ident; | |
4836 | } | |
e2414f4c | 4837 | |
3371d663 MG |
4838 | if (invalid_ecc_page_accessors(chip)) { |
4839 | pr_err("Invalid ECC page accessors setup\n"); | |
78771049 BN |
4840 | ret = -EINVAL; |
4841 | goto err_ident; | |
3371d663 MG |
4842 | } |
4843 | ||
f02ea4e6 | 4844 | if (!(chip->options & NAND_OWN_BUFFERS)) { |
3deb9979 | 4845 | nbuf = kzalloc(sizeof(*nbuf), GFP_KERNEL); |
78771049 BN |
4846 | if (!nbuf) { |
4847 | ret = -ENOMEM; | |
4848 | goto err_ident; | |
4849 | } | |
3deb9979 MY |
4850 | |
4851 | nbuf->ecccalc = kmalloc(mtd->oobsize, GFP_KERNEL); | |
4852 | if (!nbuf->ecccalc) { | |
4853 | ret = -ENOMEM; | |
4854 | goto err_free; | |
4855 | } | |
4856 | ||
4857 | nbuf->ecccode = kmalloc(mtd->oobsize, GFP_KERNEL); | |
4858 | if (!nbuf->ecccode) { | |
4859 | ret = -ENOMEM; | |
4860 | goto err_free; | |
4861 | } | |
4862 | ||
4863 | nbuf->databuf = kmalloc(mtd->writesize + mtd->oobsize, | |
4864 | GFP_KERNEL); | |
4865 | if (!nbuf->databuf) { | |
4866 | ret = -ENOMEM; | |
4867 | goto err_free; | |
4868 | } | |
f02ea4e6 HS |
4869 | |
4870 | chip->buffers = nbuf; | |
4871 | } else { | |
78771049 BN |
4872 | if (!chip->buffers) { |
4873 | ret = -ENOMEM; | |
4874 | goto err_ident; | |
4875 | } | |
f02ea4e6 | 4876 | } |
4bf63fcb | 4877 | |
7dcdcbef | 4878 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 4879 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 4880 | |
7aa65bfd | 4881 | /* |
8b6e50c9 | 4882 | * If no default placement scheme is given, select an appropriate one. |
7aa65bfd | 4883 | */ |
06f384c9 | 4884 | if (!mtd->ooblayout && |
e4225ae8 | 4885 | !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_BCH)) { |
61b03bd7 | 4886 | switch (mtd->oobsize) { |
1da177e4 | 4887 | case 8: |
1da177e4 | 4888 | case 16: |
41b207a7 | 4889 | mtd_set_ooblayout(mtd, &nand_ooblayout_sp_ops); |
1da177e4 LT |
4890 | break; |
4891 | case 64: | |
81ec5364 | 4892 | case 128: |
6a623e07 | 4893 | mtd_set_ooblayout(mtd, &nand_ooblayout_lp_hamming_ops); |
81ec5364 | 4894 | break; |
1da177e4 | 4895 | default: |
11eaf6df EG |
4896 | WARN(1, "No oob scheme defined for oobsize %d\n", |
4897 | mtd->oobsize); | |
4898 | ret = -EINVAL; | |
4899 | goto err_free; | |
1da177e4 LT |
4900 | } |
4901 | } | |
61b03bd7 | 4902 | |
61b03bd7 | 4903 | /* |
8b6e50c9 | 4904 | * Check ECC mode, default to software if 3byte/512byte hardware ECC is |
7aa65bfd | 4905 | * selected and we have 256 byte pagesize fallback to software ECC |
e0c7d767 | 4906 | */ |
956e944c | 4907 | |
97de79e0 | 4908 | switch (ecc->mode) { |
6e0cb135 SN |
4909 | case NAND_ECC_HW_OOB_FIRST: |
4910 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
97de79e0 | 4911 | if (!ecc->calculate || !ecc->correct || !ecc->hwctl) { |
11eaf6df EG |
4912 | WARN(1, "No ECC functions supplied; hardware ECC not possible\n"); |
4913 | ret = -EINVAL; | |
4914 | goto err_free; | |
6e0cb135 | 4915 | } |
97de79e0 HS |
4916 | if (!ecc->read_page) |
4917 | ecc->read_page = nand_read_page_hwecc_oob_first; | |
6e0cb135 | 4918 | |
6dfc6d25 | 4919 | case NAND_ECC_HW: |
8b6e50c9 | 4920 | /* Use standard hwecc read page function? */ |
97de79e0 HS |
4921 | if (!ecc->read_page) |
4922 | ecc->read_page = nand_read_page_hwecc; | |
4923 | if (!ecc->write_page) | |
4924 | ecc->write_page = nand_write_page_hwecc; | |
4925 | if (!ecc->read_page_raw) | |
4926 | ecc->read_page_raw = nand_read_page_raw; | |
4927 | if (!ecc->write_page_raw) | |
4928 | ecc->write_page_raw = nand_write_page_raw; | |
4929 | if (!ecc->read_oob) | |
4930 | ecc->read_oob = nand_read_oob_std; | |
4931 | if (!ecc->write_oob) | |
4932 | ecc->write_oob = nand_write_oob_std; | |
4933 | if (!ecc->read_subpage) | |
4934 | ecc->read_subpage = nand_read_subpage; | |
44991b3d | 4935 | if (!ecc->write_subpage && ecc->hwctl && ecc->calculate) |
97de79e0 | 4936 | ecc->write_subpage = nand_write_subpage_hwecc; |
f5bbdacc | 4937 | |
6dfc6d25 | 4938 | case NAND_ECC_HW_SYNDROME: |
97de79e0 HS |
4939 | if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && |
4940 | (!ecc->read_page || | |
4941 | ecc->read_page == nand_read_page_hwecc || | |
4942 | !ecc->write_page || | |
4943 | ecc->write_page == nand_write_page_hwecc)) { | |
11eaf6df EG |
4944 | WARN(1, "No ECC functions supplied; hardware ECC not possible\n"); |
4945 | ret = -EINVAL; | |
4946 | goto err_free; | |
6dfc6d25 | 4947 | } |
8b6e50c9 | 4948 | /* Use standard syndrome read/write page function? */ |
97de79e0 HS |
4949 | if (!ecc->read_page) |
4950 | ecc->read_page = nand_read_page_syndrome; | |
4951 | if (!ecc->write_page) | |
4952 | ecc->write_page = nand_write_page_syndrome; | |
4953 | if (!ecc->read_page_raw) | |
4954 | ecc->read_page_raw = nand_read_page_raw_syndrome; | |
4955 | if (!ecc->write_page_raw) | |
4956 | ecc->write_page_raw = nand_write_page_raw_syndrome; | |
4957 | if (!ecc->read_oob) | |
4958 | ecc->read_oob = nand_read_oob_syndrome; | |
4959 | if (!ecc->write_oob) | |
4960 | ecc->write_oob = nand_write_oob_syndrome; | |
4961 | ||
4962 | if (mtd->writesize >= ecc->size) { | |
4963 | if (!ecc->strength) { | |
11eaf6df EG |
4964 | WARN(1, "Driver must set ecc.strength when using hardware ECC\n"); |
4965 | ret = -EINVAL; | |
4966 | goto err_free; | |
e2788c98 | 4967 | } |
6dfc6d25 | 4968 | break; |
e2788c98 | 4969 | } |
2ac63d90 RM |
4970 | pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", |
4971 | ecc->size, mtd->writesize); | |
97de79e0 | 4972 | ecc->mode = NAND_ECC_SOFT; |
e9d4faed | 4973 | ecc->algo = NAND_ECC_HAMMING; |
61b03bd7 | 4974 | |
6dfc6d25 | 4975 | case NAND_ECC_SOFT: |
06f384c9 RM |
4976 | ret = nand_set_ecc_soft_ops(mtd); |
4977 | if (ret) { | |
11eaf6df EG |
4978 | ret = -EINVAL; |
4979 | goto err_free; | |
193bd400 ID |
4980 | } |
4981 | break; | |
4982 | ||
785818fa TP |
4983 | case NAND_ECC_ON_DIE: |
4984 | if (!ecc->read_page || !ecc->write_page) { | |
4985 | WARN(1, "No ECC functions supplied; on-die ECC not possible\n"); | |
4986 | ret = -EINVAL; | |
4987 | goto err_free; | |
4988 | } | |
4989 | if (!ecc->read_oob) | |
4990 | ecc->read_oob = nand_read_oob_std; | |
4991 | if (!ecc->write_oob) | |
4992 | ecc->write_oob = nand_write_oob_std; | |
4993 | break; | |
4994 | ||
61b03bd7 | 4995 | case NAND_ECC_NONE: |
2ac63d90 | 4996 | pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n"); |
97de79e0 HS |
4997 | ecc->read_page = nand_read_page_raw; |
4998 | ecc->write_page = nand_write_page_raw; | |
4999 | ecc->read_oob = nand_read_oob_std; | |
5000 | ecc->read_page_raw = nand_read_page_raw; | |
5001 | ecc->write_page_raw = nand_write_page_raw; | |
5002 | ecc->write_oob = nand_write_oob_std; | |
5003 | ecc->size = mtd->writesize; | |
5004 | ecc->bytes = 0; | |
5005 | ecc->strength = 0; | |
1da177e4 | 5006 | break; |
956e944c | 5007 | |
1da177e4 | 5008 | default: |
11eaf6df EG |
5009 | WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->mode); |
5010 | ret = -EINVAL; | |
5011 | goto err_free; | |
1da177e4 | 5012 | } |
61b03bd7 | 5013 | |
9ce244b3 | 5014 | /* For many systems, the standard OOB write also works for raw */ |
97de79e0 HS |
5015 | if (!ecc->read_oob_raw) |
5016 | ecc->read_oob_raw = ecc->read_oob; | |
5017 | if (!ecc->write_oob_raw) | |
5018 | ecc->write_oob_raw = ecc->write_oob; | |
9ce244b3 | 5019 | |
846031d3 | 5020 | /* propagate ecc info to mtd_info */ |
846031d3 BB |
5021 | mtd->ecc_strength = ecc->strength; |
5022 | mtd->ecc_step_size = ecc->size; | |
67a9ad9b | 5023 | |
7aa65bfd TG |
5024 | /* |
5025 | * Set the number of read / write steps for one page depending on ECC | |
8b6e50c9 | 5026 | * mode. |
7aa65bfd | 5027 | */ |
97de79e0 HS |
5028 | ecc->steps = mtd->writesize / ecc->size; |
5029 | if (ecc->steps * ecc->size != mtd->writesize) { | |
11eaf6df EG |
5030 | WARN(1, "Invalid ECC parameters\n"); |
5031 | ret = -EINVAL; | |
5032 | goto err_free; | |
1da177e4 | 5033 | } |
97de79e0 | 5034 | ecc->total = ecc->steps * ecc->bytes; |
79e0348c MY |
5035 | if (ecc->total > mtd->oobsize) { |
5036 | WARN(1, "Total number of ECC bytes exceeded oobsize\n"); | |
5037 | ret = -EINVAL; | |
5038 | goto err_free; | |
5039 | } | |
61b03bd7 | 5040 | |
846031d3 BB |
5041 | /* |
5042 | * The number of bytes available for a client to place data into | |
5043 | * the out of band area. | |
5044 | */ | |
5045 | ret = mtd_ooblayout_count_freebytes(mtd); | |
5046 | if (ret < 0) | |
5047 | ret = 0; | |
5048 | ||
5049 | mtd->oobavail = ret; | |
5050 | ||
5051 | /* ECC sanity check: warn if it's too weak */ | |
5052 | if (!nand_ecc_strength_good(mtd)) | |
5053 | pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n", | |
5054 | mtd->name); | |
5055 | ||
8b6e50c9 | 5056 | /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ |
1d0ed69d | 5057 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { |
97de79e0 | 5058 | switch (ecc->steps) { |
29072b96 TG |
5059 | case 2: |
5060 | mtd->subpage_sft = 1; | |
5061 | break; | |
5062 | case 4: | |
5063 | case 8: | |
81ec5364 | 5064 | case 16: |
29072b96 TG |
5065 | mtd->subpage_sft = 2; |
5066 | break; | |
5067 | } | |
5068 | } | |
5069 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
5070 | ||
04bbd0ea | 5071 | /* Initialize state */ |
ace4dfee | 5072 | chip->state = FL_READY; |
1da177e4 | 5073 | |
1da177e4 | 5074 | /* Invalidate the pagebuffer reference */ |
ace4dfee | 5075 | chip->pagebuf = -1; |
1da177e4 | 5076 | |
a5ff4f10 | 5077 | /* Large page NAND with SOFT_ECC should support subpage reads */ |
4007e2d1 RL |
5078 | switch (ecc->mode) { |
5079 | case NAND_ECC_SOFT: | |
4007e2d1 RL |
5080 | if (chip->page_shift > 9) |
5081 | chip->options |= NAND_SUBPAGE_READ; | |
5082 | break; | |
5083 | ||
5084 | default: | |
5085 | break; | |
5086 | } | |
a5ff4f10 | 5087 | |
1da177e4 | 5088 | /* Fill in remaining MTD driver data */ |
963d1c28 | 5089 | mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH; |
93edbad6 ML |
5090 | mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : |
5091 | MTD_CAP_NANDFLASH; | |
3c3c10bb AB |
5092 | mtd->_erase = nand_erase; |
5093 | mtd->_point = NULL; | |
5094 | mtd->_unpoint = NULL; | |
5095 | mtd->_read = nand_read; | |
5096 | mtd->_write = nand_write; | |
5097 | mtd->_panic_write = panic_nand_write; | |
5098 | mtd->_read_oob = nand_read_oob; | |
5099 | mtd->_write_oob = nand_write_oob; | |
5100 | mtd->_sync = nand_sync; | |
5101 | mtd->_lock = NULL; | |
5102 | mtd->_unlock = NULL; | |
5103 | mtd->_suspend = nand_suspend; | |
5104 | mtd->_resume = nand_resume; | |
72ea4036 | 5105 | mtd->_reboot = nand_shutdown; |
8471bb73 | 5106 | mtd->_block_isreserved = nand_block_isreserved; |
3c3c10bb AB |
5107 | mtd->_block_isbad = nand_block_isbad; |
5108 | mtd->_block_markbad = nand_block_markbad; | |
5671842f | 5109 | mtd->_max_bad_blocks = nand_max_bad_blocks; |
cbcab65a | 5110 | mtd->writebufsize = mtd->writesize; |
1da177e4 | 5111 | |
ea3b2ea2 SL |
5112 | /* |
5113 | * Initialize bitflip_threshold to its default prior scan_bbt() call. | |
5114 | * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be | |
5115 | * properly set. | |
5116 | */ | |
5117 | if (!mtd->bitflip_threshold) | |
240181fd | 5118 | mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4); |
1da177e4 | 5119 | |
0040bf38 | 5120 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 5121 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 5122 | return 0; |
1da177e4 LT |
5123 | |
5124 | /* Build bad block table */ | |
44d4182e BN |
5125 | ret = chip->scan_bbt(mtd); |
5126 | if (ret) | |
5127 | goto err_free; | |
5128 | return 0; | |
5129 | ||
11eaf6df | 5130 | err_free: |
3deb9979 MY |
5131 | if (nbuf) { |
5132 | kfree(nbuf->databuf); | |
5133 | kfree(nbuf->ecccode); | |
5134 | kfree(nbuf->ecccalc); | |
5135 | kfree(nbuf); | |
5136 | } | |
78771049 BN |
5137 | |
5138 | err_ident: | |
5139 | /* Clean up nand_scan_ident(). */ | |
5140 | ||
5141 | /* Free manufacturer priv data. */ | |
5142 | nand_manufacturer_cleanup(chip); | |
5143 | ||
11eaf6df | 5144 | return ret; |
1da177e4 | 5145 | } |
7351d3a5 | 5146 | EXPORT_SYMBOL(nand_scan_tail); |
1da177e4 | 5147 | |
8b6e50c9 BN |
5148 | /* |
5149 | * is_module_text_address() isn't exported, and it's mostly a pointless | |
7351d3a5 | 5150 | * test if this is a module _anyway_ -- they'd have to try _really_ hard |
8b6e50c9 BN |
5151 | * to call us from in-kernel code if the core NAND support is modular. |
5152 | */ | |
3b85c321 DW |
5153 | #ifdef MODULE |
5154 | #define caller_is_module() (1) | |
5155 | #else | |
5156 | #define caller_is_module() \ | |
a6e6abd5 | 5157 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
5158 | #endif |
5159 | ||
5160 | /** | |
5161 | * nand_scan - [NAND Interface] Scan for the NAND device | |
8b6e50c9 BN |
5162 | * @mtd: MTD device structure |
5163 | * @maxchips: number of chips to scan for | |
3b85c321 | 5164 | * |
8b6e50c9 BN |
5165 | * This fills out all the uninitialized function pointers with the defaults. |
5166 | * The flash ID is read and the mtd/chip structures are filled with the | |
20c07a5b | 5167 | * appropriate values. |
3b85c321 DW |
5168 | */ |
5169 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
5170 | { | |
5171 | int ret; | |
5172 | ||
5e81e88a | 5173 | ret = nand_scan_ident(mtd, maxchips, NULL); |
3b85c321 DW |
5174 | if (!ret) |
5175 | ret = nand_scan_tail(mtd); | |
5176 | return ret; | |
5177 | } | |
7351d3a5 | 5178 | EXPORT_SYMBOL(nand_scan); |
3b85c321 | 5179 | |
1da177e4 | 5180 | /** |
d44154f9 RW |
5181 | * nand_cleanup - [NAND Interface] Free resources held by the NAND device |
5182 | * @chip: NAND chip object | |
8b6e50c9 | 5183 | */ |
d44154f9 | 5184 | void nand_cleanup(struct nand_chip *chip) |
1da177e4 | 5185 | { |
e4225ae8 | 5186 | if (chip->ecc.mode == NAND_ECC_SOFT && |
06f384c9 | 5187 | chip->ecc.algo == NAND_ECC_BCH) |
193bd400 ID |
5188 | nand_bch_free((struct nand_bch_control *)chip->ecc.priv); |
5189 | ||
d8e725dd BB |
5190 | nand_release_data_interface(chip); |
5191 | ||
fa671646 | 5192 | /* Free bad block table memory */ |
ace4dfee | 5193 | kfree(chip->bbt); |
3deb9979 MY |
5194 | if (!(chip->options & NAND_OWN_BUFFERS) && chip->buffers) { |
5195 | kfree(chip->buffers->databuf); | |
5196 | kfree(chip->buffers->ecccode); | |
5197 | kfree(chip->buffers->ecccalc); | |
4bf63fcb | 5198 | kfree(chip->buffers); |
3deb9979 | 5199 | } |
58373ff0 BN |
5200 | |
5201 | /* Free bad block descriptor memory */ | |
5202 | if (chip->badblock_pattern && chip->badblock_pattern->options | |
5203 | & NAND_BBT_DYNAMICSTRUCT) | |
5204 | kfree(chip->badblock_pattern); | |
abbe26d1 BB |
5205 | |
5206 | /* Free manufacturer priv data. */ | |
5207 | nand_manufacturer_cleanup(chip); | |
1da177e4 | 5208 | } |
d44154f9 RW |
5209 | EXPORT_SYMBOL_GPL(nand_cleanup); |
5210 | ||
5211 | /** | |
5212 | * nand_release - [NAND Interface] Unregister the MTD device and free resources | |
5213 | * held by the NAND device | |
5214 | * @mtd: MTD device structure | |
5215 | */ | |
5216 | void nand_release(struct mtd_info *mtd) | |
5217 | { | |
5218 | mtd_device_unregister(mtd); | |
5219 | nand_cleanup(mtd_to_nand(mtd)); | |
5220 | } | |
e0c7d767 | 5221 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 | 5222 | |
e0c7d767 | 5223 | MODULE_LICENSE("GPL"); |
7351d3a5 FF |
5224 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); |
5225 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
e0c7d767 | 5226 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |