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mtd: cfi_cmdset_0002: Micron M29EW bugfixes as per TN-13-07
[mirror_ubuntu-hirsute-kernel.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
61b03bd7 8 *
1da177e4 9 * Additional technical information is available on
8b2b403c 10 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 11 *
1da177e4 12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 14 *
ace4dfee 15 * Credits:
61b03bd7
TG		 16 * David Woodhouse for adding multichip support
17 *
1da177e4
LT		 18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
ace4dfee 21 * TODO:
1da177e4
LT		 22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
7854d3f7 24 * if we have HW ECC support.
1da177e4
LT		 25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
c0b8ba7b 27 * BBT table is not serialized, has to be fixed
1da177e4 28 *
1da177e4
LT		 29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
552d9205 35#include <linux/module.h>
1da177e4
LT		 36#include <linux/delay.h>
37#include <linux/errno.h>
7aa65bfd 38#include <linux/err.h>
1da177e4
LT		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
193bd400 45#include <linux/mtd/nand_bch.h>
1da177e4
LT		 46#include <linux/interrupt.h>
47#include <linux/bitops.h>
8fe833c1 48#include <linux/leds.h>
7351d3a5 49#include <linux/io.h>
1da177e4 50#include <linux/mtd/partitions.h>
1da177e4
LT		 51
52/* Define default oob placement schemes for large and small page devices */
5bd34c09 53static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 54 .eccbytes = 3,
55 .eccpos = {0, 1, 2},
5bd34c09
TG		 56 .oobfree = {
57 {.offset = 3,
58 .length = 2},
59 {.offset = 6,
f8ac0414 60 .length = 2} }
1da177e4
LT		 61};
62
5bd34c09 63static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 64 .eccbytes = 6,
65 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 66 .oobfree = {
67 {.offset = 8,
f8ac0414 68 . length = 8} }
1da177e4
LT		 69};
70
5bd34c09 71static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 72 .eccbytes = 24,
73 .eccpos = {
e0c7d767
DW		 74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 77 .oobfree = {
78 {.offset = 2,
f8ac0414 79 .length = 38} }
1da177e4
LT		 80};
81
81ec5364
TG		 82static struct nand_ecclayout nand_oob_128 = {
83 .eccbytes = 48,
84 .eccpos = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
91 .oobfree = {
92 {.offset = 2,
f8ac0414 93 .length = 78} }
81ec5364
TG		 94};
95
ace4dfee 96static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
2c0a2bed 97 int new_state);
1da177e4 98
8593fbc6
TG		 99static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
100 struct mtd_oob_ops *ops);
101
d470a97c 102/*
8e87d782 103 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 104 * compiled away when LED support is disabled.
105 */
106DEFINE_LED_TRIGGER(nand_led_trigger);
107
6fe5a6ac
VS		 108static int check_offs_len(struct mtd_info *mtd,
109 loff_t ofs, uint64_t len)
110{
111 struct nand_chip *chip = mtd->priv;
112 int ret = 0;
113
114 /* Start address must align on block boundary */
115 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
289c0522 116 pr_debug("%s: unaligned address\n", __func__);
6fe5a6ac
VS		 117 ret = -EINVAL;
118 }
119
120 /* Length must align on block boundary */
121 if (len & ((1 << chip->phys_erase_shift) - 1)) {
289c0522 122 pr_debug("%s: length not block aligned\n", __func__);
6fe5a6ac
VS		 123 ret = -EINVAL;
124 }
125
6fe5a6ac
VS		 126 return ret;
127}
128
1da177e4
LT		 129/**
130 * nand_release_device - [GENERIC] release chip
8b6e50c9 131 * @mtd: MTD device structure
61b03bd7 132 *
8b6e50c9 133 * Deselect, release chip lock and wake up anyone waiting on the device.
1da177e4 134 */
e0c7d767 135static void nand_release_device(struct mtd_info *mtd)
1da177e4 136{
ace4dfee 137 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 138
139 /* De-select the NAND device */
ace4dfee 140 chip->select_chip(mtd, -1);
0dfc6246 141
a36ed299 142 /* Release the controller and the chip */
ace4dfee
TG		 143 spin_lock(&chip->controller->lock);
144 chip->controller->active = NULL;
145 chip->state = FL_READY;
146 wake_up(&chip->controller->wq);
147 spin_unlock(&chip->controller->lock);
1da177e4
LT		 148}
149
150/**
151 * nand_read_byte - [DEFAULT] read one byte from the chip
8b6e50c9 152 * @mtd: MTD device structure
1da177e4 153 *
7854d3f7 154 * Default read function for 8bit buswidth
1da177e4 155 */
58dd8f2b 156static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 157{
ace4dfee
TG		 158 struct nand_chip *chip = mtd->priv;
159 return readb(chip->IO_ADDR_R);
1da177e4
LT		 160}
161
1da177e4
LT		 162/**
163 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
7854d3f7 164 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
8b6e50c9 165 * @mtd: MTD device structure
1da177e4 166 *
7854d3f7
BN		 167 * Default read function for 16bit buswidth with endianness conversion.
168 *
1da177e4 169 */
58dd8f2b 170static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 171{
ace4dfee
TG		 172 struct nand_chip *chip = mtd->priv;
173 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 174}
175
1da177e4
LT		 176/**
177 * nand_read_word - [DEFAULT] read one word from the chip
8b6e50c9 178 * @mtd: MTD device structure
1da177e4 179 *
7854d3f7 180 * Default read function for 16bit buswidth without endianness conversion.
1da177e4
LT		 181 */
182static u16 nand_read_word(struct mtd_info *mtd)
183{
ace4dfee
TG		 184 struct nand_chip *chip = mtd->priv;
185 return readw(chip->IO_ADDR_R);
1da177e4
LT		 186}
187
1da177e4
LT		 188/**
189 * nand_select_chip - [DEFAULT] control CE line
8b6e50c9
BN		 190 * @mtd: MTD device structure
191 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 192 *
193 * Default select function for 1 chip devices.
194 */
ace4dfee 195static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 196{
ace4dfee
TG		 197 struct nand_chip *chip = mtd->priv;
198
199 switch (chipnr) {
1da177e4 200 case -1:
ace4dfee 201 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 202 break;
203 case 0:
1da177e4
LT		 204 break;
205
206 default:
207 BUG();
208 }
209}
210
211/**
212 * nand_write_buf - [DEFAULT] write buffer to chip
8b6e50c9
BN		 213 * @mtd: MTD device structure
214 * @buf: data buffer
215 * @len: number of bytes to write
1da177e4 216 *
7854d3f7 217 * Default write function for 8bit buswidth.
1da177e4 218 */
58dd8f2b 219static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 220{
221 int i;
ace4dfee 222 struct nand_chip *chip = mtd->priv;
1da177e4 223
e0c7d767 224 for (i = 0; i < len; i++)
ace4dfee 225 writeb(buf[i], chip->IO_ADDR_W);
1da177e4
LT		 226}
227
228/**
61b03bd7 229 * nand_read_buf - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 230 * @mtd: MTD device structure
231 * @buf: buffer to store date
232 * @len: number of bytes to read
1da177e4 233 *
7854d3f7 234 * Default read function for 8bit buswidth.
1da177e4 235 */
58dd8f2b 236static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 237{
238 int i;
ace4dfee 239 struct nand_chip *chip = mtd->priv;
1da177e4 240
e0c7d767 241 for (i = 0; i < len; i++)
ace4dfee 242 buf[i] = readb(chip->IO_ADDR_R);
1da177e4
LT		 243}
244
245/**
61b03bd7 246 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
8b6e50c9
BN		 247 * @mtd: MTD device structure
248 * @buf: buffer containing the data to compare
249 * @len: number of bytes to compare
1da177e4 250 *
7854d3f7 251 * Default verify function for 8bit buswidth.
1da177e4 252 */
58dd8f2b 253static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 254{
255 int i;
ace4dfee 256 struct nand_chip *chip = mtd->priv;
1da177e4 257
e0c7d767 258 for (i = 0; i < len; i++)
ace4dfee 259 if (buf[i] != readb(chip->IO_ADDR_R))
1da177e4 260 return -EFAULT;
1da177e4
LT		 261 return 0;
262}
263
264/**
265 * nand_write_buf16 - [DEFAULT] write buffer to chip
8b6e50c9
BN		 266 * @mtd: MTD device structure
267 * @buf: data buffer
268 * @len: number of bytes to write
1da177e4 269 *
7854d3f7 270 * Default write function for 16bit buswidth.
1da177e4 271 */
58dd8f2b 272static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 273{
274 int i;
ace4dfee 275 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 276 u16 *p = (u16 *) buf;
277 len >>= 1;
61b03bd7 278
e0c7d767 279 for (i = 0; i < len; i++)
ace4dfee 280 writew(p[i], chip->IO_ADDR_W);
61b03bd7 281
1da177e4
LT		 282}
283
284/**
61b03bd7 285 * nand_read_buf16 - [DEFAULT] read chip data into buffer
8b6e50c9
BN		 286 * @mtd: MTD device structure
287 * @buf: buffer to store date
288 * @len: number of bytes to read
1da177e4 289 *
7854d3f7 290 * Default read function for 16bit buswidth.
1da177e4 291 */
58dd8f2b 292static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 293{
294 int i;
ace4dfee 295 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 296 u16 *p = (u16 *) buf;
297 len >>= 1;
298
e0c7d767 299 for (i = 0; i < len; i++)
ace4dfee 300 p[i] = readw(chip->IO_ADDR_R);
1da177e4
LT		 301}
302
303/**
61b03bd7 304 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
8b6e50c9
BN		 305 * @mtd: MTD device structure
306 * @buf: buffer containing the data to compare
307 * @len: number of bytes to compare
1da177e4 308 *
7854d3f7 309 * Default verify function for 16bit buswidth.
1da177e4 310 */
58dd8f2b 311static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 312{
313 int i;
ace4dfee 314 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 315 u16 *p = (u16 *) buf;
316 len >>= 1;
317
e0c7d767 318 for (i = 0; i < len; i++)
ace4dfee 319 if (p[i] != readw(chip->IO_ADDR_R))
1da177e4
LT		 320 return -EFAULT;
321
322 return 0;
323}
324
325/**
326 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
8b6e50c9
BN		 327 * @mtd: MTD device structure
328 * @ofs: offset from device start
329 * @getchip: 0, if the chip is already selected
1da177e4 330 *
61b03bd7 331 * Check, if the block is bad.
1da177e4
LT		 332 */
333static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
334{
cdbec050 335 int page, chipnr, res = 0, i = 0;
ace4dfee 336 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 337 u16 bad;
338
5fb1549d 339 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 340 ofs += mtd->erasesize - mtd->writesize;
341
1a12f46a
TK		 342 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
343
1da177e4 344 if (getchip) {
ace4dfee 345 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 346
ace4dfee 347 nand_get_device(chip, mtd, FL_READING);
1da177e4
LT		 348
349 /* Select the NAND device */
ace4dfee 350 chip->select_chip(mtd, chipnr);
1a12f46a 351 }
1da177e4 352
cdbec050
BN		 353 do {
354 if (chip->options & NAND_BUSWIDTH_16) {
355 chip->cmdfunc(mtd, NAND_CMD_READOOB,
356 chip->badblockpos & 0xFE, page);
357 bad = cpu_to_le16(chip->read_word(mtd));
358 if (chip->badblockpos & 0x1)
359 bad >>= 8;
360 else
361 bad &= 0xFF;
362 } else {
363 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
364 page);
365 bad = chip->read_byte(mtd);
366 }
367
368 if (likely(chip->badblockbits == 8))
369 res = bad != 0xFF;
e0b58d0a 370 else
cdbec050
BN		 371 res = hweight8(bad) < chip->badblockbits;
372 ofs += mtd->writesize;
373 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
374 i++;
375 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
e0b58d0a 376
ace4dfee 377 if (getchip)
1da177e4 378 nand_release_device(mtd);
61b03bd7 379
1da177e4
LT		 380 return res;
381}
382
383/**
384 * nand_default_block_markbad - [DEFAULT] mark a block bad
8b6e50c9
BN		 385 * @mtd: MTD device structure
386 * @ofs: offset from device start
1da177e4 387 *
8b6e50c9 388 * This is the default implementation, which can be overridden by a hardware
e2414f4c
BN		 389 * specific driver. We try operations in the following order, according to our
390 * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
391 * (1) erase the affected block, to allow OOB marker to be written cleanly
392 * (2) update in-memory BBT
393 * (3) write bad block marker to OOB area of affected block
394 * (4) update flash-based BBT
395 * Note that we retain the first error encountered in (3) or (4), finish the
396 * procedures, and dump the error in the end.
1da177e4
LT		 397*/
398static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
399{
ace4dfee 400 struct nand_chip *chip = mtd->priv;
58dd8f2b 401 uint8_t buf[2] = { 0, 0 };
e2414f4c
BN		 402 int block, res, ret = 0, i = 0;
403 int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
61b03bd7 404
e2414f4c 405 if (write_oob) {
00918429
BN		 406 struct erase_info einfo;
407
408 /* Attempt erase before marking OOB */
409 memset(&einfo, 0, sizeof(einfo));
410 einfo.mtd = mtd;
411 einfo.addr = ofs;
412 einfo.len = 1 << chip->phys_erase_shift;
413 nand_erase_nand(mtd, &einfo, 0);
414 }
415
1da177e4 416 /* Get block number */
4226b510 417 block = (int)(ofs >> chip->bbt_erase_shift);
e2414f4c 418 /* Mark block bad in memory-based BBT */
ace4dfee
TG		 419 if (chip->bbt)
420 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1da177e4 421
e2414f4c
BN		 422 /* Write bad block marker to OOB */
423 if (write_oob) {
4a89ff88 424 struct mtd_oob_ops ops;
df698621 425 loff_t wr_ofs = ofs;
4a89ff88 426
c0b8ba7b 427 nand_get_device(chip, mtd, FL_WRITING);
f1a28c02 428
4a89ff88
BN		 429 ops.datbuf = NULL;
430 ops.oobbuf = buf;
85443319
BN		 431 ops.ooboffs = chip->badblockpos;
432 if (chip->options & NAND_BUSWIDTH_16) {
433 ops.ooboffs &= ~0x01;
434 ops.len = ops.ooblen = 2;
435 } else {
436 ops.len = ops.ooblen = 1;
437 }
23b1a99b 438 ops.mode = MTD_OPS_PLACE_OOB;
df698621 439
e2414f4c 440 /* Write to first/last page(s) if necessary */
df698621
BN		 441 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
442 wr_ofs += mtd->erasesize - mtd->writesize;
02ed70bb 443 do {
e2414f4c
BN		 444 res = nand_do_write_oob(mtd, wr_ofs, &ops);
445 if (!ret)
446 ret = res;
02ed70bb 447
02ed70bb 448 i++;
df698621 449 wr_ofs += mtd->writesize;
e2414f4c 450 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
02ed70bb 451
c0b8ba7b 452 nand_release_device(mtd);
f1a28c02 453 }
e2414f4c
BN		 454
455 /* Update flash-based bad block table */
456 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
457 res = nand_update_bbt(mtd, ofs);
458 if (!ret)
459 ret = res;
460 }
461
f1a28c02
TG		 462 if (!ret)
463 mtd->ecc_stats.badblocks++;
c0b8ba7b 464
f1a28c02 465 return ret;
1da177e4
LT		 466}
467
61b03bd7 468/**
1da177e4 469 * nand_check_wp - [GENERIC] check if the chip is write protected
8b6e50c9 470 * @mtd: MTD device structure
1da177e4 471 *
8b6e50c9
BN		 472 * Check, if the device is write protected. The function expects, that the
473 * device is already selected.
1da177e4 474 */
e0c7d767 475static int nand_check_wp(struct mtd_info *mtd)
1da177e4 476{
ace4dfee 477 struct nand_chip *chip = mtd->priv;
93edbad6 478
8b6e50c9 479 /* Broken xD cards report WP despite being writable */
93edbad6
ML		 480 if (chip->options & NAND_BROKEN_XD)
481 return 0;
482
1da177e4 483 /* Check the WP bit */
ace4dfee
TG		 484 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
485 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 486}
487
488/**
489 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
8b6e50c9
BN		 490 * @mtd: MTD device structure
491 * @ofs: offset from device start
492 * @getchip: 0, if the chip is already selected
493 * @allowbbt: 1, if its allowed to access the bbt area
1da177e4
LT		 494 *
495 * Check, if the block is bad. Either by reading the bad block table or
496 * calling of the scan function.
497 */
2c0a2bed
TG		 498static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
499 int allowbbt)
1da177e4 500{
ace4dfee 501 struct nand_chip *chip = mtd->priv;
61b03bd7 502
ace4dfee
TG		 503 if (!chip->bbt)
504 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 505
1da177e4 506 /* Return info from the table */
e0c7d767 507 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 508}
509
2af7c653
SK		 510/**
511 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
8b6e50c9
BN		 512 * @mtd: MTD device structure
513 * @timeo: Timeout
2af7c653
SK		 514 *
515 * Helper function for nand_wait_ready used when needing to wait in interrupt
516 * context.
517 */
518static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
519{
520 struct nand_chip *chip = mtd->priv;
521 int i;
522
523 /* Wait for the device to get ready */
524 for (i = 0; i < timeo; i++) {
525 if (chip->dev_ready(mtd))
526 break;
527 touch_softlockup_watchdog();
528 mdelay(1);
529 }
530}
531
7854d3f7 532/* Wait for the ready pin, after a command. The timeout is caught later. */
4b648b02 533void nand_wait_ready(struct mtd_info *mtd)
3b88775c 534{
ace4dfee 535 struct nand_chip *chip = mtd->priv;
e0c7d767 536 unsigned long timeo = jiffies + 2;
3b88775c 537
2af7c653
SK		 538 /* 400ms timeout */
539 if (in_interrupt() || oops_in_progress)
540 return panic_nand_wait_ready(mtd, 400);
541
8fe833c1 542 led_trigger_event(nand_led_trigger, LED_FULL);
7854d3f7 543 /* Wait until command is processed or timeout occurs */
3b88775c 544 do {
ace4dfee 545 if (chip->dev_ready(mtd))
8fe833c1 546 break;
8446f1d3 547 touch_softlockup_watchdog();
61b03bd7 548 } while (time_before(jiffies, timeo));
8fe833c1 549 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 550}
4b648b02 551EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 552
1da177e4
LT		 553/**
554 * nand_command - [DEFAULT] Send command to NAND device
8b6e50c9
BN		 555 * @mtd: MTD device structure
556 * @command: the command to be sent
557 * @column: the column address for this command, -1 if none
558 * @page_addr: the page address for this command, -1 if none
1da177e4 559 *
8b6e50c9
BN		 560 * Send command to NAND device. This function is used for small page devices
561 * (256/512 Bytes per page).
1da177e4 562 */
7abd3ef9
TG		 563static void nand_command(struct mtd_info *mtd, unsigned int command,
564 int column, int page_addr)
1da177e4 565{
ace4dfee 566 register struct nand_chip *chip = mtd->priv;
7abd3ef9 567 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 568
8b6e50c9 569 /* Write out the command to the device */
1da177e4
LT		 570 if (command == NAND_CMD_SEQIN) {
571 int readcmd;
572
28318776 573 if (column >= mtd->writesize) {
1da177e4 574 /* OOB area */
28318776 575 column -= mtd->writesize;
1da177e4
LT		 576 readcmd = NAND_CMD_READOOB;
577 } else if (column < 256) {
578 /* First 256 bytes --> READ0 */
579 readcmd = NAND_CMD_READ0;
580 } else {
581 column -= 256;
582 readcmd = NAND_CMD_READ1;
583 }
ace4dfee 584 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 585 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 586 }
ace4dfee 587 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 588
8b6e50c9 589 /* Address cycle, when necessary */
7abd3ef9
TG		 590 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
591 /* Serially input address */
592 if (column != -1) {
593 /* Adjust columns for 16 bit buswidth */
ace4dfee 594 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 595 column >>= 1;
ace4dfee 596 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 597 ctrl &= ~NAND_CTRL_CHANGE;
598 }
599 if (page_addr != -1) {
ace4dfee 600 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 601 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 602 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 603 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 604 if (chip->chipsize > (32 << 20))
605 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 606 }
ace4dfee 607 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 608
609 /*
8b6e50c9
BN		 610 * Program and erase have their own busy handlers status and sequential
611 * in needs no delay
e0c7d767 612 */
1da177e4 613 switch (command) {
61b03bd7 614
1da177e4
LT		 615 case NAND_CMD_PAGEPROG:
616 case NAND_CMD_ERASE1:
617 case NAND_CMD_ERASE2:
618 case NAND_CMD_SEQIN:
619 case NAND_CMD_STATUS:
620 return;
621
622 case NAND_CMD_RESET:
ace4dfee 623 if (chip->dev_ready)
1da177e4 624 break;
ace4dfee
TG		 625 udelay(chip->chip_delay);
626 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 627 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 628 chip->cmd_ctrl(mtd,
629 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 630 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
631 ;
1da177e4
LT		 632 return;
633
e0c7d767 634 /* This applies to read commands */
1da177e4 635 default:
61b03bd7 636 /*
1da177e4
LT		 637 * If we don't have access to the busy pin, we apply the given
638 * command delay
e0c7d767 639 */
ace4dfee
TG		 640 if (!chip->dev_ready) {
641 udelay(chip->chip_delay);
1da177e4 642 return;
61b03bd7 643 }
1da177e4 644 }
8b6e50c9
BN		 645 /*
646 * Apply this short delay always to ensure that we do wait tWB in
647 * any case on any machine.
648 */
e0c7d767 649 ndelay(100);
3b88775c
TG		 650
651 nand_wait_ready(mtd);
1da177e4
LT		 652}
653
654/**
655 * nand_command_lp - [DEFAULT] Send command to NAND large page device
8b6e50c9
BN		 656 * @mtd: MTD device structure
657 * @command: the command to be sent
658 * @column: the column address for this command, -1 if none
659 * @page_addr: the page address for this command, -1 if none
1da177e4 660 *
7abd3ef9 661 * Send command to NAND device. This is the version for the new large page
7854d3f7
BN		 662 * devices. We don't have the separate regions as we have in the small page
663 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 664 */
7abd3ef9
TG		 665static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
666 int column, int page_addr)
1da177e4 667{
ace4dfee 668 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 669
670 /* Emulate NAND_CMD_READOOB */
671 if (command == NAND_CMD_READOOB) {
28318776 672 column += mtd->writesize;
1da177e4
LT		 673 command = NAND_CMD_READ0;
674 }
61b03bd7 675
7abd3ef9 676 /* Command latch cycle */
ace4dfee 677 chip->cmd_ctrl(mtd, command & 0xff,
7abd3ef9 678 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 679
680 if (column != -1 || page_addr != -1) {
7abd3ef9 681 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 682
683 /* Serially input address */
684 if (column != -1) {
685 /* Adjust columns for 16 bit buswidth */
ace4dfee 686 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 687 column >>= 1;
ace4dfee 688 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 689 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 690 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 691 }
1da177e4 692 if (page_addr != -1) {
ace4dfee
TG		 693 chip->cmd_ctrl(mtd, page_addr, ctrl);
694 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 695 NAND_NCE | NAND_ALE);
1da177e4 696 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 697 if (chip->chipsize > (128 << 20))
698 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 699 NAND_NCE | NAND_ALE);
1da177e4 700 }
1da177e4 701 }
ace4dfee 702 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 703
704 /*
8b6e50c9
BN		 705 * Program and erase have their own busy handlers status, sequential
706 * in, and deplete1 need no delay.
30f464b7 707 */
1da177e4 708 switch (command) {
61b03bd7 709
1da177e4
LT		 710 case NAND_CMD_CACHEDPROG:
711 case NAND_CMD_PAGEPROG:
712 case NAND_CMD_ERASE1:
713 case NAND_CMD_ERASE2:
714 case NAND_CMD_SEQIN:
7bc3312b 715 case NAND_CMD_RNDIN:
1da177e4 716 case NAND_CMD_STATUS:
30f464b7 717 case NAND_CMD_DEPLETE1:
1da177e4
LT		 718 return;
719
30f464b7
DM		 720 case NAND_CMD_STATUS_ERROR:
721 case NAND_CMD_STATUS_ERROR0:
722 case NAND_CMD_STATUS_ERROR1:
723 case NAND_CMD_STATUS_ERROR2:
724 case NAND_CMD_STATUS_ERROR3:
8b6e50c9 725 /* Read error status commands require only a short delay */
ace4dfee 726 udelay(chip->chip_delay);
30f464b7 727 return;
1da177e4
LT		 728
729 case NAND_CMD_RESET:
ace4dfee 730 if (chip->dev_ready)
1da177e4 731 break;
ace4dfee 732 udelay(chip->chip_delay);
12efdde3
TG		 733 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
734 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
735 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
736 NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 737 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
738 ;
1da177e4
LT		 739 return;
740
7bc3312b
TG		 741 case NAND_CMD_RNDOUT:
742 /* No ready / busy check necessary */
743 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
744 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
745 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
746 NAND_NCE | NAND_CTRL_CHANGE);
747 return;
748
1da177e4 749 case NAND_CMD_READ0:
12efdde3
TG		 750 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
751 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
752 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
753 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 754
e0c7d767 755 /* This applies to read commands */
1da177e4 756 default:
61b03bd7 757 /*
1da177e4 758 * If we don't have access to the busy pin, we apply the given
8b6e50c9 759 * command delay.
e0c7d767 760 */
ace4dfee
TG		 761 if (!chip->dev_ready) {
762 udelay(chip->chip_delay);
1da177e4 763 return;
61b03bd7 764 }
1da177e4 765 }
3b88775c 766
8b6e50c9
BN		 767 /*
768 * Apply this short delay always to ensure that we do wait tWB in
769 * any case on any machine.
770 */
e0c7d767 771 ndelay(100);
3b88775c
TG		 772
773 nand_wait_ready(mtd);
1da177e4
LT		 774}
775
2af7c653
SK		 776/**
777 * panic_nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 778 * @chip: the nand chip descriptor
779 * @mtd: MTD device structure
780 * @new_state: the state which is requested
2af7c653
SK		 781 *
782 * Used when in panic, no locks are taken.
783 */
784static void panic_nand_get_device(struct nand_chip *chip,
785 struct mtd_info *mtd, int new_state)
786{
7854d3f7 787 /* Hardware controller shared among independent devices */
2af7c653
SK		 788 chip->controller->active = chip;
789 chip->state = new_state;
790}
791
1da177e4
LT		 792/**
793 * nand_get_device - [GENERIC] Get chip for selected access
8b6e50c9
BN		 794 * @chip: the nand chip descriptor
795 * @mtd: MTD device structure
796 * @new_state: the state which is requested
1da177e4
LT		 797 *
798 * Get the device and lock it for exclusive access
799 */
2c0a2bed 800static int
ace4dfee 801nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
1da177e4 802{
ace4dfee
TG		 803 spinlock_t *lock = &chip->controller->lock;
804 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 805 DECLARE_WAITQUEUE(wait, current);
7351d3a5 806retry:
0dfc6246
TG		 807 spin_lock(lock);
808
b8b3ee9a 809 /* Hardware controller shared among independent devices */
ace4dfee
TG		 810 if (!chip->controller->active)
811 chip->controller->active = chip;
a36ed299 812
ace4dfee
TG		 813 if (chip->controller->active == chip && chip->state == FL_READY) {
814 chip->state = new_state;
0dfc6246 815 spin_unlock(lock);
962034f4
VW		 816 return 0;
817 }
818 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 819 if (chip->controller->active->state == FL_PM_SUSPENDED) {
820 chip->state = FL_PM_SUSPENDED;
821 spin_unlock(lock);
822 return 0;
6b0d9a84 823 }
0dfc6246
TG		 824 }
825 set_current_state(TASK_UNINTERRUPTIBLE);
826 add_wait_queue(wq, &wait);
827 spin_unlock(lock);
828 schedule();
829 remove_wait_queue(wq, &wait);
1da177e4
LT		 830 goto retry;
831}
832
2af7c653 833/**
8b6e50c9
BN		 834 * panic_nand_wait - [GENERIC] wait until the command is done
835 * @mtd: MTD device structure
836 * @chip: NAND chip structure
837 * @timeo: timeout
2af7c653
SK		 838 *
839 * Wait for command done. This is a helper function for nand_wait used when
840 * we are in interrupt context. May happen when in panic and trying to write
b595076a 841 * an oops through mtdoops.
2af7c653
SK		 842 */
843static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
844 unsigned long timeo)
845{
846 int i;
847 for (i = 0; i < timeo; i++) {
848 if (chip->dev_ready) {
849 if (chip->dev_ready(mtd))
850 break;
851 } else {
852 if (chip->read_byte(mtd) & NAND_STATUS_READY)
853 break;
854 }
855 mdelay(1);
f8ac0414 856 }
2af7c653
SK		 857}
858
1da177e4 859/**
8b6e50c9
BN		 860 * nand_wait - [DEFAULT] wait until the command is done
861 * @mtd: MTD device structure
862 * @chip: NAND chip structure
1da177e4 863 *
8b6e50c9
BN		 864 * Wait for command done. This applies to erase and program only. Erase can
865 * take up to 400ms and program up to 20ms according to general NAND and
866 * SmartMedia specs.
844d3b42 867 */
7bc3312b 868static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 869{
870
e0c7d767 871 unsigned long timeo = jiffies;
7bc3312b 872 int status, state = chip->state;
61b03bd7 873
1da177e4 874 if (state == FL_ERASING)
e0c7d767 875 timeo += (HZ * 400) / 1000;
1da177e4 876 else
e0c7d767 877 timeo += (HZ * 20) / 1000;
1da177e4 878
8fe833c1
RP		 879 led_trigger_event(nand_led_trigger, LED_FULL);
880
8b6e50c9
BN		 881 /*
882 * Apply this short delay always to ensure that we do wait tWB in any
883 * case on any machine.
884 */
e0c7d767 885 ndelay(100);
1da177e4 886
ace4dfee
TG		 887 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
888 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
61b03bd7 889 else
ace4dfee 890 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 891
2af7c653
SK		 892 if (in_interrupt() || oops_in_progress)
893 panic_nand_wait(mtd, chip, timeo);
894 else {
895 while (time_before(jiffies, timeo)) {
896 if (chip->dev_ready) {
897 if (chip->dev_ready(mtd))
898 break;
899 } else {
900 if (chip->read_byte(mtd) & NAND_STATUS_READY)
901 break;
902 }
903 cond_resched();
1da177e4 904 }
1da177e4 905 }
8fe833c1
RP		 906 led_trigger_event(nand_led_trigger, LED_OFF);
907
ace4dfee 908 status = (int)chip->read_byte(mtd);
1da177e4
LT		 909 return status;
910}
911
7d70f334 912/**
b6d676db 913 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 914 * @mtd: mtd info
915 * @ofs: offset to start unlock from
916 * @len: length to unlock
8b6e50c9
BN		 917 * @invert: when = 0, unlock the range of blocks within the lower and
918 * upper boundary address
919 * when = 1, unlock the range of blocks outside the boundaries
920 * of the lower and upper boundary address
7d70f334 921 *
8b6e50c9 922 * Returs unlock status.
7d70f334
VS		 923 */
924static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
925 uint64_t len, int invert)
926{
927 int ret = 0;
928 int status, page;
929 struct nand_chip *chip = mtd->priv;
930
931 /* Submit address of first page to unlock */
932 page = ofs >> chip->page_shift;
933 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
934
935 /* Submit address of last page to unlock */
936 page = (ofs + len) >> chip->page_shift;
937 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
938 (page | invert) & chip->pagemask);
939
940 /* Call wait ready function */
941 status = chip->waitfunc(mtd, chip);
7d70f334
VS		 942 /* See if device thinks it succeeded */
943 if (status & 0x01) {
289c0522 944 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 945 __func__, status);
946 ret = -EIO;
947 }
948
949 return ret;
950}
951
952/**
b6d676db 953 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
b6d676db
RD		 954 * @mtd: mtd info
955 * @ofs: offset to start unlock from
956 * @len: length to unlock
7d70f334 957 *
8b6e50c9 958 * Returns unlock status.
7d70f334
VS		 959 */
960int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
961{
962 int ret = 0;
963 int chipnr;
964 struct nand_chip *chip = mtd->priv;
965
289c0522 966 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 967 __func__, (unsigned long long)ofs, len);
968
969 if (check_offs_len(mtd, ofs, len))
970 ret = -EINVAL;
971
972 /* Align to last block address if size addresses end of the device */
973 if (ofs + len == mtd->size)
974 len -= mtd->erasesize;
975
976 nand_get_device(chip, mtd, FL_UNLOCKING);
977
978 /* Shift to get chip number */
979 chipnr = ofs >> chip->chip_shift;
980
981 chip->select_chip(mtd, chipnr);
982
983 /* Check, if it is write protected */
984 if (nand_check_wp(mtd)) {
289c0522 985 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 986 __func__);
987 ret = -EIO;
988 goto out;
989 }
990
991 ret = __nand_unlock(mtd, ofs, len, 0);
992
993out:
7d70f334
VS		 994 nand_release_device(mtd);
995
996 return ret;
997}
7351d3a5 998EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 999
1000/**
b6d676db 1001 * nand_lock - [REPLACEABLE] locks all blocks present in the device
b6d676db
RD		 1002 * @mtd: mtd info
1003 * @ofs: offset to start unlock from
1004 * @len: length to unlock
7d70f334 1005 *
8b6e50c9
BN		 1006 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1007 * have this feature, but it allows only to lock all blocks, not for specified
1008 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1009 * now.
7d70f334 1010 *
8b6e50c9 1011 * Returns lock status.
7d70f334
VS		 1012 */
1013int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1014{
1015 int ret = 0;
1016 int chipnr, status, page;
1017 struct nand_chip *chip = mtd->priv;
1018
289c0522 1019 pr_debug("%s: start = 0x%012llx, len = %llu\n",
7d70f334
VS		 1020 __func__, (unsigned long long)ofs, len);
1021
1022 if (check_offs_len(mtd, ofs, len))
1023 ret = -EINVAL;
1024
1025 nand_get_device(chip, mtd, FL_LOCKING);
1026
1027 /* Shift to get chip number */
1028 chipnr = ofs >> chip->chip_shift;
1029
1030 chip->select_chip(mtd, chipnr);
1031
1032 /* Check, if it is write protected */
1033 if (nand_check_wp(mtd)) {
289c0522 1034 pr_debug("%s: device is write protected!\n",
7d70f334
VS		 1035 __func__);
1036 status = MTD_ERASE_FAILED;
1037 ret = -EIO;
1038 goto out;
1039 }
1040
1041 /* Submit address of first page to lock */
1042 page = ofs >> chip->page_shift;
1043 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1044
1045 /* Call wait ready function */
1046 status = chip->waitfunc(mtd, chip);
7d70f334
VS		 1047 /* See if device thinks it succeeded */
1048 if (status & 0x01) {
289c0522 1049 pr_debug("%s: error status = 0x%08x\n",
7d70f334
VS		 1050 __func__, status);
1051 ret = -EIO;
1052 goto out;
1053 }
1054
1055 ret = __nand_unlock(mtd, ofs, len, 0x1);
1056
1057out:
7d70f334
VS		 1058 nand_release_device(mtd);
1059
1060 return ret;
1061}
7351d3a5 1062EXPORT_SYMBOL(nand_lock);
7d70f334 1063
8593fbc6 1064/**
7854d3f7 1065 * nand_read_page_raw - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1066 * @mtd: mtd info structure
1067 * @chip: nand chip info structure
1068 * @buf: buffer to store read data
1fbb938d 1069 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1070 * @page: page number to read
52ff49df 1071 *
7854d3f7 1072 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6
TG		 1073 */
1074static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1075 uint8_t *buf, int oob_required, int page)
8593fbc6
TG		 1076{
1077 chip->read_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1078 if (oob_required)
1079 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
8593fbc6
TG		 1080 return 0;
1081}
1082
52ff49df 1083/**
7854d3f7 1084 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
8b6e50c9
BN		 1085 * @mtd: mtd info structure
1086 * @chip: nand chip info structure
1087 * @buf: buffer to store read data
1fbb938d 1088 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1089 * @page: page number to read
52ff49df
DB		 1090 *
1091 * We need a special oob layout and handling even when OOB isn't used.
1092 */
7351d3a5 1093static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 1094 struct nand_chip *chip, uint8_t *buf,
1095 int oob_required, int page)
52ff49df
DB		 1096{
1097 int eccsize = chip->ecc.size;
1098 int eccbytes = chip->ecc.bytes;
1099 uint8_t *oob = chip->oob_poi;
1100 int steps, size;
1101
1102 for (steps = chip->ecc.steps; steps > 0; steps--) {
1103 chip->read_buf(mtd, buf, eccsize);
1104 buf += eccsize;
1105
1106 if (chip->ecc.prepad) {
1107 chip->read_buf(mtd, oob, chip->ecc.prepad);
1108 oob += chip->ecc.prepad;
1109 }
1110
1111 chip->read_buf(mtd, oob, eccbytes);
1112 oob += eccbytes;
1113
1114 if (chip->ecc.postpad) {
1115 chip->read_buf(mtd, oob, chip->ecc.postpad);
1116 oob += chip->ecc.postpad;
1117 }
1118 }
1119
1120 size = mtd->oobsize - (oob - chip->oob_poi);
1121 if (size)
1122 chip->read_buf(mtd, oob, size);
1123
1124 return 0;
1125}
1126
1da177e4 1127/**
7854d3f7 1128 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
8b6e50c9
BN		 1129 * @mtd: mtd info structure
1130 * @chip: nand chip info structure
1131 * @buf: buffer to store read data
1fbb938d 1132 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1133 * @page: page number to read
068e3c0a 1134 */
f5bbdacc 1135static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1136 uint8_t *buf, int oob_required, int page)
1da177e4 1137{
f5bbdacc
TG		 1138 int i, eccsize = chip->ecc.size;
1139 int eccbytes = chip->ecc.bytes;
1140 int eccsteps = chip->ecc.steps;
1141 uint8_t *p = buf;
4bf63fcb
DW		 1142 uint8_t *ecc_calc = chip->buffers->ecccalc;
1143 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1144 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1145 unsigned int max_bitflips = 0;
f5bbdacc 1146
1fbb938d 1147 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
f5bbdacc
TG		 1148
1149 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1150 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1151
1152 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1153 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1154
1155 eccsteps = chip->ecc.steps;
1156 p = buf;
1157
1158 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1159 int stat;
1160
1161 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1162 if (stat < 0) {
f5bbdacc 1163 mtd->ecc_stats.failed++;
3f91e94f 1164 } else {
f5bbdacc 1165 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1166 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1167 }
f5bbdacc 1168 }
3f91e94f 1169 return max_bitflips;
22c60f5f 1170}
1da177e4 1171
3d459559 1172/**
7854d3f7 1173 * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
8b6e50c9
BN		 1174 * @mtd: mtd info structure
1175 * @chip: nand chip info structure
1176 * @data_offs: offset of requested data within the page
1177 * @readlen: data length
1178 * @bufpoi: buffer to store read data
3d459559 1179 */
7351d3a5
FF		 1180static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1181 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
3d459559
AK		 1182{
1183 int start_step, end_step, num_steps;
1184 uint32_t *eccpos = chip->ecc.layout->eccpos;
1185 uint8_t *p;
1186 int data_col_addr, i, gaps = 0;
1187 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1188 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
7351d3a5 1189 int index = 0;
3f91e94f 1190 unsigned int max_bitflips = 0;
3d459559 1191
7854d3f7 1192 /* Column address within the page aligned to ECC size (256bytes) */
3d459559
AK		 1193 start_step = data_offs / chip->ecc.size;
1194 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1195 num_steps = end_step - start_step + 1;
1196
8b6e50c9 1197 /* Data size aligned to ECC ecc.size */
3d459559
AK		 1198 datafrag_len = num_steps * chip->ecc.size;
1199 eccfrag_len = num_steps * chip->ecc.bytes;
1200
1201 data_col_addr = start_step * chip->ecc.size;
1202 /* If we read not a page aligned data */
1203 if (data_col_addr != 0)
1204 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1205
1206 p = bufpoi + data_col_addr;
1207 chip->read_buf(mtd, p, datafrag_len);
1208
8b6e50c9 1209 /* Calculate ECC */
3d459559
AK		 1210 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1211 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1212
8b6e50c9
BN		 1213 /*
1214 * The performance is faster if we position offsets according to
7854d3f7 1215 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
8b6e50c9 1216 */
3d459559
AK		 1217 for (i = 0; i < eccfrag_len - 1; i++) {
1218 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1219 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1220 gaps = 1;
1221 break;
1222 }
1223 }
1224 if (gaps) {
1225 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1226 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1227 } else {
8b6e50c9 1228 /*
7854d3f7 1229 * Send the command to read the particular ECC bytes take care
8b6e50c9
BN		 1230 * about buswidth alignment in read_buf.
1231 */
7351d3a5
FF		 1232 index = start_step * chip->ecc.bytes;
1233
1234 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1235 aligned_len = eccfrag_len;
7351d3a5 1236 if (eccpos[index] & (busw - 1))
3d459559 1237 aligned_len++;
7351d3a5 1238 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1239 aligned_len++;
1240
7351d3a5
FF		 1241 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1242 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1243 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1244 }
1245
1246 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1247 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1248
1249 p = bufpoi + data_col_addr;
1250 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1251 int stat;
1252
7351d3a5
FF		 1253 stat = chip->ecc.correct(mtd, p,
1254 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
3f91e94f 1255 if (stat < 0) {
3d459559 1256 mtd->ecc_stats.failed++;
3f91e94f 1257 } else {
3d459559 1258 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1259 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1260 }
3d459559 1261 }
3f91e94f 1262 return max_bitflips;
3d459559
AK		 1263}
1264
068e3c0a 1265/**
7854d3f7 1266 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
8b6e50c9
BN		 1267 * @mtd: mtd info structure
1268 * @chip: nand chip info structure
1269 * @buf: buffer to store read data
1fbb938d 1270 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1271 * @page: page number to read
068e3c0a 1272 *
7854d3f7 1273 * Not for syndrome calculating ECC controllers which need a special oob layout.
068e3c0a 1274 */
f5bbdacc 1275static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1276 uint8_t *buf, int oob_required, int page)
1da177e4 1277{
f5bbdacc
TG		 1278 int i, eccsize = chip->ecc.size;
1279 int eccbytes = chip->ecc.bytes;
1280 int eccsteps = chip->ecc.steps;
1281 uint8_t *p = buf;
4bf63fcb
DW		 1282 uint8_t *ecc_calc = chip->buffers->ecccalc;
1283 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1284 uint32_t *eccpos = chip->ecc.layout->eccpos;
3f91e94f 1285 unsigned int max_bitflips = 0;
f5bbdacc
TG		 1286
1287 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1288 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1289 chip->read_buf(mtd, p, eccsize);
1290 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1291 }
f75e5097 1292 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1293
f5bbdacc 1294 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1295 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1296
f5bbdacc
TG		 1297 eccsteps = chip->ecc.steps;
1298 p = buf;
61b03bd7 1299
f5bbdacc
TG		 1300 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1301 int stat;
1da177e4 1302
f5bbdacc 1303 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
3f91e94f 1304 if (stat < 0) {
f5bbdacc 1305 mtd->ecc_stats.failed++;
3f91e94f 1306 } else {
f5bbdacc 1307 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1308 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1309 }
f5bbdacc 1310 }
3f91e94f 1311 return max_bitflips;
f5bbdacc 1312}
1da177e4 1313
6e0cb135 1314/**
7854d3f7 1315 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
8b6e50c9
BN		 1316 * @mtd: mtd info structure
1317 * @chip: nand chip info structure
1318 * @buf: buffer to store read data
1fbb938d 1319 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1320 * @page: page number to read
6e0cb135 1321 *
8b6e50c9
BN		 1322 * Hardware ECC for large page chips, require OOB to be read first. For this
1323 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1324 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1325 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1326 * the data area, by overwriting the NAND manufacturer bad block markings.
6e0cb135
SN		 1327 */
1328static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1fbb938d 1329 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
6e0cb135
SN		 1330{
1331 int i, eccsize = chip->ecc.size;
1332 int eccbytes = chip->ecc.bytes;
1333 int eccsteps = chip->ecc.steps;
1334 uint8_t *p = buf;
1335 uint8_t *ecc_code = chip->buffers->ecccode;
1336 uint32_t *eccpos = chip->ecc.layout->eccpos;
1337 uint8_t *ecc_calc = chip->buffers->ecccalc;
3f91e94f 1338 unsigned int max_bitflips = 0;
6e0cb135
SN		 1339
1340 /* Read the OOB area first */
1341 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1342 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1343 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1344
1345 for (i = 0; i < chip->ecc.total; i++)
1346 ecc_code[i] = chip->oob_poi[eccpos[i]];
1347
1348 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1349 int stat;
1350
1351 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1352 chip->read_buf(mtd, p, eccsize);
1353 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1354
1355 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
3f91e94f 1356 if (stat < 0) {
6e0cb135 1357 mtd->ecc_stats.failed++;
3f91e94f 1358 } else {
6e0cb135 1359 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1360 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1361 }
6e0cb135 1362 }
3f91e94f 1363 return max_bitflips;
6e0cb135
SN		 1364}
1365
f5bbdacc 1366/**
7854d3f7 1367 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
8b6e50c9
BN		 1368 * @mtd: mtd info structure
1369 * @chip: nand chip info structure
1370 * @buf: buffer to store read data
1fbb938d 1371 * @oob_required: caller requires OOB data read to chip->oob_poi
8b6e50c9 1372 * @page: page number to read
f5bbdacc 1373 *
8b6e50c9
BN		 1374 * The hw generator calculates the error syndrome automatically. Therefore we
1375 * need a special oob layout and handling.
f5bbdacc
TG		 1376 */
1377static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1378 uint8_t *buf, int oob_required, int page)
f5bbdacc
TG		 1379{
1380 int i, eccsize = chip->ecc.size;
1381 int eccbytes = chip->ecc.bytes;
1382 int eccsteps = chip->ecc.steps;
1383 uint8_t *p = buf;
f75e5097 1384 uint8_t *oob = chip->oob_poi;
3f91e94f 1385 unsigned int max_bitflips = 0;
1da177e4 1386
f5bbdacc
TG		 1387 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1388 int stat;
61b03bd7 1389
f5bbdacc
TG		 1390 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1391 chip->read_buf(mtd, p, eccsize);
1da177e4 1392
f5bbdacc
TG		 1393 if (chip->ecc.prepad) {
1394 chip->read_buf(mtd, oob, chip->ecc.prepad);
1395 oob += chip->ecc.prepad;
1396 }
1da177e4 1397
f5bbdacc
TG		 1398 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1399 chip->read_buf(mtd, oob, eccbytes);
1400 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1401
3f91e94f 1402 if (stat < 0) {
f5bbdacc 1403 mtd->ecc_stats.failed++;
3f91e94f 1404 } else {
f5bbdacc 1405 mtd->ecc_stats.corrected += stat;
3f91e94f
MD		 1406 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1407 }
61b03bd7 1408
f5bbdacc 1409 oob += eccbytes;
1da177e4 1410
f5bbdacc
TG		 1411 if (chip->ecc.postpad) {
1412 chip->read_buf(mtd, oob, chip->ecc.postpad);
1413 oob += chip->ecc.postpad;
61b03bd7 1414 }
f5bbdacc 1415 }
1da177e4 1416
f5bbdacc 1417 /* Calculate remaining oob bytes */
7e4178f9 1418 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1419 if (i)
1420 chip->read_buf(mtd, oob, i);
61b03bd7 1421
3f91e94f 1422 return max_bitflips;
f5bbdacc 1423}
1da177e4 1424
f5bbdacc 1425/**
7854d3f7 1426 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
8b6e50c9
BN		 1427 * @chip: nand chip structure
1428 * @oob: oob destination address
1429 * @ops: oob ops structure
1430 * @len: size of oob to transfer
8593fbc6
TG		 1431 */
1432static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1433 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1434{
f8ac0414 1435 switch (ops->mode) {
8593fbc6 1436
0612b9dd
BN		 1437 case MTD_OPS_PLACE_OOB:
1438 case MTD_OPS_RAW:
8593fbc6
TG		 1439 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1440 return oob + len;
1441
0612b9dd 1442 case MTD_OPS_AUTO_OOB: {
8593fbc6 1443 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1444 uint32_t boffs = 0, roffs = ops->ooboffs;
1445 size_t bytes = 0;
8593fbc6 1446
f8ac0414 1447 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 1448 /* Read request not from offset 0? */
7bc3312b
TG		 1449 if (unlikely(roffs)) {
1450 if (roffs >= free->length) {
1451 roffs -= free->length;
1452 continue;
1453 }
1454 boffs = free->offset + roffs;
1455 bytes = min_t(size_t, len,
1456 (free->length - roffs));
1457 roffs = 0;
1458 } else {
1459 bytes = min_t(size_t, len, free->length);
1460 boffs = free->offset;
1461 }
1462 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1463 oob += bytes;
1464 }
1465 return oob;
1466 }
1467 default:
1468 BUG();
1469 }
1470 return NULL;
1471}
1472
1473/**
7854d3f7 1474 * nand_do_read_ops - [INTERN] Read data with ECC
8b6e50c9
BN		 1475 * @mtd: MTD device structure
1476 * @from: offset to read from
1477 * @ops: oob ops structure
f5bbdacc
TG		 1478 *
1479 * Internal function. Called with chip held.
1480 */
8593fbc6
TG		 1481static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1482 struct mtd_oob_ops *ops)
f5bbdacc 1483{
e47f3db4 1484 int chipnr, page, realpage, col, bytes, aligned, oob_required;
f5bbdacc
TG		 1485 struct nand_chip *chip = mtd->priv;
1486 struct mtd_ecc_stats stats;
f5bbdacc 1487 int ret = 0;
8593fbc6 1488 uint32_t readlen = ops->len;
7014568b 1489 uint32_t oobreadlen = ops->ooblen;
0612b9dd 1490 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
9aca334e
ML		 1491 mtd->oobavail : mtd->oobsize;
1492
8593fbc6 1493 uint8_t *bufpoi, *oob, *buf;
edbc4540 1494 unsigned int max_bitflips = 0;
1da177e4 1495
f5bbdacc 1496 stats = mtd->ecc_stats;
1da177e4 1497
f5bbdacc
TG		 1498 chipnr = (int)(from >> chip->chip_shift);
1499 chip->select_chip(mtd, chipnr);
61b03bd7 1500
f5bbdacc
TG		 1501 realpage = (int)(from >> chip->page_shift);
1502 page = realpage & chip->pagemask;
1da177e4 1503
f5bbdacc 1504 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1505
8593fbc6
TG		 1506 buf = ops->datbuf;
1507 oob = ops->oobbuf;
e47f3db4 1508 oob_required = oob ? 1 : 0;
8593fbc6 1509
f8ac0414 1510 while (1) {
f5bbdacc
TG		 1511 bytes = min(mtd->writesize - col, readlen);
1512 aligned = (bytes == mtd->writesize);
61b03bd7 1513
8b6e50c9 1514 /* Is the current page in the buffer? */
8593fbc6 1515 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1516 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1517
c00a0991 1518 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1da177e4 1519
edbc4540
MD		 1520 /*
1521 * Now read the page into the buffer. Absent an error,
1522 * the read methods return max bitflips per ecc step.
1523 */
0612b9dd 1524 if (unlikely(ops->mode == MTD_OPS_RAW))
1fbb938d 1525 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
e47f3db4
BN		 1526 oob_required,
1527 page);
3d459559 1528 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
7351d3a5
FF		 1529 ret = chip->ecc.read_subpage(mtd, chip,
1530 col, bytes, bufpoi);
956e944c 1531 else
46a8cf2d 1532 ret = chip->ecc.read_page(mtd, chip, bufpoi,
e47f3db4 1533 oob_required, page);
6d77b9d0
BN		 1534 if (ret < 0) {
1535 if (!aligned)
1536 /* Invalidate page cache */
1537 chip->pagebuf = -1;
1da177e4 1538 break;
6d77b9d0 1539 }
f5bbdacc 1540
edbc4540
MD		 1541 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1542
f5bbdacc
TG		 1543 /* Transfer not aligned data */
1544 if (!aligned) {
c1194c79 1545 if (!NAND_SUBPAGE_READ(chip) && !oob &&
6d77b9d0 1546 !(mtd->ecc_stats.failed - stats.failed) &&
edbc4540 1547 (ops->mode != MTD_OPS_RAW)) {
3d459559 1548 chip->pagebuf = realpage;
edbc4540
MD		 1549 chip->pagebuf_bitflips = ret;
1550 } else {
6d77b9d0
BN		 1551 /* Invalidate page cache */
1552 chip->pagebuf = -1;
edbc4540 1553 }
4bf63fcb 1554 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1555 }
1556
8593fbc6
TG		 1557 buf += bytes;
1558
1559 if (unlikely(oob)) {
b64d39d8
ML		 1560 int toread = min(oobreadlen, max_oobsize);
1561
1562 if (toread) {
1563 oob = nand_transfer_oob(chip,
1564 oob, ops, toread);
1565 oobreadlen -= toread;
1566 }
8593fbc6 1567 }
8593fbc6 1568 } else {
4bf63fcb 1569 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6 1570 buf += bytes;
edbc4540
MD		 1571 max_bitflips = max_t(unsigned int, max_bitflips,
1572 chip->pagebuf_bitflips);
8593fbc6 1573 }
1da177e4 1574
f5bbdacc 1575 readlen -= bytes;
61b03bd7 1576
f5bbdacc 1577 if (!readlen)
61b03bd7 1578 break;
1da177e4 1579
8b6e50c9 1580 /* For subsequent reads align to page boundary */
1da177e4
LT		 1581 col = 0;
1582 /* Increment page address */
1583 realpage++;
1584
ace4dfee 1585 page = realpage & chip->pagemask;
1da177e4
LT		 1586 /* Check, if we cross a chip boundary */
1587 if (!page) {
1588 chipnr++;
ace4dfee
TG		 1589 chip->select_chip(mtd, -1);
1590 chip->select_chip(mtd, chipnr);
1da177e4 1591 }
1da177e4
LT		 1592 }
1593
8593fbc6 1594 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1595 if (oob)
1596 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1597
3f91e94f 1598 if (ret < 0)
f5bbdacc
TG		 1599 return ret;
1600
9a1fcdfd
TG		 1601 if (mtd->ecc_stats.failed - stats.failed)
1602 return -EBADMSG;
1603
edbc4540 1604 return max_bitflips;
f5bbdacc
TG		 1605}
1606
1607/**
25985edc 1608 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
8b6e50c9
BN		 1609 * @mtd: MTD device structure
1610 * @from: offset to read from
1611 * @len: number of bytes to read
1612 * @retlen: pointer to variable to store the number of read bytes
1613 * @buf: the databuffer to put data
f5bbdacc 1614 *
8b6e50c9 1615 * Get hold of the chip and call nand_do_read.
f5bbdacc
TG		 1616 */
1617static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1618 size_t *retlen, uint8_t *buf)
1619{
8593fbc6 1620 struct nand_chip *chip = mtd->priv;
4a89ff88 1621 struct mtd_oob_ops ops;
f5bbdacc
TG		 1622 int ret;
1623
8593fbc6 1624 nand_get_device(chip, mtd, FL_READING);
4a89ff88
BN		 1625 ops.len = len;
1626 ops.datbuf = buf;
1627 ops.oobbuf = NULL;
23b1a99b 1628 ops.mode = 0;
4a89ff88 1629 ret = nand_do_read_ops(mtd, from, &ops);
4a89ff88 1630 *retlen = ops.retlen;
f5bbdacc 1631 nand_release_device(mtd);
f5bbdacc 1632 return ret;
1da177e4
LT		 1633}
1634
7bc3312b 1635/**
7854d3f7 1636 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
8b6e50c9
BN		 1637 * @mtd: mtd info structure
1638 * @chip: nand chip info structure
1639 * @page: page number to read
7bc3312b
TG		 1640 */
1641static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1642 int page)
7bc3312b 1643{
5c2ffb11 1644 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
7bc3312b 1645 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
5c2ffb11 1646 return 0;
7bc3312b
TG		 1647}
1648
1649/**
7854d3f7 1650 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
7bc3312b 1651 * with syndromes
8b6e50c9
BN		 1652 * @mtd: mtd info structure
1653 * @chip: nand chip info structure
1654 * @page: page number to read
7bc3312b
TG		 1655 */
1656static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
5c2ffb11 1657 int page)
7bc3312b
TG		 1658{
1659 uint8_t *buf = chip->oob_poi;
1660 int length = mtd->oobsize;
1661 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1662 int eccsize = chip->ecc.size;
1663 uint8_t *bufpoi = buf;
1664 int i, toread, sndrnd = 0, pos;
1665
1666 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1667 for (i = 0; i < chip->ecc.steps; i++) {
1668 if (sndrnd) {
1669 pos = eccsize + i * (eccsize + chunk);
1670 if (mtd->writesize > 512)
1671 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1672 else
1673 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1674 } else
1675 sndrnd = 1;
1676 toread = min_t(int, length, chunk);
1677 chip->read_buf(mtd, bufpoi, toread);
1678 bufpoi += toread;
1679 length -= toread;
1680 }
1681 if (length > 0)
1682 chip->read_buf(mtd, bufpoi, length);
1683
5c2ffb11 1684 return 0;
7bc3312b
TG		 1685}
1686
1687/**
7854d3f7 1688 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
8b6e50c9
BN		 1689 * @mtd: mtd info structure
1690 * @chip: nand chip info structure
1691 * @page: page number to write
7bc3312b
TG		 1692 */
1693static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1694 int page)
1695{
1696 int status = 0;
1697 const uint8_t *buf = chip->oob_poi;
1698 int length = mtd->oobsize;
1699
1700 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1701 chip->write_buf(mtd, buf, length);
1702 /* Send command to program the OOB data */
1703 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1704
1705 status = chip->waitfunc(mtd, chip);
1706
0d420f9d 1707 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1708}
1709
1710/**
7854d3f7 1711 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
8b6e50c9
BN		 1712 * with syndrome - only for large page flash
1713 * @mtd: mtd info structure
1714 * @chip: nand chip info structure
1715 * @page: page number to write
7bc3312b
TG		 1716 */
1717static int nand_write_oob_syndrome(struct mtd_info *mtd,
1718 struct nand_chip *chip, int page)
1719{
1720 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1721 int eccsize = chip->ecc.size, length = mtd->oobsize;
1722 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1723 const uint8_t *bufpoi = chip->oob_poi;
1724
1725 /*
1726 * data-ecc-data-ecc ... ecc-oob
1727 * or
1728 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1729 */
1730 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1731 pos = steps * (eccsize + chunk);
1732 steps = 0;
1733 } else
8b0036ee 1734 pos = eccsize;
7bc3312b
TG		 1735
1736 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1737 for (i = 0; i < steps; i++) {
1738 if (sndcmd) {
1739 if (mtd->writesize <= 512) {
1740 uint32_t fill = 0xFFFFFFFF;
1741
1742 len = eccsize;
1743 while (len > 0) {
1744 int num = min_t(int, len, 4);
1745 chip->write_buf(mtd, (uint8_t *)&fill,
1746 num);
1747 len -= num;
1748 }
1749 } else {
1750 pos = eccsize + i * (eccsize + chunk);
1751 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1752 }
1753 } else
1754 sndcmd = 1;
1755 len = min_t(int, length, chunk);
1756 chip->write_buf(mtd, bufpoi, len);
1757 bufpoi += len;
1758 length -= len;
1759 }
1760 if (length > 0)
1761 chip->write_buf(mtd, bufpoi, length);
1762
1763 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1764 status = chip->waitfunc(mtd, chip);
1765
1766 return status & NAND_STATUS_FAIL ? -EIO : 0;
1767}
1768
1da177e4 1769/**
7854d3f7 1770 * nand_do_read_oob - [INTERN] NAND read out-of-band
8b6e50c9
BN		 1771 * @mtd: MTD device structure
1772 * @from: offset to read from
1773 * @ops: oob operations description structure
1da177e4 1774 *
8b6e50c9 1775 * NAND read out-of-band data from the spare area.
1da177e4 1776 */
8593fbc6
TG		 1777static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1778 struct mtd_oob_ops *ops)
1da177e4 1779{
c00a0991 1780 int page, realpage, chipnr;
ace4dfee 1781 struct nand_chip *chip = mtd->priv;
041e4575 1782 struct mtd_ecc_stats stats;
7014568b
VW		 1783 int readlen = ops->ooblen;
1784 int len;
7bc3312b 1785 uint8_t *buf = ops->oobbuf;
1951f2f7 1786 int ret = 0;
61b03bd7 1787
289c0522 1788 pr_debug("%s: from = 0x%08Lx, len = %i\n",
20d8e248 1789 __func__, (unsigned long long)from, readlen);
1da177e4 1790
041e4575
BN		 1791 stats = mtd->ecc_stats;
1792
0612b9dd 1793 if (ops->mode == MTD_OPS_AUTO_OOB)
7014568b 1794 len = chip->ecc.layout->oobavail;
03736155
AH		 1795 else
1796 len = mtd->oobsize;
1797
1798 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 1799 pr_debug("%s: attempt to start read outside oob\n",
1800 __func__);
03736155
AH		 1801 return -EINVAL;
1802 }
1803
1804 /* Do not allow reads past end of device */
1805 if (unlikely(from >= mtd->size ||
1806 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1807 (from >> chip->page_shift)) * len)) {
289c0522
BN		 1808 pr_debug("%s: attempt to read beyond end of device\n",
1809 __func__);
03736155
AH		 1810 return -EINVAL;
1811 }
7014568b 1812
7314e9e7 1813 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1814 chip->select_chip(mtd, chipnr);
1da177e4 1815
7314e9e7
TG		 1816 /* Shift to get page */
1817 realpage = (int)(from >> chip->page_shift);
1818 page = realpage & chip->pagemask;
1da177e4 1819
f8ac0414 1820 while (1) {
0612b9dd 1821 if (ops->mode == MTD_OPS_RAW)
1951f2f7 1822 ret = chip->ecc.read_oob_raw(mtd, chip, page);
c46f6483 1823 else
1951f2f7
SL		 1824 ret = chip->ecc.read_oob(mtd, chip, page);
1825
1826 if (ret < 0)
1827 break;
7014568b
VW		 1828
1829 len = min(len, readlen);
1830 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1831
7014568b 1832 readlen -= len;
0d420f9d
SZ		 1833 if (!readlen)
1834 break;
1835
7314e9e7
TG		 1836 /* Increment page address */
1837 realpage++;
1838
1839 page = realpage & chip->pagemask;
1840 /* Check, if we cross a chip boundary */
1841 if (!page) {
1842 chipnr++;
1843 chip->select_chip(mtd, -1);
1844 chip->select_chip(mtd, chipnr);
1da177e4
LT		 1845 }
1846 }
1847
1951f2f7
SL		 1848 ops->oobretlen = ops->ooblen - readlen;
1849
1850 if (ret < 0)
1851 return ret;
041e4575
BN		 1852
1853 if (mtd->ecc_stats.failed - stats.failed)
1854 return -EBADMSG;
1855
1856 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1da177e4
LT		 1857}
1858
1859/**
8593fbc6 1860 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
8b6e50c9
BN		 1861 * @mtd: MTD device structure
1862 * @from: offset to read from
1863 * @ops: oob operation description structure
1da177e4 1864 *
8b6e50c9 1865 * NAND read data and/or out-of-band data.
1da177e4 1866 */
8593fbc6
TG		 1867static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1868 struct mtd_oob_ops *ops)
1da177e4 1869{
ace4dfee 1870 struct nand_chip *chip = mtd->priv;
8593fbc6
TG		 1871 int ret = -ENOTSUPP;
1872
1873 ops->retlen = 0;
1da177e4
LT		 1874
1875 /* Do not allow reads past end of device */
7014568b 1876 if (ops->datbuf && (from + ops->len) > mtd->size) {
289c0522
BN		 1877 pr_debug("%s: attempt to read beyond end of device\n",
1878 __func__);
1da177e4
LT		 1879 return -EINVAL;
1880 }
1881
ace4dfee 1882 nand_get_device(chip, mtd, FL_READING);
1da177e4 1883
f8ac0414 1884 switch (ops->mode) {
0612b9dd
BN		 1885 case MTD_OPS_PLACE_OOB:
1886 case MTD_OPS_AUTO_OOB:
1887 case MTD_OPS_RAW:
8593fbc6 1888 break;
1da177e4 1889
8593fbc6
TG		 1890 default:
1891 goto out;
1892 }
1da177e4 1893
8593fbc6
TG		 1894 if (!ops->datbuf)
1895 ret = nand_do_read_oob(mtd, from, ops);
1896 else
1897 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1898
7351d3a5 1899out:
8593fbc6
TG		 1900 nand_release_device(mtd);
1901 return ret;
1902}
61b03bd7 1903
1da177e4 1904
8593fbc6 1905/**
7854d3f7 1906 * nand_write_page_raw - [INTERN] raw page write function
8b6e50c9
BN		 1907 * @mtd: mtd info structure
1908 * @chip: nand chip info structure
1909 * @buf: data buffer
1fbb938d 1910 * @oob_required: must write chip->oob_poi to OOB
52ff49df 1911 *
7854d3f7 1912 * Not for syndrome calculating ECC controllers, which use a special oob layout.
8593fbc6 1913 */
fdbad98d 1914static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1915 const uint8_t *buf, int oob_required)
8593fbc6
TG		 1916{
1917 chip->write_buf(mtd, buf, mtd->writesize);
279f08d4
BN		 1918 if (oob_required)
1919 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 1920
1921 return 0;
1da177e4
LT		 1922}
1923
52ff49df 1924/**
7854d3f7 1925 * nand_write_page_raw_syndrome - [INTERN] raw page write function
8b6e50c9
BN		 1926 * @mtd: mtd info structure
1927 * @chip: nand chip info structure
1928 * @buf: data buffer
1fbb938d 1929 * @oob_required: must write chip->oob_poi to OOB
52ff49df
DB		 1930 *
1931 * We need a special oob layout and handling even when ECC isn't checked.
1932 */
fdbad98d 1933static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
7351d3a5 1934 struct nand_chip *chip,
1fbb938d 1935 const uint8_t *buf, int oob_required)
52ff49df
DB		 1936{
1937 int eccsize = chip->ecc.size;
1938 int eccbytes = chip->ecc.bytes;
1939 uint8_t *oob = chip->oob_poi;
1940 int steps, size;
1941
1942 for (steps = chip->ecc.steps; steps > 0; steps--) {
1943 chip->write_buf(mtd, buf, eccsize);
1944 buf += eccsize;
1945
1946 if (chip->ecc.prepad) {
1947 chip->write_buf(mtd, oob, chip->ecc.prepad);
1948 oob += chip->ecc.prepad;
1949 }
1950
1951 chip->read_buf(mtd, oob, eccbytes);
1952 oob += eccbytes;
1953
1954 if (chip->ecc.postpad) {
1955 chip->write_buf(mtd, oob, chip->ecc.postpad);
1956 oob += chip->ecc.postpad;
1957 }
1958 }
1959
1960 size = mtd->oobsize - (oob - chip->oob_poi);
1961 if (size)
1962 chip->write_buf(mtd, oob, size);
fdbad98d
JW		 1963
1964 return 0;
52ff49df 1965}
9223a456 1966/**
7854d3f7 1967 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
8b6e50c9
BN		 1968 * @mtd: mtd info structure
1969 * @chip: nand chip info structure
1970 * @buf: data buffer
1fbb938d 1971 * @oob_required: must write chip->oob_poi to OOB
9223a456 1972 */
fdbad98d 1973static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 1974 const uint8_t *buf, int oob_required)
9223a456 1975{
f75e5097
TG		 1976 int i, eccsize = chip->ecc.size;
1977 int eccbytes = chip->ecc.bytes;
1978 int eccsteps = chip->ecc.steps;
4bf63fcb 1979 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1980 const uint8_t *p = buf;
8b099a39 1981 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1982
7854d3f7 1983 /* Software ECC calculation */
8593fbc6
TG		 1984 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1985 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1986
8593fbc6
TG		 1987 for (i = 0; i < chip->ecc.total; i++)
1988 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 1989
fdbad98d 1990 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
f75e5097 1991}
9223a456 1992
f75e5097 1993/**
7854d3f7 1994 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
8b6e50c9
BN		 1995 * @mtd: mtd info structure
1996 * @chip: nand chip info structure
1997 * @buf: data buffer
1fbb938d 1998 * @oob_required: must write chip->oob_poi to OOB
f75e5097 1999 */
fdbad98d 2000static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d 2001 const uint8_t *buf, int oob_required)
f75e5097
TG		 2002{
2003 int i, eccsize = chip->ecc.size;
2004 int eccbytes = chip->ecc.bytes;
2005 int eccsteps = chip->ecc.steps;
4bf63fcb 2006 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 2007 const uint8_t *p = buf;
8b099a39 2008 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 2009
f75e5097
TG		 2010 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2011 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 2012 chip->write_buf(mtd, p, eccsize);
f75e5097 2013 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 2014 }
2015
f75e5097
TG		 2016 for (i = 0; i < chip->ecc.total; i++)
2017 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2018
2019 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
fdbad98d
JW		 2020
2021 return 0;
9223a456
TG		 2022}
2023
61b03bd7 2024/**
7854d3f7 2025 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
8b6e50c9
BN		 2026 * @mtd: mtd info structure
2027 * @chip: nand chip info structure
2028 * @buf: data buffer
1fbb938d 2029 * @oob_required: must write chip->oob_poi to OOB
1da177e4 2030 *
8b6e50c9
BN		 2031 * The hw generator calculates the error syndrome automatically. Therefore we
2032 * need a special oob layout and handling.
f75e5097 2033 */
fdbad98d 2034static int nand_write_page_syndrome(struct mtd_info *mtd,
1fbb938d
BN		 2035 struct nand_chip *chip,
2036 const uint8_t *buf, int oob_required)
1da177e4 2037{
f75e5097
TG		 2038 int i, eccsize = chip->ecc.size;
2039 int eccbytes = chip->ecc.bytes;
2040 int eccsteps = chip->ecc.steps;
2041 const uint8_t *p = buf;
2042 uint8_t *oob = chip->oob_poi;
1da177e4 2043
f75e5097 2044 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2045
f75e5097
TG		 2046 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2047 chip->write_buf(mtd, p, eccsize);
61b03bd7 2048
f75e5097
TG		 2049 if (chip->ecc.prepad) {
2050 chip->write_buf(mtd, oob, chip->ecc.prepad);
2051 oob += chip->ecc.prepad;
2052 }
2053
2054 chip->ecc.calculate(mtd, p, oob);
2055 chip->write_buf(mtd, oob, eccbytes);
2056 oob += eccbytes;
2057
2058 if (chip->ecc.postpad) {
2059 chip->write_buf(mtd, oob, chip->ecc.postpad);
2060 oob += chip->ecc.postpad;
1da177e4 2061 }
1da177e4 2062 }
f75e5097
TG		 2063
2064 /* Calculate remaining oob bytes */
7e4178f9 2065 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2066 if (i)
2067 chip->write_buf(mtd, oob, i);
fdbad98d
JW		 2068
2069 return 0;
f75e5097
TG		 2070}
2071
2072/**
956e944c 2073 * nand_write_page - [REPLACEABLE] write one page
8b6e50c9
BN		 2074 * @mtd: MTD device structure
2075 * @chip: NAND chip descriptor
2076 * @buf: the data to write
1fbb938d 2077 * @oob_required: must write chip->oob_poi to OOB
8b6e50c9
BN		 2078 * @page: page number to write
2079 * @cached: cached programming
2080 * @raw: use _raw version of write_page
f75e5097
TG		 2081 */
2082static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1fbb938d
BN		 2083 const uint8_t *buf, int oob_required, int page,
2084 int cached, int raw)
f75e5097
TG		 2085{
2086 int status;
2087
2088 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2089
956e944c 2090 if (unlikely(raw))
fdbad98d 2091 status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
956e944c 2092 else
fdbad98d
JW		 2093 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2094
2095 if (status < 0)
2096 return status;
f75e5097
TG		 2097
2098 /*
7854d3f7 2099 * Cached progamming disabled for now. Not sure if it's worth the
8b6e50c9 2100 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
f75e5097
TG		 2101 */
2102 cached = 0;
2103
2104 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2105
2106 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2107 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2108 /*
2109 * See if operation failed and additional status checks are
8b6e50c9 2110 * available.
f75e5097
TG		 2111 */
2112 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2113 status = chip->errstat(mtd, chip, FL_WRITING, status,
2114 page);
2115
2116 if (status & NAND_STATUS_FAIL)
2117 return -EIO;
2118 } else {
2119 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2120 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2121 }
2122
2123#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2124 /* Send command to read back the data */
2125 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2126
2127 if (chip->verify_buf(mtd, buf, mtd->writesize))
2128 return -EIO;
09cbe581
BH		 2129
2130 /* Make sure the next page prog is preceded by a status read */
2131 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
f75e5097
TG		 2132#endif
2133 return 0;
1da177e4
LT		 2134}
2135
8593fbc6 2136/**
7854d3f7 2137 * nand_fill_oob - [INTERN] Transfer client buffer to oob
f722013e 2138 * @mtd: MTD device structure
8b6e50c9
BN		 2139 * @oob: oob data buffer
2140 * @len: oob data write length
2141 * @ops: oob ops structure
8593fbc6 2142 */
f722013e
TAA		 2143static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2144 struct mtd_oob_ops *ops)
8593fbc6 2145{
f722013e
TAA		 2146 struct nand_chip *chip = mtd->priv;
2147
2148 /*
2149 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2150 * data from a previous OOB read.
2151 */
2152 memset(chip->oob_poi, 0xff, mtd->oobsize);
2153
f8ac0414 2154 switch (ops->mode) {
8593fbc6 2155
0612b9dd
BN		 2156 case MTD_OPS_PLACE_OOB:
2157 case MTD_OPS_RAW:
8593fbc6
TG		 2158 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2159 return oob + len;
2160
0612b9dd 2161 case MTD_OPS_AUTO_OOB: {
8593fbc6 2162 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2163 uint32_t boffs = 0, woffs = ops->ooboffs;
2164 size_t bytes = 0;
8593fbc6 2165
f8ac0414 2166 for (; free->length && len; free++, len -= bytes) {
8b6e50c9 2167 /* Write request not from offset 0? */
7bc3312b
TG		 2168 if (unlikely(woffs)) {
2169 if (woffs >= free->length) {
2170 woffs -= free->length;
2171 continue;
2172 }
2173 boffs = free->offset + woffs;
2174 bytes = min_t(size_t, len,
2175 (free->length - woffs));
2176 woffs = 0;
2177 } else {
2178 bytes = min_t(size_t, len, free->length);
2179 boffs = free->offset;
2180 }
8b0036ee 2181 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2182 oob += bytes;
2183 }
2184 return oob;
2185 }
2186 default:
2187 BUG();
2188 }
2189 return NULL;
2190}
2191
f8ac0414 2192#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2193
2194/**
7854d3f7 2195 * nand_do_write_ops - [INTERN] NAND write with ECC
8b6e50c9
BN		 2196 * @mtd: MTD device structure
2197 * @to: offset to write to
2198 * @ops: oob operations description structure
1da177e4 2199 *
8b6e50c9 2200 * NAND write with ECC.
1da177e4 2201 */
8593fbc6
TG		 2202static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2203 struct mtd_oob_ops *ops)
1da177e4 2204{
29072b96 2205 int chipnr, realpage, page, blockmask, column;
ace4dfee 2206 struct nand_chip *chip = mtd->priv;
8593fbc6 2207 uint32_t writelen = ops->len;
782ce79a
ML		 2208
2209 uint32_t oobwritelen = ops->ooblen;
0612b9dd 2210 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
782ce79a
ML		 2211 mtd->oobavail : mtd->oobsize;
2212
8593fbc6
TG		 2213 uint8_t *oob = ops->oobbuf;
2214 uint8_t *buf = ops->datbuf;
29072b96 2215 int ret, subpage;
e47f3db4 2216 int oob_required = oob ? 1 : 0;
1da177e4 2217
8593fbc6 2218 ops->retlen = 0;
29072b96
TG		 2219 if (!writelen)
2220 return 0;
1da177e4 2221
8b6e50c9 2222 /* Reject writes, which are not page aligned */
8593fbc6 2223 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
d0370219
BN		 2224 pr_notice("%s: attempt to write non page aligned data\n",
2225 __func__);
1da177e4
LT		 2226 return -EINVAL;
2227 }
2228
29072b96
TG		 2229 column = to & (mtd->writesize - 1);
2230 subpage = column || (writelen & (mtd->writesize - 1));
2231
2232 if (subpage && oob)
2233 return -EINVAL;
1da177e4 2234
6a930961
TG		 2235 chipnr = (int)(to >> chip->chip_shift);
2236 chip->select_chip(mtd, chipnr);
2237
1da177e4
LT		 2238 /* Check, if it is write protected */
2239 if (nand_check_wp(mtd))
8593fbc6 2240 return -EIO;
1da177e4 2241
f75e5097
TG		 2242 realpage = (int)(to >> chip->page_shift);
2243 page = realpage & chip->pagemask;
2244 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2245
2246 /* Invalidate the page cache, when we write to the cached page */
2247 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 2248 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2249 chip->pagebuf = -1;
61b03bd7 2250
782ce79a 2251 /* Don't allow multipage oob writes with offset */
cdcf12b2 2252 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
782ce79a
ML		 2253 return -EINVAL;
2254
f8ac0414 2255 while (1) {
29072b96 2256 int bytes = mtd->writesize;
f75e5097 2257 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 2258 uint8_t *wbuf = buf;
2259
8b6e50c9 2260 /* Partial page write? */
29072b96
TG		 2261 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2262 cached = 0;
2263 bytes = min_t(int, bytes - column, (int) writelen);
2264 chip->pagebuf = -1;
2265 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2266 memcpy(&chip->buffers->databuf[column], buf, bytes);
2267 wbuf = chip->buffers->databuf;
2268 }
1da177e4 2269
782ce79a
ML		 2270 if (unlikely(oob)) {
2271 size_t len = min(oobwritelen, oobmaxlen);
f722013e 2272 oob = nand_fill_oob(mtd, oob, len, ops);
782ce79a 2273 oobwritelen -= len;
f722013e
TAA		 2274 } else {
2275 /* We still need to erase leftover OOB data */
2276 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2277 }
8593fbc6 2278
e47f3db4
BN		 2279 ret = chip->write_page(mtd, chip, wbuf, oob_required, page,
2280 cached, (ops->mode == MTD_OPS_RAW));
f75e5097
TG		 2281 if (ret)
2282 break;
2283
2284 writelen -= bytes;
2285 if (!writelen)
2286 break;
2287
29072b96 2288 column = 0;
f75e5097
TG		 2289 buf += bytes;
2290 realpage++;
2291
2292 page = realpage & chip->pagemask;
2293 /* Check, if we cross a chip boundary */
2294 if (!page) {
2295 chipnr++;
2296 chip->select_chip(mtd, -1);
2297 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2298 }
2299 }
8593fbc6 2300
8593fbc6 2301 ops->retlen = ops->len - writelen;
7014568b
VW		 2302 if (unlikely(oob))
2303 ops->oobretlen = ops->ooblen;
1da177e4
LT		 2304 return ret;
2305}
2306
2af7c653
SK		 2307/**
2308 * panic_nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2309 * @mtd: MTD device structure
2310 * @to: offset to write to
2311 * @len: number of bytes to write
2312 * @retlen: pointer to variable to store the number of written bytes
2313 * @buf: the data to write
2af7c653
SK		 2314 *
2315 * NAND write with ECC. Used when performing writes in interrupt context, this
2316 * may for example be called by mtdoops when writing an oops while in panic.
2317 */
2318static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2319 size_t *retlen, const uint8_t *buf)
2320{
2321 struct nand_chip *chip = mtd->priv;
4a89ff88 2322 struct mtd_oob_ops ops;
2af7c653
SK		 2323 int ret;
2324
8b6e50c9 2325 /* Wait for the device to get ready */
2af7c653
SK		 2326 panic_nand_wait(mtd, chip, 400);
2327
8b6e50c9 2328 /* Grab the device */
2af7c653
SK		 2329 panic_nand_get_device(chip, mtd, FL_WRITING);
2330
4a89ff88
BN		 2331 ops.len = len;
2332 ops.datbuf = (uint8_t *)buf;
2333 ops.oobbuf = NULL;
23b1a99b 2334 ops.mode = 0;
2af7c653 2335
4a89ff88 2336 ret = nand_do_write_ops(mtd, to, &ops);
2af7c653 2337
4a89ff88 2338 *retlen = ops.retlen;
2af7c653
SK		 2339 return ret;
2340}
2341
f75e5097 2342/**
8593fbc6 2343 * nand_write - [MTD Interface] NAND write with ECC
8b6e50c9
BN		 2344 * @mtd: MTD device structure
2345 * @to: offset to write to
2346 * @len: number of bytes to write
2347 * @retlen: pointer to variable to store the number of written bytes
2348 * @buf: the data to write
f75e5097 2349 *
8b6e50c9 2350 * NAND write with ECC.
f75e5097 2351 */
8593fbc6
TG		 2352static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2353 size_t *retlen, const uint8_t *buf)
f75e5097
TG		 2354{
2355 struct nand_chip *chip = mtd->priv;
4a89ff88 2356 struct mtd_oob_ops ops;
f75e5097
TG		 2357 int ret;
2358
7bc3312b 2359 nand_get_device(chip, mtd, FL_WRITING);
4a89ff88
BN		 2360 ops.len = len;
2361 ops.datbuf = (uint8_t *)buf;
2362 ops.oobbuf = NULL;
23b1a99b 2363 ops.mode = 0;
4a89ff88 2364 ret = nand_do_write_ops(mtd, to, &ops);
4a89ff88 2365 *retlen = ops.retlen;
f75e5097 2366 nand_release_device(mtd);
8593fbc6 2367 return ret;
f75e5097 2368}
7314e9e7 2369
1da177e4 2370/**
8593fbc6 2371 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
8b6e50c9
BN		 2372 * @mtd: MTD device structure
2373 * @to: offset to write to
2374 * @ops: oob operation description structure
1da177e4 2375 *
8b6e50c9 2376 * NAND write out-of-band.
1da177e4 2377 */
8593fbc6
TG		 2378static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2379 struct mtd_oob_ops *ops)
1da177e4 2380{
03736155 2381 int chipnr, page, status, len;
ace4dfee 2382 struct nand_chip *chip = mtd->priv;
1da177e4 2383
289c0522 2384 pr_debug("%s: to = 0x%08x, len = %i\n",
20d8e248 2385 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2386
0612b9dd 2387 if (ops->mode == MTD_OPS_AUTO_OOB)
03736155
AH		 2388 len = chip->ecc.layout->oobavail;
2389 else
2390 len = mtd->oobsize;
2391
1da177e4 2392 /* Do not allow write past end of page */
03736155 2393 if ((ops->ooboffs + ops->ooblen) > len) {
289c0522
BN		 2394 pr_debug("%s: attempt to write past end of page\n",
2395 __func__);
1da177e4
LT		 2396 return -EINVAL;
2397 }
2398
03736155 2399 if (unlikely(ops->ooboffs >= len)) {
289c0522
BN		 2400 pr_debug("%s: attempt to start write outside oob\n",
2401 __func__);
03736155
AH		 2402 return -EINVAL;
2403 }
2404
775adc3d 2405 /* Do not allow write past end of device */
03736155
AH		 2406 if (unlikely(to >= mtd->size ||
2407 ops->ooboffs + ops->ooblen >
2408 ((mtd->size >> chip->page_shift) -
2409 (to >> chip->page_shift)) * len)) {
289c0522
BN		 2410 pr_debug("%s: attempt to write beyond end of device\n",
2411 __func__);
03736155
AH		 2412 return -EINVAL;
2413 }
2414
7314e9e7 2415 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2416 chip->select_chip(mtd, chipnr);
1da177e4 2417
7314e9e7
TG		 2418 /* Shift to get page */
2419 page = (int)(to >> chip->page_shift);
2420
2421 /*
2422 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2423 * of my DiskOnChip 2000 test units) will clear the whole data page too
2424 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2425 * it in the doc2000 driver in August 1999. dwmw2.
2426 */
ace4dfee 2427 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2428
2429 /* Check, if it is write protected */
2430 if (nand_check_wp(mtd))
8593fbc6 2431 return -EROFS;
61b03bd7 2432
1da177e4 2433 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2434 if (page == chip->pagebuf)
2435 chip->pagebuf = -1;
1da177e4 2436
f722013e 2437 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
9ce244b3 2438
0612b9dd 2439 if (ops->mode == MTD_OPS_RAW)
9ce244b3
BN		 2440 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2441 else
2442 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1da177e4 2443
7bc3312b
TG		 2444 if (status)
2445 return status;
1da177e4 2446
7014568b 2447 ops->oobretlen = ops->ooblen;
1da177e4 2448
7bc3312b 2449 return 0;
8593fbc6
TG		 2450}
2451
2452/**
2453 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
8b6e50c9
BN		 2454 * @mtd: MTD device structure
2455 * @to: offset to write to
2456 * @ops: oob operation description structure
8593fbc6
TG		 2457 */
2458static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2459 struct mtd_oob_ops *ops)
2460{
8593fbc6
TG		 2461 struct nand_chip *chip = mtd->priv;
2462 int ret = -ENOTSUPP;
2463
2464 ops->retlen = 0;
2465
2466 /* Do not allow writes past end of device */
7014568b 2467 if (ops->datbuf && (to + ops->len) > mtd->size) {
289c0522
BN		 2468 pr_debug("%s: attempt to write beyond end of device\n",
2469 __func__);
8593fbc6
TG		 2470 return -EINVAL;
2471 }
2472
7bc3312b 2473 nand_get_device(chip, mtd, FL_WRITING);
8593fbc6 2474
f8ac0414 2475 switch (ops->mode) {
0612b9dd
BN		 2476 case MTD_OPS_PLACE_OOB:
2477 case MTD_OPS_AUTO_OOB:
2478 case MTD_OPS_RAW:
8593fbc6
TG		 2479 break;
2480
2481 default:
2482 goto out;
2483 }
2484
2485 if (!ops->datbuf)
2486 ret = nand_do_write_oob(mtd, to, ops);
2487 else
2488 ret = nand_do_write_ops(mtd, to, ops);
2489
7351d3a5 2490out:
1da177e4 2491 nand_release_device(mtd);
1da177e4
LT		 2492 return ret;
2493}
2494
1da177e4 2495/**
7854d3f7 2496 * single_erase_cmd - [GENERIC] NAND standard block erase command function
8b6e50c9
BN		 2497 * @mtd: MTD device structure
2498 * @page: the page address of the block which will be erased
1da177e4 2499 *
8b6e50c9 2500 * Standard erase command for NAND chips.
1da177e4 2501 */
e0c7d767 2502static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2503{
ace4dfee 2504 struct nand_chip *chip = mtd->priv;
1da177e4 2505 /* Send commands to erase a block */
ace4dfee
TG		 2506 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2507 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2508}
2509
2510/**
7854d3f7 2511 * multi_erase_cmd - [GENERIC] AND specific block erase command function
8b6e50c9
BN		 2512 * @mtd: MTD device structure
2513 * @page: the page address of the block which will be erased
1da177e4 2514 *
8b6e50c9 2515 * AND multi block erase command function. Erase 4 consecutive blocks.
1da177e4 2516 */
e0c7d767 2517static void multi_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2518{
ace4dfee 2519 struct nand_chip *chip = mtd->priv;
1da177e4 2520 /* Send commands to erase a block */
ace4dfee
TG		 2521 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2522 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2523 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2524 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2525 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2526}
2527
2528/**
2529 * nand_erase - [MTD Interface] erase block(s)
8b6e50c9
BN		 2530 * @mtd: MTD device structure
2531 * @instr: erase instruction
1da177e4 2532 *
8b6e50c9 2533 * Erase one ore more blocks.
1da177e4 2534 */
e0c7d767 2535static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2536{
e0c7d767 2537 return nand_erase_nand(mtd, instr, 0);
1da177e4 2538}
61b03bd7 2539
30f464b7 2540#define BBT_PAGE_MASK 0xffffff3f
1da177e4 2541/**
7854d3f7 2542 * nand_erase_nand - [INTERN] erase block(s)
8b6e50c9
BN		 2543 * @mtd: MTD device structure
2544 * @instr: erase instruction
2545 * @allowbbt: allow erasing the bbt area
1da177e4 2546 *
8b6e50c9 2547 * Erase one ore more blocks.
1da177e4 2548 */
ace4dfee
TG		 2549int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2550 int allowbbt)
1da177e4 2551{
69423d99 2552 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2553 struct nand_chip *chip = mtd->priv;
f8ac0414 2554 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
ace4dfee 2555 unsigned int bbt_masked_page = 0xffffffff;
69423d99 2556 loff_t len;
1da177e4 2557
289c0522
BN		 2558 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2559 __func__, (unsigned long long)instr->addr,
2560 (unsigned long long)instr->len);
1da177e4 2561
6fe5a6ac 2562 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2563 return -EINVAL;
1da177e4 2564
1da177e4 2565 /* Grab the lock and see if the device is available */
ace4dfee 2566 nand_get_device(chip, mtd, FL_ERASING);
1da177e4
LT		 2567
2568 /* Shift to get first page */
ace4dfee
TG		 2569 page = (int)(instr->addr >> chip->page_shift);
2570 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2571
2572 /* Calculate pages in each block */
ace4dfee 2573 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2574
2575 /* Select the NAND device */
ace4dfee 2576 chip->select_chip(mtd, chipnr);
1da177e4 2577
1da177e4
LT		 2578 /* Check, if it is write protected */
2579 if (nand_check_wp(mtd)) {
289c0522
BN		 2580 pr_debug("%s: device is write protected!\n",
2581 __func__);
1da177e4
LT		 2582 instr->state = MTD_ERASE_FAILED;
2583 goto erase_exit;
2584 }
2585
ace4dfee
TG		 2586 /*
2587 * If BBT requires refresh, set the BBT page mask to see if the BBT
2588 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2589 * can not be matched. This is also done when the bbt is actually
7854d3f7 2590 * erased to avoid recursive updates.
ace4dfee
TG		 2591 */
2592 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2593 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
30f464b7 2594
1da177e4
LT		 2595 /* Loop through the pages */
2596 len = instr->len;
2597
2598 instr->state = MTD_ERASING;
2599
2600 while (len) {
12183a20 2601 /* Check if we have a bad block, we do not erase bad blocks! */
ace4dfee
TG		 2602 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2603 chip->page_shift, 0, allowbbt)) {
d0370219
BN		 2604 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2605 __func__, page);
1da177e4
LT		 2606 instr->state = MTD_ERASE_FAILED;
2607 goto erase_exit;
2608 }
61b03bd7 2609
ace4dfee
TG		 2610 /*
2611 * Invalidate the page cache, if we erase the block which
8b6e50c9 2612 * contains the current cached page.
ace4dfee
TG		 2613 */
2614 if (page <= chip->pagebuf && chip->pagebuf <
2615 (page + pages_per_block))
2616 chip->pagebuf = -1;
1da177e4 2617
ace4dfee 2618 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2619
7bc3312b 2620 status = chip->waitfunc(mtd, chip);
1da177e4 2621
ace4dfee
TG		 2622 /*
2623 * See if operation failed and additional status checks are
2624 * available
2625 */
2626 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2627 status = chip->errstat(mtd, chip, FL_ERASING,
2628 status, page);
068e3c0a 2629
1da177e4 2630 /* See if block erase succeeded */
a4ab4c5d 2631 if (status & NAND_STATUS_FAIL) {
289c0522
BN		 2632 pr_debug("%s: failed erase, page 0x%08x\n",
2633 __func__, page);
1da177e4 2634 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2635 instr->fail_addr =
2636 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2637 goto erase_exit;
2638 }
30f464b7 2639
ace4dfee
TG		 2640 /*
2641 * If BBT requires refresh, set the BBT rewrite flag to the
8b6e50c9 2642 * page being erased.
ace4dfee
TG		 2643 */
2644 if (bbt_masked_page != 0xffffffff &&
2645 (page & BBT_PAGE_MASK) == bbt_masked_page)
69423d99
AH		 2646 rewrite_bbt[chipnr] =
2647 ((loff_t)page << chip->page_shift);
61b03bd7 2648
1da177e4 2649 /* Increment page address and decrement length */
ace4dfee 2650 len -= (1 << chip->phys_erase_shift);
1da177e4
LT		 2651 page += pages_per_block;
2652
2653 /* Check, if we cross a chip boundary */
ace4dfee 2654 if (len && !(page & chip->pagemask)) {
1da177e4 2655 chipnr++;
ace4dfee
TG		 2656 chip->select_chip(mtd, -1);
2657 chip->select_chip(mtd, chipnr);
30f464b7 2658
ace4dfee
TG		 2659 /*
2660 * If BBT requires refresh and BBT-PERCHIP, set the BBT
8b6e50c9 2661 * page mask to see if this BBT should be rewritten.
ace4dfee
TG		 2662 */
2663 if (bbt_masked_page != 0xffffffff &&
2664 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2665 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2666 BBT_PAGE_MASK;
1da177e4
LT		 2667 }
2668 }
2669 instr->state = MTD_ERASE_DONE;
2670
7351d3a5 2671erase_exit:
1da177e4
LT		 2672
2673 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2674
2675 /* Deselect and wake up anyone waiting on the device */
2676 nand_release_device(mtd);
2677
49defc01
DW		 2678 /* Do call back function */
2679 if (!ret)
2680 mtd_erase_callback(instr);
2681
ace4dfee
TG		 2682 /*
2683 * If BBT requires refresh and erase was successful, rewrite any
8b6e50c9 2684 * selected bad block tables.
ace4dfee
TG		 2685 */
2686 if (bbt_masked_page == 0xffffffff || ret)
2687 return ret;
2688
2689 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2690 if (!rewrite_bbt[chipnr])
2691 continue;
8b6e50c9 2692 /* Update the BBT for chip */
289c0522
BN		 2693 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2694 __func__, chipnr, rewrite_bbt[chipnr],
2695 chip->bbt_td->pages[chipnr]);
ace4dfee 2696 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
30f464b7
DM		 2697 }
2698
1da177e4
LT		 2699 /* Return more or less happy */
2700 return ret;
2701}
2702
2703/**
2704 * nand_sync - [MTD Interface] sync
8b6e50c9 2705 * @mtd: MTD device structure
1da177e4 2706 *
8b6e50c9 2707 * Sync is actually a wait for chip ready function.
1da177e4 2708 */
e0c7d767 2709static void nand_sync(struct mtd_info *mtd)
1da177e4 2710{
ace4dfee 2711 struct nand_chip *chip = mtd->priv;
1da177e4 2712
289c0522 2713 pr_debug("%s: called\n", __func__);
1da177e4
LT		 2714
2715 /* Grab the lock and see if the device is available */
ace4dfee 2716 nand_get_device(chip, mtd, FL_SYNCING);
1da177e4 2717 /* Release it and go back */
e0c7d767 2718 nand_release_device(mtd);
1da177e4
LT		 2719}
2720
1da177e4 2721/**
ace4dfee 2722 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
8b6e50c9
BN		 2723 * @mtd: MTD device structure
2724 * @offs: offset relative to mtd start
1da177e4 2725 */
ace4dfee 2726static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4 2727{
ace4dfee 2728 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2729}
2730
2731/**
ace4dfee 2732 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
8b6e50c9
BN		 2733 * @mtd: MTD device structure
2734 * @ofs: offset relative to mtd start
1da177e4 2735 */
e0c7d767 2736static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2737{
ace4dfee 2738 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2739 int ret;
2740
f8ac0414
FF		 2741 ret = nand_block_isbad(mtd, ofs);
2742 if (ret) {
8b6e50c9 2743 /* If it was bad already, return success and do nothing */
1da177e4
LT		 2744 if (ret > 0)
2745 return 0;
e0c7d767
DW		 2746 return ret;
2747 }
1da177e4 2748
ace4dfee 2749 return chip->block_markbad(mtd, ofs);
1da177e4
LT		 2750}
2751
962034f4
VW		 2752/**
2753 * nand_suspend - [MTD Interface] Suspend the NAND flash
8b6e50c9 2754 * @mtd: MTD device structure
962034f4
VW		 2755 */
2756static int nand_suspend(struct mtd_info *mtd)
2757{
ace4dfee 2758 struct nand_chip *chip = mtd->priv;
962034f4 2759
ace4dfee 2760 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
962034f4
VW		 2761}
2762
2763/**
2764 * nand_resume - [MTD Interface] Resume the NAND flash
8b6e50c9 2765 * @mtd: MTD device structure
962034f4
VW		 2766 */
2767static void nand_resume(struct mtd_info *mtd)
2768{
ace4dfee 2769 struct nand_chip *chip = mtd->priv;
962034f4 2770
ace4dfee 2771 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2772 nand_release_device(mtd);
2773 else
d0370219
BN		 2774 pr_err("%s called for a chip which is not in suspended state\n",
2775 __func__);
962034f4
VW		 2776}
2777
8b6e50c9 2778/* Set default functions */
ace4dfee 2779static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2780{
1da177e4 2781 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2782 if (!chip->chip_delay)
2783 chip->chip_delay = 20;
1da177e4
LT		 2784
2785 /* check, if a user supplied command function given */
ace4dfee
TG		 2786 if (chip->cmdfunc == NULL)
2787 chip->cmdfunc = nand_command;
1da177e4
LT		 2788
2789 /* check, if a user supplied wait function given */
ace4dfee
TG		 2790 if (chip->waitfunc == NULL)
2791 chip->waitfunc = nand_wait;
2792
2793 if (!chip->select_chip)
2794 chip->select_chip = nand_select_chip;
2795 if (!chip->read_byte)
2796 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2797 if (!chip->read_word)
2798 chip->read_word = nand_read_word;
2799 if (!chip->block_bad)
2800 chip->block_bad = nand_block_bad;
2801 if (!chip->block_markbad)
2802 chip->block_markbad = nand_default_block_markbad;
2803 if (!chip->write_buf)
2804 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2805 if (!chip->read_buf)
2806 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2807 if (!chip->verify_buf)
2808 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2809 if (!chip->scan_bbt)
2810 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2811
2812 if (!chip->controller) {
2813 chip->controller = &chip->hwcontrol;
2814 spin_lock_init(&chip->controller->lock);
2815 init_waitqueue_head(&chip->controller->wq);
2816 }
2817
7aa65bfd
TG		 2818}
2819
8b6e50c9 2820/* Sanitize ONFI strings so we can safely print them */
d1e1f4e4
FF		 2821static void sanitize_string(uint8_t *s, size_t len)
2822{
2823 ssize_t i;
2824
8b6e50c9 2825 /* Null terminate */
d1e1f4e4
FF		 2826 s[len - 1] = 0;
2827
8b6e50c9 2828 /* Remove non printable chars */
d1e1f4e4
FF		 2829 for (i = 0; i < len - 1; i++) {
2830 if (s[i] < ' ' || s[i] > 127)
2831 s[i] = '?';
2832 }
2833
8b6e50c9 2834 /* Remove trailing spaces */
d1e1f4e4
FF		 2835 strim(s);
2836}
2837
2838static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2839{
2840 int i;
2841 while (len--) {
2842 crc ^= *p++ << 8;
2843 for (i = 0; i < 8; i++)
2844 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2845 }
2846
2847 return crc;
2848}
2849
6fb277ba 2850/*
8b6e50c9 2851 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
6fb277ba
FF		 2852 */
2853static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
08c248fb 2854 int *busw)
6fb277ba
FF		 2855{
2856 struct nand_onfi_params *p = &chip->onfi_params;
2857 int i;
2858 int val;
2859
7854d3f7 2860 /* Try ONFI for unknown chip or LP */
6fb277ba
FF		 2861 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2862 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2863 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2864 return 0;
2865
6fb277ba
FF		 2866 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2867 for (i = 0; i < 3; i++) {
2868 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2869 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2870 le16_to_cpu(p->crc)) {
9a4d4d69 2871 pr_info("ONFI param page %d valid\n", i);
6fb277ba
FF		 2872 break;
2873 }
2874 }
2875
2876 if (i == 3)
2877 return 0;
2878
8b6e50c9 2879 /* Check version */
6fb277ba 2880 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 2881 if (val & (1 << 5))
2882 chip->onfi_version = 23;
2883 else if (val & (1 << 4))
6fb277ba
FF		 2884 chip->onfi_version = 22;
2885 else if (val & (1 << 3))
2886 chip->onfi_version = 21;
2887 else if (val & (1 << 2))
2888 chip->onfi_version = 20;
b7b1a29d 2889 else if (val & (1 << 1))
6fb277ba 2890 chip->onfi_version = 10;
b7b1a29d
BN		 2891 else
2892 chip->onfi_version = 0;
2893
2894 if (!chip->onfi_version) {
d0370219 2895 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
b7b1a29d
BN		 2896 return 0;
2897 }
6fb277ba
FF		 2898
2899 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2900 sanitize_string(p->model, sizeof(p->model));
2901 if (!mtd->name)
2902 mtd->name = p->model;
2903 mtd->writesize = le32_to_cpu(p->byte_per_page);
2904 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2905 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
63795755
MC		 2906 chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2907 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
08c248fb 2908 *busw = 0;
6fb277ba 2909 if (le16_to_cpu(p->features) & 1)
08c248fb 2910 *busw = NAND_BUSWIDTH_16;
6fb277ba
FF		 2911
2912 chip->options &= ~NAND_CHIPOPTIONS_MSK;
6fb277ba 2913
d42b5de3 2914 pr_info("ONFI flash detected\n");
6fb277ba
FF		 2915 return 1;
2916}
2917
7aa65bfd 2918/*
8b6e50c9 2919 * Get the flash and manufacturer id and lookup if the type is supported.
7aa65bfd
TG		 2920 */
2921static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 2922 struct nand_chip *chip,
7351d3a5
FF		 2923 int busw,
2924 int *maf_id, int *dev_id,
5e81e88a 2925 struct nand_flash_dev *type)
7aa65bfd 2926{
d1e1f4e4 2927 int i, maf_idx;
426c457a 2928 u8 id_data[8];
6fb277ba 2929 int ret;
1da177e4
LT		 2930
2931 /* Select the device */
ace4dfee 2932 chip->select_chip(mtd, 0);
1da177e4 2933
ef89a880
KB		 2934 /*
2935 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
8b6e50c9 2936 * after power-up.
ef89a880
KB		 2937 */
2938 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2939
1da177e4 2940 /* Send the command for reading device ID */
ace4dfee 2941 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 2942
2943 /* Read manufacturer and device IDs */
ace4dfee 2944 *maf_id = chip->read_byte(mtd);
d1e1f4e4 2945 *dev_id = chip->read_byte(mtd);
1da177e4 2946
8b6e50c9
BN		 2947 /*
2948 * Try again to make sure, as some systems the bus-hold or other
ed8165c7
BD		 2949 * interface concerns can cause random data which looks like a
2950 * possibly credible NAND flash to appear. If the two results do
2951 * not match, ignore the device completely.
2952 */
2953
2954 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2955
d1e1f4e4 2956 for (i = 0; i < 2; i++)
426c457a 2957 id_data[i] = chip->read_byte(mtd);
ed8165c7 2958
d1e1f4e4 2959 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
9a4d4d69 2960 pr_info("%s: second ID read did not match "
d0370219
BN		 2961 "%02x,%02x against %02x,%02x\n", __func__,
2962 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 2963 return ERR_PTR(-ENODEV);
2964 }
2965
7aa65bfd 2966 if (!type)
5e81e88a
DW		 2967 type = nand_flash_ids;
2968
2969 for (; type->name != NULL; type++)
d1e1f4e4 2970 if (*dev_id == type->id)
f8ac0414 2971 break;
5e81e88a 2972
d1e1f4e4
FF		 2973 chip->onfi_version = 0;
2974 if (!type->name || !type->pagesize) {
6fb277ba 2975 /* Check is chip is ONFI compliant */
08c248fb 2976 ret = nand_flash_detect_onfi(mtd, chip, &busw);
6fb277ba
FF		 2977 if (ret)
2978 goto ident_done;
d1e1f4e4
FF		 2979 }
2980
2981 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2982
2983 /* Read entire ID string */
2984
2985 for (i = 0; i < 8; i++)
2986 id_data[i] = chip->read_byte(mtd);
2987
5e81e88a 2988 if (!type->name)
7aa65bfd
TG		 2989 return ERR_PTR(-ENODEV);
2990
ba0251fe
TG		 2991 if (!mtd->name)
2992 mtd->name = type->name;
2993
69423d99 2994 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 2995
12a40a57 2996 if (!type->pagesize && chip->init_size) {
8b6e50c9 2997 /* Set the pagesize, oobsize, erasesize by the driver */
12a40a57
HS		 2998 busw = chip->init_size(mtd, chip, id_data);
2999 } else if (!type->pagesize) {
7aa65bfd 3000 int extid;
29072b96 3001 /* The 3rd id byte holds MLC / multichip data */
426c457a 3002 chip->cellinfo = id_data[2];
7aa65bfd 3003 /* The 4th id byte is the important one */
426c457a 3004 extid = id_data[3];
61b03bd7 3005
426c457a
KC		 3006 /*
3007 * Field definitions are in the following datasheets:
3008 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
34c5bf6c 3009 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
426c457a
KC		 3010 *
3011 * Check for wraparound + Samsung ID + nonzero 6th byte
3012 * to decide what to do.
3013 */
3014 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
3015 id_data[0] == NAND_MFR_SAMSUNG &&
cfe3fdad 3016 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
426c457a
KC		 3017 id_data[5] != 0x00) {
3018 /* Calc pagesize */
3019 mtd->writesize = 2048 << (extid & 0x03);
3020 extid >>= 2;
3021 /* Calc oobsize */
34c5bf6c
BN		 3022 switch (extid & 0x03) {
3023 case 1:
3024 mtd->oobsize = 128;
3025 break;
3026 case 2:
3027 mtd->oobsize = 218;
3028 break;
3029 case 3:
3030 mtd->oobsize = 400;
3031 break;
3032 default:
3033 mtd->oobsize = 436;
3034 break;
3035 }
426c457a
KC		 3036 extid >>= 2;
3037 /* Calc blocksize */
3038 mtd->erasesize = (128 * 1024) <<
3039 (((extid >> 1) & 0x04) | (extid & 0x03));
3040 busw = 0;
3041 } else {
3042 /* Calc pagesize */
3043 mtd->writesize = 1024 << (extid & 0x03);
3044 extid >>= 2;
3045 /* Calc oobsize */
3046 mtd->oobsize = (8 << (extid & 0x01)) *
3047 (mtd->writesize >> 9);
3048 extid >>= 2;
3049 /* Calc blocksize. Blocksize is multiples of 64KiB */
3050 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3051 extid >>= 2;
3052 /* Get buswidth information */
3053 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3054 }
7aa65bfd
TG		 3055 } else {
3056 /*
8b6e50c9 3057 * Old devices have chip data hardcoded in the device id table.
7aa65bfd 3058 */
ba0251fe
TG		 3059 mtd->erasesize = type->erasesize;
3060 mtd->writesize = type->pagesize;
4cbb9b80 3061 mtd->oobsize = mtd->writesize / 32;
ba0251fe 3062 busw = type->options & NAND_BUSWIDTH_16;
2173bae8
BN		 3063
3064 /*
3065 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3066 * some Spansion chips have erasesize that conflicts with size
8b6e50c9 3067 * listed in nand_ids table.
2173bae8
BN		 3068 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3069 */
3070 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3071 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3072 id_data[7] == 0x00 && mtd->writesize == 512) {
3073 mtd->erasesize = 128 * 1024;
3074 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3075 }
7aa65bfd 3076 }
d1e1f4e4
FF		 3077 /* Get chip options, preserve non chip based options */
3078 chip->options &= ~NAND_CHIPOPTIONS_MSK;
3079 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3080
8b6e50c9
BN		 3081 /*
3082 * Check if chip is not a Samsung device. Do not clear the
3083 * options for chips which do not have an extended id.
d1e1f4e4
FF		 3084 */
3085 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3086 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3087ident_done:
3088
7aa65bfd 3089 /* Try to identify manufacturer */
9a909867 3090 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3091 if (nand_manuf_ids[maf_idx].id == *maf_id)
3092 break;
3093 }
0ea4a755 3094
7aa65bfd
TG		 3095 /*
3096 * Check, if buswidth is correct. Hardware drivers should set
8b6e50c9 3097 * chip correct!
7aa65bfd 3098 */
ace4dfee 3099 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
9a4d4d69 3100 pr_info("NAND device: Manufacturer ID:"
d0370219
BN		 3101 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3102 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
9a4d4d69 3103 pr_warn("NAND bus width %d instead %d bit\n",
d0370219
BN		 3104 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3105 busw ? 16 : 8);
7aa65bfd
TG		 3106 return ERR_PTR(-EINVAL);
3107 }
61b03bd7 3108
7aa65bfd 3109 /* Calculate the address shift from the page size */
ace4dfee 3110 chip->page_shift = ffs(mtd->writesize) - 1;
8b6e50c9 3111 /* Convert chipsize to number of pages per chip -1 */
ace4dfee 3112 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3113
ace4dfee 3114 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3115 ffs(mtd->erasesize) - 1;
69423d99
AH		 3116 if (chip->chipsize & 0xffffffff)
3117 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3118 else {
3119 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3120 chip->chip_shift += 32 - 1;
3121 }
1da177e4 3122
26d9be11
AB		 3123 chip->badblockbits = 8;
3124
7aa65bfd 3125 /* Set the bad block position */
065a1ed8 3126 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
c7b28e25 3127 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
065a1ed8
BN		 3128 else
3129 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
61b03bd7 3130
b60b08b0
KC		 3131 /*
3132 * Bad block marker is stored in the last page of each block
c7b28e25
BN		 3133 * on Samsung and Hynix MLC devices; stored in first two pages
3134 * of each block on Micron devices with 2KiB pages and on
8c342335
BN		 3135 * SLC Samsung, Hynix, Toshiba, AMD/Spansion, and Macronix.
3136 * All others scan only the first page.
b60b08b0
KC		 3137 */
3138 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3139 (*maf_id == NAND_MFR_SAMSUNG ||
3140 *maf_id == NAND_MFR_HYNIX))
5fb1549d 3141 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
c7b28e25
BN		 3142 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3143 (*maf_id == NAND_MFR_SAMSUNG ||
3144 *maf_id == NAND_MFR_HYNIX ||
13ed7aed 3145 *maf_id == NAND_MFR_TOSHIBA ||
8c342335
BN		 3146 *maf_id == NAND_MFR_AMD ||
3147 *maf_id == NAND_MFR_MACRONIX)) ||
c7b28e25
BN		 3148 (mtd->writesize == 2048 &&
3149 *maf_id == NAND_MFR_MICRON))
5fb1549d 3150 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
c7b28e25 3151
7aa65bfd 3152 /* Check for AND chips with 4 page planes */
ace4dfee
TG		 3153 if (chip->options & NAND_4PAGE_ARRAY)
3154 chip->erase_cmd = multi_erase_cmd;
7aa65bfd 3155 else
ace4dfee 3156 chip->erase_cmd = single_erase_cmd;
7aa65bfd 3157
8b6e50c9 3158 /* Do not replace user supplied command function! */
ace4dfee
TG		 3159 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3160 chip->cmdfunc = nand_command_lp;
7aa65bfd 3161
886bd33d
HS		 3162 pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
3163 " page size: %d, OOB size: %d\n",
3164 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
3165 chip->onfi_version ? chip->onfi_params.model : type->name,
3166 mtd->writesize, mtd->oobsize);
7aa65bfd
TG		 3167
3168 return type;
3169}
3170
7aa65bfd 3171/**
3b85c321 3172 * nand_scan_ident - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3173 * @mtd: MTD device structure
3174 * @maxchips: number of chips to scan for
3175 * @table: alternative NAND ID table
7aa65bfd 3176 *
8b6e50c9
BN		 3177 * This is the first phase of the normal nand_scan() function. It reads the
3178 * flash ID and sets up MTD fields accordingly.
7aa65bfd 3179 *
3b85c321 3180 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 3181 */
5e81e88a
DW		 3182int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3183 struct nand_flash_dev *table)
7aa65bfd 3184{
d1e1f4e4 3185 int i, busw, nand_maf_id, nand_dev_id;
ace4dfee 3186 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 3187 struct nand_flash_dev *type;
3188
7aa65bfd 3189 /* Get buswidth to select the correct functions */
ace4dfee 3190 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 3191 /* Set the default functions */
ace4dfee 3192 nand_set_defaults(chip, busw);
7aa65bfd
TG		 3193
3194 /* Read the flash type */
7351d3a5
FF		 3195 type = nand_get_flash_type(mtd, chip, busw,
3196 &nand_maf_id, &nand_dev_id, table);
7aa65bfd
TG		 3197
3198 if (IS_ERR(type)) {
b1c6e6db 3199 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
d0370219 3200 pr_warn("No NAND device found\n");
ace4dfee 3201 chip->select_chip(mtd, -1);
7aa65bfd 3202 return PTR_ERR(type);
1da177e4
LT		 3203 }
3204
7aa65bfd 3205 /* Check for a chip array */
e0c7d767 3206 for (i = 1; i < maxchips; i++) {
ace4dfee 3207 chip->select_chip(mtd, i);
ef89a880
KB		 3208 /* See comment in nand_get_flash_type for reset */
3209 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 3210 /* Send the command for reading device ID */
ace4dfee 3211 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 3212 /* Read manufacturer and device IDs */
ace4dfee 3213 if (nand_maf_id != chip->read_byte(mtd) ||
d1e1f4e4 3214 nand_dev_id != chip->read_byte(mtd))
1da177e4
LT		 3215 break;
3216 }
3217 if (i > 1)
9a4d4d69 3218 pr_info("%d NAND chips detected\n", i);
61b03bd7 3219
1da177e4 3220 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 3221 chip->numchips = i;
3222 mtd->size = i * chip->chipsize;
7aa65bfd 3223
3b85c321
DW		 3224 return 0;
3225}
7351d3a5 3226EXPORT_SYMBOL(nand_scan_ident);
3b85c321
DW		 3227
3228
3229/**
3230 * nand_scan_tail - [NAND Interface] Scan for the NAND device
8b6e50c9 3231 * @mtd: MTD device structure
3b85c321 3232 *
8b6e50c9
BN		 3233 * This is the second phase of the normal nand_scan() function. It fills out
3234 * all the uninitialized function pointers with the defaults and scans for a
3235 * bad block table if appropriate.
3b85c321
DW		 3236 */
3237int nand_scan_tail(struct mtd_info *mtd)
3238{
3239 int i;
3240 struct nand_chip *chip = mtd->priv;
3241
e2414f4c
BN		 3242 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3243 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3244 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3245
4bf63fcb
DW		 3246 if (!(chip->options & NAND_OWN_BUFFERS))
3247 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3248 if (!chip->buffers)
3249 return -ENOMEM;
3250
7dcdcbef 3251 /* Set the internal oob buffer location, just after the page data */
784f4d5e 3252 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3253
7aa65bfd 3254 /*
8b6e50c9 3255 * If no default placement scheme is given, select an appropriate one.
7aa65bfd 3256 */
193bd400 3257 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
61b03bd7 3258 switch (mtd->oobsize) {
1da177e4 3259 case 8:
5bd34c09 3260 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 3261 break;
3262 case 16:
5bd34c09 3263 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 3264 break;
3265 case 64:
5bd34c09 3266 chip->ecc.layout = &nand_oob_64;
1da177e4 3267 break;
81ec5364
TG		 3268 case 128:
3269 chip->ecc.layout = &nand_oob_128;
3270 break;
1da177e4 3271 default:
d0370219
BN		 3272 pr_warn("No oob scheme defined for oobsize %d\n",
3273 mtd->oobsize);
1da177e4
LT		 3274 BUG();
3275 }
3276 }
61b03bd7 3277
956e944c
DW		 3278 if (!chip->write_page)
3279 chip->write_page = nand_write_page;
3280
61b03bd7 3281 /*
8b6e50c9 3282 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
7aa65bfd 3283 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3284 */
956e944c 3285
ace4dfee 3286 switch (chip->ecc.mode) {
6e0cb135
SN		 3287 case NAND_ECC_HW_OOB_FIRST:
3288 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3289 if (!chip->ecc.calculate || !chip->ecc.correct ||
3290 !chip->ecc.hwctl) {
9a4d4d69 3291 pr_warn("No ECC functions supplied; "
d0370219 3292 "hardware ECC not possible\n");
6e0cb135
SN		 3293 BUG();
3294 }
3295 if (!chip->ecc.read_page)
3296 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3297
6dfc6d25 3298 case NAND_ECC_HW:
8b6e50c9 3299 /* Use standard hwecc read page function? */
f5bbdacc
TG		 3300 if (!chip->ecc.read_page)
3301 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 3302 if (!chip->ecc.write_page)
3303 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 3304 if (!chip->ecc.read_page_raw)
3305 chip->ecc.read_page_raw = nand_read_page_raw;
3306 if (!chip->ecc.write_page_raw)
3307 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3308 if (!chip->ecc.read_oob)
3309 chip->ecc.read_oob = nand_read_oob_std;
3310 if (!chip->ecc.write_oob)
3311 chip->ecc.write_oob = nand_write_oob_std;
f5bbdacc 3312
6dfc6d25 3313 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 3314 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3315 !chip->ecc.hwctl) &&
3316 (!chip->ecc.read_page ||
1c45f604 3317 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 3318 !chip->ecc.write_page ||
1c45f604 3319 chip->ecc.write_page == nand_write_page_hwecc)) {
9a4d4d69 3320 pr_warn("No ECC functions supplied; "
d0370219 3321 "hardware ECC not possible\n");
6dfc6d25
TG		 3322 BUG();
3323 }
8b6e50c9 3324 /* Use standard syndrome read/write page function? */
f5bbdacc
TG		 3325 if (!chip->ecc.read_page)
3326 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 3327 if (!chip->ecc.write_page)
3328 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 3329 if (!chip->ecc.read_page_raw)
3330 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3331 if (!chip->ecc.write_page_raw)
3332 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 3333 if (!chip->ecc.read_oob)
3334 chip->ecc.read_oob = nand_read_oob_syndrome;
3335 if (!chip->ecc.write_oob)
3336 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 3337
e2788c98
MD		 3338 if (mtd->writesize >= chip->ecc.size) {
3339 if (!chip->ecc.strength) {
3340 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3341 BUG();
3342 }
6dfc6d25 3343 break;
e2788c98 3344 }
9a4d4d69 3345 pr_warn("%d byte HW ECC not possible on "
d0370219
BN		 3346 "%d byte page size, fallback to SW ECC\n",
3347 chip->ecc.size, mtd->writesize);
ace4dfee 3348 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 3349
6dfc6d25 3350 case NAND_ECC_SOFT:
ace4dfee
TG		 3351 chip->ecc.calculate = nand_calculate_ecc;
3352 chip->ecc.correct = nand_correct_data;
f5bbdacc 3353 chip->ecc.read_page = nand_read_page_swecc;
3d459559 3354 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 3355 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 3356 chip->ecc.read_page_raw = nand_read_page_raw;
3357 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3358 chip->ecc.read_oob = nand_read_oob_std;
3359 chip->ecc.write_oob = nand_write_oob_std;
9a73290d
SV		 3360 if (!chip->ecc.size)
3361 chip->ecc.size = 256;
ace4dfee 3362 chip->ecc.bytes = 3;
6a918bad 3363 chip->ecc.strength = 1;
1da177e4 3364 break;
61b03bd7 3365
193bd400
ID		 3366 case NAND_ECC_SOFT_BCH:
3367 if (!mtd_nand_has_bch()) {
9a4d4d69 3368 pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
193bd400
ID		 3369 BUG();
3370 }
3371 chip->ecc.calculate = nand_bch_calculate_ecc;
3372 chip->ecc.correct = nand_bch_correct_data;
3373 chip->ecc.read_page = nand_read_page_swecc;
3374 chip->ecc.read_subpage = nand_read_subpage;
3375 chip->ecc.write_page = nand_write_page_swecc;
3376 chip->ecc.read_page_raw = nand_read_page_raw;
3377 chip->ecc.write_page_raw = nand_write_page_raw;
3378 chip->ecc.read_oob = nand_read_oob_std;
3379 chip->ecc.write_oob = nand_write_oob_std;
3380 /*
3381 * Board driver should supply ecc.size and ecc.bytes values to
3382 * select how many bits are correctable; see nand_bch_init()
8b6e50c9
BN		 3383 * for details. Otherwise, default to 4 bits for large page
3384 * devices.
193bd400
ID		 3385 */
3386 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3387 chip->ecc.size = 512;
3388 chip->ecc.bytes = 7;
3389 }
3390 chip->ecc.priv = nand_bch_init(mtd,
3391 chip->ecc.size,
3392 chip->ecc.bytes,
3393 &chip->ecc.layout);
3394 if (!chip->ecc.priv) {
9a4d4d69 3395 pr_warn("BCH ECC initialization failed!\n");
193bd400
ID		 3396 BUG();
3397 }
6a918bad 3398 chip->ecc.strength =
e2788c98 3399 chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
193bd400
ID		 3400 break;
3401
61b03bd7 3402 case NAND_ECC_NONE:
9a4d4d69 3403 pr_warn("NAND_ECC_NONE selected by board driver. "
d0370219 3404 "This is not recommended!\n");
8593fbc6
TG		 3405 chip->ecc.read_page = nand_read_page_raw;
3406 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 3407 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 3408 chip->ecc.read_page_raw = nand_read_page_raw;
3409 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 3410 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 3411 chip->ecc.size = mtd->writesize;
3412 chip->ecc.bytes = 0;
6a918bad 3413 chip->ecc.strength = 0;
1da177e4 3414 break;
956e944c 3415
1da177e4 3416 default:
d0370219 3417 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
61b03bd7 3418 BUG();
1da177e4 3419 }
61b03bd7 3420
9ce244b3 3421 /* For many systems, the standard OOB write also works for raw */
c46f6483
BN		 3422 if (!chip->ecc.read_oob_raw)
3423 chip->ecc.read_oob_raw = chip->ecc.read_oob;
9ce244b3
BN		 3424 if (!chip->ecc.write_oob_raw)
3425 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3426
5bd34c09
TG		 3427 /*
3428 * The number of bytes available for a client to place data into
8b6e50c9 3429 * the out of band area.
5bd34c09
TG		 3430 */
3431 chip->ecc.layout->oobavail = 0;
81d19b04
DB		 3432 for (i = 0; chip->ecc.layout->oobfree[i].length
3433 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
5bd34c09
TG		 3434 chip->ecc.layout->oobavail +=
3435 chip->ecc.layout->oobfree[i].length;
1f92267c 3436 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 3437
7aa65bfd
TG		 3438 /*
3439 * Set the number of read / write steps for one page depending on ECC
8b6e50c9 3440 * mode.
7aa65bfd 3441 */
ace4dfee 3442 chip->ecc.steps = mtd->writesize / chip->ecc.size;
f8ac0414 3443 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
9a4d4d69 3444 pr_warn("Invalid ECC parameters\n");
6dfc6d25 3445 BUG();
1da177e4 3446 }
f5bbdacc 3447 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 3448
8b6e50c9 3449 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
29072b96
TG		 3450 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3451 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
f8ac0414 3452 switch (chip->ecc.steps) {
29072b96
TG		 3453 case 2:
3454 mtd->subpage_sft = 1;
3455 break;
3456 case 4:
3457 case 8:
81ec5364 3458 case 16:
29072b96
TG		 3459 mtd->subpage_sft = 2;
3460 break;
3461 }
3462 }
3463 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3464
04bbd0ea 3465 /* Initialize state */
ace4dfee 3466 chip->state = FL_READY;
1da177e4
LT		 3467
3468 /* De-select the device */
ace4dfee 3469 chip->select_chip(mtd, -1);
1da177e4
LT		 3470
3471 /* Invalidate the pagebuffer reference */
ace4dfee 3472 chip->pagebuf = -1;
1da177e4
LT		 3473
3474 /* Fill in remaining MTD driver data */
3475 mtd->type = MTD_NANDFLASH;
93edbad6
ML		 3476 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3477 MTD_CAP_NANDFLASH;
3c3c10bb
AB		 3478 mtd->_erase = nand_erase;
3479 mtd->_point = NULL;
3480 mtd->_unpoint = NULL;
3481 mtd->_read = nand_read;
3482 mtd->_write = nand_write;
3483 mtd->_panic_write = panic_nand_write;
3484 mtd->_read_oob = nand_read_oob;
3485 mtd->_write_oob = nand_write_oob;
3486 mtd->_sync = nand_sync;
3487 mtd->_lock = NULL;
3488 mtd->_unlock = NULL;
3489 mtd->_suspend = nand_suspend;
3490 mtd->_resume = nand_resume;
3491 mtd->_block_isbad = nand_block_isbad;
3492 mtd->_block_markbad = nand_block_markbad;
cbcab65a 3493 mtd->writebufsize = mtd->writesize;
1da177e4 3494
6a918bad 3495 /* propagate ecc info to mtd_info */
5bd34c09 3496 mtd->ecclayout = chip->ecc.layout;
86c2072b 3497 mtd->ecc_strength = chip->ecc.strength;
ea3b2ea2
SL		 3498 /*
3499 * Initialize bitflip_threshold to its default prior scan_bbt() call.
3500 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3501 * properly set.
3502 */
3503 if (!mtd->bitflip_threshold)
3504 mtd->bitflip_threshold = mtd->ecc_strength;
1da177e4 3505
0040bf38 3506 /* Check, if we should skip the bad block table scan */
ace4dfee 3507 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 3508 return 0;
1da177e4
LT		 3509
3510 /* Build bad block table */
ace4dfee 3511 return chip->scan_bbt(mtd);
1da177e4 3512}
7351d3a5 3513EXPORT_SYMBOL(nand_scan_tail);
1da177e4 3514
8b6e50c9
BN		 3515/*
3516 * is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5 3517 * test if this is a module _anyway_ -- they'd have to try _really_ hard
8b6e50c9
BN		 3518 * to call us from in-kernel code if the core NAND support is modular.
3519 */
3b85c321
DW		 3520#ifdef MODULE
3521#define caller_is_module() (1)
3522#else
3523#define caller_is_module() \
a6e6abd5 3524 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 3525#endif
3526
3527/**
3528 * nand_scan - [NAND Interface] Scan for the NAND device
8b6e50c9
BN		 3529 * @mtd: MTD device structure
3530 * @maxchips: number of chips to scan for
3b85c321 3531 *
8b6e50c9
BN		 3532 * This fills out all the uninitialized function pointers with the defaults.
3533 * The flash ID is read and the mtd/chip structures are filled with the
3534 * appropriate values. The mtd->owner field must be set to the module of the
3535 * caller.
3b85c321
DW		 3536 */
3537int nand_scan(struct mtd_info *mtd, int maxchips)
3538{
3539 int ret;
3540
3541 /* Many callers got this wrong, so check for it for a while... */
3542 if (!mtd->owner && caller_is_module()) {
d0370219 3543 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3b85c321
DW		 3544 BUG();
3545 }
3546
5e81e88a 3547 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 3548 if (!ret)
3549 ret = nand_scan_tail(mtd);
3550 return ret;
3551}
7351d3a5 3552EXPORT_SYMBOL(nand_scan);
3b85c321 3553
1da177e4 3554/**
61b03bd7 3555 * nand_release - [NAND Interface] Free resources held by the NAND device
8b6e50c9
BN		 3556 * @mtd: MTD device structure
3557 */
e0c7d767 3558void nand_release(struct mtd_info *mtd)
1da177e4 3559{
ace4dfee 3560 struct nand_chip *chip = mtd->priv;
1da177e4 3561
193bd400
ID		 3562 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3563 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3564
5ffcaf3d 3565 mtd_device_unregister(mtd);
1da177e4 3566
fa671646 3567 /* Free bad block table memory */
ace4dfee 3568 kfree(chip->bbt);
4bf63fcb
DW		 3569 if (!(chip->options & NAND_OWN_BUFFERS))
3570 kfree(chip->buffers);
58373ff0
BN		 3571
3572 /* Free bad block descriptor memory */
3573 if (chip->badblock_pattern && chip->badblock_pattern->options
3574 & NAND_BBT_DYNAMICSTRUCT)
3575 kfree(chip->badblock_pattern);
1da177e4 3576}
e0c7d767 3577EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 3578
3579static int __init nand_base_init(void)
3580{
3581 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3582 return 0;
3583}
3584
3585static void __exit nand_base_exit(void)
3586{
3587 led_trigger_unregister_simple(nand_led_trigger);
3588}
3589
3590module_init(nand_base_init);
3591module_exit(nand_base_exit);
3592
e0c7d767 3593MODULE_LICENSE("GPL");
7351d3a5
FF		 3594MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3595MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 3596MODULE_DESCRIPTION("Generic NAND flash driver code");
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