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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand.c | |
3 | * | |
4 | * Overview: | |
5 | * This is the generic MTD driver for NAND flash devices. It should be | |
6 | * capable of working with almost all NAND chips currently available. | |
61b03bd7 | 7 | * |
1da177e4 | 8 | * Additional technical information is available on |
8b2b403c | 9 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 10 | * |
1da177e4 | 11 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 12 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 13 | * |
ace4dfee | 14 | * Credits: |
61b03bd7 TG |
15 | * David Woodhouse for adding multichip support |
16 | * | |
1da177e4 LT |
17 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
18 | * rework for 2K page size chips | |
19 | * | |
ace4dfee | 20 | * TODO: |
1da177e4 LT |
21 | * Enable cached programming for 2k page size chips |
22 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
7854d3f7 | 23 | * if we have HW ECC support. |
c0b8ba7b | 24 | * BBT table is not serialized, has to be fixed |
1da177e4 | 25 | * |
1da177e4 LT |
26 | * This program is free software; you can redistribute it and/or modify |
27 | * it under the terms of the GNU General Public License version 2 as | |
28 | * published by the Free Software Foundation. | |
29 | * | |
30 | */ | |
31 | ||
20171642 EG |
32 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
33 | ||
552d9205 | 34 | #include <linux/module.h> |
1da177e4 LT |
35 | #include <linux/delay.h> |
36 | #include <linux/errno.h> | |
7aa65bfd | 37 | #include <linux/err.h> |
1da177e4 LT |
38 | #include <linux/sched.h> |
39 | #include <linux/slab.h> | |
66507c7b | 40 | #include <linux/mm.h> |
1da177e4 LT |
41 | #include <linux/types.h> |
42 | #include <linux/mtd/mtd.h> | |
43 | #include <linux/mtd/nand.h> | |
44 | #include <linux/mtd/nand_ecc.h> | |
193bd400 | 45 | #include <linux/mtd/nand_bch.h> |
1da177e4 LT |
46 | #include <linux/interrupt.h> |
47 | #include <linux/bitops.h> | |
8fe833c1 | 48 | #include <linux/leds.h> |
7351d3a5 | 49 | #include <linux/io.h> |
1da177e4 | 50 | #include <linux/mtd/partitions.h> |
1da177e4 LT |
51 | |
52 | /* Define default oob placement schemes for large and small page devices */ | |
5bd34c09 | 53 | static struct nand_ecclayout nand_oob_8 = { |
1da177e4 LT |
54 | .eccbytes = 3, |
55 | .eccpos = {0, 1, 2}, | |
5bd34c09 TG |
56 | .oobfree = { |
57 | {.offset = 3, | |
58 | .length = 2}, | |
59 | {.offset = 6, | |
f8ac0414 | 60 | .length = 2} } |
1da177e4 LT |
61 | }; |
62 | ||
5bd34c09 | 63 | static struct nand_ecclayout nand_oob_16 = { |
1da177e4 LT |
64 | .eccbytes = 6, |
65 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
5bd34c09 TG |
66 | .oobfree = { |
67 | {.offset = 8, | |
f8ac0414 | 68 | . length = 8} } |
1da177e4 LT |
69 | }; |
70 | ||
5bd34c09 | 71 | static struct nand_ecclayout nand_oob_64 = { |
1da177e4 LT |
72 | .eccbytes = 24, |
73 | .eccpos = { | |
e0c7d767 DW |
74 | 40, 41, 42, 43, 44, 45, 46, 47, |
75 | 48, 49, 50, 51, 52, 53, 54, 55, | |
76 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
5bd34c09 TG |
77 | .oobfree = { |
78 | {.offset = 2, | |
f8ac0414 | 79 | .length = 38} } |
1da177e4 LT |
80 | }; |
81 | ||
81ec5364 TG |
82 | static struct nand_ecclayout nand_oob_128 = { |
83 | .eccbytes = 48, | |
84 | .eccpos = { | |
85 | 80, 81, 82, 83, 84, 85, 86, 87, | |
86 | 88, 89, 90, 91, 92, 93, 94, 95, | |
87 | 96, 97, 98, 99, 100, 101, 102, 103, | |
88 | 104, 105, 106, 107, 108, 109, 110, 111, | |
89 | 112, 113, 114, 115, 116, 117, 118, 119, | |
90 | 120, 121, 122, 123, 124, 125, 126, 127}, | |
91 | .oobfree = { | |
92 | {.offset = 2, | |
f8ac0414 | 93 | .length = 78} } |
81ec5364 TG |
94 | }; |
95 | ||
6a8214aa | 96 | static int nand_get_device(struct mtd_info *mtd, int new_state); |
1da177e4 | 97 | |
8593fbc6 TG |
98 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
99 | struct mtd_oob_ops *ops); | |
100 | ||
d470a97c | 101 | /* |
8e87d782 | 102 | * For devices which display every fart in the system on a separate LED. Is |
d470a97c TG |
103 | * compiled away when LED support is disabled. |
104 | */ | |
105 | DEFINE_LED_TRIGGER(nand_led_trigger); | |
106 | ||
6fe5a6ac VS |
107 | static int check_offs_len(struct mtd_info *mtd, |
108 | loff_t ofs, uint64_t len) | |
109 | { | |
110 | struct nand_chip *chip = mtd->priv; | |
111 | int ret = 0; | |
112 | ||
113 | /* Start address must align on block boundary */ | |
daae74ca | 114 | if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 115 | pr_debug("%s: unaligned address\n", __func__); |
6fe5a6ac VS |
116 | ret = -EINVAL; |
117 | } | |
118 | ||
119 | /* Length must align on block boundary */ | |
daae74ca | 120 | if (len & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 121 | pr_debug("%s: length not block aligned\n", __func__); |
6fe5a6ac VS |
122 | ret = -EINVAL; |
123 | } | |
124 | ||
6fe5a6ac VS |
125 | return ret; |
126 | } | |
127 | ||
1da177e4 LT |
128 | /** |
129 | * nand_release_device - [GENERIC] release chip | |
8b6e50c9 | 130 | * @mtd: MTD device structure |
61b03bd7 | 131 | * |
b0bb6903 | 132 | * Release chip lock and wake up anyone waiting on the device. |
1da177e4 | 133 | */ |
e0c7d767 | 134 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 135 | { |
ace4dfee | 136 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 137 | |
a36ed299 | 138 | /* Release the controller and the chip */ |
ace4dfee TG |
139 | spin_lock(&chip->controller->lock); |
140 | chip->controller->active = NULL; | |
141 | chip->state = FL_READY; | |
142 | wake_up(&chip->controller->wq); | |
143 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
144 | } |
145 | ||
146 | /** | |
147 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
8b6e50c9 | 148 | * @mtd: MTD device structure |
1da177e4 | 149 | * |
7854d3f7 | 150 | * Default read function for 8bit buswidth |
1da177e4 | 151 | */ |
58dd8f2b | 152 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 153 | { |
ace4dfee TG |
154 | struct nand_chip *chip = mtd->priv; |
155 | return readb(chip->IO_ADDR_R); | |
1da177e4 LT |
156 | } |
157 | ||
1da177e4 | 158 | /** |
064a7694 | 159 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
7854d3f7 | 160 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
8b6e50c9 | 161 | * @mtd: MTD device structure |
1da177e4 | 162 | * |
7854d3f7 BN |
163 | * Default read function for 16bit buswidth with endianness conversion. |
164 | * | |
1da177e4 | 165 | */ |
58dd8f2b | 166 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 167 | { |
ace4dfee TG |
168 | struct nand_chip *chip = mtd->priv; |
169 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); | |
1da177e4 LT |
170 | } |
171 | ||
1da177e4 LT |
172 | /** |
173 | * nand_read_word - [DEFAULT] read one word from the chip | |
8b6e50c9 | 174 | * @mtd: MTD device structure |
1da177e4 | 175 | * |
7854d3f7 | 176 | * Default read function for 16bit buswidth without endianness conversion. |
1da177e4 LT |
177 | */ |
178 | static u16 nand_read_word(struct mtd_info *mtd) | |
179 | { | |
ace4dfee TG |
180 | struct nand_chip *chip = mtd->priv; |
181 | return readw(chip->IO_ADDR_R); | |
1da177e4 LT |
182 | } |
183 | ||
1da177e4 LT |
184 | /** |
185 | * nand_select_chip - [DEFAULT] control CE line | |
8b6e50c9 BN |
186 | * @mtd: MTD device structure |
187 | * @chipnr: chipnumber to select, -1 for deselect | |
1da177e4 LT |
188 | * |
189 | * Default select function for 1 chip devices. | |
190 | */ | |
ace4dfee | 191 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 192 | { |
ace4dfee TG |
193 | struct nand_chip *chip = mtd->priv; |
194 | ||
195 | switch (chipnr) { | |
1da177e4 | 196 | case -1: |
ace4dfee | 197 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
198 | break; |
199 | case 0: | |
1da177e4 LT |
200 | break; |
201 | ||
202 | default: | |
203 | BUG(); | |
204 | } | |
205 | } | |
206 | ||
05f78359 UKK |
207 | /** |
208 | * nand_write_byte - [DEFAULT] write single byte to chip | |
209 | * @mtd: MTD device structure | |
210 | * @byte: value to write | |
211 | * | |
212 | * Default function to write a byte to I/O[7:0] | |
213 | */ | |
214 | static void nand_write_byte(struct mtd_info *mtd, uint8_t byte) | |
215 | { | |
216 | struct nand_chip *chip = mtd->priv; | |
217 | ||
218 | chip->write_buf(mtd, &byte, 1); | |
219 | } | |
220 | ||
221 | /** | |
222 | * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16 | |
223 | * @mtd: MTD device structure | |
224 | * @byte: value to write | |
225 | * | |
226 | * Default function to write a byte to I/O[7:0] on a 16-bit wide chip. | |
227 | */ | |
228 | static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) | |
229 | { | |
230 | struct nand_chip *chip = mtd->priv; | |
231 | uint16_t word = byte; | |
232 | ||
233 | /* | |
234 | * It's not entirely clear what should happen to I/O[15:8] when writing | |
235 | * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads: | |
236 | * | |
237 | * When the host supports a 16-bit bus width, only data is | |
238 | * transferred at the 16-bit width. All address and command line | |
239 | * transfers shall use only the lower 8-bits of the data bus. During | |
240 | * command transfers, the host may place any value on the upper | |
241 | * 8-bits of the data bus. During address transfers, the host shall | |
242 | * set the upper 8-bits of the data bus to 00h. | |
243 | * | |
244 | * One user of the write_byte callback is nand_onfi_set_features. The | |
245 | * four parameters are specified to be written to I/O[7:0], but this is | |
246 | * neither an address nor a command transfer. Let's assume a 0 on the | |
247 | * upper I/O lines is OK. | |
248 | */ | |
249 | chip->write_buf(mtd, (uint8_t *)&word, 2); | |
250 | } | |
251 | ||
1da177e4 LT |
252 | /** |
253 | * nand_write_buf - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
254 | * @mtd: MTD device structure |
255 | * @buf: data buffer | |
256 | * @len: number of bytes to write | |
1da177e4 | 257 | * |
7854d3f7 | 258 | * Default write function for 8bit buswidth. |
1da177e4 | 259 | */ |
58dd8f2b | 260 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 261 | { |
ace4dfee | 262 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 263 | |
76413839 | 264 | iowrite8_rep(chip->IO_ADDR_W, buf, len); |
1da177e4 LT |
265 | } |
266 | ||
267 | /** | |
61b03bd7 | 268 | * nand_read_buf - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
269 | * @mtd: MTD device structure |
270 | * @buf: buffer to store date | |
271 | * @len: number of bytes to read | |
1da177e4 | 272 | * |
7854d3f7 | 273 | * Default read function for 8bit buswidth. |
1da177e4 | 274 | */ |
58dd8f2b | 275 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 276 | { |
ace4dfee | 277 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 278 | |
76413839 | 279 | ioread8_rep(chip->IO_ADDR_R, buf, len); |
1da177e4 LT |
280 | } |
281 | ||
1da177e4 LT |
282 | /** |
283 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
284 | * @mtd: MTD device structure |
285 | * @buf: data buffer | |
286 | * @len: number of bytes to write | |
1da177e4 | 287 | * |
7854d3f7 | 288 | * Default write function for 16bit buswidth. |
1da177e4 | 289 | */ |
58dd8f2b | 290 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 291 | { |
ace4dfee | 292 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 293 | u16 *p = (u16 *) buf; |
61b03bd7 | 294 | |
76413839 | 295 | iowrite16_rep(chip->IO_ADDR_W, p, len >> 1); |
1da177e4 LT |
296 | } |
297 | ||
298 | /** | |
61b03bd7 | 299 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
300 | * @mtd: MTD device structure |
301 | * @buf: buffer to store date | |
302 | * @len: number of bytes to read | |
1da177e4 | 303 | * |
7854d3f7 | 304 | * Default read function for 16bit buswidth. |
1da177e4 | 305 | */ |
58dd8f2b | 306 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 307 | { |
ace4dfee | 308 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 309 | u16 *p = (u16 *) buf; |
1da177e4 | 310 | |
76413839 | 311 | ioread16_rep(chip->IO_ADDR_R, p, len >> 1); |
1da177e4 LT |
312 | } |
313 | ||
1da177e4 LT |
314 | /** |
315 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
8b6e50c9 BN |
316 | * @mtd: MTD device structure |
317 | * @ofs: offset from device start | |
318 | * @getchip: 0, if the chip is already selected | |
1da177e4 | 319 | * |
61b03bd7 | 320 | * Check, if the block is bad. |
1da177e4 LT |
321 | */ |
322 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) | |
323 | { | |
cdbec050 | 324 | int page, chipnr, res = 0, i = 0; |
ace4dfee | 325 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
326 | u16 bad; |
327 | ||
5fb1549d | 328 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
329 | ofs += mtd->erasesize - mtd->writesize; |
330 | ||
1a12f46a TK |
331 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
332 | ||
1da177e4 | 333 | if (getchip) { |
ace4dfee | 334 | chipnr = (int)(ofs >> chip->chip_shift); |
1da177e4 | 335 | |
6a8214aa | 336 | nand_get_device(mtd, FL_READING); |
1da177e4 LT |
337 | |
338 | /* Select the NAND device */ | |
ace4dfee | 339 | chip->select_chip(mtd, chipnr); |
1a12f46a | 340 | } |
1da177e4 | 341 | |
cdbec050 BN |
342 | do { |
343 | if (chip->options & NAND_BUSWIDTH_16) { | |
344 | chip->cmdfunc(mtd, NAND_CMD_READOOB, | |
345 | chip->badblockpos & 0xFE, page); | |
346 | bad = cpu_to_le16(chip->read_word(mtd)); | |
347 | if (chip->badblockpos & 0x1) | |
348 | bad >>= 8; | |
349 | else | |
350 | bad &= 0xFF; | |
351 | } else { | |
352 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, | |
353 | page); | |
354 | bad = chip->read_byte(mtd); | |
355 | } | |
356 | ||
357 | if (likely(chip->badblockbits == 8)) | |
358 | res = bad != 0xFF; | |
e0b58d0a | 359 | else |
cdbec050 BN |
360 | res = hweight8(bad) < chip->badblockbits; |
361 | ofs += mtd->writesize; | |
362 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; | |
363 | i++; | |
364 | } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); | |
e0b58d0a | 365 | |
b0bb6903 HS |
366 | if (getchip) { |
367 | chip->select_chip(mtd, -1); | |
1da177e4 | 368 | nand_release_device(mtd); |
b0bb6903 | 369 | } |
61b03bd7 | 370 | |
1da177e4 LT |
371 | return res; |
372 | } | |
373 | ||
374 | /** | |
5a0edb25 | 375 | * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker |
8b6e50c9 BN |
376 | * @mtd: MTD device structure |
377 | * @ofs: offset from device start | |
1da177e4 | 378 | * |
8b6e50c9 | 379 | * This is the default implementation, which can be overridden by a hardware |
5a0edb25 BN |
380 | * specific driver. It provides the details for writing a bad block marker to a |
381 | * block. | |
382 | */ | |
383 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
384 | { | |
385 | struct nand_chip *chip = mtd->priv; | |
386 | struct mtd_oob_ops ops; | |
387 | uint8_t buf[2] = { 0, 0 }; | |
388 | int ret = 0, res, i = 0; | |
389 | ||
390 | ops.datbuf = NULL; | |
391 | ops.oobbuf = buf; | |
392 | ops.ooboffs = chip->badblockpos; | |
393 | if (chip->options & NAND_BUSWIDTH_16) { | |
394 | ops.ooboffs &= ~0x01; | |
395 | ops.len = ops.ooblen = 2; | |
396 | } else { | |
397 | ops.len = ops.ooblen = 1; | |
398 | } | |
399 | ops.mode = MTD_OPS_PLACE_OOB; | |
400 | ||
401 | /* Write to first/last page(s) if necessary */ | |
402 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) | |
403 | ofs += mtd->erasesize - mtd->writesize; | |
404 | do { | |
405 | res = nand_do_write_oob(mtd, ofs, &ops); | |
406 | if (!ret) | |
407 | ret = res; | |
408 | ||
409 | i++; | |
410 | ofs += mtd->writesize; | |
411 | } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); | |
412 | ||
413 | return ret; | |
414 | } | |
415 | ||
416 | /** | |
417 | * nand_block_markbad_lowlevel - mark a block bad | |
418 | * @mtd: MTD device structure | |
419 | * @ofs: offset from device start | |
420 | * | |
421 | * This function performs the generic NAND bad block marking steps (i.e., bad | |
422 | * block table(s) and/or marker(s)). We only allow the hardware driver to | |
423 | * specify how to write bad block markers to OOB (chip->block_markbad). | |
424 | * | |
b32843b7 | 425 | * We try operations in the following order: |
e2414f4c | 426 | * (1) erase the affected block, to allow OOB marker to be written cleanly |
b32843b7 BN |
427 | * (2) write bad block marker to OOB area of affected block (unless flag |
428 | * NAND_BBT_NO_OOB_BBM is present) | |
429 | * (3) update the BBT | |
430 | * Note that we retain the first error encountered in (2) or (3), finish the | |
e2414f4c | 431 | * procedures, and dump the error in the end. |
1da177e4 | 432 | */ |
5a0edb25 | 433 | static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 434 | { |
ace4dfee | 435 | struct nand_chip *chip = mtd->priv; |
b32843b7 | 436 | int res, ret = 0; |
61b03bd7 | 437 | |
b32843b7 | 438 | if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { |
00918429 BN |
439 | struct erase_info einfo; |
440 | ||
441 | /* Attempt erase before marking OOB */ | |
442 | memset(&einfo, 0, sizeof(einfo)); | |
443 | einfo.mtd = mtd; | |
444 | einfo.addr = ofs; | |
daae74ca | 445 | einfo.len = 1ULL << chip->phys_erase_shift; |
00918429 | 446 | nand_erase_nand(mtd, &einfo, 0); |
1da177e4 | 447 | |
b32843b7 | 448 | /* Write bad block marker to OOB */ |
6a8214aa | 449 | nand_get_device(mtd, FL_WRITING); |
5a0edb25 | 450 | ret = chip->block_markbad(mtd, ofs); |
c0b8ba7b | 451 | nand_release_device(mtd); |
f1a28c02 | 452 | } |
e2414f4c | 453 | |
b32843b7 BN |
454 | /* Mark block bad in BBT */ |
455 | if (chip->bbt) { | |
456 | res = nand_markbad_bbt(mtd, ofs); | |
e2414f4c BN |
457 | if (!ret) |
458 | ret = res; | |
459 | } | |
460 | ||
f1a28c02 TG |
461 | if (!ret) |
462 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 463 | |
f1a28c02 | 464 | return ret; |
1da177e4 LT |
465 | } |
466 | ||
61b03bd7 | 467 | /** |
1da177e4 | 468 | * nand_check_wp - [GENERIC] check if the chip is write protected |
8b6e50c9 | 469 | * @mtd: MTD device structure |
1da177e4 | 470 | * |
8b6e50c9 BN |
471 | * Check, if the device is write protected. The function expects, that the |
472 | * device is already selected. | |
1da177e4 | 473 | */ |
e0c7d767 | 474 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 475 | { |
ace4dfee | 476 | struct nand_chip *chip = mtd->priv; |
93edbad6 | 477 | |
8b6e50c9 | 478 | /* Broken xD cards report WP despite being writable */ |
93edbad6 ML |
479 | if (chip->options & NAND_BROKEN_XD) |
480 | return 0; | |
481 | ||
1da177e4 | 482 | /* Check the WP bit */ |
ace4dfee TG |
483 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
484 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
485 | } |
486 | ||
8471bb73 EG |
487 | /** |
488 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
489 | * @mtd: MTD device structure | |
490 | * @ofs: offset from device start | |
491 | * | |
492 | * Check if the block is mark as reserved. | |
493 | */ | |
494 | static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) | |
495 | { | |
496 | struct nand_chip *chip = mtd->priv; | |
497 | ||
498 | if (!chip->bbt) | |
499 | return 0; | |
500 | /* Return info from the table */ | |
501 | return nand_isreserved_bbt(mtd, ofs); | |
502 | } | |
503 | ||
1da177e4 LT |
504 | /** |
505 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
8b6e50c9 BN |
506 | * @mtd: MTD device structure |
507 | * @ofs: offset from device start | |
508 | * @getchip: 0, if the chip is already selected | |
509 | * @allowbbt: 1, if its allowed to access the bbt area | |
1da177e4 LT |
510 | * |
511 | * Check, if the block is bad. Either by reading the bad block table or | |
512 | * calling of the scan function. | |
513 | */ | |
2c0a2bed TG |
514 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, |
515 | int allowbbt) | |
1da177e4 | 516 | { |
ace4dfee | 517 | struct nand_chip *chip = mtd->priv; |
61b03bd7 | 518 | |
ace4dfee TG |
519 | if (!chip->bbt) |
520 | return chip->block_bad(mtd, ofs, getchip); | |
61b03bd7 | 521 | |
1da177e4 | 522 | /* Return info from the table */ |
e0c7d767 | 523 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
524 | } |
525 | ||
2af7c653 SK |
526 | /** |
527 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
8b6e50c9 BN |
528 | * @mtd: MTD device structure |
529 | * @timeo: Timeout | |
2af7c653 SK |
530 | * |
531 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
532 | * context. | |
533 | */ | |
534 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
535 | { | |
536 | struct nand_chip *chip = mtd->priv; | |
537 | int i; | |
538 | ||
539 | /* Wait for the device to get ready */ | |
540 | for (i = 0; i < timeo; i++) { | |
541 | if (chip->dev_ready(mtd)) | |
542 | break; | |
543 | touch_softlockup_watchdog(); | |
544 | mdelay(1); | |
545 | } | |
546 | } | |
547 | ||
7854d3f7 | 548 | /* Wait for the ready pin, after a command. The timeout is caught later. */ |
4b648b02 | 549 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 550 | { |
ace4dfee | 551 | struct nand_chip *chip = mtd->priv; |
ca6a2489 | 552 | unsigned long timeo = jiffies + msecs_to_jiffies(20); |
3b88775c | 553 | |
2af7c653 SK |
554 | /* 400ms timeout */ |
555 | if (in_interrupt() || oops_in_progress) | |
556 | return panic_nand_wait_ready(mtd, 400); | |
557 | ||
8fe833c1 | 558 | led_trigger_event(nand_led_trigger, LED_FULL); |
7854d3f7 | 559 | /* Wait until command is processed or timeout occurs */ |
3b88775c | 560 | do { |
ace4dfee | 561 | if (chip->dev_ready(mtd)) |
8fe833c1 | 562 | break; |
8446f1d3 | 563 | touch_softlockup_watchdog(); |
61b03bd7 | 564 | } while (time_before(jiffies, timeo)); |
8fe833c1 | 565 | led_trigger_event(nand_led_trigger, LED_OFF); |
3b88775c | 566 | } |
4b648b02 | 567 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 568 | |
1da177e4 LT |
569 | /** |
570 | * nand_command - [DEFAULT] Send command to NAND device | |
8b6e50c9 BN |
571 | * @mtd: MTD device structure |
572 | * @command: the command to be sent | |
573 | * @column: the column address for this command, -1 if none | |
574 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 575 | * |
8b6e50c9 | 576 | * Send command to NAND device. This function is used for small page devices |
51148f1f | 577 | * (512 Bytes per page). |
1da177e4 | 578 | */ |
7abd3ef9 TG |
579 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
580 | int column, int page_addr) | |
1da177e4 | 581 | { |
ace4dfee | 582 | register struct nand_chip *chip = mtd->priv; |
7abd3ef9 | 583 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 584 | |
8b6e50c9 | 585 | /* Write out the command to the device */ |
1da177e4 LT |
586 | if (command == NAND_CMD_SEQIN) { |
587 | int readcmd; | |
588 | ||
28318776 | 589 | if (column >= mtd->writesize) { |
1da177e4 | 590 | /* OOB area */ |
28318776 | 591 | column -= mtd->writesize; |
1da177e4 LT |
592 | readcmd = NAND_CMD_READOOB; |
593 | } else if (column < 256) { | |
594 | /* First 256 bytes --> READ0 */ | |
595 | readcmd = NAND_CMD_READ0; | |
596 | } else { | |
597 | column -= 256; | |
598 | readcmd = NAND_CMD_READ1; | |
599 | } | |
ace4dfee | 600 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 601 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 602 | } |
ace4dfee | 603 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 604 | |
8b6e50c9 | 605 | /* Address cycle, when necessary */ |
7abd3ef9 TG |
606 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; |
607 | /* Serially input address */ | |
608 | if (column != -1) { | |
609 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
610 | if (chip->options & NAND_BUSWIDTH_16 && |
611 | !nand_opcode_8bits(command)) | |
7abd3ef9 | 612 | column >>= 1; |
ace4dfee | 613 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
614 | ctrl &= ~NAND_CTRL_CHANGE; |
615 | } | |
616 | if (page_addr != -1) { | |
ace4dfee | 617 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 618 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 619 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 620 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
621 | if (chip->chipsize > (32 << 20)) |
622 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 623 | } |
ace4dfee | 624 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
625 | |
626 | /* | |
8b6e50c9 BN |
627 | * Program and erase have their own busy handlers status and sequential |
628 | * in needs no delay | |
e0c7d767 | 629 | */ |
1da177e4 | 630 | switch (command) { |
61b03bd7 | 631 | |
1da177e4 LT |
632 | case NAND_CMD_PAGEPROG: |
633 | case NAND_CMD_ERASE1: | |
634 | case NAND_CMD_ERASE2: | |
635 | case NAND_CMD_SEQIN: | |
636 | case NAND_CMD_STATUS: | |
637 | return; | |
638 | ||
639 | case NAND_CMD_RESET: | |
ace4dfee | 640 | if (chip->dev_ready) |
1da177e4 | 641 | break; |
ace4dfee TG |
642 | udelay(chip->chip_delay); |
643 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 644 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
645 | chip->cmd_ctrl(mtd, |
646 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
647 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
648 | ; | |
1da177e4 LT |
649 | return; |
650 | ||
e0c7d767 | 651 | /* This applies to read commands */ |
1da177e4 | 652 | default: |
61b03bd7 | 653 | /* |
1da177e4 LT |
654 | * If we don't have access to the busy pin, we apply the given |
655 | * command delay | |
e0c7d767 | 656 | */ |
ace4dfee TG |
657 | if (!chip->dev_ready) { |
658 | udelay(chip->chip_delay); | |
1da177e4 | 659 | return; |
61b03bd7 | 660 | } |
1da177e4 | 661 | } |
8b6e50c9 BN |
662 | /* |
663 | * Apply this short delay always to ensure that we do wait tWB in | |
664 | * any case on any machine. | |
665 | */ | |
e0c7d767 | 666 | ndelay(100); |
3b88775c TG |
667 | |
668 | nand_wait_ready(mtd); | |
1da177e4 LT |
669 | } |
670 | ||
671 | /** | |
672 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
8b6e50c9 BN |
673 | * @mtd: MTD device structure |
674 | * @command: the command to be sent | |
675 | * @column: the column address for this command, -1 if none | |
676 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 677 | * |
7abd3ef9 | 678 | * Send command to NAND device. This is the version for the new large page |
7854d3f7 BN |
679 | * devices. We don't have the separate regions as we have in the small page |
680 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 681 | */ |
7abd3ef9 TG |
682 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
683 | int column, int page_addr) | |
1da177e4 | 684 | { |
ace4dfee | 685 | register struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
686 | |
687 | /* Emulate NAND_CMD_READOOB */ | |
688 | if (command == NAND_CMD_READOOB) { | |
28318776 | 689 | column += mtd->writesize; |
1da177e4 LT |
690 | command = NAND_CMD_READ0; |
691 | } | |
61b03bd7 | 692 | |
7abd3ef9 | 693 | /* Command latch cycle */ |
fb066ada | 694 | chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
695 | |
696 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 697 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
698 | |
699 | /* Serially input address */ | |
700 | if (column != -1) { | |
701 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
702 | if (chip->options & NAND_BUSWIDTH_16 && |
703 | !nand_opcode_8bits(command)) | |
1da177e4 | 704 | column >>= 1; |
ace4dfee | 705 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 706 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 707 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 708 | } |
1da177e4 | 709 | if (page_addr != -1) { |
ace4dfee TG |
710 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
711 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 712 | NAND_NCE | NAND_ALE); |
1da177e4 | 713 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
714 | if (chip->chipsize > (128 << 20)) |
715 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 716 | NAND_NCE | NAND_ALE); |
1da177e4 | 717 | } |
1da177e4 | 718 | } |
ace4dfee | 719 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
720 | |
721 | /* | |
8b6e50c9 BN |
722 | * Program and erase have their own busy handlers status, sequential |
723 | * in, and deplete1 need no delay. | |
30f464b7 | 724 | */ |
1da177e4 | 725 | switch (command) { |
61b03bd7 | 726 | |
1da177e4 LT |
727 | case NAND_CMD_CACHEDPROG: |
728 | case NAND_CMD_PAGEPROG: | |
729 | case NAND_CMD_ERASE1: | |
730 | case NAND_CMD_ERASE2: | |
731 | case NAND_CMD_SEQIN: | |
7bc3312b | 732 | case NAND_CMD_RNDIN: |
1da177e4 | 733 | case NAND_CMD_STATUS: |
30f464b7 | 734 | return; |
1da177e4 LT |
735 | |
736 | case NAND_CMD_RESET: | |
ace4dfee | 737 | if (chip->dev_ready) |
1da177e4 | 738 | break; |
ace4dfee | 739 | udelay(chip->chip_delay); |
12efdde3 TG |
740 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
741 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
742 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
743 | NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
744 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
745 | ; | |
1da177e4 LT |
746 | return; |
747 | ||
7bc3312b TG |
748 | case NAND_CMD_RNDOUT: |
749 | /* No ready / busy check necessary */ | |
750 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
751 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
752 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
753 | NAND_NCE | NAND_CTRL_CHANGE); | |
754 | return; | |
755 | ||
1da177e4 | 756 | case NAND_CMD_READ0: |
12efdde3 TG |
757 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
758 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
759 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
760 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 761 | |
e0c7d767 | 762 | /* This applies to read commands */ |
1da177e4 | 763 | default: |
61b03bd7 | 764 | /* |
1da177e4 | 765 | * If we don't have access to the busy pin, we apply the given |
8b6e50c9 | 766 | * command delay. |
e0c7d767 | 767 | */ |
ace4dfee TG |
768 | if (!chip->dev_ready) { |
769 | udelay(chip->chip_delay); | |
1da177e4 | 770 | return; |
61b03bd7 | 771 | } |
1da177e4 | 772 | } |
3b88775c | 773 | |
8b6e50c9 BN |
774 | /* |
775 | * Apply this short delay always to ensure that we do wait tWB in | |
776 | * any case on any machine. | |
777 | */ | |
e0c7d767 | 778 | ndelay(100); |
3b88775c TG |
779 | |
780 | nand_wait_ready(mtd); | |
1da177e4 LT |
781 | } |
782 | ||
2af7c653 SK |
783 | /** |
784 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
785 | * @chip: the nand chip descriptor |
786 | * @mtd: MTD device structure | |
787 | * @new_state: the state which is requested | |
2af7c653 SK |
788 | * |
789 | * Used when in panic, no locks are taken. | |
790 | */ | |
791 | static void panic_nand_get_device(struct nand_chip *chip, | |
792 | struct mtd_info *mtd, int new_state) | |
793 | { | |
7854d3f7 | 794 | /* Hardware controller shared among independent devices */ |
2af7c653 SK |
795 | chip->controller->active = chip; |
796 | chip->state = new_state; | |
797 | } | |
798 | ||
1da177e4 LT |
799 | /** |
800 | * nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
801 | * @mtd: MTD device structure |
802 | * @new_state: the state which is requested | |
1da177e4 LT |
803 | * |
804 | * Get the device and lock it for exclusive access | |
805 | */ | |
2c0a2bed | 806 | static int |
6a8214aa | 807 | nand_get_device(struct mtd_info *mtd, int new_state) |
1da177e4 | 808 | { |
6a8214aa | 809 | struct nand_chip *chip = mtd->priv; |
ace4dfee TG |
810 | spinlock_t *lock = &chip->controller->lock; |
811 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 812 | DECLARE_WAITQUEUE(wait, current); |
7351d3a5 | 813 | retry: |
0dfc6246 TG |
814 | spin_lock(lock); |
815 | ||
b8b3ee9a | 816 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
817 | if (!chip->controller->active) |
818 | chip->controller->active = chip; | |
a36ed299 | 819 | |
ace4dfee TG |
820 | if (chip->controller->active == chip && chip->state == FL_READY) { |
821 | chip->state = new_state; | |
0dfc6246 | 822 | spin_unlock(lock); |
962034f4 VW |
823 | return 0; |
824 | } | |
825 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
826 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
827 | chip->state = FL_PM_SUSPENDED; | |
828 | spin_unlock(lock); | |
829 | return 0; | |
6b0d9a84 | 830 | } |
0dfc6246 TG |
831 | } |
832 | set_current_state(TASK_UNINTERRUPTIBLE); | |
833 | add_wait_queue(wq, &wait); | |
834 | spin_unlock(lock); | |
835 | schedule(); | |
836 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
837 | goto retry; |
838 | } | |
839 | ||
2af7c653 | 840 | /** |
8b6e50c9 BN |
841 | * panic_nand_wait - [GENERIC] wait until the command is done |
842 | * @mtd: MTD device structure | |
843 | * @chip: NAND chip structure | |
844 | * @timeo: timeout | |
2af7c653 SK |
845 | * |
846 | * Wait for command done. This is a helper function for nand_wait used when | |
847 | * we are in interrupt context. May happen when in panic and trying to write | |
b595076a | 848 | * an oops through mtdoops. |
2af7c653 SK |
849 | */ |
850 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
851 | unsigned long timeo) | |
852 | { | |
853 | int i; | |
854 | for (i = 0; i < timeo; i++) { | |
855 | if (chip->dev_ready) { | |
856 | if (chip->dev_ready(mtd)) | |
857 | break; | |
858 | } else { | |
859 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
860 | break; | |
861 | } | |
862 | mdelay(1); | |
f8ac0414 | 863 | } |
2af7c653 SK |
864 | } |
865 | ||
1da177e4 | 866 | /** |
8b6e50c9 BN |
867 | * nand_wait - [DEFAULT] wait until the command is done |
868 | * @mtd: MTD device structure | |
869 | * @chip: NAND chip structure | |
1da177e4 | 870 | * |
8b6e50c9 BN |
871 | * Wait for command done. This applies to erase and program only. Erase can |
872 | * take up to 400ms and program up to 20ms according to general NAND and | |
873 | * SmartMedia specs. | |
844d3b42 | 874 | */ |
7bc3312b | 875 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
876 | { |
877 | ||
7bc3312b | 878 | int status, state = chip->state; |
6d2559f8 | 879 | unsigned long timeo = (state == FL_ERASING ? 400 : 20); |
1da177e4 | 880 | |
8fe833c1 RP |
881 | led_trigger_event(nand_led_trigger, LED_FULL); |
882 | ||
8b6e50c9 BN |
883 | /* |
884 | * Apply this short delay always to ensure that we do wait tWB in any | |
885 | * case on any machine. | |
886 | */ | |
e0c7d767 | 887 | ndelay(100); |
1da177e4 | 888 | |
14c65786 | 889 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 890 | |
2af7c653 SK |
891 | if (in_interrupt() || oops_in_progress) |
892 | panic_nand_wait(mtd, chip, timeo); | |
893 | else { | |
6d2559f8 | 894 | timeo = jiffies + msecs_to_jiffies(timeo); |
2af7c653 SK |
895 | while (time_before(jiffies, timeo)) { |
896 | if (chip->dev_ready) { | |
897 | if (chip->dev_ready(mtd)) | |
898 | break; | |
899 | } else { | |
900 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
901 | break; | |
902 | } | |
903 | cond_resched(); | |
1da177e4 | 904 | } |
1da177e4 | 905 | } |
8fe833c1 RP |
906 | led_trigger_event(nand_led_trigger, LED_OFF); |
907 | ||
ace4dfee | 908 | status = (int)chip->read_byte(mtd); |
f251b8df MC |
909 | /* This can happen if in case of timeout or buggy dev_ready */ |
910 | WARN_ON(!(status & NAND_STATUS_READY)); | |
1da177e4 LT |
911 | return status; |
912 | } | |
913 | ||
7d70f334 | 914 | /** |
b6d676db | 915 | * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
916 | * @mtd: mtd info |
917 | * @ofs: offset to start unlock from | |
918 | * @len: length to unlock | |
8b6e50c9 BN |
919 | * @invert: when = 0, unlock the range of blocks within the lower and |
920 | * upper boundary address | |
921 | * when = 1, unlock the range of blocks outside the boundaries | |
922 | * of the lower and upper boundary address | |
7d70f334 | 923 | * |
8b6e50c9 | 924 | * Returs unlock status. |
7d70f334 VS |
925 | */ |
926 | static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, | |
927 | uint64_t len, int invert) | |
928 | { | |
929 | int ret = 0; | |
930 | int status, page; | |
931 | struct nand_chip *chip = mtd->priv; | |
932 | ||
933 | /* Submit address of first page to unlock */ | |
934 | page = ofs >> chip->page_shift; | |
935 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); | |
936 | ||
937 | /* Submit address of last page to unlock */ | |
938 | page = (ofs + len) >> chip->page_shift; | |
939 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, | |
940 | (page | invert) & chip->pagemask); | |
941 | ||
942 | /* Call wait ready function */ | |
943 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 944 | /* See if device thinks it succeeded */ |
74830966 | 945 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 946 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
947 | __func__, status); |
948 | ret = -EIO; | |
949 | } | |
950 | ||
951 | return ret; | |
952 | } | |
953 | ||
954 | /** | |
b6d676db | 955 | * nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
956 | * @mtd: mtd info |
957 | * @ofs: offset to start unlock from | |
958 | * @len: length to unlock | |
7d70f334 | 959 | * |
8b6e50c9 | 960 | * Returns unlock status. |
7d70f334 VS |
961 | */ |
962 | int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
963 | { | |
964 | int ret = 0; | |
965 | int chipnr; | |
966 | struct nand_chip *chip = mtd->priv; | |
967 | ||
289c0522 | 968 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
969 | __func__, (unsigned long long)ofs, len); |
970 | ||
971 | if (check_offs_len(mtd, ofs, len)) | |
972 | ret = -EINVAL; | |
973 | ||
974 | /* Align to last block address if size addresses end of the device */ | |
975 | if (ofs + len == mtd->size) | |
976 | len -= mtd->erasesize; | |
977 | ||
6a8214aa | 978 | nand_get_device(mtd, FL_UNLOCKING); |
7d70f334 VS |
979 | |
980 | /* Shift to get chip number */ | |
981 | chipnr = ofs >> chip->chip_shift; | |
982 | ||
983 | chip->select_chip(mtd, chipnr); | |
984 | ||
985 | /* Check, if it is write protected */ | |
986 | if (nand_check_wp(mtd)) { | |
289c0522 | 987 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
988 | __func__); |
989 | ret = -EIO; | |
990 | goto out; | |
991 | } | |
992 | ||
993 | ret = __nand_unlock(mtd, ofs, len, 0); | |
994 | ||
995 | out: | |
b0bb6903 | 996 | chip->select_chip(mtd, -1); |
7d70f334 VS |
997 | nand_release_device(mtd); |
998 | ||
999 | return ret; | |
1000 | } | |
7351d3a5 | 1001 | EXPORT_SYMBOL(nand_unlock); |
7d70f334 VS |
1002 | |
1003 | /** | |
b6d676db | 1004 | * nand_lock - [REPLACEABLE] locks all blocks present in the device |
b6d676db RD |
1005 | * @mtd: mtd info |
1006 | * @ofs: offset to start unlock from | |
1007 | * @len: length to unlock | |
7d70f334 | 1008 | * |
8b6e50c9 BN |
1009 | * This feature is not supported in many NAND parts. 'Micron' NAND parts do |
1010 | * have this feature, but it allows only to lock all blocks, not for specified | |
1011 | * range for block. Implementing 'lock' feature by making use of 'unlock', for | |
1012 | * now. | |
7d70f334 | 1013 | * |
8b6e50c9 | 1014 | * Returns lock status. |
7d70f334 VS |
1015 | */ |
1016 | int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
1017 | { | |
1018 | int ret = 0; | |
1019 | int chipnr, status, page; | |
1020 | struct nand_chip *chip = mtd->priv; | |
1021 | ||
289c0522 | 1022 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
1023 | __func__, (unsigned long long)ofs, len); |
1024 | ||
1025 | if (check_offs_len(mtd, ofs, len)) | |
1026 | ret = -EINVAL; | |
1027 | ||
6a8214aa | 1028 | nand_get_device(mtd, FL_LOCKING); |
7d70f334 VS |
1029 | |
1030 | /* Shift to get chip number */ | |
1031 | chipnr = ofs >> chip->chip_shift; | |
1032 | ||
1033 | chip->select_chip(mtd, chipnr); | |
1034 | ||
1035 | /* Check, if it is write protected */ | |
1036 | if (nand_check_wp(mtd)) { | |
289c0522 | 1037 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
1038 | __func__); |
1039 | status = MTD_ERASE_FAILED; | |
1040 | ret = -EIO; | |
1041 | goto out; | |
1042 | } | |
1043 | ||
1044 | /* Submit address of first page to lock */ | |
1045 | page = ofs >> chip->page_shift; | |
1046 | chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); | |
1047 | ||
1048 | /* Call wait ready function */ | |
1049 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 1050 | /* See if device thinks it succeeded */ |
74830966 | 1051 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 1052 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
1053 | __func__, status); |
1054 | ret = -EIO; | |
1055 | goto out; | |
1056 | } | |
1057 | ||
1058 | ret = __nand_unlock(mtd, ofs, len, 0x1); | |
1059 | ||
1060 | out: | |
b0bb6903 | 1061 | chip->select_chip(mtd, -1); |
7d70f334 VS |
1062 | nand_release_device(mtd); |
1063 | ||
1064 | return ret; | |
1065 | } | |
7351d3a5 | 1066 | EXPORT_SYMBOL(nand_lock); |
7d70f334 | 1067 | |
8593fbc6 | 1068 | /** |
7854d3f7 | 1069 | * nand_read_page_raw - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1070 | * @mtd: mtd info structure |
1071 | * @chip: nand chip info structure | |
1072 | * @buf: buffer to store read data | |
1fbb938d | 1073 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1074 | * @page: page number to read |
52ff49df | 1075 | * |
7854d3f7 | 1076 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 TG |
1077 | */ |
1078 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1079 | uint8_t *buf, int oob_required, int page) |
8593fbc6 TG |
1080 | { |
1081 | chip->read_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
1082 | if (oob_required) |
1083 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
8593fbc6 TG |
1084 | return 0; |
1085 | } | |
1086 | ||
52ff49df | 1087 | /** |
7854d3f7 | 1088 | * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1089 | * @mtd: mtd info structure |
1090 | * @chip: nand chip info structure | |
1091 | * @buf: buffer to store read data | |
1fbb938d | 1092 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1093 | * @page: page number to read |
52ff49df DB |
1094 | * |
1095 | * We need a special oob layout and handling even when OOB isn't used. | |
1096 | */ | |
7351d3a5 | 1097 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
1098 | struct nand_chip *chip, uint8_t *buf, |
1099 | int oob_required, int page) | |
52ff49df DB |
1100 | { |
1101 | int eccsize = chip->ecc.size; | |
1102 | int eccbytes = chip->ecc.bytes; | |
1103 | uint8_t *oob = chip->oob_poi; | |
1104 | int steps, size; | |
1105 | ||
1106 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1107 | chip->read_buf(mtd, buf, eccsize); | |
1108 | buf += eccsize; | |
1109 | ||
1110 | if (chip->ecc.prepad) { | |
1111 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1112 | oob += chip->ecc.prepad; | |
1113 | } | |
1114 | ||
1115 | chip->read_buf(mtd, oob, eccbytes); | |
1116 | oob += eccbytes; | |
1117 | ||
1118 | if (chip->ecc.postpad) { | |
1119 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1120 | oob += chip->ecc.postpad; | |
1121 | } | |
1122 | } | |
1123 | ||
1124 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1125 | if (size) | |
1126 | chip->read_buf(mtd, oob, size); | |
1127 | ||
1128 | return 0; | |
1129 | } | |
1130 | ||
1da177e4 | 1131 | /** |
7854d3f7 | 1132 | * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function |
8b6e50c9 BN |
1133 | * @mtd: mtd info structure |
1134 | * @chip: nand chip info structure | |
1135 | * @buf: buffer to store read data | |
1fbb938d | 1136 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1137 | * @page: page number to read |
068e3c0a | 1138 | */ |
f5bbdacc | 1139 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1140 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1141 | { |
f5bbdacc TG |
1142 | int i, eccsize = chip->ecc.size; |
1143 | int eccbytes = chip->ecc.bytes; | |
1144 | int eccsteps = chip->ecc.steps; | |
1145 | uint8_t *p = buf; | |
4bf63fcb DW |
1146 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1147 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1148 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1149 | unsigned int max_bitflips = 0; |
f5bbdacc | 1150 | |
1fbb938d | 1151 | chip->ecc.read_page_raw(mtd, chip, buf, 1, page); |
f5bbdacc TG |
1152 | |
1153 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1154 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1155 | ||
1156 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 1157 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
1158 | |
1159 | eccsteps = chip->ecc.steps; | |
1160 | p = buf; | |
1161 | ||
1162 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1163 | int stat; | |
1164 | ||
1165 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
3f91e94f | 1166 | if (stat < 0) { |
f5bbdacc | 1167 | mtd->ecc_stats.failed++; |
3f91e94f | 1168 | } else { |
f5bbdacc | 1169 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1170 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1171 | } | |
f5bbdacc | 1172 | } |
3f91e94f | 1173 | return max_bitflips; |
22c60f5f | 1174 | } |
1da177e4 | 1175 | |
3d459559 | 1176 | /** |
837a6ba4 | 1177 | * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function |
8b6e50c9 BN |
1178 | * @mtd: mtd info structure |
1179 | * @chip: nand chip info structure | |
1180 | * @data_offs: offset of requested data within the page | |
1181 | * @readlen: data length | |
1182 | * @bufpoi: buffer to store read data | |
e004debd | 1183 | * @page: page number to read |
3d459559 | 1184 | */ |
7351d3a5 | 1185 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, |
e004debd HS |
1186 | uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi, |
1187 | int page) | |
3d459559 AK |
1188 | { |
1189 | int start_step, end_step, num_steps; | |
1190 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1191 | uint8_t *p; | |
1192 | int data_col_addr, i, gaps = 0; | |
1193 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
1194 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
4a4163ca | 1195 | int index; |
3f91e94f | 1196 | unsigned int max_bitflips = 0; |
3d459559 | 1197 | |
7854d3f7 | 1198 | /* Column address within the page aligned to ECC size (256bytes) */ |
3d459559 AK |
1199 | start_step = data_offs / chip->ecc.size; |
1200 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
1201 | num_steps = end_step - start_step + 1; | |
4a4163ca | 1202 | index = start_step * chip->ecc.bytes; |
3d459559 | 1203 | |
8b6e50c9 | 1204 | /* Data size aligned to ECC ecc.size */ |
3d459559 AK |
1205 | datafrag_len = num_steps * chip->ecc.size; |
1206 | eccfrag_len = num_steps * chip->ecc.bytes; | |
1207 | ||
1208 | data_col_addr = start_step * chip->ecc.size; | |
1209 | /* If we read not a page aligned data */ | |
1210 | if (data_col_addr != 0) | |
1211 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); | |
1212 | ||
1213 | p = bufpoi + data_col_addr; | |
1214 | chip->read_buf(mtd, p, datafrag_len); | |
1215 | ||
8b6e50c9 | 1216 | /* Calculate ECC */ |
3d459559 AK |
1217 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) |
1218 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); | |
1219 | ||
8b6e50c9 BN |
1220 | /* |
1221 | * The performance is faster if we position offsets according to | |
7854d3f7 | 1222 | * ecc.pos. Let's make sure that there are no gaps in ECC positions. |
8b6e50c9 | 1223 | */ |
3d459559 | 1224 | for (i = 0; i < eccfrag_len - 1; i++) { |
47570bb1 | 1225 | if (eccpos[i + index] + 1 != eccpos[i + index + 1]) { |
3d459559 AK |
1226 | gaps = 1; |
1227 | break; | |
1228 | } | |
1229 | } | |
1230 | if (gaps) { | |
1231 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1232 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1233 | } else { | |
8b6e50c9 | 1234 | /* |
7854d3f7 | 1235 | * Send the command to read the particular ECC bytes take care |
8b6e50c9 BN |
1236 | * about buswidth alignment in read_buf. |
1237 | */ | |
7351d3a5 | 1238 | aligned_pos = eccpos[index] & ~(busw - 1); |
3d459559 | 1239 | aligned_len = eccfrag_len; |
7351d3a5 | 1240 | if (eccpos[index] & (busw - 1)) |
3d459559 | 1241 | aligned_len++; |
7351d3a5 | 1242 | if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1)) |
3d459559 AK |
1243 | aligned_len++; |
1244 | ||
7351d3a5 FF |
1245 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, |
1246 | mtd->writesize + aligned_pos, -1); | |
3d459559 AK |
1247 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); |
1248 | } | |
1249 | ||
1250 | for (i = 0; i < eccfrag_len; i++) | |
7351d3a5 | 1251 | chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]]; |
3d459559 AK |
1252 | |
1253 | p = bufpoi + data_col_addr; | |
1254 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
1255 | int stat; | |
1256 | ||
7351d3a5 FF |
1257 | stat = chip->ecc.correct(mtd, p, |
1258 | &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); | |
3f91e94f | 1259 | if (stat < 0) { |
3d459559 | 1260 | mtd->ecc_stats.failed++; |
3f91e94f | 1261 | } else { |
3d459559 | 1262 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1263 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1264 | } | |
3d459559 | 1265 | } |
3f91e94f | 1266 | return max_bitflips; |
3d459559 AK |
1267 | } |
1268 | ||
068e3c0a | 1269 | /** |
7854d3f7 | 1270 | * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function |
8b6e50c9 BN |
1271 | * @mtd: mtd info structure |
1272 | * @chip: nand chip info structure | |
1273 | * @buf: buffer to store read data | |
1fbb938d | 1274 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1275 | * @page: page number to read |
068e3c0a | 1276 | * |
7854d3f7 | 1277 | * Not for syndrome calculating ECC controllers which need a special oob layout. |
068e3c0a | 1278 | */ |
f5bbdacc | 1279 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1280 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1281 | { |
f5bbdacc TG |
1282 | int i, eccsize = chip->ecc.size; |
1283 | int eccbytes = chip->ecc.bytes; | |
1284 | int eccsteps = chip->ecc.steps; | |
1285 | uint8_t *p = buf; | |
4bf63fcb DW |
1286 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1287 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1288 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1289 | unsigned int max_bitflips = 0; |
f5bbdacc TG |
1290 | |
1291 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1292 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1293 | chip->read_buf(mtd, p, eccsize); | |
1294 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 1295 | } |
f75e5097 | 1296 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 1297 | |
f5bbdacc | 1298 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 1299 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 1300 | |
f5bbdacc TG |
1301 | eccsteps = chip->ecc.steps; |
1302 | p = buf; | |
61b03bd7 | 1303 | |
f5bbdacc TG |
1304 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1305 | int stat; | |
1da177e4 | 1306 | |
f5bbdacc | 1307 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
3f91e94f | 1308 | if (stat < 0) { |
f5bbdacc | 1309 | mtd->ecc_stats.failed++; |
3f91e94f | 1310 | } else { |
f5bbdacc | 1311 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1312 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1313 | } | |
f5bbdacc | 1314 | } |
3f91e94f | 1315 | return max_bitflips; |
f5bbdacc | 1316 | } |
1da177e4 | 1317 | |
6e0cb135 | 1318 | /** |
7854d3f7 | 1319 | * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first |
8b6e50c9 BN |
1320 | * @mtd: mtd info structure |
1321 | * @chip: nand chip info structure | |
1322 | * @buf: buffer to store read data | |
1fbb938d | 1323 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1324 | * @page: page number to read |
6e0cb135 | 1325 | * |
8b6e50c9 BN |
1326 | * Hardware ECC for large page chips, require OOB to be read first. For this |
1327 | * ECC mode, the write_page method is re-used from ECC_HW. These methods | |
1328 | * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with | |
1329 | * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from | |
1330 | * the data area, by overwriting the NAND manufacturer bad block markings. | |
6e0cb135 SN |
1331 | */ |
1332 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1fbb938d | 1333 | struct nand_chip *chip, uint8_t *buf, int oob_required, int page) |
6e0cb135 SN |
1334 | { |
1335 | int i, eccsize = chip->ecc.size; | |
1336 | int eccbytes = chip->ecc.bytes; | |
1337 | int eccsteps = chip->ecc.steps; | |
1338 | uint8_t *p = buf; | |
1339 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1340 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1341 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
3f91e94f | 1342 | unsigned int max_bitflips = 0; |
6e0cb135 SN |
1343 | |
1344 | /* Read the OOB area first */ | |
1345 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1346 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1347 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1348 | ||
1349 | for (i = 0; i < chip->ecc.total; i++) | |
1350 | ecc_code[i] = chip->oob_poi[eccpos[i]]; | |
1351 | ||
1352 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1353 | int stat; | |
1354 | ||
1355 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1356 | chip->read_buf(mtd, p, eccsize); | |
1357 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1358 | ||
1359 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
3f91e94f | 1360 | if (stat < 0) { |
6e0cb135 | 1361 | mtd->ecc_stats.failed++; |
3f91e94f | 1362 | } else { |
6e0cb135 | 1363 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1364 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1365 | } | |
6e0cb135 | 1366 | } |
3f91e94f | 1367 | return max_bitflips; |
6e0cb135 SN |
1368 | } |
1369 | ||
f5bbdacc | 1370 | /** |
7854d3f7 | 1371 | * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read |
8b6e50c9 BN |
1372 | * @mtd: mtd info structure |
1373 | * @chip: nand chip info structure | |
1374 | * @buf: buffer to store read data | |
1fbb938d | 1375 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1376 | * @page: page number to read |
f5bbdacc | 1377 | * |
8b6e50c9 BN |
1378 | * The hw generator calculates the error syndrome automatically. Therefore we |
1379 | * need a special oob layout and handling. | |
f5bbdacc TG |
1380 | */ |
1381 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1382 | uint8_t *buf, int oob_required, int page) |
f5bbdacc TG |
1383 | { |
1384 | int i, eccsize = chip->ecc.size; | |
1385 | int eccbytes = chip->ecc.bytes; | |
1386 | int eccsteps = chip->ecc.steps; | |
1387 | uint8_t *p = buf; | |
f75e5097 | 1388 | uint8_t *oob = chip->oob_poi; |
3f91e94f | 1389 | unsigned int max_bitflips = 0; |
1da177e4 | 1390 | |
f5bbdacc TG |
1391 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1392 | int stat; | |
61b03bd7 | 1393 | |
f5bbdacc TG |
1394 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
1395 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 1396 | |
f5bbdacc TG |
1397 | if (chip->ecc.prepad) { |
1398 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1399 | oob += chip->ecc.prepad; | |
1400 | } | |
1da177e4 | 1401 | |
f5bbdacc TG |
1402 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1403 | chip->read_buf(mtd, oob, eccbytes); | |
1404 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 1405 | |
3f91e94f | 1406 | if (stat < 0) { |
f5bbdacc | 1407 | mtd->ecc_stats.failed++; |
3f91e94f | 1408 | } else { |
f5bbdacc | 1409 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1410 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1411 | } | |
61b03bd7 | 1412 | |
f5bbdacc | 1413 | oob += eccbytes; |
1da177e4 | 1414 | |
f5bbdacc TG |
1415 | if (chip->ecc.postpad) { |
1416 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1417 | oob += chip->ecc.postpad; | |
61b03bd7 | 1418 | } |
f5bbdacc | 1419 | } |
1da177e4 | 1420 | |
f5bbdacc | 1421 | /* Calculate remaining oob bytes */ |
7e4178f9 | 1422 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
1423 | if (i) |
1424 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 1425 | |
3f91e94f | 1426 | return max_bitflips; |
f5bbdacc | 1427 | } |
1da177e4 | 1428 | |
f5bbdacc | 1429 | /** |
7854d3f7 | 1430 | * nand_transfer_oob - [INTERN] Transfer oob to client buffer |
8b6e50c9 BN |
1431 | * @chip: nand chip structure |
1432 | * @oob: oob destination address | |
1433 | * @ops: oob ops structure | |
1434 | * @len: size of oob to transfer | |
8593fbc6 TG |
1435 | */ |
1436 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, | |
7014568b | 1437 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 1438 | { |
f8ac0414 | 1439 | switch (ops->mode) { |
8593fbc6 | 1440 | |
0612b9dd BN |
1441 | case MTD_OPS_PLACE_OOB: |
1442 | case MTD_OPS_RAW: | |
8593fbc6 TG |
1443 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); |
1444 | return oob + len; | |
1445 | ||
0612b9dd | 1446 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 1447 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
1448 | uint32_t boffs = 0, roffs = ops->ooboffs; |
1449 | size_t bytes = 0; | |
8593fbc6 | 1450 | |
f8ac0414 | 1451 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 1452 | /* Read request not from offset 0? */ |
7bc3312b TG |
1453 | if (unlikely(roffs)) { |
1454 | if (roffs >= free->length) { | |
1455 | roffs -= free->length; | |
1456 | continue; | |
1457 | } | |
1458 | boffs = free->offset + roffs; | |
1459 | bytes = min_t(size_t, len, | |
1460 | (free->length - roffs)); | |
1461 | roffs = 0; | |
1462 | } else { | |
1463 | bytes = min_t(size_t, len, free->length); | |
1464 | boffs = free->offset; | |
1465 | } | |
1466 | memcpy(oob, chip->oob_poi + boffs, bytes); | |
8593fbc6 TG |
1467 | oob += bytes; |
1468 | } | |
1469 | return oob; | |
1470 | } | |
1471 | default: | |
1472 | BUG(); | |
1473 | } | |
1474 | return NULL; | |
1475 | } | |
1476 | ||
ba84fb59 BN |
1477 | /** |
1478 | * nand_setup_read_retry - [INTERN] Set the READ RETRY mode | |
1479 | * @mtd: MTD device structure | |
1480 | * @retry_mode: the retry mode to use | |
1481 | * | |
1482 | * Some vendors supply a special command to shift the Vt threshold, to be used | |
1483 | * when there are too many bitflips in a page (i.e., ECC error). After setting | |
1484 | * a new threshold, the host should retry reading the page. | |
1485 | */ | |
1486 | static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) | |
1487 | { | |
1488 | struct nand_chip *chip = mtd->priv; | |
1489 | ||
1490 | pr_debug("setting READ RETRY mode %d\n", retry_mode); | |
1491 | ||
1492 | if (retry_mode >= chip->read_retries) | |
1493 | return -EINVAL; | |
1494 | ||
1495 | if (!chip->setup_read_retry) | |
1496 | return -EOPNOTSUPP; | |
1497 | ||
1498 | return chip->setup_read_retry(mtd, retry_mode); | |
1499 | } | |
1500 | ||
8593fbc6 | 1501 | /** |
7854d3f7 | 1502 | * nand_do_read_ops - [INTERN] Read data with ECC |
8b6e50c9 BN |
1503 | * @mtd: MTD device structure |
1504 | * @from: offset to read from | |
1505 | * @ops: oob ops structure | |
f5bbdacc TG |
1506 | * |
1507 | * Internal function. Called with chip held. | |
1508 | */ | |
8593fbc6 TG |
1509 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
1510 | struct mtd_oob_ops *ops) | |
f5bbdacc | 1511 | { |
e47f3db4 | 1512 | int chipnr, page, realpage, col, bytes, aligned, oob_required; |
f5bbdacc | 1513 | struct nand_chip *chip = mtd->priv; |
f5bbdacc | 1514 | int ret = 0; |
8593fbc6 | 1515 | uint32_t readlen = ops->len; |
7014568b | 1516 | uint32_t oobreadlen = ops->ooblen; |
0612b9dd | 1517 | uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ? |
9aca334e ML |
1518 | mtd->oobavail : mtd->oobsize; |
1519 | ||
8593fbc6 | 1520 | uint8_t *bufpoi, *oob, *buf; |
66507c7b | 1521 | int use_bufpoi; |
edbc4540 | 1522 | unsigned int max_bitflips = 0; |
ba84fb59 | 1523 | int retry_mode = 0; |
b72f3dfb | 1524 | bool ecc_fail = false; |
1da177e4 | 1525 | |
f5bbdacc TG |
1526 | chipnr = (int)(from >> chip->chip_shift); |
1527 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 1528 | |
f5bbdacc TG |
1529 | realpage = (int)(from >> chip->page_shift); |
1530 | page = realpage & chip->pagemask; | |
1da177e4 | 1531 | |
f5bbdacc | 1532 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 1533 | |
8593fbc6 TG |
1534 | buf = ops->datbuf; |
1535 | oob = ops->oobbuf; | |
e47f3db4 | 1536 | oob_required = oob ? 1 : 0; |
8593fbc6 | 1537 | |
f8ac0414 | 1538 | while (1) { |
b72f3dfb BN |
1539 | unsigned int ecc_failures = mtd->ecc_stats.failed; |
1540 | ||
f5bbdacc TG |
1541 | bytes = min(mtd->writesize - col, readlen); |
1542 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 1543 | |
66507c7b KD |
1544 | if (!aligned) |
1545 | use_bufpoi = 1; | |
1546 | else if (chip->options & NAND_USE_BOUNCE_BUFFER) | |
1547 | use_bufpoi = !virt_addr_valid(buf); | |
1548 | else | |
1549 | use_bufpoi = 0; | |
1550 | ||
8b6e50c9 | 1551 | /* Is the current page in the buffer? */ |
8593fbc6 | 1552 | if (realpage != chip->pagebuf || oob) { |
66507c7b KD |
1553 | bufpoi = use_bufpoi ? chip->buffers->databuf : buf; |
1554 | ||
1555 | if (use_bufpoi && aligned) | |
1556 | pr_debug("%s: using read bounce buffer for buf@%p\n", | |
1557 | __func__, buf); | |
61b03bd7 | 1558 | |
ba84fb59 | 1559 | read_retry: |
c00a0991 | 1560 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); |
1da177e4 | 1561 | |
edbc4540 MD |
1562 | /* |
1563 | * Now read the page into the buffer. Absent an error, | |
1564 | * the read methods return max bitflips per ecc step. | |
1565 | */ | |
0612b9dd | 1566 | if (unlikely(ops->mode == MTD_OPS_RAW)) |
1fbb938d | 1567 | ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, |
e47f3db4 BN |
1568 | oob_required, |
1569 | page); | |
a5ff4f10 JW |
1570 | else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && |
1571 | !oob) | |
7351d3a5 | 1572 | ret = chip->ecc.read_subpage(mtd, chip, |
e004debd HS |
1573 | col, bytes, bufpoi, |
1574 | page); | |
956e944c | 1575 | else |
46a8cf2d | 1576 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
e47f3db4 | 1577 | oob_required, page); |
6d77b9d0 | 1578 | if (ret < 0) { |
66507c7b | 1579 | if (use_bufpoi) |
6d77b9d0 BN |
1580 | /* Invalidate page cache */ |
1581 | chip->pagebuf = -1; | |
1da177e4 | 1582 | break; |
6d77b9d0 | 1583 | } |
f5bbdacc | 1584 | |
edbc4540 MD |
1585 | max_bitflips = max_t(unsigned int, max_bitflips, ret); |
1586 | ||
f5bbdacc | 1587 | /* Transfer not aligned data */ |
66507c7b | 1588 | if (use_bufpoi) { |
a5ff4f10 | 1589 | if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && |
b72f3dfb | 1590 | !(mtd->ecc_stats.failed - ecc_failures) && |
edbc4540 | 1591 | (ops->mode != MTD_OPS_RAW)) { |
3d459559 | 1592 | chip->pagebuf = realpage; |
edbc4540 MD |
1593 | chip->pagebuf_bitflips = ret; |
1594 | } else { | |
6d77b9d0 BN |
1595 | /* Invalidate page cache */ |
1596 | chip->pagebuf = -1; | |
edbc4540 | 1597 | } |
4bf63fcb | 1598 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
1599 | } |
1600 | ||
8593fbc6 | 1601 | if (unlikely(oob)) { |
b64d39d8 ML |
1602 | int toread = min(oobreadlen, max_oobsize); |
1603 | ||
1604 | if (toread) { | |
1605 | oob = nand_transfer_oob(chip, | |
1606 | oob, ops, toread); | |
1607 | oobreadlen -= toread; | |
1608 | } | |
8593fbc6 | 1609 | } |
5bc7c33c BN |
1610 | |
1611 | if (chip->options & NAND_NEED_READRDY) { | |
1612 | /* Apply delay or wait for ready/busy pin */ | |
1613 | if (!chip->dev_ready) | |
1614 | udelay(chip->chip_delay); | |
1615 | else | |
1616 | nand_wait_ready(mtd); | |
1617 | } | |
b72f3dfb | 1618 | |
ba84fb59 | 1619 | if (mtd->ecc_stats.failed - ecc_failures) { |
28fa65e6 | 1620 | if (retry_mode + 1 < chip->read_retries) { |
ba84fb59 BN |
1621 | retry_mode++; |
1622 | ret = nand_setup_read_retry(mtd, | |
1623 | retry_mode); | |
1624 | if (ret < 0) | |
1625 | break; | |
1626 | ||
1627 | /* Reset failures; retry */ | |
1628 | mtd->ecc_stats.failed = ecc_failures; | |
1629 | goto read_retry; | |
1630 | } else { | |
1631 | /* No more retry modes; real failure */ | |
1632 | ecc_fail = true; | |
1633 | } | |
1634 | } | |
1635 | ||
1636 | buf += bytes; | |
8593fbc6 | 1637 | } else { |
4bf63fcb | 1638 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 | 1639 | buf += bytes; |
edbc4540 MD |
1640 | max_bitflips = max_t(unsigned int, max_bitflips, |
1641 | chip->pagebuf_bitflips); | |
8593fbc6 | 1642 | } |
1da177e4 | 1643 | |
f5bbdacc | 1644 | readlen -= bytes; |
61b03bd7 | 1645 | |
ba84fb59 BN |
1646 | /* Reset to retry mode 0 */ |
1647 | if (retry_mode) { | |
1648 | ret = nand_setup_read_retry(mtd, 0); | |
1649 | if (ret < 0) | |
1650 | break; | |
1651 | retry_mode = 0; | |
1652 | } | |
1653 | ||
f5bbdacc | 1654 | if (!readlen) |
61b03bd7 | 1655 | break; |
1da177e4 | 1656 | |
8b6e50c9 | 1657 | /* For subsequent reads align to page boundary */ |
1da177e4 LT |
1658 | col = 0; |
1659 | /* Increment page address */ | |
1660 | realpage++; | |
1661 | ||
ace4dfee | 1662 | page = realpage & chip->pagemask; |
1da177e4 LT |
1663 | /* Check, if we cross a chip boundary */ |
1664 | if (!page) { | |
1665 | chipnr++; | |
ace4dfee TG |
1666 | chip->select_chip(mtd, -1); |
1667 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1668 | } |
1da177e4 | 1669 | } |
b0bb6903 | 1670 | chip->select_chip(mtd, -1); |
1da177e4 | 1671 | |
8593fbc6 | 1672 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
1673 | if (oob) |
1674 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 1675 | |
3f91e94f | 1676 | if (ret < 0) |
f5bbdacc TG |
1677 | return ret; |
1678 | ||
b72f3dfb | 1679 | if (ecc_fail) |
9a1fcdfd TG |
1680 | return -EBADMSG; |
1681 | ||
edbc4540 | 1682 | return max_bitflips; |
f5bbdacc TG |
1683 | } |
1684 | ||
1685 | /** | |
25985edc | 1686 | * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc |
8b6e50c9 BN |
1687 | * @mtd: MTD device structure |
1688 | * @from: offset to read from | |
1689 | * @len: number of bytes to read | |
1690 | * @retlen: pointer to variable to store the number of read bytes | |
1691 | * @buf: the databuffer to put data | |
f5bbdacc | 1692 | * |
8b6e50c9 | 1693 | * Get hold of the chip and call nand_do_read. |
f5bbdacc TG |
1694 | */ |
1695 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1696 | size_t *retlen, uint8_t *buf) | |
1697 | { | |
4a89ff88 | 1698 | struct mtd_oob_ops ops; |
f5bbdacc TG |
1699 | int ret; |
1700 | ||
6a8214aa | 1701 | nand_get_device(mtd, FL_READING); |
4a89ff88 BN |
1702 | ops.len = len; |
1703 | ops.datbuf = buf; | |
1704 | ops.oobbuf = NULL; | |
11041ae6 | 1705 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 1706 | ret = nand_do_read_ops(mtd, from, &ops); |
4a89ff88 | 1707 | *retlen = ops.retlen; |
f5bbdacc | 1708 | nand_release_device(mtd); |
f5bbdacc | 1709 | return ret; |
1da177e4 LT |
1710 | } |
1711 | ||
7bc3312b | 1712 | /** |
7854d3f7 | 1713 | * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function |
8b6e50c9 BN |
1714 | * @mtd: mtd info structure |
1715 | * @chip: nand chip info structure | |
1716 | * @page: page number to read | |
7bc3312b TG |
1717 | */ |
1718 | static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1719 | int page) |
7bc3312b | 1720 | { |
5c2ffb11 | 1721 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); |
7bc3312b | 1722 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
5c2ffb11 | 1723 | return 0; |
7bc3312b TG |
1724 | } |
1725 | ||
1726 | /** | |
7854d3f7 | 1727 | * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC |
7bc3312b | 1728 | * with syndromes |
8b6e50c9 BN |
1729 | * @mtd: mtd info structure |
1730 | * @chip: nand chip info structure | |
1731 | * @page: page number to read | |
7bc3312b TG |
1732 | */ |
1733 | static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1734 | int page) |
7bc3312b TG |
1735 | { |
1736 | uint8_t *buf = chip->oob_poi; | |
1737 | int length = mtd->oobsize; | |
1738 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1739 | int eccsize = chip->ecc.size; | |
1740 | uint8_t *bufpoi = buf; | |
1741 | int i, toread, sndrnd = 0, pos; | |
1742 | ||
1743 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
1744 | for (i = 0; i < chip->ecc.steps; i++) { | |
1745 | if (sndrnd) { | |
1746 | pos = eccsize + i * (eccsize + chunk); | |
1747 | if (mtd->writesize > 512) | |
1748 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
1749 | else | |
1750 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
1751 | } else | |
1752 | sndrnd = 1; | |
1753 | toread = min_t(int, length, chunk); | |
1754 | chip->read_buf(mtd, bufpoi, toread); | |
1755 | bufpoi += toread; | |
1756 | length -= toread; | |
1757 | } | |
1758 | if (length > 0) | |
1759 | chip->read_buf(mtd, bufpoi, length); | |
1760 | ||
5c2ffb11 | 1761 | return 0; |
7bc3312b TG |
1762 | } |
1763 | ||
1764 | /** | |
7854d3f7 | 1765 | * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function |
8b6e50c9 BN |
1766 | * @mtd: mtd info structure |
1767 | * @chip: nand chip info structure | |
1768 | * @page: page number to write | |
7bc3312b TG |
1769 | */ |
1770 | static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1771 | int page) | |
1772 | { | |
1773 | int status = 0; | |
1774 | const uint8_t *buf = chip->oob_poi; | |
1775 | int length = mtd->oobsize; | |
1776 | ||
1777 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
1778 | chip->write_buf(mtd, buf, length); | |
1779 | /* Send command to program the OOB data */ | |
1780 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1781 | ||
1782 | status = chip->waitfunc(mtd, chip); | |
1783 | ||
0d420f9d | 1784 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b TG |
1785 | } |
1786 | ||
1787 | /** | |
7854d3f7 | 1788 | * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC |
8b6e50c9 BN |
1789 | * with syndrome - only for large page flash |
1790 | * @mtd: mtd info structure | |
1791 | * @chip: nand chip info structure | |
1792 | * @page: page number to write | |
7bc3312b TG |
1793 | */ |
1794 | static int nand_write_oob_syndrome(struct mtd_info *mtd, | |
1795 | struct nand_chip *chip, int page) | |
1796 | { | |
1797 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1798 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
1799 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
1800 | const uint8_t *bufpoi = chip->oob_poi; | |
1801 | ||
1802 | /* | |
1803 | * data-ecc-data-ecc ... ecc-oob | |
1804 | * or | |
1805 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
1806 | */ | |
1807 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
1808 | pos = steps * (eccsize + chunk); | |
1809 | steps = 0; | |
1810 | } else | |
8b0036ee | 1811 | pos = eccsize; |
7bc3312b TG |
1812 | |
1813 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
1814 | for (i = 0; i < steps; i++) { | |
1815 | if (sndcmd) { | |
1816 | if (mtd->writesize <= 512) { | |
1817 | uint32_t fill = 0xFFFFFFFF; | |
1818 | ||
1819 | len = eccsize; | |
1820 | while (len > 0) { | |
1821 | int num = min_t(int, len, 4); | |
1822 | chip->write_buf(mtd, (uint8_t *)&fill, | |
1823 | num); | |
1824 | len -= num; | |
1825 | } | |
1826 | } else { | |
1827 | pos = eccsize + i * (eccsize + chunk); | |
1828 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
1829 | } | |
1830 | } else | |
1831 | sndcmd = 1; | |
1832 | len = min_t(int, length, chunk); | |
1833 | chip->write_buf(mtd, bufpoi, len); | |
1834 | bufpoi += len; | |
1835 | length -= len; | |
1836 | } | |
1837 | if (length > 0) | |
1838 | chip->write_buf(mtd, bufpoi, length); | |
1839 | ||
1840 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1841 | status = chip->waitfunc(mtd, chip); | |
1842 | ||
1843 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
1844 | } | |
1845 | ||
1da177e4 | 1846 | /** |
7854d3f7 | 1847 | * nand_do_read_oob - [INTERN] NAND read out-of-band |
8b6e50c9 BN |
1848 | * @mtd: MTD device structure |
1849 | * @from: offset to read from | |
1850 | * @ops: oob operations description structure | |
1da177e4 | 1851 | * |
8b6e50c9 | 1852 | * NAND read out-of-band data from the spare area. |
1da177e4 | 1853 | */ |
8593fbc6 TG |
1854 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
1855 | struct mtd_oob_ops *ops) | |
1da177e4 | 1856 | { |
c00a0991 | 1857 | int page, realpage, chipnr; |
ace4dfee | 1858 | struct nand_chip *chip = mtd->priv; |
041e4575 | 1859 | struct mtd_ecc_stats stats; |
7014568b VW |
1860 | int readlen = ops->ooblen; |
1861 | int len; | |
7bc3312b | 1862 | uint8_t *buf = ops->oobbuf; |
1951f2f7 | 1863 | int ret = 0; |
61b03bd7 | 1864 | |
289c0522 | 1865 | pr_debug("%s: from = 0x%08Lx, len = %i\n", |
20d8e248 | 1866 | __func__, (unsigned long long)from, readlen); |
1da177e4 | 1867 | |
041e4575 BN |
1868 | stats = mtd->ecc_stats; |
1869 | ||
0612b9dd | 1870 | if (ops->mode == MTD_OPS_AUTO_OOB) |
7014568b | 1871 | len = chip->ecc.layout->oobavail; |
03736155 AH |
1872 | else |
1873 | len = mtd->oobsize; | |
1874 | ||
1875 | if (unlikely(ops->ooboffs >= len)) { | |
289c0522 BN |
1876 | pr_debug("%s: attempt to start read outside oob\n", |
1877 | __func__); | |
03736155 AH |
1878 | return -EINVAL; |
1879 | } | |
1880 | ||
1881 | /* Do not allow reads past end of device */ | |
1882 | if (unlikely(from >= mtd->size || | |
1883 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
1884 | (from >> chip->page_shift)) * len)) { | |
289c0522 BN |
1885 | pr_debug("%s: attempt to read beyond end of device\n", |
1886 | __func__); | |
03736155 AH |
1887 | return -EINVAL; |
1888 | } | |
7014568b | 1889 | |
7314e9e7 | 1890 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 1891 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1892 | |
7314e9e7 TG |
1893 | /* Shift to get page */ |
1894 | realpage = (int)(from >> chip->page_shift); | |
1895 | page = realpage & chip->pagemask; | |
1da177e4 | 1896 | |
f8ac0414 | 1897 | while (1) { |
0612b9dd | 1898 | if (ops->mode == MTD_OPS_RAW) |
1951f2f7 | 1899 | ret = chip->ecc.read_oob_raw(mtd, chip, page); |
c46f6483 | 1900 | else |
1951f2f7 SL |
1901 | ret = chip->ecc.read_oob(mtd, chip, page); |
1902 | ||
1903 | if (ret < 0) | |
1904 | break; | |
7014568b VW |
1905 | |
1906 | len = min(len, readlen); | |
1907 | buf = nand_transfer_oob(chip, buf, ops, len); | |
8593fbc6 | 1908 | |
5bc7c33c BN |
1909 | if (chip->options & NAND_NEED_READRDY) { |
1910 | /* Apply delay or wait for ready/busy pin */ | |
1911 | if (!chip->dev_ready) | |
1912 | udelay(chip->chip_delay); | |
1913 | else | |
1914 | nand_wait_ready(mtd); | |
1915 | } | |
1916 | ||
7014568b | 1917 | readlen -= len; |
0d420f9d SZ |
1918 | if (!readlen) |
1919 | break; | |
1920 | ||
7314e9e7 TG |
1921 | /* Increment page address */ |
1922 | realpage++; | |
1923 | ||
1924 | page = realpage & chip->pagemask; | |
1925 | /* Check, if we cross a chip boundary */ | |
1926 | if (!page) { | |
1927 | chipnr++; | |
1928 | chip->select_chip(mtd, -1); | |
1929 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
1930 | } |
1931 | } | |
b0bb6903 | 1932 | chip->select_chip(mtd, -1); |
1da177e4 | 1933 | |
1951f2f7 SL |
1934 | ops->oobretlen = ops->ooblen - readlen; |
1935 | ||
1936 | if (ret < 0) | |
1937 | return ret; | |
041e4575 BN |
1938 | |
1939 | if (mtd->ecc_stats.failed - stats.failed) | |
1940 | return -EBADMSG; | |
1941 | ||
1942 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
1da177e4 LT |
1943 | } |
1944 | ||
1945 | /** | |
8593fbc6 | 1946 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
8b6e50c9 BN |
1947 | * @mtd: MTD device structure |
1948 | * @from: offset to read from | |
1949 | * @ops: oob operation description structure | |
1da177e4 | 1950 | * |
8b6e50c9 | 1951 | * NAND read data and/or out-of-band data. |
1da177e4 | 1952 | */ |
8593fbc6 TG |
1953 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
1954 | struct mtd_oob_ops *ops) | |
1da177e4 | 1955 | { |
8593fbc6 TG |
1956 | int ret = -ENOTSUPP; |
1957 | ||
1958 | ops->retlen = 0; | |
1da177e4 LT |
1959 | |
1960 | /* Do not allow reads past end of device */ | |
7014568b | 1961 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
289c0522 BN |
1962 | pr_debug("%s: attempt to read beyond end of device\n", |
1963 | __func__); | |
1da177e4 LT |
1964 | return -EINVAL; |
1965 | } | |
1966 | ||
6a8214aa | 1967 | nand_get_device(mtd, FL_READING); |
1da177e4 | 1968 | |
f8ac0414 | 1969 | switch (ops->mode) { |
0612b9dd BN |
1970 | case MTD_OPS_PLACE_OOB: |
1971 | case MTD_OPS_AUTO_OOB: | |
1972 | case MTD_OPS_RAW: | |
8593fbc6 | 1973 | break; |
1da177e4 | 1974 | |
8593fbc6 TG |
1975 | default: |
1976 | goto out; | |
1977 | } | |
1da177e4 | 1978 | |
8593fbc6 TG |
1979 | if (!ops->datbuf) |
1980 | ret = nand_do_read_oob(mtd, from, ops); | |
1981 | else | |
1982 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 1983 | |
7351d3a5 | 1984 | out: |
8593fbc6 TG |
1985 | nand_release_device(mtd); |
1986 | return ret; | |
1987 | } | |
61b03bd7 | 1988 | |
1da177e4 | 1989 | |
8593fbc6 | 1990 | /** |
7854d3f7 | 1991 | * nand_write_page_raw - [INTERN] raw page write function |
8b6e50c9 BN |
1992 | * @mtd: mtd info structure |
1993 | * @chip: nand chip info structure | |
1994 | * @buf: data buffer | |
1fbb938d | 1995 | * @oob_required: must write chip->oob_poi to OOB |
52ff49df | 1996 | * |
7854d3f7 | 1997 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 | 1998 | */ |
fdbad98d | 1999 | static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 2000 | const uint8_t *buf, int oob_required) |
8593fbc6 TG |
2001 | { |
2002 | chip->write_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
2003 | if (oob_required) |
2004 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
2005 | |
2006 | return 0; | |
1da177e4 LT |
2007 | } |
2008 | ||
52ff49df | 2009 | /** |
7854d3f7 | 2010 | * nand_write_page_raw_syndrome - [INTERN] raw page write function |
8b6e50c9 BN |
2011 | * @mtd: mtd info structure |
2012 | * @chip: nand chip info structure | |
2013 | * @buf: data buffer | |
1fbb938d | 2014 | * @oob_required: must write chip->oob_poi to OOB |
52ff49df DB |
2015 | * |
2016 | * We need a special oob layout and handling even when ECC isn't checked. | |
2017 | */ | |
fdbad98d | 2018 | static int nand_write_page_raw_syndrome(struct mtd_info *mtd, |
7351d3a5 | 2019 | struct nand_chip *chip, |
1fbb938d | 2020 | const uint8_t *buf, int oob_required) |
52ff49df DB |
2021 | { |
2022 | int eccsize = chip->ecc.size; | |
2023 | int eccbytes = chip->ecc.bytes; | |
2024 | uint8_t *oob = chip->oob_poi; | |
2025 | int steps, size; | |
2026 | ||
2027 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
2028 | chip->write_buf(mtd, buf, eccsize); | |
2029 | buf += eccsize; | |
2030 | ||
2031 | if (chip->ecc.prepad) { | |
2032 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2033 | oob += chip->ecc.prepad; | |
2034 | } | |
2035 | ||
60c3bc1f | 2036 | chip->write_buf(mtd, oob, eccbytes); |
52ff49df DB |
2037 | oob += eccbytes; |
2038 | ||
2039 | if (chip->ecc.postpad) { | |
2040 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2041 | oob += chip->ecc.postpad; | |
2042 | } | |
2043 | } | |
2044 | ||
2045 | size = mtd->oobsize - (oob - chip->oob_poi); | |
2046 | if (size) | |
2047 | chip->write_buf(mtd, oob, size); | |
fdbad98d JW |
2048 | |
2049 | return 0; | |
52ff49df | 2050 | } |
9223a456 | 2051 | /** |
7854d3f7 | 2052 | * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function |
8b6e50c9 BN |
2053 | * @mtd: mtd info structure |
2054 | * @chip: nand chip info structure | |
2055 | * @buf: data buffer | |
1fbb938d | 2056 | * @oob_required: must write chip->oob_poi to OOB |
9223a456 | 2057 | */ |
fdbad98d | 2058 | static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 2059 | const uint8_t *buf, int oob_required) |
9223a456 | 2060 | { |
f75e5097 TG |
2061 | int i, eccsize = chip->ecc.size; |
2062 | int eccbytes = chip->ecc.bytes; | |
2063 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2064 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2065 | const uint8_t *p = buf; |
8b099a39 | 2066 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 2067 | |
7854d3f7 | 2068 | /* Software ECC calculation */ |
8593fbc6 TG |
2069 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
2070 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 2071 | |
8593fbc6 TG |
2072 | for (i = 0; i < chip->ecc.total; i++) |
2073 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 | 2074 | |
fdbad98d | 2075 | return chip->ecc.write_page_raw(mtd, chip, buf, 1); |
f75e5097 | 2076 | } |
9223a456 | 2077 | |
f75e5097 | 2078 | /** |
7854d3f7 | 2079 | * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function |
8b6e50c9 BN |
2080 | * @mtd: mtd info structure |
2081 | * @chip: nand chip info structure | |
2082 | * @buf: data buffer | |
1fbb938d | 2083 | * @oob_required: must write chip->oob_poi to OOB |
f75e5097 | 2084 | */ |
fdbad98d | 2085 | static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 2086 | const uint8_t *buf, int oob_required) |
f75e5097 TG |
2087 | { |
2088 | int i, eccsize = chip->ecc.size; | |
2089 | int eccbytes = chip->ecc.bytes; | |
2090 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2091 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2092 | const uint8_t *p = buf; |
8b099a39 | 2093 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 2094 | |
f75e5097 TG |
2095 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
2096 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 2097 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 2098 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
2099 | } |
2100 | ||
f75e5097 TG |
2101 | for (i = 0; i < chip->ecc.total; i++) |
2102 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
2103 | ||
2104 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
2105 | |
2106 | return 0; | |
9223a456 TG |
2107 | } |
2108 | ||
837a6ba4 GP |
2109 | |
2110 | /** | |
2111 | * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write | |
2112 | * @mtd: mtd info structure | |
2113 | * @chip: nand chip info structure | |
d6a95080 | 2114 | * @offset: column address of subpage within the page |
837a6ba4 | 2115 | * @data_len: data length |
d6a95080 | 2116 | * @buf: data buffer |
837a6ba4 GP |
2117 | * @oob_required: must write chip->oob_poi to OOB |
2118 | */ | |
2119 | static int nand_write_subpage_hwecc(struct mtd_info *mtd, | |
2120 | struct nand_chip *chip, uint32_t offset, | |
d6a95080 | 2121 | uint32_t data_len, const uint8_t *buf, |
837a6ba4 GP |
2122 | int oob_required) |
2123 | { | |
2124 | uint8_t *oob_buf = chip->oob_poi; | |
2125 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
2126 | int ecc_size = chip->ecc.size; | |
2127 | int ecc_bytes = chip->ecc.bytes; | |
2128 | int ecc_steps = chip->ecc.steps; | |
2129 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
2130 | uint32_t start_step = offset / ecc_size; | |
2131 | uint32_t end_step = (offset + data_len - 1) / ecc_size; | |
2132 | int oob_bytes = mtd->oobsize / ecc_steps; | |
2133 | int step, i; | |
2134 | ||
2135 | for (step = 0; step < ecc_steps; step++) { | |
2136 | /* configure controller for WRITE access */ | |
2137 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
2138 | ||
2139 | /* write data (untouched subpages already masked by 0xFF) */ | |
d6a95080 | 2140 | chip->write_buf(mtd, buf, ecc_size); |
837a6ba4 GP |
2141 | |
2142 | /* mask ECC of un-touched subpages by padding 0xFF */ | |
2143 | if ((step < start_step) || (step > end_step)) | |
2144 | memset(ecc_calc, 0xff, ecc_bytes); | |
2145 | else | |
d6a95080 | 2146 | chip->ecc.calculate(mtd, buf, ecc_calc); |
837a6ba4 GP |
2147 | |
2148 | /* mask OOB of un-touched subpages by padding 0xFF */ | |
2149 | /* if oob_required, preserve OOB metadata of written subpage */ | |
2150 | if (!oob_required || (step < start_step) || (step > end_step)) | |
2151 | memset(oob_buf, 0xff, oob_bytes); | |
2152 | ||
d6a95080 | 2153 | buf += ecc_size; |
837a6ba4 GP |
2154 | ecc_calc += ecc_bytes; |
2155 | oob_buf += oob_bytes; | |
2156 | } | |
2157 | ||
2158 | /* copy calculated ECC for whole page to chip->buffer->oob */ | |
2159 | /* this include masked-value(0xFF) for unwritten subpages */ | |
2160 | ecc_calc = chip->buffers->ecccalc; | |
2161 | for (i = 0; i < chip->ecc.total; i++) | |
2162 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
2163 | ||
2164 | /* write OOB buffer to NAND device */ | |
2165 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
2166 | ||
2167 | return 0; | |
2168 | } | |
2169 | ||
2170 | ||
61b03bd7 | 2171 | /** |
7854d3f7 | 2172 | * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write |
8b6e50c9 BN |
2173 | * @mtd: mtd info structure |
2174 | * @chip: nand chip info structure | |
2175 | * @buf: data buffer | |
1fbb938d | 2176 | * @oob_required: must write chip->oob_poi to OOB |
1da177e4 | 2177 | * |
8b6e50c9 BN |
2178 | * The hw generator calculates the error syndrome automatically. Therefore we |
2179 | * need a special oob layout and handling. | |
f75e5097 | 2180 | */ |
fdbad98d | 2181 | static int nand_write_page_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
2182 | struct nand_chip *chip, |
2183 | const uint8_t *buf, int oob_required) | |
1da177e4 | 2184 | { |
f75e5097 TG |
2185 | int i, eccsize = chip->ecc.size; |
2186 | int eccbytes = chip->ecc.bytes; | |
2187 | int eccsteps = chip->ecc.steps; | |
2188 | const uint8_t *p = buf; | |
2189 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 2190 | |
f75e5097 | 2191 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 2192 | |
f75e5097 TG |
2193 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
2194 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 2195 | |
f75e5097 TG |
2196 | if (chip->ecc.prepad) { |
2197 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2198 | oob += chip->ecc.prepad; | |
2199 | } | |
2200 | ||
2201 | chip->ecc.calculate(mtd, p, oob); | |
2202 | chip->write_buf(mtd, oob, eccbytes); | |
2203 | oob += eccbytes; | |
2204 | ||
2205 | if (chip->ecc.postpad) { | |
2206 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2207 | oob += chip->ecc.postpad; | |
1da177e4 | 2208 | } |
1da177e4 | 2209 | } |
f75e5097 TG |
2210 | |
2211 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 2212 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
2213 | if (i) |
2214 | chip->write_buf(mtd, oob, i); | |
fdbad98d JW |
2215 | |
2216 | return 0; | |
f75e5097 TG |
2217 | } |
2218 | ||
2219 | /** | |
956e944c | 2220 | * nand_write_page - [REPLACEABLE] write one page |
8b6e50c9 BN |
2221 | * @mtd: MTD device structure |
2222 | * @chip: NAND chip descriptor | |
837a6ba4 GP |
2223 | * @offset: address offset within the page |
2224 | * @data_len: length of actual data to be written | |
8b6e50c9 | 2225 | * @buf: the data to write |
1fbb938d | 2226 | * @oob_required: must write chip->oob_poi to OOB |
8b6e50c9 BN |
2227 | * @page: page number to write |
2228 | * @cached: cached programming | |
2229 | * @raw: use _raw version of write_page | |
f75e5097 TG |
2230 | */ |
2231 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
837a6ba4 GP |
2232 | uint32_t offset, int data_len, const uint8_t *buf, |
2233 | int oob_required, int page, int cached, int raw) | |
f75e5097 | 2234 | { |
837a6ba4 GP |
2235 | int status, subpage; |
2236 | ||
2237 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && | |
2238 | chip->ecc.write_subpage) | |
2239 | subpage = offset || (data_len < mtd->writesize); | |
2240 | else | |
2241 | subpage = 0; | |
f75e5097 TG |
2242 | |
2243 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
2244 | ||
956e944c | 2245 | if (unlikely(raw)) |
837a6ba4 GP |
2246 | status = chip->ecc.write_page_raw(mtd, chip, buf, |
2247 | oob_required); | |
2248 | else if (subpage) | |
2249 | status = chip->ecc.write_subpage(mtd, chip, offset, data_len, | |
2250 | buf, oob_required); | |
956e944c | 2251 | else |
fdbad98d JW |
2252 | status = chip->ecc.write_page(mtd, chip, buf, oob_required); |
2253 | ||
2254 | if (status < 0) | |
2255 | return status; | |
f75e5097 TG |
2256 | |
2257 | /* | |
7854d3f7 | 2258 | * Cached progamming disabled for now. Not sure if it's worth the |
8b6e50c9 | 2259 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s). |
f75e5097 TG |
2260 | */ |
2261 | cached = 0; | |
2262 | ||
3239a6cd | 2263 | if (!cached || !NAND_HAS_CACHEPROG(chip)) { |
f75e5097 TG |
2264 | |
2265 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
7bc3312b | 2266 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2267 | /* |
2268 | * See if operation failed and additional status checks are | |
8b6e50c9 | 2269 | * available. |
f75e5097 TG |
2270 | */ |
2271 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2272 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
2273 | page); | |
2274 | ||
2275 | if (status & NAND_STATUS_FAIL) | |
2276 | return -EIO; | |
2277 | } else { | |
2278 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
7bc3312b | 2279 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2280 | } |
2281 | ||
f75e5097 | 2282 | return 0; |
1da177e4 LT |
2283 | } |
2284 | ||
8593fbc6 | 2285 | /** |
7854d3f7 | 2286 | * nand_fill_oob - [INTERN] Transfer client buffer to oob |
f722013e | 2287 | * @mtd: MTD device structure |
8b6e50c9 BN |
2288 | * @oob: oob data buffer |
2289 | * @len: oob data write length | |
2290 | * @ops: oob ops structure | |
8593fbc6 | 2291 | */ |
f722013e TAA |
2292 | static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, |
2293 | struct mtd_oob_ops *ops) | |
8593fbc6 | 2294 | { |
f722013e TAA |
2295 | struct nand_chip *chip = mtd->priv; |
2296 | ||
2297 | /* | |
2298 | * Initialise to all 0xFF, to avoid the possibility of left over OOB | |
2299 | * data from a previous OOB read. | |
2300 | */ | |
2301 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
2302 | ||
f8ac0414 | 2303 | switch (ops->mode) { |
8593fbc6 | 2304 | |
0612b9dd BN |
2305 | case MTD_OPS_PLACE_OOB: |
2306 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2307 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); |
2308 | return oob + len; | |
2309 | ||
0612b9dd | 2310 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 2311 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
2312 | uint32_t boffs = 0, woffs = ops->ooboffs; |
2313 | size_t bytes = 0; | |
8593fbc6 | 2314 | |
f8ac0414 | 2315 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 2316 | /* Write request not from offset 0? */ |
7bc3312b TG |
2317 | if (unlikely(woffs)) { |
2318 | if (woffs >= free->length) { | |
2319 | woffs -= free->length; | |
2320 | continue; | |
2321 | } | |
2322 | boffs = free->offset + woffs; | |
2323 | bytes = min_t(size_t, len, | |
2324 | (free->length - woffs)); | |
2325 | woffs = 0; | |
2326 | } else { | |
2327 | bytes = min_t(size_t, len, free->length); | |
2328 | boffs = free->offset; | |
2329 | } | |
8b0036ee | 2330 | memcpy(chip->oob_poi + boffs, oob, bytes); |
8593fbc6 TG |
2331 | oob += bytes; |
2332 | } | |
2333 | return oob; | |
2334 | } | |
2335 | default: | |
2336 | BUG(); | |
2337 | } | |
2338 | return NULL; | |
2339 | } | |
2340 | ||
f8ac0414 | 2341 | #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) |
1da177e4 LT |
2342 | |
2343 | /** | |
7854d3f7 | 2344 | * nand_do_write_ops - [INTERN] NAND write with ECC |
8b6e50c9 BN |
2345 | * @mtd: MTD device structure |
2346 | * @to: offset to write to | |
2347 | * @ops: oob operations description structure | |
1da177e4 | 2348 | * |
8b6e50c9 | 2349 | * NAND write with ECC. |
1da177e4 | 2350 | */ |
8593fbc6 TG |
2351 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
2352 | struct mtd_oob_ops *ops) | |
1da177e4 | 2353 | { |
29072b96 | 2354 | int chipnr, realpage, page, blockmask, column; |
ace4dfee | 2355 | struct nand_chip *chip = mtd->priv; |
8593fbc6 | 2356 | uint32_t writelen = ops->len; |
782ce79a ML |
2357 | |
2358 | uint32_t oobwritelen = ops->ooblen; | |
0612b9dd | 2359 | uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ? |
782ce79a ML |
2360 | mtd->oobavail : mtd->oobsize; |
2361 | ||
8593fbc6 TG |
2362 | uint8_t *oob = ops->oobbuf; |
2363 | uint8_t *buf = ops->datbuf; | |
837a6ba4 | 2364 | int ret; |
e47f3db4 | 2365 | int oob_required = oob ? 1 : 0; |
1da177e4 | 2366 | |
8593fbc6 | 2367 | ops->retlen = 0; |
29072b96 TG |
2368 | if (!writelen) |
2369 | return 0; | |
1da177e4 | 2370 | |
8b6e50c9 | 2371 | /* Reject writes, which are not page aligned */ |
8593fbc6 | 2372 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
d0370219 BN |
2373 | pr_notice("%s: attempt to write non page aligned data\n", |
2374 | __func__); | |
1da177e4 LT |
2375 | return -EINVAL; |
2376 | } | |
2377 | ||
29072b96 | 2378 | column = to & (mtd->writesize - 1); |
1da177e4 | 2379 | |
6a930961 TG |
2380 | chipnr = (int)(to >> chip->chip_shift); |
2381 | chip->select_chip(mtd, chipnr); | |
2382 | ||
1da177e4 | 2383 | /* Check, if it is write protected */ |
b0bb6903 HS |
2384 | if (nand_check_wp(mtd)) { |
2385 | ret = -EIO; | |
2386 | goto err_out; | |
2387 | } | |
1da177e4 | 2388 | |
f75e5097 TG |
2389 | realpage = (int)(to >> chip->page_shift); |
2390 | page = realpage & chip->pagemask; | |
2391 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
2392 | ||
2393 | /* Invalidate the page cache, when we write to the cached page */ | |
2394 | if (to <= (chip->pagebuf << chip->page_shift) && | |
8593fbc6 | 2395 | (chip->pagebuf << chip->page_shift) < (to + ops->len)) |
ace4dfee | 2396 | chip->pagebuf = -1; |
61b03bd7 | 2397 | |
782ce79a | 2398 | /* Don't allow multipage oob writes with offset */ |
b0bb6903 HS |
2399 | if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { |
2400 | ret = -EINVAL; | |
2401 | goto err_out; | |
2402 | } | |
782ce79a | 2403 | |
f8ac0414 | 2404 | while (1) { |
29072b96 | 2405 | int bytes = mtd->writesize; |
f75e5097 | 2406 | int cached = writelen > bytes && page != blockmask; |
29072b96 | 2407 | uint8_t *wbuf = buf; |
66507c7b KD |
2408 | int use_bufpoi; |
2409 | int part_pagewr = (column || writelen < (mtd->writesize - 1)); | |
2410 | ||
2411 | if (part_pagewr) | |
2412 | use_bufpoi = 1; | |
2413 | else if (chip->options & NAND_USE_BOUNCE_BUFFER) | |
2414 | use_bufpoi = !virt_addr_valid(buf); | |
2415 | else | |
2416 | use_bufpoi = 0; | |
29072b96 | 2417 | |
66507c7b KD |
2418 | /* Partial page write?, or need to use bounce buffer */ |
2419 | if (use_bufpoi) { | |
2420 | pr_debug("%s: using write bounce buffer for buf@%p\n", | |
2421 | __func__, buf); | |
29072b96 | 2422 | cached = 0; |
66507c7b KD |
2423 | if (part_pagewr) |
2424 | bytes = min_t(int, bytes - column, writelen); | |
29072b96 TG |
2425 | chip->pagebuf = -1; |
2426 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
2427 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
2428 | wbuf = chip->buffers->databuf; | |
2429 | } | |
1da177e4 | 2430 | |
782ce79a ML |
2431 | if (unlikely(oob)) { |
2432 | size_t len = min(oobwritelen, oobmaxlen); | |
f722013e | 2433 | oob = nand_fill_oob(mtd, oob, len, ops); |
782ce79a | 2434 | oobwritelen -= len; |
f722013e TAA |
2435 | } else { |
2436 | /* We still need to erase leftover OOB data */ | |
2437 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
782ce79a | 2438 | } |
837a6ba4 GP |
2439 | ret = chip->write_page(mtd, chip, column, bytes, wbuf, |
2440 | oob_required, page, cached, | |
2441 | (ops->mode == MTD_OPS_RAW)); | |
f75e5097 TG |
2442 | if (ret) |
2443 | break; | |
2444 | ||
2445 | writelen -= bytes; | |
2446 | if (!writelen) | |
2447 | break; | |
2448 | ||
29072b96 | 2449 | column = 0; |
f75e5097 TG |
2450 | buf += bytes; |
2451 | realpage++; | |
2452 | ||
2453 | page = realpage & chip->pagemask; | |
2454 | /* Check, if we cross a chip boundary */ | |
2455 | if (!page) { | |
2456 | chipnr++; | |
2457 | chip->select_chip(mtd, -1); | |
2458 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2459 | } |
2460 | } | |
8593fbc6 | 2461 | |
8593fbc6 | 2462 | ops->retlen = ops->len - writelen; |
7014568b VW |
2463 | if (unlikely(oob)) |
2464 | ops->oobretlen = ops->ooblen; | |
b0bb6903 HS |
2465 | |
2466 | err_out: | |
2467 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
2468 | return ret; |
2469 | } | |
2470 | ||
2af7c653 SK |
2471 | /** |
2472 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
8b6e50c9 BN |
2473 | * @mtd: MTD device structure |
2474 | * @to: offset to write to | |
2475 | * @len: number of bytes to write | |
2476 | * @retlen: pointer to variable to store the number of written bytes | |
2477 | * @buf: the data to write | |
2af7c653 SK |
2478 | * |
2479 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
2480 | * may for example be called by mtdoops when writing an oops while in panic. | |
2481 | */ | |
2482 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
2483 | size_t *retlen, const uint8_t *buf) | |
2484 | { | |
2485 | struct nand_chip *chip = mtd->priv; | |
4a89ff88 | 2486 | struct mtd_oob_ops ops; |
2af7c653 SK |
2487 | int ret; |
2488 | ||
8b6e50c9 | 2489 | /* Wait for the device to get ready */ |
2af7c653 SK |
2490 | panic_nand_wait(mtd, chip, 400); |
2491 | ||
8b6e50c9 | 2492 | /* Grab the device */ |
2af7c653 SK |
2493 | panic_nand_get_device(chip, mtd, FL_WRITING); |
2494 | ||
4a89ff88 BN |
2495 | ops.len = len; |
2496 | ops.datbuf = (uint8_t *)buf; | |
2497 | ops.oobbuf = NULL; | |
11041ae6 | 2498 | ops.mode = MTD_OPS_PLACE_OOB; |
2af7c653 | 2499 | |
4a89ff88 | 2500 | ret = nand_do_write_ops(mtd, to, &ops); |
2af7c653 | 2501 | |
4a89ff88 | 2502 | *retlen = ops.retlen; |
2af7c653 SK |
2503 | return ret; |
2504 | } | |
2505 | ||
f75e5097 | 2506 | /** |
8593fbc6 | 2507 | * nand_write - [MTD Interface] NAND write with ECC |
8b6e50c9 BN |
2508 | * @mtd: MTD device structure |
2509 | * @to: offset to write to | |
2510 | * @len: number of bytes to write | |
2511 | * @retlen: pointer to variable to store the number of written bytes | |
2512 | * @buf: the data to write | |
f75e5097 | 2513 | * |
8b6e50c9 | 2514 | * NAND write with ECC. |
f75e5097 | 2515 | */ |
8593fbc6 TG |
2516 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
2517 | size_t *retlen, const uint8_t *buf) | |
f75e5097 | 2518 | { |
4a89ff88 | 2519 | struct mtd_oob_ops ops; |
f75e5097 TG |
2520 | int ret; |
2521 | ||
6a8214aa | 2522 | nand_get_device(mtd, FL_WRITING); |
4a89ff88 BN |
2523 | ops.len = len; |
2524 | ops.datbuf = (uint8_t *)buf; | |
2525 | ops.oobbuf = NULL; | |
11041ae6 | 2526 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 2527 | ret = nand_do_write_ops(mtd, to, &ops); |
4a89ff88 | 2528 | *retlen = ops.retlen; |
f75e5097 | 2529 | nand_release_device(mtd); |
8593fbc6 | 2530 | return ret; |
f75e5097 | 2531 | } |
7314e9e7 | 2532 | |
1da177e4 | 2533 | /** |
8593fbc6 | 2534 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
8b6e50c9 BN |
2535 | * @mtd: MTD device structure |
2536 | * @to: offset to write to | |
2537 | * @ops: oob operation description structure | |
1da177e4 | 2538 | * |
8b6e50c9 | 2539 | * NAND write out-of-band. |
1da177e4 | 2540 | */ |
8593fbc6 TG |
2541 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
2542 | struct mtd_oob_ops *ops) | |
1da177e4 | 2543 | { |
03736155 | 2544 | int chipnr, page, status, len; |
ace4dfee | 2545 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2546 | |
289c0522 | 2547 | pr_debug("%s: to = 0x%08x, len = %i\n", |
20d8e248 | 2548 | __func__, (unsigned int)to, (int)ops->ooblen); |
1da177e4 | 2549 | |
0612b9dd | 2550 | if (ops->mode == MTD_OPS_AUTO_OOB) |
03736155 AH |
2551 | len = chip->ecc.layout->oobavail; |
2552 | else | |
2553 | len = mtd->oobsize; | |
2554 | ||
1da177e4 | 2555 | /* Do not allow write past end of page */ |
03736155 | 2556 | if ((ops->ooboffs + ops->ooblen) > len) { |
289c0522 BN |
2557 | pr_debug("%s: attempt to write past end of page\n", |
2558 | __func__); | |
1da177e4 LT |
2559 | return -EINVAL; |
2560 | } | |
2561 | ||
03736155 | 2562 | if (unlikely(ops->ooboffs >= len)) { |
289c0522 BN |
2563 | pr_debug("%s: attempt to start write outside oob\n", |
2564 | __func__); | |
03736155 AH |
2565 | return -EINVAL; |
2566 | } | |
2567 | ||
775adc3d | 2568 | /* Do not allow write past end of device */ |
03736155 AH |
2569 | if (unlikely(to >= mtd->size || |
2570 | ops->ooboffs + ops->ooblen > | |
2571 | ((mtd->size >> chip->page_shift) - | |
2572 | (to >> chip->page_shift)) * len)) { | |
289c0522 BN |
2573 | pr_debug("%s: attempt to write beyond end of device\n", |
2574 | __func__); | |
03736155 AH |
2575 | return -EINVAL; |
2576 | } | |
2577 | ||
7314e9e7 | 2578 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 2579 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2580 | |
7314e9e7 TG |
2581 | /* Shift to get page */ |
2582 | page = (int)(to >> chip->page_shift); | |
2583 | ||
2584 | /* | |
2585 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
2586 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
2587 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
2588 | * it in the doc2000 driver in August 1999. dwmw2. | |
2589 | */ | |
ace4dfee | 2590 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
2591 | |
2592 | /* Check, if it is write protected */ | |
b0bb6903 HS |
2593 | if (nand_check_wp(mtd)) { |
2594 | chip->select_chip(mtd, -1); | |
8593fbc6 | 2595 | return -EROFS; |
b0bb6903 | 2596 | } |
61b03bd7 | 2597 | |
1da177e4 | 2598 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
2599 | if (page == chip->pagebuf) |
2600 | chip->pagebuf = -1; | |
1da177e4 | 2601 | |
f722013e | 2602 | nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops); |
9ce244b3 | 2603 | |
0612b9dd | 2604 | if (ops->mode == MTD_OPS_RAW) |
9ce244b3 BN |
2605 | status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask); |
2606 | else | |
2607 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); | |
1da177e4 | 2608 | |
b0bb6903 HS |
2609 | chip->select_chip(mtd, -1); |
2610 | ||
7bc3312b TG |
2611 | if (status) |
2612 | return status; | |
1da177e4 | 2613 | |
7014568b | 2614 | ops->oobretlen = ops->ooblen; |
1da177e4 | 2615 | |
7bc3312b | 2616 | return 0; |
8593fbc6 TG |
2617 | } |
2618 | ||
2619 | /** | |
2620 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
8b6e50c9 BN |
2621 | * @mtd: MTD device structure |
2622 | * @to: offset to write to | |
2623 | * @ops: oob operation description structure | |
8593fbc6 TG |
2624 | */ |
2625 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
2626 | struct mtd_oob_ops *ops) | |
2627 | { | |
8593fbc6 TG |
2628 | int ret = -ENOTSUPP; |
2629 | ||
2630 | ops->retlen = 0; | |
2631 | ||
2632 | /* Do not allow writes past end of device */ | |
7014568b | 2633 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
289c0522 BN |
2634 | pr_debug("%s: attempt to write beyond end of device\n", |
2635 | __func__); | |
8593fbc6 TG |
2636 | return -EINVAL; |
2637 | } | |
2638 | ||
6a8214aa | 2639 | nand_get_device(mtd, FL_WRITING); |
8593fbc6 | 2640 | |
f8ac0414 | 2641 | switch (ops->mode) { |
0612b9dd BN |
2642 | case MTD_OPS_PLACE_OOB: |
2643 | case MTD_OPS_AUTO_OOB: | |
2644 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2645 | break; |
2646 | ||
2647 | default: | |
2648 | goto out; | |
2649 | } | |
2650 | ||
2651 | if (!ops->datbuf) | |
2652 | ret = nand_do_write_oob(mtd, to, ops); | |
2653 | else | |
2654 | ret = nand_do_write_ops(mtd, to, ops); | |
2655 | ||
7351d3a5 | 2656 | out: |
1da177e4 | 2657 | nand_release_device(mtd); |
1da177e4 LT |
2658 | return ret; |
2659 | } | |
2660 | ||
1da177e4 | 2661 | /** |
49c50b97 | 2662 | * single_erase - [GENERIC] NAND standard block erase command function |
8b6e50c9 BN |
2663 | * @mtd: MTD device structure |
2664 | * @page: the page address of the block which will be erased | |
1da177e4 | 2665 | * |
49c50b97 | 2666 | * Standard erase command for NAND chips. Returns NAND status. |
1da177e4 | 2667 | */ |
49c50b97 | 2668 | static int single_erase(struct mtd_info *mtd, int page) |
1da177e4 | 2669 | { |
ace4dfee | 2670 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2671 | /* Send commands to erase a block */ |
ace4dfee TG |
2672 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
2673 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
49c50b97 BN |
2674 | |
2675 | return chip->waitfunc(mtd, chip); | |
1da177e4 LT |
2676 | } |
2677 | ||
1da177e4 LT |
2678 | /** |
2679 | * nand_erase - [MTD Interface] erase block(s) | |
8b6e50c9 BN |
2680 | * @mtd: MTD device structure |
2681 | * @instr: erase instruction | |
1da177e4 | 2682 | * |
8b6e50c9 | 2683 | * Erase one ore more blocks. |
1da177e4 | 2684 | */ |
e0c7d767 | 2685 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 2686 | { |
e0c7d767 | 2687 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 2688 | } |
61b03bd7 | 2689 | |
1da177e4 | 2690 | /** |
7854d3f7 | 2691 | * nand_erase_nand - [INTERN] erase block(s) |
8b6e50c9 BN |
2692 | * @mtd: MTD device structure |
2693 | * @instr: erase instruction | |
2694 | * @allowbbt: allow erasing the bbt area | |
1da177e4 | 2695 | * |
8b6e50c9 | 2696 | * Erase one ore more blocks. |
1da177e4 | 2697 | */ |
ace4dfee TG |
2698 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
2699 | int allowbbt) | |
1da177e4 | 2700 | { |
69423d99 | 2701 | int page, status, pages_per_block, ret, chipnr; |
ace4dfee | 2702 | struct nand_chip *chip = mtd->priv; |
69423d99 | 2703 | loff_t len; |
1da177e4 | 2704 | |
289c0522 BN |
2705 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
2706 | __func__, (unsigned long long)instr->addr, | |
2707 | (unsigned long long)instr->len); | |
1da177e4 | 2708 | |
6fe5a6ac | 2709 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 2710 | return -EINVAL; |
1da177e4 | 2711 | |
1da177e4 | 2712 | /* Grab the lock and see if the device is available */ |
6a8214aa | 2713 | nand_get_device(mtd, FL_ERASING); |
1da177e4 LT |
2714 | |
2715 | /* Shift to get first page */ | |
ace4dfee TG |
2716 | page = (int)(instr->addr >> chip->page_shift); |
2717 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
2718 | |
2719 | /* Calculate pages in each block */ | |
ace4dfee | 2720 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
2721 | |
2722 | /* Select the NAND device */ | |
ace4dfee | 2723 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2724 | |
1da177e4 LT |
2725 | /* Check, if it is write protected */ |
2726 | if (nand_check_wp(mtd)) { | |
289c0522 BN |
2727 | pr_debug("%s: device is write protected!\n", |
2728 | __func__); | |
1da177e4 LT |
2729 | instr->state = MTD_ERASE_FAILED; |
2730 | goto erase_exit; | |
2731 | } | |
2732 | ||
2733 | /* Loop through the pages */ | |
2734 | len = instr->len; | |
2735 | ||
2736 | instr->state = MTD_ERASING; | |
2737 | ||
2738 | while (len) { | |
12183a20 | 2739 | /* Check if we have a bad block, we do not erase bad blocks! */ |
ace4dfee TG |
2740 | if (nand_block_checkbad(mtd, ((loff_t) page) << |
2741 | chip->page_shift, 0, allowbbt)) { | |
d0370219 BN |
2742 | pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", |
2743 | __func__, page); | |
1da177e4 LT |
2744 | instr->state = MTD_ERASE_FAILED; |
2745 | goto erase_exit; | |
2746 | } | |
61b03bd7 | 2747 | |
ace4dfee TG |
2748 | /* |
2749 | * Invalidate the page cache, if we erase the block which | |
8b6e50c9 | 2750 | * contains the current cached page. |
ace4dfee TG |
2751 | */ |
2752 | if (page <= chip->pagebuf && chip->pagebuf < | |
2753 | (page + pages_per_block)) | |
2754 | chip->pagebuf = -1; | |
1da177e4 | 2755 | |
49c50b97 | 2756 | status = chip->erase(mtd, page & chip->pagemask); |
1da177e4 | 2757 | |
ace4dfee TG |
2758 | /* |
2759 | * See if operation failed and additional status checks are | |
2760 | * available | |
2761 | */ | |
2762 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2763 | status = chip->errstat(mtd, chip, FL_ERASING, | |
2764 | status, page); | |
068e3c0a | 2765 | |
1da177e4 | 2766 | /* See if block erase succeeded */ |
a4ab4c5d | 2767 | if (status & NAND_STATUS_FAIL) { |
289c0522 BN |
2768 | pr_debug("%s: failed erase, page 0x%08x\n", |
2769 | __func__, page); | |
1da177e4 | 2770 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
2771 | instr->fail_addr = |
2772 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
2773 | goto erase_exit; |
2774 | } | |
30f464b7 | 2775 | |
1da177e4 | 2776 | /* Increment page address and decrement length */ |
daae74ca | 2777 | len -= (1ULL << chip->phys_erase_shift); |
1da177e4 LT |
2778 | page += pages_per_block; |
2779 | ||
2780 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 2781 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 2782 | chipnr++; |
ace4dfee TG |
2783 | chip->select_chip(mtd, -1); |
2784 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2785 | } |
2786 | } | |
2787 | instr->state = MTD_ERASE_DONE; | |
2788 | ||
7351d3a5 | 2789 | erase_exit: |
1da177e4 LT |
2790 | |
2791 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
2792 | |
2793 | /* Deselect and wake up anyone waiting on the device */ | |
b0bb6903 | 2794 | chip->select_chip(mtd, -1); |
1da177e4 LT |
2795 | nand_release_device(mtd); |
2796 | ||
49defc01 DW |
2797 | /* Do call back function */ |
2798 | if (!ret) | |
2799 | mtd_erase_callback(instr); | |
2800 | ||
1da177e4 LT |
2801 | /* Return more or less happy */ |
2802 | return ret; | |
2803 | } | |
2804 | ||
2805 | /** | |
2806 | * nand_sync - [MTD Interface] sync | |
8b6e50c9 | 2807 | * @mtd: MTD device structure |
1da177e4 | 2808 | * |
8b6e50c9 | 2809 | * Sync is actually a wait for chip ready function. |
1da177e4 | 2810 | */ |
e0c7d767 | 2811 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 2812 | { |
289c0522 | 2813 | pr_debug("%s: called\n", __func__); |
1da177e4 LT |
2814 | |
2815 | /* Grab the lock and see if the device is available */ | |
6a8214aa | 2816 | nand_get_device(mtd, FL_SYNCING); |
1da177e4 | 2817 | /* Release it and go back */ |
e0c7d767 | 2818 | nand_release_device(mtd); |
1da177e4 LT |
2819 | } |
2820 | ||
1da177e4 | 2821 | /** |
ace4dfee | 2822 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
8b6e50c9 BN |
2823 | * @mtd: MTD device structure |
2824 | * @offs: offset relative to mtd start | |
1da177e4 | 2825 | */ |
ace4dfee | 2826 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 | 2827 | { |
ace4dfee | 2828 | return nand_block_checkbad(mtd, offs, 1, 0); |
1da177e4 LT |
2829 | } |
2830 | ||
2831 | /** | |
ace4dfee | 2832 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
8b6e50c9 BN |
2833 | * @mtd: MTD device structure |
2834 | * @ofs: offset relative to mtd start | |
1da177e4 | 2835 | */ |
e0c7d767 | 2836 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 2837 | { |
1da177e4 LT |
2838 | int ret; |
2839 | ||
f8ac0414 FF |
2840 | ret = nand_block_isbad(mtd, ofs); |
2841 | if (ret) { | |
8b6e50c9 | 2842 | /* If it was bad already, return success and do nothing */ |
1da177e4 LT |
2843 | if (ret > 0) |
2844 | return 0; | |
e0c7d767 DW |
2845 | return ret; |
2846 | } | |
1da177e4 | 2847 | |
5a0edb25 | 2848 | return nand_block_markbad_lowlevel(mtd, ofs); |
1da177e4 LT |
2849 | } |
2850 | ||
7db03ecc HS |
2851 | /** |
2852 | * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand | |
2853 | * @mtd: MTD device structure | |
2854 | * @chip: nand chip info structure | |
2855 | * @addr: feature address. | |
2856 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
2857 | */ | |
2858 | static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, | |
2859 | int addr, uint8_t *subfeature_param) | |
2860 | { | |
2861 | int status; | |
05f78359 | 2862 | int i; |
7db03ecc | 2863 | |
d914c932 DM |
2864 | if (!chip->onfi_version || |
2865 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
2866 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
2867 | return -EINVAL; |
2868 | ||
2869 | chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1); | |
05f78359 UKK |
2870 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
2871 | chip->write_byte(mtd, subfeature_param[i]); | |
2872 | ||
7db03ecc HS |
2873 | status = chip->waitfunc(mtd, chip); |
2874 | if (status & NAND_STATUS_FAIL) | |
2875 | return -EIO; | |
2876 | return 0; | |
2877 | } | |
2878 | ||
2879 | /** | |
2880 | * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand | |
2881 | * @mtd: MTD device structure | |
2882 | * @chip: nand chip info structure | |
2883 | * @addr: feature address. | |
2884 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
2885 | */ | |
2886 | static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, | |
2887 | int addr, uint8_t *subfeature_param) | |
2888 | { | |
05f78359 UKK |
2889 | int i; |
2890 | ||
d914c932 DM |
2891 | if (!chip->onfi_version || |
2892 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
2893 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
2894 | return -EINVAL; |
2895 | ||
2896 | /* clear the sub feature parameters */ | |
2897 | memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN); | |
2898 | ||
2899 | chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1); | |
05f78359 UKK |
2900 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
2901 | *subfeature_param++ = chip->read_byte(mtd); | |
7db03ecc HS |
2902 | return 0; |
2903 | } | |
2904 | ||
962034f4 VW |
2905 | /** |
2906 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
8b6e50c9 | 2907 | * @mtd: MTD device structure |
962034f4 VW |
2908 | */ |
2909 | static int nand_suspend(struct mtd_info *mtd) | |
2910 | { | |
6a8214aa | 2911 | return nand_get_device(mtd, FL_PM_SUSPENDED); |
962034f4 VW |
2912 | } |
2913 | ||
2914 | /** | |
2915 | * nand_resume - [MTD Interface] Resume the NAND flash | |
8b6e50c9 | 2916 | * @mtd: MTD device structure |
962034f4 VW |
2917 | */ |
2918 | static void nand_resume(struct mtd_info *mtd) | |
2919 | { | |
ace4dfee | 2920 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2921 | |
ace4dfee | 2922 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
2923 | nand_release_device(mtd); |
2924 | else | |
d0370219 BN |
2925 | pr_err("%s called for a chip which is not in suspended state\n", |
2926 | __func__); | |
962034f4 VW |
2927 | } |
2928 | ||
8b6e50c9 | 2929 | /* Set default functions */ |
ace4dfee | 2930 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 2931 | { |
1da177e4 | 2932 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
2933 | if (!chip->chip_delay) |
2934 | chip->chip_delay = 20; | |
1da177e4 LT |
2935 | |
2936 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
2937 | if (chip->cmdfunc == NULL) |
2938 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
2939 | |
2940 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
2941 | if (chip->waitfunc == NULL) |
2942 | chip->waitfunc = nand_wait; | |
2943 | ||
2944 | if (!chip->select_chip) | |
2945 | chip->select_chip = nand_select_chip; | |
68e80780 | 2946 | |
4204cccd HS |
2947 | /* set for ONFI nand */ |
2948 | if (!chip->onfi_set_features) | |
2949 | chip->onfi_set_features = nand_onfi_set_features; | |
2950 | if (!chip->onfi_get_features) | |
2951 | chip->onfi_get_features = nand_onfi_get_features; | |
2952 | ||
68e80780 BN |
2953 | /* If called twice, pointers that depend on busw may need to be reset */ |
2954 | if (!chip->read_byte || chip->read_byte == nand_read_byte) | |
ace4dfee TG |
2955 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; |
2956 | if (!chip->read_word) | |
2957 | chip->read_word = nand_read_word; | |
2958 | if (!chip->block_bad) | |
2959 | chip->block_bad = nand_block_bad; | |
2960 | if (!chip->block_markbad) | |
2961 | chip->block_markbad = nand_default_block_markbad; | |
68e80780 | 2962 | if (!chip->write_buf || chip->write_buf == nand_write_buf) |
ace4dfee | 2963 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; |
05f78359 UKK |
2964 | if (!chip->write_byte || chip->write_byte == nand_write_byte) |
2965 | chip->write_byte = busw ? nand_write_byte16 : nand_write_byte; | |
68e80780 | 2966 | if (!chip->read_buf || chip->read_buf == nand_read_buf) |
ace4dfee | 2967 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; |
ace4dfee TG |
2968 | if (!chip->scan_bbt) |
2969 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
2970 | |
2971 | if (!chip->controller) { | |
2972 | chip->controller = &chip->hwcontrol; | |
2973 | spin_lock_init(&chip->controller->lock); | |
2974 | init_waitqueue_head(&chip->controller->wq); | |
2975 | } | |
2976 | ||
7aa65bfd TG |
2977 | } |
2978 | ||
8b6e50c9 | 2979 | /* Sanitize ONFI strings so we can safely print them */ |
d1e1f4e4 FF |
2980 | static void sanitize_string(uint8_t *s, size_t len) |
2981 | { | |
2982 | ssize_t i; | |
2983 | ||
8b6e50c9 | 2984 | /* Null terminate */ |
d1e1f4e4 FF |
2985 | s[len - 1] = 0; |
2986 | ||
8b6e50c9 | 2987 | /* Remove non printable chars */ |
d1e1f4e4 FF |
2988 | for (i = 0; i < len - 1; i++) { |
2989 | if (s[i] < ' ' || s[i] > 127) | |
2990 | s[i] = '?'; | |
2991 | } | |
2992 | ||
8b6e50c9 | 2993 | /* Remove trailing spaces */ |
d1e1f4e4 FF |
2994 | strim(s); |
2995 | } | |
2996 | ||
2997 | static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) | |
2998 | { | |
2999 | int i; | |
3000 | while (len--) { | |
3001 | crc ^= *p++ << 8; | |
3002 | for (i = 0; i < 8; i++) | |
3003 | crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); | |
3004 | } | |
3005 | ||
3006 | return crc; | |
3007 | } | |
3008 | ||
6dcbe0cd HS |
3009 | /* Parse the Extended Parameter Page. */ |
3010 | static int nand_flash_detect_ext_param_page(struct mtd_info *mtd, | |
3011 | struct nand_chip *chip, struct nand_onfi_params *p) | |
3012 | { | |
3013 | struct onfi_ext_param_page *ep; | |
3014 | struct onfi_ext_section *s; | |
3015 | struct onfi_ext_ecc_info *ecc; | |
3016 | uint8_t *cursor; | |
3017 | int ret = -EINVAL; | |
3018 | int len; | |
3019 | int i; | |
3020 | ||
3021 | len = le16_to_cpu(p->ext_param_page_length) * 16; | |
3022 | ep = kmalloc(len, GFP_KERNEL); | |
5cb13271 BN |
3023 | if (!ep) |
3024 | return -ENOMEM; | |
6dcbe0cd HS |
3025 | |
3026 | /* Send our own NAND_CMD_PARAM. */ | |
3027 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); | |
3028 | ||
3029 | /* Use the Change Read Column command to skip the ONFI param pages. */ | |
3030 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, | |
3031 | sizeof(*p) * p->num_of_param_pages , -1); | |
3032 | ||
3033 | /* Read out the Extended Parameter Page. */ | |
3034 | chip->read_buf(mtd, (uint8_t *)ep, len); | |
3035 | if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2) | |
3036 | != le16_to_cpu(ep->crc))) { | |
3037 | pr_debug("fail in the CRC.\n"); | |
3038 | goto ext_out; | |
3039 | } | |
3040 | ||
3041 | /* | |
3042 | * Check the signature. | |
3043 | * Do not strictly follow the ONFI spec, maybe changed in future. | |
3044 | */ | |
3045 | if (strncmp(ep->sig, "EPPS", 4)) { | |
3046 | pr_debug("The signature is invalid.\n"); | |
3047 | goto ext_out; | |
3048 | } | |
3049 | ||
3050 | /* find the ECC section. */ | |
3051 | cursor = (uint8_t *)(ep + 1); | |
3052 | for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) { | |
3053 | s = ep->sections + i; | |
3054 | if (s->type == ONFI_SECTION_TYPE_2) | |
3055 | break; | |
3056 | cursor += s->length * 16; | |
3057 | } | |
3058 | if (i == ONFI_EXT_SECTION_MAX) { | |
3059 | pr_debug("We can not find the ECC section.\n"); | |
3060 | goto ext_out; | |
3061 | } | |
3062 | ||
3063 | /* get the info we want. */ | |
3064 | ecc = (struct onfi_ext_ecc_info *)cursor; | |
3065 | ||
4ae7d228 BN |
3066 | if (!ecc->codeword_size) { |
3067 | pr_debug("Invalid codeword size\n"); | |
3068 | goto ext_out; | |
6dcbe0cd HS |
3069 | } |
3070 | ||
4ae7d228 BN |
3071 | chip->ecc_strength_ds = ecc->ecc_bits; |
3072 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
5cb13271 | 3073 | ret = 0; |
6dcbe0cd HS |
3074 | |
3075 | ext_out: | |
3076 | kfree(ep); | |
3077 | return ret; | |
3078 | } | |
3079 | ||
8429bb39 BN |
3080 | static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode) |
3081 | { | |
3082 | struct nand_chip *chip = mtd->priv; | |
3083 | uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; | |
3084 | ||
3085 | return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, | |
3086 | feature); | |
3087 | } | |
3088 | ||
3089 | /* | |
3090 | * Configure chip properties from Micron vendor-specific ONFI table | |
3091 | */ | |
3092 | static void nand_onfi_detect_micron(struct nand_chip *chip, | |
3093 | struct nand_onfi_params *p) | |
3094 | { | |
3095 | struct nand_onfi_vendor_micron *micron = (void *)p->vendor; | |
3096 | ||
3097 | if (le16_to_cpu(p->vendor_revision) < 1) | |
3098 | return; | |
3099 | ||
3100 | chip->read_retries = micron->read_retry_options; | |
3101 | chip->setup_read_retry = nand_setup_read_retry_micron; | |
3102 | } | |
3103 | ||
6fb277ba | 3104 | /* |
8b6e50c9 | 3105 | * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. |
6fb277ba FF |
3106 | */ |
3107 | static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, | |
08c248fb | 3108 | int *busw) |
6fb277ba FF |
3109 | { |
3110 | struct nand_onfi_params *p = &chip->onfi_params; | |
bd9c6e99 | 3111 | int i, j; |
6fb277ba FF |
3112 | int val; |
3113 | ||
7854d3f7 | 3114 | /* Try ONFI for unknown chip or LP */ |
6fb277ba FF |
3115 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); |
3116 | if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || | |
3117 | chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') | |
3118 | return 0; | |
3119 | ||
6fb277ba FF |
3120 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); |
3121 | for (i = 0; i < 3; i++) { | |
bd9c6e99 BN |
3122 | for (j = 0; j < sizeof(*p); j++) |
3123 | ((uint8_t *)p)[j] = chip->read_byte(mtd); | |
6fb277ba FF |
3124 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == |
3125 | le16_to_cpu(p->crc)) { | |
6fb277ba FF |
3126 | break; |
3127 | } | |
3128 | } | |
3129 | ||
c7f23a70 BN |
3130 | if (i == 3) { |
3131 | pr_err("Could not find valid ONFI parameter page; aborting\n"); | |
6fb277ba | 3132 | return 0; |
c7f23a70 | 3133 | } |
6fb277ba | 3134 | |
8b6e50c9 | 3135 | /* Check version */ |
6fb277ba | 3136 | val = le16_to_cpu(p->revision); |
b7b1a29d BN |
3137 | if (val & (1 << 5)) |
3138 | chip->onfi_version = 23; | |
3139 | else if (val & (1 << 4)) | |
6fb277ba FF |
3140 | chip->onfi_version = 22; |
3141 | else if (val & (1 << 3)) | |
3142 | chip->onfi_version = 21; | |
3143 | else if (val & (1 << 2)) | |
3144 | chip->onfi_version = 20; | |
b7b1a29d | 3145 | else if (val & (1 << 1)) |
6fb277ba | 3146 | chip->onfi_version = 10; |
b7b1a29d BN |
3147 | |
3148 | if (!chip->onfi_version) { | |
20171642 | 3149 | pr_info("unsupported ONFI version: %d\n", val); |
b7b1a29d BN |
3150 | return 0; |
3151 | } | |
6fb277ba FF |
3152 | |
3153 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3154 | sanitize_string(p->model, sizeof(p->model)); | |
3155 | if (!mtd->name) | |
3156 | mtd->name = p->model; | |
4355b70c | 3157 | |
6fb277ba | 3158 | mtd->writesize = le32_to_cpu(p->byte_per_page); |
4355b70c BN |
3159 | |
3160 | /* | |
3161 | * pages_per_block and blocks_per_lun may not be a power-of-2 size | |
3162 | * (don't ask me who thought of this...). MTD assumes that these | |
3163 | * dimensions will be power-of-2, so just truncate the remaining area. | |
3164 | */ | |
3165 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3166 | mtd->erasesize *= mtd->writesize; | |
3167 | ||
6fb277ba | 3168 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); |
4355b70c BN |
3169 | |
3170 | /* See erasesize comment */ | |
3171 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
63795755 | 3172 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; |
13fbd179 | 3173 | chip->bits_per_cell = p->bits_per_cell; |
e2985fc1 HS |
3174 | |
3175 | if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) | |
08c248fb | 3176 | *busw = NAND_BUSWIDTH_16; |
e2985fc1 HS |
3177 | else |
3178 | *busw = 0; | |
6fb277ba | 3179 | |
10c86bab HS |
3180 | if (p->ecc_bits != 0xff) { |
3181 | chip->ecc_strength_ds = p->ecc_bits; | |
3182 | chip->ecc_step_ds = 512; | |
6dcbe0cd HS |
3183 | } else if (chip->onfi_version >= 21 && |
3184 | (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) { | |
3185 | ||
3186 | /* | |
3187 | * The nand_flash_detect_ext_param_page() uses the | |
3188 | * Change Read Column command which maybe not supported | |
3189 | * by the chip->cmdfunc. So try to update the chip->cmdfunc | |
3190 | * now. We do not replace user supplied command function. | |
3191 | */ | |
3192 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) | |
3193 | chip->cmdfunc = nand_command_lp; | |
3194 | ||
3195 | /* The Extended Parameter Page is supported since ONFI 2.1. */ | |
3196 | if (nand_flash_detect_ext_param_page(mtd, chip, p)) | |
c7f23a70 BN |
3197 | pr_warn("Failed to detect ONFI extended param page\n"); |
3198 | } else { | |
3199 | pr_warn("Could not retrieve ONFI ECC requirements\n"); | |
10c86bab HS |
3200 | } |
3201 | ||
8429bb39 BN |
3202 | if (p->jedec_id == NAND_MFR_MICRON) |
3203 | nand_onfi_detect_micron(chip, p); | |
3204 | ||
6fb277ba FF |
3205 | return 1; |
3206 | } | |
3207 | ||
91361818 HS |
3208 | /* |
3209 | * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise. | |
3210 | */ | |
3211 | static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip, | |
3212 | int *busw) | |
3213 | { | |
3214 | struct nand_jedec_params *p = &chip->jedec_params; | |
3215 | struct jedec_ecc_info *ecc; | |
3216 | int val; | |
3217 | int i, j; | |
3218 | ||
3219 | /* Try JEDEC for unknown chip or LP */ | |
3220 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1); | |
3221 | if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' || | |
3222 | chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' || | |
3223 | chip->read_byte(mtd) != 'C') | |
3224 | return 0; | |
3225 | ||
3226 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1); | |
3227 | for (i = 0; i < 3; i++) { | |
3228 | for (j = 0; j < sizeof(*p); j++) | |
3229 | ((uint8_t *)p)[j] = chip->read_byte(mtd); | |
3230 | ||
3231 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) == | |
3232 | le16_to_cpu(p->crc)) | |
3233 | break; | |
3234 | } | |
3235 | ||
3236 | if (i == 3) { | |
3237 | pr_err("Could not find valid JEDEC parameter page; aborting\n"); | |
3238 | return 0; | |
3239 | } | |
3240 | ||
3241 | /* Check version */ | |
3242 | val = le16_to_cpu(p->revision); | |
3243 | if (val & (1 << 2)) | |
3244 | chip->jedec_version = 10; | |
3245 | else if (val & (1 << 1)) | |
3246 | chip->jedec_version = 1; /* vendor specific version */ | |
3247 | ||
3248 | if (!chip->jedec_version) { | |
3249 | pr_info("unsupported JEDEC version: %d\n", val); | |
3250 | return 0; | |
3251 | } | |
3252 | ||
3253 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3254 | sanitize_string(p->model, sizeof(p->model)); | |
3255 | if (!mtd->name) | |
3256 | mtd->name = p->model; | |
3257 | ||
3258 | mtd->writesize = le32_to_cpu(p->byte_per_page); | |
3259 | ||
3260 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
3261 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3262 | mtd->erasesize *= mtd->writesize; | |
3263 | ||
3264 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); | |
3265 | ||
3266 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
3267 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
3268 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; | |
3269 | chip->bits_per_cell = p->bits_per_cell; | |
3270 | ||
3271 | if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS) | |
3272 | *busw = NAND_BUSWIDTH_16; | |
3273 | else | |
3274 | *busw = 0; | |
3275 | ||
3276 | /* ECC info */ | |
3277 | ecc = &p->ecc_info[0]; | |
3278 | ||
3279 | if (ecc->codeword_size >= 9) { | |
3280 | chip->ecc_strength_ds = ecc->ecc_bits; | |
3281 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
3282 | } else { | |
3283 | pr_warn("Invalid codeword size\n"); | |
3284 | } | |
3285 | ||
3286 | return 1; | |
3287 | } | |
3288 | ||
e3b88bd6 BN |
3289 | /* |
3290 | * nand_id_has_period - Check if an ID string has a given wraparound period | |
3291 | * @id_data: the ID string | |
3292 | * @arrlen: the length of the @id_data array | |
3293 | * @period: the period of repitition | |
3294 | * | |
3295 | * Check if an ID string is repeated within a given sequence of bytes at | |
3296 | * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a | |
d4d4f1bf | 3297 | * period of 3). This is a helper function for nand_id_len(). Returns non-zero |
e3b88bd6 BN |
3298 | * if the repetition has a period of @period; otherwise, returns zero. |
3299 | */ | |
3300 | static int nand_id_has_period(u8 *id_data, int arrlen, int period) | |
3301 | { | |
3302 | int i, j; | |
3303 | for (i = 0; i < period; i++) | |
3304 | for (j = i + period; j < arrlen; j += period) | |
3305 | if (id_data[i] != id_data[j]) | |
3306 | return 0; | |
3307 | return 1; | |
3308 | } | |
3309 | ||
3310 | /* | |
3311 | * nand_id_len - Get the length of an ID string returned by CMD_READID | |
3312 | * @id_data: the ID string | |
3313 | * @arrlen: the length of the @id_data array | |
3314 | ||
3315 | * Returns the length of the ID string, according to known wraparound/trailing | |
3316 | * zero patterns. If no pattern exists, returns the length of the array. | |
3317 | */ | |
3318 | static int nand_id_len(u8 *id_data, int arrlen) | |
3319 | { | |
3320 | int last_nonzero, period; | |
3321 | ||
3322 | /* Find last non-zero byte */ | |
3323 | for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) | |
3324 | if (id_data[last_nonzero]) | |
3325 | break; | |
3326 | ||
3327 | /* All zeros */ | |
3328 | if (last_nonzero < 0) | |
3329 | return 0; | |
3330 | ||
3331 | /* Calculate wraparound period */ | |
3332 | for (period = 1; period < arrlen; period++) | |
3333 | if (nand_id_has_period(id_data, arrlen, period)) | |
3334 | break; | |
3335 | ||
3336 | /* There's a repeated pattern */ | |
3337 | if (period < arrlen) | |
3338 | return period; | |
3339 | ||
3340 | /* There are trailing zeros */ | |
3341 | if (last_nonzero < arrlen - 1) | |
3342 | return last_nonzero + 1; | |
3343 | ||
3344 | /* No pattern detected */ | |
3345 | return arrlen; | |
3346 | } | |
3347 | ||
7db906b7 HS |
3348 | /* Extract the bits of per cell from the 3rd byte of the extended ID */ |
3349 | static int nand_get_bits_per_cell(u8 cellinfo) | |
3350 | { | |
3351 | int bits; | |
3352 | ||
3353 | bits = cellinfo & NAND_CI_CELLTYPE_MSK; | |
3354 | bits >>= NAND_CI_CELLTYPE_SHIFT; | |
3355 | return bits + 1; | |
3356 | } | |
3357 | ||
fc09bbc0 BN |
3358 | /* |
3359 | * Many new NAND share similar device ID codes, which represent the size of the | |
3360 | * chip. The rest of the parameters must be decoded according to generic or | |
3361 | * manufacturer-specific "extended ID" decoding patterns. | |
3362 | */ | |
3363 | static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, | |
3364 | u8 id_data[8], int *busw) | |
3365 | { | |
e3b88bd6 | 3366 | int extid, id_len; |
fc09bbc0 | 3367 | /* The 3rd id byte holds MLC / multichip data */ |
7db906b7 | 3368 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
fc09bbc0 BN |
3369 | /* The 4th id byte is the important one */ |
3370 | extid = id_data[3]; | |
3371 | ||
e3b88bd6 BN |
3372 | id_len = nand_id_len(id_data, 8); |
3373 | ||
fc09bbc0 BN |
3374 | /* |
3375 | * Field definitions are in the following datasheets: | |
3376 | * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) | |
af451af4 | 3377 | * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) |
73ca392f | 3378 | * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) |
fc09bbc0 | 3379 | * |
af451af4 BN |
3380 | * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung |
3381 | * ID to decide what to do. | |
fc09bbc0 | 3382 | */ |
af451af4 | 3383 | if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && |
1d0ed69d | 3384 | !nand_is_slc(chip) && id_data[5] != 0x00) { |
fc09bbc0 BN |
3385 | /* Calc pagesize */ |
3386 | mtd->writesize = 2048 << (extid & 0x03); | |
3387 | extid >>= 2; | |
3388 | /* Calc oobsize */ | |
e2d3a35e | 3389 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { |
fc09bbc0 BN |
3390 | case 1: |
3391 | mtd->oobsize = 128; | |
3392 | break; | |
3393 | case 2: | |
3394 | mtd->oobsize = 218; | |
3395 | break; | |
3396 | case 3: | |
3397 | mtd->oobsize = 400; | |
3398 | break; | |
e2d3a35e | 3399 | case 4: |
fc09bbc0 BN |
3400 | mtd->oobsize = 436; |
3401 | break; | |
e2d3a35e BN |
3402 | case 5: |
3403 | mtd->oobsize = 512; | |
3404 | break; | |
3405 | case 6: | |
e2d3a35e BN |
3406 | mtd->oobsize = 640; |
3407 | break; | |
94d04e82 HS |
3408 | case 7: |
3409 | default: /* Other cases are "reserved" (unknown) */ | |
3410 | mtd->oobsize = 1024; | |
3411 | break; | |
fc09bbc0 BN |
3412 | } |
3413 | extid >>= 2; | |
3414 | /* Calc blocksize */ | |
3415 | mtd->erasesize = (128 * 1024) << | |
3416 | (((extid >> 1) & 0x04) | (extid & 0x03)); | |
3417 | *busw = 0; | |
73ca392f | 3418 | } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && |
1d0ed69d | 3419 | !nand_is_slc(chip)) { |
73ca392f BN |
3420 | unsigned int tmp; |
3421 | ||
3422 | /* Calc pagesize */ | |
3423 | mtd->writesize = 2048 << (extid & 0x03); | |
3424 | extid >>= 2; | |
3425 | /* Calc oobsize */ | |
3426 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { | |
3427 | case 0: | |
3428 | mtd->oobsize = 128; | |
3429 | break; | |
3430 | case 1: | |
3431 | mtd->oobsize = 224; | |
3432 | break; | |
3433 | case 2: | |
3434 | mtd->oobsize = 448; | |
3435 | break; | |
3436 | case 3: | |
3437 | mtd->oobsize = 64; | |
3438 | break; | |
3439 | case 4: | |
3440 | mtd->oobsize = 32; | |
3441 | break; | |
3442 | case 5: | |
3443 | mtd->oobsize = 16; | |
3444 | break; | |
3445 | default: | |
3446 | mtd->oobsize = 640; | |
3447 | break; | |
3448 | } | |
3449 | extid >>= 2; | |
3450 | /* Calc blocksize */ | |
3451 | tmp = ((extid >> 1) & 0x04) | (extid & 0x03); | |
3452 | if (tmp < 0x03) | |
3453 | mtd->erasesize = (128 * 1024) << tmp; | |
3454 | else if (tmp == 0x03) | |
3455 | mtd->erasesize = 768 * 1024; | |
3456 | else | |
3457 | mtd->erasesize = (64 * 1024) << tmp; | |
3458 | *busw = 0; | |
fc09bbc0 BN |
3459 | } else { |
3460 | /* Calc pagesize */ | |
3461 | mtd->writesize = 1024 << (extid & 0x03); | |
3462 | extid >>= 2; | |
3463 | /* Calc oobsize */ | |
3464 | mtd->oobsize = (8 << (extid & 0x01)) * | |
3465 | (mtd->writesize >> 9); | |
3466 | extid >>= 2; | |
3467 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
3468 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
3469 | extid >>= 2; | |
3470 | /* Get buswidth information */ | |
3471 | *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
60c67382 BN |
3472 | |
3473 | /* | |
3474 | * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per | |
3475 | * 512B page. For Toshiba SLC, we decode the 5th/6th byte as | |
3476 | * follows: | |
3477 | * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, | |
3478 | * 110b -> 24nm | |
3479 | * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC | |
3480 | */ | |
3481 | if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA && | |
1d0ed69d | 3482 | nand_is_slc(chip) && |
60c67382 BN |
3483 | (id_data[5] & 0x7) == 0x6 /* 24nm */ && |
3484 | !(id_data[4] & 0x80) /* !BENAND */) { | |
3485 | mtd->oobsize = 32 * mtd->writesize >> 9; | |
3486 | } | |
3487 | ||
fc09bbc0 BN |
3488 | } |
3489 | } | |
3490 | ||
f23a481c BN |
3491 | /* |
3492 | * Old devices have chip data hardcoded in the device ID table. nand_decode_id | |
3493 | * decodes a matching ID table entry and assigns the MTD size parameters for | |
3494 | * the chip. | |
3495 | */ | |
3496 | static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, | |
3497 | struct nand_flash_dev *type, u8 id_data[8], | |
3498 | int *busw) | |
3499 | { | |
3500 | int maf_id = id_data[0]; | |
3501 | ||
3502 | mtd->erasesize = type->erasesize; | |
3503 | mtd->writesize = type->pagesize; | |
3504 | mtd->oobsize = mtd->writesize / 32; | |
3505 | *busw = type->options & NAND_BUSWIDTH_16; | |
3506 | ||
1c195e90 HS |
3507 | /* All legacy ID NAND are small-page, SLC */ |
3508 | chip->bits_per_cell = 1; | |
3509 | ||
f23a481c BN |
3510 | /* |
3511 | * Check for Spansion/AMD ID + repeating 5th, 6th byte since | |
3512 | * some Spansion chips have erasesize that conflicts with size | |
3513 | * listed in nand_ids table. | |
3514 | * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) | |
3515 | */ | |
3516 | if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00 | |
3517 | && id_data[6] == 0x00 && id_data[7] == 0x00 | |
3518 | && mtd->writesize == 512) { | |
3519 | mtd->erasesize = 128 * 1024; | |
3520 | mtd->erasesize <<= ((id_data[3] & 0x03) << 1); | |
3521 | } | |
3522 | } | |
3523 | ||
7e74c2d7 BN |
3524 | /* |
3525 | * Set the bad block marker/indicator (BBM/BBI) patterns according to some | |
3526 | * heuristic patterns using various detected parameters (e.g., manufacturer, | |
3527 | * page size, cell-type information). | |
3528 | */ | |
3529 | static void nand_decode_bbm_options(struct mtd_info *mtd, | |
3530 | struct nand_chip *chip, u8 id_data[8]) | |
3531 | { | |
3532 | int maf_id = id_data[0]; | |
3533 | ||
3534 | /* Set the bad block position */ | |
3535 | if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) | |
3536 | chip->badblockpos = NAND_LARGE_BADBLOCK_POS; | |
3537 | else | |
3538 | chip->badblockpos = NAND_SMALL_BADBLOCK_POS; | |
3539 | ||
3540 | /* | |
3541 | * Bad block marker is stored in the last page of each block on Samsung | |
3542 | * and Hynix MLC devices; stored in first two pages of each block on | |
3543 | * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, | |
3544 | * AMD/Spansion, and Macronix. All others scan only the first page. | |
3545 | */ | |
1d0ed69d | 3546 | if (!nand_is_slc(chip) && |
7e74c2d7 BN |
3547 | (maf_id == NAND_MFR_SAMSUNG || |
3548 | maf_id == NAND_MFR_HYNIX)) | |
3549 | chip->bbt_options |= NAND_BBT_SCANLASTPAGE; | |
1d0ed69d | 3550 | else if ((nand_is_slc(chip) && |
7e74c2d7 BN |
3551 | (maf_id == NAND_MFR_SAMSUNG || |
3552 | maf_id == NAND_MFR_HYNIX || | |
3553 | maf_id == NAND_MFR_TOSHIBA || | |
3554 | maf_id == NAND_MFR_AMD || | |
3555 | maf_id == NAND_MFR_MACRONIX)) || | |
3556 | (mtd->writesize == 2048 && | |
3557 | maf_id == NAND_MFR_MICRON)) | |
3558 | chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; | |
3559 | } | |
3560 | ||
ec6e87e3 HS |
3561 | static inline bool is_full_id_nand(struct nand_flash_dev *type) |
3562 | { | |
3563 | return type->id_len; | |
3564 | } | |
3565 | ||
3566 | static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, | |
3567 | struct nand_flash_dev *type, u8 *id_data, int *busw) | |
3568 | { | |
3569 | if (!strncmp(type->id, id_data, type->id_len)) { | |
3570 | mtd->writesize = type->pagesize; | |
3571 | mtd->erasesize = type->erasesize; | |
3572 | mtd->oobsize = type->oobsize; | |
3573 | ||
7db906b7 | 3574 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
ec6e87e3 HS |
3575 | chip->chipsize = (uint64_t)type->chipsize << 20; |
3576 | chip->options |= type->options; | |
57219342 HS |
3577 | chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); |
3578 | chip->ecc_step_ds = NAND_ECC_STEP(type); | |
ec6e87e3 HS |
3579 | |
3580 | *busw = type->options & NAND_BUSWIDTH_16; | |
3581 | ||
092b6a1d CZ |
3582 | if (!mtd->name) |
3583 | mtd->name = type->name; | |
3584 | ||
ec6e87e3 HS |
3585 | return true; |
3586 | } | |
3587 | return false; | |
3588 | } | |
3589 | ||
7aa65bfd | 3590 | /* |
8b6e50c9 | 3591 | * Get the flash and manufacturer id and lookup if the type is supported. |
7aa65bfd TG |
3592 | */ |
3593 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 3594 | struct nand_chip *chip, |
7351d3a5 | 3595 | int *maf_id, int *dev_id, |
5e81e88a | 3596 | struct nand_flash_dev *type) |
7aa65bfd | 3597 | { |
bb77082f | 3598 | int busw; |
d1e1f4e4 | 3599 | int i, maf_idx; |
426c457a | 3600 | u8 id_data[8]; |
1da177e4 LT |
3601 | |
3602 | /* Select the device */ | |
ace4dfee | 3603 | chip->select_chip(mtd, 0); |
1da177e4 | 3604 | |
ef89a880 KB |
3605 | /* |
3606 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
8b6e50c9 | 3607 | * after power-up. |
ef89a880 KB |
3608 | */ |
3609 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
3610 | ||
1da177e4 | 3611 | /* Send the command for reading device ID */ |
ace4dfee | 3612 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
3613 | |
3614 | /* Read manufacturer and device IDs */ | |
ace4dfee | 3615 | *maf_id = chip->read_byte(mtd); |
d1e1f4e4 | 3616 | *dev_id = chip->read_byte(mtd); |
1da177e4 | 3617 | |
8b6e50c9 BN |
3618 | /* |
3619 | * Try again to make sure, as some systems the bus-hold or other | |
ed8165c7 BD |
3620 | * interface concerns can cause random data which looks like a |
3621 | * possibly credible NAND flash to appear. If the two results do | |
3622 | * not match, ignore the device completely. | |
3623 | */ | |
3624 | ||
3625 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
3626 | ||
4aef9b78 BN |
3627 | /* Read entire ID string */ |
3628 | for (i = 0; i < 8; i++) | |
426c457a | 3629 | id_data[i] = chip->read_byte(mtd); |
ed8165c7 | 3630 | |
d1e1f4e4 | 3631 | if (id_data[0] != *maf_id || id_data[1] != *dev_id) { |
20171642 | 3632 | pr_info("second ID read did not match %02x,%02x against %02x,%02x\n", |
d0370219 | 3633 | *maf_id, *dev_id, id_data[0], id_data[1]); |
ed8165c7 BD |
3634 | return ERR_PTR(-ENODEV); |
3635 | } | |
3636 | ||
7aa65bfd | 3637 | if (!type) |
5e81e88a DW |
3638 | type = nand_flash_ids; |
3639 | ||
ec6e87e3 HS |
3640 | for (; type->name != NULL; type++) { |
3641 | if (is_full_id_nand(type)) { | |
3642 | if (find_full_id_nand(mtd, chip, type, id_data, &busw)) | |
3643 | goto ident_done; | |
3644 | } else if (*dev_id == type->dev_id) { | |
3645 | break; | |
3646 | } | |
3647 | } | |
5e81e88a | 3648 | |
d1e1f4e4 FF |
3649 | chip->onfi_version = 0; |
3650 | if (!type->name || !type->pagesize) { | |
35fc5195 | 3651 | /* Check if the chip is ONFI compliant */ |
47450b35 | 3652 | if (nand_flash_detect_onfi(mtd, chip, &busw)) |
6fb277ba | 3653 | goto ident_done; |
91361818 HS |
3654 | |
3655 | /* Check if the chip is JEDEC compliant */ | |
3656 | if (nand_flash_detect_jedec(mtd, chip, &busw)) | |
3657 | goto ident_done; | |
d1e1f4e4 FF |
3658 | } |
3659 | ||
5e81e88a | 3660 | if (!type->name) |
7aa65bfd TG |
3661 | return ERR_PTR(-ENODEV); |
3662 | ||
ba0251fe TG |
3663 | if (!mtd->name) |
3664 | mtd->name = type->name; | |
3665 | ||
69423d99 | 3666 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd | 3667 | |
12a40a57 | 3668 | if (!type->pagesize && chip->init_size) { |
8b6e50c9 | 3669 | /* Set the pagesize, oobsize, erasesize by the driver */ |
12a40a57 HS |
3670 | busw = chip->init_size(mtd, chip, id_data); |
3671 | } else if (!type->pagesize) { | |
fc09bbc0 BN |
3672 | /* Decode parameters from extended ID */ |
3673 | nand_decode_ext_id(mtd, chip, id_data, &busw); | |
7aa65bfd | 3674 | } else { |
f23a481c | 3675 | nand_decode_id(mtd, chip, type, id_data, &busw); |
7aa65bfd | 3676 | } |
bf7a01bf BN |
3677 | /* Get chip options */ |
3678 | chip->options |= type->options; | |
d1e1f4e4 | 3679 | |
8b6e50c9 BN |
3680 | /* |
3681 | * Check if chip is not a Samsung device. Do not clear the | |
3682 | * options for chips which do not have an extended id. | |
d1e1f4e4 FF |
3683 | */ |
3684 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) | |
3685 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; | |
3686 | ident_done: | |
3687 | ||
7aa65bfd | 3688 | /* Try to identify manufacturer */ |
9a909867 | 3689 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { |
7aa65bfd TG |
3690 | if (nand_manuf_ids[maf_idx].id == *maf_id) |
3691 | break; | |
3692 | } | |
0ea4a755 | 3693 | |
64b37b2a MC |
3694 | if (chip->options & NAND_BUSWIDTH_AUTO) { |
3695 | WARN_ON(chip->options & NAND_BUSWIDTH_16); | |
3696 | chip->options |= busw; | |
3697 | nand_set_defaults(chip, busw); | |
3698 | } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { | |
3699 | /* | |
3700 | * Check, if buswidth is correct. Hardware drivers should set | |
3701 | * chip correct! | |
3702 | */ | |
20171642 EG |
3703 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
3704 | *maf_id, *dev_id); | |
3705 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name); | |
3706 | pr_warn("bus width %d instead %d bit\n", | |
d0370219 BN |
3707 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
3708 | busw ? 16 : 8); | |
7aa65bfd TG |
3709 | return ERR_PTR(-EINVAL); |
3710 | } | |
61b03bd7 | 3711 | |
7e74c2d7 BN |
3712 | nand_decode_bbm_options(mtd, chip, id_data); |
3713 | ||
7aa65bfd | 3714 | /* Calculate the address shift from the page size */ |
ace4dfee | 3715 | chip->page_shift = ffs(mtd->writesize) - 1; |
8b6e50c9 | 3716 | /* Convert chipsize to number of pages per chip -1 */ |
ace4dfee | 3717 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 3718 | |
ace4dfee | 3719 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 3720 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
3721 | if (chip->chipsize & 0xffffffff) |
3722 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
7351d3a5 FF |
3723 | else { |
3724 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); | |
3725 | chip->chip_shift += 32 - 1; | |
3726 | } | |
1da177e4 | 3727 | |
26d9be11 | 3728 | chip->badblockbits = 8; |
49c50b97 | 3729 | chip->erase = single_erase; |
7aa65bfd | 3730 | |
8b6e50c9 | 3731 | /* Do not replace user supplied command function! */ |
ace4dfee TG |
3732 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
3733 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd | 3734 | |
20171642 EG |
3735 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
3736 | *maf_id, *dev_id); | |
ffdac6cd HS |
3737 | |
3738 | if (chip->onfi_version) | |
3739 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3740 | chip->onfi_params.model); | |
3741 | else if (chip->jedec_version) | |
3742 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3743 | chip->jedec_params.model); | |
3744 | else | |
3745 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3746 | type->name); | |
3747 | ||
20171642 | 3748 | pr_info("%dMiB, %s, page size: %d, OOB size: %d\n", |
3723e93c HS |
3749 | (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", |
3750 | mtd->writesize, mtd->oobsize); | |
7aa65bfd TG |
3751 | return type; |
3752 | } | |
3753 | ||
7aa65bfd | 3754 | /** |
3b85c321 | 3755 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
8b6e50c9 BN |
3756 | * @mtd: MTD device structure |
3757 | * @maxchips: number of chips to scan for | |
3758 | * @table: alternative NAND ID table | |
7aa65bfd | 3759 | * |
8b6e50c9 BN |
3760 | * This is the first phase of the normal nand_scan() function. It reads the |
3761 | * flash ID and sets up MTD fields accordingly. | |
7aa65bfd | 3762 | * |
3b85c321 | 3763 | * The mtd->owner field must be set to the module of the caller. |
7aa65bfd | 3764 | */ |
5e81e88a DW |
3765 | int nand_scan_ident(struct mtd_info *mtd, int maxchips, |
3766 | struct nand_flash_dev *table) | |
7aa65bfd | 3767 | { |
bb77082f | 3768 | int i, nand_maf_id, nand_dev_id; |
ace4dfee | 3769 | struct nand_chip *chip = mtd->priv; |
7aa65bfd TG |
3770 | struct nand_flash_dev *type; |
3771 | ||
7aa65bfd | 3772 | /* Set the default functions */ |
bb77082f | 3773 | nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16); |
7aa65bfd TG |
3774 | |
3775 | /* Read the flash type */ | |
bb77082f CZ |
3776 | type = nand_get_flash_type(mtd, chip, &nand_maf_id, |
3777 | &nand_dev_id, table); | |
7aa65bfd TG |
3778 | |
3779 | if (IS_ERR(type)) { | |
b1c6e6db | 3780 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
d0370219 | 3781 | pr_warn("No NAND device found\n"); |
ace4dfee | 3782 | chip->select_chip(mtd, -1); |
7aa65bfd | 3783 | return PTR_ERR(type); |
1da177e4 LT |
3784 | } |
3785 | ||
07300164 HS |
3786 | chip->select_chip(mtd, -1); |
3787 | ||
7aa65bfd | 3788 | /* Check for a chip array */ |
e0c7d767 | 3789 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 3790 | chip->select_chip(mtd, i); |
ef89a880 KB |
3791 | /* See comment in nand_get_flash_type for reset */ |
3792 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1da177e4 | 3793 | /* Send the command for reading device ID */ |
ace4dfee | 3794 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 3795 | /* Read manufacturer and device IDs */ |
ace4dfee | 3796 | if (nand_maf_id != chip->read_byte(mtd) || |
07300164 HS |
3797 | nand_dev_id != chip->read_byte(mtd)) { |
3798 | chip->select_chip(mtd, -1); | |
1da177e4 | 3799 | break; |
07300164 HS |
3800 | } |
3801 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
3802 | } |
3803 | if (i > 1) | |
20171642 | 3804 | pr_info("%d chips detected\n", i); |
61b03bd7 | 3805 | |
1da177e4 | 3806 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
3807 | chip->numchips = i; |
3808 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 3809 | |
3b85c321 DW |
3810 | return 0; |
3811 | } | |
7351d3a5 | 3812 | EXPORT_SYMBOL(nand_scan_ident); |
3b85c321 | 3813 | |
67a9ad9b EG |
3814 | /* |
3815 | * Check if the chip configuration meet the datasheet requirements. | |
3816 | ||
3817 | * If our configuration corrects A bits per B bytes and the minimum | |
3818 | * required correction level is X bits per Y bytes, then we must ensure | |
3819 | * both of the following are true: | |
3820 | * | |
3821 | * (1) A / B >= X / Y | |
3822 | * (2) A >= X | |
3823 | * | |
3824 | * Requirement (1) ensures we can correct for the required bitflip density. | |
3825 | * Requirement (2) ensures we can correct even when all bitflips are clumped | |
3826 | * in the same sector. | |
3827 | */ | |
3828 | static bool nand_ecc_strength_good(struct mtd_info *mtd) | |
3829 | { | |
3830 | struct nand_chip *chip = mtd->priv; | |
3831 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
3832 | int corr, ds_corr; | |
3833 | ||
3834 | if (ecc->size == 0 || chip->ecc_step_ds == 0) | |
3835 | /* Not enough information */ | |
3836 | return true; | |
3837 | ||
3838 | /* | |
3839 | * We get the number of corrected bits per page to compare | |
3840 | * the correction density. | |
3841 | */ | |
3842 | corr = (mtd->writesize * ecc->strength) / ecc->size; | |
3843 | ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds; | |
3844 | ||
3845 | return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds; | |
3846 | } | |
3b85c321 DW |
3847 | |
3848 | /** | |
3849 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
8b6e50c9 | 3850 | * @mtd: MTD device structure |
3b85c321 | 3851 | * |
8b6e50c9 BN |
3852 | * This is the second phase of the normal nand_scan() function. It fills out |
3853 | * all the uninitialized function pointers with the defaults and scans for a | |
3854 | * bad block table if appropriate. | |
3b85c321 DW |
3855 | */ |
3856 | int nand_scan_tail(struct mtd_info *mtd) | |
3857 | { | |
3858 | int i; | |
3859 | struct nand_chip *chip = mtd->priv; | |
97de79e0 | 3860 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
f02ea4e6 | 3861 | struct nand_buffers *nbuf; |
3b85c321 | 3862 | |
e2414f4c BN |
3863 | /* New bad blocks should be marked in OOB, flash-based BBT, or both */ |
3864 | BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && | |
3865 | !(chip->bbt_options & NAND_BBT_USE_FLASH)); | |
3866 | ||
f02ea4e6 HS |
3867 | if (!(chip->options & NAND_OWN_BUFFERS)) { |
3868 | nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize | |
3869 | + mtd->oobsize * 3, GFP_KERNEL); | |
3870 | if (!nbuf) | |
3871 | return -ENOMEM; | |
3872 | nbuf->ecccalc = (uint8_t *)(nbuf + 1); | |
3873 | nbuf->ecccode = nbuf->ecccalc + mtd->oobsize; | |
3874 | nbuf->databuf = nbuf->ecccode + mtd->oobsize; | |
3875 | ||
3876 | chip->buffers = nbuf; | |
3877 | } else { | |
3878 | if (!chip->buffers) | |
3879 | return -ENOMEM; | |
3880 | } | |
4bf63fcb | 3881 | |
7dcdcbef | 3882 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 3883 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 3884 | |
7aa65bfd | 3885 | /* |
8b6e50c9 | 3886 | * If no default placement scheme is given, select an appropriate one. |
7aa65bfd | 3887 | */ |
97de79e0 | 3888 | if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) { |
61b03bd7 | 3889 | switch (mtd->oobsize) { |
1da177e4 | 3890 | case 8: |
97de79e0 | 3891 | ecc->layout = &nand_oob_8; |
1da177e4 LT |
3892 | break; |
3893 | case 16: | |
97de79e0 | 3894 | ecc->layout = &nand_oob_16; |
1da177e4 LT |
3895 | break; |
3896 | case 64: | |
97de79e0 | 3897 | ecc->layout = &nand_oob_64; |
1da177e4 | 3898 | break; |
81ec5364 | 3899 | case 128: |
97de79e0 | 3900 | ecc->layout = &nand_oob_128; |
81ec5364 | 3901 | break; |
1da177e4 | 3902 | default: |
d0370219 BN |
3903 | pr_warn("No oob scheme defined for oobsize %d\n", |
3904 | mtd->oobsize); | |
1da177e4 LT |
3905 | BUG(); |
3906 | } | |
3907 | } | |
61b03bd7 | 3908 | |
956e944c DW |
3909 | if (!chip->write_page) |
3910 | chip->write_page = nand_write_page; | |
3911 | ||
61b03bd7 | 3912 | /* |
8b6e50c9 | 3913 | * Check ECC mode, default to software if 3byte/512byte hardware ECC is |
7aa65bfd | 3914 | * selected and we have 256 byte pagesize fallback to software ECC |
e0c7d767 | 3915 | */ |
956e944c | 3916 | |
97de79e0 | 3917 | switch (ecc->mode) { |
6e0cb135 SN |
3918 | case NAND_ECC_HW_OOB_FIRST: |
3919 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
97de79e0 | 3920 | if (!ecc->calculate || !ecc->correct || !ecc->hwctl) { |
9a4d4d69 | 3921 | pr_warn("No ECC functions supplied; " |
d0370219 | 3922 | "hardware ECC not possible\n"); |
6e0cb135 SN |
3923 | BUG(); |
3924 | } | |
97de79e0 HS |
3925 | if (!ecc->read_page) |
3926 | ecc->read_page = nand_read_page_hwecc_oob_first; | |
6e0cb135 | 3927 | |
6dfc6d25 | 3928 | case NAND_ECC_HW: |
8b6e50c9 | 3929 | /* Use standard hwecc read page function? */ |
97de79e0 HS |
3930 | if (!ecc->read_page) |
3931 | ecc->read_page = nand_read_page_hwecc; | |
3932 | if (!ecc->write_page) | |
3933 | ecc->write_page = nand_write_page_hwecc; | |
3934 | if (!ecc->read_page_raw) | |
3935 | ecc->read_page_raw = nand_read_page_raw; | |
3936 | if (!ecc->write_page_raw) | |
3937 | ecc->write_page_raw = nand_write_page_raw; | |
3938 | if (!ecc->read_oob) | |
3939 | ecc->read_oob = nand_read_oob_std; | |
3940 | if (!ecc->write_oob) | |
3941 | ecc->write_oob = nand_write_oob_std; | |
3942 | if (!ecc->read_subpage) | |
3943 | ecc->read_subpage = nand_read_subpage; | |
3944 | if (!ecc->write_subpage) | |
3945 | ecc->write_subpage = nand_write_subpage_hwecc; | |
f5bbdacc | 3946 | |
6dfc6d25 | 3947 | case NAND_ECC_HW_SYNDROME: |
97de79e0 HS |
3948 | if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && |
3949 | (!ecc->read_page || | |
3950 | ecc->read_page == nand_read_page_hwecc || | |
3951 | !ecc->write_page || | |
3952 | ecc->write_page == nand_write_page_hwecc)) { | |
9a4d4d69 | 3953 | pr_warn("No ECC functions supplied; " |
d0370219 | 3954 | "hardware ECC not possible\n"); |
6dfc6d25 TG |
3955 | BUG(); |
3956 | } | |
8b6e50c9 | 3957 | /* Use standard syndrome read/write page function? */ |
97de79e0 HS |
3958 | if (!ecc->read_page) |
3959 | ecc->read_page = nand_read_page_syndrome; | |
3960 | if (!ecc->write_page) | |
3961 | ecc->write_page = nand_write_page_syndrome; | |
3962 | if (!ecc->read_page_raw) | |
3963 | ecc->read_page_raw = nand_read_page_raw_syndrome; | |
3964 | if (!ecc->write_page_raw) | |
3965 | ecc->write_page_raw = nand_write_page_raw_syndrome; | |
3966 | if (!ecc->read_oob) | |
3967 | ecc->read_oob = nand_read_oob_syndrome; | |
3968 | if (!ecc->write_oob) | |
3969 | ecc->write_oob = nand_write_oob_syndrome; | |
3970 | ||
3971 | if (mtd->writesize >= ecc->size) { | |
3972 | if (!ecc->strength) { | |
e2788c98 MD |
3973 | pr_warn("Driver must set ecc.strength when using hardware ECC\n"); |
3974 | BUG(); | |
3975 | } | |
6dfc6d25 | 3976 | break; |
e2788c98 | 3977 | } |
9a4d4d69 | 3978 | pr_warn("%d byte HW ECC not possible on " |
d0370219 | 3979 | "%d byte page size, fallback to SW ECC\n", |
97de79e0 HS |
3980 | ecc->size, mtd->writesize); |
3981 | ecc->mode = NAND_ECC_SOFT; | |
61b03bd7 | 3982 | |
6dfc6d25 | 3983 | case NAND_ECC_SOFT: |
97de79e0 HS |
3984 | ecc->calculate = nand_calculate_ecc; |
3985 | ecc->correct = nand_correct_data; | |
3986 | ecc->read_page = nand_read_page_swecc; | |
3987 | ecc->read_subpage = nand_read_subpage; | |
3988 | ecc->write_page = nand_write_page_swecc; | |
3989 | ecc->read_page_raw = nand_read_page_raw; | |
3990 | ecc->write_page_raw = nand_write_page_raw; | |
3991 | ecc->read_oob = nand_read_oob_std; | |
3992 | ecc->write_oob = nand_write_oob_std; | |
3993 | if (!ecc->size) | |
3994 | ecc->size = 256; | |
3995 | ecc->bytes = 3; | |
3996 | ecc->strength = 1; | |
1da177e4 | 3997 | break; |
61b03bd7 | 3998 | |
193bd400 ID |
3999 | case NAND_ECC_SOFT_BCH: |
4000 | if (!mtd_nand_has_bch()) { | |
148256fa | 4001 | pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n"); |
193bd400 ID |
4002 | BUG(); |
4003 | } | |
97de79e0 HS |
4004 | ecc->calculate = nand_bch_calculate_ecc; |
4005 | ecc->correct = nand_bch_correct_data; | |
4006 | ecc->read_page = nand_read_page_swecc; | |
4007 | ecc->read_subpage = nand_read_subpage; | |
4008 | ecc->write_page = nand_write_page_swecc; | |
4009 | ecc->read_page_raw = nand_read_page_raw; | |
4010 | ecc->write_page_raw = nand_write_page_raw; | |
4011 | ecc->read_oob = nand_read_oob_std; | |
4012 | ecc->write_oob = nand_write_oob_std; | |
193bd400 ID |
4013 | /* |
4014 | * Board driver should supply ecc.size and ecc.bytes values to | |
4015 | * select how many bits are correctable; see nand_bch_init() | |
8b6e50c9 BN |
4016 | * for details. Otherwise, default to 4 bits for large page |
4017 | * devices. | |
193bd400 | 4018 | */ |
97de79e0 HS |
4019 | if (!ecc->size && (mtd->oobsize >= 64)) { |
4020 | ecc->size = 512; | |
4021 | ecc->bytes = 7; | |
193bd400 | 4022 | } |
97de79e0 HS |
4023 | ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes, |
4024 | &ecc->layout); | |
4025 | if (!ecc->priv) { | |
9a4d4d69 | 4026 | pr_warn("BCH ECC initialization failed!\n"); |
193bd400 ID |
4027 | BUG(); |
4028 | } | |
97de79e0 | 4029 | ecc->strength = ecc->bytes * 8 / fls(8 * ecc->size); |
193bd400 ID |
4030 | break; |
4031 | ||
61b03bd7 | 4032 | case NAND_ECC_NONE: |
9a4d4d69 | 4033 | pr_warn("NAND_ECC_NONE selected by board driver. " |
d0370219 | 4034 | "This is not recommended!\n"); |
97de79e0 HS |
4035 | ecc->read_page = nand_read_page_raw; |
4036 | ecc->write_page = nand_write_page_raw; | |
4037 | ecc->read_oob = nand_read_oob_std; | |
4038 | ecc->read_page_raw = nand_read_page_raw; | |
4039 | ecc->write_page_raw = nand_write_page_raw; | |
4040 | ecc->write_oob = nand_write_oob_std; | |
4041 | ecc->size = mtd->writesize; | |
4042 | ecc->bytes = 0; | |
4043 | ecc->strength = 0; | |
1da177e4 | 4044 | break; |
956e944c | 4045 | |
1da177e4 | 4046 | default: |
97de79e0 | 4047 | pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode); |
61b03bd7 | 4048 | BUG(); |
1da177e4 | 4049 | } |
61b03bd7 | 4050 | |
9ce244b3 | 4051 | /* For many systems, the standard OOB write also works for raw */ |
97de79e0 HS |
4052 | if (!ecc->read_oob_raw) |
4053 | ecc->read_oob_raw = ecc->read_oob; | |
4054 | if (!ecc->write_oob_raw) | |
4055 | ecc->write_oob_raw = ecc->write_oob; | |
9ce244b3 | 4056 | |
5bd34c09 TG |
4057 | /* |
4058 | * The number of bytes available for a client to place data into | |
8b6e50c9 | 4059 | * the out of band area. |
5bd34c09 | 4060 | */ |
97de79e0 HS |
4061 | ecc->layout->oobavail = 0; |
4062 | for (i = 0; ecc->layout->oobfree[i].length | |
4063 | && i < ARRAY_SIZE(ecc->layout->oobfree); i++) | |
4064 | ecc->layout->oobavail += ecc->layout->oobfree[i].length; | |
4065 | mtd->oobavail = ecc->layout->oobavail; | |
5bd34c09 | 4066 | |
67a9ad9b EG |
4067 | /* ECC sanity check: warn noisily if it's too weak */ |
4068 | WARN_ON(!nand_ecc_strength_good(mtd)); | |
4069 | ||
7aa65bfd TG |
4070 | /* |
4071 | * Set the number of read / write steps for one page depending on ECC | |
8b6e50c9 | 4072 | * mode. |
7aa65bfd | 4073 | */ |
97de79e0 HS |
4074 | ecc->steps = mtd->writesize / ecc->size; |
4075 | if (ecc->steps * ecc->size != mtd->writesize) { | |
9a4d4d69 | 4076 | pr_warn("Invalid ECC parameters\n"); |
6dfc6d25 | 4077 | BUG(); |
1da177e4 | 4078 | } |
97de79e0 | 4079 | ecc->total = ecc->steps * ecc->bytes; |
61b03bd7 | 4080 | |
8b6e50c9 | 4081 | /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ |
1d0ed69d | 4082 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { |
97de79e0 | 4083 | switch (ecc->steps) { |
29072b96 TG |
4084 | case 2: |
4085 | mtd->subpage_sft = 1; | |
4086 | break; | |
4087 | case 4: | |
4088 | case 8: | |
81ec5364 | 4089 | case 16: |
29072b96 TG |
4090 | mtd->subpage_sft = 2; |
4091 | break; | |
4092 | } | |
4093 | } | |
4094 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
4095 | ||
04bbd0ea | 4096 | /* Initialize state */ |
ace4dfee | 4097 | chip->state = FL_READY; |
1da177e4 | 4098 | |
1da177e4 | 4099 | /* Invalidate the pagebuffer reference */ |
ace4dfee | 4100 | chip->pagebuf = -1; |
1da177e4 | 4101 | |
a5ff4f10 | 4102 | /* Large page NAND with SOFT_ECC should support subpage reads */ |
4007e2d1 RL |
4103 | switch (ecc->mode) { |
4104 | case NAND_ECC_SOFT: | |
4105 | case NAND_ECC_SOFT_BCH: | |
4106 | if (chip->page_shift > 9) | |
4107 | chip->options |= NAND_SUBPAGE_READ; | |
4108 | break; | |
4109 | ||
4110 | default: | |
4111 | break; | |
4112 | } | |
a5ff4f10 | 4113 | |
1da177e4 | 4114 | /* Fill in remaining MTD driver data */ |
963d1c28 | 4115 | mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH; |
93edbad6 ML |
4116 | mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : |
4117 | MTD_CAP_NANDFLASH; | |
3c3c10bb AB |
4118 | mtd->_erase = nand_erase; |
4119 | mtd->_point = NULL; | |
4120 | mtd->_unpoint = NULL; | |
4121 | mtd->_read = nand_read; | |
4122 | mtd->_write = nand_write; | |
4123 | mtd->_panic_write = panic_nand_write; | |
4124 | mtd->_read_oob = nand_read_oob; | |
4125 | mtd->_write_oob = nand_write_oob; | |
4126 | mtd->_sync = nand_sync; | |
4127 | mtd->_lock = NULL; | |
4128 | mtd->_unlock = NULL; | |
4129 | mtd->_suspend = nand_suspend; | |
4130 | mtd->_resume = nand_resume; | |
8471bb73 | 4131 | mtd->_block_isreserved = nand_block_isreserved; |
3c3c10bb AB |
4132 | mtd->_block_isbad = nand_block_isbad; |
4133 | mtd->_block_markbad = nand_block_markbad; | |
cbcab65a | 4134 | mtd->writebufsize = mtd->writesize; |
1da177e4 | 4135 | |
6a918bad | 4136 | /* propagate ecc info to mtd_info */ |
97de79e0 HS |
4137 | mtd->ecclayout = ecc->layout; |
4138 | mtd->ecc_strength = ecc->strength; | |
4139 | mtd->ecc_step_size = ecc->size; | |
ea3b2ea2 SL |
4140 | /* |
4141 | * Initialize bitflip_threshold to its default prior scan_bbt() call. | |
4142 | * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be | |
4143 | * properly set. | |
4144 | */ | |
4145 | if (!mtd->bitflip_threshold) | |
4146 | mtd->bitflip_threshold = mtd->ecc_strength; | |
1da177e4 | 4147 | |
0040bf38 | 4148 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 4149 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 4150 | return 0; |
1da177e4 LT |
4151 | |
4152 | /* Build bad block table */ | |
ace4dfee | 4153 | return chip->scan_bbt(mtd); |
1da177e4 | 4154 | } |
7351d3a5 | 4155 | EXPORT_SYMBOL(nand_scan_tail); |
1da177e4 | 4156 | |
8b6e50c9 BN |
4157 | /* |
4158 | * is_module_text_address() isn't exported, and it's mostly a pointless | |
7351d3a5 | 4159 | * test if this is a module _anyway_ -- they'd have to try _really_ hard |
8b6e50c9 BN |
4160 | * to call us from in-kernel code if the core NAND support is modular. |
4161 | */ | |
3b85c321 DW |
4162 | #ifdef MODULE |
4163 | #define caller_is_module() (1) | |
4164 | #else | |
4165 | #define caller_is_module() \ | |
a6e6abd5 | 4166 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
4167 | #endif |
4168 | ||
4169 | /** | |
4170 | * nand_scan - [NAND Interface] Scan for the NAND device | |
8b6e50c9 BN |
4171 | * @mtd: MTD device structure |
4172 | * @maxchips: number of chips to scan for | |
3b85c321 | 4173 | * |
8b6e50c9 BN |
4174 | * This fills out all the uninitialized function pointers with the defaults. |
4175 | * The flash ID is read and the mtd/chip structures are filled with the | |
4176 | * appropriate values. The mtd->owner field must be set to the module of the | |
4177 | * caller. | |
3b85c321 DW |
4178 | */ |
4179 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
4180 | { | |
4181 | int ret; | |
4182 | ||
4183 | /* Many callers got this wrong, so check for it for a while... */ | |
4184 | if (!mtd->owner && caller_is_module()) { | |
d0370219 | 4185 | pr_crit("%s called with NULL mtd->owner!\n", __func__); |
3b85c321 DW |
4186 | BUG(); |
4187 | } | |
4188 | ||
5e81e88a | 4189 | ret = nand_scan_ident(mtd, maxchips, NULL); |
3b85c321 DW |
4190 | if (!ret) |
4191 | ret = nand_scan_tail(mtd); | |
4192 | return ret; | |
4193 | } | |
7351d3a5 | 4194 | EXPORT_SYMBOL(nand_scan); |
3b85c321 | 4195 | |
1da177e4 | 4196 | /** |
61b03bd7 | 4197 | * nand_release - [NAND Interface] Free resources held by the NAND device |
8b6e50c9 BN |
4198 | * @mtd: MTD device structure |
4199 | */ | |
e0c7d767 | 4200 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 4201 | { |
ace4dfee | 4202 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 4203 | |
193bd400 ID |
4204 | if (chip->ecc.mode == NAND_ECC_SOFT_BCH) |
4205 | nand_bch_free((struct nand_bch_control *)chip->ecc.priv); | |
4206 | ||
5ffcaf3d | 4207 | mtd_device_unregister(mtd); |
1da177e4 | 4208 | |
fa671646 | 4209 | /* Free bad block table memory */ |
ace4dfee | 4210 | kfree(chip->bbt); |
4bf63fcb DW |
4211 | if (!(chip->options & NAND_OWN_BUFFERS)) |
4212 | kfree(chip->buffers); | |
58373ff0 BN |
4213 | |
4214 | /* Free bad block descriptor memory */ | |
4215 | if (chip->badblock_pattern && chip->badblock_pattern->options | |
4216 | & NAND_BBT_DYNAMICSTRUCT) | |
4217 | kfree(chip->badblock_pattern); | |
1da177e4 | 4218 | } |
e0c7d767 | 4219 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 RP |
4220 | |
4221 | static int __init nand_base_init(void) | |
4222 | { | |
4223 | led_trigger_register_simple("nand-disk", &nand_led_trigger); | |
4224 | return 0; | |
4225 | } | |
4226 | ||
4227 | static void __exit nand_base_exit(void) | |
4228 | { | |
4229 | led_trigger_unregister_simple(nand_led_trigger); | |
4230 | } | |
4231 | ||
4232 | module_init(nand_base_init); | |
4233 | module_exit(nand_base_exit); | |
4234 | ||
e0c7d767 | 4235 | MODULE_LICENSE("GPL"); |
7351d3a5 FF |
4236 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); |
4237 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
e0c7d767 | 4238 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |