]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Overview: |
3 | * This is the generic MTD driver for NAND flash devices. It should be | |
4 | * capable of working with almost all NAND chips currently available. | |
61b03bd7 | 5 | * |
1da177e4 | 6 | * Additional technical information is available on |
8b2b403c | 7 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 8 | * |
1da177e4 | 9 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 10 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 11 | * |
ace4dfee | 12 | * Credits: |
61b03bd7 TG |
13 | * David Woodhouse for adding multichip support |
14 | * | |
1da177e4 LT |
15 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
16 | * rework for 2K page size chips | |
17 | * | |
ace4dfee | 18 | * TODO: |
1da177e4 LT |
19 | * Enable cached programming for 2k page size chips |
20 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
7854d3f7 | 21 | * if we have HW ECC support. |
c0b8ba7b | 22 | * BBT table is not serialized, has to be fixed |
1da177e4 | 23 | * |
1da177e4 LT |
24 | * This program is free software; you can redistribute it and/or modify |
25 | * it under the terms of the GNU General Public License version 2 as | |
26 | * published by the Free Software Foundation. | |
27 | * | |
28 | */ | |
29 | ||
20171642 EG |
30 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
31 | ||
552d9205 | 32 | #include <linux/module.h> |
1da177e4 LT |
33 | #include <linux/delay.h> |
34 | #include <linux/errno.h> | |
7aa65bfd | 35 | #include <linux/err.h> |
1da177e4 LT |
36 | #include <linux/sched.h> |
37 | #include <linux/slab.h> | |
66507c7b | 38 | #include <linux/mm.h> |
1da177e4 LT |
39 | #include <linux/types.h> |
40 | #include <linux/mtd/mtd.h> | |
41 | #include <linux/mtd/nand.h> | |
42 | #include <linux/mtd/nand_ecc.h> | |
193bd400 | 43 | #include <linux/mtd/nand_bch.h> |
1da177e4 LT |
44 | #include <linux/interrupt.h> |
45 | #include <linux/bitops.h> | |
8fe833c1 | 46 | #include <linux/leds.h> |
7351d3a5 | 47 | #include <linux/io.h> |
1da177e4 | 48 | #include <linux/mtd/partitions.h> |
5844feea | 49 | #include <linux/of_mtd.h> |
1da177e4 LT |
50 | |
51 | /* Define default oob placement schemes for large and small page devices */ | |
5bd34c09 | 52 | static struct nand_ecclayout nand_oob_8 = { |
1da177e4 LT |
53 | .eccbytes = 3, |
54 | .eccpos = {0, 1, 2}, | |
5bd34c09 TG |
55 | .oobfree = { |
56 | {.offset = 3, | |
57 | .length = 2}, | |
58 | {.offset = 6, | |
f8ac0414 | 59 | .length = 2} } |
1da177e4 LT |
60 | }; |
61 | ||
5bd34c09 | 62 | static struct nand_ecclayout nand_oob_16 = { |
1da177e4 LT |
63 | .eccbytes = 6, |
64 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
5bd34c09 TG |
65 | .oobfree = { |
66 | {.offset = 8, | |
f8ac0414 | 67 | . length = 8} } |
1da177e4 LT |
68 | }; |
69 | ||
5bd34c09 | 70 | static struct nand_ecclayout nand_oob_64 = { |
1da177e4 LT |
71 | .eccbytes = 24, |
72 | .eccpos = { | |
e0c7d767 DW |
73 | 40, 41, 42, 43, 44, 45, 46, 47, |
74 | 48, 49, 50, 51, 52, 53, 54, 55, | |
75 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
5bd34c09 TG |
76 | .oobfree = { |
77 | {.offset = 2, | |
f8ac0414 | 78 | .length = 38} } |
1da177e4 LT |
79 | }; |
80 | ||
81ec5364 TG |
81 | static struct nand_ecclayout nand_oob_128 = { |
82 | .eccbytes = 48, | |
83 | .eccpos = { | |
84 | 80, 81, 82, 83, 84, 85, 86, 87, | |
85 | 88, 89, 90, 91, 92, 93, 94, 95, | |
86 | 96, 97, 98, 99, 100, 101, 102, 103, | |
87 | 104, 105, 106, 107, 108, 109, 110, 111, | |
88 | 112, 113, 114, 115, 116, 117, 118, 119, | |
89 | 120, 121, 122, 123, 124, 125, 126, 127}, | |
90 | .oobfree = { | |
91 | {.offset = 2, | |
f8ac0414 | 92 | .length = 78} } |
81ec5364 TG |
93 | }; |
94 | ||
6a8214aa | 95 | static int nand_get_device(struct mtd_info *mtd, int new_state); |
1da177e4 | 96 | |
8593fbc6 TG |
97 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
98 | struct mtd_oob_ops *ops); | |
99 | ||
d470a97c | 100 | /* |
8e87d782 | 101 | * For devices which display every fart in the system on a separate LED. Is |
d470a97c TG |
102 | * compiled away when LED support is disabled. |
103 | */ | |
104 | DEFINE_LED_TRIGGER(nand_led_trigger); | |
105 | ||
6fe5a6ac VS |
106 | static int check_offs_len(struct mtd_info *mtd, |
107 | loff_t ofs, uint64_t len) | |
108 | { | |
109 | struct nand_chip *chip = mtd->priv; | |
110 | int ret = 0; | |
111 | ||
112 | /* Start address must align on block boundary */ | |
daae74ca | 113 | if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 114 | pr_debug("%s: unaligned address\n", __func__); |
6fe5a6ac VS |
115 | ret = -EINVAL; |
116 | } | |
117 | ||
118 | /* Length must align on block boundary */ | |
daae74ca | 119 | if (len & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 120 | pr_debug("%s: length not block aligned\n", __func__); |
6fe5a6ac VS |
121 | ret = -EINVAL; |
122 | } | |
123 | ||
6fe5a6ac VS |
124 | return ret; |
125 | } | |
126 | ||
1da177e4 LT |
127 | /** |
128 | * nand_release_device - [GENERIC] release chip | |
8b6e50c9 | 129 | * @mtd: MTD device structure |
61b03bd7 | 130 | * |
b0bb6903 | 131 | * Release chip lock and wake up anyone waiting on the device. |
1da177e4 | 132 | */ |
e0c7d767 | 133 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 134 | { |
ace4dfee | 135 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 136 | |
a36ed299 | 137 | /* Release the controller and the chip */ |
ace4dfee TG |
138 | spin_lock(&chip->controller->lock); |
139 | chip->controller->active = NULL; | |
140 | chip->state = FL_READY; | |
141 | wake_up(&chip->controller->wq); | |
142 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
143 | } |
144 | ||
145 | /** | |
146 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
8b6e50c9 | 147 | * @mtd: MTD device structure |
1da177e4 | 148 | * |
7854d3f7 | 149 | * Default read function for 8bit buswidth |
1da177e4 | 150 | */ |
58dd8f2b | 151 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 152 | { |
ace4dfee TG |
153 | struct nand_chip *chip = mtd->priv; |
154 | return readb(chip->IO_ADDR_R); | |
1da177e4 LT |
155 | } |
156 | ||
1da177e4 | 157 | /** |
7854d3f7 | 158 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
8b6e50c9 | 159 | * @mtd: MTD device structure |
1da177e4 | 160 | * |
7854d3f7 BN |
161 | * Default read function for 16bit buswidth with endianness conversion. |
162 | * | |
1da177e4 | 163 | */ |
58dd8f2b | 164 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 165 | { |
ace4dfee TG |
166 | struct nand_chip *chip = mtd->priv; |
167 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); | |
1da177e4 LT |
168 | } |
169 | ||
1da177e4 LT |
170 | /** |
171 | * nand_read_word - [DEFAULT] read one word from the chip | |
8b6e50c9 | 172 | * @mtd: MTD device structure |
1da177e4 | 173 | * |
7854d3f7 | 174 | * Default read function for 16bit buswidth without endianness conversion. |
1da177e4 LT |
175 | */ |
176 | static u16 nand_read_word(struct mtd_info *mtd) | |
177 | { | |
ace4dfee TG |
178 | struct nand_chip *chip = mtd->priv; |
179 | return readw(chip->IO_ADDR_R); | |
1da177e4 LT |
180 | } |
181 | ||
1da177e4 LT |
182 | /** |
183 | * nand_select_chip - [DEFAULT] control CE line | |
8b6e50c9 BN |
184 | * @mtd: MTD device structure |
185 | * @chipnr: chipnumber to select, -1 for deselect | |
1da177e4 LT |
186 | * |
187 | * Default select function for 1 chip devices. | |
188 | */ | |
ace4dfee | 189 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 190 | { |
ace4dfee TG |
191 | struct nand_chip *chip = mtd->priv; |
192 | ||
193 | switch (chipnr) { | |
1da177e4 | 194 | case -1: |
ace4dfee | 195 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
196 | break; |
197 | case 0: | |
1da177e4 LT |
198 | break; |
199 | ||
200 | default: | |
201 | BUG(); | |
202 | } | |
203 | } | |
204 | ||
05f78359 UKK |
205 | /** |
206 | * nand_write_byte - [DEFAULT] write single byte to chip | |
207 | * @mtd: MTD device structure | |
208 | * @byte: value to write | |
209 | * | |
210 | * Default function to write a byte to I/O[7:0] | |
211 | */ | |
212 | static void nand_write_byte(struct mtd_info *mtd, uint8_t byte) | |
213 | { | |
214 | struct nand_chip *chip = mtd->priv; | |
215 | ||
216 | chip->write_buf(mtd, &byte, 1); | |
217 | } | |
218 | ||
219 | /** | |
220 | * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16 | |
221 | * @mtd: MTD device structure | |
222 | * @byte: value to write | |
223 | * | |
224 | * Default function to write a byte to I/O[7:0] on a 16-bit wide chip. | |
225 | */ | |
226 | static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) | |
227 | { | |
228 | struct nand_chip *chip = mtd->priv; | |
229 | uint16_t word = byte; | |
230 | ||
231 | /* | |
232 | * It's not entirely clear what should happen to I/O[15:8] when writing | |
233 | * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads: | |
234 | * | |
235 | * When the host supports a 16-bit bus width, only data is | |
236 | * transferred at the 16-bit width. All address and command line | |
237 | * transfers shall use only the lower 8-bits of the data bus. During | |
238 | * command transfers, the host may place any value on the upper | |
239 | * 8-bits of the data bus. During address transfers, the host shall | |
240 | * set the upper 8-bits of the data bus to 00h. | |
241 | * | |
242 | * One user of the write_byte callback is nand_onfi_set_features. The | |
243 | * four parameters are specified to be written to I/O[7:0], but this is | |
244 | * neither an address nor a command transfer. Let's assume a 0 on the | |
245 | * upper I/O lines is OK. | |
246 | */ | |
247 | chip->write_buf(mtd, (uint8_t *)&word, 2); | |
248 | } | |
249 | ||
1da177e4 LT |
250 | /** |
251 | * nand_write_buf - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
252 | * @mtd: MTD device structure |
253 | * @buf: data buffer | |
254 | * @len: number of bytes to write | |
1da177e4 | 255 | * |
7854d3f7 | 256 | * Default write function for 8bit buswidth. |
1da177e4 | 257 | */ |
58dd8f2b | 258 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 259 | { |
ace4dfee | 260 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 261 | |
76413839 | 262 | iowrite8_rep(chip->IO_ADDR_W, buf, len); |
1da177e4 LT |
263 | } |
264 | ||
265 | /** | |
61b03bd7 | 266 | * nand_read_buf - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
267 | * @mtd: MTD device structure |
268 | * @buf: buffer to store date | |
269 | * @len: number of bytes to read | |
1da177e4 | 270 | * |
7854d3f7 | 271 | * Default read function for 8bit buswidth. |
1da177e4 | 272 | */ |
58dd8f2b | 273 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 274 | { |
ace4dfee | 275 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 276 | |
76413839 | 277 | ioread8_rep(chip->IO_ADDR_R, buf, len); |
1da177e4 LT |
278 | } |
279 | ||
1da177e4 LT |
280 | /** |
281 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
282 | * @mtd: MTD device structure |
283 | * @buf: data buffer | |
284 | * @len: number of bytes to write | |
1da177e4 | 285 | * |
7854d3f7 | 286 | * Default write function for 16bit buswidth. |
1da177e4 | 287 | */ |
58dd8f2b | 288 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 289 | { |
ace4dfee | 290 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 291 | u16 *p = (u16 *) buf; |
61b03bd7 | 292 | |
76413839 | 293 | iowrite16_rep(chip->IO_ADDR_W, p, len >> 1); |
1da177e4 LT |
294 | } |
295 | ||
296 | /** | |
61b03bd7 | 297 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
298 | * @mtd: MTD device structure |
299 | * @buf: buffer to store date | |
300 | * @len: number of bytes to read | |
1da177e4 | 301 | * |
7854d3f7 | 302 | * Default read function for 16bit buswidth. |
1da177e4 | 303 | */ |
58dd8f2b | 304 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 305 | { |
ace4dfee | 306 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 307 | u16 *p = (u16 *) buf; |
1da177e4 | 308 | |
76413839 | 309 | ioread16_rep(chip->IO_ADDR_R, p, len >> 1); |
1da177e4 LT |
310 | } |
311 | ||
1da177e4 LT |
312 | /** |
313 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
8b6e50c9 BN |
314 | * @mtd: MTD device structure |
315 | * @ofs: offset from device start | |
316 | * @getchip: 0, if the chip is already selected | |
1da177e4 | 317 | * |
61b03bd7 | 318 | * Check, if the block is bad. |
1da177e4 LT |
319 | */ |
320 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) | |
321 | { | |
cdbec050 | 322 | int page, chipnr, res = 0, i = 0; |
ace4dfee | 323 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
324 | u16 bad; |
325 | ||
5fb1549d | 326 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
327 | ofs += mtd->erasesize - mtd->writesize; |
328 | ||
1a12f46a TK |
329 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
330 | ||
1da177e4 | 331 | if (getchip) { |
ace4dfee | 332 | chipnr = (int)(ofs >> chip->chip_shift); |
1da177e4 | 333 | |
6a8214aa | 334 | nand_get_device(mtd, FL_READING); |
1da177e4 LT |
335 | |
336 | /* Select the NAND device */ | |
ace4dfee | 337 | chip->select_chip(mtd, chipnr); |
1a12f46a | 338 | } |
1da177e4 | 339 | |
cdbec050 BN |
340 | do { |
341 | if (chip->options & NAND_BUSWIDTH_16) { | |
342 | chip->cmdfunc(mtd, NAND_CMD_READOOB, | |
343 | chip->badblockpos & 0xFE, page); | |
344 | bad = cpu_to_le16(chip->read_word(mtd)); | |
345 | if (chip->badblockpos & 0x1) | |
346 | bad >>= 8; | |
347 | else | |
348 | bad &= 0xFF; | |
349 | } else { | |
350 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, | |
351 | page); | |
352 | bad = chip->read_byte(mtd); | |
353 | } | |
354 | ||
355 | if (likely(chip->badblockbits == 8)) | |
356 | res = bad != 0xFF; | |
e0b58d0a | 357 | else |
cdbec050 BN |
358 | res = hweight8(bad) < chip->badblockbits; |
359 | ofs += mtd->writesize; | |
360 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; | |
361 | i++; | |
362 | } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); | |
e0b58d0a | 363 | |
b0bb6903 HS |
364 | if (getchip) { |
365 | chip->select_chip(mtd, -1); | |
1da177e4 | 366 | nand_release_device(mtd); |
b0bb6903 | 367 | } |
61b03bd7 | 368 | |
1da177e4 LT |
369 | return res; |
370 | } | |
371 | ||
372 | /** | |
5a0edb25 | 373 | * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker |
8b6e50c9 BN |
374 | * @mtd: MTD device structure |
375 | * @ofs: offset from device start | |
1da177e4 | 376 | * |
8b6e50c9 | 377 | * This is the default implementation, which can be overridden by a hardware |
5a0edb25 BN |
378 | * specific driver. It provides the details for writing a bad block marker to a |
379 | * block. | |
380 | */ | |
381 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
382 | { | |
383 | struct nand_chip *chip = mtd->priv; | |
384 | struct mtd_oob_ops ops; | |
385 | uint8_t buf[2] = { 0, 0 }; | |
386 | int ret = 0, res, i = 0; | |
387 | ||
0ec56dc4 | 388 | memset(&ops, 0, sizeof(ops)); |
5a0edb25 BN |
389 | ops.oobbuf = buf; |
390 | ops.ooboffs = chip->badblockpos; | |
391 | if (chip->options & NAND_BUSWIDTH_16) { | |
392 | ops.ooboffs &= ~0x01; | |
393 | ops.len = ops.ooblen = 2; | |
394 | } else { | |
395 | ops.len = ops.ooblen = 1; | |
396 | } | |
397 | ops.mode = MTD_OPS_PLACE_OOB; | |
398 | ||
399 | /* Write to first/last page(s) if necessary */ | |
400 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) | |
401 | ofs += mtd->erasesize - mtd->writesize; | |
402 | do { | |
403 | res = nand_do_write_oob(mtd, ofs, &ops); | |
404 | if (!ret) | |
405 | ret = res; | |
406 | ||
407 | i++; | |
408 | ofs += mtd->writesize; | |
409 | } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); | |
410 | ||
411 | return ret; | |
412 | } | |
413 | ||
414 | /** | |
415 | * nand_block_markbad_lowlevel - mark a block bad | |
416 | * @mtd: MTD device structure | |
417 | * @ofs: offset from device start | |
418 | * | |
419 | * This function performs the generic NAND bad block marking steps (i.e., bad | |
420 | * block table(s) and/or marker(s)). We only allow the hardware driver to | |
421 | * specify how to write bad block markers to OOB (chip->block_markbad). | |
422 | * | |
b32843b7 | 423 | * We try operations in the following order: |
e2414f4c | 424 | * (1) erase the affected block, to allow OOB marker to be written cleanly |
b32843b7 BN |
425 | * (2) write bad block marker to OOB area of affected block (unless flag |
426 | * NAND_BBT_NO_OOB_BBM is present) | |
427 | * (3) update the BBT | |
428 | * Note that we retain the first error encountered in (2) or (3), finish the | |
e2414f4c | 429 | * procedures, and dump the error in the end. |
1da177e4 | 430 | */ |
5a0edb25 | 431 | static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 432 | { |
ace4dfee | 433 | struct nand_chip *chip = mtd->priv; |
b32843b7 | 434 | int res, ret = 0; |
61b03bd7 | 435 | |
b32843b7 | 436 | if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { |
00918429 BN |
437 | struct erase_info einfo; |
438 | ||
439 | /* Attempt erase before marking OOB */ | |
440 | memset(&einfo, 0, sizeof(einfo)); | |
441 | einfo.mtd = mtd; | |
442 | einfo.addr = ofs; | |
daae74ca | 443 | einfo.len = 1ULL << chip->phys_erase_shift; |
00918429 | 444 | nand_erase_nand(mtd, &einfo, 0); |
1da177e4 | 445 | |
b32843b7 | 446 | /* Write bad block marker to OOB */ |
6a8214aa | 447 | nand_get_device(mtd, FL_WRITING); |
5a0edb25 | 448 | ret = chip->block_markbad(mtd, ofs); |
c0b8ba7b | 449 | nand_release_device(mtd); |
f1a28c02 | 450 | } |
e2414f4c | 451 | |
b32843b7 BN |
452 | /* Mark block bad in BBT */ |
453 | if (chip->bbt) { | |
454 | res = nand_markbad_bbt(mtd, ofs); | |
e2414f4c BN |
455 | if (!ret) |
456 | ret = res; | |
457 | } | |
458 | ||
f1a28c02 TG |
459 | if (!ret) |
460 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 461 | |
f1a28c02 | 462 | return ret; |
1da177e4 LT |
463 | } |
464 | ||
61b03bd7 | 465 | /** |
1da177e4 | 466 | * nand_check_wp - [GENERIC] check if the chip is write protected |
8b6e50c9 | 467 | * @mtd: MTD device structure |
1da177e4 | 468 | * |
8b6e50c9 BN |
469 | * Check, if the device is write protected. The function expects, that the |
470 | * device is already selected. | |
1da177e4 | 471 | */ |
e0c7d767 | 472 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 473 | { |
ace4dfee | 474 | struct nand_chip *chip = mtd->priv; |
93edbad6 | 475 | |
8b6e50c9 | 476 | /* Broken xD cards report WP despite being writable */ |
93edbad6 ML |
477 | if (chip->options & NAND_BROKEN_XD) |
478 | return 0; | |
479 | ||
1da177e4 | 480 | /* Check the WP bit */ |
ace4dfee TG |
481 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
482 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
483 | } |
484 | ||
8471bb73 | 485 | /** |
c30e1f79 | 486 | * nand_block_isreserved - [GENERIC] Check if a block is marked reserved. |
8471bb73 EG |
487 | * @mtd: MTD device structure |
488 | * @ofs: offset from device start | |
489 | * | |
c30e1f79 | 490 | * Check if the block is marked as reserved. |
8471bb73 EG |
491 | */ |
492 | static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) | |
493 | { | |
494 | struct nand_chip *chip = mtd->priv; | |
495 | ||
496 | if (!chip->bbt) | |
497 | return 0; | |
498 | /* Return info from the table */ | |
499 | return nand_isreserved_bbt(mtd, ofs); | |
500 | } | |
501 | ||
1da177e4 LT |
502 | /** |
503 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
8b6e50c9 BN |
504 | * @mtd: MTD device structure |
505 | * @ofs: offset from device start | |
506 | * @getchip: 0, if the chip is already selected | |
507 | * @allowbbt: 1, if its allowed to access the bbt area | |
1da177e4 LT |
508 | * |
509 | * Check, if the block is bad. Either by reading the bad block table or | |
510 | * calling of the scan function. | |
511 | */ | |
2c0a2bed TG |
512 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, |
513 | int allowbbt) | |
1da177e4 | 514 | { |
ace4dfee | 515 | struct nand_chip *chip = mtd->priv; |
61b03bd7 | 516 | |
ace4dfee TG |
517 | if (!chip->bbt) |
518 | return chip->block_bad(mtd, ofs, getchip); | |
61b03bd7 | 519 | |
1da177e4 | 520 | /* Return info from the table */ |
e0c7d767 | 521 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
522 | } |
523 | ||
2af7c653 SK |
524 | /** |
525 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
8b6e50c9 BN |
526 | * @mtd: MTD device structure |
527 | * @timeo: Timeout | |
2af7c653 SK |
528 | * |
529 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
530 | * context. | |
531 | */ | |
532 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
533 | { | |
534 | struct nand_chip *chip = mtd->priv; | |
535 | int i; | |
536 | ||
537 | /* Wait for the device to get ready */ | |
538 | for (i = 0; i < timeo; i++) { | |
539 | if (chip->dev_ready(mtd)) | |
540 | break; | |
541 | touch_softlockup_watchdog(); | |
542 | mdelay(1); | |
543 | } | |
544 | } | |
545 | ||
7854d3f7 | 546 | /* Wait for the ready pin, after a command. The timeout is caught later. */ |
4b648b02 | 547 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 548 | { |
ace4dfee | 549 | struct nand_chip *chip = mtd->priv; |
ca6a2489 | 550 | unsigned long timeo = jiffies + msecs_to_jiffies(20); |
3b88775c | 551 | |
2af7c653 SK |
552 | /* 400ms timeout */ |
553 | if (in_interrupt() || oops_in_progress) | |
554 | return panic_nand_wait_ready(mtd, 400); | |
555 | ||
8fe833c1 | 556 | led_trigger_event(nand_led_trigger, LED_FULL); |
7854d3f7 | 557 | /* Wait until command is processed or timeout occurs */ |
3b88775c | 558 | do { |
ace4dfee | 559 | if (chip->dev_ready(mtd)) |
8fe833c1 | 560 | break; |
8446f1d3 | 561 | touch_softlockup_watchdog(); |
61b03bd7 | 562 | } while (time_before(jiffies, timeo)); |
8fe833c1 | 563 | led_trigger_event(nand_led_trigger, LED_OFF); |
3b88775c | 564 | } |
4b648b02 | 565 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 566 | |
60c70d66 RQ |
567 | /** |
568 | * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands. | |
569 | * @mtd: MTD device structure | |
570 | * @timeo: Timeout in ms | |
571 | * | |
572 | * Wait for status ready (i.e. command done) or timeout. | |
573 | */ | |
574 | static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo) | |
575 | { | |
576 | register struct nand_chip *chip = mtd->priv; | |
577 | ||
578 | timeo = jiffies + msecs_to_jiffies(timeo); | |
579 | do { | |
580 | if ((chip->read_byte(mtd) & NAND_STATUS_READY)) | |
581 | break; | |
582 | touch_softlockup_watchdog(); | |
583 | } while (time_before(jiffies, timeo)); | |
584 | }; | |
585 | ||
1da177e4 LT |
586 | /** |
587 | * nand_command - [DEFAULT] Send command to NAND device | |
8b6e50c9 BN |
588 | * @mtd: MTD device structure |
589 | * @command: the command to be sent | |
590 | * @column: the column address for this command, -1 if none | |
591 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 592 | * |
8b6e50c9 | 593 | * Send command to NAND device. This function is used for small page devices |
51148f1f | 594 | * (512 Bytes per page). |
1da177e4 | 595 | */ |
7abd3ef9 TG |
596 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
597 | int column, int page_addr) | |
1da177e4 | 598 | { |
ace4dfee | 599 | register struct nand_chip *chip = mtd->priv; |
7abd3ef9 | 600 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 601 | |
8b6e50c9 | 602 | /* Write out the command to the device */ |
1da177e4 LT |
603 | if (command == NAND_CMD_SEQIN) { |
604 | int readcmd; | |
605 | ||
28318776 | 606 | if (column >= mtd->writesize) { |
1da177e4 | 607 | /* OOB area */ |
28318776 | 608 | column -= mtd->writesize; |
1da177e4 LT |
609 | readcmd = NAND_CMD_READOOB; |
610 | } else if (column < 256) { | |
611 | /* First 256 bytes --> READ0 */ | |
612 | readcmd = NAND_CMD_READ0; | |
613 | } else { | |
614 | column -= 256; | |
615 | readcmd = NAND_CMD_READ1; | |
616 | } | |
ace4dfee | 617 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 618 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 619 | } |
ace4dfee | 620 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 621 | |
8b6e50c9 | 622 | /* Address cycle, when necessary */ |
7abd3ef9 TG |
623 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; |
624 | /* Serially input address */ | |
625 | if (column != -1) { | |
626 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
627 | if (chip->options & NAND_BUSWIDTH_16 && |
628 | !nand_opcode_8bits(command)) | |
7abd3ef9 | 629 | column >>= 1; |
ace4dfee | 630 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
631 | ctrl &= ~NAND_CTRL_CHANGE; |
632 | } | |
633 | if (page_addr != -1) { | |
ace4dfee | 634 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 635 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 636 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 637 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
638 | if (chip->chipsize > (32 << 20)) |
639 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 640 | } |
ace4dfee | 641 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
642 | |
643 | /* | |
8b6e50c9 BN |
644 | * Program and erase have their own busy handlers status and sequential |
645 | * in needs no delay | |
e0c7d767 | 646 | */ |
1da177e4 | 647 | switch (command) { |
61b03bd7 | 648 | |
1da177e4 LT |
649 | case NAND_CMD_PAGEPROG: |
650 | case NAND_CMD_ERASE1: | |
651 | case NAND_CMD_ERASE2: | |
652 | case NAND_CMD_SEQIN: | |
653 | case NAND_CMD_STATUS: | |
654 | return; | |
655 | ||
656 | case NAND_CMD_RESET: | |
ace4dfee | 657 | if (chip->dev_ready) |
1da177e4 | 658 | break; |
ace4dfee TG |
659 | udelay(chip->chip_delay); |
660 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 661 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
662 | chip->cmd_ctrl(mtd, |
663 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
60c70d66 RQ |
664 | /* EZ-NAND can take upto 250ms as per ONFi v4.0 */ |
665 | nand_wait_status_ready(mtd, 250); | |
1da177e4 LT |
666 | return; |
667 | ||
e0c7d767 | 668 | /* This applies to read commands */ |
1da177e4 | 669 | default: |
61b03bd7 | 670 | /* |
1da177e4 LT |
671 | * If we don't have access to the busy pin, we apply the given |
672 | * command delay | |
e0c7d767 | 673 | */ |
ace4dfee TG |
674 | if (!chip->dev_ready) { |
675 | udelay(chip->chip_delay); | |
1da177e4 | 676 | return; |
61b03bd7 | 677 | } |
1da177e4 | 678 | } |
8b6e50c9 BN |
679 | /* |
680 | * Apply this short delay always to ensure that we do wait tWB in | |
681 | * any case on any machine. | |
682 | */ | |
e0c7d767 | 683 | ndelay(100); |
3b88775c TG |
684 | |
685 | nand_wait_ready(mtd); | |
1da177e4 LT |
686 | } |
687 | ||
688 | /** | |
689 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
8b6e50c9 BN |
690 | * @mtd: MTD device structure |
691 | * @command: the command to be sent | |
692 | * @column: the column address for this command, -1 if none | |
693 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 694 | * |
7abd3ef9 | 695 | * Send command to NAND device. This is the version for the new large page |
7854d3f7 BN |
696 | * devices. We don't have the separate regions as we have in the small page |
697 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 698 | */ |
7abd3ef9 TG |
699 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
700 | int column, int page_addr) | |
1da177e4 | 701 | { |
ace4dfee | 702 | register struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
703 | |
704 | /* Emulate NAND_CMD_READOOB */ | |
705 | if (command == NAND_CMD_READOOB) { | |
28318776 | 706 | column += mtd->writesize; |
1da177e4 LT |
707 | command = NAND_CMD_READ0; |
708 | } | |
61b03bd7 | 709 | |
7abd3ef9 | 710 | /* Command latch cycle */ |
fb066ada | 711 | chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
712 | |
713 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 714 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
715 | |
716 | /* Serially input address */ | |
717 | if (column != -1) { | |
718 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
719 | if (chip->options & NAND_BUSWIDTH_16 && |
720 | !nand_opcode_8bits(command)) | |
1da177e4 | 721 | column >>= 1; |
ace4dfee | 722 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 723 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 724 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 725 | } |
1da177e4 | 726 | if (page_addr != -1) { |
ace4dfee TG |
727 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
728 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 729 | NAND_NCE | NAND_ALE); |
1da177e4 | 730 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
731 | if (chip->chipsize > (128 << 20)) |
732 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 733 | NAND_NCE | NAND_ALE); |
1da177e4 | 734 | } |
1da177e4 | 735 | } |
ace4dfee | 736 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
737 | |
738 | /* | |
8b6e50c9 | 739 | * Program and erase have their own busy handlers status, sequential |
7a442f17 | 740 | * in and status need no delay. |
30f464b7 | 741 | */ |
1da177e4 | 742 | switch (command) { |
61b03bd7 | 743 | |
1da177e4 LT |
744 | case NAND_CMD_CACHEDPROG: |
745 | case NAND_CMD_PAGEPROG: | |
746 | case NAND_CMD_ERASE1: | |
747 | case NAND_CMD_ERASE2: | |
748 | case NAND_CMD_SEQIN: | |
7bc3312b | 749 | case NAND_CMD_RNDIN: |
1da177e4 | 750 | case NAND_CMD_STATUS: |
30f464b7 | 751 | return; |
1da177e4 LT |
752 | |
753 | case NAND_CMD_RESET: | |
ace4dfee | 754 | if (chip->dev_ready) |
1da177e4 | 755 | break; |
ace4dfee | 756 | udelay(chip->chip_delay); |
12efdde3 TG |
757 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
758 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
759 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
760 | NAND_NCE | NAND_CTRL_CHANGE); | |
60c70d66 RQ |
761 | /* EZ-NAND can take upto 250ms as per ONFi v4.0 */ |
762 | nand_wait_status_ready(mtd, 250); | |
1da177e4 LT |
763 | return; |
764 | ||
7bc3312b TG |
765 | case NAND_CMD_RNDOUT: |
766 | /* No ready / busy check necessary */ | |
767 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
768 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
769 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
770 | NAND_NCE | NAND_CTRL_CHANGE); | |
771 | return; | |
772 | ||
1da177e4 | 773 | case NAND_CMD_READ0: |
12efdde3 TG |
774 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
775 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
776 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
777 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 778 | |
e0c7d767 | 779 | /* This applies to read commands */ |
1da177e4 | 780 | default: |
61b03bd7 | 781 | /* |
1da177e4 | 782 | * If we don't have access to the busy pin, we apply the given |
8b6e50c9 | 783 | * command delay. |
e0c7d767 | 784 | */ |
ace4dfee TG |
785 | if (!chip->dev_ready) { |
786 | udelay(chip->chip_delay); | |
1da177e4 | 787 | return; |
61b03bd7 | 788 | } |
1da177e4 | 789 | } |
3b88775c | 790 | |
8b6e50c9 BN |
791 | /* |
792 | * Apply this short delay always to ensure that we do wait tWB in | |
793 | * any case on any machine. | |
794 | */ | |
e0c7d767 | 795 | ndelay(100); |
3b88775c TG |
796 | |
797 | nand_wait_ready(mtd); | |
1da177e4 LT |
798 | } |
799 | ||
2af7c653 SK |
800 | /** |
801 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
802 | * @chip: the nand chip descriptor |
803 | * @mtd: MTD device structure | |
804 | * @new_state: the state which is requested | |
2af7c653 SK |
805 | * |
806 | * Used when in panic, no locks are taken. | |
807 | */ | |
808 | static void panic_nand_get_device(struct nand_chip *chip, | |
809 | struct mtd_info *mtd, int new_state) | |
810 | { | |
7854d3f7 | 811 | /* Hardware controller shared among independent devices */ |
2af7c653 SK |
812 | chip->controller->active = chip; |
813 | chip->state = new_state; | |
814 | } | |
815 | ||
1da177e4 LT |
816 | /** |
817 | * nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
818 | * @mtd: MTD device structure |
819 | * @new_state: the state which is requested | |
1da177e4 LT |
820 | * |
821 | * Get the device and lock it for exclusive access | |
822 | */ | |
2c0a2bed | 823 | static int |
6a8214aa | 824 | nand_get_device(struct mtd_info *mtd, int new_state) |
1da177e4 | 825 | { |
6a8214aa | 826 | struct nand_chip *chip = mtd->priv; |
ace4dfee TG |
827 | spinlock_t *lock = &chip->controller->lock; |
828 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 829 | DECLARE_WAITQUEUE(wait, current); |
7351d3a5 | 830 | retry: |
0dfc6246 TG |
831 | spin_lock(lock); |
832 | ||
b8b3ee9a | 833 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
834 | if (!chip->controller->active) |
835 | chip->controller->active = chip; | |
a36ed299 | 836 | |
ace4dfee TG |
837 | if (chip->controller->active == chip && chip->state == FL_READY) { |
838 | chip->state = new_state; | |
0dfc6246 | 839 | spin_unlock(lock); |
962034f4 VW |
840 | return 0; |
841 | } | |
842 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
843 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
844 | chip->state = FL_PM_SUSPENDED; | |
845 | spin_unlock(lock); | |
846 | return 0; | |
6b0d9a84 | 847 | } |
0dfc6246 TG |
848 | } |
849 | set_current_state(TASK_UNINTERRUPTIBLE); | |
850 | add_wait_queue(wq, &wait); | |
851 | spin_unlock(lock); | |
852 | schedule(); | |
853 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
854 | goto retry; |
855 | } | |
856 | ||
2af7c653 | 857 | /** |
8b6e50c9 BN |
858 | * panic_nand_wait - [GENERIC] wait until the command is done |
859 | * @mtd: MTD device structure | |
860 | * @chip: NAND chip structure | |
861 | * @timeo: timeout | |
2af7c653 SK |
862 | * |
863 | * Wait for command done. This is a helper function for nand_wait used when | |
864 | * we are in interrupt context. May happen when in panic and trying to write | |
b595076a | 865 | * an oops through mtdoops. |
2af7c653 SK |
866 | */ |
867 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
868 | unsigned long timeo) | |
869 | { | |
870 | int i; | |
871 | for (i = 0; i < timeo; i++) { | |
872 | if (chip->dev_ready) { | |
873 | if (chip->dev_ready(mtd)) | |
874 | break; | |
875 | } else { | |
876 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
877 | break; | |
878 | } | |
879 | mdelay(1); | |
f8ac0414 | 880 | } |
2af7c653 SK |
881 | } |
882 | ||
1da177e4 | 883 | /** |
8b6e50c9 BN |
884 | * nand_wait - [DEFAULT] wait until the command is done |
885 | * @mtd: MTD device structure | |
886 | * @chip: NAND chip structure | |
1da177e4 | 887 | * |
8b6e50c9 BN |
888 | * Wait for command done. This applies to erase and program only. Erase can |
889 | * take up to 400ms and program up to 20ms according to general NAND and | |
890 | * SmartMedia specs. | |
844d3b42 | 891 | */ |
7bc3312b | 892 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
893 | { |
894 | ||
7bc3312b | 895 | int status, state = chip->state; |
6d2559f8 | 896 | unsigned long timeo = (state == FL_ERASING ? 400 : 20); |
1da177e4 | 897 | |
8fe833c1 RP |
898 | led_trigger_event(nand_led_trigger, LED_FULL); |
899 | ||
8b6e50c9 BN |
900 | /* |
901 | * Apply this short delay always to ensure that we do wait tWB in any | |
902 | * case on any machine. | |
903 | */ | |
e0c7d767 | 904 | ndelay(100); |
1da177e4 | 905 | |
14c65786 | 906 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 907 | |
2af7c653 SK |
908 | if (in_interrupt() || oops_in_progress) |
909 | panic_nand_wait(mtd, chip, timeo); | |
910 | else { | |
6d2559f8 | 911 | timeo = jiffies + msecs_to_jiffies(timeo); |
2af7c653 SK |
912 | while (time_before(jiffies, timeo)) { |
913 | if (chip->dev_ready) { | |
914 | if (chip->dev_ready(mtd)) | |
915 | break; | |
916 | } else { | |
917 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
918 | break; | |
919 | } | |
920 | cond_resched(); | |
1da177e4 | 921 | } |
1da177e4 | 922 | } |
8fe833c1 RP |
923 | led_trigger_event(nand_led_trigger, LED_OFF); |
924 | ||
ace4dfee | 925 | status = (int)chip->read_byte(mtd); |
f251b8df MC |
926 | /* This can happen if in case of timeout or buggy dev_ready */ |
927 | WARN_ON(!(status & NAND_STATUS_READY)); | |
1da177e4 LT |
928 | return status; |
929 | } | |
930 | ||
7d70f334 | 931 | /** |
b6d676db | 932 | * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
933 | * @mtd: mtd info |
934 | * @ofs: offset to start unlock from | |
935 | * @len: length to unlock | |
8b6e50c9 BN |
936 | * @invert: when = 0, unlock the range of blocks within the lower and |
937 | * upper boundary address | |
938 | * when = 1, unlock the range of blocks outside the boundaries | |
939 | * of the lower and upper boundary address | |
7d70f334 | 940 | * |
8b6e50c9 | 941 | * Returs unlock status. |
7d70f334 VS |
942 | */ |
943 | static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, | |
944 | uint64_t len, int invert) | |
945 | { | |
946 | int ret = 0; | |
947 | int status, page; | |
948 | struct nand_chip *chip = mtd->priv; | |
949 | ||
950 | /* Submit address of first page to unlock */ | |
951 | page = ofs >> chip->page_shift; | |
952 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); | |
953 | ||
954 | /* Submit address of last page to unlock */ | |
955 | page = (ofs + len) >> chip->page_shift; | |
956 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, | |
957 | (page | invert) & chip->pagemask); | |
958 | ||
959 | /* Call wait ready function */ | |
960 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 961 | /* See if device thinks it succeeded */ |
74830966 | 962 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 963 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
964 | __func__, status); |
965 | ret = -EIO; | |
966 | } | |
967 | ||
968 | return ret; | |
969 | } | |
970 | ||
971 | /** | |
b6d676db | 972 | * nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
973 | * @mtd: mtd info |
974 | * @ofs: offset to start unlock from | |
975 | * @len: length to unlock | |
7d70f334 | 976 | * |
8b6e50c9 | 977 | * Returns unlock status. |
7d70f334 VS |
978 | */ |
979 | int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
980 | { | |
981 | int ret = 0; | |
982 | int chipnr; | |
983 | struct nand_chip *chip = mtd->priv; | |
984 | ||
289c0522 | 985 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
986 | __func__, (unsigned long long)ofs, len); |
987 | ||
988 | if (check_offs_len(mtd, ofs, len)) | |
b1a2348a | 989 | return -EINVAL; |
7d70f334 VS |
990 | |
991 | /* Align to last block address if size addresses end of the device */ | |
992 | if (ofs + len == mtd->size) | |
993 | len -= mtd->erasesize; | |
994 | ||
6a8214aa | 995 | nand_get_device(mtd, FL_UNLOCKING); |
7d70f334 VS |
996 | |
997 | /* Shift to get chip number */ | |
998 | chipnr = ofs >> chip->chip_shift; | |
999 | ||
1000 | chip->select_chip(mtd, chipnr); | |
1001 | ||
57d3a9a8 WD |
1002 | /* |
1003 | * Reset the chip. | |
1004 | * If we want to check the WP through READ STATUS and check the bit 7 | |
1005 | * we must reset the chip | |
1006 | * some operation can also clear the bit 7 of status register | |
1007 | * eg. erase/program a locked block | |
1008 | */ | |
1009 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1010 | ||
7d70f334 VS |
1011 | /* Check, if it is write protected */ |
1012 | if (nand_check_wp(mtd)) { | |
289c0522 | 1013 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
1014 | __func__); |
1015 | ret = -EIO; | |
1016 | goto out; | |
1017 | } | |
1018 | ||
1019 | ret = __nand_unlock(mtd, ofs, len, 0); | |
1020 | ||
1021 | out: | |
b0bb6903 | 1022 | chip->select_chip(mtd, -1); |
7d70f334 VS |
1023 | nand_release_device(mtd); |
1024 | ||
1025 | return ret; | |
1026 | } | |
7351d3a5 | 1027 | EXPORT_SYMBOL(nand_unlock); |
7d70f334 VS |
1028 | |
1029 | /** | |
b6d676db | 1030 | * nand_lock - [REPLACEABLE] locks all blocks present in the device |
b6d676db RD |
1031 | * @mtd: mtd info |
1032 | * @ofs: offset to start unlock from | |
1033 | * @len: length to unlock | |
7d70f334 | 1034 | * |
8b6e50c9 BN |
1035 | * This feature is not supported in many NAND parts. 'Micron' NAND parts do |
1036 | * have this feature, but it allows only to lock all blocks, not for specified | |
1037 | * range for block. Implementing 'lock' feature by making use of 'unlock', for | |
1038 | * now. | |
7d70f334 | 1039 | * |
8b6e50c9 | 1040 | * Returns lock status. |
7d70f334 VS |
1041 | */ |
1042 | int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
1043 | { | |
1044 | int ret = 0; | |
1045 | int chipnr, status, page; | |
1046 | struct nand_chip *chip = mtd->priv; | |
1047 | ||
289c0522 | 1048 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
1049 | __func__, (unsigned long long)ofs, len); |
1050 | ||
1051 | if (check_offs_len(mtd, ofs, len)) | |
b1a2348a | 1052 | return -EINVAL; |
7d70f334 | 1053 | |
6a8214aa | 1054 | nand_get_device(mtd, FL_LOCKING); |
7d70f334 VS |
1055 | |
1056 | /* Shift to get chip number */ | |
1057 | chipnr = ofs >> chip->chip_shift; | |
1058 | ||
1059 | chip->select_chip(mtd, chipnr); | |
1060 | ||
57d3a9a8 WD |
1061 | /* |
1062 | * Reset the chip. | |
1063 | * If we want to check the WP through READ STATUS and check the bit 7 | |
1064 | * we must reset the chip | |
1065 | * some operation can also clear the bit 7 of status register | |
1066 | * eg. erase/program a locked block | |
1067 | */ | |
1068 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1069 | ||
7d70f334 VS |
1070 | /* Check, if it is write protected */ |
1071 | if (nand_check_wp(mtd)) { | |
289c0522 | 1072 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
1073 | __func__); |
1074 | status = MTD_ERASE_FAILED; | |
1075 | ret = -EIO; | |
1076 | goto out; | |
1077 | } | |
1078 | ||
1079 | /* Submit address of first page to lock */ | |
1080 | page = ofs >> chip->page_shift; | |
1081 | chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); | |
1082 | ||
1083 | /* Call wait ready function */ | |
1084 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 1085 | /* See if device thinks it succeeded */ |
74830966 | 1086 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 1087 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
1088 | __func__, status); |
1089 | ret = -EIO; | |
1090 | goto out; | |
1091 | } | |
1092 | ||
1093 | ret = __nand_unlock(mtd, ofs, len, 0x1); | |
1094 | ||
1095 | out: | |
b0bb6903 | 1096 | chip->select_chip(mtd, -1); |
7d70f334 VS |
1097 | nand_release_device(mtd); |
1098 | ||
1099 | return ret; | |
1100 | } | |
7351d3a5 | 1101 | EXPORT_SYMBOL(nand_lock); |
7d70f334 | 1102 | |
730a43fb BB |
1103 | /** |
1104 | * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data | |
1105 | * @buf: buffer to test | |
1106 | * @len: buffer length | |
1107 | * @bitflips_threshold: maximum number of bitflips | |
1108 | * | |
1109 | * Check if a buffer contains only 0xff, which means the underlying region | |
1110 | * has been erased and is ready to be programmed. | |
1111 | * The bitflips_threshold specify the maximum number of bitflips before | |
1112 | * considering the region is not erased. | |
1113 | * Note: The logic of this function has been extracted from the memweight | |
1114 | * implementation, except that nand_check_erased_buf function exit before | |
1115 | * testing the whole buffer if the number of bitflips exceed the | |
1116 | * bitflips_threshold value. | |
1117 | * | |
1118 | * Returns a positive number of bitflips less than or equal to | |
1119 | * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the | |
1120 | * threshold. | |
1121 | */ | |
1122 | static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold) | |
1123 | { | |
1124 | const unsigned char *bitmap = buf; | |
1125 | int bitflips = 0; | |
1126 | int weight; | |
1127 | ||
1128 | for (; len && ((uintptr_t)bitmap) % sizeof(long); | |
1129 | len--, bitmap++) { | |
1130 | weight = hweight8(*bitmap); | |
1131 | bitflips += BITS_PER_BYTE - weight; | |
1132 | if (unlikely(bitflips > bitflips_threshold)) | |
1133 | return -EBADMSG; | |
1134 | } | |
1135 | ||
1136 | for (; len >= sizeof(long); | |
1137 | len -= sizeof(long), bitmap += sizeof(long)) { | |
1138 | weight = hweight_long(*((unsigned long *)bitmap)); | |
1139 | bitflips += BITS_PER_LONG - weight; | |
1140 | if (unlikely(bitflips > bitflips_threshold)) | |
1141 | return -EBADMSG; | |
1142 | } | |
1143 | ||
1144 | for (; len > 0; len--, bitmap++) { | |
1145 | weight = hweight8(*bitmap); | |
1146 | bitflips += BITS_PER_BYTE - weight; | |
1147 | if (unlikely(bitflips > bitflips_threshold)) | |
1148 | return -EBADMSG; | |
1149 | } | |
1150 | ||
1151 | return bitflips; | |
1152 | } | |
1153 | ||
1154 | /** | |
1155 | * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only | |
1156 | * 0xff data | |
1157 | * @data: data buffer to test | |
1158 | * @datalen: data length | |
1159 | * @ecc: ECC buffer | |
1160 | * @ecclen: ECC length | |
1161 | * @extraoob: extra OOB buffer | |
1162 | * @extraooblen: extra OOB length | |
1163 | * @bitflips_threshold: maximum number of bitflips | |
1164 | * | |
1165 | * Check if a data buffer and its associated ECC and OOB data contains only | |
1166 | * 0xff pattern, which means the underlying region has been erased and is | |
1167 | * ready to be programmed. | |
1168 | * The bitflips_threshold specify the maximum number of bitflips before | |
1169 | * considering the region as not erased. | |
1170 | * | |
1171 | * Note: | |
1172 | * 1/ ECC algorithms are working on pre-defined block sizes which are usually | |
1173 | * different from the NAND page size. When fixing bitflips, ECC engines will | |
1174 | * report the number of errors per chunk, and the NAND core infrastructure | |
1175 | * expect you to return the maximum number of bitflips for the whole page. | |
1176 | * This is why you should always use this function on a single chunk and | |
1177 | * not on the whole page. After checking each chunk you should update your | |
1178 | * max_bitflips value accordingly. | |
1179 | * 2/ When checking for bitflips in erased pages you should not only check | |
1180 | * the payload data but also their associated ECC data, because a user might | |
1181 | * have programmed almost all bits to 1 but a few. In this case, we | |
1182 | * shouldn't consider the chunk as erased, and checking ECC bytes prevent | |
1183 | * this case. | |
1184 | * 3/ The extraoob argument is optional, and should be used if some of your OOB | |
1185 | * data are protected by the ECC engine. | |
1186 | * It could also be used if you support subpages and want to attach some | |
1187 | * extra OOB data to an ECC chunk. | |
1188 | * | |
1189 | * Returns a positive number of bitflips less than or equal to | |
1190 | * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the | |
1191 | * threshold. In case of success, the passed buffers are filled with 0xff. | |
1192 | */ | |
1193 | int nand_check_erased_ecc_chunk(void *data, int datalen, | |
1194 | void *ecc, int ecclen, | |
1195 | void *extraoob, int extraooblen, | |
1196 | int bitflips_threshold) | |
1197 | { | |
1198 | int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0; | |
1199 | ||
1200 | data_bitflips = nand_check_erased_buf(data, datalen, | |
1201 | bitflips_threshold); | |
1202 | if (data_bitflips < 0) | |
1203 | return data_bitflips; | |
1204 | ||
1205 | bitflips_threshold -= data_bitflips; | |
1206 | ||
1207 | ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold); | |
1208 | if (ecc_bitflips < 0) | |
1209 | return ecc_bitflips; | |
1210 | ||
1211 | bitflips_threshold -= ecc_bitflips; | |
1212 | ||
1213 | extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen, | |
1214 | bitflips_threshold); | |
1215 | if (extraoob_bitflips < 0) | |
1216 | return extraoob_bitflips; | |
1217 | ||
1218 | if (data_bitflips) | |
1219 | memset(data, 0xff, datalen); | |
1220 | ||
1221 | if (ecc_bitflips) | |
1222 | memset(ecc, 0xff, ecclen); | |
1223 | ||
1224 | if (extraoob_bitflips) | |
1225 | memset(extraoob, 0xff, extraooblen); | |
1226 | ||
1227 | return data_bitflips + ecc_bitflips + extraoob_bitflips; | |
1228 | } | |
1229 | EXPORT_SYMBOL(nand_check_erased_ecc_chunk); | |
1230 | ||
8593fbc6 | 1231 | /** |
7854d3f7 | 1232 | * nand_read_page_raw - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1233 | * @mtd: mtd info structure |
1234 | * @chip: nand chip info structure | |
1235 | * @buf: buffer to store read data | |
1fbb938d | 1236 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1237 | * @page: page number to read |
52ff49df | 1238 | * |
7854d3f7 | 1239 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 TG |
1240 | */ |
1241 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1242 | uint8_t *buf, int oob_required, int page) |
8593fbc6 TG |
1243 | { |
1244 | chip->read_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
1245 | if (oob_required) |
1246 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
8593fbc6 TG |
1247 | return 0; |
1248 | } | |
1249 | ||
52ff49df | 1250 | /** |
7854d3f7 | 1251 | * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1252 | * @mtd: mtd info structure |
1253 | * @chip: nand chip info structure | |
1254 | * @buf: buffer to store read data | |
1fbb938d | 1255 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1256 | * @page: page number to read |
52ff49df DB |
1257 | * |
1258 | * We need a special oob layout and handling even when OOB isn't used. | |
1259 | */ | |
7351d3a5 | 1260 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
1261 | struct nand_chip *chip, uint8_t *buf, |
1262 | int oob_required, int page) | |
52ff49df DB |
1263 | { |
1264 | int eccsize = chip->ecc.size; | |
1265 | int eccbytes = chip->ecc.bytes; | |
1266 | uint8_t *oob = chip->oob_poi; | |
1267 | int steps, size; | |
1268 | ||
1269 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1270 | chip->read_buf(mtd, buf, eccsize); | |
1271 | buf += eccsize; | |
1272 | ||
1273 | if (chip->ecc.prepad) { | |
1274 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1275 | oob += chip->ecc.prepad; | |
1276 | } | |
1277 | ||
1278 | chip->read_buf(mtd, oob, eccbytes); | |
1279 | oob += eccbytes; | |
1280 | ||
1281 | if (chip->ecc.postpad) { | |
1282 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1283 | oob += chip->ecc.postpad; | |
1284 | } | |
1285 | } | |
1286 | ||
1287 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1288 | if (size) | |
1289 | chip->read_buf(mtd, oob, size); | |
1290 | ||
1291 | return 0; | |
1292 | } | |
1293 | ||
1da177e4 | 1294 | /** |
7854d3f7 | 1295 | * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function |
8b6e50c9 BN |
1296 | * @mtd: mtd info structure |
1297 | * @chip: nand chip info structure | |
1298 | * @buf: buffer to store read data | |
1fbb938d | 1299 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1300 | * @page: page number to read |
068e3c0a | 1301 | */ |
f5bbdacc | 1302 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1303 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1304 | { |
f5bbdacc TG |
1305 | int i, eccsize = chip->ecc.size; |
1306 | int eccbytes = chip->ecc.bytes; | |
1307 | int eccsteps = chip->ecc.steps; | |
1308 | uint8_t *p = buf; | |
4bf63fcb DW |
1309 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1310 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1311 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1312 | unsigned int max_bitflips = 0; |
f5bbdacc | 1313 | |
1fbb938d | 1314 | chip->ecc.read_page_raw(mtd, chip, buf, 1, page); |
f5bbdacc TG |
1315 | |
1316 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1317 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1318 | ||
1319 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 1320 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
1321 | |
1322 | eccsteps = chip->ecc.steps; | |
1323 | p = buf; | |
1324 | ||
1325 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1326 | int stat; | |
1327 | ||
1328 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
3f91e94f | 1329 | if (stat < 0) { |
f5bbdacc | 1330 | mtd->ecc_stats.failed++; |
3f91e94f | 1331 | } else { |
f5bbdacc | 1332 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1333 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1334 | } | |
f5bbdacc | 1335 | } |
3f91e94f | 1336 | return max_bitflips; |
22c60f5f | 1337 | } |
1da177e4 | 1338 | |
3d459559 | 1339 | /** |
837a6ba4 | 1340 | * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function |
8b6e50c9 BN |
1341 | * @mtd: mtd info structure |
1342 | * @chip: nand chip info structure | |
1343 | * @data_offs: offset of requested data within the page | |
1344 | * @readlen: data length | |
1345 | * @bufpoi: buffer to store read data | |
e004debd | 1346 | * @page: page number to read |
3d459559 | 1347 | */ |
7351d3a5 | 1348 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, |
e004debd HS |
1349 | uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi, |
1350 | int page) | |
3d459559 AK |
1351 | { |
1352 | int start_step, end_step, num_steps; | |
1353 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1354 | uint8_t *p; | |
1355 | int data_col_addr, i, gaps = 0; | |
1356 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
1357 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
4a4163ca | 1358 | int index; |
3f91e94f | 1359 | unsigned int max_bitflips = 0; |
3d459559 | 1360 | |
7854d3f7 | 1361 | /* Column address within the page aligned to ECC size (256bytes) */ |
3d459559 AK |
1362 | start_step = data_offs / chip->ecc.size; |
1363 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
1364 | num_steps = end_step - start_step + 1; | |
4a4163ca | 1365 | index = start_step * chip->ecc.bytes; |
3d459559 | 1366 | |
8b6e50c9 | 1367 | /* Data size aligned to ECC ecc.size */ |
3d459559 AK |
1368 | datafrag_len = num_steps * chip->ecc.size; |
1369 | eccfrag_len = num_steps * chip->ecc.bytes; | |
1370 | ||
1371 | data_col_addr = start_step * chip->ecc.size; | |
1372 | /* If we read not a page aligned data */ | |
1373 | if (data_col_addr != 0) | |
1374 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); | |
1375 | ||
1376 | p = bufpoi + data_col_addr; | |
1377 | chip->read_buf(mtd, p, datafrag_len); | |
1378 | ||
8b6e50c9 | 1379 | /* Calculate ECC */ |
3d459559 AK |
1380 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) |
1381 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); | |
1382 | ||
8b6e50c9 BN |
1383 | /* |
1384 | * The performance is faster if we position offsets according to | |
7854d3f7 | 1385 | * ecc.pos. Let's make sure that there are no gaps in ECC positions. |
8b6e50c9 | 1386 | */ |
3d459559 | 1387 | for (i = 0; i < eccfrag_len - 1; i++) { |
47570bb1 | 1388 | if (eccpos[i + index] + 1 != eccpos[i + index + 1]) { |
3d459559 AK |
1389 | gaps = 1; |
1390 | break; | |
1391 | } | |
1392 | } | |
1393 | if (gaps) { | |
1394 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1395 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1396 | } else { | |
8b6e50c9 | 1397 | /* |
7854d3f7 | 1398 | * Send the command to read the particular ECC bytes take care |
8b6e50c9 BN |
1399 | * about buswidth alignment in read_buf. |
1400 | */ | |
7351d3a5 | 1401 | aligned_pos = eccpos[index] & ~(busw - 1); |
3d459559 | 1402 | aligned_len = eccfrag_len; |
7351d3a5 | 1403 | if (eccpos[index] & (busw - 1)) |
3d459559 | 1404 | aligned_len++; |
7351d3a5 | 1405 | if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1)) |
3d459559 AK |
1406 | aligned_len++; |
1407 | ||
7351d3a5 FF |
1408 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, |
1409 | mtd->writesize + aligned_pos, -1); | |
3d459559 AK |
1410 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); |
1411 | } | |
1412 | ||
1413 | for (i = 0; i < eccfrag_len; i++) | |
7351d3a5 | 1414 | chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]]; |
3d459559 AK |
1415 | |
1416 | p = bufpoi + data_col_addr; | |
1417 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
1418 | int stat; | |
1419 | ||
7351d3a5 FF |
1420 | stat = chip->ecc.correct(mtd, p, |
1421 | &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); | |
3f91e94f | 1422 | if (stat < 0) { |
3d459559 | 1423 | mtd->ecc_stats.failed++; |
3f91e94f | 1424 | } else { |
3d459559 | 1425 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1426 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1427 | } | |
3d459559 | 1428 | } |
3f91e94f | 1429 | return max_bitflips; |
3d459559 AK |
1430 | } |
1431 | ||
068e3c0a | 1432 | /** |
7854d3f7 | 1433 | * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function |
8b6e50c9 BN |
1434 | * @mtd: mtd info structure |
1435 | * @chip: nand chip info structure | |
1436 | * @buf: buffer to store read data | |
1fbb938d | 1437 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1438 | * @page: page number to read |
068e3c0a | 1439 | * |
7854d3f7 | 1440 | * Not for syndrome calculating ECC controllers which need a special oob layout. |
068e3c0a | 1441 | */ |
f5bbdacc | 1442 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1443 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1444 | { |
f5bbdacc TG |
1445 | int i, eccsize = chip->ecc.size; |
1446 | int eccbytes = chip->ecc.bytes; | |
1447 | int eccsteps = chip->ecc.steps; | |
1448 | uint8_t *p = buf; | |
4bf63fcb DW |
1449 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1450 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1451 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1452 | unsigned int max_bitflips = 0; |
f5bbdacc TG |
1453 | |
1454 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1455 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1456 | chip->read_buf(mtd, p, eccsize); | |
1457 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 1458 | } |
f75e5097 | 1459 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 1460 | |
f5bbdacc | 1461 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 1462 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 1463 | |
f5bbdacc TG |
1464 | eccsteps = chip->ecc.steps; |
1465 | p = buf; | |
61b03bd7 | 1466 | |
f5bbdacc TG |
1467 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1468 | int stat; | |
1da177e4 | 1469 | |
f5bbdacc | 1470 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
3f91e94f | 1471 | if (stat < 0) { |
f5bbdacc | 1472 | mtd->ecc_stats.failed++; |
3f91e94f | 1473 | } else { |
f5bbdacc | 1474 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1475 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1476 | } | |
f5bbdacc | 1477 | } |
3f91e94f | 1478 | return max_bitflips; |
f5bbdacc | 1479 | } |
1da177e4 | 1480 | |
6e0cb135 | 1481 | /** |
7854d3f7 | 1482 | * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first |
8b6e50c9 BN |
1483 | * @mtd: mtd info structure |
1484 | * @chip: nand chip info structure | |
1485 | * @buf: buffer to store read data | |
1fbb938d | 1486 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1487 | * @page: page number to read |
6e0cb135 | 1488 | * |
8b6e50c9 BN |
1489 | * Hardware ECC for large page chips, require OOB to be read first. For this |
1490 | * ECC mode, the write_page method is re-used from ECC_HW. These methods | |
1491 | * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with | |
1492 | * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from | |
1493 | * the data area, by overwriting the NAND manufacturer bad block markings. | |
6e0cb135 SN |
1494 | */ |
1495 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1fbb938d | 1496 | struct nand_chip *chip, uint8_t *buf, int oob_required, int page) |
6e0cb135 SN |
1497 | { |
1498 | int i, eccsize = chip->ecc.size; | |
1499 | int eccbytes = chip->ecc.bytes; | |
1500 | int eccsteps = chip->ecc.steps; | |
1501 | uint8_t *p = buf; | |
1502 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1503 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1504 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
3f91e94f | 1505 | unsigned int max_bitflips = 0; |
6e0cb135 SN |
1506 | |
1507 | /* Read the OOB area first */ | |
1508 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1509 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1510 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1511 | ||
1512 | for (i = 0; i < chip->ecc.total; i++) | |
1513 | ecc_code[i] = chip->oob_poi[eccpos[i]]; | |
1514 | ||
1515 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1516 | int stat; | |
1517 | ||
1518 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1519 | chip->read_buf(mtd, p, eccsize); | |
1520 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1521 | ||
1522 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
3f91e94f | 1523 | if (stat < 0) { |
6e0cb135 | 1524 | mtd->ecc_stats.failed++; |
3f91e94f | 1525 | } else { |
6e0cb135 | 1526 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1527 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1528 | } | |
6e0cb135 | 1529 | } |
3f91e94f | 1530 | return max_bitflips; |
6e0cb135 SN |
1531 | } |
1532 | ||
f5bbdacc | 1533 | /** |
7854d3f7 | 1534 | * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read |
8b6e50c9 BN |
1535 | * @mtd: mtd info structure |
1536 | * @chip: nand chip info structure | |
1537 | * @buf: buffer to store read data | |
1fbb938d | 1538 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1539 | * @page: page number to read |
f5bbdacc | 1540 | * |
8b6e50c9 BN |
1541 | * The hw generator calculates the error syndrome automatically. Therefore we |
1542 | * need a special oob layout and handling. | |
f5bbdacc TG |
1543 | */ |
1544 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1545 | uint8_t *buf, int oob_required, int page) |
f5bbdacc TG |
1546 | { |
1547 | int i, eccsize = chip->ecc.size; | |
1548 | int eccbytes = chip->ecc.bytes; | |
1549 | int eccsteps = chip->ecc.steps; | |
1550 | uint8_t *p = buf; | |
f75e5097 | 1551 | uint8_t *oob = chip->oob_poi; |
3f91e94f | 1552 | unsigned int max_bitflips = 0; |
1da177e4 | 1553 | |
f5bbdacc TG |
1554 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1555 | int stat; | |
61b03bd7 | 1556 | |
f5bbdacc TG |
1557 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
1558 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 1559 | |
f5bbdacc TG |
1560 | if (chip->ecc.prepad) { |
1561 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1562 | oob += chip->ecc.prepad; | |
1563 | } | |
1da177e4 | 1564 | |
f5bbdacc TG |
1565 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1566 | chip->read_buf(mtd, oob, eccbytes); | |
1567 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 1568 | |
3f91e94f | 1569 | if (stat < 0) { |
f5bbdacc | 1570 | mtd->ecc_stats.failed++; |
3f91e94f | 1571 | } else { |
f5bbdacc | 1572 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1573 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1574 | } | |
61b03bd7 | 1575 | |
f5bbdacc | 1576 | oob += eccbytes; |
1da177e4 | 1577 | |
f5bbdacc TG |
1578 | if (chip->ecc.postpad) { |
1579 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1580 | oob += chip->ecc.postpad; | |
61b03bd7 | 1581 | } |
f5bbdacc | 1582 | } |
1da177e4 | 1583 | |
f5bbdacc | 1584 | /* Calculate remaining oob bytes */ |
7e4178f9 | 1585 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
1586 | if (i) |
1587 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 1588 | |
3f91e94f | 1589 | return max_bitflips; |
f5bbdacc | 1590 | } |
1da177e4 | 1591 | |
f5bbdacc | 1592 | /** |
7854d3f7 | 1593 | * nand_transfer_oob - [INTERN] Transfer oob to client buffer |
8b6e50c9 BN |
1594 | * @chip: nand chip structure |
1595 | * @oob: oob destination address | |
1596 | * @ops: oob ops structure | |
1597 | * @len: size of oob to transfer | |
8593fbc6 TG |
1598 | */ |
1599 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, | |
7014568b | 1600 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 1601 | { |
f8ac0414 | 1602 | switch (ops->mode) { |
8593fbc6 | 1603 | |
0612b9dd BN |
1604 | case MTD_OPS_PLACE_OOB: |
1605 | case MTD_OPS_RAW: | |
8593fbc6 TG |
1606 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); |
1607 | return oob + len; | |
1608 | ||
0612b9dd | 1609 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 1610 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
1611 | uint32_t boffs = 0, roffs = ops->ooboffs; |
1612 | size_t bytes = 0; | |
8593fbc6 | 1613 | |
f8ac0414 | 1614 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 1615 | /* Read request not from offset 0? */ |
7bc3312b TG |
1616 | if (unlikely(roffs)) { |
1617 | if (roffs >= free->length) { | |
1618 | roffs -= free->length; | |
1619 | continue; | |
1620 | } | |
1621 | boffs = free->offset + roffs; | |
1622 | bytes = min_t(size_t, len, | |
1623 | (free->length - roffs)); | |
1624 | roffs = 0; | |
1625 | } else { | |
1626 | bytes = min_t(size_t, len, free->length); | |
1627 | boffs = free->offset; | |
1628 | } | |
1629 | memcpy(oob, chip->oob_poi + boffs, bytes); | |
8593fbc6 TG |
1630 | oob += bytes; |
1631 | } | |
1632 | return oob; | |
1633 | } | |
1634 | default: | |
1635 | BUG(); | |
1636 | } | |
1637 | return NULL; | |
1638 | } | |
1639 | ||
ba84fb59 BN |
1640 | /** |
1641 | * nand_setup_read_retry - [INTERN] Set the READ RETRY mode | |
1642 | * @mtd: MTD device structure | |
1643 | * @retry_mode: the retry mode to use | |
1644 | * | |
1645 | * Some vendors supply a special command to shift the Vt threshold, to be used | |
1646 | * when there are too many bitflips in a page (i.e., ECC error). After setting | |
1647 | * a new threshold, the host should retry reading the page. | |
1648 | */ | |
1649 | static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) | |
1650 | { | |
1651 | struct nand_chip *chip = mtd->priv; | |
1652 | ||
1653 | pr_debug("setting READ RETRY mode %d\n", retry_mode); | |
1654 | ||
1655 | if (retry_mode >= chip->read_retries) | |
1656 | return -EINVAL; | |
1657 | ||
1658 | if (!chip->setup_read_retry) | |
1659 | return -EOPNOTSUPP; | |
1660 | ||
1661 | return chip->setup_read_retry(mtd, retry_mode); | |
1662 | } | |
1663 | ||
8593fbc6 | 1664 | /** |
7854d3f7 | 1665 | * nand_do_read_ops - [INTERN] Read data with ECC |
8b6e50c9 BN |
1666 | * @mtd: MTD device structure |
1667 | * @from: offset to read from | |
1668 | * @ops: oob ops structure | |
f5bbdacc TG |
1669 | * |
1670 | * Internal function. Called with chip held. | |
1671 | */ | |
8593fbc6 TG |
1672 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
1673 | struct mtd_oob_ops *ops) | |
f5bbdacc | 1674 | { |
e47f3db4 | 1675 | int chipnr, page, realpage, col, bytes, aligned, oob_required; |
f5bbdacc | 1676 | struct nand_chip *chip = mtd->priv; |
f5bbdacc | 1677 | int ret = 0; |
8593fbc6 | 1678 | uint32_t readlen = ops->len; |
7014568b | 1679 | uint32_t oobreadlen = ops->ooblen; |
0612b9dd | 1680 | uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ? |
9aca334e ML |
1681 | mtd->oobavail : mtd->oobsize; |
1682 | ||
8593fbc6 | 1683 | uint8_t *bufpoi, *oob, *buf; |
66507c7b | 1684 | int use_bufpoi; |
edbc4540 | 1685 | unsigned int max_bitflips = 0; |
ba84fb59 | 1686 | int retry_mode = 0; |
b72f3dfb | 1687 | bool ecc_fail = false; |
1da177e4 | 1688 | |
f5bbdacc TG |
1689 | chipnr = (int)(from >> chip->chip_shift); |
1690 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 1691 | |
f5bbdacc TG |
1692 | realpage = (int)(from >> chip->page_shift); |
1693 | page = realpage & chip->pagemask; | |
1da177e4 | 1694 | |
f5bbdacc | 1695 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 1696 | |
8593fbc6 TG |
1697 | buf = ops->datbuf; |
1698 | oob = ops->oobbuf; | |
e47f3db4 | 1699 | oob_required = oob ? 1 : 0; |
8593fbc6 | 1700 | |
f8ac0414 | 1701 | while (1) { |
b72f3dfb BN |
1702 | unsigned int ecc_failures = mtd->ecc_stats.failed; |
1703 | ||
f5bbdacc TG |
1704 | bytes = min(mtd->writesize - col, readlen); |
1705 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 1706 | |
66507c7b KD |
1707 | if (!aligned) |
1708 | use_bufpoi = 1; | |
1709 | else if (chip->options & NAND_USE_BOUNCE_BUFFER) | |
1710 | use_bufpoi = !virt_addr_valid(buf); | |
1711 | else | |
1712 | use_bufpoi = 0; | |
1713 | ||
8b6e50c9 | 1714 | /* Is the current page in the buffer? */ |
8593fbc6 | 1715 | if (realpage != chip->pagebuf || oob) { |
66507c7b KD |
1716 | bufpoi = use_bufpoi ? chip->buffers->databuf : buf; |
1717 | ||
1718 | if (use_bufpoi && aligned) | |
1719 | pr_debug("%s: using read bounce buffer for buf@%p\n", | |
1720 | __func__, buf); | |
61b03bd7 | 1721 | |
ba84fb59 | 1722 | read_retry: |
c00a0991 | 1723 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); |
1da177e4 | 1724 | |
edbc4540 MD |
1725 | /* |
1726 | * Now read the page into the buffer. Absent an error, | |
1727 | * the read methods return max bitflips per ecc step. | |
1728 | */ | |
0612b9dd | 1729 | if (unlikely(ops->mode == MTD_OPS_RAW)) |
1fbb938d | 1730 | ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, |
e47f3db4 BN |
1731 | oob_required, |
1732 | page); | |
a5ff4f10 JW |
1733 | else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && |
1734 | !oob) | |
7351d3a5 | 1735 | ret = chip->ecc.read_subpage(mtd, chip, |
e004debd HS |
1736 | col, bytes, bufpoi, |
1737 | page); | |
956e944c | 1738 | else |
46a8cf2d | 1739 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
e47f3db4 | 1740 | oob_required, page); |
6d77b9d0 | 1741 | if (ret < 0) { |
66507c7b | 1742 | if (use_bufpoi) |
6d77b9d0 BN |
1743 | /* Invalidate page cache */ |
1744 | chip->pagebuf = -1; | |
1da177e4 | 1745 | break; |
6d77b9d0 | 1746 | } |
f5bbdacc | 1747 | |
edbc4540 MD |
1748 | max_bitflips = max_t(unsigned int, max_bitflips, ret); |
1749 | ||
f5bbdacc | 1750 | /* Transfer not aligned data */ |
66507c7b | 1751 | if (use_bufpoi) { |
a5ff4f10 | 1752 | if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && |
b72f3dfb | 1753 | !(mtd->ecc_stats.failed - ecc_failures) && |
edbc4540 | 1754 | (ops->mode != MTD_OPS_RAW)) { |
3d459559 | 1755 | chip->pagebuf = realpage; |
edbc4540 MD |
1756 | chip->pagebuf_bitflips = ret; |
1757 | } else { | |
6d77b9d0 BN |
1758 | /* Invalidate page cache */ |
1759 | chip->pagebuf = -1; | |
edbc4540 | 1760 | } |
4bf63fcb | 1761 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
1762 | } |
1763 | ||
8593fbc6 | 1764 | if (unlikely(oob)) { |
b64d39d8 ML |
1765 | int toread = min(oobreadlen, max_oobsize); |
1766 | ||
1767 | if (toread) { | |
1768 | oob = nand_transfer_oob(chip, | |
1769 | oob, ops, toread); | |
1770 | oobreadlen -= toread; | |
1771 | } | |
8593fbc6 | 1772 | } |
5bc7c33c BN |
1773 | |
1774 | if (chip->options & NAND_NEED_READRDY) { | |
1775 | /* Apply delay or wait for ready/busy pin */ | |
1776 | if (!chip->dev_ready) | |
1777 | udelay(chip->chip_delay); | |
1778 | else | |
1779 | nand_wait_ready(mtd); | |
1780 | } | |
b72f3dfb | 1781 | |
ba84fb59 | 1782 | if (mtd->ecc_stats.failed - ecc_failures) { |
28fa65e6 | 1783 | if (retry_mode + 1 < chip->read_retries) { |
ba84fb59 BN |
1784 | retry_mode++; |
1785 | ret = nand_setup_read_retry(mtd, | |
1786 | retry_mode); | |
1787 | if (ret < 0) | |
1788 | break; | |
1789 | ||
1790 | /* Reset failures; retry */ | |
1791 | mtd->ecc_stats.failed = ecc_failures; | |
1792 | goto read_retry; | |
1793 | } else { | |
1794 | /* No more retry modes; real failure */ | |
1795 | ecc_fail = true; | |
1796 | } | |
1797 | } | |
1798 | ||
1799 | buf += bytes; | |
8593fbc6 | 1800 | } else { |
4bf63fcb | 1801 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 | 1802 | buf += bytes; |
edbc4540 MD |
1803 | max_bitflips = max_t(unsigned int, max_bitflips, |
1804 | chip->pagebuf_bitflips); | |
8593fbc6 | 1805 | } |
1da177e4 | 1806 | |
f5bbdacc | 1807 | readlen -= bytes; |
61b03bd7 | 1808 | |
ba84fb59 BN |
1809 | /* Reset to retry mode 0 */ |
1810 | if (retry_mode) { | |
1811 | ret = nand_setup_read_retry(mtd, 0); | |
1812 | if (ret < 0) | |
1813 | break; | |
1814 | retry_mode = 0; | |
1815 | } | |
1816 | ||
f5bbdacc | 1817 | if (!readlen) |
61b03bd7 | 1818 | break; |
1da177e4 | 1819 | |
8b6e50c9 | 1820 | /* For subsequent reads align to page boundary */ |
1da177e4 LT |
1821 | col = 0; |
1822 | /* Increment page address */ | |
1823 | realpage++; | |
1824 | ||
ace4dfee | 1825 | page = realpage & chip->pagemask; |
1da177e4 LT |
1826 | /* Check, if we cross a chip boundary */ |
1827 | if (!page) { | |
1828 | chipnr++; | |
ace4dfee TG |
1829 | chip->select_chip(mtd, -1); |
1830 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1831 | } |
1da177e4 | 1832 | } |
b0bb6903 | 1833 | chip->select_chip(mtd, -1); |
1da177e4 | 1834 | |
8593fbc6 | 1835 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
1836 | if (oob) |
1837 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 1838 | |
3f91e94f | 1839 | if (ret < 0) |
f5bbdacc TG |
1840 | return ret; |
1841 | ||
b72f3dfb | 1842 | if (ecc_fail) |
9a1fcdfd TG |
1843 | return -EBADMSG; |
1844 | ||
edbc4540 | 1845 | return max_bitflips; |
f5bbdacc TG |
1846 | } |
1847 | ||
1848 | /** | |
25985edc | 1849 | * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc |
8b6e50c9 BN |
1850 | * @mtd: MTD device structure |
1851 | * @from: offset to read from | |
1852 | * @len: number of bytes to read | |
1853 | * @retlen: pointer to variable to store the number of read bytes | |
1854 | * @buf: the databuffer to put data | |
f5bbdacc | 1855 | * |
8b6e50c9 | 1856 | * Get hold of the chip and call nand_do_read. |
f5bbdacc TG |
1857 | */ |
1858 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1859 | size_t *retlen, uint8_t *buf) | |
1860 | { | |
4a89ff88 | 1861 | struct mtd_oob_ops ops; |
f5bbdacc TG |
1862 | int ret; |
1863 | ||
6a8214aa | 1864 | nand_get_device(mtd, FL_READING); |
0ec56dc4 | 1865 | memset(&ops, 0, sizeof(ops)); |
4a89ff88 BN |
1866 | ops.len = len; |
1867 | ops.datbuf = buf; | |
11041ae6 | 1868 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 1869 | ret = nand_do_read_ops(mtd, from, &ops); |
4a89ff88 | 1870 | *retlen = ops.retlen; |
f5bbdacc | 1871 | nand_release_device(mtd); |
f5bbdacc | 1872 | return ret; |
1da177e4 LT |
1873 | } |
1874 | ||
7bc3312b | 1875 | /** |
7854d3f7 | 1876 | * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function |
8b6e50c9 BN |
1877 | * @mtd: mtd info structure |
1878 | * @chip: nand chip info structure | |
1879 | * @page: page number to read | |
7bc3312b TG |
1880 | */ |
1881 | static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1882 | int page) |
7bc3312b | 1883 | { |
5c2ffb11 | 1884 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); |
7bc3312b | 1885 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
5c2ffb11 | 1886 | return 0; |
7bc3312b TG |
1887 | } |
1888 | ||
1889 | /** | |
7854d3f7 | 1890 | * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC |
7bc3312b | 1891 | * with syndromes |
8b6e50c9 BN |
1892 | * @mtd: mtd info structure |
1893 | * @chip: nand chip info structure | |
1894 | * @page: page number to read | |
7bc3312b TG |
1895 | */ |
1896 | static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1897 | int page) |
7bc3312b | 1898 | { |
7bc3312b TG |
1899 | int length = mtd->oobsize; |
1900 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1901 | int eccsize = chip->ecc.size; | |
2ea69d21 | 1902 | uint8_t *bufpoi = chip->oob_poi; |
7bc3312b TG |
1903 | int i, toread, sndrnd = 0, pos; |
1904 | ||
1905 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
1906 | for (i = 0; i < chip->ecc.steps; i++) { | |
1907 | if (sndrnd) { | |
1908 | pos = eccsize + i * (eccsize + chunk); | |
1909 | if (mtd->writesize > 512) | |
1910 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
1911 | else | |
1912 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
1913 | } else | |
1914 | sndrnd = 1; | |
1915 | toread = min_t(int, length, chunk); | |
1916 | chip->read_buf(mtd, bufpoi, toread); | |
1917 | bufpoi += toread; | |
1918 | length -= toread; | |
1919 | } | |
1920 | if (length > 0) | |
1921 | chip->read_buf(mtd, bufpoi, length); | |
1922 | ||
5c2ffb11 | 1923 | return 0; |
7bc3312b TG |
1924 | } |
1925 | ||
1926 | /** | |
7854d3f7 | 1927 | * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function |
8b6e50c9 BN |
1928 | * @mtd: mtd info structure |
1929 | * @chip: nand chip info structure | |
1930 | * @page: page number to write | |
7bc3312b TG |
1931 | */ |
1932 | static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1933 | int page) | |
1934 | { | |
1935 | int status = 0; | |
1936 | const uint8_t *buf = chip->oob_poi; | |
1937 | int length = mtd->oobsize; | |
1938 | ||
1939 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
1940 | chip->write_buf(mtd, buf, length); | |
1941 | /* Send command to program the OOB data */ | |
1942 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1943 | ||
1944 | status = chip->waitfunc(mtd, chip); | |
1945 | ||
0d420f9d | 1946 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b TG |
1947 | } |
1948 | ||
1949 | /** | |
7854d3f7 | 1950 | * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC |
8b6e50c9 BN |
1951 | * with syndrome - only for large page flash |
1952 | * @mtd: mtd info structure | |
1953 | * @chip: nand chip info structure | |
1954 | * @page: page number to write | |
7bc3312b TG |
1955 | */ |
1956 | static int nand_write_oob_syndrome(struct mtd_info *mtd, | |
1957 | struct nand_chip *chip, int page) | |
1958 | { | |
1959 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1960 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
1961 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
1962 | const uint8_t *bufpoi = chip->oob_poi; | |
1963 | ||
1964 | /* | |
1965 | * data-ecc-data-ecc ... ecc-oob | |
1966 | * or | |
1967 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
1968 | */ | |
1969 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
1970 | pos = steps * (eccsize + chunk); | |
1971 | steps = 0; | |
1972 | } else | |
8b0036ee | 1973 | pos = eccsize; |
7bc3312b TG |
1974 | |
1975 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
1976 | for (i = 0; i < steps; i++) { | |
1977 | if (sndcmd) { | |
1978 | if (mtd->writesize <= 512) { | |
1979 | uint32_t fill = 0xFFFFFFFF; | |
1980 | ||
1981 | len = eccsize; | |
1982 | while (len > 0) { | |
1983 | int num = min_t(int, len, 4); | |
1984 | chip->write_buf(mtd, (uint8_t *)&fill, | |
1985 | num); | |
1986 | len -= num; | |
1987 | } | |
1988 | } else { | |
1989 | pos = eccsize + i * (eccsize + chunk); | |
1990 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
1991 | } | |
1992 | } else | |
1993 | sndcmd = 1; | |
1994 | len = min_t(int, length, chunk); | |
1995 | chip->write_buf(mtd, bufpoi, len); | |
1996 | bufpoi += len; | |
1997 | length -= len; | |
1998 | } | |
1999 | if (length > 0) | |
2000 | chip->write_buf(mtd, bufpoi, length); | |
2001 | ||
2002 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
2003 | status = chip->waitfunc(mtd, chip); | |
2004 | ||
2005 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
2006 | } | |
2007 | ||
1da177e4 | 2008 | /** |
7854d3f7 | 2009 | * nand_do_read_oob - [INTERN] NAND read out-of-band |
8b6e50c9 BN |
2010 | * @mtd: MTD device structure |
2011 | * @from: offset to read from | |
2012 | * @ops: oob operations description structure | |
1da177e4 | 2013 | * |
8b6e50c9 | 2014 | * NAND read out-of-band data from the spare area. |
1da177e4 | 2015 | */ |
8593fbc6 TG |
2016 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
2017 | struct mtd_oob_ops *ops) | |
1da177e4 | 2018 | { |
c00a0991 | 2019 | int page, realpage, chipnr; |
ace4dfee | 2020 | struct nand_chip *chip = mtd->priv; |
041e4575 | 2021 | struct mtd_ecc_stats stats; |
7014568b VW |
2022 | int readlen = ops->ooblen; |
2023 | int len; | |
7bc3312b | 2024 | uint8_t *buf = ops->oobbuf; |
1951f2f7 | 2025 | int ret = 0; |
61b03bd7 | 2026 | |
289c0522 | 2027 | pr_debug("%s: from = 0x%08Lx, len = %i\n", |
20d8e248 | 2028 | __func__, (unsigned long long)from, readlen); |
1da177e4 | 2029 | |
041e4575 BN |
2030 | stats = mtd->ecc_stats; |
2031 | ||
0612b9dd | 2032 | if (ops->mode == MTD_OPS_AUTO_OOB) |
7014568b | 2033 | len = chip->ecc.layout->oobavail; |
03736155 AH |
2034 | else |
2035 | len = mtd->oobsize; | |
2036 | ||
2037 | if (unlikely(ops->ooboffs >= len)) { | |
289c0522 BN |
2038 | pr_debug("%s: attempt to start read outside oob\n", |
2039 | __func__); | |
03736155 AH |
2040 | return -EINVAL; |
2041 | } | |
2042 | ||
2043 | /* Do not allow reads past end of device */ | |
2044 | if (unlikely(from >= mtd->size || | |
2045 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
2046 | (from >> chip->page_shift)) * len)) { | |
289c0522 BN |
2047 | pr_debug("%s: attempt to read beyond end of device\n", |
2048 | __func__); | |
03736155 AH |
2049 | return -EINVAL; |
2050 | } | |
7014568b | 2051 | |
7314e9e7 | 2052 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 2053 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2054 | |
7314e9e7 TG |
2055 | /* Shift to get page */ |
2056 | realpage = (int)(from >> chip->page_shift); | |
2057 | page = realpage & chip->pagemask; | |
1da177e4 | 2058 | |
f8ac0414 | 2059 | while (1) { |
0612b9dd | 2060 | if (ops->mode == MTD_OPS_RAW) |
1951f2f7 | 2061 | ret = chip->ecc.read_oob_raw(mtd, chip, page); |
c46f6483 | 2062 | else |
1951f2f7 SL |
2063 | ret = chip->ecc.read_oob(mtd, chip, page); |
2064 | ||
2065 | if (ret < 0) | |
2066 | break; | |
7014568b VW |
2067 | |
2068 | len = min(len, readlen); | |
2069 | buf = nand_transfer_oob(chip, buf, ops, len); | |
8593fbc6 | 2070 | |
5bc7c33c BN |
2071 | if (chip->options & NAND_NEED_READRDY) { |
2072 | /* Apply delay or wait for ready/busy pin */ | |
2073 | if (!chip->dev_ready) | |
2074 | udelay(chip->chip_delay); | |
2075 | else | |
2076 | nand_wait_ready(mtd); | |
2077 | } | |
2078 | ||
7014568b | 2079 | readlen -= len; |
0d420f9d SZ |
2080 | if (!readlen) |
2081 | break; | |
2082 | ||
7314e9e7 TG |
2083 | /* Increment page address */ |
2084 | realpage++; | |
2085 | ||
2086 | page = realpage & chip->pagemask; | |
2087 | /* Check, if we cross a chip boundary */ | |
2088 | if (!page) { | |
2089 | chipnr++; | |
2090 | chip->select_chip(mtd, -1); | |
2091 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2092 | } |
2093 | } | |
b0bb6903 | 2094 | chip->select_chip(mtd, -1); |
1da177e4 | 2095 | |
1951f2f7 SL |
2096 | ops->oobretlen = ops->ooblen - readlen; |
2097 | ||
2098 | if (ret < 0) | |
2099 | return ret; | |
041e4575 BN |
2100 | |
2101 | if (mtd->ecc_stats.failed - stats.failed) | |
2102 | return -EBADMSG; | |
2103 | ||
2104 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
1da177e4 LT |
2105 | } |
2106 | ||
2107 | /** | |
8593fbc6 | 2108 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
8b6e50c9 BN |
2109 | * @mtd: MTD device structure |
2110 | * @from: offset to read from | |
2111 | * @ops: oob operation description structure | |
1da177e4 | 2112 | * |
8b6e50c9 | 2113 | * NAND read data and/or out-of-band data. |
1da177e4 | 2114 | */ |
8593fbc6 TG |
2115 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
2116 | struct mtd_oob_ops *ops) | |
1da177e4 | 2117 | { |
8593fbc6 TG |
2118 | int ret = -ENOTSUPP; |
2119 | ||
2120 | ops->retlen = 0; | |
1da177e4 LT |
2121 | |
2122 | /* Do not allow reads past end of device */ | |
7014568b | 2123 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
289c0522 BN |
2124 | pr_debug("%s: attempt to read beyond end of device\n", |
2125 | __func__); | |
1da177e4 LT |
2126 | return -EINVAL; |
2127 | } | |
2128 | ||
6a8214aa | 2129 | nand_get_device(mtd, FL_READING); |
1da177e4 | 2130 | |
f8ac0414 | 2131 | switch (ops->mode) { |
0612b9dd BN |
2132 | case MTD_OPS_PLACE_OOB: |
2133 | case MTD_OPS_AUTO_OOB: | |
2134 | case MTD_OPS_RAW: | |
8593fbc6 | 2135 | break; |
1da177e4 | 2136 | |
8593fbc6 TG |
2137 | default: |
2138 | goto out; | |
2139 | } | |
1da177e4 | 2140 | |
8593fbc6 TG |
2141 | if (!ops->datbuf) |
2142 | ret = nand_do_read_oob(mtd, from, ops); | |
2143 | else | |
2144 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 2145 | |
7351d3a5 | 2146 | out: |
8593fbc6 TG |
2147 | nand_release_device(mtd); |
2148 | return ret; | |
2149 | } | |
61b03bd7 | 2150 | |
1da177e4 | 2151 | |
8593fbc6 | 2152 | /** |
7854d3f7 | 2153 | * nand_write_page_raw - [INTERN] raw page write function |
8b6e50c9 BN |
2154 | * @mtd: mtd info structure |
2155 | * @chip: nand chip info structure | |
2156 | * @buf: data buffer | |
1fbb938d | 2157 | * @oob_required: must write chip->oob_poi to OOB |
52ff49df | 2158 | * |
7854d3f7 | 2159 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 | 2160 | */ |
fdbad98d | 2161 | static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 2162 | const uint8_t *buf, int oob_required) |
8593fbc6 TG |
2163 | { |
2164 | chip->write_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
2165 | if (oob_required) |
2166 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
2167 | |
2168 | return 0; | |
1da177e4 LT |
2169 | } |
2170 | ||
52ff49df | 2171 | /** |
7854d3f7 | 2172 | * nand_write_page_raw_syndrome - [INTERN] raw page write function |
8b6e50c9 BN |
2173 | * @mtd: mtd info structure |
2174 | * @chip: nand chip info structure | |
2175 | * @buf: data buffer | |
1fbb938d | 2176 | * @oob_required: must write chip->oob_poi to OOB |
52ff49df DB |
2177 | * |
2178 | * We need a special oob layout and handling even when ECC isn't checked. | |
2179 | */ | |
fdbad98d | 2180 | static int nand_write_page_raw_syndrome(struct mtd_info *mtd, |
7351d3a5 | 2181 | struct nand_chip *chip, |
1fbb938d | 2182 | const uint8_t *buf, int oob_required) |
52ff49df DB |
2183 | { |
2184 | int eccsize = chip->ecc.size; | |
2185 | int eccbytes = chip->ecc.bytes; | |
2186 | uint8_t *oob = chip->oob_poi; | |
2187 | int steps, size; | |
2188 | ||
2189 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
2190 | chip->write_buf(mtd, buf, eccsize); | |
2191 | buf += eccsize; | |
2192 | ||
2193 | if (chip->ecc.prepad) { | |
2194 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2195 | oob += chip->ecc.prepad; | |
2196 | } | |
2197 | ||
60c3bc1f | 2198 | chip->write_buf(mtd, oob, eccbytes); |
52ff49df DB |
2199 | oob += eccbytes; |
2200 | ||
2201 | if (chip->ecc.postpad) { | |
2202 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2203 | oob += chip->ecc.postpad; | |
2204 | } | |
2205 | } | |
2206 | ||
2207 | size = mtd->oobsize - (oob - chip->oob_poi); | |
2208 | if (size) | |
2209 | chip->write_buf(mtd, oob, size); | |
fdbad98d JW |
2210 | |
2211 | return 0; | |
52ff49df | 2212 | } |
9223a456 | 2213 | /** |
7854d3f7 | 2214 | * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function |
8b6e50c9 BN |
2215 | * @mtd: mtd info structure |
2216 | * @chip: nand chip info structure | |
2217 | * @buf: data buffer | |
1fbb938d | 2218 | * @oob_required: must write chip->oob_poi to OOB |
9223a456 | 2219 | */ |
fdbad98d | 2220 | static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 2221 | const uint8_t *buf, int oob_required) |
9223a456 | 2222 | { |
f75e5097 TG |
2223 | int i, eccsize = chip->ecc.size; |
2224 | int eccbytes = chip->ecc.bytes; | |
2225 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2226 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2227 | const uint8_t *p = buf; |
8b099a39 | 2228 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 2229 | |
7854d3f7 | 2230 | /* Software ECC calculation */ |
8593fbc6 TG |
2231 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
2232 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 2233 | |
8593fbc6 TG |
2234 | for (i = 0; i < chip->ecc.total; i++) |
2235 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 | 2236 | |
fdbad98d | 2237 | return chip->ecc.write_page_raw(mtd, chip, buf, 1); |
f75e5097 | 2238 | } |
9223a456 | 2239 | |
f75e5097 | 2240 | /** |
7854d3f7 | 2241 | * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function |
8b6e50c9 BN |
2242 | * @mtd: mtd info structure |
2243 | * @chip: nand chip info structure | |
2244 | * @buf: data buffer | |
1fbb938d | 2245 | * @oob_required: must write chip->oob_poi to OOB |
f75e5097 | 2246 | */ |
fdbad98d | 2247 | static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 2248 | const uint8_t *buf, int oob_required) |
f75e5097 TG |
2249 | { |
2250 | int i, eccsize = chip->ecc.size; | |
2251 | int eccbytes = chip->ecc.bytes; | |
2252 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2253 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2254 | const uint8_t *p = buf; |
8b099a39 | 2255 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 2256 | |
f75e5097 TG |
2257 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
2258 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 2259 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 2260 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
2261 | } |
2262 | ||
f75e5097 TG |
2263 | for (i = 0; i < chip->ecc.total; i++) |
2264 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
2265 | ||
2266 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
2267 | |
2268 | return 0; | |
9223a456 TG |
2269 | } |
2270 | ||
837a6ba4 GP |
2271 | |
2272 | /** | |
73c8aaf4 | 2273 | * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write |
837a6ba4 GP |
2274 | * @mtd: mtd info structure |
2275 | * @chip: nand chip info structure | |
d6a95080 | 2276 | * @offset: column address of subpage within the page |
837a6ba4 | 2277 | * @data_len: data length |
d6a95080 | 2278 | * @buf: data buffer |
837a6ba4 GP |
2279 | * @oob_required: must write chip->oob_poi to OOB |
2280 | */ | |
2281 | static int nand_write_subpage_hwecc(struct mtd_info *mtd, | |
2282 | struct nand_chip *chip, uint32_t offset, | |
d6a95080 | 2283 | uint32_t data_len, const uint8_t *buf, |
837a6ba4 GP |
2284 | int oob_required) |
2285 | { | |
2286 | uint8_t *oob_buf = chip->oob_poi; | |
2287 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
2288 | int ecc_size = chip->ecc.size; | |
2289 | int ecc_bytes = chip->ecc.bytes; | |
2290 | int ecc_steps = chip->ecc.steps; | |
2291 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
2292 | uint32_t start_step = offset / ecc_size; | |
2293 | uint32_t end_step = (offset + data_len - 1) / ecc_size; | |
2294 | int oob_bytes = mtd->oobsize / ecc_steps; | |
2295 | int step, i; | |
2296 | ||
2297 | for (step = 0; step < ecc_steps; step++) { | |
2298 | /* configure controller for WRITE access */ | |
2299 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
2300 | ||
2301 | /* write data (untouched subpages already masked by 0xFF) */ | |
d6a95080 | 2302 | chip->write_buf(mtd, buf, ecc_size); |
837a6ba4 GP |
2303 | |
2304 | /* mask ECC of un-touched subpages by padding 0xFF */ | |
2305 | if ((step < start_step) || (step > end_step)) | |
2306 | memset(ecc_calc, 0xff, ecc_bytes); | |
2307 | else | |
d6a95080 | 2308 | chip->ecc.calculate(mtd, buf, ecc_calc); |
837a6ba4 GP |
2309 | |
2310 | /* mask OOB of un-touched subpages by padding 0xFF */ | |
2311 | /* if oob_required, preserve OOB metadata of written subpage */ | |
2312 | if (!oob_required || (step < start_step) || (step > end_step)) | |
2313 | memset(oob_buf, 0xff, oob_bytes); | |
2314 | ||
d6a95080 | 2315 | buf += ecc_size; |
837a6ba4 GP |
2316 | ecc_calc += ecc_bytes; |
2317 | oob_buf += oob_bytes; | |
2318 | } | |
2319 | ||
2320 | /* copy calculated ECC for whole page to chip->buffer->oob */ | |
2321 | /* this include masked-value(0xFF) for unwritten subpages */ | |
2322 | ecc_calc = chip->buffers->ecccalc; | |
2323 | for (i = 0; i < chip->ecc.total; i++) | |
2324 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
2325 | ||
2326 | /* write OOB buffer to NAND device */ | |
2327 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
2328 | ||
2329 | return 0; | |
2330 | } | |
2331 | ||
2332 | ||
61b03bd7 | 2333 | /** |
7854d3f7 | 2334 | * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write |
8b6e50c9 BN |
2335 | * @mtd: mtd info structure |
2336 | * @chip: nand chip info structure | |
2337 | * @buf: data buffer | |
1fbb938d | 2338 | * @oob_required: must write chip->oob_poi to OOB |
1da177e4 | 2339 | * |
8b6e50c9 BN |
2340 | * The hw generator calculates the error syndrome automatically. Therefore we |
2341 | * need a special oob layout and handling. | |
f75e5097 | 2342 | */ |
fdbad98d | 2343 | static int nand_write_page_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
2344 | struct nand_chip *chip, |
2345 | const uint8_t *buf, int oob_required) | |
1da177e4 | 2346 | { |
f75e5097 TG |
2347 | int i, eccsize = chip->ecc.size; |
2348 | int eccbytes = chip->ecc.bytes; | |
2349 | int eccsteps = chip->ecc.steps; | |
2350 | const uint8_t *p = buf; | |
2351 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 2352 | |
f75e5097 | 2353 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 2354 | |
f75e5097 TG |
2355 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
2356 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 2357 | |
f75e5097 TG |
2358 | if (chip->ecc.prepad) { |
2359 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2360 | oob += chip->ecc.prepad; | |
2361 | } | |
2362 | ||
2363 | chip->ecc.calculate(mtd, p, oob); | |
2364 | chip->write_buf(mtd, oob, eccbytes); | |
2365 | oob += eccbytes; | |
2366 | ||
2367 | if (chip->ecc.postpad) { | |
2368 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2369 | oob += chip->ecc.postpad; | |
1da177e4 | 2370 | } |
1da177e4 | 2371 | } |
f75e5097 TG |
2372 | |
2373 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 2374 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
2375 | if (i) |
2376 | chip->write_buf(mtd, oob, i); | |
fdbad98d JW |
2377 | |
2378 | return 0; | |
f75e5097 TG |
2379 | } |
2380 | ||
2381 | /** | |
956e944c | 2382 | * nand_write_page - [REPLACEABLE] write one page |
8b6e50c9 BN |
2383 | * @mtd: MTD device structure |
2384 | * @chip: NAND chip descriptor | |
837a6ba4 GP |
2385 | * @offset: address offset within the page |
2386 | * @data_len: length of actual data to be written | |
8b6e50c9 | 2387 | * @buf: the data to write |
1fbb938d | 2388 | * @oob_required: must write chip->oob_poi to OOB |
8b6e50c9 BN |
2389 | * @page: page number to write |
2390 | * @cached: cached programming | |
2391 | * @raw: use _raw version of write_page | |
f75e5097 TG |
2392 | */ |
2393 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
837a6ba4 GP |
2394 | uint32_t offset, int data_len, const uint8_t *buf, |
2395 | int oob_required, int page, int cached, int raw) | |
f75e5097 | 2396 | { |
837a6ba4 GP |
2397 | int status, subpage; |
2398 | ||
2399 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && | |
2400 | chip->ecc.write_subpage) | |
2401 | subpage = offset || (data_len < mtd->writesize); | |
2402 | else | |
2403 | subpage = 0; | |
f75e5097 TG |
2404 | |
2405 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
2406 | ||
956e944c | 2407 | if (unlikely(raw)) |
837a6ba4 GP |
2408 | status = chip->ecc.write_page_raw(mtd, chip, buf, |
2409 | oob_required); | |
2410 | else if (subpage) | |
2411 | status = chip->ecc.write_subpage(mtd, chip, offset, data_len, | |
2412 | buf, oob_required); | |
956e944c | 2413 | else |
fdbad98d JW |
2414 | status = chip->ecc.write_page(mtd, chip, buf, oob_required); |
2415 | ||
2416 | if (status < 0) | |
2417 | return status; | |
f75e5097 TG |
2418 | |
2419 | /* | |
7854d3f7 | 2420 | * Cached progamming disabled for now. Not sure if it's worth the |
8b6e50c9 | 2421 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s). |
f75e5097 TG |
2422 | */ |
2423 | cached = 0; | |
2424 | ||
3239a6cd | 2425 | if (!cached || !NAND_HAS_CACHEPROG(chip)) { |
f75e5097 TG |
2426 | |
2427 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
7bc3312b | 2428 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2429 | /* |
2430 | * See if operation failed and additional status checks are | |
8b6e50c9 | 2431 | * available. |
f75e5097 TG |
2432 | */ |
2433 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2434 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
2435 | page); | |
2436 | ||
2437 | if (status & NAND_STATUS_FAIL) | |
2438 | return -EIO; | |
2439 | } else { | |
2440 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
7bc3312b | 2441 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2442 | } |
2443 | ||
f75e5097 | 2444 | return 0; |
1da177e4 LT |
2445 | } |
2446 | ||
8593fbc6 | 2447 | /** |
7854d3f7 | 2448 | * nand_fill_oob - [INTERN] Transfer client buffer to oob |
f722013e | 2449 | * @mtd: MTD device structure |
8b6e50c9 BN |
2450 | * @oob: oob data buffer |
2451 | * @len: oob data write length | |
2452 | * @ops: oob ops structure | |
8593fbc6 | 2453 | */ |
f722013e TAA |
2454 | static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, |
2455 | struct mtd_oob_ops *ops) | |
8593fbc6 | 2456 | { |
f722013e TAA |
2457 | struct nand_chip *chip = mtd->priv; |
2458 | ||
2459 | /* | |
2460 | * Initialise to all 0xFF, to avoid the possibility of left over OOB | |
2461 | * data from a previous OOB read. | |
2462 | */ | |
2463 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
2464 | ||
f8ac0414 | 2465 | switch (ops->mode) { |
8593fbc6 | 2466 | |
0612b9dd BN |
2467 | case MTD_OPS_PLACE_OOB: |
2468 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2469 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); |
2470 | return oob + len; | |
2471 | ||
0612b9dd | 2472 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 2473 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
2474 | uint32_t boffs = 0, woffs = ops->ooboffs; |
2475 | size_t bytes = 0; | |
8593fbc6 | 2476 | |
f8ac0414 | 2477 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 2478 | /* Write request not from offset 0? */ |
7bc3312b TG |
2479 | if (unlikely(woffs)) { |
2480 | if (woffs >= free->length) { | |
2481 | woffs -= free->length; | |
2482 | continue; | |
2483 | } | |
2484 | boffs = free->offset + woffs; | |
2485 | bytes = min_t(size_t, len, | |
2486 | (free->length - woffs)); | |
2487 | woffs = 0; | |
2488 | } else { | |
2489 | bytes = min_t(size_t, len, free->length); | |
2490 | boffs = free->offset; | |
2491 | } | |
8b0036ee | 2492 | memcpy(chip->oob_poi + boffs, oob, bytes); |
8593fbc6 TG |
2493 | oob += bytes; |
2494 | } | |
2495 | return oob; | |
2496 | } | |
2497 | default: | |
2498 | BUG(); | |
2499 | } | |
2500 | return NULL; | |
2501 | } | |
2502 | ||
f8ac0414 | 2503 | #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) |
1da177e4 LT |
2504 | |
2505 | /** | |
7854d3f7 | 2506 | * nand_do_write_ops - [INTERN] NAND write with ECC |
8b6e50c9 BN |
2507 | * @mtd: MTD device structure |
2508 | * @to: offset to write to | |
2509 | * @ops: oob operations description structure | |
1da177e4 | 2510 | * |
8b6e50c9 | 2511 | * NAND write with ECC. |
1da177e4 | 2512 | */ |
8593fbc6 TG |
2513 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
2514 | struct mtd_oob_ops *ops) | |
1da177e4 | 2515 | { |
29072b96 | 2516 | int chipnr, realpage, page, blockmask, column; |
ace4dfee | 2517 | struct nand_chip *chip = mtd->priv; |
8593fbc6 | 2518 | uint32_t writelen = ops->len; |
782ce79a ML |
2519 | |
2520 | uint32_t oobwritelen = ops->ooblen; | |
0612b9dd | 2521 | uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ? |
782ce79a ML |
2522 | mtd->oobavail : mtd->oobsize; |
2523 | ||
8593fbc6 TG |
2524 | uint8_t *oob = ops->oobbuf; |
2525 | uint8_t *buf = ops->datbuf; | |
837a6ba4 | 2526 | int ret; |
e47f3db4 | 2527 | int oob_required = oob ? 1 : 0; |
1da177e4 | 2528 | |
8593fbc6 | 2529 | ops->retlen = 0; |
29072b96 TG |
2530 | if (!writelen) |
2531 | return 0; | |
1da177e4 | 2532 | |
8b6e50c9 | 2533 | /* Reject writes, which are not page aligned */ |
8593fbc6 | 2534 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
d0370219 BN |
2535 | pr_notice("%s: attempt to write non page aligned data\n", |
2536 | __func__); | |
1da177e4 LT |
2537 | return -EINVAL; |
2538 | } | |
2539 | ||
29072b96 | 2540 | column = to & (mtd->writesize - 1); |
1da177e4 | 2541 | |
6a930961 TG |
2542 | chipnr = (int)(to >> chip->chip_shift); |
2543 | chip->select_chip(mtd, chipnr); | |
2544 | ||
1da177e4 | 2545 | /* Check, if it is write protected */ |
b0bb6903 HS |
2546 | if (nand_check_wp(mtd)) { |
2547 | ret = -EIO; | |
2548 | goto err_out; | |
2549 | } | |
1da177e4 | 2550 | |
f75e5097 TG |
2551 | realpage = (int)(to >> chip->page_shift); |
2552 | page = realpage & chip->pagemask; | |
2553 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
2554 | ||
2555 | /* Invalidate the page cache, when we write to the cached page */ | |
537ab1bd BN |
2556 | if (to <= ((loff_t)chip->pagebuf << chip->page_shift) && |
2557 | ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len)) | |
ace4dfee | 2558 | chip->pagebuf = -1; |
61b03bd7 | 2559 | |
782ce79a | 2560 | /* Don't allow multipage oob writes with offset */ |
b0bb6903 HS |
2561 | if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { |
2562 | ret = -EINVAL; | |
2563 | goto err_out; | |
2564 | } | |
782ce79a | 2565 | |
f8ac0414 | 2566 | while (1) { |
29072b96 | 2567 | int bytes = mtd->writesize; |
f75e5097 | 2568 | int cached = writelen > bytes && page != blockmask; |
29072b96 | 2569 | uint8_t *wbuf = buf; |
66507c7b KD |
2570 | int use_bufpoi; |
2571 | int part_pagewr = (column || writelen < (mtd->writesize - 1)); | |
2572 | ||
2573 | if (part_pagewr) | |
2574 | use_bufpoi = 1; | |
2575 | else if (chip->options & NAND_USE_BOUNCE_BUFFER) | |
2576 | use_bufpoi = !virt_addr_valid(buf); | |
2577 | else | |
2578 | use_bufpoi = 0; | |
29072b96 | 2579 | |
66507c7b KD |
2580 | /* Partial page write?, or need to use bounce buffer */ |
2581 | if (use_bufpoi) { | |
2582 | pr_debug("%s: using write bounce buffer for buf@%p\n", | |
2583 | __func__, buf); | |
29072b96 | 2584 | cached = 0; |
66507c7b KD |
2585 | if (part_pagewr) |
2586 | bytes = min_t(int, bytes - column, writelen); | |
29072b96 TG |
2587 | chip->pagebuf = -1; |
2588 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
2589 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
2590 | wbuf = chip->buffers->databuf; | |
2591 | } | |
1da177e4 | 2592 | |
782ce79a ML |
2593 | if (unlikely(oob)) { |
2594 | size_t len = min(oobwritelen, oobmaxlen); | |
f722013e | 2595 | oob = nand_fill_oob(mtd, oob, len, ops); |
782ce79a | 2596 | oobwritelen -= len; |
f722013e TAA |
2597 | } else { |
2598 | /* We still need to erase leftover OOB data */ | |
2599 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
782ce79a | 2600 | } |
837a6ba4 GP |
2601 | ret = chip->write_page(mtd, chip, column, bytes, wbuf, |
2602 | oob_required, page, cached, | |
2603 | (ops->mode == MTD_OPS_RAW)); | |
f75e5097 TG |
2604 | if (ret) |
2605 | break; | |
2606 | ||
2607 | writelen -= bytes; | |
2608 | if (!writelen) | |
2609 | break; | |
2610 | ||
29072b96 | 2611 | column = 0; |
f75e5097 TG |
2612 | buf += bytes; |
2613 | realpage++; | |
2614 | ||
2615 | page = realpage & chip->pagemask; | |
2616 | /* Check, if we cross a chip boundary */ | |
2617 | if (!page) { | |
2618 | chipnr++; | |
2619 | chip->select_chip(mtd, -1); | |
2620 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2621 | } |
2622 | } | |
8593fbc6 | 2623 | |
8593fbc6 | 2624 | ops->retlen = ops->len - writelen; |
7014568b VW |
2625 | if (unlikely(oob)) |
2626 | ops->oobretlen = ops->ooblen; | |
b0bb6903 HS |
2627 | |
2628 | err_out: | |
2629 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
2630 | return ret; |
2631 | } | |
2632 | ||
2af7c653 SK |
2633 | /** |
2634 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
8b6e50c9 BN |
2635 | * @mtd: MTD device structure |
2636 | * @to: offset to write to | |
2637 | * @len: number of bytes to write | |
2638 | * @retlen: pointer to variable to store the number of written bytes | |
2639 | * @buf: the data to write | |
2af7c653 SK |
2640 | * |
2641 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
2642 | * may for example be called by mtdoops when writing an oops while in panic. | |
2643 | */ | |
2644 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
2645 | size_t *retlen, const uint8_t *buf) | |
2646 | { | |
2647 | struct nand_chip *chip = mtd->priv; | |
4a89ff88 | 2648 | struct mtd_oob_ops ops; |
2af7c653 SK |
2649 | int ret; |
2650 | ||
8b6e50c9 | 2651 | /* Wait for the device to get ready */ |
2af7c653 SK |
2652 | panic_nand_wait(mtd, chip, 400); |
2653 | ||
8b6e50c9 | 2654 | /* Grab the device */ |
2af7c653 SK |
2655 | panic_nand_get_device(chip, mtd, FL_WRITING); |
2656 | ||
0ec56dc4 | 2657 | memset(&ops, 0, sizeof(ops)); |
4a89ff88 BN |
2658 | ops.len = len; |
2659 | ops.datbuf = (uint8_t *)buf; | |
11041ae6 | 2660 | ops.mode = MTD_OPS_PLACE_OOB; |
2af7c653 | 2661 | |
4a89ff88 | 2662 | ret = nand_do_write_ops(mtd, to, &ops); |
2af7c653 | 2663 | |
4a89ff88 | 2664 | *retlen = ops.retlen; |
2af7c653 SK |
2665 | return ret; |
2666 | } | |
2667 | ||
f75e5097 | 2668 | /** |
8593fbc6 | 2669 | * nand_write - [MTD Interface] NAND write with ECC |
8b6e50c9 BN |
2670 | * @mtd: MTD device structure |
2671 | * @to: offset to write to | |
2672 | * @len: number of bytes to write | |
2673 | * @retlen: pointer to variable to store the number of written bytes | |
2674 | * @buf: the data to write | |
f75e5097 | 2675 | * |
8b6e50c9 | 2676 | * NAND write with ECC. |
f75e5097 | 2677 | */ |
8593fbc6 TG |
2678 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
2679 | size_t *retlen, const uint8_t *buf) | |
f75e5097 | 2680 | { |
4a89ff88 | 2681 | struct mtd_oob_ops ops; |
f75e5097 TG |
2682 | int ret; |
2683 | ||
6a8214aa | 2684 | nand_get_device(mtd, FL_WRITING); |
0ec56dc4 | 2685 | memset(&ops, 0, sizeof(ops)); |
4a89ff88 BN |
2686 | ops.len = len; |
2687 | ops.datbuf = (uint8_t *)buf; | |
11041ae6 | 2688 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 2689 | ret = nand_do_write_ops(mtd, to, &ops); |
4a89ff88 | 2690 | *retlen = ops.retlen; |
f75e5097 | 2691 | nand_release_device(mtd); |
8593fbc6 | 2692 | return ret; |
f75e5097 | 2693 | } |
7314e9e7 | 2694 | |
1da177e4 | 2695 | /** |
8593fbc6 | 2696 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
8b6e50c9 BN |
2697 | * @mtd: MTD device structure |
2698 | * @to: offset to write to | |
2699 | * @ops: oob operation description structure | |
1da177e4 | 2700 | * |
8b6e50c9 | 2701 | * NAND write out-of-band. |
1da177e4 | 2702 | */ |
8593fbc6 TG |
2703 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
2704 | struct mtd_oob_ops *ops) | |
1da177e4 | 2705 | { |
03736155 | 2706 | int chipnr, page, status, len; |
ace4dfee | 2707 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2708 | |
289c0522 | 2709 | pr_debug("%s: to = 0x%08x, len = %i\n", |
20d8e248 | 2710 | __func__, (unsigned int)to, (int)ops->ooblen); |
1da177e4 | 2711 | |
0612b9dd | 2712 | if (ops->mode == MTD_OPS_AUTO_OOB) |
03736155 AH |
2713 | len = chip->ecc.layout->oobavail; |
2714 | else | |
2715 | len = mtd->oobsize; | |
2716 | ||
1da177e4 | 2717 | /* Do not allow write past end of page */ |
03736155 | 2718 | if ((ops->ooboffs + ops->ooblen) > len) { |
289c0522 BN |
2719 | pr_debug("%s: attempt to write past end of page\n", |
2720 | __func__); | |
1da177e4 LT |
2721 | return -EINVAL; |
2722 | } | |
2723 | ||
03736155 | 2724 | if (unlikely(ops->ooboffs >= len)) { |
289c0522 BN |
2725 | pr_debug("%s: attempt to start write outside oob\n", |
2726 | __func__); | |
03736155 AH |
2727 | return -EINVAL; |
2728 | } | |
2729 | ||
775adc3d | 2730 | /* Do not allow write past end of device */ |
03736155 AH |
2731 | if (unlikely(to >= mtd->size || |
2732 | ops->ooboffs + ops->ooblen > | |
2733 | ((mtd->size >> chip->page_shift) - | |
2734 | (to >> chip->page_shift)) * len)) { | |
289c0522 BN |
2735 | pr_debug("%s: attempt to write beyond end of device\n", |
2736 | __func__); | |
03736155 AH |
2737 | return -EINVAL; |
2738 | } | |
2739 | ||
7314e9e7 | 2740 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 2741 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2742 | |
7314e9e7 TG |
2743 | /* Shift to get page */ |
2744 | page = (int)(to >> chip->page_shift); | |
2745 | ||
2746 | /* | |
2747 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
2748 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
2749 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
2750 | * it in the doc2000 driver in August 1999. dwmw2. | |
2751 | */ | |
ace4dfee | 2752 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
2753 | |
2754 | /* Check, if it is write protected */ | |
b0bb6903 HS |
2755 | if (nand_check_wp(mtd)) { |
2756 | chip->select_chip(mtd, -1); | |
8593fbc6 | 2757 | return -EROFS; |
b0bb6903 | 2758 | } |
61b03bd7 | 2759 | |
1da177e4 | 2760 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
2761 | if (page == chip->pagebuf) |
2762 | chip->pagebuf = -1; | |
1da177e4 | 2763 | |
f722013e | 2764 | nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops); |
9ce244b3 | 2765 | |
0612b9dd | 2766 | if (ops->mode == MTD_OPS_RAW) |
9ce244b3 BN |
2767 | status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask); |
2768 | else | |
2769 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); | |
1da177e4 | 2770 | |
b0bb6903 HS |
2771 | chip->select_chip(mtd, -1); |
2772 | ||
7bc3312b TG |
2773 | if (status) |
2774 | return status; | |
1da177e4 | 2775 | |
7014568b | 2776 | ops->oobretlen = ops->ooblen; |
1da177e4 | 2777 | |
7bc3312b | 2778 | return 0; |
8593fbc6 TG |
2779 | } |
2780 | ||
2781 | /** | |
2782 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
8b6e50c9 BN |
2783 | * @mtd: MTD device structure |
2784 | * @to: offset to write to | |
2785 | * @ops: oob operation description structure | |
8593fbc6 TG |
2786 | */ |
2787 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
2788 | struct mtd_oob_ops *ops) | |
2789 | { | |
8593fbc6 TG |
2790 | int ret = -ENOTSUPP; |
2791 | ||
2792 | ops->retlen = 0; | |
2793 | ||
2794 | /* Do not allow writes past end of device */ | |
7014568b | 2795 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
289c0522 BN |
2796 | pr_debug("%s: attempt to write beyond end of device\n", |
2797 | __func__); | |
8593fbc6 TG |
2798 | return -EINVAL; |
2799 | } | |
2800 | ||
6a8214aa | 2801 | nand_get_device(mtd, FL_WRITING); |
8593fbc6 | 2802 | |
f8ac0414 | 2803 | switch (ops->mode) { |
0612b9dd BN |
2804 | case MTD_OPS_PLACE_OOB: |
2805 | case MTD_OPS_AUTO_OOB: | |
2806 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2807 | break; |
2808 | ||
2809 | default: | |
2810 | goto out; | |
2811 | } | |
2812 | ||
2813 | if (!ops->datbuf) | |
2814 | ret = nand_do_write_oob(mtd, to, ops); | |
2815 | else | |
2816 | ret = nand_do_write_ops(mtd, to, ops); | |
2817 | ||
7351d3a5 | 2818 | out: |
1da177e4 | 2819 | nand_release_device(mtd); |
1da177e4 LT |
2820 | return ret; |
2821 | } | |
2822 | ||
1da177e4 | 2823 | /** |
49c50b97 | 2824 | * single_erase - [GENERIC] NAND standard block erase command function |
8b6e50c9 BN |
2825 | * @mtd: MTD device structure |
2826 | * @page: the page address of the block which will be erased | |
1da177e4 | 2827 | * |
49c50b97 | 2828 | * Standard erase command for NAND chips. Returns NAND status. |
1da177e4 | 2829 | */ |
49c50b97 | 2830 | static int single_erase(struct mtd_info *mtd, int page) |
1da177e4 | 2831 | { |
ace4dfee | 2832 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2833 | /* Send commands to erase a block */ |
ace4dfee TG |
2834 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
2835 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
49c50b97 BN |
2836 | |
2837 | return chip->waitfunc(mtd, chip); | |
1da177e4 LT |
2838 | } |
2839 | ||
1da177e4 LT |
2840 | /** |
2841 | * nand_erase - [MTD Interface] erase block(s) | |
8b6e50c9 BN |
2842 | * @mtd: MTD device structure |
2843 | * @instr: erase instruction | |
1da177e4 | 2844 | * |
8b6e50c9 | 2845 | * Erase one ore more blocks. |
1da177e4 | 2846 | */ |
e0c7d767 | 2847 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 2848 | { |
e0c7d767 | 2849 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 2850 | } |
61b03bd7 | 2851 | |
1da177e4 | 2852 | /** |
7854d3f7 | 2853 | * nand_erase_nand - [INTERN] erase block(s) |
8b6e50c9 BN |
2854 | * @mtd: MTD device structure |
2855 | * @instr: erase instruction | |
2856 | * @allowbbt: allow erasing the bbt area | |
1da177e4 | 2857 | * |
8b6e50c9 | 2858 | * Erase one ore more blocks. |
1da177e4 | 2859 | */ |
ace4dfee TG |
2860 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
2861 | int allowbbt) | |
1da177e4 | 2862 | { |
69423d99 | 2863 | int page, status, pages_per_block, ret, chipnr; |
ace4dfee | 2864 | struct nand_chip *chip = mtd->priv; |
69423d99 | 2865 | loff_t len; |
1da177e4 | 2866 | |
289c0522 BN |
2867 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
2868 | __func__, (unsigned long long)instr->addr, | |
2869 | (unsigned long long)instr->len); | |
1da177e4 | 2870 | |
6fe5a6ac | 2871 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 2872 | return -EINVAL; |
1da177e4 | 2873 | |
1da177e4 | 2874 | /* Grab the lock and see if the device is available */ |
6a8214aa | 2875 | nand_get_device(mtd, FL_ERASING); |
1da177e4 LT |
2876 | |
2877 | /* Shift to get first page */ | |
ace4dfee TG |
2878 | page = (int)(instr->addr >> chip->page_shift); |
2879 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
2880 | |
2881 | /* Calculate pages in each block */ | |
ace4dfee | 2882 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
2883 | |
2884 | /* Select the NAND device */ | |
ace4dfee | 2885 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2886 | |
1da177e4 LT |
2887 | /* Check, if it is write protected */ |
2888 | if (nand_check_wp(mtd)) { | |
289c0522 BN |
2889 | pr_debug("%s: device is write protected!\n", |
2890 | __func__); | |
1da177e4 LT |
2891 | instr->state = MTD_ERASE_FAILED; |
2892 | goto erase_exit; | |
2893 | } | |
2894 | ||
2895 | /* Loop through the pages */ | |
2896 | len = instr->len; | |
2897 | ||
2898 | instr->state = MTD_ERASING; | |
2899 | ||
2900 | while (len) { | |
12183a20 | 2901 | /* Check if we have a bad block, we do not erase bad blocks! */ |
ace4dfee TG |
2902 | if (nand_block_checkbad(mtd, ((loff_t) page) << |
2903 | chip->page_shift, 0, allowbbt)) { | |
d0370219 BN |
2904 | pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", |
2905 | __func__, page); | |
1da177e4 LT |
2906 | instr->state = MTD_ERASE_FAILED; |
2907 | goto erase_exit; | |
2908 | } | |
61b03bd7 | 2909 | |
ace4dfee TG |
2910 | /* |
2911 | * Invalidate the page cache, if we erase the block which | |
8b6e50c9 | 2912 | * contains the current cached page. |
ace4dfee TG |
2913 | */ |
2914 | if (page <= chip->pagebuf && chip->pagebuf < | |
2915 | (page + pages_per_block)) | |
2916 | chip->pagebuf = -1; | |
1da177e4 | 2917 | |
49c50b97 | 2918 | status = chip->erase(mtd, page & chip->pagemask); |
1da177e4 | 2919 | |
ace4dfee TG |
2920 | /* |
2921 | * See if operation failed and additional status checks are | |
2922 | * available | |
2923 | */ | |
2924 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2925 | status = chip->errstat(mtd, chip, FL_ERASING, | |
2926 | status, page); | |
068e3c0a | 2927 | |
1da177e4 | 2928 | /* See if block erase succeeded */ |
a4ab4c5d | 2929 | if (status & NAND_STATUS_FAIL) { |
289c0522 BN |
2930 | pr_debug("%s: failed erase, page 0x%08x\n", |
2931 | __func__, page); | |
1da177e4 | 2932 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
2933 | instr->fail_addr = |
2934 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
2935 | goto erase_exit; |
2936 | } | |
30f464b7 | 2937 | |
1da177e4 | 2938 | /* Increment page address and decrement length */ |
daae74ca | 2939 | len -= (1ULL << chip->phys_erase_shift); |
1da177e4 LT |
2940 | page += pages_per_block; |
2941 | ||
2942 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 2943 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 2944 | chipnr++; |
ace4dfee TG |
2945 | chip->select_chip(mtd, -1); |
2946 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2947 | } |
2948 | } | |
2949 | instr->state = MTD_ERASE_DONE; | |
2950 | ||
7351d3a5 | 2951 | erase_exit: |
1da177e4 LT |
2952 | |
2953 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
2954 | |
2955 | /* Deselect and wake up anyone waiting on the device */ | |
b0bb6903 | 2956 | chip->select_chip(mtd, -1); |
1da177e4 LT |
2957 | nand_release_device(mtd); |
2958 | ||
49defc01 DW |
2959 | /* Do call back function */ |
2960 | if (!ret) | |
2961 | mtd_erase_callback(instr); | |
2962 | ||
1da177e4 LT |
2963 | /* Return more or less happy */ |
2964 | return ret; | |
2965 | } | |
2966 | ||
2967 | /** | |
2968 | * nand_sync - [MTD Interface] sync | |
8b6e50c9 | 2969 | * @mtd: MTD device structure |
1da177e4 | 2970 | * |
8b6e50c9 | 2971 | * Sync is actually a wait for chip ready function. |
1da177e4 | 2972 | */ |
e0c7d767 | 2973 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 2974 | { |
289c0522 | 2975 | pr_debug("%s: called\n", __func__); |
1da177e4 LT |
2976 | |
2977 | /* Grab the lock and see if the device is available */ | |
6a8214aa | 2978 | nand_get_device(mtd, FL_SYNCING); |
1da177e4 | 2979 | /* Release it and go back */ |
e0c7d767 | 2980 | nand_release_device(mtd); |
1da177e4 LT |
2981 | } |
2982 | ||
1da177e4 | 2983 | /** |
ace4dfee | 2984 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
8b6e50c9 BN |
2985 | * @mtd: MTD device structure |
2986 | * @offs: offset relative to mtd start | |
1da177e4 | 2987 | */ |
ace4dfee | 2988 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 | 2989 | { |
ace4dfee | 2990 | return nand_block_checkbad(mtd, offs, 1, 0); |
1da177e4 LT |
2991 | } |
2992 | ||
2993 | /** | |
ace4dfee | 2994 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
8b6e50c9 BN |
2995 | * @mtd: MTD device structure |
2996 | * @ofs: offset relative to mtd start | |
1da177e4 | 2997 | */ |
e0c7d767 | 2998 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 2999 | { |
1da177e4 LT |
3000 | int ret; |
3001 | ||
f8ac0414 FF |
3002 | ret = nand_block_isbad(mtd, ofs); |
3003 | if (ret) { | |
8b6e50c9 | 3004 | /* If it was bad already, return success and do nothing */ |
1da177e4 LT |
3005 | if (ret > 0) |
3006 | return 0; | |
e0c7d767 DW |
3007 | return ret; |
3008 | } | |
1da177e4 | 3009 | |
5a0edb25 | 3010 | return nand_block_markbad_lowlevel(mtd, ofs); |
1da177e4 LT |
3011 | } |
3012 | ||
7db03ecc HS |
3013 | /** |
3014 | * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand | |
3015 | * @mtd: MTD device structure | |
3016 | * @chip: nand chip info structure | |
3017 | * @addr: feature address. | |
3018 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
3019 | */ | |
3020 | static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, | |
3021 | int addr, uint8_t *subfeature_param) | |
3022 | { | |
3023 | int status; | |
05f78359 | 3024 | int i; |
7db03ecc | 3025 | |
d914c932 DM |
3026 | if (!chip->onfi_version || |
3027 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
3028 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
3029 | return -EINVAL; |
3030 | ||
3031 | chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1); | |
05f78359 UKK |
3032 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
3033 | chip->write_byte(mtd, subfeature_param[i]); | |
3034 | ||
7db03ecc HS |
3035 | status = chip->waitfunc(mtd, chip); |
3036 | if (status & NAND_STATUS_FAIL) | |
3037 | return -EIO; | |
3038 | return 0; | |
3039 | } | |
3040 | ||
3041 | /** | |
3042 | * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand | |
3043 | * @mtd: MTD device structure | |
3044 | * @chip: nand chip info structure | |
3045 | * @addr: feature address. | |
3046 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
3047 | */ | |
3048 | static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, | |
3049 | int addr, uint8_t *subfeature_param) | |
3050 | { | |
05f78359 UKK |
3051 | int i; |
3052 | ||
d914c932 DM |
3053 | if (!chip->onfi_version || |
3054 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
3055 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
3056 | return -EINVAL; |
3057 | ||
7db03ecc | 3058 | chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1); |
05f78359 UKK |
3059 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
3060 | *subfeature_param++ = chip->read_byte(mtd); | |
7db03ecc HS |
3061 | return 0; |
3062 | } | |
3063 | ||
962034f4 VW |
3064 | /** |
3065 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
8b6e50c9 | 3066 | * @mtd: MTD device structure |
962034f4 VW |
3067 | */ |
3068 | static int nand_suspend(struct mtd_info *mtd) | |
3069 | { | |
6a8214aa | 3070 | return nand_get_device(mtd, FL_PM_SUSPENDED); |
962034f4 VW |
3071 | } |
3072 | ||
3073 | /** | |
3074 | * nand_resume - [MTD Interface] Resume the NAND flash | |
8b6e50c9 | 3075 | * @mtd: MTD device structure |
962034f4 VW |
3076 | */ |
3077 | static void nand_resume(struct mtd_info *mtd) | |
3078 | { | |
ace4dfee | 3079 | struct nand_chip *chip = mtd->priv; |
962034f4 | 3080 | |
ace4dfee | 3081 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
3082 | nand_release_device(mtd); |
3083 | else | |
d0370219 BN |
3084 | pr_err("%s called for a chip which is not in suspended state\n", |
3085 | __func__); | |
962034f4 VW |
3086 | } |
3087 | ||
72ea4036 SB |
3088 | /** |
3089 | * nand_shutdown - [MTD Interface] Finish the current NAND operation and | |
3090 | * prevent further operations | |
3091 | * @mtd: MTD device structure | |
3092 | */ | |
3093 | static void nand_shutdown(struct mtd_info *mtd) | |
3094 | { | |
3095 | nand_get_device(mtd, FL_SHUTDOWN); | |
3096 | } | |
3097 | ||
8b6e50c9 | 3098 | /* Set default functions */ |
ace4dfee | 3099 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 3100 | { |
1da177e4 | 3101 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
3102 | if (!chip->chip_delay) |
3103 | chip->chip_delay = 20; | |
1da177e4 LT |
3104 | |
3105 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
3106 | if (chip->cmdfunc == NULL) |
3107 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
3108 | |
3109 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
3110 | if (chip->waitfunc == NULL) |
3111 | chip->waitfunc = nand_wait; | |
3112 | ||
3113 | if (!chip->select_chip) | |
3114 | chip->select_chip = nand_select_chip; | |
68e80780 | 3115 | |
4204cccd HS |
3116 | /* set for ONFI nand */ |
3117 | if (!chip->onfi_set_features) | |
3118 | chip->onfi_set_features = nand_onfi_set_features; | |
3119 | if (!chip->onfi_get_features) | |
3120 | chip->onfi_get_features = nand_onfi_get_features; | |
3121 | ||
68e80780 BN |
3122 | /* If called twice, pointers that depend on busw may need to be reset */ |
3123 | if (!chip->read_byte || chip->read_byte == nand_read_byte) | |
ace4dfee TG |
3124 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; |
3125 | if (!chip->read_word) | |
3126 | chip->read_word = nand_read_word; | |
3127 | if (!chip->block_bad) | |
3128 | chip->block_bad = nand_block_bad; | |
3129 | if (!chip->block_markbad) | |
3130 | chip->block_markbad = nand_default_block_markbad; | |
68e80780 | 3131 | if (!chip->write_buf || chip->write_buf == nand_write_buf) |
ace4dfee | 3132 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; |
05f78359 UKK |
3133 | if (!chip->write_byte || chip->write_byte == nand_write_byte) |
3134 | chip->write_byte = busw ? nand_write_byte16 : nand_write_byte; | |
68e80780 | 3135 | if (!chip->read_buf || chip->read_buf == nand_read_buf) |
ace4dfee | 3136 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; |
ace4dfee TG |
3137 | if (!chip->scan_bbt) |
3138 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
3139 | |
3140 | if (!chip->controller) { | |
3141 | chip->controller = &chip->hwcontrol; | |
3142 | spin_lock_init(&chip->controller->lock); | |
3143 | init_waitqueue_head(&chip->controller->wq); | |
3144 | } | |
3145 | ||
7aa65bfd TG |
3146 | } |
3147 | ||
8b6e50c9 | 3148 | /* Sanitize ONFI strings so we can safely print them */ |
d1e1f4e4 FF |
3149 | static void sanitize_string(uint8_t *s, size_t len) |
3150 | { | |
3151 | ssize_t i; | |
3152 | ||
8b6e50c9 | 3153 | /* Null terminate */ |
d1e1f4e4 FF |
3154 | s[len - 1] = 0; |
3155 | ||
8b6e50c9 | 3156 | /* Remove non printable chars */ |
d1e1f4e4 FF |
3157 | for (i = 0; i < len - 1; i++) { |
3158 | if (s[i] < ' ' || s[i] > 127) | |
3159 | s[i] = '?'; | |
3160 | } | |
3161 | ||
8b6e50c9 | 3162 | /* Remove trailing spaces */ |
d1e1f4e4 FF |
3163 | strim(s); |
3164 | } | |
3165 | ||
3166 | static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) | |
3167 | { | |
3168 | int i; | |
3169 | while (len--) { | |
3170 | crc ^= *p++ << 8; | |
3171 | for (i = 0; i < 8; i++) | |
3172 | crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); | |
3173 | } | |
3174 | ||
3175 | return crc; | |
3176 | } | |
3177 | ||
6dcbe0cd HS |
3178 | /* Parse the Extended Parameter Page. */ |
3179 | static int nand_flash_detect_ext_param_page(struct mtd_info *mtd, | |
3180 | struct nand_chip *chip, struct nand_onfi_params *p) | |
3181 | { | |
3182 | struct onfi_ext_param_page *ep; | |
3183 | struct onfi_ext_section *s; | |
3184 | struct onfi_ext_ecc_info *ecc; | |
3185 | uint8_t *cursor; | |
3186 | int ret = -EINVAL; | |
3187 | int len; | |
3188 | int i; | |
3189 | ||
3190 | len = le16_to_cpu(p->ext_param_page_length) * 16; | |
3191 | ep = kmalloc(len, GFP_KERNEL); | |
5cb13271 BN |
3192 | if (!ep) |
3193 | return -ENOMEM; | |
6dcbe0cd HS |
3194 | |
3195 | /* Send our own NAND_CMD_PARAM. */ | |
3196 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); | |
3197 | ||
3198 | /* Use the Change Read Column command to skip the ONFI param pages. */ | |
3199 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, | |
3200 | sizeof(*p) * p->num_of_param_pages , -1); | |
3201 | ||
3202 | /* Read out the Extended Parameter Page. */ | |
3203 | chip->read_buf(mtd, (uint8_t *)ep, len); | |
3204 | if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2) | |
3205 | != le16_to_cpu(ep->crc))) { | |
3206 | pr_debug("fail in the CRC.\n"); | |
3207 | goto ext_out; | |
3208 | } | |
3209 | ||
3210 | /* | |
3211 | * Check the signature. | |
3212 | * Do not strictly follow the ONFI spec, maybe changed in future. | |
3213 | */ | |
3214 | if (strncmp(ep->sig, "EPPS", 4)) { | |
3215 | pr_debug("The signature is invalid.\n"); | |
3216 | goto ext_out; | |
3217 | } | |
3218 | ||
3219 | /* find the ECC section. */ | |
3220 | cursor = (uint8_t *)(ep + 1); | |
3221 | for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) { | |
3222 | s = ep->sections + i; | |
3223 | if (s->type == ONFI_SECTION_TYPE_2) | |
3224 | break; | |
3225 | cursor += s->length * 16; | |
3226 | } | |
3227 | if (i == ONFI_EXT_SECTION_MAX) { | |
3228 | pr_debug("We can not find the ECC section.\n"); | |
3229 | goto ext_out; | |
3230 | } | |
3231 | ||
3232 | /* get the info we want. */ | |
3233 | ecc = (struct onfi_ext_ecc_info *)cursor; | |
3234 | ||
4ae7d228 BN |
3235 | if (!ecc->codeword_size) { |
3236 | pr_debug("Invalid codeword size\n"); | |
3237 | goto ext_out; | |
6dcbe0cd HS |
3238 | } |
3239 | ||
4ae7d228 BN |
3240 | chip->ecc_strength_ds = ecc->ecc_bits; |
3241 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
5cb13271 | 3242 | ret = 0; |
6dcbe0cd HS |
3243 | |
3244 | ext_out: | |
3245 | kfree(ep); | |
3246 | return ret; | |
3247 | } | |
3248 | ||
8429bb39 BN |
3249 | static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode) |
3250 | { | |
3251 | struct nand_chip *chip = mtd->priv; | |
3252 | uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; | |
3253 | ||
3254 | return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, | |
3255 | feature); | |
3256 | } | |
3257 | ||
3258 | /* | |
3259 | * Configure chip properties from Micron vendor-specific ONFI table | |
3260 | */ | |
3261 | static void nand_onfi_detect_micron(struct nand_chip *chip, | |
3262 | struct nand_onfi_params *p) | |
3263 | { | |
3264 | struct nand_onfi_vendor_micron *micron = (void *)p->vendor; | |
3265 | ||
3266 | if (le16_to_cpu(p->vendor_revision) < 1) | |
3267 | return; | |
3268 | ||
3269 | chip->read_retries = micron->read_retry_options; | |
3270 | chip->setup_read_retry = nand_setup_read_retry_micron; | |
3271 | } | |
3272 | ||
6fb277ba | 3273 | /* |
8b6e50c9 | 3274 | * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. |
6fb277ba FF |
3275 | */ |
3276 | static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, | |
08c248fb | 3277 | int *busw) |
6fb277ba FF |
3278 | { |
3279 | struct nand_onfi_params *p = &chip->onfi_params; | |
bd9c6e99 | 3280 | int i, j; |
6fb277ba FF |
3281 | int val; |
3282 | ||
7854d3f7 | 3283 | /* Try ONFI for unknown chip or LP */ |
6fb277ba FF |
3284 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); |
3285 | if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || | |
3286 | chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') | |
3287 | return 0; | |
3288 | ||
6fb277ba FF |
3289 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); |
3290 | for (i = 0; i < 3; i++) { | |
bd9c6e99 BN |
3291 | for (j = 0; j < sizeof(*p); j++) |
3292 | ((uint8_t *)p)[j] = chip->read_byte(mtd); | |
6fb277ba FF |
3293 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == |
3294 | le16_to_cpu(p->crc)) { | |
6fb277ba FF |
3295 | break; |
3296 | } | |
3297 | } | |
3298 | ||
c7f23a70 BN |
3299 | if (i == 3) { |
3300 | pr_err("Could not find valid ONFI parameter page; aborting\n"); | |
6fb277ba | 3301 | return 0; |
c7f23a70 | 3302 | } |
6fb277ba | 3303 | |
8b6e50c9 | 3304 | /* Check version */ |
6fb277ba | 3305 | val = le16_to_cpu(p->revision); |
b7b1a29d BN |
3306 | if (val & (1 << 5)) |
3307 | chip->onfi_version = 23; | |
3308 | else if (val & (1 << 4)) | |
6fb277ba FF |
3309 | chip->onfi_version = 22; |
3310 | else if (val & (1 << 3)) | |
3311 | chip->onfi_version = 21; | |
3312 | else if (val & (1 << 2)) | |
3313 | chip->onfi_version = 20; | |
b7b1a29d | 3314 | else if (val & (1 << 1)) |
6fb277ba | 3315 | chip->onfi_version = 10; |
b7b1a29d BN |
3316 | |
3317 | if (!chip->onfi_version) { | |
20171642 | 3318 | pr_info("unsupported ONFI version: %d\n", val); |
b7b1a29d BN |
3319 | return 0; |
3320 | } | |
6fb277ba FF |
3321 | |
3322 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3323 | sanitize_string(p->model, sizeof(p->model)); | |
3324 | if (!mtd->name) | |
3325 | mtd->name = p->model; | |
4355b70c | 3326 | |
6fb277ba | 3327 | mtd->writesize = le32_to_cpu(p->byte_per_page); |
4355b70c BN |
3328 | |
3329 | /* | |
3330 | * pages_per_block and blocks_per_lun may not be a power-of-2 size | |
3331 | * (don't ask me who thought of this...). MTD assumes that these | |
3332 | * dimensions will be power-of-2, so just truncate the remaining area. | |
3333 | */ | |
3334 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3335 | mtd->erasesize *= mtd->writesize; | |
3336 | ||
6fb277ba | 3337 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); |
4355b70c BN |
3338 | |
3339 | /* See erasesize comment */ | |
3340 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
63795755 | 3341 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; |
13fbd179 | 3342 | chip->bits_per_cell = p->bits_per_cell; |
e2985fc1 HS |
3343 | |
3344 | if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) | |
08c248fb | 3345 | *busw = NAND_BUSWIDTH_16; |
e2985fc1 HS |
3346 | else |
3347 | *busw = 0; | |
6fb277ba | 3348 | |
10c86bab HS |
3349 | if (p->ecc_bits != 0xff) { |
3350 | chip->ecc_strength_ds = p->ecc_bits; | |
3351 | chip->ecc_step_ds = 512; | |
6dcbe0cd HS |
3352 | } else if (chip->onfi_version >= 21 && |
3353 | (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) { | |
3354 | ||
3355 | /* | |
3356 | * The nand_flash_detect_ext_param_page() uses the | |
3357 | * Change Read Column command which maybe not supported | |
3358 | * by the chip->cmdfunc. So try to update the chip->cmdfunc | |
3359 | * now. We do not replace user supplied command function. | |
3360 | */ | |
3361 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) | |
3362 | chip->cmdfunc = nand_command_lp; | |
3363 | ||
3364 | /* The Extended Parameter Page is supported since ONFI 2.1. */ | |
3365 | if (nand_flash_detect_ext_param_page(mtd, chip, p)) | |
c7f23a70 BN |
3366 | pr_warn("Failed to detect ONFI extended param page\n"); |
3367 | } else { | |
3368 | pr_warn("Could not retrieve ONFI ECC requirements\n"); | |
10c86bab HS |
3369 | } |
3370 | ||
8429bb39 BN |
3371 | if (p->jedec_id == NAND_MFR_MICRON) |
3372 | nand_onfi_detect_micron(chip, p); | |
3373 | ||
6fb277ba FF |
3374 | return 1; |
3375 | } | |
3376 | ||
91361818 HS |
3377 | /* |
3378 | * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise. | |
3379 | */ | |
3380 | static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip, | |
3381 | int *busw) | |
3382 | { | |
3383 | struct nand_jedec_params *p = &chip->jedec_params; | |
3384 | struct jedec_ecc_info *ecc; | |
3385 | int val; | |
3386 | int i, j; | |
3387 | ||
3388 | /* Try JEDEC for unknown chip or LP */ | |
3389 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1); | |
3390 | if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' || | |
3391 | chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' || | |
3392 | chip->read_byte(mtd) != 'C') | |
3393 | return 0; | |
3394 | ||
3395 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1); | |
3396 | for (i = 0; i < 3; i++) { | |
3397 | for (j = 0; j < sizeof(*p); j++) | |
3398 | ((uint8_t *)p)[j] = chip->read_byte(mtd); | |
3399 | ||
3400 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) == | |
3401 | le16_to_cpu(p->crc)) | |
3402 | break; | |
3403 | } | |
3404 | ||
3405 | if (i == 3) { | |
3406 | pr_err("Could not find valid JEDEC parameter page; aborting\n"); | |
3407 | return 0; | |
3408 | } | |
3409 | ||
3410 | /* Check version */ | |
3411 | val = le16_to_cpu(p->revision); | |
3412 | if (val & (1 << 2)) | |
3413 | chip->jedec_version = 10; | |
3414 | else if (val & (1 << 1)) | |
3415 | chip->jedec_version = 1; /* vendor specific version */ | |
3416 | ||
3417 | if (!chip->jedec_version) { | |
3418 | pr_info("unsupported JEDEC version: %d\n", val); | |
3419 | return 0; | |
3420 | } | |
3421 | ||
3422 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3423 | sanitize_string(p->model, sizeof(p->model)); | |
3424 | if (!mtd->name) | |
3425 | mtd->name = p->model; | |
3426 | ||
3427 | mtd->writesize = le32_to_cpu(p->byte_per_page); | |
3428 | ||
3429 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
3430 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3431 | mtd->erasesize *= mtd->writesize; | |
3432 | ||
3433 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); | |
3434 | ||
3435 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
3436 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
3437 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; | |
3438 | chip->bits_per_cell = p->bits_per_cell; | |
3439 | ||
3440 | if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS) | |
3441 | *busw = NAND_BUSWIDTH_16; | |
3442 | else | |
3443 | *busw = 0; | |
3444 | ||
3445 | /* ECC info */ | |
3446 | ecc = &p->ecc_info[0]; | |
3447 | ||
3448 | if (ecc->codeword_size >= 9) { | |
3449 | chip->ecc_strength_ds = ecc->ecc_bits; | |
3450 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
3451 | } else { | |
3452 | pr_warn("Invalid codeword size\n"); | |
3453 | } | |
3454 | ||
3455 | return 1; | |
3456 | } | |
3457 | ||
e3b88bd6 BN |
3458 | /* |
3459 | * nand_id_has_period - Check if an ID string has a given wraparound period | |
3460 | * @id_data: the ID string | |
3461 | * @arrlen: the length of the @id_data array | |
3462 | * @period: the period of repitition | |
3463 | * | |
3464 | * Check if an ID string is repeated within a given sequence of bytes at | |
3465 | * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a | |
d4d4f1bf | 3466 | * period of 3). This is a helper function for nand_id_len(). Returns non-zero |
e3b88bd6 BN |
3467 | * if the repetition has a period of @period; otherwise, returns zero. |
3468 | */ | |
3469 | static int nand_id_has_period(u8 *id_data, int arrlen, int period) | |
3470 | { | |
3471 | int i, j; | |
3472 | for (i = 0; i < period; i++) | |
3473 | for (j = i + period; j < arrlen; j += period) | |
3474 | if (id_data[i] != id_data[j]) | |
3475 | return 0; | |
3476 | return 1; | |
3477 | } | |
3478 | ||
3479 | /* | |
3480 | * nand_id_len - Get the length of an ID string returned by CMD_READID | |
3481 | * @id_data: the ID string | |
3482 | * @arrlen: the length of the @id_data array | |
3483 | ||
3484 | * Returns the length of the ID string, according to known wraparound/trailing | |
3485 | * zero patterns. If no pattern exists, returns the length of the array. | |
3486 | */ | |
3487 | static int nand_id_len(u8 *id_data, int arrlen) | |
3488 | { | |
3489 | int last_nonzero, period; | |
3490 | ||
3491 | /* Find last non-zero byte */ | |
3492 | for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) | |
3493 | if (id_data[last_nonzero]) | |
3494 | break; | |
3495 | ||
3496 | /* All zeros */ | |
3497 | if (last_nonzero < 0) | |
3498 | return 0; | |
3499 | ||
3500 | /* Calculate wraparound period */ | |
3501 | for (period = 1; period < arrlen; period++) | |
3502 | if (nand_id_has_period(id_data, arrlen, period)) | |
3503 | break; | |
3504 | ||
3505 | /* There's a repeated pattern */ | |
3506 | if (period < arrlen) | |
3507 | return period; | |
3508 | ||
3509 | /* There are trailing zeros */ | |
3510 | if (last_nonzero < arrlen - 1) | |
3511 | return last_nonzero + 1; | |
3512 | ||
3513 | /* No pattern detected */ | |
3514 | return arrlen; | |
3515 | } | |
3516 | ||
7db906b7 HS |
3517 | /* Extract the bits of per cell from the 3rd byte of the extended ID */ |
3518 | static int nand_get_bits_per_cell(u8 cellinfo) | |
3519 | { | |
3520 | int bits; | |
3521 | ||
3522 | bits = cellinfo & NAND_CI_CELLTYPE_MSK; | |
3523 | bits >>= NAND_CI_CELLTYPE_SHIFT; | |
3524 | return bits + 1; | |
3525 | } | |
3526 | ||
fc09bbc0 BN |
3527 | /* |
3528 | * Many new NAND share similar device ID codes, which represent the size of the | |
3529 | * chip. The rest of the parameters must be decoded according to generic or | |
3530 | * manufacturer-specific "extended ID" decoding patterns. | |
3531 | */ | |
3532 | static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, | |
3533 | u8 id_data[8], int *busw) | |
3534 | { | |
e3b88bd6 | 3535 | int extid, id_len; |
fc09bbc0 | 3536 | /* The 3rd id byte holds MLC / multichip data */ |
7db906b7 | 3537 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
fc09bbc0 BN |
3538 | /* The 4th id byte is the important one */ |
3539 | extid = id_data[3]; | |
3540 | ||
e3b88bd6 BN |
3541 | id_len = nand_id_len(id_data, 8); |
3542 | ||
fc09bbc0 BN |
3543 | /* |
3544 | * Field definitions are in the following datasheets: | |
3545 | * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) | |
af451af4 | 3546 | * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) |
73ca392f | 3547 | * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) |
fc09bbc0 | 3548 | * |
af451af4 BN |
3549 | * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung |
3550 | * ID to decide what to do. | |
fc09bbc0 | 3551 | */ |
af451af4 | 3552 | if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && |
1d0ed69d | 3553 | !nand_is_slc(chip) && id_data[5] != 0x00) { |
fc09bbc0 BN |
3554 | /* Calc pagesize */ |
3555 | mtd->writesize = 2048 << (extid & 0x03); | |
3556 | extid >>= 2; | |
3557 | /* Calc oobsize */ | |
e2d3a35e | 3558 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { |
fc09bbc0 BN |
3559 | case 1: |
3560 | mtd->oobsize = 128; | |
3561 | break; | |
3562 | case 2: | |
3563 | mtd->oobsize = 218; | |
3564 | break; | |
3565 | case 3: | |
3566 | mtd->oobsize = 400; | |
3567 | break; | |
e2d3a35e | 3568 | case 4: |
fc09bbc0 BN |
3569 | mtd->oobsize = 436; |
3570 | break; | |
e2d3a35e BN |
3571 | case 5: |
3572 | mtd->oobsize = 512; | |
3573 | break; | |
3574 | case 6: | |
e2d3a35e BN |
3575 | mtd->oobsize = 640; |
3576 | break; | |
94d04e82 HS |
3577 | case 7: |
3578 | default: /* Other cases are "reserved" (unknown) */ | |
3579 | mtd->oobsize = 1024; | |
3580 | break; | |
fc09bbc0 BN |
3581 | } |
3582 | extid >>= 2; | |
3583 | /* Calc blocksize */ | |
3584 | mtd->erasesize = (128 * 1024) << | |
3585 | (((extid >> 1) & 0x04) | (extid & 0x03)); | |
3586 | *busw = 0; | |
73ca392f | 3587 | } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && |
1d0ed69d | 3588 | !nand_is_slc(chip)) { |
73ca392f BN |
3589 | unsigned int tmp; |
3590 | ||
3591 | /* Calc pagesize */ | |
3592 | mtd->writesize = 2048 << (extid & 0x03); | |
3593 | extid >>= 2; | |
3594 | /* Calc oobsize */ | |
3595 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { | |
3596 | case 0: | |
3597 | mtd->oobsize = 128; | |
3598 | break; | |
3599 | case 1: | |
3600 | mtd->oobsize = 224; | |
3601 | break; | |
3602 | case 2: | |
3603 | mtd->oobsize = 448; | |
3604 | break; | |
3605 | case 3: | |
3606 | mtd->oobsize = 64; | |
3607 | break; | |
3608 | case 4: | |
3609 | mtd->oobsize = 32; | |
3610 | break; | |
3611 | case 5: | |
3612 | mtd->oobsize = 16; | |
3613 | break; | |
3614 | default: | |
3615 | mtd->oobsize = 640; | |
3616 | break; | |
3617 | } | |
3618 | extid >>= 2; | |
3619 | /* Calc blocksize */ | |
3620 | tmp = ((extid >> 1) & 0x04) | (extid & 0x03); | |
3621 | if (tmp < 0x03) | |
3622 | mtd->erasesize = (128 * 1024) << tmp; | |
3623 | else if (tmp == 0x03) | |
3624 | mtd->erasesize = 768 * 1024; | |
3625 | else | |
3626 | mtd->erasesize = (64 * 1024) << tmp; | |
3627 | *busw = 0; | |
fc09bbc0 BN |
3628 | } else { |
3629 | /* Calc pagesize */ | |
3630 | mtd->writesize = 1024 << (extid & 0x03); | |
3631 | extid >>= 2; | |
3632 | /* Calc oobsize */ | |
3633 | mtd->oobsize = (8 << (extid & 0x01)) * | |
3634 | (mtd->writesize >> 9); | |
3635 | extid >>= 2; | |
3636 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
3637 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
3638 | extid >>= 2; | |
3639 | /* Get buswidth information */ | |
3640 | *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
60c67382 BN |
3641 | |
3642 | /* | |
3643 | * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per | |
3644 | * 512B page. For Toshiba SLC, we decode the 5th/6th byte as | |
3645 | * follows: | |
3646 | * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, | |
3647 | * 110b -> 24nm | |
3648 | * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC | |
3649 | */ | |
3650 | if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA && | |
1d0ed69d | 3651 | nand_is_slc(chip) && |
60c67382 BN |
3652 | (id_data[5] & 0x7) == 0x6 /* 24nm */ && |
3653 | !(id_data[4] & 0x80) /* !BENAND */) { | |
3654 | mtd->oobsize = 32 * mtd->writesize >> 9; | |
3655 | } | |
3656 | ||
fc09bbc0 BN |
3657 | } |
3658 | } | |
3659 | ||
f23a481c BN |
3660 | /* |
3661 | * Old devices have chip data hardcoded in the device ID table. nand_decode_id | |
3662 | * decodes a matching ID table entry and assigns the MTD size parameters for | |
3663 | * the chip. | |
3664 | */ | |
3665 | static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, | |
3666 | struct nand_flash_dev *type, u8 id_data[8], | |
3667 | int *busw) | |
3668 | { | |
3669 | int maf_id = id_data[0]; | |
3670 | ||
3671 | mtd->erasesize = type->erasesize; | |
3672 | mtd->writesize = type->pagesize; | |
3673 | mtd->oobsize = mtd->writesize / 32; | |
3674 | *busw = type->options & NAND_BUSWIDTH_16; | |
3675 | ||
1c195e90 HS |
3676 | /* All legacy ID NAND are small-page, SLC */ |
3677 | chip->bits_per_cell = 1; | |
3678 | ||
f23a481c BN |
3679 | /* |
3680 | * Check for Spansion/AMD ID + repeating 5th, 6th byte since | |
3681 | * some Spansion chips have erasesize that conflicts with size | |
3682 | * listed in nand_ids table. | |
3683 | * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) | |
3684 | */ | |
3685 | if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00 | |
3686 | && id_data[6] == 0x00 && id_data[7] == 0x00 | |
3687 | && mtd->writesize == 512) { | |
3688 | mtd->erasesize = 128 * 1024; | |
3689 | mtd->erasesize <<= ((id_data[3] & 0x03) << 1); | |
3690 | } | |
3691 | } | |
3692 | ||
7e74c2d7 BN |
3693 | /* |
3694 | * Set the bad block marker/indicator (BBM/BBI) patterns according to some | |
3695 | * heuristic patterns using various detected parameters (e.g., manufacturer, | |
3696 | * page size, cell-type information). | |
3697 | */ | |
3698 | static void nand_decode_bbm_options(struct mtd_info *mtd, | |
3699 | struct nand_chip *chip, u8 id_data[8]) | |
3700 | { | |
3701 | int maf_id = id_data[0]; | |
3702 | ||
3703 | /* Set the bad block position */ | |
3704 | if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) | |
3705 | chip->badblockpos = NAND_LARGE_BADBLOCK_POS; | |
3706 | else | |
3707 | chip->badblockpos = NAND_SMALL_BADBLOCK_POS; | |
3708 | ||
3709 | /* | |
3710 | * Bad block marker is stored in the last page of each block on Samsung | |
3711 | * and Hynix MLC devices; stored in first two pages of each block on | |
3712 | * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, | |
3713 | * AMD/Spansion, and Macronix. All others scan only the first page. | |
3714 | */ | |
1d0ed69d | 3715 | if (!nand_is_slc(chip) && |
7e74c2d7 BN |
3716 | (maf_id == NAND_MFR_SAMSUNG || |
3717 | maf_id == NAND_MFR_HYNIX)) | |
3718 | chip->bbt_options |= NAND_BBT_SCANLASTPAGE; | |
1d0ed69d | 3719 | else if ((nand_is_slc(chip) && |
7e74c2d7 BN |
3720 | (maf_id == NAND_MFR_SAMSUNG || |
3721 | maf_id == NAND_MFR_HYNIX || | |
3722 | maf_id == NAND_MFR_TOSHIBA || | |
3723 | maf_id == NAND_MFR_AMD || | |
3724 | maf_id == NAND_MFR_MACRONIX)) || | |
3725 | (mtd->writesize == 2048 && | |
3726 | maf_id == NAND_MFR_MICRON)) | |
3727 | chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; | |
3728 | } | |
3729 | ||
ec6e87e3 HS |
3730 | static inline bool is_full_id_nand(struct nand_flash_dev *type) |
3731 | { | |
3732 | return type->id_len; | |
3733 | } | |
3734 | ||
3735 | static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, | |
3736 | struct nand_flash_dev *type, u8 *id_data, int *busw) | |
3737 | { | |
3738 | if (!strncmp(type->id, id_data, type->id_len)) { | |
3739 | mtd->writesize = type->pagesize; | |
3740 | mtd->erasesize = type->erasesize; | |
3741 | mtd->oobsize = type->oobsize; | |
3742 | ||
7db906b7 | 3743 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
ec6e87e3 HS |
3744 | chip->chipsize = (uint64_t)type->chipsize << 20; |
3745 | chip->options |= type->options; | |
57219342 HS |
3746 | chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); |
3747 | chip->ecc_step_ds = NAND_ECC_STEP(type); | |
57a94e24 BB |
3748 | chip->onfi_timing_mode_default = |
3749 | type->onfi_timing_mode_default; | |
ec6e87e3 HS |
3750 | |
3751 | *busw = type->options & NAND_BUSWIDTH_16; | |
3752 | ||
092b6a1d CZ |
3753 | if (!mtd->name) |
3754 | mtd->name = type->name; | |
3755 | ||
ec6e87e3 HS |
3756 | return true; |
3757 | } | |
3758 | return false; | |
3759 | } | |
3760 | ||
7aa65bfd | 3761 | /* |
8b6e50c9 | 3762 | * Get the flash and manufacturer id and lookup if the type is supported. |
7aa65bfd TG |
3763 | */ |
3764 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 3765 | struct nand_chip *chip, |
7351d3a5 | 3766 | int *maf_id, int *dev_id, |
5e81e88a | 3767 | struct nand_flash_dev *type) |
7aa65bfd | 3768 | { |
bb77082f | 3769 | int busw; |
d1e1f4e4 | 3770 | int i, maf_idx; |
426c457a | 3771 | u8 id_data[8]; |
1da177e4 LT |
3772 | |
3773 | /* Select the device */ | |
ace4dfee | 3774 | chip->select_chip(mtd, 0); |
1da177e4 | 3775 | |
ef89a880 KB |
3776 | /* |
3777 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
8b6e50c9 | 3778 | * after power-up. |
ef89a880 KB |
3779 | */ |
3780 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
3781 | ||
1da177e4 | 3782 | /* Send the command for reading device ID */ |
ace4dfee | 3783 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
3784 | |
3785 | /* Read manufacturer and device IDs */ | |
ace4dfee | 3786 | *maf_id = chip->read_byte(mtd); |
d1e1f4e4 | 3787 | *dev_id = chip->read_byte(mtd); |
1da177e4 | 3788 | |
8b6e50c9 BN |
3789 | /* |
3790 | * Try again to make sure, as some systems the bus-hold or other | |
ed8165c7 BD |
3791 | * interface concerns can cause random data which looks like a |
3792 | * possibly credible NAND flash to appear. If the two results do | |
3793 | * not match, ignore the device completely. | |
3794 | */ | |
3795 | ||
3796 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
3797 | ||
4aef9b78 BN |
3798 | /* Read entire ID string */ |
3799 | for (i = 0; i < 8; i++) | |
426c457a | 3800 | id_data[i] = chip->read_byte(mtd); |
ed8165c7 | 3801 | |
d1e1f4e4 | 3802 | if (id_data[0] != *maf_id || id_data[1] != *dev_id) { |
20171642 | 3803 | pr_info("second ID read did not match %02x,%02x against %02x,%02x\n", |
d0370219 | 3804 | *maf_id, *dev_id, id_data[0], id_data[1]); |
ed8165c7 BD |
3805 | return ERR_PTR(-ENODEV); |
3806 | } | |
3807 | ||
7aa65bfd | 3808 | if (!type) |
5e81e88a DW |
3809 | type = nand_flash_ids; |
3810 | ||
ec6e87e3 HS |
3811 | for (; type->name != NULL; type++) { |
3812 | if (is_full_id_nand(type)) { | |
3813 | if (find_full_id_nand(mtd, chip, type, id_data, &busw)) | |
3814 | goto ident_done; | |
3815 | } else if (*dev_id == type->dev_id) { | |
db5b09f6 | 3816 | break; |
ec6e87e3 HS |
3817 | } |
3818 | } | |
5e81e88a | 3819 | |
d1e1f4e4 FF |
3820 | chip->onfi_version = 0; |
3821 | if (!type->name || !type->pagesize) { | |
35fc5195 | 3822 | /* Check if the chip is ONFI compliant */ |
47450b35 | 3823 | if (nand_flash_detect_onfi(mtd, chip, &busw)) |
6fb277ba | 3824 | goto ident_done; |
91361818 HS |
3825 | |
3826 | /* Check if the chip is JEDEC compliant */ | |
3827 | if (nand_flash_detect_jedec(mtd, chip, &busw)) | |
3828 | goto ident_done; | |
d1e1f4e4 FF |
3829 | } |
3830 | ||
5e81e88a | 3831 | if (!type->name) |
7aa65bfd TG |
3832 | return ERR_PTR(-ENODEV); |
3833 | ||
ba0251fe TG |
3834 | if (!mtd->name) |
3835 | mtd->name = type->name; | |
3836 | ||
69423d99 | 3837 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd | 3838 | |
12a40a57 | 3839 | if (!type->pagesize && chip->init_size) { |
8b6e50c9 | 3840 | /* Set the pagesize, oobsize, erasesize by the driver */ |
12a40a57 HS |
3841 | busw = chip->init_size(mtd, chip, id_data); |
3842 | } else if (!type->pagesize) { | |
fc09bbc0 BN |
3843 | /* Decode parameters from extended ID */ |
3844 | nand_decode_ext_id(mtd, chip, id_data, &busw); | |
7aa65bfd | 3845 | } else { |
f23a481c | 3846 | nand_decode_id(mtd, chip, type, id_data, &busw); |
7aa65bfd | 3847 | } |
bf7a01bf BN |
3848 | /* Get chip options */ |
3849 | chip->options |= type->options; | |
d1e1f4e4 | 3850 | |
8b6e50c9 BN |
3851 | /* |
3852 | * Check if chip is not a Samsung device. Do not clear the | |
3853 | * options for chips which do not have an extended id. | |
d1e1f4e4 FF |
3854 | */ |
3855 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) | |
3856 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; | |
3857 | ident_done: | |
3858 | ||
7aa65bfd | 3859 | /* Try to identify manufacturer */ |
9a909867 | 3860 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { |
7aa65bfd TG |
3861 | if (nand_manuf_ids[maf_idx].id == *maf_id) |
3862 | break; | |
3863 | } | |
0ea4a755 | 3864 | |
64b37b2a MC |
3865 | if (chip->options & NAND_BUSWIDTH_AUTO) { |
3866 | WARN_ON(chip->options & NAND_BUSWIDTH_16); | |
3867 | chip->options |= busw; | |
3868 | nand_set_defaults(chip, busw); | |
3869 | } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { | |
3870 | /* | |
3871 | * Check, if buswidth is correct. Hardware drivers should set | |
3872 | * chip correct! | |
3873 | */ | |
20171642 EG |
3874 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
3875 | *maf_id, *dev_id); | |
3876 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name); | |
3877 | pr_warn("bus width %d instead %d bit\n", | |
d0370219 BN |
3878 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
3879 | busw ? 16 : 8); | |
7aa65bfd TG |
3880 | return ERR_PTR(-EINVAL); |
3881 | } | |
61b03bd7 | 3882 | |
7e74c2d7 BN |
3883 | nand_decode_bbm_options(mtd, chip, id_data); |
3884 | ||
7aa65bfd | 3885 | /* Calculate the address shift from the page size */ |
ace4dfee | 3886 | chip->page_shift = ffs(mtd->writesize) - 1; |
8b6e50c9 | 3887 | /* Convert chipsize to number of pages per chip -1 */ |
ace4dfee | 3888 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 3889 | |
ace4dfee | 3890 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 3891 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
3892 | if (chip->chipsize & 0xffffffff) |
3893 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
7351d3a5 FF |
3894 | else { |
3895 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); | |
3896 | chip->chip_shift += 32 - 1; | |
3897 | } | |
1da177e4 | 3898 | |
26d9be11 | 3899 | chip->badblockbits = 8; |
49c50b97 | 3900 | chip->erase = single_erase; |
7aa65bfd | 3901 | |
8b6e50c9 | 3902 | /* Do not replace user supplied command function! */ |
ace4dfee TG |
3903 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
3904 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd | 3905 | |
20171642 EG |
3906 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
3907 | *maf_id, *dev_id); | |
ffdac6cd HS |
3908 | |
3909 | if (chip->onfi_version) | |
3910 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3911 | chip->onfi_params.model); | |
3912 | else if (chip->jedec_version) | |
3913 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3914 | chip->jedec_params.model); | |
3915 | else | |
3916 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3917 | type->name); | |
3918 | ||
3755a991 | 3919 | pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n", |
3723e93c | 3920 | (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", |
3755a991 | 3921 | mtd->erasesize >> 10, mtd->writesize, mtd->oobsize); |
7aa65bfd TG |
3922 | return type; |
3923 | } | |
3924 | ||
5844feea BN |
3925 | static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, |
3926 | struct device_node *dn) | |
3927 | { | |
3928 | int ecc_mode, ecc_strength, ecc_step; | |
3929 | ||
3930 | if (of_get_nand_bus_width(dn) == 16) | |
3931 | chip->options |= NAND_BUSWIDTH_16; | |
3932 | ||
3933 | if (of_get_nand_on_flash_bbt(dn)) | |
3934 | chip->bbt_options |= NAND_BBT_USE_FLASH; | |
3935 | ||
3936 | ecc_mode = of_get_nand_ecc_mode(dn); | |
3937 | ecc_strength = of_get_nand_ecc_strength(dn); | |
3938 | ecc_step = of_get_nand_ecc_step_size(dn); | |
3939 | ||
3940 | if ((ecc_step >= 0 && !(ecc_strength >= 0)) || | |
3941 | (!(ecc_step >= 0) && ecc_strength >= 0)) { | |
3942 | pr_err("must set both strength and step size in DT\n"); | |
3943 | return -EINVAL; | |
3944 | } | |
3945 | ||
3946 | if (ecc_mode >= 0) | |
3947 | chip->ecc.mode = ecc_mode; | |
3948 | ||
3949 | if (ecc_strength >= 0) | |
3950 | chip->ecc.strength = ecc_strength; | |
3951 | ||
3952 | if (ecc_step > 0) | |
3953 | chip->ecc.size = ecc_step; | |
3954 | ||
3955 | return 0; | |
3956 | } | |
3957 | ||
7aa65bfd | 3958 | /** |
3b85c321 | 3959 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
8b6e50c9 BN |
3960 | * @mtd: MTD device structure |
3961 | * @maxchips: number of chips to scan for | |
3962 | * @table: alternative NAND ID table | |
7aa65bfd | 3963 | * |
8b6e50c9 BN |
3964 | * This is the first phase of the normal nand_scan() function. It reads the |
3965 | * flash ID and sets up MTD fields accordingly. | |
7aa65bfd | 3966 | * |
3b85c321 | 3967 | * The mtd->owner field must be set to the module of the caller. |
7aa65bfd | 3968 | */ |
5e81e88a DW |
3969 | int nand_scan_ident(struct mtd_info *mtd, int maxchips, |
3970 | struct nand_flash_dev *table) | |
7aa65bfd | 3971 | { |
bb77082f | 3972 | int i, nand_maf_id, nand_dev_id; |
ace4dfee | 3973 | struct nand_chip *chip = mtd->priv; |
7aa65bfd | 3974 | struct nand_flash_dev *type; |
5844feea BN |
3975 | int ret; |
3976 | ||
61528d88 MV |
3977 | if (chip->flash_node) { |
3978 | ret = nand_dt_init(mtd, chip, chip->flash_node); | |
5844feea BN |
3979 | if (ret) |
3980 | return ret; | |
3981 | } | |
7aa65bfd | 3982 | |
7aa65bfd | 3983 | /* Set the default functions */ |
bb77082f | 3984 | nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16); |
7aa65bfd TG |
3985 | |
3986 | /* Read the flash type */ | |
bb77082f CZ |
3987 | type = nand_get_flash_type(mtd, chip, &nand_maf_id, |
3988 | &nand_dev_id, table); | |
7aa65bfd TG |
3989 | |
3990 | if (IS_ERR(type)) { | |
b1c6e6db | 3991 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
d0370219 | 3992 | pr_warn("No NAND device found\n"); |
ace4dfee | 3993 | chip->select_chip(mtd, -1); |
7aa65bfd | 3994 | return PTR_ERR(type); |
1da177e4 LT |
3995 | } |
3996 | ||
07300164 HS |
3997 | chip->select_chip(mtd, -1); |
3998 | ||
7aa65bfd | 3999 | /* Check for a chip array */ |
e0c7d767 | 4000 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 4001 | chip->select_chip(mtd, i); |
ef89a880 KB |
4002 | /* See comment in nand_get_flash_type for reset */ |
4003 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1da177e4 | 4004 | /* Send the command for reading device ID */ |
ace4dfee | 4005 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 4006 | /* Read manufacturer and device IDs */ |
ace4dfee | 4007 | if (nand_maf_id != chip->read_byte(mtd) || |
07300164 HS |
4008 | nand_dev_id != chip->read_byte(mtd)) { |
4009 | chip->select_chip(mtd, -1); | |
1da177e4 | 4010 | break; |
07300164 HS |
4011 | } |
4012 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
4013 | } |
4014 | if (i > 1) | |
20171642 | 4015 | pr_info("%d chips detected\n", i); |
61b03bd7 | 4016 | |
1da177e4 | 4017 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
4018 | chip->numchips = i; |
4019 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 4020 | |
3b85c321 DW |
4021 | return 0; |
4022 | } | |
7351d3a5 | 4023 | EXPORT_SYMBOL(nand_scan_ident); |
3b85c321 | 4024 | |
67a9ad9b EG |
4025 | /* |
4026 | * Check if the chip configuration meet the datasheet requirements. | |
4027 | ||
4028 | * If our configuration corrects A bits per B bytes and the minimum | |
4029 | * required correction level is X bits per Y bytes, then we must ensure | |
4030 | * both of the following are true: | |
4031 | * | |
4032 | * (1) A / B >= X / Y | |
4033 | * (2) A >= X | |
4034 | * | |
4035 | * Requirement (1) ensures we can correct for the required bitflip density. | |
4036 | * Requirement (2) ensures we can correct even when all bitflips are clumped | |
4037 | * in the same sector. | |
4038 | */ | |
4039 | static bool nand_ecc_strength_good(struct mtd_info *mtd) | |
4040 | { | |
4041 | struct nand_chip *chip = mtd->priv; | |
4042 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
4043 | int corr, ds_corr; | |
4044 | ||
4045 | if (ecc->size == 0 || chip->ecc_step_ds == 0) | |
4046 | /* Not enough information */ | |
4047 | return true; | |
4048 | ||
4049 | /* | |
4050 | * We get the number of corrected bits per page to compare | |
4051 | * the correction density. | |
4052 | */ | |
4053 | corr = (mtd->writesize * ecc->strength) / ecc->size; | |
4054 | ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds; | |
4055 | ||
4056 | return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds; | |
4057 | } | |
3b85c321 DW |
4058 | |
4059 | /** | |
4060 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
8b6e50c9 | 4061 | * @mtd: MTD device structure |
3b85c321 | 4062 | * |
8b6e50c9 BN |
4063 | * This is the second phase of the normal nand_scan() function. It fills out |
4064 | * all the uninitialized function pointers with the defaults and scans for a | |
4065 | * bad block table if appropriate. | |
3b85c321 DW |
4066 | */ |
4067 | int nand_scan_tail(struct mtd_info *mtd) | |
4068 | { | |
4069 | int i; | |
4070 | struct nand_chip *chip = mtd->priv; | |
97de79e0 | 4071 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
f02ea4e6 | 4072 | struct nand_buffers *nbuf; |
3b85c321 | 4073 | |
e2414f4c BN |
4074 | /* New bad blocks should be marked in OOB, flash-based BBT, or both */ |
4075 | BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && | |
4076 | !(chip->bbt_options & NAND_BBT_USE_FLASH)); | |
4077 | ||
f02ea4e6 HS |
4078 | if (!(chip->options & NAND_OWN_BUFFERS)) { |
4079 | nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize | |
4080 | + mtd->oobsize * 3, GFP_KERNEL); | |
4081 | if (!nbuf) | |
4082 | return -ENOMEM; | |
4083 | nbuf->ecccalc = (uint8_t *)(nbuf + 1); | |
4084 | nbuf->ecccode = nbuf->ecccalc + mtd->oobsize; | |
4085 | nbuf->databuf = nbuf->ecccode + mtd->oobsize; | |
4086 | ||
4087 | chip->buffers = nbuf; | |
4088 | } else { | |
4089 | if (!chip->buffers) | |
4090 | return -ENOMEM; | |
4091 | } | |
4bf63fcb | 4092 | |
7dcdcbef | 4093 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 4094 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 4095 | |
7aa65bfd | 4096 | /* |
8b6e50c9 | 4097 | * If no default placement scheme is given, select an appropriate one. |
7aa65bfd | 4098 | */ |
97de79e0 | 4099 | if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) { |
61b03bd7 | 4100 | switch (mtd->oobsize) { |
1da177e4 | 4101 | case 8: |
97de79e0 | 4102 | ecc->layout = &nand_oob_8; |
1da177e4 LT |
4103 | break; |
4104 | case 16: | |
97de79e0 | 4105 | ecc->layout = &nand_oob_16; |
1da177e4 LT |
4106 | break; |
4107 | case 64: | |
97de79e0 | 4108 | ecc->layout = &nand_oob_64; |
1da177e4 | 4109 | break; |
81ec5364 | 4110 | case 128: |
97de79e0 | 4111 | ecc->layout = &nand_oob_128; |
81ec5364 | 4112 | break; |
1da177e4 | 4113 | default: |
d0370219 BN |
4114 | pr_warn("No oob scheme defined for oobsize %d\n", |
4115 | mtd->oobsize); | |
1da177e4 LT |
4116 | BUG(); |
4117 | } | |
4118 | } | |
61b03bd7 | 4119 | |
956e944c DW |
4120 | if (!chip->write_page) |
4121 | chip->write_page = nand_write_page; | |
4122 | ||
61b03bd7 | 4123 | /* |
8b6e50c9 | 4124 | * Check ECC mode, default to software if 3byte/512byte hardware ECC is |
7aa65bfd | 4125 | * selected and we have 256 byte pagesize fallback to software ECC |
e0c7d767 | 4126 | */ |
956e944c | 4127 | |
97de79e0 | 4128 | switch (ecc->mode) { |
6e0cb135 SN |
4129 | case NAND_ECC_HW_OOB_FIRST: |
4130 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
97de79e0 | 4131 | if (!ecc->calculate || !ecc->correct || !ecc->hwctl) { |
2ac63d90 | 4132 | pr_warn("No ECC functions supplied; hardware ECC not possible\n"); |
6e0cb135 SN |
4133 | BUG(); |
4134 | } | |
97de79e0 HS |
4135 | if (!ecc->read_page) |
4136 | ecc->read_page = nand_read_page_hwecc_oob_first; | |
6e0cb135 | 4137 | |
6dfc6d25 | 4138 | case NAND_ECC_HW: |
8b6e50c9 | 4139 | /* Use standard hwecc read page function? */ |
97de79e0 HS |
4140 | if (!ecc->read_page) |
4141 | ecc->read_page = nand_read_page_hwecc; | |
4142 | if (!ecc->write_page) | |
4143 | ecc->write_page = nand_write_page_hwecc; | |
4144 | if (!ecc->read_page_raw) | |
4145 | ecc->read_page_raw = nand_read_page_raw; | |
4146 | if (!ecc->write_page_raw) | |
4147 | ecc->write_page_raw = nand_write_page_raw; | |
4148 | if (!ecc->read_oob) | |
4149 | ecc->read_oob = nand_read_oob_std; | |
4150 | if (!ecc->write_oob) | |
4151 | ecc->write_oob = nand_write_oob_std; | |
4152 | if (!ecc->read_subpage) | |
4153 | ecc->read_subpage = nand_read_subpage; | |
4154 | if (!ecc->write_subpage) | |
4155 | ecc->write_subpage = nand_write_subpage_hwecc; | |
f5bbdacc | 4156 | |
6dfc6d25 | 4157 | case NAND_ECC_HW_SYNDROME: |
97de79e0 HS |
4158 | if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && |
4159 | (!ecc->read_page || | |
4160 | ecc->read_page == nand_read_page_hwecc || | |
4161 | !ecc->write_page || | |
4162 | ecc->write_page == nand_write_page_hwecc)) { | |
2ac63d90 | 4163 | pr_warn("No ECC functions supplied; hardware ECC not possible\n"); |
6dfc6d25 TG |
4164 | BUG(); |
4165 | } | |
8b6e50c9 | 4166 | /* Use standard syndrome read/write page function? */ |
97de79e0 HS |
4167 | if (!ecc->read_page) |
4168 | ecc->read_page = nand_read_page_syndrome; | |
4169 | if (!ecc->write_page) | |
4170 | ecc->write_page = nand_write_page_syndrome; | |
4171 | if (!ecc->read_page_raw) | |
4172 | ecc->read_page_raw = nand_read_page_raw_syndrome; | |
4173 | if (!ecc->write_page_raw) | |
4174 | ecc->write_page_raw = nand_write_page_raw_syndrome; | |
4175 | if (!ecc->read_oob) | |
4176 | ecc->read_oob = nand_read_oob_syndrome; | |
4177 | if (!ecc->write_oob) | |
4178 | ecc->write_oob = nand_write_oob_syndrome; | |
4179 | ||
4180 | if (mtd->writesize >= ecc->size) { | |
4181 | if (!ecc->strength) { | |
e2788c98 MD |
4182 | pr_warn("Driver must set ecc.strength when using hardware ECC\n"); |
4183 | BUG(); | |
4184 | } | |
6dfc6d25 | 4185 | break; |
e2788c98 | 4186 | } |
2ac63d90 RM |
4187 | pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", |
4188 | ecc->size, mtd->writesize); | |
97de79e0 | 4189 | ecc->mode = NAND_ECC_SOFT; |
61b03bd7 | 4190 | |
6dfc6d25 | 4191 | case NAND_ECC_SOFT: |
97de79e0 HS |
4192 | ecc->calculate = nand_calculate_ecc; |
4193 | ecc->correct = nand_correct_data; | |
4194 | ecc->read_page = nand_read_page_swecc; | |
4195 | ecc->read_subpage = nand_read_subpage; | |
4196 | ecc->write_page = nand_write_page_swecc; | |
4197 | ecc->read_page_raw = nand_read_page_raw; | |
4198 | ecc->write_page_raw = nand_write_page_raw; | |
4199 | ecc->read_oob = nand_read_oob_std; | |
4200 | ecc->write_oob = nand_write_oob_std; | |
4201 | if (!ecc->size) | |
4202 | ecc->size = 256; | |
4203 | ecc->bytes = 3; | |
4204 | ecc->strength = 1; | |
1da177e4 | 4205 | break; |
61b03bd7 | 4206 | |
193bd400 ID |
4207 | case NAND_ECC_SOFT_BCH: |
4208 | if (!mtd_nand_has_bch()) { | |
148256fa | 4209 | pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n"); |
193bd400 ID |
4210 | BUG(); |
4211 | } | |
97de79e0 HS |
4212 | ecc->calculate = nand_bch_calculate_ecc; |
4213 | ecc->correct = nand_bch_correct_data; | |
4214 | ecc->read_page = nand_read_page_swecc; | |
4215 | ecc->read_subpage = nand_read_subpage; | |
4216 | ecc->write_page = nand_write_page_swecc; | |
4217 | ecc->read_page_raw = nand_read_page_raw; | |
4218 | ecc->write_page_raw = nand_write_page_raw; | |
4219 | ecc->read_oob = nand_read_oob_std; | |
4220 | ecc->write_oob = nand_write_oob_std; | |
193bd400 | 4221 | /* |
e0377cde AS |
4222 | * Board driver should supply ecc.size and ecc.strength values |
4223 | * to select how many bits are correctable. Otherwise, default | |
4224 | * to 4 bits for large page devices. | |
193bd400 | 4225 | */ |
97de79e0 HS |
4226 | if (!ecc->size && (mtd->oobsize >= 64)) { |
4227 | ecc->size = 512; | |
e0377cde | 4228 | ecc->strength = 4; |
193bd400 | 4229 | } |
e0377cde AS |
4230 | |
4231 | /* See nand_bch_init() for details. */ | |
4232 | ecc->bytes = DIV_ROUND_UP( | |
4233 | ecc->strength * fls(8 * ecc->size), 8); | |
97de79e0 HS |
4234 | ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes, |
4235 | &ecc->layout); | |
4236 | if (!ecc->priv) { | |
9a4d4d69 | 4237 | pr_warn("BCH ECC initialization failed!\n"); |
193bd400 ID |
4238 | BUG(); |
4239 | } | |
4240 | break; | |
4241 | ||
61b03bd7 | 4242 | case NAND_ECC_NONE: |
2ac63d90 | 4243 | pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n"); |
97de79e0 HS |
4244 | ecc->read_page = nand_read_page_raw; |
4245 | ecc->write_page = nand_write_page_raw; | |
4246 | ecc->read_oob = nand_read_oob_std; | |
4247 | ecc->read_page_raw = nand_read_page_raw; | |
4248 | ecc->write_page_raw = nand_write_page_raw; | |
4249 | ecc->write_oob = nand_write_oob_std; | |
4250 | ecc->size = mtd->writesize; | |
4251 | ecc->bytes = 0; | |
4252 | ecc->strength = 0; | |
1da177e4 | 4253 | break; |
956e944c | 4254 | |
1da177e4 | 4255 | default: |
97de79e0 | 4256 | pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode); |
61b03bd7 | 4257 | BUG(); |
1da177e4 | 4258 | } |
61b03bd7 | 4259 | |
9ce244b3 | 4260 | /* For many systems, the standard OOB write also works for raw */ |
97de79e0 HS |
4261 | if (!ecc->read_oob_raw) |
4262 | ecc->read_oob_raw = ecc->read_oob; | |
4263 | if (!ecc->write_oob_raw) | |
4264 | ecc->write_oob_raw = ecc->write_oob; | |
9ce244b3 | 4265 | |
5bd34c09 TG |
4266 | /* |
4267 | * The number of bytes available for a client to place data into | |
8b6e50c9 | 4268 | * the out of band area. |
5bd34c09 | 4269 | */ |
97de79e0 HS |
4270 | ecc->layout->oobavail = 0; |
4271 | for (i = 0; ecc->layout->oobfree[i].length | |
4272 | && i < ARRAY_SIZE(ecc->layout->oobfree); i++) | |
4273 | ecc->layout->oobavail += ecc->layout->oobfree[i].length; | |
4274 | mtd->oobavail = ecc->layout->oobavail; | |
5bd34c09 | 4275 | |
54c39e9b TP |
4276 | /* ECC sanity check: warn if it's too weak */ |
4277 | if (!nand_ecc_strength_good(mtd)) | |
4278 | pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n", | |
4279 | mtd->name); | |
67a9ad9b | 4280 | |
7aa65bfd TG |
4281 | /* |
4282 | * Set the number of read / write steps for one page depending on ECC | |
8b6e50c9 | 4283 | * mode. |
7aa65bfd | 4284 | */ |
97de79e0 HS |
4285 | ecc->steps = mtd->writesize / ecc->size; |
4286 | if (ecc->steps * ecc->size != mtd->writesize) { | |
9a4d4d69 | 4287 | pr_warn("Invalid ECC parameters\n"); |
6dfc6d25 | 4288 | BUG(); |
1da177e4 | 4289 | } |
97de79e0 | 4290 | ecc->total = ecc->steps * ecc->bytes; |
61b03bd7 | 4291 | |
8b6e50c9 | 4292 | /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ |
1d0ed69d | 4293 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { |
97de79e0 | 4294 | switch (ecc->steps) { |
29072b96 TG |
4295 | case 2: |
4296 | mtd->subpage_sft = 1; | |
4297 | break; | |
4298 | case 4: | |
4299 | case 8: | |
81ec5364 | 4300 | case 16: |
29072b96 TG |
4301 | mtd->subpage_sft = 2; |
4302 | break; | |
4303 | } | |
4304 | } | |
4305 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
4306 | ||
04bbd0ea | 4307 | /* Initialize state */ |
ace4dfee | 4308 | chip->state = FL_READY; |
1da177e4 | 4309 | |
1da177e4 | 4310 | /* Invalidate the pagebuffer reference */ |
ace4dfee | 4311 | chip->pagebuf = -1; |
1da177e4 | 4312 | |
a5ff4f10 | 4313 | /* Large page NAND with SOFT_ECC should support subpage reads */ |
4007e2d1 RL |
4314 | switch (ecc->mode) { |
4315 | case NAND_ECC_SOFT: | |
4316 | case NAND_ECC_SOFT_BCH: | |
4317 | if (chip->page_shift > 9) | |
4318 | chip->options |= NAND_SUBPAGE_READ; | |
4319 | break; | |
4320 | ||
4321 | default: | |
4322 | break; | |
4323 | } | |
a5ff4f10 | 4324 | |
1da177e4 | 4325 | /* Fill in remaining MTD driver data */ |
963d1c28 | 4326 | mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH; |
93edbad6 ML |
4327 | mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : |
4328 | MTD_CAP_NANDFLASH; | |
3c3c10bb AB |
4329 | mtd->_erase = nand_erase; |
4330 | mtd->_point = NULL; | |
4331 | mtd->_unpoint = NULL; | |
4332 | mtd->_read = nand_read; | |
4333 | mtd->_write = nand_write; | |
4334 | mtd->_panic_write = panic_nand_write; | |
4335 | mtd->_read_oob = nand_read_oob; | |
4336 | mtd->_write_oob = nand_write_oob; | |
4337 | mtd->_sync = nand_sync; | |
4338 | mtd->_lock = NULL; | |
4339 | mtd->_unlock = NULL; | |
4340 | mtd->_suspend = nand_suspend; | |
4341 | mtd->_resume = nand_resume; | |
72ea4036 | 4342 | mtd->_reboot = nand_shutdown; |
8471bb73 | 4343 | mtd->_block_isreserved = nand_block_isreserved; |
3c3c10bb AB |
4344 | mtd->_block_isbad = nand_block_isbad; |
4345 | mtd->_block_markbad = nand_block_markbad; | |
cbcab65a | 4346 | mtd->writebufsize = mtd->writesize; |
1da177e4 | 4347 | |
6a918bad | 4348 | /* propagate ecc info to mtd_info */ |
97de79e0 HS |
4349 | mtd->ecclayout = ecc->layout; |
4350 | mtd->ecc_strength = ecc->strength; | |
4351 | mtd->ecc_step_size = ecc->size; | |
ea3b2ea2 SL |
4352 | /* |
4353 | * Initialize bitflip_threshold to its default prior scan_bbt() call. | |
4354 | * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be | |
4355 | * properly set. | |
4356 | */ | |
4357 | if (!mtd->bitflip_threshold) | |
240181fd | 4358 | mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4); |
1da177e4 | 4359 | |
0040bf38 | 4360 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 4361 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 4362 | return 0; |
1da177e4 LT |
4363 | |
4364 | /* Build bad block table */ | |
ace4dfee | 4365 | return chip->scan_bbt(mtd); |
1da177e4 | 4366 | } |
7351d3a5 | 4367 | EXPORT_SYMBOL(nand_scan_tail); |
1da177e4 | 4368 | |
8b6e50c9 BN |
4369 | /* |
4370 | * is_module_text_address() isn't exported, and it's mostly a pointless | |
7351d3a5 | 4371 | * test if this is a module _anyway_ -- they'd have to try _really_ hard |
8b6e50c9 BN |
4372 | * to call us from in-kernel code if the core NAND support is modular. |
4373 | */ | |
3b85c321 DW |
4374 | #ifdef MODULE |
4375 | #define caller_is_module() (1) | |
4376 | #else | |
4377 | #define caller_is_module() \ | |
a6e6abd5 | 4378 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
4379 | #endif |
4380 | ||
4381 | /** | |
4382 | * nand_scan - [NAND Interface] Scan for the NAND device | |
8b6e50c9 BN |
4383 | * @mtd: MTD device structure |
4384 | * @maxchips: number of chips to scan for | |
3b85c321 | 4385 | * |
8b6e50c9 BN |
4386 | * This fills out all the uninitialized function pointers with the defaults. |
4387 | * The flash ID is read and the mtd/chip structures are filled with the | |
4388 | * appropriate values. The mtd->owner field must be set to the module of the | |
4389 | * caller. | |
3b85c321 DW |
4390 | */ |
4391 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
4392 | { | |
4393 | int ret; | |
4394 | ||
4395 | /* Many callers got this wrong, so check for it for a while... */ | |
4396 | if (!mtd->owner && caller_is_module()) { | |
d0370219 | 4397 | pr_crit("%s called with NULL mtd->owner!\n", __func__); |
3b85c321 DW |
4398 | BUG(); |
4399 | } | |
4400 | ||
5e81e88a | 4401 | ret = nand_scan_ident(mtd, maxchips, NULL); |
3b85c321 DW |
4402 | if (!ret) |
4403 | ret = nand_scan_tail(mtd); | |
4404 | return ret; | |
4405 | } | |
7351d3a5 | 4406 | EXPORT_SYMBOL(nand_scan); |
3b85c321 | 4407 | |
1da177e4 | 4408 | /** |
61b03bd7 | 4409 | * nand_release - [NAND Interface] Free resources held by the NAND device |
8b6e50c9 BN |
4410 | * @mtd: MTD device structure |
4411 | */ | |
e0c7d767 | 4412 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 4413 | { |
ace4dfee | 4414 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 4415 | |
193bd400 ID |
4416 | if (chip->ecc.mode == NAND_ECC_SOFT_BCH) |
4417 | nand_bch_free((struct nand_bch_control *)chip->ecc.priv); | |
4418 | ||
5ffcaf3d | 4419 | mtd_device_unregister(mtd); |
1da177e4 | 4420 | |
fa671646 | 4421 | /* Free bad block table memory */ |
ace4dfee | 4422 | kfree(chip->bbt); |
4bf63fcb DW |
4423 | if (!(chip->options & NAND_OWN_BUFFERS)) |
4424 | kfree(chip->buffers); | |
58373ff0 BN |
4425 | |
4426 | /* Free bad block descriptor memory */ | |
4427 | if (chip->badblock_pattern && chip->badblock_pattern->options | |
4428 | & NAND_BBT_DYNAMICSTRUCT) | |
4429 | kfree(chip->badblock_pattern); | |
1da177e4 | 4430 | } |
e0c7d767 | 4431 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 RP |
4432 | |
4433 | static int __init nand_base_init(void) | |
4434 | { | |
4435 | led_trigger_register_simple("nand-disk", &nand_led_trigger); | |
4436 | return 0; | |
4437 | } | |
4438 | ||
4439 | static void __exit nand_base_exit(void) | |
4440 | { | |
4441 | led_trigger_unregister_simple(nand_led_trigger); | |
4442 | } | |
4443 | ||
4444 | module_init(nand_base_init); | |
4445 | module_exit(nand_base_exit); | |
4446 | ||
e0c7d767 | 4447 | MODULE_LICENSE("GPL"); |
7351d3a5 FF |
4448 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); |
4449 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
e0c7d767 | 4450 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |