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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand.c | |
3 | * | |
4 | * Overview: | |
5 | * This is the generic MTD driver for NAND flash devices. It should be | |
6 | * capable of working with almost all NAND chips currently available. | |
7 | * Basic support for AG-AND chips is provided. | |
61b03bd7 | 8 | * |
1da177e4 | 9 | * Additional technical information is available on |
8b2b403c | 10 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 11 | * |
1da177e4 | 12 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 13 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 14 | * |
ace4dfee | 15 | * Credits: |
61b03bd7 TG |
16 | * David Woodhouse for adding multichip support |
17 | * | |
1da177e4 LT |
18 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
19 | * rework for 2K page size chips | |
20 | * | |
ace4dfee | 21 | * TODO: |
1da177e4 LT |
22 | * Enable cached programming for 2k page size chips |
23 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
24 | * if we have HW ecc support. | |
25 | * The AG-AND chips have nice features for speed improvement, | |
26 | * which are not supported yet. Read / program 4 pages in one go. | |
c0b8ba7b | 27 | * BBT table is not serialized, has to be fixed |
1da177e4 | 28 | * |
1da177e4 LT |
29 | * This program is free software; you can redistribute it and/or modify |
30 | * it under the terms of the GNU General Public License version 2 as | |
31 | * published by the Free Software Foundation. | |
32 | * | |
33 | */ | |
34 | ||
552d9205 | 35 | #include <linux/module.h> |
1da177e4 LT |
36 | #include <linux/delay.h> |
37 | #include <linux/errno.h> | |
7aa65bfd | 38 | #include <linux/err.h> |
1da177e4 LT |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
41 | #include <linux/types.h> | |
42 | #include <linux/mtd/mtd.h> | |
43 | #include <linux/mtd/nand.h> | |
44 | #include <linux/mtd/nand_ecc.h> | |
45 | #include <linux/mtd/compatmac.h> | |
46 | #include <linux/interrupt.h> | |
47 | #include <linux/bitops.h> | |
8fe833c1 | 48 | #include <linux/leds.h> |
1da177e4 LT |
49 | #include <asm/io.h> |
50 | ||
51 | #ifdef CONFIG_MTD_PARTITIONS | |
52 | #include <linux/mtd/partitions.h> | |
53 | #endif | |
54 | ||
55 | /* Define default oob placement schemes for large and small page devices */ | |
5bd34c09 | 56 | static struct nand_ecclayout nand_oob_8 = { |
1da177e4 LT |
57 | .eccbytes = 3, |
58 | .eccpos = {0, 1, 2}, | |
5bd34c09 TG |
59 | .oobfree = { |
60 | {.offset = 3, | |
61 | .length = 2}, | |
62 | {.offset = 6, | |
63 | .length = 2}} | |
1da177e4 LT |
64 | }; |
65 | ||
5bd34c09 | 66 | static struct nand_ecclayout nand_oob_16 = { |
1da177e4 LT |
67 | .eccbytes = 6, |
68 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
5bd34c09 TG |
69 | .oobfree = { |
70 | {.offset = 8, | |
71 | . length = 8}} | |
1da177e4 LT |
72 | }; |
73 | ||
5bd34c09 | 74 | static struct nand_ecclayout nand_oob_64 = { |
1da177e4 LT |
75 | .eccbytes = 24, |
76 | .eccpos = { | |
e0c7d767 DW |
77 | 40, 41, 42, 43, 44, 45, 46, 47, |
78 | 48, 49, 50, 51, 52, 53, 54, 55, | |
79 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
5bd34c09 TG |
80 | .oobfree = { |
81 | {.offset = 2, | |
82 | .length = 38}} | |
1da177e4 LT |
83 | }; |
84 | ||
81ec5364 TG |
85 | static struct nand_ecclayout nand_oob_128 = { |
86 | .eccbytes = 48, | |
87 | .eccpos = { | |
88 | 80, 81, 82, 83, 84, 85, 86, 87, | |
89 | 88, 89, 90, 91, 92, 93, 94, 95, | |
90 | 96, 97, 98, 99, 100, 101, 102, 103, | |
91 | 104, 105, 106, 107, 108, 109, 110, 111, | |
92 | 112, 113, 114, 115, 116, 117, 118, 119, | |
93 | 120, 121, 122, 123, 124, 125, 126, 127}, | |
94 | .oobfree = { | |
95 | {.offset = 2, | |
96 | .length = 78}} | |
97 | }; | |
98 | ||
ace4dfee | 99 | static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, |
2c0a2bed | 100 | int new_state); |
1da177e4 | 101 | |
8593fbc6 TG |
102 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
103 | struct mtd_oob_ops *ops); | |
104 | ||
d470a97c | 105 | /* |
8e87d782 | 106 | * For devices which display every fart in the system on a separate LED. Is |
d470a97c TG |
107 | * compiled away when LED support is disabled. |
108 | */ | |
109 | DEFINE_LED_TRIGGER(nand_led_trigger); | |
110 | ||
6fe5a6ac VS |
111 | static int check_offs_len(struct mtd_info *mtd, |
112 | loff_t ofs, uint64_t len) | |
113 | { | |
114 | struct nand_chip *chip = mtd->priv; | |
115 | int ret = 0; | |
116 | ||
117 | /* Start address must align on block boundary */ | |
118 | if (ofs & ((1 << chip->phys_erase_shift) - 1)) { | |
119 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__); | |
120 | ret = -EINVAL; | |
121 | } | |
122 | ||
123 | /* Length must align on block boundary */ | |
124 | if (len & ((1 << chip->phys_erase_shift) - 1)) { | |
125 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n", | |
126 | __func__); | |
127 | ret = -EINVAL; | |
128 | } | |
129 | ||
130 | /* Do not allow past end of device */ | |
131 | if (ofs + len > mtd->size) { | |
132 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n", | |
133 | __func__); | |
134 | ret = -EINVAL; | |
135 | } | |
136 | ||
137 | return ret; | |
138 | } | |
139 | ||
1da177e4 LT |
140 | /** |
141 | * nand_release_device - [GENERIC] release chip | |
142 | * @mtd: MTD device structure | |
61b03bd7 TG |
143 | * |
144 | * Deselect, release chip lock and wake up anyone waiting on the device | |
1da177e4 | 145 | */ |
e0c7d767 | 146 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 147 | { |
ace4dfee | 148 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
149 | |
150 | /* De-select the NAND device */ | |
ace4dfee | 151 | chip->select_chip(mtd, -1); |
0dfc6246 | 152 | |
a36ed299 | 153 | /* Release the controller and the chip */ |
ace4dfee TG |
154 | spin_lock(&chip->controller->lock); |
155 | chip->controller->active = NULL; | |
156 | chip->state = FL_READY; | |
157 | wake_up(&chip->controller->wq); | |
158 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
159 | } |
160 | ||
161 | /** | |
162 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
163 | * @mtd: MTD device structure | |
164 | * | |
165 | * Default read function for 8bit buswith | |
166 | */ | |
58dd8f2b | 167 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 168 | { |
ace4dfee TG |
169 | struct nand_chip *chip = mtd->priv; |
170 | return readb(chip->IO_ADDR_R); | |
1da177e4 LT |
171 | } |
172 | ||
1da177e4 LT |
173 | /** |
174 | * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip | |
175 | * @mtd: MTD device structure | |
176 | * | |
61b03bd7 | 177 | * Default read function for 16bit buswith with |
1da177e4 LT |
178 | * endianess conversion |
179 | */ | |
58dd8f2b | 180 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 181 | { |
ace4dfee TG |
182 | struct nand_chip *chip = mtd->priv; |
183 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); | |
1da177e4 LT |
184 | } |
185 | ||
1da177e4 LT |
186 | /** |
187 | * nand_read_word - [DEFAULT] read one word from the chip | |
188 | * @mtd: MTD device structure | |
189 | * | |
61b03bd7 | 190 | * Default read function for 16bit buswith without |
1da177e4 LT |
191 | * endianess conversion |
192 | */ | |
193 | static u16 nand_read_word(struct mtd_info *mtd) | |
194 | { | |
ace4dfee TG |
195 | struct nand_chip *chip = mtd->priv; |
196 | return readw(chip->IO_ADDR_R); | |
1da177e4 LT |
197 | } |
198 | ||
1da177e4 LT |
199 | /** |
200 | * nand_select_chip - [DEFAULT] control CE line | |
201 | * @mtd: MTD device structure | |
844d3b42 | 202 | * @chipnr: chipnumber to select, -1 for deselect |
1da177e4 LT |
203 | * |
204 | * Default select function for 1 chip devices. | |
205 | */ | |
ace4dfee | 206 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 207 | { |
ace4dfee TG |
208 | struct nand_chip *chip = mtd->priv; |
209 | ||
210 | switch (chipnr) { | |
1da177e4 | 211 | case -1: |
ace4dfee | 212 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
213 | break; |
214 | case 0: | |
1da177e4 LT |
215 | break; |
216 | ||
217 | default: | |
218 | BUG(); | |
219 | } | |
220 | } | |
221 | ||
222 | /** | |
223 | * nand_write_buf - [DEFAULT] write buffer to chip | |
224 | * @mtd: MTD device structure | |
225 | * @buf: data buffer | |
226 | * @len: number of bytes to write | |
227 | * | |
228 | * Default write function for 8bit buswith | |
229 | */ | |
58dd8f2b | 230 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
231 | { |
232 | int i; | |
ace4dfee | 233 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 234 | |
e0c7d767 | 235 | for (i = 0; i < len; i++) |
ace4dfee | 236 | writeb(buf[i], chip->IO_ADDR_W); |
1da177e4 LT |
237 | } |
238 | ||
239 | /** | |
61b03bd7 | 240 | * nand_read_buf - [DEFAULT] read chip data into buffer |
1da177e4 LT |
241 | * @mtd: MTD device structure |
242 | * @buf: buffer to store date | |
243 | * @len: number of bytes to read | |
244 | * | |
245 | * Default read function for 8bit buswith | |
246 | */ | |
58dd8f2b | 247 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
248 | { |
249 | int i; | |
ace4dfee | 250 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 251 | |
e0c7d767 | 252 | for (i = 0; i < len; i++) |
ace4dfee | 253 | buf[i] = readb(chip->IO_ADDR_R); |
1da177e4 LT |
254 | } |
255 | ||
256 | /** | |
61b03bd7 | 257 | * nand_verify_buf - [DEFAULT] Verify chip data against buffer |
1da177e4 LT |
258 | * @mtd: MTD device structure |
259 | * @buf: buffer containing the data to compare | |
260 | * @len: number of bytes to compare | |
261 | * | |
262 | * Default verify function for 8bit buswith | |
263 | */ | |
58dd8f2b | 264 | static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
265 | { |
266 | int i; | |
ace4dfee | 267 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 268 | |
e0c7d767 | 269 | for (i = 0; i < len; i++) |
ace4dfee | 270 | if (buf[i] != readb(chip->IO_ADDR_R)) |
1da177e4 | 271 | return -EFAULT; |
1da177e4 LT |
272 | return 0; |
273 | } | |
274 | ||
275 | /** | |
276 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
277 | * @mtd: MTD device structure | |
278 | * @buf: data buffer | |
279 | * @len: number of bytes to write | |
280 | * | |
281 | * Default write function for 16bit buswith | |
282 | */ | |
58dd8f2b | 283 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
284 | { |
285 | int i; | |
ace4dfee | 286 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
287 | u16 *p = (u16 *) buf; |
288 | len >>= 1; | |
61b03bd7 | 289 | |
e0c7d767 | 290 | for (i = 0; i < len; i++) |
ace4dfee | 291 | writew(p[i], chip->IO_ADDR_W); |
61b03bd7 | 292 | |
1da177e4 LT |
293 | } |
294 | ||
295 | /** | |
61b03bd7 | 296 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
1da177e4 LT |
297 | * @mtd: MTD device structure |
298 | * @buf: buffer to store date | |
299 | * @len: number of bytes to read | |
300 | * | |
301 | * Default read function for 16bit buswith | |
302 | */ | |
58dd8f2b | 303 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
304 | { |
305 | int i; | |
ace4dfee | 306 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
307 | u16 *p = (u16 *) buf; |
308 | len >>= 1; | |
309 | ||
e0c7d767 | 310 | for (i = 0; i < len; i++) |
ace4dfee | 311 | p[i] = readw(chip->IO_ADDR_R); |
1da177e4 LT |
312 | } |
313 | ||
314 | /** | |
61b03bd7 | 315 | * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer |
1da177e4 LT |
316 | * @mtd: MTD device structure |
317 | * @buf: buffer containing the data to compare | |
318 | * @len: number of bytes to compare | |
319 | * | |
320 | * Default verify function for 16bit buswith | |
321 | */ | |
58dd8f2b | 322 | static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
323 | { |
324 | int i; | |
ace4dfee | 325 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
326 | u16 *p = (u16 *) buf; |
327 | len >>= 1; | |
328 | ||
e0c7d767 | 329 | for (i = 0; i < len; i++) |
ace4dfee | 330 | if (p[i] != readw(chip->IO_ADDR_R)) |
1da177e4 LT |
331 | return -EFAULT; |
332 | ||
333 | return 0; | |
334 | } | |
335 | ||
336 | /** | |
337 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
338 | * @mtd: MTD device structure | |
339 | * @ofs: offset from device start | |
340 | * @getchip: 0, if the chip is already selected | |
341 | * | |
61b03bd7 | 342 | * Check, if the block is bad. |
1da177e4 LT |
343 | */ |
344 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) | |
345 | { | |
346 | int page, chipnr, res = 0; | |
ace4dfee | 347 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
348 | u16 bad; |
349 | ||
1a12f46a TK |
350 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
351 | ||
1da177e4 | 352 | if (getchip) { |
ace4dfee | 353 | chipnr = (int)(ofs >> chip->chip_shift); |
1da177e4 | 354 | |
ace4dfee | 355 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 LT |
356 | |
357 | /* Select the NAND device */ | |
ace4dfee | 358 | chip->select_chip(mtd, chipnr); |
1a12f46a | 359 | } |
1da177e4 | 360 | |
ace4dfee TG |
361 | if (chip->options & NAND_BUSWIDTH_16) { |
362 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE, | |
1a12f46a | 363 | page); |
ace4dfee TG |
364 | bad = cpu_to_le16(chip->read_word(mtd)); |
365 | if (chip->badblockpos & 0x1) | |
49196f33 | 366 | bad >>= 8; |
1da177e4 LT |
367 | if ((bad & 0xFF) != 0xff) |
368 | res = 1; | |
369 | } else { | |
1a12f46a | 370 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page); |
ace4dfee | 371 | if (chip->read_byte(mtd) != 0xff) |
1da177e4 LT |
372 | res = 1; |
373 | } | |
61b03bd7 | 374 | |
ace4dfee | 375 | if (getchip) |
1da177e4 | 376 | nand_release_device(mtd); |
61b03bd7 | 377 | |
1da177e4 LT |
378 | return res; |
379 | } | |
380 | ||
381 | /** | |
382 | * nand_default_block_markbad - [DEFAULT] mark a block bad | |
383 | * @mtd: MTD device structure | |
384 | * @ofs: offset from device start | |
385 | * | |
386 | * This is the default implementation, which can be overridden by | |
387 | * a hardware specific driver. | |
388 | */ | |
389 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
390 | { | |
ace4dfee | 391 | struct nand_chip *chip = mtd->priv; |
58dd8f2b | 392 | uint8_t buf[2] = { 0, 0 }; |
f1a28c02 | 393 | int block, ret; |
61b03bd7 | 394 | |
1da177e4 | 395 | /* Get block number */ |
4226b510 | 396 | block = (int)(ofs >> chip->bbt_erase_shift); |
ace4dfee TG |
397 | if (chip->bbt) |
398 | chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); | |
1da177e4 LT |
399 | |
400 | /* Do we have a flash based bad block table ? */ | |
ace4dfee | 401 | if (chip->options & NAND_USE_FLASH_BBT) |
f1a28c02 TG |
402 | ret = nand_update_bbt(mtd, ofs); |
403 | else { | |
404 | /* We write two bytes, so we dont have to mess with 16 bit | |
405 | * access | |
406 | */ | |
c0b8ba7b | 407 | nand_get_device(chip, mtd, FL_WRITING); |
f1a28c02 | 408 | ofs += mtd->oobsize; |
ff0dab64 | 409 | chip->ops.len = chip->ops.ooblen = 2; |
f1a28c02 TG |
410 | chip->ops.datbuf = NULL; |
411 | chip->ops.oobbuf = buf; | |
412 | chip->ops.ooboffs = chip->badblockpos & ~0x01; | |
413 | ||
414 | ret = nand_do_write_oob(mtd, ofs, &chip->ops); | |
c0b8ba7b | 415 | nand_release_device(mtd); |
f1a28c02 TG |
416 | } |
417 | if (!ret) | |
418 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 419 | |
f1a28c02 | 420 | return ret; |
1da177e4 LT |
421 | } |
422 | ||
61b03bd7 | 423 | /** |
1da177e4 LT |
424 | * nand_check_wp - [GENERIC] check if the chip is write protected |
425 | * @mtd: MTD device structure | |
61b03bd7 | 426 | * Check, if the device is write protected |
1da177e4 | 427 | * |
61b03bd7 | 428 | * The function expects, that the device is already selected |
1da177e4 | 429 | */ |
e0c7d767 | 430 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 431 | { |
ace4dfee | 432 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 433 | /* Check the WP bit */ |
ace4dfee TG |
434 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
435 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
436 | } |
437 | ||
438 | /** | |
439 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
440 | * @mtd: MTD device structure | |
441 | * @ofs: offset from device start | |
442 | * @getchip: 0, if the chip is already selected | |
443 | * @allowbbt: 1, if its allowed to access the bbt area | |
444 | * | |
445 | * Check, if the block is bad. Either by reading the bad block table or | |
446 | * calling of the scan function. | |
447 | */ | |
2c0a2bed TG |
448 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, |
449 | int allowbbt) | |
1da177e4 | 450 | { |
ace4dfee | 451 | struct nand_chip *chip = mtd->priv; |
61b03bd7 | 452 | |
ace4dfee TG |
453 | if (!chip->bbt) |
454 | return chip->block_bad(mtd, ofs, getchip); | |
61b03bd7 | 455 | |
1da177e4 | 456 | /* Return info from the table */ |
e0c7d767 | 457 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
458 | } |
459 | ||
2af7c653 SK |
460 | /** |
461 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
462 | * @mtd: MTD device structure | |
463 | * @timeo: Timeout | |
464 | * | |
465 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
466 | * context. | |
467 | */ | |
468 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
469 | { | |
470 | struct nand_chip *chip = mtd->priv; | |
471 | int i; | |
472 | ||
473 | /* Wait for the device to get ready */ | |
474 | for (i = 0; i < timeo; i++) { | |
475 | if (chip->dev_ready(mtd)) | |
476 | break; | |
477 | touch_softlockup_watchdog(); | |
478 | mdelay(1); | |
479 | } | |
480 | } | |
481 | ||
61b03bd7 | 482 | /* |
3b88775c TG |
483 | * Wait for the ready pin, after a command |
484 | * The timeout is catched later. | |
485 | */ | |
4b648b02 | 486 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 487 | { |
ace4dfee | 488 | struct nand_chip *chip = mtd->priv; |
e0c7d767 | 489 | unsigned long timeo = jiffies + 2; |
3b88775c | 490 | |
2af7c653 SK |
491 | /* 400ms timeout */ |
492 | if (in_interrupt() || oops_in_progress) | |
493 | return panic_nand_wait_ready(mtd, 400); | |
494 | ||
8fe833c1 | 495 | led_trigger_event(nand_led_trigger, LED_FULL); |
3b88775c TG |
496 | /* wait until command is processed or timeout occures */ |
497 | do { | |
ace4dfee | 498 | if (chip->dev_ready(mtd)) |
8fe833c1 | 499 | break; |
8446f1d3 | 500 | touch_softlockup_watchdog(); |
61b03bd7 | 501 | } while (time_before(jiffies, timeo)); |
8fe833c1 | 502 | led_trigger_event(nand_led_trigger, LED_OFF); |
3b88775c | 503 | } |
4b648b02 | 504 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 505 | |
1da177e4 LT |
506 | /** |
507 | * nand_command - [DEFAULT] Send command to NAND device | |
508 | * @mtd: MTD device structure | |
509 | * @command: the command to be sent | |
510 | * @column: the column address for this command, -1 if none | |
511 | * @page_addr: the page address for this command, -1 if none | |
512 | * | |
513 | * Send command to NAND device. This function is used for small page | |
514 | * devices (256/512 Bytes per page) | |
515 | */ | |
7abd3ef9 TG |
516 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
517 | int column, int page_addr) | |
1da177e4 | 518 | { |
ace4dfee | 519 | register struct nand_chip *chip = mtd->priv; |
7abd3ef9 | 520 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 521 | |
1da177e4 LT |
522 | /* |
523 | * Write out the command to the device. | |
524 | */ | |
525 | if (command == NAND_CMD_SEQIN) { | |
526 | int readcmd; | |
527 | ||
28318776 | 528 | if (column >= mtd->writesize) { |
1da177e4 | 529 | /* OOB area */ |
28318776 | 530 | column -= mtd->writesize; |
1da177e4 LT |
531 | readcmd = NAND_CMD_READOOB; |
532 | } else if (column < 256) { | |
533 | /* First 256 bytes --> READ0 */ | |
534 | readcmd = NAND_CMD_READ0; | |
535 | } else { | |
536 | column -= 256; | |
537 | readcmd = NAND_CMD_READ1; | |
538 | } | |
ace4dfee | 539 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 540 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 541 | } |
ace4dfee | 542 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 543 | |
7abd3ef9 TG |
544 | /* |
545 | * Address cycle, when necessary | |
546 | */ | |
547 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; | |
548 | /* Serially input address */ | |
549 | if (column != -1) { | |
550 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 551 | if (chip->options & NAND_BUSWIDTH_16) |
7abd3ef9 | 552 | column >>= 1; |
ace4dfee | 553 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
554 | ctrl &= ~NAND_CTRL_CHANGE; |
555 | } | |
556 | if (page_addr != -1) { | |
ace4dfee | 557 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 558 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 559 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 560 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
561 | if (chip->chipsize > (32 << 20)) |
562 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 563 | } |
ace4dfee | 564 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
565 | |
566 | /* | |
567 | * program and erase have their own busy handlers | |
1da177e4 | 568 | * status and sequential in needs no delay |
e0c7d767 | 569 | */ |
1da177e4 | 570 | switch (command) { |
61b03bd7 | 571 | |
1da177e4 LT |
572 | case NAND_CMD_PAGEPROG: |
573 | case NAND_CMD_ERASE1: | |
574 | case NAND_CMD_ERASE2: | |
575 | case NAND_CMD_SEQIN: | |
576 | case NAND_CMD_STATUS: | |
577 | return; | |
578 | ||
579 | case NAND_CMD_RESET: | |
ace4dfee | 580 | if (chip->dev_ready) |
1da177e4 | 581 | break; |
ace4dfee TG |
582 | udelay(chip->chip_delay); |
583 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 584 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
585 | chip->cmd_ctrl(mtd, |
586 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
ace4dfee | 587 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; |
1da177e4 LT |
588 | return; |
589 | ||
e0c7d767 | 590 | /* This applies to read commands */ |
1da177e4 | 591 | default: |
61b03bd7 | 592 | /* |
1da177e4 LT |
593 | * If we don't have access to the busy pin, we apply the given |
594 | * command delay | |
e0c7d767 | 595 | */ |
ace4dfee TG |
596 | if (!chip->dev_ready) { |
597 | udelay(chip->chip_delay); | |
1da177e4 | 598 | return; |
61b03bd7 | 599 | } |
1da177e4 | 600 | } |
1da177e4 LT |
601 | /* Apply this short delay always to ensure that we do wait tWB in |
602 | * any case on any machine. */ | |
e0c7d767 | 603 | ndelay(100); |
3b88775c TG |
604 | |
605 | nand_wait_ready(mtd); | |
1da177e4 LT |
606 | } |
607 | ||
608 | /** | |
609 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
610 | * @mtd: MTD device structure | |
611 | * @command: the command to be sent | |
612 | * @column: the column address for this command, -1 if none | |
613 | * @page_addr: the page address for this command, -1 if none | |
614 | * | |
7abd3ef9 TG |
615 | * Send command to NAND device. This is the version for the new large page |
616 | * devices We dont have the separate regions as we have in the small page | |
617 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 618 | */ |
7abd3ef9 TG |
619 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
620 | int column, int page_addr) | |
1da177e4 | 621 | { |
ace4dfee | 622 | register struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
623 | |
624 | /* Emulate NAND_CMD_READOOB */ | |
625 | if (command == NAND_CMD_READOOB) { | |
28318776 | 626 | column += mtd->writesize; |
1da177e4 LT |
627 | command = NAND_CMD_READ0; |
628 | } | |
61b03bd7 | 629 | |
7abd3ef9 | 630 | /* Command latch cycle */ |
ace4dfee | 631 | chip->cmd_ctrl(mtd, command & 0xff, |
7abd3ef9 | 632 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
633 | |
634 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 635 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
636 | |
637 | /* Serially input address */ | |
638 | if (column != -1) { | |
639 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 640 | if (chip->options & NAND_BUSWIDTH_16) |
1da177e4 | 641 | column >>= 1; |
ace4dfee | 642 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 643 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 644 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 645 | } |
1da177e4 | 646 | if (page_addr != -1) { |
ace4dfee TG |
647 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
648 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 649 | NAND_NCE | NAND_ALE); |
1da177e4 | 650 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
651 | if (chip->chipsize > (128 << 20)) |
652 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 653 | NAND_NCE | NAND_ALE); |
1da177e4 | 654 | } |
1da177e4 | 655 | } |
ace4dfee | 656 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
657 | |
658 | /* | |
659 | * program and erase have their own busy handlers | |
30f464b7 DM |
660 | * status, sequential in, and deplete1 need no delay |
661 | */ | |
1da177e4 | 662 | switch (command) { |
61b03bd7 | 663 | |
1da177e4 LT |
664 | case NAND_CMD_CACHEDPROG: |
665 | case NAND_CMD_PAGEPROG: | |
666 | case NAND_CMD_ERASE1: | |
667 | case NAND_CMD_ERASE2: | |
668 | case NAND_CMD_SEQIN: | |
7bc3312b | 669 | case NAND_CMD_RNDIN: |
1da177e4 | 670 | case NAND_CMD_STATUS: |
30f464b7 | 671 | case NAND_CMD_DEPLETE1: |
1da177e4 LT |
672 | return; |
673 | ||
e0c7d767 DW |
674 | /* |
675 | * read error status commands require only a short delay | |
676 | */ | |
30f464b7 DM |
677 | case NAND_CMD_STATUS_ERROR: |
678 | case NAND_CMD_STATUS_ERROR0: | |
679 | case NAND_CMD_STATUS_ERROR1: | |
680 | case NAND_CMD_STATUS_ERROR2: | |
681 | case NAND_CMD_STATUS_ERROR3: | |
ace4dfee | 682 | udelay(chip->chip_delay); |
30f464b7 | 683 | return; |
1da177e4 LT |
684 | |
685 | case NAND_CMD_RESET: | |
ace4dfee | 686 | if (chip->dev_ready) |
1da177e4 | 687 | break; |
ace4dfee | 688 | udelay(chip->chip_delay); |
12efdde3 TG |
689 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
690 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
691 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
692 | NAND_NCE | NAND_CTRL_CHANGE); | |
ace4dfee | 693 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; |
1da177e4 LT |
694 | return; |
695 | ||
7bc3312b TG |
696 | case NAND_CMD_RNDOUT: |
697 | /* No ready / busy check necessary */ | |
698 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
699 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
700 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
701 | NAND_NCE | NAND_CTRL_CHANGE); | |
702 | return; | |
703 | ||
1da177e4 | 704 | case NAND_CMD_READ0: |
12efdde3 TG |
705 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
706 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
707 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
708 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 709 | |
e0c7d767 | 710 | /* This applies to read commands */ |
1da177e4 | 711 | default: |
61b03bd7 | 712 | /* |
1da177e4 LT |
713 | * If we don't have access to the busy pin, we apply the given |
714 | * command delay | |
e0c7d767 | 715 | */ |
ace4dfee TG |
716 | if (!chip->dev_ready) { |
717 | udelay(chip->chip_delay); | |
1da177e4 | 718 | return; |
61b03bd7 | 719 | } |
1da177e4 | 720 | } |
3b88775c | 721 | |
1da177e4 LT |
722 | /* Apply this short delay always to ensure that we do wait tWB in |
723 | * any case on any machine. */ | |
e0c7d767 | 724 | ndelay(100); |
3b88775c TG |
725 | |
726 | nand_wait_ready(mtd); | |
1da177e4 LT |
727 | } |
728 | ||
2af7c653 SK |
729 | /** |
730 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
731 | * @chip: the nand chip descriptor | |
732 | * @mtd: MTD device structure | |
733 | * @new_state: the state which is requested | |
734 | * | |
735 | * Used when in panic, no locks are taken. | |
736 | */ | |
737 | static void panic_nand_get_device(struct nand_chip *chip, | |
738 | struct mtd_info *mtd, int new_state) | |
739 | { | |
740 | /* Hardware controller shared among independend devices */ | |
741 | chip->controller->active = chip; | |
742 | chip->state = new_state; | |
743 | } | |
744 | ||
1da177e4 LT |
745 | /** |
746 | * nand_get_device - [GENERIC] Get chip for selected access | |
844d3b42 | 747 | * @chip: the nand chip descriptor |
1da177e4 | 748 | * @mtd: MTD device structure |
61b03bd7 | 749 | * @new_state: the state which is requested |
1da177e4 LT |
750 | * |
751 | * Get the device and lock it for exclusive access | |
752 | */ | |
2c0a2bed | 753 | static int |
ace4dfee | 754 | nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state) |
1da177e4 | 755 | { |
ace4dfee TG |
756 | spinlock_t *lock = &chip->controller->lock; |
757 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 758 | DECLARE_WAITQUEUE(wait, current); |
e0c7d767 | 759 | retry: |
0dfc6246 TG |
760 | spin_lock(lock); |
761 | ||
b8b3ee9a | 762 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
763 | if (!chip->controller->active) |
764 | chip->controller->active = chip; | |
a36ed299 | 765 | |
ace4dfee TG |
766 | if (chip->controller->active == chip && chip->state == FL_READY) { |
767 | chip->state = new_state; | |
0dfc6246 | 768 | spin_unlock(lock); |
962034f4 VW |
769 | return 0; |
770 | } | |
771 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
772 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
773 | chip->state = FL_PM_SUSPENDED; | |
774 | spin_unlock(lock); | |
775 | return 0; | |
6b0d9a84 | 776 | } |
0dfc6246 TG |
777 | } |
778 | set_current_state(TASK_UNINTERRUPTIBLE); | |
779 | add_wait_queue(wq, &wait); | |
780 | spin_unlock(lock); | |
781 | schedule(); | |
782 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
783 | goto retry; |
784 | } | |
785 | ||
2af7c653 SK |
786 | /** |
787 | * panic_nand_wait - [GENERIC] wait until the command is done | |
788 | * @mtd: MTD device structure | |
789 | * @chip: NAND chip structure | |
790 | * @timeo: Timeout | |
791 | * | |
792 | * Wait for command done. This is a helper function for nand_wait used when | |
793 | * we are in interrupt context. May happen when in panic and trying to write | |
794 | * an oops trough mtdoops. | |
795 | */ | |
796 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
797 | unsigned long timeo) | |
798 | { | |
799 | int i; | |
800 | for (i = 0; i < timeo; i++) { | |
801 | if (chip->dev_ready) { | |
802 | if (chip->dev_ready(mtd)) | |
803 | break; | |
804 | } else { | |
805 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
806 | break; | |
807 | } | |
808 | mdelay(1); | |
809 | } | |
810 | } | |
811 | ||
1da177e4 LT |
812 | /** |
813 | * nand_wait - [DEFAULT] wait until the command is done | |
814 | * @mtd: MTD device structure | |
844d3b42 | 815 | * @chip: NAND chip structure |
1da177e4 LT |
816 | * |
817 | * Wait for command done. This applies to erase and program only | |
61b03bd7 | 818 | * Erase can take up to 400ms and program up to 20ms according to |
1da177e4 | 819 | * general NAND and SmartMedia specs |
844d3b42 | 820 | */ |
7bc3312b | 821 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
822 | { |
823 | ||
e0c7d767 | 824 | unsigned long timeo = jiffies; |
7bc3312b | 825 | int status, state = chip->state; |
61b03bd7 | 826 | |
1da177e4 | 827 | if (state == FL_ERASING) |
e0c7d767 | 828 | timeo += (HZ * 400) / 1000; |
1da177e4 | 829 | else |
e0c7d767 | 830 | timeo += (HZ * 20) / 1000; |
1da177e4 | 831 | |
8fe833c1 RP |
832 | led_trigger_event(nand_led_trigger, LED_FULL); |
833 | ||
1da177e4 LT |
834 | /* Apply this short delay always to ensure that we do wait tWB in |
835 | * any case on any machine. */ | |
e0c7d767 | 836 | ndelay(100); |
1da177e4 | 837 | |
ace4dfee TG |
838 | if ((state == FL_ERASING) && (chip->options & NAND_IS_AND)) |
839 | chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); | |
61b03bd7 | 840 | else |
ace4dfee | 841 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 842 | |
2af7c653 SK |
843 | if (in_interrupt() || oops_in_progress) |
844 | panic_nand_wait(mtd, chip, timeo); | |
845 | else { | |
846 | while (time_before(jiffies, timeo)) { | |
847 | if (chip->dev_ready) { | |
848 | if (chip->dev_ready(mtd)) | |
849 | break; | |
850 | } else { | |
851 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
852 | break; | |
853 | } | |
854 | cond_resched(); | |
1da177e4 | 855 | } |
1da177e4 | 856 | } |
8fe833c1 RP |
857 | led_trigger_event(nand_led_trigger, LED_OFF); |
858 | ||
ace4dfee | 859 | status = (int)chip->read_byte(mtd); |
1da177e4 LT |
860 | return status; |
861 | } | |
862 | ||
7d70f334 VS |
863 | /** |
864 | * __nand_unlock - [REPLACABLE] unlocks specified locked blockes | |
865 | * | |
866 | * @param mtd - mtd info | |
867 | * @param ofs - offset to start unlock from | |
868 | * @param len - length to unlock | |
869 | * @invert - when = 0, unlock the range of blocks within the lower and | |
870 | * upper boundary address | |
871 | * whne = 1, unlock the range of blocks outside the boundaries | |
872 | * of the lower and upper boundary address | |
873 | * | |
874 | * @return - unlock status | |
875 | */ | |
876 | static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, | |
877 | uint64_t len, int invert) | |
878 | { | |
879 | int ret = 0; | |
880 | int status, page; | |
881 | struct nand_chip *chip = mtd->priv; | |
882 | ||
883 | /* Submit address of first page to unlock */ | |
884 | page = ofs >> chip->page_shift; | |
885 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); | |
886 | ||
887 | /* Submit address of last page to unlock */ | |
888 | page = (ofs + len) >> chip->page_shift; | |
889 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, | |
890 | (page | invert) & chip->pagemask); | |
891 | ||
892 | /* Call wait ready function */ | |
893 | status = chip->waitfunc(mtd, chip); | |
894 | udelay(1000); | |
895 | /* See if device thinks it succeeded */ | |
896 | if (status & 0x01) { | |
897 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n", | |
898 | __func__, status); | |
899 | ret = -EIO; | |
900 | } | |
901 | ||
902 | return ret; | |
903 | } | |
904 | ||
905 | /** | |
906 | * nand_unlock - [REPLACABLE] unlocks specified locked blockes | |
907 | * | |
908 | * @param mtd - mtd info | |
909 | * @param ofs - offset to start unlock from | |
910 | * @param len - length to unlock | |
911 | * | |
912 | * @return - unlock status | |
913 | */ | |
914 | int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
915 | { | |
916 | int ret = 0; | |
917 | int chipnr; | |
918 | struct nand_chip *chip = mtd->priv; | |
919 | ||
920 | DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n", | |
921 | __func__, (unsigned long long)ofs, len); | |
922 | ||
923 | if (check_offs_len(mtd, ofs, len)) | |
924 | ret = -EINVAL; | |
925 | ||
926 | /* Align to last block address if size addresses end of the device */ | |
927 | if (ofs + len == mtd->size) | |
928 | len -= mtd->erasesize; | |
929 | ||
930 | nand_get_device(chip, mtd, FL_UNLOCKING); | |
931 | ||
932 | /* Shift to get chip number */ | |
933 | chipnr = ofs >> chip->chip_shift; | |
934 | ||
935 | chip->select_chip(mtd, chipnr); | |
936 | ||
937 | /* Check, if it is write protected */ | |
938 | if (nand_check_wp(mtd)) { | |
939 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n", | |
940 | __func__); | |
941 | ret = -EIO; | |
942 | goto out; | |
943 | } | |
944 | ||
945 | ret = __nand_unlock(mtd, ofs, len, 0); | |
946 | ||
947 | out: | |
948 | /* de-select the NAND device */ | |
949 | chip->select_chip(mtd, -1); | |
950 | ||
951 | nand_release_device(mtd); | |
952 | ||
953 | return ret; | |
954 | } | |
955 | ||
956 | /** | |
957 | * nand_lock - [REPLACABLE] locks all blockes present in the device | |
958 | * | |
959 | * @param mtd - mtd info | |
960 | * @param ofs - offset to start unlock from | |
961 | * @param len - length to unlock | |
962 | * | |
963 | * @return - lock status | |
964 | * | |
965 | * This feature is not support in many NAND parts. 'Micron' NAND parts | |
966 | * do have this feature, but it allows only to lock all blocks not for | |
967 | * specified range for block. | |
968 | * | |
969 | * Implementing 'lock' feature by making use of 'unlock', for now. | |
970 | */ | |
971 | int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
972 | { | |
973 | int ret = 0; | |
974 | int chipnr, status, page; | |
975 | struct nand_chip *chip = mtd->priv; | |
976 | ||
977 | DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n", | |
978 | __func__, (unsigned long long)ofs, len); | |
979 | ||
980 | if (check_offs_len(mtd, ofs, len)) | |
981 | ret = -EINVAL; | |
982 | ||
983 | nand_get_device(chip, mtd, FL_LOCKING); | |
984 | ||
985 | /* Shift to get chip number */ | |
986 | chipnr = ofs >> chip->chip_shift; | |
987 | ||
988 | chip->select_chip(mtd, chipnr); | |
989 | ||
990 | /* Check, if it is write protected */ | |
991 | if (nand_check_wp(mtd)) { | |
992 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n", | |
993 | __func__); | |
994 | status = MTD_ERASE_FAILED; | |
995 | ret = -EIO; | |
996 | goto out; | |
997 | } | |
998 | ||
999 | /* Submit address of first page to lock */ | |
1000 | page = ofs >> chip->page_shift; | |
1001 | chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); | |
1002 | ||
1003 | /* Call wait ready function */ | |
1004 | status = chip->waitfunc(mtd, chip); | |
1005 | udelay(1000); | |
1006 | /* See if device thinks it succeeded */ | |
1007 | if (status & 0x01) { | |
1008 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n", | |
1009 | __func__, status); | |
1010 | ret = -EIO; | |
1011 | goto out; | |
1012 | } | |
1013 | ||
1014 | ret = __nand_unlock(mtd, ofs, len, 0x1); | |
1015 | ||
1016 | out: | |
1017 | /* de-select the NAND device */ | |
1018 | chip->select_chip(mtd, -1); | |
1019 | ||
1020 | nand_release_device(mtd); | |
1021 | ||
1022 | return ret; | |
1023 | } | |
1024 | ||
8593fbc6 TG |
1025 | /** |
1026 | * nand_read_page_raw - [Intern] read raw page data without ecc | |
1027 | * @mtd: mtd info structure | |
1028 | * @chip: nand chip info structure | |
1029 | * @buf: buffer to store read data | |
58475fb9 | 1030 | * @page: page number to read |
52ff49df DB |
1031 | * |
1032 | * Not for syndrome calculating ecc controllers, which use a special oob layout | |
8593fbc6 TG |
1033 | */ |
1034 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
46a8cf2d | 1035 | uint8_t *buf, int page) |
8593fbc6 TG |
1036 | { |
1037 | chip->read_buf(mtd, buf, mtd->writesize); | |
1038 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1039 | return 0; | |
1040 | } | |
1041 | ||
52ff49df DB |
1042 | /** |
1043 | * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc | |
1044 | * @mtd: mtd info structure | |
1045 | * @chip: nand chip info structure | |
1046 | * @buf: buffer to store read data | |
58475fb9 | 1047 | * @page: page number to read |
52ff49df DB |
1048 | * |
1049 | * We need a special oob layout and handling even when OOB isn't used. | |
1050 | */ | |
1051 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
46a8cf2d | 1052 | uint8_t *buf, int page) |
52ff49df DB |
1053 | { |
1054 | int eccsize = chip->ecc.size; | |
1055 | int eccbytes = chip->ecc.bytes; | |
1056 | uint8_t *oob = chip->oob_poi; | |
1057 | int steps, size; | |
1058 | ||
1059 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1060 | chip->read_buf(mtd, buf, eccsize); | |
1061 | buf += eccsize; | |
1062 | ||
1063 | if (chip->ecc.prepad) { | |
1064 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1065 | oob += chip->ecc.prepad; | |
1066 | } | |
1067 | ||
1068 | chip->read_buf(mtd, oob, eccbytes); | |
1069 | oob += eccbytes; | |
1070 | ||
1071 | if (chip->ecc.postpad) { | |
1072 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1073 | oob += chip->ecc.postpad; | |
1074 | } | |
1075 | } | |
1076 | ||
1077 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1078 | if (size) | |
1079 | chip->read_buf(mtd, oob, size); | |
1080 | ||
1081 | return 0; | |
1082 | } | |
1083 | ||
1da177e4 | 1084 | /** |
d29ebdbe | 1085 | * nand_read_page_swecc - [REPLACABLE] software ecc based page read function |
f5bbdacc TG |
1086 | * @mtd: mtd info structure |
1087 | * @chip: nand chip info structure | |
1088 | * @buf: buffer to store read data | |
58475fb9 | 1089 | * @page: page number to read |
068e3c0a | 1090 | */ |
f5bbdacc | 1091 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
46a8cf2d | 1092 | uint8_t *buf, int page) |
1da177e4 | 1093 | { |
f5bbdacc TG |
1094 | int i, eccsize = chip->ecc.size; |
1095 | int eccbytes = chip->ecc.bytes; | |
1096 | int eccsteps = chip->ecc.steps; | |
1097 | uint8_t *p = buf; | |
4bf63fcb DW |
1098 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1099 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1100 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
f5bbdacc | 1101 | |
46a8cf2d | 1102 | chip->ecc.read_page_raw(mtd, chip, buf, page); |
f5bbdacc TG |
1103 | |
1104 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1105 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1106 | ||
1107 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 1108 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
1109 | |
1110 | eccsteps = chip->ecc.steps; | |
1111 | p = buf; | |
1112 | ||
1113 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1114 | int stat; | |
1115 | ||
1116 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
c32b8dcc | 1117 | if (stat < 0) |
f5bbdacc TG |
1118 | mtd->ecc_stats.failed++; |
1119 | else | |
1120 | mtd->ecc_stats.corrected += stat; | |
1121 | } | |
1122 | return 0; | |
22c60f5f | 1123 | } |
1da177e4 | 1124 | |
3d459559 AK |
1125 | /** |
1126 | * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function | |
1127 | * @mtd: mtd info structure | |
1128 | * @chip: nand chip info structure | |
17c1d2be AK |
1129 | * @data_offs: offset of requested data within the page |
1130 | * @readlen: data length | |
1131 | * @bufpoi: buffer to store read data | |
3d459559 AK |
1132 | */ |
1133 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi) | |
1134 | { | |
1135 | int start_step, end_step, num_steps; | |
1136 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1137 | uint8_t *p; | |
1138 | int data_col_addr, i, gaps = 0; | |
1139 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
1140 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
1141 | ||
1142 | /* Column address wihin the page aligned to ECC size (256bytes). */ | |
1143 | start_step = data_offs / chip->ecc.size; | |
1144 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
1145 | num_steps = end_step - start_step + 1; | |
1146 | ||
1147 | /* Data size aligned to ECC ecc.size*/ | |
1148 | datafrag_len = num_steps * chip->ecc.size; | |
1149 | eccfrag_len = num_steps * chip->ecc.bytes; | |
1150 | ||
1151 | data_col_addr = start_step * chip->ecc.size; | |
1152 | /* If we read not a page aligned data */ | |
1153 | if (data_col_addr != 0) | |
1154 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); | |
1155 | ||
1156 | p = bufpoi + data_col_addr; | |
1157 | chip->read_buf(mtd, p, datafrag_len); | |
1158 | ||
1159 | /* Calculate ECC */ | |
1160 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) | |
1161 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); | |
1162 | ||
1163 | /* The performance is faster if to position offsets | |
1164 | according to ecc.pos. Let make sure here that | |
1165 | there are no gaps in ecc positions */ | |
1166 | for (i = 0; i < eccfrag_len - 1; i++) { | |
1167 | if (eccpos[i + start_step * chip->ecc.bytes] + 1 != | |
1168 | eccpos[i + start_step * chip->ecc.bytes + 1]) { | |
1169 | gaps = 1; | |
1170 | break; | |
1171 | } | |
1172 | } | |
1173 | if (gaps) { | |
1174 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1175 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1176 | } else { | |
1177 | /* send the command to read the particular ecc bytes */ | |
1178 | /* take care about buswidth alignment in read_buf */ | |
1179 | aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1); | |
1180 | aligned_len = eccfrag_len; | |
1181 | if (eccpos[start_step * chip->ecc.bytes] & (busw - 1)) | |
1182 | aligned_len++; | |
1183 | if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1)) | |
1184 | aligned_len++; | |
1185 | ||
1186 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1); | |
1187 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); | |
1188 | } | |
1189 | ||
1190 | for (i = 0; i < eccfrag_len; i++) | |
1191 | chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]]; | |
1192 | ||
1193 | p = bufpoi + data_col_addr; | |
1194 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
1195 | int stat; | |
1196 | ||
1197 | stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); | |
1198 | if (stat == -1) | |
1199 | mtd->ecc_stats.failed++; | |
1200 | else | |
1201 | mtd->ecc_stats.corrected += stat; | |
1202 | } | |
1203 | return 0; | |
1204 | } | |
1205 | ||
068e3c0a | 1206 | /** |
d29ebdbe | 1207 | * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function |
f5bbdacc TG |
1208 | * @mtd: mtd info structure |
1209 | * @chip: nand chip info structure | |
1210 | * @buf: buffer to store read data | |
58475fb9 | 1211 | * @page: page number to read |
068e3c0a | 1212 | * |
f5bbdacc | 1213 | * Not for syndrome calculating ecc controllers which need a special oob layout |
068e3c0a | 1214 | */ |
f5bbdacc | 1215 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
46a8cf2d | 1216 | uint8_t *buf, int page) |
1da177e4 | 1217 | { |
f5bbdacc TG |
1218 | int i, eccsize = chip->ecc.size; |
1219 | int eccbytes = chip->ecc.bytes; | |
1220 | int eccsteps = chip->ecc.steps; | |
1221 | uint8_t *p = buf; | |
4bf63fcb DW |
1222 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1223 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1224 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
f5bbdacc TG |
1225 | |
1226 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1227 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1228 | chip->read_buf(mtd, p, eccsize); | |
1229 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 1230 | } |
f75e5097 | 1231 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 1232 | |
f5bbdacc | 1233 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 1234 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 1235 | |
f5bbdacc TG |
1236 | eccsteps = chip->ecc.steps; |
1237 | p = buf; | |
61b03bd7 | 1238 | |
f5bbdacc TG |
1239 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1240 | int stat; | |
1da177e4 | 1241 | |
f5bbdacc | 1242 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
c32b8dcc | 1243 | if (stat < 0) |
f5bbdacc TG |
1244 | mtd->ecc_stats.failed++; |
1245 | else | |
1246 | mtd->ecc_stats.corrected += stat; | |
1247 | } | |
1248 | return 0; | |
1249 | } | |
1da177e4 | 1250 | |
6e0cb135 SN |
1251 | /** |
1252 | * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first | |
1253 | * @mtd: mtd info structure | |
1254 | * @chip: nand chip info structure | |
1255 | * @buf: buffer to store read data | |
58475fb9 | 1256 | * @page: page number to read |
6e0cb135 SN |
1257 | * |
1258 | * Hardware ECC for large page chips, require OOB to be read first. | |
1259 | * For this ECC mode, the write_page method is re-used from ECC_HW. | |
1260 | * These methods read/write ECC from the OOB area, unlike the | |
1261 | * ECC_HW_SYNDROME support with multiple ECC steps, follows the | |
1262 | * "infix ECC" scheme and reads/writes ECC from the data area, by | |
1263 | * overwriting the NAND manufacturer bad block markings. | |
1264 | */ | |
1265 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1266 | struct nand_chip *chip, uint8_t *buf, int page) | |
1267 | { | |
1268 | int i, eccsize = chip->ecc.size; | |
1269 | int eccbytes = chip->ecc.bytes; | |
1270 | int eccsteps = chip->ecc.steps; | |
1271 | uint8_t *p = buf; | |
1272 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1273 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1274 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
1275 | ||
1276 | /* Read the OOB area first */ | |
1277 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1278 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1279 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1280 | ||
1281 | for (i = 0; i < chip->ecc.total; i++) | |
1282 | ecc_code[i] = chip->oob_poi[eccpos[i]]; | |
1283 | ||
1284 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1285 | int stat; | |
1286 | ||
1287 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1288 | chip->read_buf(mtd, p, eccsize); | |
1289 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1290 | ||
1291 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
1292 | if (stat < 0) | |
1293 | mtd->ecc_stats.failed++; | |
1294 | else | |
1295 | mtd->ecc_stats.corrected += stat; | |
1296 | } | |
1297 | return 0; | |
1298 | } | |
1299 | ||
f5bbdacc | 1300 | /** |
d29ebdbe | 1301 | * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read |
f5bbdacc TG |
1302 | * @mtd: mtd info structure |
1303 | * @chip: nand chip info structure | |
1304 | * @buf: buffer to store read data | |
58475fb9 | 1305 | * @page: page number to read |
f5bbdacc TG |
1306 | * |
1307 | * The hw generator calculates the error syndrome automatically. Therefor | |
f75e5097 | 1308 | * we need a special oob layout and handling. |
f5bbdacc TG |
1309 | */ |
1310 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
46a8cf2d | 1311 | uint8_t *buf, int page) |
f5bbdacc TG |
1312 | { |
1313 | int i, eccsize = chip->ecc.size; | |
1314 | int eccbytes = chip->ecc.bytes; | |
1315 | int eccsteps = chip->ecc.steps; | |
1316 | uint8_t *p = buf; | |
f75e5097 | 1317 | uint8_t *oob = chip->oob_poi; |
1da177e4 | 1318 | |
f5bbdacc TG |
1319 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1320 | int stat; | |
61b03bd7 | 1321 | |
f5bbdacc TG |
1322 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
1323 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 1324 | |
f5bbdacc TG |
1325 | if (chip->ecc.prepad) { |
1326 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1327 | oob += chip->ecc.prepad; | |
1328 | } | |
1da177e4 | 1329 | |
f5bbdacc TG |
1330 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1331 | chip->read_buf(mtd, oob, eccbytes); | |
1332 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 1333 | |
c32b8dcc | 1334 | if (stat < 0) |
f5bbdacc | 1335 | mtd->ecc_stats.failed++; |
61b03bd7 | 1336 | else |
f5bbdacc | 1337 | mtd->ecc_stats.corrected += stat; |
61b03bd7 | 1338 | |
f5bbdacc | 1339 | oob += eccbytes; |
1da177e4 | 1340 | |
f5bbdacc TG |
1341 | if (chip->ecc.postpad) { |
1342 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1343 | oob += chip->ecc.postpad; | |
61b03bd7 | 1344 | } |
f5bbdacc | 1345 | } |
1da177e4 | 1346 | |
f5bbdacc | 1347 | /* Calculate remaining oob bytes */ |
7e4178f9 | 1348 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
1349 | if (i) |
1350 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 1351 | |
f5bbdacc TG |
1352 | return 0; |
1353 | } | |
1da177e4 | 1354 | |
f5bbdacc | 1355 | /** |
8593fbc6 TG |
1356 | * nand_transfer_oob - [Internal] Transfer oob to client buffer |
1357 | * @chip: nand chip structure | |
844d3b42 | 1358 | * @oob: oob destination address |
8593fbc6 | 1359 | * @ops: oob ops structure |
7014568b | 1360 | * @len: size of oob to transfer |
8593fbc6 TG |
1361 | */ |
1362 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, | |
7014568b | 1363 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 1364 | { |
8593fbc6 TG |
1365 | switch(ops->mode) { |
1366 | ||
1367 | case MTD_OOB_PLACE: | |
1368 | case MTD_OOB_RAW: | |
1369 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); | |
1370 | return oob + len; | |
1371 | ||
1372 | case MTD_OOB_AUTO: { | |
1373 | struct nand_oobfree *free = chip->ecc.layout->oobfree; | |
7bc3312b TG |
1374 | uint32_t boffs = 0, roffs = ops->ooboffs; |
1375 | size_t bytes = 0; | |
8593fbc6 TG |
1376 | |
1377 | for(; free->length && len; free++, len -= bytes) { | |
7bc3312b TG |
1378 | /* Read request not from offset 0 ? */ |
1379 | if (unlikely(roffs)) { | |
1380 | if (roffs >= free->length) { | |
1381 | roffs -= free->length; | |
1382 | continue; | |
1383 | } | |
1384 | boffs = free->offset + roffs; | |
1385 | bytes = min_t(size_t, len, | |
1386 | (free->length - roffs)); | |
1387 | roffs = 0; | |
1388 | } else { | |
1389 | bytes = min_t(size_t, len, free->length); | |
1390 | boffs = free->offset; | |
1391 | } | |
1392 | memcpy(oob, chip->oob_poi + boffs, bytes); | |
8593fbc6 TG |
1393 | oob += bytes; |
1394 | } | |
1395 | return oob; | |
1396 | } | |
1397 | default: | |
1398 | BUG(); | |
1399 | } | |
1400 | return NULL; | |
1401 | } | |
1402 | ||
1403 | /** | |
1404 | * nand_do_read_ops - [Internal] Read data with ECC | |
f5bbdacc TG |
1405 | * |
1406 | * @mtd: MTD device structure | |
1407 | * @from: offset to read from | |
844d3b42 | 1408 | * @ops: oob ops structure |
f5bbdacc TG |
1409 | * |
1410 | * Internal function. Called with chip held. | |
1411 | */ | |
8593fbc6 TG |
1412 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
1413 | struct mtd_oob_ops *ops) | |
f5bbdacc TG |
1414 | { |
1415 | int chipnr, page, realpage, col, bytes, aligned; | |
1416 | struct nand_chip *chip = mtd->priv; | |
1417 | struct mtd_ecc_stats stats; | |
1418 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
1419 | int sndcmd = 1; | |
1420 | int ret = 0; | |
8593fbc6 | 1421 | uint32_t readlen = ops->len; |
7014568b | 1422 | uint32_t oobreadlen = ops->ooblen; |
9aca334e ML |
1423 | uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ? |
1424 | mtd->oobavail : mtd->oobsize; | |
1425 | ||
8593fbc6 | 1426 | uint8_t *bufpoi, *oob, *buf; |
1da177e4 | 1427 | |
f5bbdacc | 1428 | stats = mtd->ecc_stats; |
1da177e4 | 1429 | |
f5bbdacc TG |
1430 | chipnr = (int)(from >> chip->chip_shift); |
1431 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 1432 | |
f5bbdacc TG |
1433 | realpage = (int)(from >> chip->page_shift); |
1434 | page = realpage & chip->pagemask; | |
1da177e4 | 1435 | |
f5bbdacc | 1436 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 1437 | |
8593fbc6 TG |
1438 | buf = ops->datbuf; |
1439 | oob = ops->oobbuf; | |
1440 | ||
f5bbdacc TG |
1441 | while(1) { |
1442 | bytes = min(mtd->writesize - col, readlen); | |
1443 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 1444 | |
f5bbdacc | 1445 | /* Is the current page in the buffer ? */ |
8593fbc6 | 1446 | if (realpage != chip->pagebuf || oob) { |
4bf63fcb | 1447 | bufpoi = aligned ? buf : chip->buffers->databuf; |
61b03bd7 | 1448 | |
f5bbdacc TG |
1449 | if (likely(sndcmd)) { |
1450 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); | |
1451 | sndcmd = 0; | |
1da177e4 | 1452 | } |
1da177e4 | 1453 | |
f5bbdacc | 1454 | /* Now read the page into the buffer */ |
956e944c | 1455 | if (unlikely(ops->mode == MTD_OOB_RAW)) |
46a8cf2d SN |
1456 | ret = chip->ecc.read_page_raw(mtd, chip, |
1457 | bufpoi, page); | |
3d459559 AK |
1458 | else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob) |
1459 | ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi); | |
956e944c | 1460 | else |
46a8cf2d SN |
1461 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
1462 | page); | |
f5bbdacc | 1463 | if (ret < 0) |
1da177e4 | 1464 | break; |
f5bbdacc TG |
1465 | |
1466 | /* Transfer not aligned data */ | |
1467 | if (!aligned) { | |
3d459559 AK |
1468 | if (!NAND_SUBPAGE_READ(chip) && !oob) |
1469 | chip->pagebuf = realpage; | |
4bf63fcb | 1470 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
1471 | } |
1472 | ||
8593fbc6 TG |
1473 | buf += bytes; |
1474 | ||
1475 | if (unlikely(oob)) { | |
9aca334e | 1476 | |
8593fbc6 | 1477 | /* Raw mode does data:oob:data:oob */ |
7014568b VW |
1478 | if (ops->mode != MTD_OOB_RAW) { |
1479 | int toread = min(oobreadlen, | |
9aca334e | 1480 | max_oobsize); |
7014568b VW |
1481 | if (toread) { |
1482 | oob = nand_transfer_oob(chip, | |
1483 | oob, ops, toread); | |
1484 | oobreadlen -= toread; | |
1485 | } | |
1486 | } else | |
1487 | buf = nand_transfer_oob(chip, | |
1488 | buf, ops, mtd->oobsize); | |
8593fbc6 TG |
1489 | } |
1490 | ||
f5bbdacc TG |
1491 | if (!(chip->options & NAND_NO_READRDY)) { |
1492 | /* | |
1493 | * Apply delay or wait for ready/busy pin. Do | |
1494 | * this before the AUTOINCR check, so no | |
1495 | * problems arise if a chip which does auto | |
1496 | * increment is marked as NOAUTOINCR by the | |
1497 | * board driver. | |
1498 | */ | |
1499 | if (!chip->dev_ready) | |
1500 | udelay(chip->chip_delay); | |
1501 | else | |
1502 | nand_wait_ready(mtd); | |
1da177e4 | 1503 | } |
8593fbc6 | 1504 | } else { |
4bf63fcb | 1505 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 TG |
1506 | buf += bytes; |
1507 | } | |
1da177e4 | 1508 | |
f5bbdacc | 1509 | readlen -= bytes; |
61b03bd7 | 1510 | |
f5bbdacc | 1511 | if (!readlen) |
61b03bd7 | 1512 | break; |
1da177e4 LT |
1513 | |
1514 | /* For subsequent reads align to page boundary. */ | |
1515 | col = 0; | |
1516 | /* Increment page address */ | |
1517 | realpage++; | |
1518 | ||
ace4dfee | 1519 | page = realpage & chip->pagemask; |
1da177e4 LT |
1520 | /* Check, if we cross a chip boundary */ |
1521 | if (!page) { | |
1522 | chipnr++; | |
ace4dfee TG |
1523 | chip->select_chip(mtd, -1); |
1524 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1525 | } |
f5bbdacc | 1526 | |
61b03bd7 TG |
1527 | /* Check, if the chip supports auto page increment |
1528 | * or if we have hit a block boundary. | |
e0c7d767 | 1529 | */ |
f5bbdacc | 1530 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) |
61b03bd7 | 1531 | sndcmd = 1; |
1da177e4 LT |
1532 | } |
1533 | ||
8593fbc6 | 1534 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
1535 | if (oob) |
1536 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 1537 | |
f5bbdacc TG |
1538 | if (ret) |
1539 | return ret; | |
1540 | ||
9a1fcdfd TG |
1541 | if (mtd->ecc_stats.failed - stats.failed) |
1542 | return -EBADMSG; | |
1543 | ||
1544 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
f5bbdacc TG |
1545 | } |
1546 | ||
1547 | /** | |
1548 | * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc | |
1549 | * @mtd: MTD device structure | |
1550 | * @from: offset to read from | |
1551 | * @len: number of bytes to read | |
1552 | * @retlen: pointer to variable to store the number of read bytes | |
1553 | * @buf: the databuffer to put data | |
1554 | * | |
1555 | * Get hold of the chip and call nand_do_read | |
1556 | */ | |
1557 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1558 | size_t *retlen, uint8_t *buf) | |
1559 | { | |
8593fbc6 | 1560 | struct nand_chip *chip = mtd->priv; |
f5bbdacc TG |
1561 | int ret; |
1562 | ||
f5bbdacc TG |
1563 | /* Do not allow reads past end of device */ |
1564 | if ((from + len) > mtd->size) | |
1565 | return -EINVAL; | |
1566 | if (!len) | |
1567 | return 0; | |
1568 | ||
8593fbc6 | 1569 | nand_get_device(chip, mtd, FL_READING); |
f5bbdacc | 1570 | |
8593fbc6 TG |
1571 | chip->ops.len = len; |
1572 | chip->ops.datbuf = buf; | |
1573 | chip->ops.oobbuf = NULL; | |
1574 | ||
1575 | ret = nand_do_read_ops(mtd, from, &chip->ops); | |
f5bbdacc | 1576 | |
7fd5aecc RP |
1577 | *retlen = chip->ops.retlen; |
1578 | ||
f5bbdacc TG |
1579 | nand_release_device(mtd); |
1580 | ||
1581 | return ret; | |
1da177e4 LT |
1582 | } |
1583 | ||
7bc3312b TG |
1584 | /** |
1585 | * nand_read_oob_std - [REPLACABLE] the most common OOB data read function | |
1586 | * @mtd: mtd info structure | |
1587 | * @chip: nand chip info structure | |
1588 | * @page: page number to read | |
1589 | * @sndcmd: flag whether to issue read command or not | |
1590 | */ | |
1591 | static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1592 | int page, int sndcmd) | |
1593 | { | |
1594 | if (sndcmd) { | |
1595 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1596 | sndcmd = 0; | |
1597 | } | |
1598 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1599 | return sndcmd; | |
1600 | } | |
1601 | ||
1602 | /** | |
1603 | * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC | |
1604 | * with syndromes | |
1605 | * @mtd: mtd info structure | |
1606 | * @chip: nand chip info structure | |
1607 | * @page: page number to read | |
1608 | * @sndcmd: flag whether to issue read command or not | |
1609 | */ | |
1610 | static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1611 | int page, int sndcmd) | |
1612 | { | |
1613 | uint8_t *buf = chip->oob_poi; | |
1614 | int length = mtd->oobsize; | |
1615 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1616 | int eccsize = chip->ecc.size; | |
1617 | uint8_t *bufpoi = buf; | |
1618 | int i, toread, sndrnd = 0, pos; | |
1619 | ||
1620 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
1621 | for (i = 0; i < chip->ecc.steps; i++) { | |
1622 | if (sndrnd) { | |
1623 | pos = eccsize + i * (eccsize + chunk); | |
1624 | if (mtd->writesize > 512) | |
1625 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
1626 | else | |
1627 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
1628 | } else | |
1629 | sndrnd = 1; | |
1630 | toread = min_t(int, length, chunk); | |
1631 | chip->read_buf(mtd, bufpoi, toread); | |
1632 | bufpoi += toread; | |
1633 | length -= toread; | |
1634 | } | |
1635 | if (length > 0) | |
1636 | chip->read_buf(mtd, bufpoi, length); | |
1637 | ||
1638 | return 1; | |
1639 | } | |
1640 | ||
1641 | /** | |
1642 | * nand_write_oob_std - [REPLACABLE] the most common OOB data write function | |
1643 | * @mtd: mtd info structure | |
1644 | * @chip: nand chip info structure | |
1645 | * @page: page number to write | |
1646 | */ | |
1647 | static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1648 | int page) | |
1649 | { | |
1650 | int status = 0; | |
1651 | const uint8_t *buf = chip->oob_poi; | |
1652 | int length = mtd->oobsize; | |
1653 | ||
1654 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
1655 | chip->write_buf(mtd, buf, length); | |
1656 | /* Send command to program the OOB data */ | |
1657 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1658 | ||
1659 | status = chip->waitfunc(mtd, chip); | |
1660 | ||
0d420f9d | 1661 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b TG |
1662 | } |
1663 | ||
1664 | /** | |
1665 | * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC | |
1666 | * with syndrome - only for large page flash ! | |
1667 | * @mtd: mtd info structure | |
1668 | * @chip: nand chip info structure | |
1669 | * @page: page number to write | |
1670 | */ | |
1671 | static int nand_write_oob_syndrome(struct mtd_info *mtd, | |
1672 | struct nand_chip *chip, int page) | |
1673 | { | |
1674 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1675 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
1676 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
1677 | const uint8_t *bufpoi = chip->oob_poi; | |
1678 | ||
1679 | /* | |
1680 | * data-ecc-data-ecc ... ecc-oob | |
1681 | * or | |
1682 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
1683 | */ | |
1684 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
1685 | pos = steps * (eccsize + chunk); | |
1686 | steps = 0; | |
1687 | } else | |
8b0036ee | 1688 | pos = eccsize; |
7bc3312b TG |
1689 | |
1690 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
1691 | for (i = 0; i < steps; i++) { | |
1692 | if (sndcmd) { | |
1693 | if (mtd->writesize <= 512) { | |
1694 | uint32_t fill = 0xFFFFFFFF; | |
1695 | ||
1696 | len = eccsize; | |
1697 | while (len > 0) { | |
1698 | int num = min_t(int, len, 4); | |
1699 | chip->write_buf(mtd, (uint8_t *)&fill, | |
1700 | num); | |
1701 | len -= num; | |
1702 | } | |
1703 | } else { | |
1704 | pos = eccsize + i * (eccsize + chunk); | |
1705 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
1706 | } | |
1707 | } else | |
1708 | sndcmd = 1; | |
1709 | len = min_t(int, length, chunk); | |
1710 | chip->write_buf(mtd, bufpoi, len); | |
1711 | bufpoi += len; | |
1712 | length -= len; | |
1713 | } | |
1714 | if (length > 0) | |
1715 | chip->write_buf(mtd, bufpoi, length); | |
1716 | ||
1717 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1718 | status = chip->waitfunc(mtd, chip); | |
1719 | ||
1720 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
1721 | } | |
1722 | ||
1da177e4 | 1723 | /** |
8593fbc6 | 1724 | * nand_do_read_oob - [Intern] NAND read out-of-band |
1da177e4 LT |
1725 | * @mtd: MTD device structure |
1726 | * @from: offset to read from | |
8593fbc6 | 1727 | * @ops: oob operations description structure |
1da177e4 LT |
1728 | * |
1729 | * NAND read out-of-band data from the spare area | |
1730 | */ | |
8593fbc6 TG |
1731 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
1732 | struct mtd_oob_ops *ops) | |
1da177e4 | 1733 | { |
7bc3312b | 1734 | int page, realpage, chipnr, sndcmd = 1; |
ace4dfee | 1735 | struct nand_chip *chip = mtd->priv; |
7314e9e7 | 1736 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; |
7014568b VW |
1737 | int readlen = ops->ooblen; |
1738 | int len; | |
7bc3312b | 1739 | uint8_t *buf = ops->oobbuf; |
61b03bd7 | 1740 | |
20d8e248 | 1741 | DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n", |
1742 | __func__, (unsigned long long)from, readlen); | |
1da177e4 | 1743 | |
03736155 | 1744 | if (ops->mode == MTD_OOB_AUTO) |
7014568b | 1745 | len = chip->ecc.layout->oobavail; |
03736155 AH |
1746 | else |
1747 | len = mtd->oobsize; | |
1748 | ||
1749 | if (unlikely(ops->ooboffs >= len)) { | |
20d8e248 | 1750 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read " |
1751 | "outside oob\n", __func__); | |
03736155 AH |
1752 | return -EINVAL; |
1753 | } | |
1754 | ||
1755 | /* Do not allow reads past end of device */ | |
1756 | if (unlikely(from >= mtd->size || | |
1757 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
1758 | (from >> chip->page_shift)) * len)) { | |
20d8e248 | 1759 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end " |
1760 | "of device\n", __func__); | |
03736155 AH |
1761 | return -EINVAL; |
1762 | } | |
7014568b | 1763 | |
7314e9e7 | 1764 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 1765 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1766 | |
7314e9e7 TG |
1767 | /* Shift to get page */ |
1768 | realpage = (int)(from >> chip->page_shift); | |
1769 | page = realpage & chip->pagemask; | |
1da177e4 | 1770 | |
7314e9e7 | 1771 | while(1) { |
7bc3312b | 1772 | sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd); |
7014568b VW |
1773 | |
1774 | len = min(len, readlen); | |
1775 | buf = nand_transfer_oob(chip, buf, ops, len); | |
8593fbc6 | 1776 | |
7314e9e7 TG |
1777 | if (!(chip->options & NAND_NO_READRDY)) { |
1778 | /* | |
1779 | * Apply delay or wait for ready/busy pin. Do this | |
1780 | * before the AUTOINCR check, so no problems arise if a | |
1781 | * chip which does auto increment is marked as | |
1782 | * NOAUTOINCR by the board driver. | |
19870da7 | 1783 | */ |
ace4dfee TG |
1784 | if (!chip->dev_ready) |
1785 | udelay(chip->chip_delay); | |
19870da7 TG |
1786 | else |
1787 | nand_wait_ready(mtd); | |
7314e9e7 | 1788 | } |
19870da7 | 1789 | |
7014568b | 1790 | readlen -= len; |
0d420f9d SZ |
1791 | if (!readlen) |
1792 | break; | |
1793 | ||
7314e9e7 TG |
1794 | /* Increment page address */ |
1795 | realpage++; | |
1796 | ||
1797 | page = realpage & chip->pagemask; | |
1798 | /* Check, if we cross a chip boundary */ | |
1799 | if (!page) { | |
1800 | chipnr++; | |
1801 | chip->select_chip(mtd, -1); | |
1802 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1803 | } |
7314e9e7 TG |
1804 | |
1805 | /* Check, if the chip supports auto page increment | |
1806 | * or if we have hit a block boundary. | |
1807 | */ | |
1808 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) | |
1809 | sndcmd = 1; | |
1da177e4 LT |
1810 | } |
1811 | ||
7014568b | 1812 | ops->oobretlen = ops->ooblen; |
1da177e4 LT |
1813 | return 0; |
1814 | } | |
1815 | ||
1816 | /** | |
8593fbc6 | 1817 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
1da177e4 | 1818 | * @mtd: MTD device structure |
1da177e4 | 1819 | * @from: offset to read from |
8593fbc6 | 1820 | * @ops: oob operation description structure |
1da177e4 | 1821 | * |
8593fbc6 | 1822 | * NAND read data and/or out-of-band data |
1da177e4 | 1823 | */ |
8593fbc6 TG |
1824 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
1825 | struct mtd_oob_ops *ops) | |
1da177e4 | 1826 | { |
ace4dfee | 1827 | struct nand_chip *chip = mtd->priv; |
8593fbc6 TG |
1828 | int ret = -ENOTSUPP; |
1829 | ||
1830 | ops->retlen = 0; | |
1da177e4 LT |
1831 | |
1832 | /* Do not allow reads past end of device */ | |
7014568b | 1833 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
20d8e248 | 1834 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read " |
1835 | "beyond end of device\n", __func__); | |
1da177e4 LT |
1836 | return -EINVAL; |
1837 | } | |
1838 | ||
ace4dfee | 1839 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 | 1840 | |
8593fbc6 TG |
1841 | switch(ops->mode) { |
1842 | case MTD_OOB_PLACE: | |
1843 | case MTD_OOB_AUTO: | |
8593fbc6 | 1844 | case MTD_OOB_RAW: |
8593fbc6 | 1845 | break; |
1da177e4 | 1846 | |
8593fbc6 TG |
1847 | default: |
1848 | goto out; | |
1849 | } | |
1da177e4 | 1850 | |
8593fbc6 TG |
1851 | if (!ops->datbuf) |
1852 | ret = nand_do_read_oob(mtd, from, ops); | |
1853 | else | |
1854 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 1855 | |
8593fbc6 TG |
1856 | out: |
1857 | nand_release_device(mtd); | |
1858 | return ret; | |
1859 | } | |
61b03bd7 | 1860 | |
1da177e4 | 1861 | |
8593fbc6 TG |
1862 | /** |
1863 | * nand_write_page_raw - [Intern] raw page write function | |
1864 | * @mtd: mtd info structure | |
1865 | * @chip: nand chip info structure | |
1866 | * @buf: data buffer | |
52ff49df DB |
1867 | * |
1868 | * Not for syndrome calculating ecc controllers, which use a special oob layout | |
8593fbc6 TG |
1869 | */ |
1870 | static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1871 | const uint8_t *buf) | |
1872 | { | |
1873 | chip->write_buf(mtd, buf, mtd->writesize); | |
1874 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1da177e4 LT |
1875 | } |
1876 | ||
52ff49df DB |
1877 | /** |
1878 | * nand_write_page_raw_syndrome - [Intern] raw page write function | |
1879 | * @mtd: mtd info structure | |
1880 | * @chip: nand chip info structure | |
1881 | * @buf: data buffer | |
1882 | * | |
1883 | * We need a special oob layout and handling even when ECC isn't checked. | |
1884 | */ | |
1885 | static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1886 | const uint8_t *buf) | |
1887 | { | |
1888 | int eccsize = chip->ecc.size; | |
1889 | int eccbytes = chip->ecc.bytes; | |
1890 | uint8_t *oob = chip->oob_poi; | |
1891 | int steps, size; | |
1892 | ||
1893 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1894 | chip->write_buf(mtd, buf, eccsize); | |
1895 | buf += eccsize; | |
1896 | ||
1897 | if (chip->ecc.prepad) { | |
1898 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
1899 | oob += chip->ecc.prepad; | |
1900 | } | |
1901 | ||
1902 | chip->read_buf(mtd, oob, eccbytes); | |
1903 | oob += eccbytes; | |
1904 | ||
1905 | if (chip->ecc.postpad) { | |
1906 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
1907 | oob += chip->ecc.postpad; | |
1908 | } | |
1909 | } | |
1910 | ||
1911 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1912 | if (size) | |
1913 | chip->write_buf(mtd, oob, size); | |
1914 | } | |
9223a456 | 1915 | /** |
d29ebdbe | 1916 | * nand_write_page_swecc - [REPLACABLE] software ecc based page write function |
f75e5097 TG |
1917 | * @mtd: mtd info structure |
1918 | * @chip: nand chip info structure | |
1919 | * @buf: data buffer | |
9223a456 | 1920 | */ |
f75e5097 TG |
1921 | static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1922 | const uint8_t *buf) | |
9223a456 | 1923 | { |
f75e5097 TG |
1924 | int i, eccsize = chip->ecc.size; |
1925 | int eccbytes = chip->ecc.bytes; | |
1926 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 1927 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 1928 | const uint8_t *p = buf; |
8b099a39 | 1929 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1930 | |
8593fbc6 TG |
1931 | /* Software ecc calculation */ |
1932 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1933 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 1934 | |
8593fbc6 TG |
1935 | for (i = 0; i < chip->ecc.total; i++) |
1936 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 | 1937 | |
90424de8 | 1938 | chip->ecc.write_page_raw(mtd, chip, buf); |
f75e5097 | 1939 | } |
9223a456 | 1940 | |
f75e5097 | 1941 | /** |
d29ebdbe | 1942 | * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function |
f75e5097 TG |
1943 | * @mtd: mtd info structure |
1944 | * @chip: nand chip info structure | |
1945 | * @buf: data buffer | |
1946 | */ | |
1947 | static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, | |
1948 | const uint8_t *buf) | |
1949 | { | |
1950 | int i, eccsize = chip->ecc.size; | |
1951 | int eccbytes = chip->ecc.bytes; | |
1952 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 1953 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 1954 | const uint8_t *p = buf; |
8b099a39 | 1955 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1956 | |
f75e5097 TG |
1957 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1958 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 1959 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 1960 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
1961 | } |
1962 | ||
f75e5097 TG |
1963 | for (i = 0; i < chip->ecc.total; i++) |
1964 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
1965 | ||
1966 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
9223a456 TG |
1967 | } |
1968 | ||
61b03bd7 | 1969 | /** |
d29ebdbe | 1970 | * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write |
f75e5097 TG |
1971 | * @mtd: mtd info structure |
1972 | * @chip: nand chip info structure | |
1973 | * @buf: data buffer | |
1da177e4 | 1974 | * |
f75e5097 TG |
1975 | * The hw generator calculates the error syndrome automatically. Therefor |
1976 | * we need a special oob layout and handling. | |
1977 | */ | |
1978 | static void nand_write_page_syndrome(struct mtd_info *mtd, | |
1979 | struct nand_chip *chip, const uint8_t *buf) | |
1da177e4 | 1980 | { |
f75e5097 TG |
1981 | int i, eccsize = chip->ecc.size; |
1982 | int eccbytes = chip->ecc.bytes; | |
1983 | int eccsteps = chip->ecc.steps; | |
1984 | const uint8_t *p = buf; | |
1985 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 1986 | |
f75e5097 | 1987 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 1988 | |
f75e5097 TG |
1989 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
1990 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 1991 | |
f75e5097 TG |
1992 | if (chip->ecc.prepad) { |
1993 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
1994 | oob += chip->ecc.prepad; | |
1995 | } | |
1996 | ||
1997 | chip->ecc.calculate(mtd, p, oob); | |
1998 | chip->write_buf(mtd, oob, eccbytes); | |
1999 | oob += eccbytes; | |
2000 | ||
2001 | if (chip->ecc.postpad) { | |
2002 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2003 | oob += chip->ecc.postpad; | |
1da177e4 | 2004 | } |
1da177e4 | 2005 | } |
f75e5097 TG |
2006 | |
2007 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 2008 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
2009 | if (i) |
2010 | chip->write_buf(mtd, oob, i); | |
2011 | } | |
2012 | ||
2013 | /** | |
956e944c | 2014 | * nand_write_page - [REPLACEABLE] write one page |
f75e5097 TG |
2015 | * @mtd: MTD device structure |
2016 | * @chip: NAND chip descriptor | |
2017 | * @buf: the data to write | |
2018 | * @page: page number to write | |
2019 | * @cached: cached programming | |
efbfe96c | 2020 | * @raw: use _raw version of write_page |
f75e5097 TG |
2021 | */ |
2022 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
956e944c | 2023 | const uint8_t *buf, int page, int cached, int raw) |
f75e5097 TG |
2024 | { |
2025 | int status; | |
2026 | ||
2027 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
2028 | ||
956e944c DW |
2029 | if (unlikely(raw)) |
2030 | chip->ecc.write_page_raw(mtd, chip, buf); | |
2031 | else | |
2032 | chip->ecc.write_page(mtd, chip, buf); | |
f75e5097 TG |
2033 | |
2034 | /* | |
2035 | * Cached progamming disabled for now, Not sure if its worth the | |
2036 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s) | |
2037 | */ | |
2038 | cached = 0; | |
2039 | ||
2040 | if (!cached || !(chip->options & NAND_CACHEPRG)) { | |
2041 | ||
2042 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
7bc3312b | 2043 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2044 | /* |
2045 | * See if operation failed and additional status checks are | |
2046 | * available | |
2047 | */ | |
2048 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2049 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
2050 | page); | |
2051 | ||
2052 | if (status & NAND_STATUS_FAIL) | |
2053 | return -EIO; | |
2054 | } else { | |
2055 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
7bc3312b | 2056 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2057 | } |
2058 | ||
2059 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE | |
2060 | /* Send command to read back the data */ | |
2061 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
2062 | ||
2063 | if (chip->verify_buf(mtd, buf, mtd->writesize)) | |
2064 | return -EIO; | |
2065 | #endif | |
2066 | return 0; | |
1da177e4 LT |
2067 | } |
2068 | ||
8593fbc6 TG |
2069 | /** |
2070 | * nand_fill_oob - [Internal] Transfer client buffer to oob | |
2071 | * @chip: nand chip structure | |
2072 | * @oob: oob data buffer | |
2073 | * @ops: oob ops structure | |
2074 | */ | |
2075 | static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, | |
2076 | struct mtd_oob_ops *ops) | |
2077 | { | |
2078 | size_t len = ops->ooblen; | |
2079 | ||
2080 | switch(ops->mode) { | |
2081 | ||
2082 | case MTD_OOB_PLACE: | |
2083 | case MTD_OOB_RAW: | |
2084 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); | |
2085 | return oob + len; | |
2086 | ||
2087 | case MTD_OOB_AUTO: { | |
2088 | struct nand_oobfree *free = chip->ecc.layout->oobfree; | |
7bc3312b TG |
2089 | uint32_t boffs = 0, woffs = ops->ooboffs; |
2090 | size_t bytes = 0; | |
8593fbc6 TG |
2091 | |
2092 | for(; free->length && len; free++, len -= bytes) { | |
7bc3312b TG |
2093 | /* Write request not from offset 0 ? */ |
2094 | if (unlikely(woffs)) { | |
2095 | if (woffs >= free->length) { | |
2096 | woffs -= free->length; | |
2097 | continue; | |
2098 | } | |
2099 | boffs = free->offset + woffs; | |
2100 | bytes = min_t(size_t, len, | |
2101 | (free->length - woffs)); | |
2102 | woffs = 0; | |
2103 | } else { | |
2104 | bytes = min_t(size_t, len, free->length); | |
2105 | boffs = free->offset; | |
2106 | } | |
8b0036ee | 2107 | memcpy(chip->oob_poi + boffs, oob, bytes); |
8593fbc6 TG |
2108 | oob += bytes; |
2109 | } | |
2110 | return oob; | |
2111 | } | |
2112 | default: | |
2113 | BUG(); | |
2114 | } | |
2115 | return NULL; | |
2116 | } | |
2117 | ||
29072b96 | 2118 | #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0 |
1da177e4 LT |
2119 | |
2120 | /** | |
8593fbc6 | 2121 | * nand_do_write_ops - [Internal] NAND write with ECC |
1da177e4 LT |
2122 | * @mtd: MTD device structure |
2123 | * @to: offset to write to | |
8593fbc6 | 2124 | * @ops: oob operations description structure |
1da177e4 LT |
2125 | * |
2126 | * NAND write with ECC | |
2127 | */ | |
8593fbc6 TG |
2128 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
2129 | struct mtd_oob_ops *ops) | |
1da177e4 | 2130 | { |
29072b96 | 2131 | int chipnr, realpage, page, blockmask, column; |
ace4dfee | 2132 | struct nand_chip *chip = mtd->priv; |
8593fbc6 TG |
2133 | uint32_t writelen = ops->len; |
2134 | uint8_t *oob = ops->oobbuf; | |
2135 | uint8_t *buf = ops->datbuf; | |
29072b96 | 2136 | int ret, subpage; |
1da177e4 | 2137 | |
8593fbc6 | 2138 | ops->retlen = 0; |
29072b96 TG |
2139 | if (!writelen) |
2140 | return 0; | |
1da177e4 | 2141 | |
61b03bd7 | 2142 | /* reject writes, which are not page aligned */ |
8593fbc6 | 2143 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
20d8e248 | 2144 | printk(KERN_NOTICE "%s: Attempt to write not " |
2145 | "page aligned data\n", __func__); | |
1da177e4 LT |
2146 | return -EINVAL; |
2147 | } | |
2148 | ||
29072b96 TG |
2149 | column = to & (mtd->writesize - 1); |
2150 | subpage = column || (writelen & (mtd->writesize - 1)); | |
2151 | ||
2152 | if (subpage && oob) | |
2153 | return -EINVAL; | |
1da177e4 | 2154 | |
6a930961 TG |
2155 | chipnr = (int)(to >> chip->chip_shift); |
2156 | chip->select_chip(mtd, chipnr); | |
2157 | ||
1da177e4 LT |
2158 | /* Check, if it is write protected */ |
2159 | if (nand_check_wp(mtd)) | |
8593fbc6 | 2160 | return -EIO; |
1da177e4 | 2161 | |
f75e5097 TG |
2162 | realpage = (int)(to >> chip->page_shift); |
2163 | page = realpage & chip->pagemask; | |
2164 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
2165 | ||
2166 | /* Invalidate the page cache, when we write to the cached page */ | |
2167 | if (to <= (chip->pagebuf << chip->page_shift) && | |
8593fbc6 | 2168 | (chip->pagebuf << chip->page_shift) < (to + ops->len)) |
ace4dfee | 2169 | chip->pagebuf = -1; |
61b03bd7 | 2170 | |
7dcdcbef DW |
2171 | /* If we're not given explicit OOB data, let it be 0xFF */ |
2172 | if (likely(!oob)) | |
2173 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
61b03bd7 | 2174 | |
f75e5097 | 2175 | while(1) { |
29072b96 | 2176 | int bytes = mtd->writesize; |
f75e5097 | 2177 | int cached = writelen > bytes && page != blockmask; |
29072b96 TG |
2178 | uint8_t *wbuf = buf; |
2179 | ||
2180 | /* Partial page write ? */ | |
2181 | if (unlikely(column || writelen < (mtd->writesize - 1))) { | |
2182 | cached = 0; | |
2183 | bytes = min_t(int, bytes - column, (int) writelen); | |
2184 | chip->pagebuf = -1; | |
2185 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
2186 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
2187 | wbuf = chip->buffers->databuf; | |
2188 | } | |
1da177e4 | 2189 | |
8593fbc6 TG |
2190 | if (unlikely(oob)) |
2191 | oob = nand_fill_oob(chip, oob, ops); | |
2192 | ||
29072b96 | 2193 | ret = chip->write_page(mtd, chip, wbuf, page, cached, |
956e944c | 2194 | (ops->mode == MTD_OOB_RAW)); |
f75e5097 TG |
2195 | if (ret) |
2196 | break; | |
2197 | ||
2198 | writelen -= bytes; | |
2199 | if (!writelen) | |
2200 | break; | |
2201 | ||
29072b96 | 2202 | column = 0; |
f75e5097 TG |
2203 | buf += bytes; |
2204 | realpage++; | |
2205 | ||
2206 | page = realpage & chip->pagemask; | |
2207 | /* Check, if we cross a chip boundary */ | |
2208 | if (!page) { | |
2209 | chipnr++; | |
2210 | chip->select_chip(mtd, -1); | |
2211 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2212 | } |
2213 | } | |
8593fbc6 | 2214 | |
8593fbc6 | 2215 | ops->retlen = ops->len - writelen; |
7014568b VW |
2216 | if (unlikely(oob)) |
2217 | ops->oobretlen = ops->ooblen; | |
1da177e4 LT |
2218 | return ret; |
2219 | } | |
2220 | ||
2af7c653 SK |
2221 | /** |
2222 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
2223 | * @mtd: MTD device structure | |
2224 | * @to: offset to write to | |
2225 | * @len: number of bytes to write | |
2226 | * @retlen: pointer to variable to store the number of written bytes | |
2227 | * @buf: the data to write | |
2228 | * | |
2229 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
2230 | * may for example be called by mtdoops when writing an oops while in panic. | |
2231 | */ | |
2232 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
2233 | size_t *retlen, const uint8_t *buf) | |
2234 | { | |
2235 | struct nand_chip *chip = mtd->priv; | |
2236 | int ret; | |
2237 | ||
2238 | /* Do not allow reads past end of device */ | |
2239 | if ((to + len) > mtd->size) | |
2240 | return -EINVAL; | |
2241 | if (!len) | |
2242 | return 0; | |
2243 | ||
2244 | /* Wait for the device to get ready. */ | |
2245 | panic_nand_wait(mtd, chip, 400); | |
2246 | ||
2247 | /* Grab the device. */ | |
2248 | panic_nand_get_device(chip, mtd, FL_WRITING); | |
2249 | ||
2250 | chip->ops.len = len; | |
2251 | chip->ops.datbuf = (uint8_t *)buf; | |
2252 | chip->ops.oobbuf = NULL; | |
2253 | ||
2254 | ret = nand_do_write_ops(mtd, to, &chip->ops); | |
2255 | ||
2256 | *retlen = chip->ops.retlen; | |
2257 | return ret; | |
2258 | } | |
2259 | ||
f75e5097 | 2260 | /** |
8593fbc6 | 2261 | * nand_write - [MTD Interface] NAND write with ECC |
f75e5097 | 2262 | * @mtd: MTD device structure |
f75e5097 TG |
2263 | * @to: offset to write to |
2264 | * @len: number of bytes to write | |
8593fbc6 TG |
2265 | * @retlen: pointer to variable to store the number of written bytes |
2266 | * @buf: the data to write | |
f75e5097 | 2267 | * |
8593fbc6 | 2268 | * NAND write with ECC |
f75e5097 | 2269 | */ |
8593fbc6 TG |
2270 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
2271 | size_t *retlen, const uint8_t *buf) | |
f75e5097 TG |
2272 | { |
2273 | struct nand_chip *chip = mtd->priv; | |
f75e5097 TG |
2274 | int ret; |
2275 | ||
8593fbc6 TG |
2276 | /* Do not allow reads past end of device */ |
2277 | if ((to + len) > mtd->size) | |
f75e5097 | 2278 | return -EINVAL; |
8593fbc6 TG |
2279 | if (!len) |
2280 | return 0; | |
f75e5097 | 2281 | |
7bc3312b | 2282 | nand_get_device(chip, mtd, FL_WRITING); |
f75e5097 | 2283 | |
8593fbc6 TG |
2284 | chip->ops.len = len; |
2285 | chip->ops.datbuf = (uint8_t *)buf; | |
2286 | chip->ops.oobbuf = NULL; | |
f75e5097 | 2287 | |
8593fbc6 | 2288 | ret = nand_do_write_ops(mtd, to, &chip->ops); |
f75e5097 | 2289 | |
7fd5aecc RP |
2290 | *retlen = chip->ops.retlen; |
2291 | ||
f75e5097 | 2292 | nand_release_device(mtd); |
8593fbc6 | 2293 | |
8593fbc6 | 2294 | return ret; |
f75e5097 | 2295 | } |
7314e9e7 | 2296 | |
1da177e4 | 2297 | /** |
8593fbc6 | 2298 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
1da177e4 LT |
2299 | * @mtd: MTD device structure |
2300 | * @to: offset to write to | |
8593fbc6 | 2301 | * @ops: oob operation description structure |
1da177e4 LT |
2302 | * |
2303 | * NAND write out-of-band | |
2304 | */ | |
8593fbc6 TG |
2305 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
2306 | struct mtd_oob_ops *ops) | |
1da177e4 | 2307 | { |
03736155 | 2308 | int chipnr, page, status, len; |
ace4dfee | 2309 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2310 | |
20d8e248 | 2311 | DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n", |
2312 | __func__, (unsigned int)to, (int)ops->ooblen); | |
1da177e4 | 2313 | |
03736155 AH |
2314 | if (ops->mode == MTD_OOB_AUTO) |
2315 | len = chip->ecc.layout->oobavail; | |
2316 | else | |
2317 | len = mtd->oobsize; | |
2318 | ||
1da177e4 | 2319 | /* Do not allow write past end of page */ |
03736155 | 2320 | if ((ops->ooboffs + ops->ooblen) > len) { |
20d8e248 | 2321 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write " |
2322 | "past end of page\n", __func__); | |
1da177e4 LT |
2323 | return -EINVAL; |
2324 | } | |
2325 | ||
03736155 | 2326 | if (unlikely(ops->ooboffs >= len)) { |
20d8e248 | 2327 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start " |
2328 | "write outside oob\n", __func__); | |
03736155 AH |
2329 | return -EINVAL; |
2330 | } | |
2331 | ||
2332 | /* Do not allow reads past end of device */ | |
2333 | if (unlikely(to >= mtd->size || | |
2334 | ops->ooboffs + ops->ooblen > | |
2335 | ((mtd->size >> chip->page_shift) - | |
2336 | (to >> chip->page_shift)) * len)) { | |
20d8e248 | 2337 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond " |
2338 | "end of device\n", __func__); | |
03736155 AH |
2339 | return -EINVAL; |
2340 | } | |
2341 | ||
7314e9e7 | 2342 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 2343 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2344 | |
7314e9e7 TG |
2345 | /* Shift to get page */ |
2346 | page = (int)(to >> chip->page_shift); | |
2347 | ||
2348 | /* | |
2349 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
2350 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
2351 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
2352 | * it in the doc2000 driver in August 1999. dwmw2. | |
2353 | */ | |
ace4dfee | 2354 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
2355 | |
2356 | /* Check, if it is write protected */ | |
2357 | if (nand_check_wp(mtd)) | |
8593fbc6 | 2358 | return -EROFS; |
61b03bd7 | 2359 | |
1da177e4 | 2360 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
2361 | if (page == chip->pagebuf) |
2362 | chip->pagebuf = -1; | |
1da177e4 | 2363 | |
7bc3312b TG |
2364 | memset(chip->oob_poi, 0xff, mtd->oobsize); |
2365 | nand_fill_oob(chip, ops->oobbuf, ops); | |
2366 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); | |
2367 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
1da177e4 | 2368 | |
7bc3312b TG |
2369 | if (status) |
2370 | return status; | |
1da177e4 | 2371 | |
7014568b | 2372 | ops->oobretlen = ops->ooblen; |
1da177e4 | 2373 | |
7bc3312b | 2374 | return 0; |
8593fbc6 TG |
2375 | } |
2376 | ||
2377 | /** | |
2378 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
2379 | * @mtd: MTD device structure | |
844d3b42 | 2380 | * @to: offset to write to |
8593fbc6 TG |
2381 | * @ops: oob operation description structure |
2382 | */ | |
2383 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
2384 | struct mtd_oob_ops *ops) | |
2385 | { | |
8593fbc6 TG |
2386 | struct nand_chip *chip = mtd->priv; |
2387 | int ret = -ENOTSUPP; | |
2388 | ||
2389 | ops->retlen = 0; | |
2390 | ||
2391 | /* Do not allow writes past end of device */ | |
7014568b | 2392 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
20d8e248 | 2393 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond " |
2394 | "end of device\n", __func__); | |
8593fbc6 TG |
2395 | return -EINVAL; |
2396 | } | |
2397 | ||
7bc3312b | 2398 | nand_get_device(chip, mtd, FL_WRITING); |
8593fbc6 TG |
2399 | |
2400 | switch(ops->mode) { | |
2401 | case MTD_OOB_PLACE: | |
2402 | case MTD_OOB_AUTO: | |
8593fbc6 | 2403 | case MTD_OOB_RAW: |
8593fbc6 TG |
2404 | break; |
2405 | ||
2406 | default: | |
2407 | goto out; | |
2408 | } | |
2409 | ||
2410 | if (!ops->datbuf) | |
2411 | ret = nand_do_write_oob(mtd, to, ops); | |
2412 | else | |
2413 | ret = nand_do_write_ops(mtd, to, ops); | |
2414 | ||
e0c7d767 | 2415 | out: |
1da177e4 | 2416 | nand_release_device(mtd); |
1da177e4 LT |
2417 | return ret; |
2418 | } | |
2419 | ||
1da177e4 LT |
2420 | /** |
2421 | * single_erease_cmd - [GENERIC] NAND standard block erase command function | |
2422 | * @mtd: MTD device structure | |
2423 | * @page: the page address of the block which will be erased | |
2424 | * | |
2425 | * Standard erase command for NAND chips | |
2426 | */ | |
e0c7d767 | 2427 | static void single_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 2428 | { |
ace4dfee | 2429 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2430 | /* Send commands to erase a block */ |
ace4dfee TG |
2431 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
2432 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
2433 | } |
2434 | ||
2435 | /** | |
2436 | * multi_erease_cmd - [GENERIC] AND specific block erase command function | |
2437 | * @mtd: MTD device structure | |
2438 | * @page: the page address of the block which will be erased | |
2439 | * | |
2440 | * AND multi block erase command function | |
2441 | * Erase 4 consecutive blocks | |
2442 | */ | |
e0c7d767 | 2443 | static void multi_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 2444 | { |
ace4dfee | 2445 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2446 | /* Send commands to erase a block */ |
ace4dfee TG |
2447 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); |
2448 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
2449 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
2450 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); | |
2451 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
2452 | } |
2453 | ||
2454 | /** | |
2455 | * nand_erase - [MTD Interface] erase block(s) | |
2456 | * @mtd: MTD device structure | |
2457 | * @instr: erase instruction | |
2458 | * | |
2459 | * Erase one ore more blocks | |
2460 | */ | |
e0c7d767 | 2461 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 2462 | { |
e0c7d767 | 2463 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 2464 | } |
61b03bd7 | 2465 | |
30f464b7 | 2466 | #define BBT_PAGE_MASK 0xffffff3f |
1da177e4 | 2467 | /** |
ace4dfee | 2468 | * nand_erase_nand - [Internal] erase block(s) |
1da177e4 LT |
2469 | * @mtd: MTD device structure |
2470 | * @instr: erase instruction | |
2471 | * @allowbbt: allow erasing the bbt area | |
2472 | * | |
2473 | * Erase one ore more blocks | |
2474 | */ | |
ace4dfee TG |
2475 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
2476 | int allowbbt) | |
1da177e4 | 2477 | { |
69423d99 | 2478 | int page, status, pages_per_block, ret, chipnr; |
ace4dfee | 2479 | struct nand_chip *chip = mtd->priv; |
69423d99 | 2480 | loff_t rewrite_bbt[NAND_MAX_CHIPS]={0}; |
ace4dfee | 2481 | unsigned int bbt_masked_page = 0xffffffff; |
69423d99 | 2482 | loff_t len; |
1da177e4 | 2483 | |
20d8e248 | 2484 | DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n", |
2485 | __func__, (unsigned long long)instr->addr, | |
2486 | (unsigned long long)instr->len); | |
1da177e4 | 2487 | |
6fe5a6ac | 2488 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 2489 | return -EINVAL; |
1da177e4 | 2490 | |
bb0eb217 | 2491 | instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN; |
1da177e4 LT |
2492 | |
2493 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 2494 | nand_get_device(chip, mtd, FL_ERASING); |
1da177e4 LT |
2495 | |
2496 | /* Shift to get first page */ | |
ace4dfee TG |
2497 | page = (int)(instr->addr >> chip->page_shift); |
2498 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
2499 | |
2500 | /* Calculate pages in each block */ | |
ace4dfee | 2501 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
2502 | |
2503 | /* Select the NAND device */ | |
ace4dfee | 2504 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2505 | |
1da177e4 LT |
2506 | /* Check, if it is write protected */ |
2507 | if (nand_check_wp(mtd)) { | |
20d8e248 | 2508 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n", |
2509 | __func__); | |
1da177e4 LT |
2510 | instr->state = MTD_ERASE_FAILED; |
2511 | goto erase_exit; | |
2512 | } | |
2513 | ||
ace4dfee TG |
2514 | /* |
2515 | * If BBT requires refresh, set the BBT page mask to see if the BBT | |
2516 | * should be rewritten. Otherwise the mask is set to 0xffffffff which | |
2517 | * can not be matched. This is also done when the bbt is actually | |
2518 | * erased to avoid recusrsive updates | |
2519 | */ | |
2520 | if (chip->options & BBT_AUTO_REFRESH && !allowbbt) | |
2521 | bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK; | |
30f464b7 | 2522 | |
1da177e4 LT |
2523 | /* Loop through the pages */ |
2524 | len = instr->len; | |
2525 | ||
2526 | instr->state = MTD_ERASING; | |
2527 | ||
2528 | while (len) { | |
ace4dfee TG |
2529 | /* |
2530 | * heck if we have a bad block, we do not erase bad blocks ! | |
2531 | */ | |
2532 | if (nand_block_checkbad(mtd, ((loff_t) page) << | |
2533 | chip->page_shift, 0, allowbbt)) { | |
20d8e248 | 2534 | printk(KERN_WARNING "%s: attempt to erase a bad block " |
2535 | "at page 0x%08x\n", __func__, page); | |
1da177e4 LT |
2536 | instr->state = MTD_ERASE_FAILED; |
2537 | goto erase_exit; | |
2538 | } | |
61b03bd7 | 2539 | |
ace4dfee TG |
2540 | /* |
2541 | * Invalidate the page cache, if we erase the block which | |
2542 | * contains the current cached page | |
2543 | */ | |
2544 | if (page <= chip->pagebuf && chip->pagebuf < | |
2545 | (page + pages_per_block)) | |
2546 | chip->pagebuf = -1; | |
1da177e4 | 2547 | |
ace4dfee | 2548 | chip->erase_cmd(mtd, page & chip->pagemask); |
61b03bd7 | 2549 | |
7bc3312b | 2550 | status = chip->waitfunc(mtd, chip); |
1da177e4 | 2551 | |
ace4dfee TG |
2552 | /* |
2553 | * See if operation failed and additional status checks are | |
2554 | * available | |
2555 | */ | |
2556 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2557 | status = chip->errstat(mtd, chip, FL_ERASING, | |
2558 | status, page); | |
068e3c0a | 2559 | |
1da177e4 | 2560 | /* See if block erase succeeded */ |
a4ab4c5d | 2561 | if (status & NAND_STATUS_FAIL) { |
20d8e248 | 2562 | DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, " |
2563 | "page 0x%08x\n", __func__, page); | |
1da177e4 | 2564 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
2565 | instr->fail_addr = |
2566 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
2567 | goto erase_exit; |
2568 | } | |
30f464b7 | 2569 | |
ace4dfee TG |
2570 | /* |
2571 | * If BBT requires refresh, set the BBT rewrite flag to the | |
2572 | * page being erased | |
2573 | */ | |
2574 | if (bbt_masked_page != 0xffffffff && | |
2575 | (page & BBT_PAGE_MASK) == bbt_masked_page) | |
69423d99 AH |
2576 | rewrite_bbt[chipnr] = |
2577 | ((loff_t)page << chip->page_shift); | |
61b03bd7 | 2578 | |
1da177e4 | 2579 | /* Increment page address and decrement length */ |
ace4dfee | 2580 | len -= (1 << chip->phys_erase_shift); |
1da177e4 LT |
2581 | page += pages_per_block; |
2582 | ||
2583 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 2584 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 2585 | chipnr++; |
ace4dfee TG |
2586 | chip->select_chip(mtd, -1); |
2587 | chip->select_chip(mtd, chipnr); | |
30f464b7 | 2588 | |
ace4dfee TG |
2589 | /* |
2590 | * If BBT requires refresh and BBT-PERCHIP, set the BBT | |
2591 | * page mask to see if this BBT should be rewritten | |
2592 | */ | |
2593 | if (bbt_masked_page != 0xffffffff && | |
2594 | (chip->bbt_td->options & NAND_BBT_PERCHIP)) | |
2595 | bbt_masked_page = chip->bbt_td->pages[chipnr] & | |
2596 | BBT_PAGE_MASK; | |
1da177e4 LT |
2597 | } |
2598 | } | |
2599 | instr->state = MTD_ERASE_DONE; | |
2600 | ||
e0c7d767 | 2601 | erase_exit: |
1da177e4 LT |
2602 | |
2603 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
2604 | |
2605 | /* Deselect and wake up anyone waiting on the device */ | |
2606 | nand_release_device(mtd); | |
2607 | ||
49defc01 DW |
2608 | /* Do call back function */ |
2609 | if (!ret) | |
2610 | mtd_erase_callback(instr); | |
2611 | ||
ace4dfee TG |
2612 | /* |
2613 | * If BBT requires refresh and erase was successful, rewrite any | |
2614 | * selected bad block tables | |
2615 | */ | |
2616 | if (bbt_masked_page == 0xffffffff || ret) | |
2617 | return ret; | |
2618 | ||
2619 | for (chipnr = 0; chipnr < chip->numchips; chipnr++) { | |
2620 | if (!rewrite_bbt[chipnr]) | |
2621 | continue; | |
2622 | /* update the BBT for chip */ | |
20d8e248 | 2623 | DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt " |
2624 | "(%d:0x%0llx 0x%0x)\n", __func__, chipnr, | |
2625 | rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]); | |
ace4dfee | 2626 | nand_update_bbt(mtd, rewrite_bbt[chipnr]); |
30f464b7 DM |
2627 | } |
2628 | ||
1da177e4 LT |
2629 | /* Return more or less happy */ |
2630 | return ret; | |
2631 | } | |
2632 | ||
2633 | /** | |
2634 | * nand_sync - [MTD Interface] sync | |
2635 | * @mtd: MTD device structure | |
2636 | * | |
2637 | * Sync is actually a wait for chip ready function | |
2638 | */ | |
e0c7d767 | 2639 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 2640 | { |
ace4dfee | 2641 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2642 | |
20d8e248 | 2643 | DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__); |
1da177e4 LT |
2644 | |
2645 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 2646 | nand_get_device(chip, mtd, FL_SYNCING); |
1da177e4 | 2647 | /* Release it and go back */ |
e0c7d767 | 2648 | nand_release_device(mtd); |
1da177e4 LT |
2649 | } |
2650 | ||
1da177e4 | 2651 | /** |
ace4dfee | 2652 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
1da177e4 | 2653 | * @mtd: MTD device structure |
844d3b42 | 2654 | * @offs: offset relative to mtd start |
1da177e4 | 2655 | */ |
ace4dfee | 2656 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 LT |
2657 | { |
2658 | /* Check for invalid offset */ | |
ace4dfee | 2659 | if (offs > mtd->size) |
1da177e4 | 2660 | return -EINVAL; |
61b03bd7 | 2661 | |
ace4dfee | 2662 | return nand_block_checkbad(mtd, offs, 1, 0); |
1da177e4 LT |
2663 | } |
2664 | ||
2665 | /** | |
ace4dfee | 2666 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
1da177e4 LT |
2667 | * @mtd: MTD device structure |
2668 | * @ofs: offset relative to mtd start | |
2669 | */ | |
e0c7d767 | 2670 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 2671 | { |
ace4dfee | 2672 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
2673 | int ret; |
2674 | ||
e0c7d767 DW |
2675 | if ((ret = nand_block_isbad(mtd, ofs))) { |
2676 | /* If it was bad already, return success and do nothing. */ | |
1da177e4 LT |
2677 | if (ret > 0) |
2678 | return 0; | |
e0c7d767 DW |
2679 | return ret; |
2680 | } | |
1da177e4 | 2681 | |
ace4dfee | 2682 | return chip->block_markbad(mtd, ofs); |
1da177e4 LT |
2683 | } |
2684 | ||
962034f4 VW |
2685 | /** |
2686 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
2687 | * @mtd: MTD device structure | |
2688 | */ | |
2689 | static int nand_suspend(struct mtd_info *mtd) | |
2690 | { | |
ace4dfee | 2691 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2692 | |
ace4dfee | 2693 | return nand_get_device(chip, mtd, FL_PM_SUSPENDED); |
962034f4 VW |
2694 | } |
2695 | ||
2696 | /** | |
2697 | * nand_resume - [MTD Interface] Resume the NAND flash | |
2698 | * @mtd: MTD device structure | |
2699 | */ | |
2700 | static void nand_resume(struct mtd_info *mtd) | |
2701 | { | |
ace4dfee | 2702 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2703 | |
ace4dfee | 2704 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
2705 | nand_release_device(mtd); |
2706 | else | |
20d8e248 | 2707 | printk(KERN_ERR "%s called for a chip which is not " |
2708 | "in suspended state\n", __func__); | |
962034f4 VW |
2709 | } |
2710 | ||
7aa65bfd TG |
2711 | /* |
2712 | * Set default functions | |
2713 | */ | |
ace4dfee | 2714 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 2715 | { |
1da177e4 | 2716 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
2717 | if (!chip->chip_delay) |
2718 | chip->chip_delay = 20; | |
1da177e4 LT |
2719 | |
2720 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
2721 | if (chip->cmdfunc == NULL) |
2722 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
2723 | |
2724 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
2725 | if (chip->waitfunc == NULL) |
2726 | chip->waitfunc = nand_wait; | |
2727 | ||
2728 | if (!chip->select_chip) | |
2729 | chip->select_chip = nand_select_chip; | |
2730 | if (!chip->read_byte) | |
2731 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; | |
2732 | if (!chip->read_word) | |
2733 | chip->read_word = nand_read_word; | |
2734 | if (!chip->block_bad) | |
2735 | chip->block_bad = nand_block_bad; | |
2736 | if (!chip->block_markbad) | |
2737 | chip->block_markbad = nand_default_block_markbad; | |
2738 | if (!chip->write_buf) | |
2739 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; | |
2740 | if (!chip->read_buf) | |
2741 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; | |
2742 | if (!chip->verify_buf) | |
2743 | chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; | |
2744 | if (!chip->scan_bbt) | |
2745 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
2746 | |
2747 | if (!chip->controller) { | |
2748 | chip->controller = &chip->hwcontrol; | |
2749 | spin_lock_init(&chip->controller->lock); | |
2750 | init_waitqueue_head(&chip->controller->wq); | |
2751 | } | |
2752 | ||
7aa65bfd TG |
2753 | } |
2754 | ||
2755 | /* | |
ace4dfee | 2756 | * Get the flash and manufacturer id and lookup if the type is supported |
7aa65bfd TG |
2757 | */ |
2758 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 2759 | struct nand_chip *chip, |
7aa65bfd TG |
2760 | int busw, int *maf_id) |
2761 | { | |
2762 | struct nand_flash_dev *type = NULL; | |
2763 | int i, dev_id, maf_idx; | |
ed8165c7 | 2764 | int tmp_id, tmp_manf; |
1da177e4 LT |
2765 | |
2766 | /* Select the device */ | |
ace4dfee | 2767 | chip->select_chip(mtd, 0); |
1da177e4 | 2768 | |
ef89a880 KB |
2769 | /* |
2770 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
2771 | * after power-up | |
2772 | */ | |
2773 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
2774 | ||
1da177e4 | 2775 | /* Send the command for reading device ID */ |
ace4dfee | 2776 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
2777 | |
2778 | /* Read manufacturer and device IDs */ | |
ace4dfee TG |
2779 | *maf_id = chip->read_byte(mtd); |
2780 | dev_id = chip->read_byte(mtd); | |
1da177e4 | 2781 | |
ed8165c7 BD |
2782 | /* Try again to make sure, as some systems the bus-hold or other |
2783 | * interface concerns can cause random data which looks like a | |
2784 | * possibly credible NAND flash to appear. If the two results do | |
2785 | * not match, ignore the device completely. | |
2786 | */ | |
2787 | ||
2788 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
2789 | ||
2790 | /* Read manufacturer and device IDs */ | |
2791 | ||
2792 | tmp_manf = chip->read_byte(mtd); | |
2793 | tmp_id = chip->read_byte(mtd); | |
2794 | ||
2795 | if (tmp_manf != *maf_id || tmp_id != dev_id) { | |
2796 | printk(KERN_INFO "%s: second ID read did not match " | |
2797 | "%02x,%02x against %02x,%02x\n", __func__, | |
2798 | *maf_id, dev_id, tmp_manf, tmp_id); | |
2799 | return ERR_PTR(-ENODEV); | |
2800 | } | |
2801 | ||
7aa65bfd | 2802 | /* Lookup the flash id */ |
1da177e4 | 2803 | for (i = 0; nand_flash_ids[i].name != NULL; i++) { |
7aa65bfd TG |
2804 | if (dev_id == nand_flash_ids[i].id) { |
2805 | type = &nand_flash_ids[i]; | |
2806 | break; | |
2807 | } | |
2808 | } | |
61b03bd7 | 2809 | |
7aa65bfd TG |
2810 | if (!type) |
2811 | return ERR_PTR(-ENODEV); | |
2812 | ||
ba0251fe TG |
2813 | if (!mtd->name) |
2814 | mtd->name = type->name; | |
2815 | ||
69423d99 | 2816 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd TG |
2817 | |
2818 | /* Newer devices have all the information in additional id bytes */ | |
ba0251fe | 2819 | if (!type->pagesize) { |
7aa65bfd | 2820 | int extid; |
29072b96 TG |
2821 | /* The 3rd id byte holds MLC / multichip data */ |
2822 | chip->cellinfo = chip->read_byte(mtd); | |
7aa65bfd | 2823 | /* The 4th id byte is the important one */ |
ace4dfee | 2824 | extid = chip->read_byte(mtd); |
7aa65bfd | 2825 | /* Calc pagesize */ |
4cbb9b80 | 2826 | mtd->writesize = 1024 << (extid & 0x3); |
7aa65bfd TG |
2827 | extid >>= 2; |
2828 | /* Calc oobsize */ | |
4cbb9b80 | 2829 | mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9); |
7aa65bfd TG |
2830 | extid >>= 2; |
2831 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
2832 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
2833 | extid >>= 2; | |
2834 | /* Get buswidth information */ | |
2835 | busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
61b03bd7 | 2836 | |
7aa65bfd TG |
2837 | } else { |
2838 | /* | |
ace4dfee | 2839 | * Old devices have chip data hardcoded in the device id table |
7aa65bfd | 2840 | */ |
ba0251fe TG |
2841 | mtd->erasesize = type->erasesize; |
2842 | mtd->writesize = type->pagesize; | |
4cbb9b80 | 2843 | mtd->oobsize = mtd->writesize / 32; |
ba0251fe | 2844 | busw = type->options & NAND_BUSWIDTH_16; |
7aa65bfd | 2845 | } |
1da177e4 | 2846 | |
7aa65bfd | 2847 | /* Try to identify manufacturer */ |
9a909867 | 2848 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { |
7aa65bfd TG |
2849 | if (nand_manuf_ids[maf_idx].id == *maf_id) |
2850 | break; | |
2851 | } | |
0ea4a755 | 2852 | |
7aa65bfd TG |
2853 | /* |
2854 | * Check, if buswidth is correct. Hardware drivers should set | |
ace4dfee | 2855 | * chip correct ! |
7aa65bfd | 2856 | */ |
ace4dfee | 2857 | if (busw != (chip->options & NAND_BUSWIDTH_16)) { |
7aa65bfd TG |
2858 | printk(KERN_INFO "NAND device: Manufacturer ID:" |
2859 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, | |
2860 | dev_id, nand_manuf_ids[maf_idx].name, mtd->name); | |
2861 | printk(KERN_WARNING "NAND bus width %d instead %d bit\n", | |
ace4dfee | 2862 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
7aa65bfd TG |
2863 | busw ? 16 : 8); |
2864 | return ERR_PTR(-EINVAL); | |
2865 | } | |
61b03bd7 | 2866 | |
7aa65bfd | 2867 | /* Calculate the address shift from the page size */ |
ace4dfee | 2868 | chip->page_shift = ffs(mtd->writesize) - 1; |
7aa65bfd | 2869 | /* Convert chipsize to number of pages per chip -1. */ |
ace4dfee | 2870 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 2871 | |
ace4dfee | 2872 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 2873 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
2874 | if (chip->chipsize & 0xffffffff) |
2875 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
2876 | else | |
2877 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1; | |
1da177e4 | 2878 | |
7aa65bfd | 2879 | /* Set the bad block position */ |
ace4dfee | 2880 | chip->badblockpos = mtd->writesize > 512 ? |
7aa65bfd | 2881 | NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS; |
61b03bd7 | 2882 | |
7aa65bfd | 2883 | /* Get chip options, preserve non chip based options */ |
ace4dfee | 2884 | chip->options &= ~NAND_CHIPOPTIONS_MSK; |
ba0251fe | 2885 | chip->options |= type->options & NAND_CHIPOPTIONS_MSK; |
7aa65bfd TG |
2886 | |
2887 | /* | |
ace4dfee | 2888 | * Set chip as a default. Board drivers can override it, if necessary |
7aa65bfd | 2889 | */ |
ace4dfee | 2890 | chip->options |= NAND_NO_AUTOINCR; |
7aa65bfd | 2891 | |
ace4dfee | 2892 | /* Check if chip is a not a samsung device. Do not clear the |
7aa65bfd TG |
2893 | * options for chips which are not having an extended id. |
2894 | */ | |
ba0251fe | 2895 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) |
ace4dfee | 2896 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; |
7aa65bfd TG |
2897 | |
2898 | /* Check for AND chips with 4 page planes */ | |
ace4dfee TG |
2899 | if (chip->options & NAND_4PAGE_ARRAY) |
2900 | chip->erase_cmd = multi_erase_cmd; | |
7aa65bfd | 2901 | else |
ace4dfee | 2902 | chip->erase_cmd = single_erase_cmd; |
7aa65bfd TG |
2903 | |
2904 | /* Do not replace user supplied command function ! */ | |
ace4dfee TG |
2905 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
2906 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd TG |
2907 | |
2908 | printk(KERN_INFO "NAND device: Manufacturer ID:" | |
2909 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id, | |
2910 | nand_manuf_ids[maf_idx].name, type->name); | |
2911 | ||
2912 | return type; | |
2913 | } | |
2914 | ||
7aa65bfd | 2915 | /** |
3b85c321 DW |
2916 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
2917 | * @mtd: MTD device structure | |
2918 | * @maxchips: Number of chips to scan for | |
7aa65bfd | 2919 | * |
3b85c321 DW |
2920 | * This is the first phase of the normal nand_scan() function. It |
2921 | * reads the flash ID and sets up MTD fields accordingly. | |
7aa65bfd | 2922 | * |
3b85c321 | 2923 | * The mtd->owner field must be set to the module of the caller. |
7aa65bfd | 2924 | */ |
3b85c321 | 2925 | int nand_scan_ident(struct mtd_info *mtd, int maxchips) |
7aa65bfd TG |
2926 | { |
2927 | int i, busw, nand_maf_id; | |
ace4dfee | 2928 | struct nand_chip *chip = mtd->priv; |
7aa65bfd TG |
2929 | struct nand_flash_dev *type; |
2930 | ||
7aa65bfd | 2931 | /* Get buswidth to select the correct functions */ |
ace4dfee | 2932 | busw = chip->options & NAND_BUSWIDTH_16; |
7aa65bfd | 2933 | /* Set the default functions */ |
ace4dfee | 2934 | nand_set_defaults(chip, busw); |
7aa65bfd TG |
2935 | |
2936 | /* Read the flash type */ | |
ace4dfee | 2937 | type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id); |
7aa65bfd TG |
2938 | |
2939 | if (IS_ERR(type)) { | |
b1c6e6db BD |
2940 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
2941 | printk(KERN_WARNING "No NAND device found.\n"); | |
ace4dfee | 2942 | chip->select_chip(mtd, -1); |
7aa65bfd | 2943 | return PTR_ERR(type); |
1da177e4 LT |
2944 | } |
2945 | ||
7aa65bfd | 2946 | /* Check for a chip array */ |
e0c7d767 | 2947 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 2948 | chip->select_chip(mtd, i); |
ef89a880 KB |
2949 | /* See comment in nand_get_flash_type for reset */ |
2950 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1da177e4 | 2951 | /* Send the command for reading device ID */ |
ace4dfee | 2952 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 2953 | /* Read manufacturer and device IDs */ |
ace4dfee TG |
2954 | if (nand_maf_id != chip->read_byte(mtd) || |
2955 | type->id != chip->read_byte(mtd)) | |
1da177e4 LT |
2956 | break; |
2957 | } | |
2958 | if (i > 1) | |
2959 | printk(KERN_INFO "%d NAND chips detected\n", i); | |
61b03bd7 | 2960 | |
1da177e4 | 2961 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
2962 | chip->numchips = i; |
2963 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 2964 | |
3b85c321 DW |
2965 | return 0; |
2966 | } | |
2967 | ||
2968 | ||
2969 | /** | |
2970 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
2971 | * @mtd: MTD device structure | |
3b85c321 DW |
2972 | * |
2973 | * This is the second phase of the normal nand_scan() function. It | |
2974 | * fills out all the uninitialized function pointers with the defaults | |
2975 | * and scans for a bad block table if appropriate. | |
2976 | */ | |
2977 | int nand_scan_tail(struct mtd_info *mtd) | |
2978 | { | |
2979 | int i; | |
2980 | struct nand_chip *chip = mtd->priv; | |
2981 | ||
4bf63fcb DW |
2982 | if (!(chip->options & NAND_OWN_BUFFERS)) |
2983 | chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); | |
2984 | if (!chip->buffers) | |
2985 | return -ENOMEM; | |
2986 | ||
7dcdcbef | 2987 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 2988 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 2989 | |
7aa65bfd TG |
2990 | /* |
2991 | * If no default placement scheme is given, select an appropriate one | |
2992 | */ | |
5bd34c09 | 2993 | if (!chip->ecc.layout) { |
61b03bd7 | 2994 | switch (mtd->oobsize) { |
1da177e4 | 2995 | case 8: |
5bd34c09 | 2996 | chip->ecc.layout = &nand_oob_8; |
1da177e4 LT |
2997 | break; |
2998 | case 16: | |
5bd34c09 | 2999 | chip->ecc.layout = &nand_oob_16; |
1da177e4 LT |
3000 | break; |
3001 | case 64: | |
5bd34c09 | 3002 | chip->ecc.layout = &nand_oob_64; |
1da177e4 | 3003 | break; |
81ec5364 TG |
3004 | case 128: |
3005 | chip->ecc.layout = &nand_oob_128; | |
3006 | break; | |
1da177e4 | 3007 | default: |
7aa65bfd TG |
3008 | printk(KERN_WARNING "No oob scheme defined for " |
3009 | "oobsize %d\n", mtd->oobsize); | |
1da177e4 LT |
3010 | BUG(); |
3011 | } | |
3012 | } | |
61b03bd7 | 3013 | |
956e944c DW |
3014 | if (!chip->write_page) |
3015 | chip->write_page = nand_write_page; | |
3016 | ||
61b03bd7 | 3017 | /* |
7aa65bfd TG |
3018 | * check ECC mode, default to software if 3byte/512byte hardware ECC is |
3019 | * selected and we have 256 byte pagesize fallback to software ECC | |
e0c7d767 | 3020 | */ |
956e944c | 3021 | |
ace4dfee | 3022 | switch (chip->ecc.mode) { |
6e0cb135 SN |
3023 | case NAND_ECC_HW_OOB_FIRST: |
3024 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
3025 | if (!chip->ecc.calculate || !chip->ecc.correct || | |
3026 | !chip->ecc.hwctl) { | |
3027 | printk(KERN_WARNING "No ECC functions supplied; " | |
3028 | "Hardware ECC not possible\n"); | |
3029 | BUG(); | |
3030 | } | |
3031 | if (!chip->ecc.read_page) | |
3032 | chip->ecc.read_page = nand_read_page_hwecc_oob_first; | |
3033 | ||
6dfc6d25 | 3034 | case NAND_ECC_HW: |
f5bbdacc TG |
3035 | /* Use standard hwecc read page function ? */ |
3036 | if (!chip->ecc.read_page) | |
3037 | chip->ecc.read_page = nand_read_page_hwecc; | |
f75e5097 TG |
3038 | if (!chip->ecc.write_page) |
3039 | chip->ecc.write_page = nand_write_page_hwecc; | |
52ff49df DB |
3040 | if (!chip->ecc.read_page_raw) |
3041 | chip->ecc.read_page_raw = nand_read_page_raw; | |
3042 | if (!chip->ecc.write_page_raw) | |
3043 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b TG |
3044 | if (!chip->ecc.read_oob) |
3045 | chip->ecc.read_oob = nand_read_oob_std; | |
3046 | if (!chip->ecc.write_oob) | |
3047 | chip->ecc.write_oob = nand_write_oob_std; | |
f5bbdacc | 3048 | |
6dfc6d25 | 3049 | case NAND_ECC_HW_SYNDROME: |
78b65179 SW |
3050 | if ((!chip->ecc.calculate || !chip->ecc.correct || |
3051 | !chip->ecc.hwctl) && | |
3052 | (!chip->ecc.read_page || | |
1c45f604 | 3053 | chip->ecc.read_page == nand_read_page_hwecc || |
78b65179 | 3054 | !chip->ecc.write_page || |
1c45f604 | 3055 | chip->ecc.write_page == nand_write_page_hwecc)) { |
6e0cb135 | 3056 | printk(KERN_WARNING "No ECC functions supplied; " |
6dfc6d25 TG |
3057 | "Hardware ECC not possible\n"); |
3058 | BUG(); | |
3059 | } | |
f75e5097 | 3060 | /* Use standard syndrome read/write page function ? */ |
f5bbdacc TG |
3061 | if (!chip->ecc.read_page) |
3062 | chip->ecc.read_page = nand_read_page_syndrome; | |
f75e5097 TG |
3063 | if (!chip->ecc.write_page) |
3064 | chip->ecc.write_page = nand_write_page_syndrome; | |
52ff49df DB |
3065 | if (!chip->ecc.read_page_raw) |
3066 | chip->ecc.read_page_raw = nand_read_page_raw_syndrome; | |
3067 | if (!chip->ecc.write_page_raw) | |
3068 | chip->ecc.write_page_raw = nand_write_page_raw_syndrome; | |
7bc3312b TG |
3069 | if (!chip->ecc.read_oob) |
3070 | chip->ecc.read_oob = nand_read_oob_syndrome; | |
3071 | if (!chip->ecc.write_oob) | |
3072 | chip->ecc.write_oob = nand_write_oob_syndrome; | |
f5bbdacc | 3073 | |
ace4dfee | 3074 | if (mtd->writesize >= chip->ecc.size) |
6dfc6d25 TG |
3075 | break; |
3076 | printk(KERN_WARNING "%d byte HW ECC not possible on " | |
3077 | "%d byte page size, fallback to SW ECC\n", | |
ace4dfee TG |
3078 | chip->ecc.size, mtd->writesize); |
3079 | chip->ecc.mode = NAND_ECC_SOFT; | |
61b03bd7 | 3080 | |
6dfc6d25 | 3081 | case NAND_ECC_SOFT: |
ace4dfee TG |
3082 | chip->ecc.calculate = nand_calculate_ecc; |
3083 | chip->ecc.correct = nand_correct_data; | |
f5bbdacc | 3084 | chip->ecc.read_page = nand_read_page_swecc; |
3d459559 | 3085 | chip->ecc.read_subpage = nand_read_subpage; |
f75e5097 | 3086 | chip->ecc.write_page = nand_write_page_swecc; |
52ff49df DB |
3087 | chip->ecc.read_page_raw = nand_read_page_raw; |
3088 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b TG |
3089 | chip->ecc.read_oob = nand_read_oob_std; |
3090 | chip->ecc.write_oob = nand_write_oob_std; | |
9a73290d SV |
3091 | if (!chip->ecc.size) |
3092 | chip->ecc.size = 256; | |
ace4dfee | 3093 | chip->ecc.bytes = 3; |
1da177e4 | 3094 | break; |
61b03bd7 TG |
3095 | |
3096 | case NAND_ECC_NONE: | |
7aa65bfd TG |
3097 | printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. " |
3098 | "This is not recommended !!\n"); | |
8593fbc6 TG |
3099 | chip->ecc.read_page = nand_read_page_raw; |
3100 | chip->ecc.write_page = nand_write_page_raw; | |
7bc3312b | 3101 | chip->ecc.read_oob = nand_read_oob_std; |
52ff49df DB |
3102 | chip->ecc.read_page_raw = nand_read_page_raw; |
3103 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b | 3104 | chip->ecc.write_oob = nand_write_oob_std; |
ace4dfee TG |
3105 | chip->ecc.size = mtd->writesize; |
3106 | chip->ecc.bytes = 0; | |
1da177e4 | 3107 | break; |
956e944c | 3108 | |
1da177e4 | 3109 | default: |
7aa65bfd | 3110 | printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n", |
ace4dfee | 3111 | chip->ecc.mode); |
61b03bd7 | 3112 | BUG(); |
1da177e4 | 3113 | } |
61b03bd7 | 3114 | |
5bd34c09 TG |
3115 | /* |
3116 | * The number of bytes available for a client to place data into | |
3117 | * the out of band area | |
3118 | */ | |
3119 | chip->ecc.layout->oobavail = 0; | |
81d19b04 DB |
3120 | for (i = 0; chip->ecc.layout->oobfree[i].length |
3121 | && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++) | |
5bd34c09 TG |
3122 | chip->ecc.layout->oobavail += |
3123 | chip->ecc.layout->oobfree[i].length; | |
1f92267c | 3124 | mtd->oobavail = chip->ecc.layout->oobavail; |
5bd34c09 | 3125 | |
7aa65bfd TG |
3126 | /* |
3127 | * Set the number of read / write steps for one page depending on ECC | |
3128 | * mode | |
3129 | */ | |
ace4dfee TG |
3130 | chip->ecc.steps = mtd->writesize / chip->ecc.size; |
3131 | if(chip->ecc.steps * chip->ecc.size != mtd->writesize) { | |
6dfc6d25 TG |
3132 | printk(KERN_WARNING "Invalid ecc parameters\n"); |
3133 | BUG(); | |
1da177e4 | 3134 | } |
f5bbdacc | 3135 | chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; |
61b03bd7 | 3136 | |
29072b96 TG |
3137 | /* |
3138 | * Allow subpage writes up to ecc.steps. Not possible for MLC | |
3139 | * FLASH. | |
3140 | */ | |
3141 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && | |
3142 | !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { | |
3143 | switch(chip->ecc.steps) { | |
3144 | case 2: | |
3145 | mtd->subpage_sft = 1; | |
3146 | break; | |
3147 | case 4: | |
3148 | case 8: | |
81ec5364 | 3149 | case 16: |
29072b96 TG |
3150 | mtd->subpage_sft = 2; |
3151 | break; | |
3152 | } | |
3153 | } | |
3154 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
3155 | ||
04bbd0ea | 3156 | /* Initialize state */ |
ace4dfee | 3157 | chip->state = FL_READY; |
1da177e4 LT |
3158 | |
3159 | /* De-select the device */ | |
ace4dfee | 3160 | chip->select_chip(mtd, -1); |
1da177e4 LT |
3161 | |
3162 | /* Invalidate the pagebuffer reference */ | |
ace4dfee | 3163 | chip->pagebuf = -1; |
1da177e4 LT |
3164 | |
3165 | /* Fill in remaining MTD driver data */ | |
3166 | mtd->type = MTD_NANDFLASH; | |
5fa43394 | 3167 | mtd->flags = MTD_CAP_NANDFLASH; |
1da177e4 LT |
3168 | mtd->erase = nand_erase; |
3169 | mtd->point = NULL; | |
3170 | mtd->unpoint = NULL; | |
3171 | mtd->read = nand_read; | |
3172 | mtd->write = nand_write; | |
2af7c653 | 3173 | mtd->panic_write = panic_nand_write; |
1da177e4 LT |
3174 | mtd->read_oob = nand_read_oob; |
3175 | mtd->write_oob = nand_write_oob; | |
1da177e4 LT |
3176 | mtd->sync = nand_sync; |
3177 | mtd->lock = NULL; | |
3178 | mtd->unlock = NULL; | |
962034f4 VW |
3179 | mtd->suspend = nand_suspend; |
3180 | mtd->resume = nand_resume; | |
1da177e4 LT |
3181 | mtd->block_isbad = nand_block_isbad; |
3182 | mtd->block_markbad = nand_block_markbad; | |
3183 | ||
5bd34c09 TG |
3184 | /* propagate ecc.layout to mtd_info */ |
3185 | mtd->ecclayout = chip->ecc.layout; | |
1da177e4 | 3186 | |
0040bf38 | 3187 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 3188 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 3189 | return 0; |
1da177e4 LT |
3190 | |
3191 | /* Build bad block table */ | |
ace4dfee | 3192 | return chip->scan_bbt(mtd); |
1da177e4 LT |
3193 | } |
3194 | ||
a6e6abd5 | 3195 | /* is_module_text_address() isn't exported, and it's mostly a pointless |
3b85c321 DW |
3196 | test if this is a module _anyway_ -- they'd have to try _really_ hard |
3197 | to call us from in-kernel code if the core NAND support is modular. */ | |
3198 | #ifdef MODULE | |
3199 | #define caller_is_module() (1) | |
3200 | #else | |
3201 | #define caller_is_module() \ | |
a6e6abd5 | 3202 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
3203 | #endif |
3204 | ||
3205 | /** | |
3206 | * nand_scan - [NAND Interface] Scan for the NAND device | |
3207 | * @mtd: MTD device structure | |
3208 | * @maxchips: Number of chips to scan for | |
3209 | * | |
3210 | * This fills out all the uninitialized function pointers | |
3211 | * with the defaults. | |
3212 | * The flash ID is read and the mtd/chip structures are | |
3213 | * filled with the appropriate values. | |
3214 | * The mtd->owner field must be set to the module of the caller | |
3215 | * | |
3216 | */ | |
3217 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
3218 | { | |
3219 | int ret; | |
3220 | ||
3221 | /* Many callers got this wrong, so check for it for a while... */ | |
3222 | if (!mtd->owner && caller_is_module()) { | |
20d8e248 | 3223 | printk(KERN_CRIT "%s called with NULL mtd->owner!\n", |
3224 | __func__); | |
3b85c321 DW |
3225 | BUG(); |
3226 | } | |
3227 | ||
3228 | ret = nand_scan_ident(mtd, maxchips); | |
3229 | if (!ret) | |
3230 | ret = nand_scan_tail(mtd); | |
3231 | return ret; | |
3232 | } | |
3233 | ||
1da177e4 | 3234 | /** |
61b03bd7 | 3235 | * nand_release - [NAND Interface] Free resources held by the NAND device |
1da177e4 LT |
3236 | * @mtd: MTD device structure |
3237 | */ | |
e0c7d767 | 3238 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 3239 | { |
ace4dfee | 3240 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
3241 | |
3242 | #ifdef CONFIG_MTD_PARTITIONS | |
3243 | /* Deregister partitions */ | |
e0c7d767 | 3244 | del_mtd_partitions(mtd); |
1da177e4 LT |
3245 | #endif |
3246 | /* Deregister the device */ | |
e0c7d767 | 3247 | del_mtd_device(mtd); |
1da177e4 | 3248 | |
fa671646 | 3249 | /* Free bad block table memory */ |
ace4dfee | 3250 | kfree(chip->bbt); |
4bf63fcb DW |
3251 | if (!(chip->options & NAND_OWN_BUFFERS)) |
3252 | kfree(chip->buffers); | |
1da177e4 LT |
3253 | } |
3254 | ||
7d70f334 VS |
3255 | EXPORT_SYMBOL_GPL(nand_lock); |
3256 | EXPORT_SYMBOL_GPL(nand_unlock); | |
e0c7d767 | 3257 | EXPORT_SYMBOL_GPL(nand_scan); |
3b85c321 DW |
3258 | EXPORT_SYMBOL_GPL(nand_scan_ident); |
3259 | EXPORT_SYMBOL_GPL(nand_scan_tail); | |
e0c7d767 | 3260 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 RP |
3261 | |
3262 | static int __init nand_base_init(void) | |
3263 | { | |
3264 | led_trigger_register_simple("nand-disk", &nand_led_trigger); | |
3265 | return 0; | |
3266 | } | |
3267 | ||
3268 | static void __exit nand_base_exit(void) | |
3269 | { | |
3270 | led_trigger_unregister_simple(nand_led_trigger); | |
3271 | } | |
3272 | ||
3273 | module_init(nand_base_init); | |
3274 | module_exit(nand_base_exit); | |
3275 | ||
e0c7d767 DW |
3276 | MODULE_LICENSE("GPL"); |
3277 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>"); | |
3278 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |