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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand.c | |
3 | * | |
4 | * Overview: | |
5 | * This is the generic MTD driver for NAND flash devices. It should be | |
6 | * capable of working with almost all NAND chips currently available. | |
7 | * Basic support for AG-AND chips is provided. | |
61b03bd7 | 8 | * |
1da177e4 LT |
9 | * Additional technical information is available on |
10 | * http://www.linux-mtd.infradead.org/tech/nand.html | |
61b03bd7 | 11 | * |
1da177e4 | 12 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 13 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 14 | * |
ace4dfee | 15 | * Credits: |
61b03bd7 TG |
16 | * David Woodhouse for adding multichip support |
17 | * | |
1da177e4 LT |
18 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
19 | * rework for 2K page size chips | |
20 | * | |
ace4dfee | 21 | * TODO: |
1da177e4 LT |
22 | * Enable cached programming for 2k page size chips |
23 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
24 | * if we have HW ecc support. | |
25 | * The AG-AND chips have nice features for speed improvement, | |
26 | * which are not supported yet. Read / program 4 pages in one go. | |
27 | * | |
1da177e4 LT |
28 | * This program is free software; you can redistribute it and/or modify |
29 | * it under the terms of the GNU General Public License version 2 as | |
30 | * published by the Free Software Foundation. | |
31 | * | |
32 | */ | |
33 | ||
552d9205 | 34 | #include <linux/module.h> |
1da177e4 LT |
35 | #include <linux/delay.h> |
36 | #include <linux/errno.h> | |
7aa65bfd | 37 | #include <linux/err.h> |
1da177e4 LT |
38 | #include <linux/sched.h> |
39 | #include <linux/slab.h> | |
40 | #include <linux/types.h> | |
41 | #include <linux/mtd/mtd.h> | |
42 | #include <linux/mtd/nand.h> | |
43 | #include <linux/mtd/nand_ecc.h> | |
44 | #include <linux/mtd/compatmac.h> | |
45 | #include <linux/interrupt.h> | |
46 | #include <linux/bitops.h> | |
8fe833c1 | 47 | #include <linux/leds.h> |
1da177e4 LT |
48 | #include <asm/io.h> |
49 | ||
50 | #ifdef CONFIG_MTD_PARTITIONS | |
51 | #include <linux/mtd/partitions.h> | |
52 | #endif | |
53 | ||
54 | /* Define default oob placement schemes for large and small page devices */ | |
55 | static struct nand_oobinfo nand_oob_8 = { | |
56 | .useecc = MTD_NANDECC_AUTOPLACE, | |
57 | .eccbytes = 3, | |
58 | .eccpos = {0, 1, 2}, | |
e0c7d767 | 59 | .oobfree = {{3, 2}, {6, 2}} |
1da177e4 LT |
60 | }; |
61 | ||
62 | static struct nand_oobinfo nand_oob_16 = { | |
63 | .useecc = MTD_NANDECC_AUTOPLACE, | |
64 | .eccbytes = 6, | |
65 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
e0c7d767 | 66 | .oobfree = {{8, 8}} |
1da177e4 LT |
67 | }; |
68 | ||
69 | static struct nand_oobinfo nand_oob_64 = { | |
70 | .useecc = MTD_NANDECC_AUTOPLACE, | |
71 | .eccbytes = 24, | |
72 | .eccpos = { | |
e0c7d767 DW |
73 | 40, 41, 42, 43, 44, 45, 46, 47, |
74 | 48, 49, 50, 51, 52, 53, 54, 55, | |
75 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
76 | .oobfree = {{2, 38}} | |
1da177e4 LT |
77 | }; |
78 | ||
79 | /* This is used for padding purposes in nand_write_oob */ | |
58dd8f2b | 80 | static uint8_t ffchars[] = { |
1da177e4 LT |
81 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, |
82 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
83 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
84 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
85 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
86 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
87 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
88 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
89 | }; | |
90 | ||
2c0a2bed | 91 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, size_t len, |
58dd8f2b | 92 | size_t *retlen, const uint8_t *buf); |
ace4dfee | 93 | static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, |
2c0a2bed | 94 | int new_state); |
1da177e4 | 95 | |
d470a97c TG |
96 | /* |
97 | * For devices which display every fart in the system on a seperate LED. Is | |
98 | * compiled away when LED support is disabled. | |
99 | */ | |
100 | DEFINE_LED_TRIGGER(nand_led_trigger); | |
101 | ||
1da177e4 LT |
102 | /** |
103 | * nand_release_device - [GENERIC] release chip | |
104 | * @mtd: MTD device structure | |
61b03bd7 TG |
105 | * |
106 | * Deselect, release chip lock and wake up anyone waiting on the device | |
1da177e4 | 107 | */ |
e0c7d767 | 108 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 109 | { |
ace4dfee | 110 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
111 | |
112 | /* De-select the NAND device */ | |
ace4dfee | 113 | chip->select_chip(mtd, -1); |
0dfc6246 | 114 | |
a36ed299 | 115 | /* Release the controller and the chip */ |
ace4dfee TG |
116 | spin_lock(&chip->controller->lock); |
117 | chip->controller->active = NULL; | |
118 | chip->state = FL_READY; | |
119 | wake_up(&chip->controller->wq); | |
120 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
121 | } |
122 | ||
123 | /** | |
124 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
125 | * @mtd: MTD device structure | |
126 | * | |
127 | * Default read function for 8bit buswith | |
128 | */ | |
58dd8f2b | 129 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 130 | { |
ace4dfee TG |
131 | struct nand_chip *chip = mtd->priv; |
132 | return readb(chip->IO_ADDR_R); | |
1da177e4 LT |
133 | } |
134 | ||
1da177e4 LT |
135 | /** |
136 | * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip | |
137 | * @mtd: MTD device structure | |
138 | * | |
61b03bd7 | 139 | * Default read function for 16bit buswith with |
1da177e4 LT |
140 | * endianess conversion |
141 | */ | |
58dd8f2b | 142 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 143 | { |
ace4dfee TG |
144 | struct nand_chip *chip = mtd->priv; |
145 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); | |
1da177e4 LT |
146 | } |
147 | ||
1da177e4 LT |
148 | /** |
149 | * nand_read_word - [DEFAULT] read one word from the chip | |
150 | * @mtd: MTD device structure | |
151 | * | |
61b03bd7 | 152 | * Default read function for 16bit buswith without |
1da177e4 LT |
153 | * endianess conversion |
154 | */ | |
155 | static u16 nand_read_word(struct mtd_info *mtd) | |
156 | { | |
ace4dfee TG |
157 | struct nand_chip *chip = mtd->priv; |
158 | return readw(chip->IO_ADDR_R); | |
1da177e4 LT |
159 | } |
160 | ||
1da177e4 LT |
161 | /** |
162 | * nand_select_chip - [DEFAULT] control CE line | |
163 | * @mtd: MTD device structure | |
164 | * @chip: chipnumber to select, -1 for deselect | |
165 | * | |
166 | * Default select function for 1 chip devices. | |
167 | */ | |
ace4dfee | 168 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 169 | { |
ace4dfee TG |
170 | struct nand_chip *chip = mtd->priv; |
171 | ||
172 | switch (chipnr) { | |
1da177e4 | 173 | case -1: |
ace4dfee | 174 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
175 | break; |
176 | case 0: | |
ace4dfee TG |
177 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, |
178 | NAND_NCE | NAND_CTRL_CHANGE); | |
1da177e4 LT |
179 | break; |
180 | ||
181 | default: | |
182 | BUG(); | |
183 | } | |
184 | } | |
185 | ||
186 | /** | |
187 | * nand_write_buf - [DEFAULT] write buffer to chip | |
188 | * @mtd: MTD device structure | |
189 | * @buf: data buffer | |
190 | * @len: number of bytes to write | |
191 | * | |
192 | * Default write function for 8bit buswith | |
193 | */ | |
58dd8f2b | 194 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
195 | { |
196 | int i; | |
ace4dfee | 197 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 198 | |
e0c7d767 | 199 | for (i = 0; i < len; i++) |
ace4dfee | 200 | writeb(buf[i], chip->IO_ADDR_W); |
1da177e4 LT |
201 | } |
202 | ||
203 | /** | |
61b03bd7 | 204 | * nand_read_buf - [DEFAULT] read chip data into buffer |
1da177e4 LT |
205 | * @mtd: MTD device structure |
206 | * @buf: buffer to store date | |
207 | * @len: number of bytes to read | |
208 | * | |
209 | * Default read function for 8bit buswith | |
210 | */ | |
58dd8f2b | 211 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
212 | { |
213 | int i; | |
ace4dfee | 214 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 215 | |
e0c7d767 | 216 | for (i = 0; i < len; i++) |
ace4dfee | 217 | buf[i] = readb(chip->IO_ADDR_R); |
1da177e4 LT |
218 | } |
219 | ||
220 | /** | |
61b03bd7 | 221 | * nand_verify_buf - [DEFAULT] Verify chip data against buffer |
1da177e4 LT |
222 | * @mtd: MTD device structure |
223 | * @buf: buffer containing the data to compare | |
224 | * @len: number of bytes to compare | |
225 | * | |
226 | * Default verify function for 8bit buswith | |
227 | */ | |
58dd8f2b | 228 | static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
229 | { |
230 | int i; | |
ace4dfee | 231 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 232 | |
e0c7d767 | 233 | for (i = 0; i < len; i++) |
ace4dfee | 234 | if (buf[i] != readb(chip->IO_ADDR_R)) |
1da177e4 | 235 | return -EFAULT; |
1da177e4 LT |
236 | return 0; |
237 | } | |
238 | ||
239 | /** | |
240 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
241 | * @mtd: MTD device structure | |
242 | * @buf: data buffer | |
243 | * @len: number of bytes to write | |
244 | * | |
245 | * Default write function for 16bit buswith | |
246 | */ | |
58dd8f2b | 247 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
248 | { |
249 | int i; | |
ace4dfee | 250 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
251 | u16 *p = (u16 *) buf; |
252 | len >>= 1; | |
61b03bd7 | 253 | |
e0c7d767 | 254 | for (i = 0; i < len; i++) |
ace4dfee | 255 | writew(p[i], chip->IO_ADDR_W); |
61b03bd7 | 256 | |
1da177e4 LT |
257 | } |
258 | ||
259 | /** | |
61b03bd7 | 260 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
1da177e4 LT |
261 | * @mtd: MTD device structure |
262 | * @buf: buffer to store date | |
263 | * @len: number of bytes to read | |
264 | * | |
265 | * Default read function for 16bit buswith | |
266 | */ | |
58dd8f2b | 267 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
268 | { |
269 | int i; | |
ace4dfee | 270 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
271 | u16 *p = (u16 *) buf; |
272 | len >>= 1; | |
273 | ||
e0c7d767 | 274 | for (i = 0; i < len; i++) |
ace4dfee | 275 | p[i] = readw(chip->IO_ADDR_R); |
1da177e4 LT |
276 | } |
277 | ||
278 | /** | |
61b03bd7 | 279 | * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer |
1da177e4 LT |
280 | * @mtd: MTD device structure |
281 | * @buf: buffer containing the data to compare | |
282 | * @len: number of bytes to compare | |
283 | * | |
284 | * Default verify function for 16bit buswith | |
285 | */ | |
58dd8f2b | 286 | static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
287 | { |
288 | int i; | |
ace4dfee | 289 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
290 | u16 *p = (u16 *) buf; |
291 | len >>= 1; | |
292 | ||
e0c7d767 | 293 | for (i = 0; i < len; i++) |
ace4dfee | 294 | if (p[i] != readw(chip->IO_ADDR_R)) |
1da177e4 LT |
295 | return -EFAULT; |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
300 | /** | |
301 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
302 | * @mtd: MTD device structure | |
303 | * @ofs: offset from device start | |
304 | * @getchip: 0, if the chip is already selected | |
305 | * | |
61b03bd7 | 306 | * Check, if the block is bad. |
1da177e4 LT |
307 | */ |
308 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) | |
309 | { | |
310 | int page, chipnr, res = 0; | |
ace4dfee | 311 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
312 | u16 bad; |
313 | ||
314 | if (getchip) { | |
ace4dfee TG |
315 | page = (int)(ofs >> chip->page_shift); |
316 | chipnr = (int)(ofs >> chip->chip_shift); | |
1da177e4 | 317 | |
ace4dfee | 318 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 LT |
319 | |
320 | /* Select the NAND device */ | |
ace4dfee | 321 | chip->select_chip(mtd, chipnr); |
61b03bd7 | 322 | } else |
e0c7d767 | 323 | page = (int)ofs; |
1da177e4 | 324 | |
ace4dfee TG |
325 | if (chip->options & NAND_BUSWIDTH_16) { |
326 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE, | |
327 | page & chip->pagemask); | |
328 | bad = cpu_to_le16(chip->read_word(mtd)); | |
329 | if (chip->badblockpos & 0x1) | |
49196f33 | 330 | bad >>= 8; |
1da177e4 LT |
331 | if ((bad & 0xFF) != 0xff) |
332 | res = 1; | |
333 | } else { | |
ace4dfee TG |
334 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, |
335 | page & chip->pagemask); | |
336 | if (chip->read_byte(mtd) != 0xff) | |
1da177e4 LT |
337 | res = 1; |
338 | } | |
61b03bd7 | 339 | |
ace4dfee | 340 | if (getchip) |
1da177e4 | 341 | nand_release_device(mtd); |
61b03bd7 | 342 | |
1da177e4 LT |
343 | return res; |
344 | } | |
345 | ||
346 | /** | |
347 | * nand_default_block_markbad - [DEFAULT] mark a block bad | |
348 | * @mtd: MTD device structure | |
349 | * @ofs: offset from device start | |
350 | * | |
351 | * This is the default implementation, which can be overridden by | |
352 | * a hardware specific driver. | |
353 | */ | |
354 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
355 | { | |
ace4dfee | 356 | struct nand_chip *chip = mtd->priv; |
58dd8f2b | 357 | uint8_t buf[2] = { 0, 0 }; |
e0c7d767 | 358 | size_t retlen; |
1da177e4 | 359 | int block; |
61b03bd7 | 360 | |
1da177e4 | 361 | /* Get block number */ |
ace4dfee TG |
362 | block = ((int)ofs) >> chip->bbt_erase_shift; |
363 | if (chip->bbt) | |
364 | chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); | |
1da177e4 LT |
365 | |
366 | /* Do we have a flash based bad block table ? */ | |
ace4dfee | 367 | if (chip->options & NAND_USE_FLASH_BBT) |
e0c7d767 | 368 | return nand_update_bbt(mtd, ofs); |
61b03bd7 | 369 | |
1da177e4 | 370 | /* We write two bytes, so we dont have to mess with 16 bit access */ |
ace4dfee | 371 | ofs += mtd->oobsize + (chip->badblockpos & ~0x01); |
e0c7d767 | 372 | return nand_write_oob(mtd, ofs, 2, &retlen, buf); |
1da177e4 LT |
373 | } |
374 | ||
61b03bd7 | 375 | /** |
1da177e4 LT |
376 | * nand_check_wp - [GENERIC] check if the chip is write protected |
377 | * @mtd: MTD device structure | |
61b03bd7 | 378 | * Check, if the device is write protected |
1da177e4 | 379 | * |
61b03bd7 | 380 | * The function expects, that the device is already selected |
1da177e4 | 381 | */ |
e0c7d767 | 382 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 383 | { |
ace4dfee | 384 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 385 | /* Check the WP bit */ |
ace4dfee TG |
386 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
387 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
388 | } |
389 | ||
390 | /** | |
391 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
392 | * @mtd: MTD device structure | |
393 | * @ofs: offset from device start | |
394 | * @getchip: 0, if the chip is already selected | |
395 | * @allowbbt: 1, if its allowed to access the bbt area | |
396 | * | |
397 | * Check, if the block is bad. Either by reading the bad block table or | |
398 | * calling of the scan function. | |
399 | */ | |
2c0a2bed TG |
400 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, |
401 | int allowbbt) | |
1da177e4 | 402 | { |
ace4dfee | 403 | struct nand_chip *chip = mtd->priv; |
61b03bd7 | 404 | |
ace4dfee TG |
405 | if (!chip->bbt) |
406 | return chip->block_bad(mtd, ofs, getchip); | |
61b03bd7 | 407 | |
1da177e4 | 408 | /* Return info from the table */ |
e0c7d767 | 409 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
410 | } |
411 | ||
61b03bd7 | 412 | /* |
3b88775c TG |
413 | * Wait for the ready pin, after a command |
414 | * The timeout is catched later. | |
415 | */ | |
416 | static void nand_wait_ready(struct mtd_info *mtd) | |
417 | { | |
ace4dfee | 418 | struct nand_chip *chip = mtd->priv; |
e0c7d767 | 419 | unsigned long timeo = jiffies + 2; |
3b88775c | 420 | |
8fe833c1 | 421 | led_trigger_event(nand_led_trigger, LED_FULL); |
3b88775c TG |
422 | /* wait until command is processed or timeout occures */ |
423 | do { | |
ace4dfee | 424 | if (chip->dev_ready(mtd)) |
8fe833c1 | 425 | break; |
8446f1d3 | 426 | touch_softlockup_watchdog(); |
61b03bd7 | 427 | } while (time_before(jiffies, timeo)); |
8fe833c1 | 428 | led_trigger_event(nand_led_trigger, LED_OFF); |
3b88775c TG |
429 | } |
430 | ||
1da177e4 LT |
431 | /** |
432 | * nand_command - [DEFAULT] Send command to NAND device | |
433 | * @mtd: MTD device structure | |
434 | * @command: the command to be sent | |
435 | * @column: the column address for this command, -1 if none | |
436 | * @page_addr: the page address for this command, -1 if none | |
437 | * | |
438 | * Send command to NAND device. This function is used for small page | |
439 | * devices (256/512 Bytes per page) | |
440 | */ | |
7abd3ef9 TG |
441 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
442 | int column, int page_addr) | |
1da177e4 | 443 | { |
ace4dfee | 444 | register struct nand_chip *chip = mtd->priv; |
7abd3ef9 | 445 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 446 | |
1da177e4 LT |
447 | /* |
448 | * Write out the command to the device. | |
449 | */ | |
450 | if (command == NAND_CMD_SEQIN) { | |
451 | int readcmd; | |
452 | ||
28318776 | 453 | if (column >= mtd->writesize) { |
1da177e4 | 454 | /* OOB area */ |
28318776 | 455 | column -= mtd->writesize; |
1da177e4 LT |
456 | readcmd = NAND_CMD_READOOB; |
457 | } else if (column < 256) { | |
458 | /* First 256 bytes --> READ0 */ | |
459 | readcmd = NAND_CMD_READ0; | |
460 | } else { | |
461 | column -= 256; | |
462 | readcmd = NAND_CMD_READ1; | |
463 | } | |
ace4dfee | 464 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 465 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 466 | } |
ace4dfee | 467 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 468 | |
7abd3ef9 TG |
469 | /* |
470 | * Address cycle, when necessary | |
471 | */ | |
472 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; | |
473 | /* Serially input address */ | |
474 | if (column != -1) { | |
475 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 476 | if (chip->options & NAND_BUSWIDTH_16) |
7abd3ef9 | 477 | column >>= 1; |
ace4dfee | 478 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
479 | ctrl &= ~NAND_CTRL_CHANGE; |
480 | } | |
481 | if (page_addr != -1) { | |
ace4dfee | 482 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 483 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 484 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 485 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
486 | if (chip->chipsize > (32 << 20)) |
487 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 488 | } |
ace4dfee | 489 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
490 | |
491 | /* | |
492 | * program and erase have their own busy handlers | |
1da177e4 | 493 | * status and sequential in needs no delay |
e0c7d767 | 494 | */ |
1da177e4 | 495 | switch (command) { |
61b03bd7 | 496 | |
1da177e4 LT |
497 | case NAND_CMD_PAGEPROG: |
498 | case NAND_CMD_ERASE1: | |
499 | case NAND_CMD_ERASE2: | |
500 | case NAND_CMD_SEQIN: | |
501 | case NAND_CMD_STATUS: | |
ace4dfee | 502 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE); |
1da177e4 LT |
503 | return; |
504 | ||
505 | case NAND_CMD_RESET: | |
ace4dfee | 506 | if (chip->dev_ready) |
1da177e4 | 507 | break; |
ace4dfee TG |
508 | udelay(chip->chip_delay); |
509 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 510 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
511 | chip->cmd_ctrl(mtd, |
512 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
ace4dfee | 513 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; |
1da177e4 LT |
514 | return; |
515 | ||
e0c7d767 | 516 | /* This applies to read commands */ |
1da177e4 | 517 | default: |
61b03bd7 | 518 | /* |
1da177e4 LT |
519 | * If we don't have access to the busy pin, we apply the given |
520 | * command delay | |
e0c7d767 | 521 | */ |
ace4dfee TG |
522 | if (!chip->dev_ready) { |
523 | udelay(chip->chip_delay); | |
1da177e4 | 524 | return; |
61b03bd7 | 525 | } |
1da177e4 | 526 | } |
1da177e4 LT |
527 | /* Apply this short delay always to ensure that we do wait tWB in |
528 | * any case on any machine. */ | |
e0c7d767 | 529 | ndelay(100); |
3b88775c TG |
530 | |
531 | nand_wait_ready(mtd); | |
1da177e4 LT |
532 | } |
533 | ||
534 | /** | |
535 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
536 | * @mtd: MTD device structure | |
537 | * @command: the command to be sent | |
538 | * @column: the column address for this command, -1 if none | |
539 | * @page_addr: the page address for this command, -1 if none | |
540 | * | |
7abd3ef9 TG |
541 | * Send command to NAND device. This is the version for the new large page |
542 | * devices We dont have the separate regions as we have in the small page | |
543 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 LT |
544 | * |
545 | */ | |
7abd3ef9 TG |
546 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
547 | int column, int page_addr) | |
1da177e4 | 548 | { |
ace4dfee | 549 | register struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
550 | |
551 | /* Emulate NAND_CMD_READOOB */ | |
552 | if (command == NAND_CMD_READOOB) { | |
28318776 | 553 | column += mtd->writesize; |
1da177e4 LT |
554 | command = NAND_CMD_READ0; |
555 | } | |
61b03bd7 | 556 | |
7abd3ef9 | 557 | /* Command latch cycle */ |
ace4dfee | 558 | chip->cmd_ctrl(mtd, command & 0xff, |
7abd3ef9 | 559 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
560 | |
561 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 562 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
563 | |
564 | /* Serially input address */ | |
565 | if (column != -1) { | |
566 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 567 | if (chip->options & NAND_BUSWIDTH_16) |
1da177e4 | 568 | column >>= 1; |
ace4dfee | 569 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 570 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 571 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 572 | } |
1da177e4 | 573 | if (page_addr != -1) { |
ace4dfee TG |
574 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
575 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 576 | NAND_NCE | NAND_ALE); |
1da177e4 | 577 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
578 | if (chip->chipsize > (128 << 20)) |
579 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 580 | NAND_NCE | NAND_ALE); |
1da177e4 | 581 | } |
1da177e4 | 582 | } |
ace4dfee | 583 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
584 | |
585 | /* | |
586 | * program and erase have their own busy handlers | |
30f464b7 DM |
587 | * status, sequential in, and deplete1 need no delay |
588 | */ | |
1da177e4 | 589 | switch (command) { |
61b03bd7 | 590 | |
1da177e4 LT |
591 | case NAND_CMD_CACHEDPROG: |
592 | case NAND_CMD_PAGEPROG: | |
593 | case NAND_CMD_ERASE1: | |
594 | case NAND_CMD_ERASE2: | |
595 | case NAND_CMD_SEQIN: | |
596 | case NAND_CMD_STATUS: | |
30f464b7 | 597 | case NAND_CMD_DEPLETE1: |
1da177e4 LT |
598 | return; |
599 | ||
e0c7d767 DW |
600 | /* |
601 | * read error status commands require only a short delay | |
602 | */ | |
30f464b7 DM |
603 | case NAND_CMD_STATUS_ERROR: |
604 | case NAND_CMD_STATUS_ERROR0: | |
605 | case NAND_CMD_STATUS_ERROR1: | |
606 | case NAND_CMD_STATUS_ERROR2: | |
607 | case NAND_CMD_STATUS_ERROR3: | |
ace4dfee | 608 | udelay(chip->chip_delay); |
30f464b7 | 609 | return; |
1da177e4 LT |
610 | |
611 | case NAND_CMD_RESET: | |
ace4dfee | 612 | if (chip->dev_ready) |
1da177e4 | 613 | break; |
ace4dfee | 614 | udelay(chip->chip_delay); |
12efdde3 TG |
615 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
616 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
617 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
618 | NAND_NCE | NAND_CTRL_CHANGE); | |
ace4dfee | 619 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ; |
1da177e4 LT |
620 | return; |
621 | ||
622 | case NAND_CMD_READ0: | |
12efdde3 TG |
623 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
624 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
625 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
626 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 627 | |
e0c7d767 | 628 | /* This applies to read commands */ |
1da177e4 | 629 | default: |
61b03bd7 | 630 | /* |
1da177e4 LT |
631 | * If we don't have access to the busy pin, we apply the given |
632 | * command delay | |
e0c7d767 | 633 | */ |
ace4dfee TG |
634 | if (!chip->dev_ready) { |
635 | udelay(chip->chip_delay); | |
1da177e4 | 636 | return; |
61b03bd7 | 637 | } |
1da177e4 | 638 | } |
3b88775c | 639 | |
1da177e4 LT |
640 | /* Apply this short delay always to ensure that we do wait tWB in |
641 | * any case on any machine. */ | |
e0c7d767 | 642 | ndelay(100); |
3b88775c TG |
643 | |
644 | nand_wait_ready(mtd); | |
1da177e4 LT |
645 | } |
646 | ||
647 | /** | |
648 | * nand_get_device - [GENERIC] Get chip for selected access | |
649 | * @this: the nand chip descriptor | |
650 | * @mtd: MTD device structure | |
61b03bd7 | 651 | * @new_state: the state which is requested |
1da177e4 LT |
652 | * |
653 | * Get the device and lock it for exclusive access | |
654 | */ | |
2c0a2bed | 655 | static int |
ace4dfee | 656 | nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state) |
1da177e4 | 657 | { |
ace4dfee TG |
658 | spinlock_t *lock = &chip->controller->lock; |
659 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 660 | DECLARE_WAITQUEUE(wait, current); |
e0c7d767 | 661 | retry: |
0dfc6246 TG |
662 | spin_lock(lock); |
663 | ||
1da177e4 | 664 | /* Hardware controller shared among independend devices */ |
a36ed299 | 665 | /* Hardware controller shared among independend devices */ |
ace4dfee TG |
666 | if (!chip->controller->active) |
667 | chip->controller->active = chip; | |
a36ed299 | 668 | |
ace4dfee TG |
669 | if (chip->controller->active == chip && chip->state == FL_READY) { |
670 | chip->state = new_state; | |
0dfc6246 | 671 | spin_unlock(lock); |
962034f4 VW |
672 | return 0; |
673 | } | |
674 | if (new_state == FL_PM_SUSPENDED) { | |
675 | spin_unlock(lock); | |
ace4dfee | 676 | return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN; |
0dfc6246 TG |
677 | } |
678 | set_current_state(TASK_UNINTERRUPTIBLE); | |
679 | add_wait_queue(wq, &wait); | |
680 | spin_unlock(lock); | |
681 | schedule(); | |
682 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
683 | goto retry; |
684 | } | |
685 | ||
686 | /** | |
687 | * nand_wait - [DEFAULT] wait until the command is done | |
688 | * @mtd: MTD device structure | |
689 | * @this: NAND chip structure | |
690 | * @state: state to select the max. timeout value | |
691 | * | |
692 | * Wait for command done. This applies to erase and program only | |
61b03bd7 | 693 | * Erase can take up to 400ms and program up to 20ms according to |
1da177e4 LT |
694 | * general NAND and SmartMedia specs |
695 | * | |
696 | */ | |
ace4dfee | 697 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip, int state) |
1da177e4 LT |
698 | { |
699 | ||
e0c7d767 DW |
700 | unsigned long timeo = jiffies; |
701 | int status; | |
61b03bd7 | 702 | |
1da177e4 | 703 | if (state == FL_ERASING) |
e0c7d767 | 704 | timeo += (HZ * 400) / 1000; |
1da177e4 | 705 | else |
e0c7d767 | 706 | timeo += (HZ * 20) / 1000; |
1da177e4 | 707 | |
8fe833c1 RP |
708 | led_trigger_event(nand_led_trigger, LED_FULL); |
709 | ||
1da177e4 LT |
710 | /* Apply this short delay always to ensure that we do wait tWB in |
711 | * any case on any machine. */ | |
e0c7d767 | 712 | ndelay(100); |
1da177e4 | 713 | |
ace4dfee TG |
714 | if ((state == FL_ERASING) && (chip->options & NAND_IS_AND)) |
715 | chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); | |
61b03bd7 | 716 | else |
ace4dfee | 717 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 718 | |
61b03bd7 | 719 | while (time_before(jiffies, timeo)) { |
1da177e4 | 720 | /* Check, if we were interrupted */ |
ace4dfee | 721 | if (chip->state != state) |
1da177e4 LT |
722 | return 0; |
723 | ||
ace4dfee TG |
724 | if (chip->dev_ready) { |
725 | if (chip->dev_ready(mtd)) | |
61b03bd7 | 726 | break; |
1da177e4 | 727 | } else { |
ace4dfee | 728 | if (chip->read_byte(mtd) & NAND_STATUS_READY) |
1da177e4 LT |
729 | break; |
730 | } | |
20a6c211 | 731 | cond_resched(); |
1da177e4 | 732 | } |
8fe833c1 RP |
733 | led_trigger_event(nand_led_trigger, LED_OFF); |
734 | ||
ace4dfee | 735 | status = (int)chip->read_byte(mtd); |
1da177e4 LT |
736 | return status; |
737 | } | |
738 | ||
1da177e4 | 739 | /** |
f5bbdacc TG |
740 | * nand_read_page_swecc - {REPLACABLE] software ecc based page read function |
741 | * @mtd: mtd info structure | |
742 | * @chip: nand chip info structure | |
743 | * @buf: buffer to store read data | |
068e3c0a | 744 | */ |
f5bbdacc TG |
745 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
746 | uint8_t *buf) | |
1da177e4 | 747 | { |
f5bbdacc TG |
748 | int i, eccsize = chip->ecc.size; |
749 | int eccbytes = chip->ecc.bytes; | |
750 | int eccsteps = chip->ecc.steps; | |
751 | uint8_t *p = buf; | |
f75e5097 TG |
752 | uint8_t *ecc_calc = chip->buffers.ecccalc; |
753 | uint8_t *ecc_code = chip->buffers.ecccode; | |
f5bbdacc TG |
754 | int *eccpos = chip->autooob->eccpos; |
755 | ||
756 | chip->read_buf(mtd, buf, mtd->writesize); | |
f75e5097 | 757 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
f5bbdacc TG |
758 | |
759 | if (chip->ecc.mode == NAND_ECC_NONE) | |
760 | return 0; | |
761 | ||
762 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
763 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
764 | ||
765 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 766 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
767 | |
768 | eccsteps = chip->ecc.steps; | |
769 | p = buf; | |
770 | ||
771 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
772 | int stat; | |
773 | ||
774 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
775 | if (stat == -1) | |
776 | mtd->ecc_stats.failed++; | |
777 | else | |
778 | mtd->ecc_stats.corrected += stat; | |
779 | } | |
780 | return 0; | |
22c60f5f | 781 | } |
1da177e4 | 782 | |
068e3c0a | 783 | /** |
f5bbdacc TG |
784 | * nand_read_page_hwecc - {REPLACABLE] hardware ecc based page read function |
785 | * @mtd: mtd info structure | |
786 | * @chip: nand chip info structure | |
787 | * @buf: buffer to store read data | |
068e3c0a | 788 | * |
f5bbdacc | 789 | * Not for syndrome calculating ecc controllers which need a special oob layout |
068e3c0a | 790 | */ |
f5bbdacc TG |
791 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
792 | uint8_t *buf) | |
1da177e4 | 793 | { |
f5bbdacc TG |
794 | int i, eccsize = chip->ecc.size; |
795 | int eccbytes = chip->ecc.bytes; | |
796 | int eccsteps = chip->ecc.steps; | |
797 | uint8_t *p = buf; | |
f75e5097 TG |
798 | uint8_t *ecc_calc = chip->buffers.ecccalc; |
799 | uint8_t *ecc_code = chip->buffers.ecccode; | |
f5bbdacc TG |
800 | int *eccpos = chip->autooob->eccpos; |
801 | ||
802 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
803 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
804 | chip->read_buf(mtd, p, eccsize); | |
805 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 806 | } |
f75e5097 | 807 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 808 | |
f5bbdacc | 809 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 810 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 811 | |
f5bbdacc TG |
812 | eccsteps = chip->ecc.steps; |
813 | p = buf; | |
61b03bd7 | 814 | |
f5bbdacc TG |
815 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
816 | int stat; | |
1da177e4 | 817 | |
f5bbdacc TG |
818 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
819 | if (stat == -1) | |
820 | mtd->ecc_stats.failed++; | |
821 | else | |
822 | mtd->ecc_stats.corrected += stat; | |
823 | } | |
824 | return 0; | |
825 | } | |
1da177e4 | 826 | |
f5bbdacc TG |
827 | /** |
828 | * nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read | |
829 | * @mtd: mtd info structure | |
830 | * @chip: nand chip info structure | |
831 | * @buf: buffer to store read data | |
832 | * | |
833 | * The hw generator calculates the error syndrome automatically. Therefor | |
f75e5097 | 834 | * we need a special oob layout and handling. |
f5bbdacc TG |
835 | */ |
836 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
837 | uint8_t *buf) | |
838 | { | |
839 | int i, eccsize = chip->ecc.size; | |
840 | int eccbytes = chip->ecc.bytes; | |
841 | int eccsteps = chip->ecc.steps; | |
842 | uint8_t *p = buf; | |
f75e5097 | 843 | uint8_t *oob = chip->oob_poi; |
1da177e4 | 844 | |
f5bbdacc TG |
845 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
846 | int stat; | |
61b03bd7 | 847 | |
f5bbdacc TG |
848 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
849 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 850 | |
f5bbdacc TG |
851 | if (chip->ecc.prepad) { |
852 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
853 | oob += chip->ecc.prepad; | |
854 | } | |
1da177e4 | 855 | |
f5bbdacc TG |
856 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
857 | chip->read_buf(mtd, oob, eccbytes); | |
858 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 859 | |
f5bbdacc TG |
860 | if (stat == -1) |
861 | mtd->ecc_stats.failed++; | |
61b03bd7 | 862 | else |
f5bbdacc | 863 | mtd->ecc_stats.corrected += stat; |
61b03bd7 | 864 | |
f5bbdacc | 865 | oob += eccbytes; |
1da177e4 | 866 | |
f5bbdacc TG |
867 | if (chip->ecc.postpad) { |
868 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
869 | oob += chip->ecc.postpad; | |
61b03bd7 | 870 | } |
f5bbdacc | 871 | } |
1da177e4 | 872 | |
f5bbdacc | 873 | /* Calculate remaining oob bytes */ |
f75e5097 | 874 | i = oob - chip->oob_poi; |
f5bbdacc TG |
875 | if (i) |
876 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 877 | |
f5bbdacc TG |
878 | return 0; |
879 | } | |
1da177e4 | 880 | |
f5bbdacc TG |
881 | /** |
882 | * nand_do_read - [Internal] Read data with ECC | |
883 | * | |
884 | * @mtd: MTD device structure | |
885 | * @from: offset to read from | |
886 | * @len: number of bytes to read | |
887 | * @retlen: pointer to variable to store the number of read bytes | |
888 | * @buf: the databuffer to put data | |
889 | * | |
890 | * Internal function. Called with chip held. | |
891 | */ | |
892 | int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, | |
893 | size_t *retlen, uint8_t *buf) | |
894 | { | |
895 | int chipnr, page, realpage, col, bytes, aligned; | |
896 | struct nand_chip *chip = mtd->priv; | |
897 | struct mtd_ecc_stats stats; | |
898 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
899 | int sndcmd = 1; | |
900 | int ret = 0; | |
901 | uint32_t readlen = len; | |
902 | uint8_t *bufpoi; | |
1da177e4 | 903 | |
f5bbdacc | 904 | stats = mtd->ecc_stats; |
1da177e4 | 905 | |
f5bbdacc TG |
906 | chipnr = (int)(from >> chip->chip_shift); |
907 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 908 | |
f5bbdacc TG |
909 | realpage = (int)(from >> chip->page_shift); |
910 | page = realpage & chip->pagemask; | |
1da177e4 | 911 | |
f5bbdacc | 912 | col = (int)(from & (mtd->writesize - 1)); |
f75e5097 | 913 | chip->oob_poi = chip->buffers.oobrbuf; |
61b03bd7 | 914 | |
f5bbdacc TG |
915 | while(1) { |
916 | bytes = min(mtd->writesize - col, readlen); | |
917 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 918 | |
f5bbdacc TG |
919 | /* Is the current page in the buffer ? */ |
920 | if (realpage != chip->pagebuf) { | |
f75e5097 | 921 | bufpoi = aligned ? buf : chip->buffers.databuf; |
61b03bd7 | 922 | |
f5bbdacc TG |
923 | if (likely(sndcmd)) { |
924 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); | |
925 | sndcmd = 0; | |
1da177e4 | 926 | } |
1da177e4 | 927 | |
f5bbdacc TG |
928 | /* Now read the page into the buffer */ |
929 | ret = chip->ecc.read_page(mtd, chip, bufpoi); | |
930 | if (ret < 0) | |
1da177e4 | 931 | break; |
f5bbdacc TG |
932 | |
933 | /* Transfer not aligned data */ | |
934 | if (!aligned) { | |
935 | chip->pagebuf = realpage; | |
f75e5097 | 936 | memcpy(buf, chip->buffers.databuf + col, bytes); |
f5bbdacc TG |
937 | } |
938 | ||
939 | if (!(chip->options & NAND_NO_READRDY)) { | |
940 | /* | |
941 | * Apply delay or wait for ready/busy pin. Do | |
942 | * this before the AUTOINCR check, so no | |
943 | * problems arise if a chip which does auto | |
944 | * increment is marked as NOAUTOINCR by the | |
945 | * board driver. | |
946 | */ | |
947 | if (!chip->dev_ready) | |
948 | udelay(chip->chip_delay); | |
949 | else | |
950 | nand_wait_ready(mtd); | |
1da177e4 | 951 | } |
61b03bd7 | 952 | } else |
f75e5097 | 953 | memcpy(buf, chip->buffers.databuf + col, bytes); |
1da177e4 | 954 | |
f5bbdacc TG |
955 | buf += bytes; |
956 | readlen -= bytes; | |
61b03bd7 | 957 | |
f5bbdacc | 958 | if (!readlen) |
61b03bd7 | 959 | break; |
1da177e4 LT |
960 | |
961 | /* For subsequent reads align to page boundary. */ | |
962 | col = 0; | |
963 | /* Increment page address */ | |
964 | realpage++; | |
965 | ||
ace4dfee | 966 | page = realpage & chip->pagemask; |
1da177e4 LT |
967 | /* Check, if we cross a chip boundary */ |
968 | if (!page) { | |
969 | chipnr++; | |
ace4dfee TG |
970 | chip->select_chip(mtd, -1); |
971 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 972 | } |
f5bbdacc | 973 | |
61b03bd7 TG |
974 | /* Check, if the chip supports auto page increment |
975 | * or if we have hit a block boundary. | |
e0c7d767 | 976 | */ |
f5bbdacc | 977 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) |
61b03bd7 | 978 | sndcmd = 1; |
1da177e4 LT |
979 | } |
980 | ||
f5bbdacc | 981 | *retlen = len - (size_t) readlen; |
1da177e4 | 982 | |
f5bbdacc TG |
983 | if (ret) |
984 | return ret; | |
985 | ||
986 | return mtd->ecc_stats.failed - stats.failed ? -EBADMSG : 0; | |
987 | } | |
988 | ||
989 | /** | |
990 | * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc | |
991 | * @mtd: MTD device structure | |
992 | * @from: offset to read from | |
993 | * @len: number of bytes to read | |
994 | * @retlen: pointer to variable to store the number of read bytes | |
995 | * @buf: the databuffer to put data | |
996 | * | |
997 | * Get hold of the chip and call nand_do_read | |
998 | */ | |
999 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1000 | size_t *retlen, uint8_t *buf) | |
1001 | { | |
1002 | int ret; | |
1003 | ||
1004 | *retlen = 0; | |
1005 | /* Do not allow reads past end of device */ | |
1006 | if ((from + len) > mtd->size) | |
1007 | return -EINVAL; | |
1008 | if (!len) | |
1009 | return 0; | |
1010 | ||
1011 | nand_get_device(mtd->priv, mtd, FL_READING); | |
1012 | ||
1013 | ret = nand_do_read(mtd, from, len, retlen, buf); | |
1014 | ||
1015 | nand_release_device(mtd); | |
1016 | ||
1017 | return ret; | |
1da177e4 LT |
1018 | } |
1019 | ||
1020 | /** | |
1021 | * nand_read_oob - [MTD Interface] NAND read out-of-band | |
1022 | * @mtd: MTD device structure | |
1023 | * @from: offset to read from | |
1024 | * @len: number of bytes to read | |
1025 | * @retlen: pointer to variable to store the number of read bytes | |
1026 | * @buf: the databuffer to put data | |
1027 | * | |
1028 | * NAND read out-of-band data from the spare area | |
1029 | */ | |
7314e9e7 TG |
1030 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, size_t len, |
1031 | size_t *retlen, uint8_t *buf) | |
1da177e4 | 1032 | { |
7314e9e7 | 1033 | int col, page, realpage, chipnr, sndcmd = 1; |
ace4dfee | 1034 | struct nand_chip *chip = mtd->priv; |
7314e9e7 TG |
1035 | int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; |
1036 | int readlen = len; | |
61b03bd7 | 1037 | |
7314e9e7 TG |
1038 | DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n", |
1039 | (unsigned int)from, (int)len); | |
1da177e4 LT |
1040 | |
1041 | /* Initialize return length value */ | |
1042 | *retlen = 0; | |
1043 | ||
1044 | /* Do not allow reads past end of device */ | |
1045 | if ((from + len) > mtd->size) { | |
7314e9e7 TG |
1046 | DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: " |
1047 | "Attempt read beyond end of device\n"); | |
1da177e4 LT |
1048 | return -EINVAL; |
1049 | } | |
1050 | ||
ace4dfee | 1051 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 | 1052 | |
7314e9e7 | 1053 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 1054 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1055 | |
7314e9e7 TG |
1056 | /* Shift to get page */ |
1057 | realpage = (int)(from >> chip->page_shift); | |
1058 | page = realpage & chip->pagemask; | |
1da177e4 | 1059 | |
7314e9e7 TG |
1060 | /* Mask to get column */ |
1061 | col = from & (mtd->oobsize - 1); | |
1062 | ||
1063 | while(1) { | |
1064 | int bytes = min((int)(mtd->oobsize - col), readlen); | |
1065 | ||
1066 | if (likely(sndcmd)) { | |
1067 | chip->cmdfunc(mtd, NAND_CMD_READOOB, col, page); | |
1068 | sndcmd = 0; | |
1069 | } | |
1070 | ||
1071 | chip->read_buf(mtd, buf, bytes); | |
61b03bd7 | 1072 | |
7314e9e7 TG |
1073 | readlen -= bytes; |
1074 | if (!readlen) | |
1075 | break; | |
1076 | ||
1077 | if (!(chip->options & NAND_NO_READRDY)) { | |
1078 | /* | |
1079 | * Apply delay or wait for ready/busy pin. Do this | |
1080 | * before the AUTOINCR check, so no problems arise if a | |
1081 | * chip which does auto increment is marked as | |
1082 | * NOAUTOINCR by the board driver. | |
19870da7 | 1083 | */ |
ace4dfee TG |
1084 | if (!chip->dev_ready) |
1085 | udelay(chip->chip_delay); | |
19870da7 TG |
1086 | else |
1087 | nand_wait_ready(mtd); | |
7314e9e7 | 1088 | } |
19870da7 | 1089 | |
7314e9e7 TG |
1090 | buf += bytes; |
1091 | bytes = mtd->oobsize; | |
1092 | col = 0; | |
1093 | ||
1094 | /* Increment page address */ | |
1095 | realpage++; | |
1096 | ||
1097 | page = realpage & chip->pagemask; | |
1098 | /* Check, if we cross a chip boundary */ | |
1099 | if (!page) { | |
1100 | chipnr++; | |
1101 | chip->select_chip(mtd, -1); | |
1102 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1103 | } |
7314e9e7 TG |
1104 | |
1105 | /* Check, if the chip supports auto page increment | |
1106 | * or if we have hit a block boundary. | |
1107 | */ | |
1108 | if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck)) | |
1109 | sndcmd = 1; | |
1da177e4 LT |
1110 | } |
1111 | ||
1112 | /* Deselect and wake up anyone waiting on the device */ | |
1113 | nand_release_device(mtd); | |
1114 | ||
1da177e4 LT |
1115 | *retlen = len; |
1116 | return 0; | |
1117 | } | |
1118 | ||
1119 | /** | |
1120 | * nand_read_raw - [GENERIC] Read raw data including oob into buffer | |
1121 | * @mtd: MTD device structure | |
1122 | * @buf: temporary buffer | |
1123 | * @from: offset to read from | |
1124 | * @len: number of bytes to read | |
1125 | * @ooblen: number of oob data bytes to read | |
1126 | * | |
1127 | * Read raw data including oob into buffer | |
1128 | */ | |
ace4dfee TG |
1129 | int nand_read_raw(struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, |
1130 | size_t ooblen) | |
1da177e4 | 1131 | { |
ace4dfee TG |
1132 | struct nand_chip *chip = mtd->priv; |
1133 | int page = (int)(from >> chip->page_shift); | |
1134 | int chipnr = (int)(from >> chip->chip_shift); | |
1da177e4 LT |
1135 | int sndcmd = 1; |
1136 | int cnt = 0; | |
28318776 | 1137 | int pagesize = mtd->writesize + mtd->oobsize; |
ace4dfee | 1138 | int blockcheck; |
1da177e4 LT |
1139 | |
1140 | /* Do not allow reads past end of device */ | |
1141 | if ((from + len) > mtd->size) { | |
ace4dfee TG |
1142 | DEBUG(MTD_DEBUG_LEVEL0, "nand_read_raw: " |
1143 | "Attempt read beyond end of device\n"); | |
1da177e4 LT |
1144 | return -EINVAL; |
1145 | } | |
1146 | ||
1147 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 1148 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 | 1149 | |
ace4dfee | 1150 | chip->select_chip(mtd, chipnr); |
61b03bd7 | 1151 | |
1da177e4 LT |
1152 | /* Add requested oob length */ |
1153 | len += ooblen; | |
ace4dfee | 1154 | blockcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; |
61b03bd7 | 1155 | |
1da177e4 | 1156 | while (len) { |
f75e5097 | 1157 | if (likely(sndcmd)) { |
ace4dfee TG |
1158 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, |
1159 | page & chip->pagemask); | |
f75e5097 TG |
1160 | sndcmd = 0; |
1161 | } | |
1da177e4 | 1162 | |
ace4dfee | 1163 | chip->read_buf(mtd, &buf[cnt], pagesize); |
1da177e4 LT |
1164 | |
1165 | len -= pagesize; | |
1166 | cnt += pagesize; | |
1167 | page++; | |
61b03bd7 | 1168 | |
f75e5097 TG |
1169 | if (!(chip->options & NAND_NO_READRDY)) { |
1170 | if (!chip->dev_ready) | |
1171 | udelay(chip->chip_delay); | |
1172 | else | |
1173 | nand_wait_ready(mtd); | |
1174 | } | |
61b03bd7 | 1175 | |
ace4dfee TG |
1176 | /* |
1177 | * Check, if the chip supports auto page increment or if we | |
1178 | * cross a block boundary. | |
1179 | */ | |
1180 | if (!NAND_CANAUTOINCR(chip) || !(page & blockcheck)) | |
1da177e4 LT |
1181 | sndcmd = 1; |
1182 | } | |
1183 | ||
1184 | /* Deselect and wake up anyone waiting on the device */ | |
1185 | nand_release_device(mtd); | |
1186 | return 0; | |
1187 | } | |
1188 | ||
9223a456 | 1189 | /** |
f75e5097 TG |
1190 | * nand_write_page_swecc - {REPLACABLE] software ecc based page write function |
1191 | * @mtd: mtd info structure | |
1192 | * @chip: nand chip info structure | |
1193 | * @buf: data buffer | |
9223a456 | 1194 | */ |
f75e5097 TG |
1195 | static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1196 | const uint8_t *buf) | |
9223a456 | 1197 | { |
f75e5097 TG |
1198 | int i, eccsize = chip->ecc.size; |
1199 | int eccbytes = chip->ecc.bytes; | |
1200 | int eccsteps = chip->ecc.steps; | |
1201 | uint8_t *ecc_calc = chip->buffers.ecccalc; | |
1202 | const uint8_t *p = buf; | |
1203 | int *eccpos = chip->autooob->eccpos; | |
9223a456 | 1204 | |
f75e5097 TG |
1205 | if (chip->ecc.mode != NAND_ECC_NONE) { |
1206 | /* Software ecc calculation */ | |
1207 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1208 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 1209 | |
f75e5097 TG |
1210 | for (i = 0; i < chip->ecc.total; i++) |
1211 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 TG |
1212 | } |
1213 | ||
f75e5097 TG |
1214 | chip->write_buf(mtd, buf, mtd->writesize); |
1215 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1216 | } | |
9223a456 | 1217 | |
f75e5097 TG |
1218 | /** |
1219 | * nand_write_page_hwecc - {REPLACABLE] hardware ecc based page write function | |
1220 | * @mtd: mtd info structure | |
1221 | * @chip: nand chip info structure | |
1222 | * @buf: data buffer | |
1223 | */ | |
1224 | static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, | |
1225 | const uint8_t *buf) | |
1226 | { | |
1227 | int i, eccsize = chip->ecc.size; | |
1228 | int eccbytes = chip->ecc.bytes; | |
1229 | int eccsteps = chip->ecc.steps; | |
1230 | uint8_t *ecc_calc = chip->buffers.ecccalc; | |
1231 | const uint8_t *p = buf; | |
1232 | int *eccpos = chip->autooob->eccpos; | |
9223a456 | 1233 | |
f75e5097 TG |
1234 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1235 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
1236 | chip->write_buf(mtd, p, mtd->writesize); | |
1237 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 TG |
1238 | } |
1239 | ||
f75e5097 TG |
1240 | for (i = 0; i < chip->ecc.total; i++) |
1241 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
1242 | ||
1243 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
9223a456 TG |
1244 | } |
1245 | ||
61b03bd7 | 1246 | /** |
f75e5097 TG |
1247 | * nand_write_page_syndrome - {REPLACABLE] hardware ecc syndrom based page write |
1248 | * @mtd: mtd info structure | |
1249 | * @chip: nand chip info structure | |
1250 | * @buf: data buffer | |
1da177e4 | 1251 | * |
f75e5097 TG |
1252 | * The hw generator calculates the error syndrome automatically. Therefor |
1253 | * we need a special oob layout and handling. | |
1254 | */ | |
1255 | static void nand_write_page_syndrome(struct mtd_info *mtd, | |
1256 | struct nand_chip *chip, const uint8_t *buf) | |
1da177e4 | 1257 | { |
f75e5097 TG |
1258 | int i, eccsize = chip->ecc.size; |
1259 | int eccbytes = chip->ecc.bytes; | |
1260 | int eccsteps = chip->ecc.steps; | |
1261 | const uint8_t *p = buf; | |
1262 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 1263 | |
f75e5097 | 1264 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 1265 | |
f75e5097 TG |
1266 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
1267 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 1268 | |
f75e5097 TG |
1269 | if (chip->ecc.prepad) { |
1270 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
1271 | oob += chip->ecc.prepad; | |
1272 | } | |
1273 | ||
1274 | chip->ecc.calculate(mtd, p, oob); | |
1275 | chip->write_buf(mtd, oob, eccbytes); | |
1276 | oob += eccbytes; | |
1277 | ||
1278 | if (chip->ecc.postpad) { | |
1279 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
1280 | oob += chip->ecc.postpad; | |
1da177e4 | 1281 | } |
1da177e4 | 1282 | } |
f75e5097 TG |
1283 | |
1284 | /* Calculate remaining oob bytes */ | |
1285 | i = oob - chip->oob_poi; | |
1286 | if (i) | |
1287 | chip->write_buf(mtd, oob, i); | |
1288 | } | |
1289 | ||
1290 | /** | |
1291 | * nand_write_page - [INTERNAL] write one page | |
1292 | * @mtd: MTD device structure | |
1293 | * @chip: NAND chip descriptor | |
1294 | * @buf: the data to write | |
1295 | * @page: page number to write | |
1296 | * @cached: cached programming | |
1297 | */ | |
1298 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
1299 | const uint8_t *buf, int page, int cached) | |
1300 | { | |
1301 | int status; | |
1302 | ||
1303 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
1304 | ||
1305 | chip->ecc.write_page(mtd, chip, buf); | |
1306 | ||
1307 | /* | |
1308 | * Cached progamming disabled for now, Not sure if its worth the | |
1309 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s) | |
1310 | */ | |
1311 | cached = 0; | |
1312 | ||
1313 | if (!cached || !(chip->options & NAND_CACHEPRG)) { | |
1314 | ||
1315 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1316 | status = chip->waitfunc(mtd, chip, FL_WRITING); | |
1317 | /* | |
1318 | * See if operation failed and additional status checks are | |
1319 | * available | |
1320 | */ | |
1321 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
1322 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
1323 | page); | |
1324 | ||
1325 | if (status & NAND_STATUS_FAIL) | |
1326 | return -EIO; | |
1327 | } else { | |
1328 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
1329 | status = chip->waitfunc(mtd, chip, FL_WRITING); | |
1330 | } | |
1331 | ||
1332 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE | |
1333 | /* Send command to read back the data */ | |
1334 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1335 | ||
1336 | if (chip->verify_buf(mtd, buf, mtd->writesize)) | |
1337 | return -EIO; | |
1338 | #endif | |
1339 | return 0; | |
1da177e4 LT |
1340 | } |
1341 | ||
28318776 | 1342 | #define NOTALIGNED(x) (x & (mtd->writesize-1)) != 0 |
1da177e4 LT |
1343 | |
1344 | /** | |
9223a456 | 1345 | * nand_write - [MTD Interface] NAND write with ECC |
1da177e4 LT |
1346 | * @mtd: MTD device structure |
1347 | * @to: offset to write to | |
1348 | * @len: number of bytes to write | |
1349 | * @retlen: pointer to variable to store the number of written bytes | |
1350 | * @buf: the data to write | |
1da177e4 LT |
1351 | * |
1352 | * NAND write with ECC | |
1353 | */ | |
9223a456 TG |
1354 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
1355 | size_t *retlen, const uint8_t *buf) | |
1da177e4 | 1356 | { |
f75e5097 | 1357 | int chipnr, realpage, page, blockmask; |
ace4dfee | 1358 | struct nand_chip *chip = mtd->priv; |
f75e5097 TG |
1359 | uint32_t writelen = len; |
1360 | int bytes = mtd->writesize; | |
1361 | int ret = -EIO; | |
1da177e4 | 1362 | |
1da177e4 LT |
1363 | *retlen = 0; |
1364 | ||
1365 | /* Do not allow write past end of device */ | |
1366 | if ((to + len) > mtd->size) { | |
f75e5097 TG |
1367 | DEBUG(MTD_DEBUG_LEVEL0, "nand_write: " |
1368 | "Attempt to write past end of page\n"); | |
1da177e4 LT |
1369 | return -EINVAL; |
1370 | } | |
1371 | ||
61b03bd7 | 1372 | /* reject writes, which are not page aligned */ |
e0c7d767 | 1373 | if (NOTALIGNED(to) || NOTALIGNED(len)) { |
f75e5097 TG |
1374 | printk(KERN_NOTICE "nand_write: " |
1375 | "Attempt to write not page aligned data\n"); | |
1da177e4 LT |
1376 | return -EINVAL; |
1377 | } | |
1378 | ||
f75e5097 TG |
1379 | if (!len) |
1380 | return 0; | |
1da177e4 | 1381 | |
f75e5097 | 1382 | nand_get_device(chip, mtd, FL_WRITING); |
1da177e4 LT |
1383 | |
1384 | /* Check, if it is write protected */ | |
1385 | if (nand_check_wp(mtd)) | |
1386 | goto out; | |
1387 | ||
f75e5097 TG |
1388 | chipnr = (int)(to >> chip->chip_shift); |
1389 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1390 | |
f75e5097 TG |
1391 | realpage = (int)(to >> chip->page_shift); |
1392 | page = realpage & chip->pagemask; | |
1393 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
1394 | ||
1395 | /* Invalidate the page cache, when we write to the cached page */ | |
1396 | if (to <= (chip->pagebuf << chip->page_shift) && | |
1397 | (chip->pagebuf << chip->page_shift) < (to + len)) | |
ace4dfee | 1398 | chip->pagebuf = -1; |
61b03bd7 | 1399 | |
f75e5097 | 1400 | chip->oob_poi = chip->buffers.oobwbuf; |
61b03bd7 | 1401 | |
f75e5097 TG |
1402 | while(1) { |
1403 | int cached = writelen > bytes && page != blockmask; | |
1da177e4 | 1404 | |
f75e5097 TG |
1405 | ret = nand_write_page(mtd, chip, buf, page, cached); |
1406 | if (ret) | |
1407 | break; | |
1408 | ||
1409 | writelen -= bytes; | |
1410 | if (!writelen) | |
1411 | break; | |
1412 | ||
1413 | buf += bytes; | |
1414 | realpage++; | |
1415 | ||
1416 | page = realpage & chip->pagemask; | |
1417 | /* Check, if we cross a chip boundary */ | |
1418 | if (!page) { | |
1419 | chipnr++; | |
1420 | chip->select_chip(mtd, -1); | |
1421 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
1422 | } |
1423 | } | |
e0c7d767 | 1424 | out: |
f75e5097 | 1425 | *retlen = len - writelen; |
1da177e4 | 1426 | nand_release_device(mtd); |
1da177e4 LT |
1427 | return ret; |
1428 | } | |
1429 | ||
f75e5097 TG |
1430 | /** |
1431 | * nand_write_raw - [GENERIC] Write raw data including oob | |
1432 | * @mtd: MTD device structure | |
1433 | * @buf: source buffer | |
1434 | * @to: offset to write to | |
1435 | * @len: number of bytes to write | |
1436 | * @buf: source buffer | |
1437 | * @oob: oob buffer | |
1438 | * | |
1439 | * Write raw data including oob | |
1440 | */ | |
1441 | int nand_write_raw(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, | |
1442 | const uint8_t *buf, uint8_t *oob) | |
1443 | { | |
1444 | struct nand_chip *chip = mtd->priv; | |
1445 | int page = (int)(to >> chip->page_shift); | |
1446 | int chipnr = (int)(to >> chip->chip_shift); | |
1447 | int ret; | |
1448 | ||
1449 | *retlen = 0; | |
1450 | ||
1451 | /* Do not allow writes past end of device */ | |
1452 | if ((to + len) > mtd->size) { | |
1453 | DEBUG(MTD_DEBUG_LEVEL0, "nand_read_raw: Attempt write " | |
1454 | "beyond end of device\n"); | |
1455 | return -EINVAL; | |
1456 | } | |
1457 | ||
1458 | /* Grab the lock and see if the device is available */ | |
1459 | nand_get_device(chip, mtd, FL_WRITING); | |
1460 | ||
1461 | chip->select_chip(mtd, chipnr); | |
1462 | chip->oob_poi = oob; | |
1463 | ||
1464 | while (len != *retlen) { | |
1465 | ret = nand_write_page(mtd, chip, buf, page, 0); | |
1466 | if (ret) | |
1467 | return ret; | |
1468 | page++; | |
1469 | *retlen += mtd->writesize; | |
1470 | buf += mtd->writesize; | |
1471 | chip->oob_poi += mtd->oobsize; | |
1472 | } | |
1473 | ||
1474 | /* Deselect and wake up anyone waiting on the device */ | |
1475 | nand_release_device(mtd); | |
1476 | return 0; | |
1477 | } | |
1478 | EXPORT_SYMBOL_GPL(nand_write_raw); | |
7314e9e7 | 1479 | |
1da177e4 LT |
1480 | /** |
1481 | * nand_write_oob - [MTD Interface] NAND write out-of-band | |
1482 | * @mtd: MTD device structure | |
1483 | * @to: offset to write to | |
1484 | * @len: number of bytes to write | |
1485 | * @retlen: pointer to variable to store the number of written bytes | |
1486 | * @buf: the data to write | |
1487 | * | |
1488 | * NAND write out-of-band | |
1489 | */ | |
7314e9e7 TG |
1490 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, size_t len, |
1491 | size_t *retlen, const uint8_t *buf) | |
1da177e4 LT |
1492 | { |
1493 | int column, page, status, ret = -EIO, chipnr; | |
ace4dfee | 1494 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 1495 | |
7314e9e7 TG |
1496 | DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", |
1497 | (unsigned int)to, (int)len); | |
1da177e4 LT |
1498 | |
1499 | /* Initialize return length value */ | |
1500 | *retlen = 0; | |
1501 | ||
1502 | /* Do not allow write past end of page */ | |
7314e9e7 | 1503 | column = to & (mtd->oobsize - 1); |
1da177e4 | 1504 | if ((column + len) > mtd->oobsize) { |
7314e9e7 TG |
1505 | DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: " |
1506 | "Attempt to write past end of page\n"); | |
1da177e4 LT |
1507 | return -EINVAL; |
1508 | } | |
1509 | ||
ace4dfee | 1510 | nand_get_device(chip, mtd, FL_WRITING); |
1da177e4 | 1511 | |
7314e9e7 | 1512 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 1513 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1514 | |
7314e9e7 TG |
1515 | /* Shift to get page */ |
1516 | page = (int)(to >> chip->page_shift); | |
1517 | ||
1518 | /* | |
1519 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
1520 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
1521 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
1522 | * it in the doc2000 driver in August 1999. dwmw2. | |
1523 | */ | |
ace4dfee | 1524 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
1525 | |
1526 | /* Check, if it is write protected */ | |
1527 | if (nand_check_wp(mtd)) | |
1528 | goto out; | |
61b03bd7 | 1529 | |
1da177e4 | 1530 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
1531 | if (page == chip->pagebuf) |
1532 | chip->pagebuf = -1; | |
1da177e4 | 1533 | |
ace4dfee | 1534 | if (NAND_MUST_PAD(chip)) { |
7314e9e7 TG |
1535 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, |
1536 | page & chip->pagemask); | |
1da177e4 | 1537 | /* prepad 0xff for partial programming */ |
ace4dfee | 1538 | chip->write_buf(mtd, ffchars, column); |
1da177e4 | 1539 | /* write data */ |
ace4dfee | 1540 | chip->write_buf(mtd, buf, len); |
1da177e4 | 1541 | /* postpad 0xff for partial programming */ |
ace4dfee | 1542 | chip->write_buf(mtd, ffchars, mtd->oobsize - (len + column)); |
1da177e4 | 1543 | } else { |
7314e9e7 TG |
1544 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize + column, |
1545 | page & chip->pagemask); | |
ace4dfee | 1546 | chip->write_buf(mtd, buf, len); |
1da177e4 LT |
1547 | } |
1548 | /* Send command to program the OOB data */ | |
ace4dfee | 1549 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); |
1da177e4 | 1550 | |
ace4dfee | 1551 | status = chip->waitfunc(mtd, chip, FL_WRITING); |
1da177e4 LT |
1552 | |
1553 | /* See if device thinks it succeeded */ | |
a4ab4c5d | 1554 | if (status & NAND_STATUS_FAIL) { |
7314e9e7 TG |
1555 | DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: " |
1556 | "Failed write, page 0x%08x\n", page); | |
1da177e4 LT |
1557 | ret = -EIO; |
1558 | goto out; | |
1559 | } | |
1da177e4 LT |
1560 | *retlen = len; |
1561 | ||
1562 | #ifdef CONFIG_MTD_NAND_VERIFY_WRITE | |
1563 | /* Send command to read back the data */ | |
ace4dfee | 1564 | chip->cmdfunc(mtd, NAND_CMD_READOOB, column, page & chip->pagemask); |
1da177e4 | 1565 | |
ace4dfee | 1566 | if (chip->verify_buf(mtd, buf, len)) { |
7314e9e7 TG |
1567 | DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: " |
1568 | "Failed write verify, page 0x%08x\n", page); | |
1da177e4 LT |
1569 | ret = -EIO; |
1570 | goto out; | |
1571 | } | |
1572 | #endif | |
1573 | ret = 0; | |
e0c7d767 | 1574 | out: |
1da177e4 LT |
1575 | /* Deselect and wake up anyone waiting on the device */ |
1576 | nand_release_device(mtd); | |
1577 | ||
1578 | return ret; | |
1579 | } | |
1580 | ||
1da177e4 LT |
1581 | /** |
1582 | * single_erease_cmd - [GENERIC] NAND standard block erase command function | |
1583 | * @mtd: MTD device structure | |
1584 | * @page: the page address of the block which will be erased | |
1585 | * | |
1586 | * Standard erase command for NAND chips | |
1587 | */ | |
e0c7d767 | 1588 | static void single_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 1589 | { |
ace4dfee | 1590 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 1591 | /* Send commands to erase a block */ |
ace4dfee TG |
1592 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
1593 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
1594 | } |
1595 | ||
1596 | /** | |
1597 | * multi_erease_cmd - [GENERIC] AND specific block erase command function | |
1598 | * @mtd: MTD device structure | |
1599 | * @page: the page address of the block which will be erased | |
1600 | * | |
1601 | * AND multi block erase command function | |
1602 | * Erase 4 consecutive blocks | |
1603 | */ | |
e0c7d767 | 1604 | static void multi_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 1605 | { |
ace4dfee | 1606 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 1607 | /* Send commands to erase a block */ |
ace4dfee TG |
1608 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); |
1609 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
1610 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
1611 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); | |
1612 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
1613 | } |
1614 | ||
1615 | /** | |
1616 | * nand_erase - [MTD Interface] erase block(s) | |
1617 | * @mtd: MTD device structure | |
1618 | * @instr: erase instruction | |
1619 | * | |
1620 | * Erase one ore more blocks | |
1621 | */ | |
e0c7d767 | 1622 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 1623 | { |
e0c7d767 | 1624 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 1625 | } |
61b03bd7 | 1626 | |
30f464b7 | 1627 | #define BBT_PAGE_MASK 0xffffff3f |
1da177e4 | 1628 | /** |
ace4dfee | 1629 | * nand_erase_nand - [Internal] erase block(s) |
1da177e4 LT |
1630 | * @mtd: MTD device structure |
1631 | * @instr: erase instruction | |
1632 | * @allowbbt: allow erasing the bbt area | |
1633 | * | |
1634 | * Erase one ore more blocks | |
1635 | */ | |
ace4dfee TG |
1636 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
1637 | int allowbbt) | |
1da177e4 LT |
1638 | { |
1639 | int page, len, status, pages_per_block, ret, chipnr; | |
ace4dfee TG |
1640 | struct nand_chip *chip = mtd->priv; |
1641 | int rewrite_bbt[NAND_MAX_CHIPS]={0}; | |
1642 | unsigned int bbt_masked_page = 0xffffffff; | |
1da177e4 | 1643 | |
ace4dfee TG |
1644 | DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n", |
1645 | (unsigned int)instr->addr, (unsigned int)instr->len); | |
1da177e4 LT |
1646 | |
1647 | /* Start address must align on block boundary */ | |
ace4dfee | 1648 | if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) { |
e0c7d767 | 1649 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n"); |
1da177e4 LT |
1650 | return -EINVAL; |
1651 | } | |
1652 | ||
1653 | /* Length must align on block boundary */ | |
ace4dfee TG |
1654 | if (instr->len & ((1 << chip->phys_erase_shift) - 1)) { |
1655 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " | |
1656 | "Length not block aligned\n"); | |
1da177e4 LT |
1657 | return -EINVAL; |
1658 | } | |
1659 | ||
1660 | /* Do not allow erase past end of device */ | |
1661 | if ((instr->len + instr->addr) > mtd->size) { | |
ace4dfee TG |
1662 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " |
1663 | "Erase past end of device\n"); | |
1da177e4 LT |
1664 | return -EINVAL; |
1665 | } | |
1666 | ||
1667 | instr->fail_addr = 0xffffffff; | |
1668 | ||
1669 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 1670 | nand_get_device(chip, mtd, FL_ERASING); |
1da177e4 LT |
1671 | |
1672 | /* Shift to get first page */ | |
ace4dfee TG |
1673 | page = (int)(instr->addr >> chip->page_shift); |
1674 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
1675 | |
1676 | /* Calculate pages in each block */ | |
ace4dfee | 1677 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
1678 | |
1679 | /* Select the NAND device */ | |
ace4dfee | 1680 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1681 | |
1da177e4 LT |
1682 | /* Check, if it is write protected */ |
1683 | if (nand_check_wp(mtd)) { | |
ace4dfee TG |
1684 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " |
1685 | "Device is write protected!!!\n"); | |
1da177e4 LT |
1686 | instr->state = MTD_ERASE_FAILED; |
1687 | goto erase_exit; | |
1688 | } | |
1689 | ||
ace4dfee TG |
1690 | /* |
1691 | * If BBT requires refresh, set the BBT page mask to see if the BBT | |
1692 | * should be rewritten. Otherwise the mask is set to 0xffffffff which | |
1693 | * can not be matched. This is also done when the bbt is actually | |
1694 | * erased to avoid recusrsive updates | |
1695 | */ | |
1696 | if (chip->options & BBT_AUTO_REFRESH && !allowbbt) | |
1697 | bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK; | |
30f464b7 | 1698 | |
1da177e4 LT |
1699 | /* Loop through the pages */ |
1700 | len = instr->len; | |
1701 | ||
1702 | instr->state = MTD_ERASING; | |
1703 | ||
1704 | while (len) { | |
ace4dfee TG |
1705 | /* |
1706 | * heck if we have a bad block, we do not erase bad blocks ! | |
1707 | */ | |
1708 | if (nand_block_checkbad(mtd, ((loff_t) page) << | |
1709 | chip->page_shift, 0, allowbbt)) { | |
1710 | printk(KERN_WARNING "nand_erase: attempt to erase a " | |
1711 | "bad block at page 0x%08x\n", page); | |
1da177e4 LT |
1712 | instr->state = MTD_ERASE_FAILED; |
1713 | goto erase_exit; | |
1714 | } | |
61b03bd7 | 1715 | |
ace4dfee TG |
1716 | /* |
1717 | * Invalidate the page cache, if we erase the block which | |
1718 | * contains the current cached page | |
1719 | */ | |
1720 | if (page <= chip->pagebuf && chip->pagebuf < | |
1721 | (page + pages_per_block)) | |
1722 | chip->pagebuf = -1; | |
1da177e4 | 1723 | |
ace4dfee | 1724 | chip->erase_cmd(mtd, page & chip->pagemask); |
61b03bd7 | 1725 | |
ace4dfee | 1726 | status = chip->waitfunc(mtd, chip, FL_ERASING); |
1da177e4 | 1727 | |
ace4dfee TG |
1728 | /* |
1729 | * See if operation failed and additional status checks are | |
1730 | * available | |
1731 | */ | |
1732 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
1733 | status = chip->errstat(mtd, chip, FL_ERASING, | |
1734 | status, page); | |
068e3c0a | 1735 | |
1da177e4 | 1736 | /* See if block erase succeeded */ |
a4ab4c5d | 1737 | if (status & NAND_STATUS_FAIL) { |
ace4dfee TG |
1738 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: " |
1739 | "Failed erase, page 0x%08x\n", page); | |
1da177e4 | 1740 | instr->state = MTD_ERASE_FAILED; |
ace4dfee | 1741 | instr->fail_addr = (page << chip->page_shift); |
1da177e4 LT |
1742 | goto erase_exit; |
1743 | } | |
30f464b7 | 1744 | |
ace4dfee TG |
1745 | /* |
1746 | * If BBT requires refresh, set the BBT rewrite flag to the | |
1747 | * page being erased | |
1748 | */ | |
1749 | if (bbt_masked_page != 0xffffffff && | |
1750 | (page & BBT_PAGE_MASK) == bbt_masked_page) | |
1751 | rewrite_bbt[chipnr] = (page << chip->page_shift); | |
61b03bd7 | 1752 | |
1da177e4 | 1753 | /* Increment page address and decrement length */ |
ace4dfee | 1754 | len -= (1 << chip->phys_erase_shift); |
1da177e4 LT |
1755 | page += pages_per_block; |
1756 | ||
1757 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 1758 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 1759 | chipnr++; |
ace4dfee TG |
1760 | chip->select_chip(mtd, -1); |
1761 | chip->select_chip(mtd, chipnr); | |
30f464b7 | 1762 | |
ace4dfee TG |
1763 | /* |
1764 | * If BBT requires refresh and BBT-PERCHIP, set the BBT | |
1765 | * page mask to see if this BBT should be rewritten | |
1766 | */ | |
1767 | if (bbt_masked_page != 0xffffffff && | |
1768 | (chip->bbt_td->options & NAND_BBT_PERCHIP)) | |
1769 | bbt_masked_page = chip->bbt_td->pages[chipnr] & | |
1770 | BBT_PAGE_MASK; | |
1da177e4 LT |
1771 | } |
1772 | } | |
1773 | instr->state = MTD_ERASE_DONE; | |
1774 | ||
e0c7d767 | 1775 | erase_exit: |
1da177e4 LT |
1776 | |
1777 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1778 | /* Do call back function */ | |
1779 | if (!ret) | |
1780 | mtd_erase_callback(instr); | |
1781 | ||
1782 | /* Deselect and wake up anyone waiting on the device */ | |
1783 | nand_release_device(mtd); | |
1784 | ||
ace4dfee TG |
1785 | /* |
1786 | * If BBT requires refresh and erase was successful, rewrite any | |
1787 | * selected bad block tables | |
1788 | */ | |
1789 | if (bbt_masked_page == 0xffffffff || ret) | |
1790 | return ret; | |
1791 | ||
1792 | for (chipnr = 0; chipnr < chip->numchips; chipnr++) { | |
1793 | if (!rewrite_bbt[chipnr]) | |
1794 | continue; | |
1795 | /* update the BBT for chip */ | |
1796 | DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt " | |
1797 | "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr], | |
1798 | chip->bbt_td->pages[chipnr]); | |
1799 | nand_update_bbt(mtd, rewrite_bbt[chipnr]); | |
30f464b7 DM |
1800 | } |
1801 | ||
1da177e4 LT |
1802 | /* Return more or less happy */ |
1803 | return ret; | |
1804 | } | |
1805 | ||
1806 | /** | |
1807 | * nand_sync - [MTD Interface] sync | |
1808 | * @mtd: MTD device structure | |
1809 | * | |
1810 | * Sync is actually a wait for chip ready function | |
1811 | */ | |
e0c7d767 | 1812 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 1813 | { |
ace4dfee | 1814 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 1815 | |
e0c7d767 | 1816 | DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n"); |
1da177e4 LT |
1817 | |
1818 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 1819 | nand_get_device(chip, mtd, FL_SYNCING); |
1da177e4 | 1820 | /* Release it and go back */ |
e0c7d767 | 1821 | nand_release_device(mtd); |
1da177e4 LT |
1822 | } |
1823 | ||
1da177e4 | 1824 | /** |
ace4dfee | 1825 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
1da177e4 LT |
1826 | * @mtd: MTD device structure |
1827 | * @ofs: offset relative to mtd start | |
1828 | */ | |
ace4dfee | 1829 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 LT |
1830 | { |
1831 | /* Check for invalid offset */ | |
ace4dfee | 1832 | if (offs > mtd->size) |
1da177e4 | 1833 | return -EINVAL; |
61b03bd7 | 1834 | |
ace4dfee | 1835 | return nand_block_checkbad(mtd, offs, 1, 0); |
1da177e4 LT |
1836 | } |
1837 | ||
1838 | /** | |
ace4dfee | 1839 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
1da177e4 LT |
1840 | * @mtd: MTD device structure |
1841 | * @ofs: offset relative to mtd start | |
1842 | */ | |
e0c7d767 | 1843 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 1844 | { |
ace4dfee | 1845 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
1846 | int ret; |
1847 | ||
e0c7d767 DW |
1848 | if ((ret = nand_block_isbad(mtd, ofs))) { |
1849 | /* If it was bad already, return success and do nothing. */ | |
1da177e4 LT |
1850 | if (ret > 0) |
1851 | return 0; | |
e0c7d767 DW |
1852 | return ret; |
1853 | } | |
1da177e4 | 1854 | |
ace4dfee | 1855 | return chip->block_markbad(mtd, ofs); |
1da177e4 LT |
1856 | } |
1857 | ||
962034f4 VW |
1858 | /** |
1859 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
1860 | * @mtd: MTD device structure | |
1861 | */ | |
1862 | static int nand_suspend(struct mtd_info *mtd) | |
1863 | { | |
ace4dfee | 1864 | struct nand_chip *chip = mtd->priv; |
962034f4 | 1865 | |
ace4dfee | 1866 | return nand_get_device(chip, mtd, FL_PM_SUSPENDED); |
962034f4 VW |
1867 | } |
1868 | ||
1869 | /** | |
1870 | * nand_resume - [MTD Interface] Resume the NAND flash | |
1871 | * @mtd: MTD device structure | |
1872 | */ | |
1873 | static void nand_resume(struct mtd_info *mtd) | |
1874 | { | |
ace4dfee | 1875 | struct nand_chip *chip = mtd->priv; |
962034f4 | 1876 | |
ace4dfee | 1877 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
1878 | nand_release_device(mtd); |
1879 | else | |
2c0a2bed TG |
1880 | printk(KERN_ERR "nand_resume() called for a chip which is not " |
1881 | "in suspended state\n"); | |
962034f4 VW |
1882 | } |
1883 | ||
7aa65bfd TG |
1884 | /* |
1885 | * Set default functions | |
1886 | */ | |
ace4dfee | 1887 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 1888 | { |
1da177e4 | 1889 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
1890 | if (!chip->chip_delay) |
1891 | chip->chip_delay = 20; | |
1da177e4 LT |
1892 | |
1893 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
1894 | if (chip->cmdfunc == NULL) |
1895 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
1896 | |
1897 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
1898 | if (chip->waitfunc == NULL) |
1899 | chip->waitfunc = nand_wait; | |
1900 | ||
1901 | if (!chip->select_chip) | |
1902 | chip->select_chip = nand_select_chip; | |
1903 | if (!chip->read_byte) | |
1904 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; | |
1905 | if (!chip->read_word) | |
1906 | chip->read_word = nand_read_word; | |
1907 | if (!chip->block_bad) | |
1908 | chip->block_bad = nand_block_bad; | |
1909 | if (!chip->block_markbad) | |
1910 | chip->block_markbad = nand_default_block_markbad; | |
1911 | if (!chip->write_buf) | |
1912 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; | |
1913 | if (!chip->read_buf) | |
1914 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; | |
1915 | if (!chip->verify_buf) | |
1916 | chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; | |
1917 | if (!chip->scan_bbt) | |
1918 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
1919 | |
1920 | if (!chip->controller) { | |
1921 | chip->controller = &chip->hwcontrol; | |
1922 | spin_lock_init(&chip->controller->lock); | |
1923 | init_waitqueue_head(&chip->controller->wq); | |
1924 | } | |
1925 | ||
7aa65bfd TG |
1926 | } |
1927 | ||
1928 | /* | |
ace4dfee | 1929 | * Get the flash and manufacturer id and lookup if the type is supported |
7aa65bfd TG |
1930 | */ |
1931 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 1932 | struct nand_chip *chip, |
7aa65bfd TG |
1933 | int busw, int *maf_id) |
1934 | { | |
1935 | struct nand_flash_dev *type = NULL; | |
1936 | int i, dev_id, maf_idx; | |
1da177e4 LT |
1937 | |
1938 | /* Select the device */ | |
ace4dfee | 1939 | chip->select_chip(mtd, 0); |
1da177e4 LT |
1940 | |
1941 | /* Send the command for reading device ID */ | |
ace4dfee | 1942 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
1943 | |
1944 | /* Read manufacturer and device IDs */ | |
ace4dfee TG |
1945 | *maf_id = chip->read_byte(mtd); |
1946 | dev_id = chip->read_byte(mtd); | |
1da177e4 | 1947 | |
7aa65bfd | 1948 | /* Lookup the flash id */ |
1da177e4 | 1949 | for (i = 0; nand_flash_ids[i].name != NULL; i++) { |
7aa65bfd TG |
1950 | if (dev_id == nand_flash_ids[i].id) { |
1951 | type = &nand_flash_ids[i]; | |
1952 | break; | |
1953 | } | |
1954 | } | |
61b03bd7 | 1955 | |
7aa65bfd TG |
1956 | if (!type) |
1957 | return ERR_PTR(-ENODEV); | |
1958 | ||
ace4dfee | 1959 | chip->chipsize = nand_flash_ids[i].chipsize << 20; |
7aa65bfd TG |
1960 | |
1961 | /* Newer devices have all the information in additional id bytes */ | |
1962 | if (!nand_flash_ids[i].pagesize) { | |
1963 | int extid; | |
1964 | /* The 3rd id byte contains non relevant data ATM */ | |
ace4dfee | 1965 | extid = chip->read_byte(mtd); |
7aa65bfd | 1966 | /* The 4th id byte is the important one */ |
ace4dfee | 1967 | extid = chip->read_byte(mtd); |
7aa65bfd | 1968 | /* Calc pagesize */ |
4cbb9b80 | 1969 | mtd->writesize = 1024 << (extid & 0x3); |
7aa65bfd TG |
1970 | extid >>= 2; |
1971 | /* Calc oobsize */ | |
4cbb9b80 | 1972 | mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9); |
7aa65bfd TG |
1973 | extid >>= 2; |
1974 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
1975 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
1976 | extid >>= 2; | |
1977 | /* Get buswidth information */ | |
1978 | busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
61b03bd7 | 1979 | |
7aa65bfd TG |
1980 | } else { |
1981 | /* | |
ace4dfee | 1982 | * Old devices have chip data hardcoded in the device id table |
7aa65bfd TG |
1983 | */ |
1984 | mtd->erasesize = nand_flash_ids[i].erasesize; | |
4cbb9b80 TG |
1985 | mtd->writesize = nand_flash_ids[i].pagesize; |
1986 | mtd->oobsize = mtd->writesize / 32; | |
7aa65bfd TG |
1987 | busw = nand_flash_ids[i].options & NAND_BUSWIDTH_16; |
1988 | } | |
1da177e4 | 1989 | |
7aa65bfd TG |
1990 | /* Try to identify manufacturer */ |
1991 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_id++) { | |
1992 | if (nand_manuf_ids[maf_idx].id == *maf_id) | |
1993 | break; | |
1994 | } | |
0ea4a755 | 1995 | |
7aa65bfd TG |
1996 | /* |
1997 | * Check, if buswidth is correct. Hardware drivers should set | |
ace4dfee | 1998 | * chip correct ! |
7aa65bfd | 1999 | */ |
ace4dfee | 2000 | if (busw != (chip->options & NAND_BUSWIDTH_16)) { |
7aa65bfd TG |
2001 | printk(KERN_INFO "NAND device: Manufacturer ID:" |
2002 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, | |
2003 | dev_id, nand_manuf_ids[maf_idx].name, mtd->name); | |
2004 | printk(KERN_WARNING "NAND bus width %d instead %d bit\n", | |
ace4dfee | 2005 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
7aa65bfd TG |
2006 | busw ? 16 : 8); |
2007 | return ERR_PTR(-EINVAL); | |
2008 | } | |
61b03bd7 | 2009 | |
7aa65bfd | 2010 | /* Calculate the address shift from the page size */ |
ace4dfee | 2011 | chip->page_shift = ffs(mtd->writesize) - 1; |
7aa65bfd | 2012 | /* Convert chipsize to number of pages per chip -1. */ |
ace4dfee | 2013 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 2014 | |
ace4dfee | 2015 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 2016 | ffs(mtd->erasesize) - 1; |
ace4dfee | 2017 | chip->chip_shift = ffs(chip->chipsize) - 1; |
1da177e4 | 2018 | |
7aa65bfd | 2019 | /* Set the bad block position */ |
ace4dfee | 2020 | chip->badblockpos = mtd->writesize > 512 ? |
7aa65bfd | 2021 | NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS; |
61b03bd7 | 2022 | |
7aa65bfd | 2023 | /* Get chip options, preserve non chip based options */ |
ace4dfee TG |
2024 | chip->options &= ~NAND_CHIPOPTIONS_MSK; |
2025 | chip->options |= nand_flash_ids[i].options & NAND_CHIPOPTIONS_MSK; | |
7aa65bfd TG |
2026 | |
2027 | /* | |
ace4dfee | 2028 | * Set chip as a default. Board drivers can override it, if necessary |
7aa65bfd | 2029 | */ |
ace4dfee | 2030 | chip->options |= NAND_NO_AUTOINCR; |
7aa65bfd | 2031 | |
ace4dfee | 2032 | /* Check if chip is a not a samsung device. Do not clear the |
7aa65bfd TG |
2033 | * options for chips which are not having an extended id. |
2034 | */ | |
2035 | if (*maf_id != NAND_MFR_SAMSUNG && !nand_flash_ids[i].pagesize) | |
ace4dfee | 2036 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; |
7aa65bfd TG |
2037 | |
2038 | /* Check for AND chips with 4 page planes */ | |
ace4dfee TG |
2039 | if (chip->options & NAND_4PAGE_ARRAY) |
2040 | chip->erase_cmd = multi_erase_cmd; | |
7aa65bfd | 2041 | else |
ace4dfee | 2042 | chip->erase_cmd = single_erase_cmd; |
7aa65bfd TG |
2043 | |
2044 | /* Do not replace user supplied command function ! */ | |
ace4dfee TG |
2045 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
2046 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd TG |
2047 | |
2048 | printk(KERN_INFO "NAND device: Manufacturer ID:" | |
2049 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id, | |
2050 | nand_manuf_ids[maf_idx].name, type->name); | |
2051 | ||
2052 | return type; | |
2053 | } | |
2054 | ||
2055 | /* module_text_address() isn't exported, and it's mostly a pointless | |
2056 | test if this is a module _anyway_ -- they'd have to try _really_ hard | |
2057 | to call us from in-kernel code if the core NAND support is modular. */ | |
2058 | #ifdef MODULE | |
2059 | #define caller_is_module() (1) | |
2060 | #else | |
2061 | #define caller_is_module() \ | |
2062 | module_text_address((unsigned long)__builtin_return_address(0)) | |
2063 | #endif | |
2064 | ||
2065 | /** | |
2066 | * nand_scan - [NAND Interface] Scan for the NAND device | |
2067 | * @mtd: MTD device structure | |
2068 | * @maxchips: Number of chips to scan for | |
2069 | * | |
2070 | * This fills out all the uninitialized function pointers | |
2071 | * with the defaults. | |
2072 | * The flash ID is read and the mtd/chip structures are | |
f75e5097 | 2073 | * filled with the appropriate values. |
7aa65bfd TG |
2074 | * The mtd->owner field must be set to the module of the caller |
2075 | * | |
2076 | */ | |
2077 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
2078 | { | |
2079 | int i, busw, nand_maf_id; | |
ace4dfee | 2080 | struct nand_chip *chip = mtd->priv; |
7aa65bfd TG |
2081 | struct nand_flash_dev *type; |
2082 | ||
2083 | /* Many callers got this wrong, so check for it for a while... */ | |
2084 | if (!mtd->owner && caller_is_module()) { | |
2085 | printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n"); | |
2086 | BUG(); | |
1da177e4 LT |
2087 | } |
2088 | ||
7aa65bfd | 2089 | /* Get buswidth to select the correct functions */ |
ace4dfee | 2090 | busw = chip->options & NAND_BUSWIDTH_16; |
7aa65bfd | 2091 | /* Set the default functions */ |
ace4dfee | 2092 | nand_set_defaults(chip, busw); |
7aa65bfd TG |
2093 | |
2094 | /* Read the flash type */ | |
ace4dfee | 2095 | type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id); |
7aa65bfd TG |
2096 | |
2097 | if (IS_ERR(type)) { | |
e0c7d767 | 2098 | printk(KERN_WARNING "No NAND device found!!!\n"); |
ace4dfee | 2099 | chip->select_chip(mtd, -1); |
7aa65bfd | 2100 | return PTR_ERR(type); |
1da177e4 LT |
2101 | } |
2102 | ||
7aa65bfd | 2103 | /* Check for a chip array */ |
e0c7d767 | 2104 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 2105 | chip->select_chip(mtd, i); |
1da177e4 | 2106 | /* Send the command for reading device ID */ |
ace4dfee | 2107 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 2108 | /* Read manufacturer and device IDs */ |
ace4dfee TG |
2109 | if (nand_maf_id != chip->read_byte(mtd) || |
2110 | type->id != chip->read_byte(mtd)) | |
1da177e4 LT |
2111 | break; |
2112 | } | |
2113 | if (i > 1) | |
2114 | printk(KERN_INFO "%d NAND chips detected\n", i); | |
61b03bd7 | 2115 | |
1da177e4 | 2116 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
2117 | chip->numchips = i; |
2118 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 2119 | |
f75e5097 TG |
2120 | /* Preset the internal oob write buffer */ |
2121 | memset(chip->buffers.oobwbuf, 0xff, mtd->oobsize); | |
1da177e4 | 2122 | |
7aa65bfd TG |
2123 | /* |
2124 | * If no default placement scheme is given, select an appropriate one | |
2125 | */ | |
ace4dfee | 2126 | if (!chip->autooob) { |
61b03bd7 | 2127 | switch (mtd->oobsize) { |
1da177e4 | 2128 | case 8: |
ace4dfee | 2129 | chip->autooob = &nand_oob_8; |
1da177e4 LT |
2130 | break; |
2131 | case 16: | |
ace4dfee | 2132 | chip->autooob = &nand_oob_16; |
1da177e4 LT |
2133 | break; |
2134 | case 64: | |
ace4dfee | 2135 | chip->autooob = &nand_oob_64; |
1da177e4 LT |
2136 | break; |
2137 | default: | |
7aa65bfd TG |
2138 | printk(KERN_WARNING "No oob scheme defined for " |
2139 | "oobsize %d\n", mtd->oobsize); | |
1da177e4 LT |
2140 | BUG(); |
2141 | } | |
2142 | } | |
61b03bd7 | 2143 | |
7aa65bfd TG |
2144 | /* |
2145 | * The number of bytes available for the filesystem to place fs | |
2146 | * dependend oob data | |
2147 | */ | |
998cf640 | 2148 | mtd->oobavail = 0; |
ace4dfee TG |
2149 | for (i = 0; chip->autooob->oobfree[i][1]; i++) |
2150 | mtd->oobavail += chip->autooob->oobfree[i][1]; | |
1da177e4 | 2151 | |
61b03bd7 | 2152 | /* |
7aa65bfd TG |
2153 | * check ECC mode, default to software if 3byte/512byte hardware ECC is |
2154 | * selected and we have 256 byte pagesize fallback to software ECC | |
e0c7d767 | 2155 | */ |
ace4dfee | 2156 | switch (chip->ecc.mode) { |
6dfc6d25 | 2157 | case NAND_ECC_HW: |
f5bbdacc TG |
2158 | /* Use standard hwecc read page function ? */ |
2159 | if (!chip->ecc.read_page) | |
2160 | chip->ecc.read_page = nand_read_page_hwecc; | |
f75e5097 TG |
2161 | if (!chip->ecc.write_page) |
2162 | chip->ecc.write_page = nand_write_page_hwecc; | |
f5bbdacc | 2163 | |
6dfc6d25 | 2164 | case NAND_ECC_HW_SYNDROME: |
ace4dfee TG |
2165 | if (!chip->ecc.calculate || !chip->ecc.correct || |
2166 | !chip->ecc.hwctl) { | |
6dfc6d25 TG |
2167 | printk(KERN_WARNING "No ECC functions supplied, " |
2168 | "Hardware ECC not possible\n"); | |
2169 | BUG(); | |
2170 | } | |
f75e5097 | 2171 | /* Use standard syndrome read/write page function ? */ |
f5bbdacc TG |
2172 | if (!chip->ecc.read_page) |
2173 | chip->ecc.read_page = nand_read_page_syndrome; | |
f75e5097 TG |
2174 | if (!chip->ecc.write_page) |
2175 | chip->ecc.write_page = nand_write_page_syndrome; | |
f5bbdacc | 2176 | |
ace4dfee | 2177 | if (mtd->writesize >= chip->ecc.size) |
6dfc6d25 TG |
2178 | break; |
2179 | printk(KERN_WARNING "%d byte HW ECC not possible on " | |
2180 | "%d byte page size, fallback to SW ECC\n", | |
ace4dfee TG |
2181 | chip->ecc.size, mtd->writesize); |
2182 | chip->ecc.mode = NAND_ECC_SOFT; | |
61b03bd7 | 2183 | |
6dfc6d25 | 2184 | case NAND_ECC_SOFT: |
ace4dfee TG |
2185 | chip->ecc.calculate = nand_calculate_ecc; |
2186 | chip->ecc.correct = nand_correct_data; | |
f5bbdacc | 2187 | chip->ecc.read_page = nand_read_page_swecc; |
f75e5097 | 2188 | chip->ecc.write_page = nand_write_page_swecc; |
ace4dfee TG |
2189 | chip->ecc.size = 256; |
2190 | chip->ecc.bytes = 3; | |
1da177e4 | 2191 | break; |
61b03bd7 TG |
2192 | |
2193 | case NAND_ECC_NONE: | |
7aa65bfd TG |
2194 | printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. " |
2195 | "This is not recommended !!\n"); | |
f5bbdacc | 2196 | chip->ecc.read_page = nand_read_page_swecc; |
f75e5097 | 2197 | chip->ecc.write_page = nand_write_page_swecc; |
ace4dfee TG |
2198 | chip->ecc.size = mtd->writesize; |
2199 | chip->ecc.bytes = 0; | |
1da177e4 | 2200 | break; |
1da177e4 | 2201 | default: |
7aa65bfd | 2202 | printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n", |
ace4dfee | 2203 | chip->ecc.mode); |
61b03bd7 | 2204 | BUG(); |
1da177e4 | 2205 | } |
61b03bd7 | 2206 | |
7aa65bfd TG |
2207 | /* |
2208 | * Set the number of read / write steps for one page depending on ECC | |
2209 | * mode | |
2210 | */ | |
ace4dfee TG |
2211 | chip->ecc.steps = mtd->writesize / chip->ecc.size; |
2212 | if(chip->ecc.steps * chip->ecc.size != mtd->writesize) { | |
6dfc6d25 TG |
2213 | printk(KERN_WARNING "Invalid ecc parameters\n"); |
2214 | BUG(); | |
1da177e4 | 2215 | } |
f5bbdacc | 2216 | chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; |
61b03bd7 | 2217 | |
04bbd0ea | 2218 | /* Initialize state */ |
ace4dfee | 2219 | chip->state = FL_READY; |
1da177e4 LT |
2220 | |
2221 | /* De-select the device */ | |
ace4dfee | 2222 | chip->select_chip(mtd, -1); |
1da177e4 LT |
2223 | |
2224 | /* Invalidate the pagebuffer reference */ | |
ace4dfee | 2225 | chip->pagebuf = -1; |
1da177e4 LT |
2226 | |
2227 | /* Fill in remaining MTD driver data */ | |
2228 | mtd->type = MTD_NANDFLASH; | |
5fa43394 | 2229 | mtd->flags = MTD_CAP_NANDFLASH; |
1da177e4 LT |
2230 | mtd->ecctype = MTD_ECC_SW; |
2231 | mtd->erase = nand_erase; | |
2232 | mtd->point = NULL; | |
2233 | mtd->unpoint = NULL; | |
2234 | mtd->read = nand_read; | |
2235 | mtd->write = nand_write; | |
1da177e4 LT |
2236 | mtd->read_oob = nand_read_oob; |
2237 | mtd->write_oob = nand_write_oob; | |
1da177e4 LT |
2238 | mtd->sync = nand_sync; |
2239 | mtd->lock = NULL; | |
2240 | mtd->unlock = NULL; | |
962034f4 VW |
2241 | mtd->suspend = nand_suspend; |
2242 | mtd->resume = nand_resume; | |
1da177e4 LT |
2243 | mtd->block_isbad = nand_block_isbad; |
2244 | mtd->block_markbad = nand_block_markbad; | |
2245 | ||
2246 | /* and make the autooob the default one */ | |
ace4dfee | 2247 | memcpy(&mtd->oobinfo, chip->autooob, sizeof(mtd->oobinfo)); |
1da177e4 | 2248 | |
0040bf38 | 2249 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 2250 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 2251 | return 0; |
1da177e4 LT |
2252 | |
2253 | /* Build bad block table */ | |
ace4dfee | 2254 | return chip->scan_bbt(mtd); |
1da177e4 LT |
2255 | } |
2256 | ||
2257 | /** | |
61b03bd7 | 2258 | * nand_release - [NAND Interface] Free resources held by the NAND device |
1da177e4 LT |
2259 | * @mtd: MTD device structure |
2260 | */ | |
e0c7d767 | 2261 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 2262 | { |
ace4dfee | 2263 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
2264 | |
2265 | #ifdef CONFIG_MTD_PARTITIONS | |
2266 | /* Deregister partitions */ | |
e0c7d767 | 2267 | del_mtd_partitions(mtd); |
1da177e4 LT |
2268 | #endif |
2269 | /* Deregister the device */ | |
e0c7d767 | 2270 | del_mtd_device(mtd); |
1da177e4 | 2271 | |
fa671646 | 2272 | /* Free bad block table memory */ |
ace4dfee | 2273 | kfree(chip->bbt); |
1da177e4 LT |
2274 | } |
2275 | ||
e0c7d767 DW |
2276 | EXPORT_SYMBOL_GPL(nand_scan); |
2277 | EXPORT_SYMBOL_GPL(nand_release); | |
8fe833c1 RP |
2278 | |
2279 | static int __init nand_base_init(void) | |
2280 | { | |
2281 | led_trigger_register_simple("nand-disk", &nand_led_trigger); | |
2282 | return 0; | |
2283 | } | |
2284 | ||
2285 | static void __exit nand_base_exit(void) | |
2286 | { | |
2287 | led_trigger_unregister_simple(nand_led_trigger); | |
2288 | } | |
2289 | ||
2290 | module_init(nand_base_init); | |
2291 | module_exit(nand_base_exit); | |
2292 | ||
e0c7d767 DW |
2293 | MODULE_LICENSE("GPL"); |
2294 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>"); | |
2295 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |