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mtd: nand: remove NAND_BBT_SCANBYTE1AND6 option
[mirror_ubuntu-hirsute-kernel.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
61b03bd7 8 *
1da177e4 9 * Additional technical information is available on
8b2b403c 10 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 11 *
1da177e4 12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 14 *
ace4dfee 15 * Credits:
61b03bd7
TG		 16 * David Woodhouse for adding multichip support
17 *
1da177e4
LT		 18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
ace4dfee 21 * TODO:
1da177e4
LT		 22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
c0b8ba7b 27 * BBT table is not serialized, has to be fixed
1da177e4 28 *
1da177e4
LT		 29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
552d9205 35#include <linux/module.h>
1da177e4
LT		 36#include <linux/delay.h>
37#include <linux/errno.h>
7aa65bfd 38#include <linux/err.h>
1da177e4
LT		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
193bd400 45#include <linux/mtd/nand_bch.h>
1da177e4
LT		 46#include <linux/interrupt.h>
47#include <linux/bitops.h>
8fe833c1 48#include <linux/leds.h>
7351d3a5 49#include <linux/io.h>
1da177e4 50#include <linux/mtd/partitions.h>
1da177e4
LT		 51
52/* Define default oob placement schemes for large and small page devices */
5bd34c09 53static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 54 .eccbytes = 3,
55 .eccpos = {0, 1, 2},
5bd34c09
TG		 56 .oobfree = {
57 {.offset = 3,
58 .length = 2},
59 {.offset = 6,
f8ac0414 60 .length = 2} }
1da177e4
LT		 61};
62
5bd34c09 63static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 64 .eccbytes = 6,
65 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 66 .oobfree = {
67 {.offset = 8,
f8ac0414 68 . length = 8} }
1da177e4
LT		 69};
70
5bd34c09 71static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 72 .eccbytes = 24,
73 .eccpos = {
e0c7d767
DW		 74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 77 .oobfree = {
78 {.offset = 2,
f8ac0414 79 .length = 38} }
1da177e4
LT		 80};
81
81ec5364
TG		 82static struct nand_ecclayout nand_oob_128 = {
83 .eccbytes = 48,
84 .eccpos = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
91 .oobfree = {
92 {.offset = 2,
f8ac0414 93 .length = 78} }
81ec5364
TG		 94};
95
ace4dfee 96static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
2c0a2bed 97 int new_state);
1da177e4 98
8593fbc6
TG		 99static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
100 struct mtd_oob_ops *ops);
101
d470a97c 102/*
8e87d782 103 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 104 * compiled away when LED support is disabled.
105 */
106DEFINE_LED_TRIGGER(nand_led_trigger);
107
6fe5a6ac
VS		 108static int check_offs_len(struct mtd_info *mtd,
109 loff_t ofs, uint64_t len)
110{
111 struct nand_chip *chip = mtd->priv;
112 int ret = 0;
113
114 /* Start address must align on block boundary */
115 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
116 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
117 ret = -EINVAL;
118 }
119
120 /* Length must align on block boundary */
121 if (len & ((1 << chip->phys_erase_shift) - 1)) {
122 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
123 __func__);
124 ret = -EINVAL;
125 }
126
127 /* Do not allow past end of device */
128 if (ofs + len > mtd->size) {
129 DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
130 __func__);
131 ret = -EINVAL;
132 }
133
134 return ret;
135}
136
1da177e4
LT		 137/**
138 * nand_release_device - [GENERIC] release chip
139 * @mtd: MTD device structure
61b03bd7
TG		 140 *
141 * Deselect, release chip lock and wake up anyone waiting on the device
1da177e4 142 */
e0c7d767 143static void nand_release_device(struct mtd_info *mtd)
1da177e4 144{
ace4dfee 145 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 146
147 /* De-select the NAND device */
ace4dfee 148 chip->select_chip(mtd, -1);
0dfc6246 149
a36ed299 150 /* Release the controller and the chip */
ace4dfee
TG		 151 spin_lock(&chip->controller->lock);
152 chip->controller->active = NULL;
153 chip->state = FL_READY;
154 wake_up(&chip->controller->wq);
155 spin_unlock(&chip->controller->lock);
1da177e4
LT		 156}
157
158/**
159 * nand_read_byte - [DEFAULT] read one byte from the chip
160 * @mtd: MTD device structure
161 *
162 * Default read function for 8bit buswith
163 */
58dd8f2b 164static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 165{
ace4dfee
TG		 166 struct nand_chip *chip = mtd->priv;
167 return readb(chip->IO_ADDR_R);
1da177e4
LT		 168}
169
1da177e4
LT		 170/**
171 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
172 * @mtd: MTD device structure
173 *
61b03bd7 174 * Default read function for 16bit buswith with
1da177e4
LT		 175 * endianess conversion
176 */
58dd8f2b 177static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 178{
ace4dfee
TG		 179 struct nand_chip *chip = mtd->priv;
180 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 181}
182
1da177e4
LT		 183/**
184 * nand_read_word - [DEFAULT] read one word from the chip
185 * @mtd: MTD device structure
186 *
61b03bd7 187 * Default read function for 16bit buswith without
1da177e4
LT		 188 * endianess conversion
189 */
190static u16 nand_read_word(struct mtd_info *mtd)
191{
ace4dfee
TG		 192 struct nand_chip *chip = mtd->priv;
193 return readw(chip->IO_ADDR_R);
1da177e4
LT		 194}
195
1da177e4
LT		 196/**
197 * nand_select_chip - [DEFAULT] control CE line
198 * @mtd: MTD device structure
844d3b42 199 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 200 *
201 * Default select function for 1 chip devices.
202 */
ace4dfee 203static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 204{
ace4dfee
TG		 205 struct nand_chip *chip = mtd->priv;
206
207 switch (chipnr) {
1da177e4 208 case -1:
ace4dfee 209 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 210 break;
211 case 0:
1da177e4
LT		 212 break;
213
214 default:
215 BUG();
216 }
217}
218
219/**
220 * nand_write_buf - [DEFAULT] write buffer to chip
221 * @mtd: MTD device structure
222 * @buf: data buffer
223 * @len: number of bytes to write
224 *
225 * Default write function for 8bit buswith
226 */
58dd8f2b 227static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 228{
229 int i;
ace4dfee 230 struct nand_chip *chip = mtd->priv;
1da177e4 231
e0c7d767 232 for (i = 0; i < len; i++)
ace4dfee 233 writeb(buf[i], chip->IO_ADDR_W);
1da177e4
LT		 234}
235
236/**
61b03bd7 237 * nand_read_buf - [DEFAULT] read chip data into buffer
1da177e4
LT		 238 * @mtd: MTD device structure
239 * @buf: buffer to store date
240 * @len: number of bytes to read
241 *
242 * Default read function for 8bit buswith
243 */
58dd8f2b 244static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 245{
246 int i;
ace4dfee 247 struct nand_chip *chip = mtd->priv;
1da177e4 248
e0c7d767 249 for (i = 0; i < len; i++)
ace4dfee 250 buf[i] = readb(chip->IO_ADDR_R);
1da177e4
LT		 251}
252
253/**
61b03bd7 254 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
1da177e4
LT		 255 * @mtd: MTD device structure
256 * @buf: buffer containing the data to compare
257 * @len: number of bytes to compare
258 *
259 * Default verify function for 8bit buswith
260 */
58dd8f2b 261static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 262{
263 int i;
ace4dfee 264 struct nand_chip *chip = mtd->priv;
1da177e4 265
e0c7d767 266 for (i = 0; i < len; i++)
ace4dfee 267 if (buf[i] != readb(chip->IO_ADDR_R))
1da177e4 268 return -EFAULT;
1da177e4
LT		 269 return 0;
270}
271
272/**
273 * nand_write_buf16 - [DEFAULT] write buffer to chip
274 * @mtd: MTD device structure
275 * @buf: data buffer
276 * @len: number of bytes to write
277 *
278 * Default write function for 16bit buswith
279 */
58dd8f2b 280static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 281{
282 int i;
ace4dfee 283 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 284 u16 *p = (u16 *) buf;
285 len >>= 1;
61b03bd7 286
e0c7d767 287 for (i = 0; i < len; i++)
ace4dfee 288 writew(p[i], chip->IO_ADDR_W);
61b03bd7 289
1da177e4
LT		 290}
291
292/**
61b03bd7 293 * nand_read_buf16 - [DEFAULT] read chip data into buffer
1da177e4
LT		 294 * @mtd: MTD device structure
295 * @buf: buffer to store date
296 * @len: number of bytes to read
297 *
298 * Default read function for 16bit buswith
299 */
58dd8f2b 300static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 301{
302 int i;
ace4dfee 303 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 304 u16 *p = (u16 *) buf;
305 len >>= 1;
306
e0c7d767 307 for (i = 0; i < len; i++)
ace4dfee 308 p[i] = readw(chip->IO_ADDR_R);
1da177e4
LT		 309}
310
311/**
61b03bd7 312 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
1da177e4
LT		 313 * @mtd: MTD device structure
314 * @buf: buffer containing the data to compare
315 * @len: number of bytes to compare
316 *
317 * Default verify function for 16bit buswith
318 */
58dd8f2b 319static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 320{
321 int i;
ace4dfee 322 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 323 u16 *p = (u16 *) buf;
324 len >>= 1;
325
e0c7d767 326 for (i = 0; i < len; i++)
ace4dfee 327 if (p[i] != readw(chip->IO_ADDR_R))
1da177e4
LT		 328 return -EFAULT;
329
330 return 0;
331}
332
333/**
334 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
335 * @mtd: MTD device structure
336 * @ofs: offset from device start
337 * @getchip: 0, if the chip is already selected
338 *
61b03bd7 339 * Check, if the block is bad.
1da177e4
LT		 340 */
341static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
342{
343 int page, chipnr, res = 0;
ace4dfee 344 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 345 u16 bad;
346
30fe8115 347 if (chip->options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 348 ofs += mtd->erasesize - mtd->writesize;
349
1a12f46a
TK		 350 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
351
1da177e4 352 if (getchip) {
ace4dfee 353 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 354
ace4dfee 355 nand_get_device(chip, mtd, FL_READING);
1da177e4
LT		 356
357 /* Select the NAND device */
ace4dfee 358 chip->select_chip(mtd, chipnr);
1a12f46a 359 }
1da177e4 360
ace4dfee
TG		 361 if (chip->options & NAND_BUSWIDTH_16) {
362 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
1a12f46a 363 page);
ace4dfee
TG		 364 bad = cpu_to_le16(chip->read_word(mtd));
365 if (chip->badblockpos & 0x1)
49196f33 366 bad >>= 8;
e0b58d0a
ML		 367 else
368 bad &= 0xFF;
1da177e4 369 } else {
1a12f46a 370 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
e0b58d0a 371 bad = chip->read_byte(mtd);
1da177e4 372 }
61b03bd7 373
e0b58d0a
ML		 374 if (likely(chip->badblockbits == 8))
375 res = bad != 0xFF;
376 else
377 res = hweight8(bad) < chip->badblockbits;
378
ace4dfee 379 if (getchip)
1da177e4 380 nand_release_device(mtd);
61b03bd7 381
1da177e4
LT		 382 return res;
383}
384
385/**
386 * nand_default_block_markbad - [DEFAULT] mark a block bad
387 * @mtd: MTD device structure
388 * @ofs: offset from device start
389 *
390 * This is the default implementation, which can be overridden by
391 * a hardware specific driver.
392*/
393static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
394{
ace4dfee 395 struct nand_chip *chip = mtd->priv;
58dd8f2b 396 uint8_t buf[2] = { 0, 0 };
02ed70bb 397 int block, ret, i = 0;
61b03bd7 398
30fe8115 399 if (chip->options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 400 ofs += mtd->erasesize - mtd->writesize;
401
1da177e4 402 /* Get block number */
4226b510 403 block = (int)(ofs >> chip->bbt_erase_shift);
ace4dfee
TG		 404 if (chip->bbt)
405 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1da177e4
LT		 406
407 /* Do we have a flash based bad block table ? */
ace4dfee 408 if (chip->options & NAND_USE_FLASH_BBT)
f1a28c02
TG		 409 ret = nand_update_bbt(mtd, ofs);
410 else {
c0b8ba7b 411 nand_get_device(chip, mtd, FL_WRITING);
f1a28c02 412
a0dc5529
BN		 413 /*
414 * Write to first two pages if necessary. If we write to more
415 * than one location, the first error encountered quits the
416 * procedure. We write two bytes per location, so we dont have
417 * to mess with 16 bit access.
02ed70bb
BN		 418 */
419 do {
420 chip->ops.len = chip->ops.ooblen = 2;
421 chip->ops.datbuf = NULL;
422 chip->ops.oobbuf = buf;
423 chip->ops.ooboffs = chip->badblockpos & ~0x01;
424
425 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
426
02ed70bb
BN		 427 i++;
428 ofs += mtd->writesize;
429 } while (!ret && (chip->options & NAND_BBT_SCAN2NDPAGE) &&
430 i < 2);
431
c0b8ba7b 432 nand_release_device(mtd);
f1a28c02
TG		 433 }
434 if (!ret)
435 mtd->ecc_stats.badblocks++;
c0b8ba7b 436
f1a28c02 437 return ret;
1da177e4
LT		 438}
439
61b03bd7 440/**
1da177e4
LT		 441 * nand_check_wp - [GENERIC] check if the chip is write protected
442 * @mtd: MTD device structure
61b03bd7 443 * Check, if the device is write protected
1da177e4 444 *
61b03bd7 445 * The function expects, that the device is already selected
1da177e4 446 */
e0c7d767 447static int nand_check_wp(struct mtd_info *mtd)
1da177e4 448{
ace4dfee 449 struct nand_chip *chip = mtd->priv;
93edbad6
ML		 450
451 /* broken xD cards report WP despite being writable */
452 if (chip->options & NAND_BROKEN_XD)
453 return 0;
454
1da177e4 455 /* Check the WP bit */
ace4dfee
TG		 456 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
457 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 458}
459
460/**
461 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
462 * @mtd: MTD device structure
463 * @ofs: offset from device start
464 * @getchip: 0, if the chip is already selected
465 * @allowbbt: 1, if its allowed to access the bbt area
466 *
467 * Check, if the block is bad. Either by reading the bad block table or
468 * calling of the scan function.
469 */
2c0a2bed
TG		 470static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
471 int allowbbt)
1da177e4 472{
ace4dfee 473 struct nand_chip *chip = mtd->priv;
61b03bd7 474
ace4dfee
TG		 475 if (!chip->bbt)
476 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 477
1da177e4 478 /* Return info from the table */
e0c7d767 479 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 480}
481
2af7c653
SK		 482/**
483 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
484 * @mtd: MTD device structure
485 * @timeo: Timeout
486 *
487 * Helper function for nand_wait_ready used when needing to wait in interrupt
488 * context.
489 */
490static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
491{
492 struct nand_chip *chip = mtd->priv;
493 int i;
494
495 /* Wait for the device to get ready */
496 for (i = 0; i < timeo; i++) {
497 if (chip->dev_ready(mtd))
498 break;
499 touch_softlockup_watchdog();
500 mdelay(1);
501 }
502}
503
61b03bd7 504/*
3b88775c
TG		 505 * Wait for the ready pin, after a command
506 * The timeout is catched later.
507 */
4b648b02 508void nand_wait_ready(struct mtd_info *mtd)
3b88775c 509{
ace4dfee 510 struct nand_chip *chip = mtd->priv;
e0c7d767 511 unsigned long timeo = jiffies + 2;
3b88775c 512
2af7c653
SK		 513 /* 400ms timeout */
514 if (in_interrupt() || oops_in_progress)
515 return panic_nand_wait_ready(mtd, 400);
516
8fe833c1 517 led_trigger_event(nand_led_trigger, LED_FULL);
3b88775c
TG		 518 /* wait until command is processed or timeout occures */
519 do {
ace4dfee 520 if (chip->dev_ready(mtd))
8fe833c1 521 break;
8446f1d3 522 touch_softlockup_watchdog();
61b03bd7 523 } while (time_before(jiffies, timeo));
8fe833c1 524 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 525}
4b648b02 526EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 527
1da177e4
LT		 528/**
529 * nand_command - [DEFAULT] Send command to NAND device
530 * @mtd: MTD device structure
531 * @command: the command to be sent
532 * @column: the column address for this command, -1 if none
533 * @page_addr: the page address for this command, -1 if none
534 *
535 * Send command to NAND device. This function is used for small page
536 * devices (256/512 Bytes per page)
537 */
7abd3ef9
TG		 538static void nand_command(struct mtd_info *mtd, unsigned int command,
539 int column, int page_addr)
1da177e4 540{
ace4dfee 541 register struct nand_chip *chip = mtd->priv;
7abd3ef9 542 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 543
1da177e4
LT		 544 /*
545 * Write out the command to the device.
546 */
547 if (command == NAND_CMD_SEQIN) {
548 int readcmd;
549
28318776 550 if (column >= mtd->writesize) {
1da177e4 551 /* OOB area */
28318776 552 column -= mtd->writesize;
1da177e4
LT		 553 readcmd = NAND_CMD_READOOB;
554 } else if (column < 256) {
555 /* First 256 bytes --> READ0 */
556 readcmd = NAND_CMD_READ0;
557 } else {
558 column -= 256;
559 readcmd = NAND_CMD_READ1;
560 }
ace4dfee 561 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 562 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 563 }
ace4dfee 564 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 565
7abd3ef9
TG		 566 /*
567 * Address cycle, when necessary
568 */
569 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
570 /* Serially input address */
571 if (column != -1) {
572 /* Adjust columns for 16 bit buswidth */
ace4dfee 573 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 574 column >>= 1;
ace4dfee 575 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 576 ctrl &= ~NAND_CTRL_CHANGE;
577 }
578 if (page_addr != -1) {
ace4dfee 579 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 580 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 581 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 582 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 583 if (chip->chipsize > (32 << 20))
584 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 585 }
ace4dfee 586 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 587
588 /*
589 * program and erase have their own busy handlers
1da177e4 590 * status and sequential in needs no delay
e0c7d767 591 */
1da177e4 592 switch (command) {
61b03bd7 593
1da177e4
LT		 594 case NAND_CMD_PAGEPROG:
595 case NAND_CMD_ERASE1:
596 case NAND_CMD_ERASE2:
597 case NAND_CMD_SEQIN:
598 case NAND_CMD_STATUS:
599 return;
600
601 case NAND_CMD_RESET:
ace4dfee 602 if (chip->dev_ready)
1da177e4 603 break;
ace4dfee
TG		 604 udelay(chip->chip_delay);
605 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 606 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 607 chip->cmd_ctrl(mtd,
608 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 609 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
610 ;
1da177e4
LT		 611 return;
612
e0c7d767 613 /* This applies to read commands */
1da177e4 614 default:
61b03bd7 615 /*
1da177e4
LT		 616 * If we don't have access to the busy pin, we apply the given
617 * command delay
e0c7d767 618 */
ace4dfee
TG		 619 if (!chip->dev_ready) {
620 udelay(chip->chip_delay);
1da177e4 621 return;
61b03bd7 622 }
1da177e4 623 }
1da177e4
LT		 624 /* Apply this short delay always to ensure that we do wait tWB in
625 * any case on any machine. */
e0c7d767 626 ndelay(100);
3b88775c
TG		 627
628 nand_wait_ready(mtd);
1da177e4
LT		 629}
630
631/**
632 * nand_command_lp - [DEFAULT] Send command to NAND large page device
633 * @mtd: MTD device structure
634 * @command: the command to be sent
635 * @column: the column address for this command, -1 if none
636 * @page_addr: the page address for this command, -1 if none
637 *
7abd3ef9
TG		 638 * Send command to NAND device. This is the version for the new large page
639 * devices We dont have the separate regions as we have in the small page
640 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 641 */
7abd3ef9
TG		 642static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
643 int column, int page_addr)
1da177e4 644{
ace4dfee 645 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 646
647 /* Emulate NAND_CMD_READOOB */
648 if (command == NAND_CMD_READOOB) {
28318776 649 column += mtd->writesize;
1da177e4
LT		 650 command = NAND_CMD_READ0;
651 }
61b03bd7 652
7abd3ef9 653 /* Command latch cycle */
ace4dfee 654 chip->cmd_ctrl(mtd, command & 0xff,
7abd3ef9 655 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 656
657 if (column != -1 || page_addr != -1) {
7abd3ef9 658 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 659
660 /* Serially input address */
661 if (column != -1) {
662 /* Adjust columns for 16 bit buswidth */
ace4dfee 663 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 664 column >>= 1;
ace4dfee 665 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 666 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 667 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 668 }
1da177e4 669 if (page_addr != -1) {
ace4dfee
TG		 670 chip->cmd_ctrl(mtd, page_addr, ctrl);
671 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 672 NAND_NCE | NAND_ALE);
1da177e4 673 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 674 if (chip->chipsize > (128 << 20))
675 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 676 NAND_NCE | NAND_ALE);
1da177e4 677 }
1da177e4 678 }
ace4dfee 679 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 680
681 /*
682 * program and erase have their own busy handlers
30f464b7
DM		 683 * status, sequential in, and deplete1 need no delay
684 */
1da177e4 685 switch (command) {
61b03bd7 686
1da177e4
LT		 687 case NAND_CMD_CACHEDPROG:
688 case NAND_CMD_PAGEPROG:
689 case NAND_CMD_ERASE1:
690 case NAND_CMD_ERASE2:
691 case NAND_CMD_SEQIN:
7bc3312b 692 case NAND_CMD_RNDIN:
1da177e4 693 case NAND_CMD_STATUS:
30f464b7 694 case NAND_CMD_DEPLETE1:
1da177e4
LT		 695 return;
696
e0c7d767
DW		 697 /*
698 * read error status commands require only a short delay
699 */
30f464b7
DM		 700 case NAND_CMD_STATUS_ERROR:
701 case NAND_CMD_STATUS_ERROR0:
702 case NAND_CMD_STATUS_ERROR1:
703 case NAND_CMD_STATUS_ERROR2:
704 case NAND_CMD_STATUS_ERROR3:
ace4dfee 705 udelay(chip->chip_delay);
30f464b7 706 return;
1da177e4
LT		 707
708 case NAND_CMD_RESET:
ace4dfee 709 if (chip->dev_ready)
1da177e4 710 break;
ace4dfee 711 udelay(chip->chip_delay);
12efdde3
TG		 712 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
713 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
714 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
715 NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 716 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
717 ;
1da177e4
LT		 718 return;
719
7bc3312b
TG		 720 case NAND_CMD_RNDOUT:
721 /* No ready / busy check necessary */
722 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
723 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
724 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
725 NAND_NCE | NAND_CTRL_CHANGE);
726 return;
727
1da177e4 728 case NAND_CMD_READ0:
12efdde3
TG		 729 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
730 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
731 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
732 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 733
e0c7d767 734 /* This applies to read commands */
1da177e4 735 default:
61b03bd7 736 /*
1da177e4
LT		 737 * If we don't have access to the busy pin, we apply the given
738 * command delay
e0c7d767 739 */
ace4dfee
TG		 740 if (!chip->dev_ready) {
741 udelay(chip->chip_delay);
1da177e4 742 return;
61b03bd7 743 }
1da177e4 744 }
3b88775c 745
1da177e4
LT		 746 /* Apply this short delay always to ensure that we do wait tWB in
747 * any case on any machine. */
e0c7d767 748 ndelay(100);
3b88775c
TG		 749
750 nand_wait_ready(mtd);
1da177e4
LT		 751}
752
2af7c653
SK		 753/**
754 * panic_nand_get_device - [GENERIC] Get chip for selected access
755 * @chip: the nand chip descriptor
756 * @mtd: MTD device structure
757 * @new_state: the state which is requested
758 *
759 * Used when in panic, no locks are taken.
760 */
761static void panic_nand_get_device(struct nand_chip *chip,
762 struct mtd_info *mtd, int new_state)
763{
764 /* Hardware controller shared among independend devices */
765 chip->controller->active = chip;
766 chip->state = new_state;
767}
768
1da177e4
LT		 769/**
770 * nand_get_device - [GENERIC] Get chip for selected access
844d3b42 771 * @chip: the nand chip descriptor
1da177e4 772 * @mtd: MTD device structure
61b03bd7 773 * @new_state: the state which is requested
1da177e4
LT		 774 *
775 * Get the device and lock it for exclusive access
776 */
2c0a2bed 777static int
ace4dfee 778nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
1da177e4 779{
ace4dfee
TG		 780 spinlock_t *lock = &chip->controller->lock;
781 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 782 DECLARE_WAITQUEUE(wait, current);
7351d3a5 783retry:
0dfc6246
TG		 784 spin_lock(lock);
785
b8b3ee9a 786 /* Hardware controller shared among independent devices */
ace4dfee
TG		 787 if (!chip->controller->active)
788 chip->controller->active = chip;
a36ed299 789
ace4dfee
TG		 790 if (chip->controller->active == chip && chip->state == FL_READY) {
791 chip->state = new_state;
0dfc6246 792 spin_unlock(lock);
962034f4
VW		 793 return 0;
794 }
795 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 796 if (chip->controller->active->state == FL_PM_SUSPENDED) {
797 chip->state = FL_PM_SUSPENDED;
798 spin_unlock(lock);
799 return 0;
6b0d9a84 800 }
0dfc6246
TG		 801 }
802 set_current_state(TASK_UNINTERRUPTIBLE);
803 add_wait_queue(wq, &wait);
804 spin_unlock(lock);
805 schedule();
806 remove_wait_queue(wq, &wait);
1da177e4
LT		 807 goto retry;
808}
809
2af7c653
SK		 810/**
811 * panic_nand_wait - [GENERIC] wait until the command is done
812 * @mtd: MTD device structure
813 * @chip: NAND chip structure
814 * @timeo: Timeout
815 *
816 * Wait for command done. This is a helper function for nand_wait used when
817 * we are in interrupt context. May happen when in panic and trying to write
b595076a 818 * an oops through mtdoops.
2af7c653
SK		 819 */
820static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
821 unsigned long timeo)
822{
823 int i;
824 for (i = 0; i < timeo; i++) {
825 if (chip->dev_ready) {
826 if (chip->dev_ready(mtd))
827 break;
828 } else {
829 if (chip->read_byte(mtd) & NAND_STATUS_READY)
830 break;
831 }
832 mdelay(1);
f8ac0414 833 }
2af7c653
SK		 834}
835
1da177e4
LT		 836/**
837 * nand_wait - [DEFAULT] wait until the command is done
838 * @mtd: MTD device structure
844d3b42 839 * @chip: NAND chip structure
1da177e4
LT		 840 *
841 * Wait for command done. This applies to erase and program only
61b03bd7 842 * Erase can take up to 400ms and program up to 20ms according to
1da177e4 843 * general NAND and SmartMedia specs
844d3b42 844 */
7bc3312b 845static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 846{
847
e0c7d767 848 unsigned long timeo = jiffies;
7bc3312b 849 int status, state = chip->state;
61b03bd7 850
1da177e4 851 if (state == FL_ERASING)
e0c7d767 852 timeo += (HZ * 400) / 1000;
1da177e4 853 else
e0c7d767 854 timeo += (HZ * 20) / 1000;
1da177e4 855
8fe833c1
RP		 856 led_trigger_event(nand_led_trigger, LED_FULL);
857
1da177e4
LT		 858 /* Apply this short delay always to ensure that we do wait tWB in
859 * any case on any machine. */
e0c7d767 860 ndelay(100);
1da177e4 861
ace4dfee
TG		 862 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
863 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
61b03bd7 864 else
ace4dfee 865 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 866
2af7c653
SK		 867 if (in_interrupt() || oops_in_progress)
868 panic_nand_wait(mtd, chip, timeo);
869 else {
870 while (time_before(jiffies, timeo)) {
871 if (chip->dev_ready) {
872 if (chip->dev_ready(mtd))
873 break;
874 } else {
875 if (chip->read_byte(mtd) & NAND_STATUS_READY)
876 break;
877 }
878 cond_resched();
1da177e4 879 }
1da177e4 880 }
8fe833c1
RP		 881 led_trigger_event(nand_led_trigger, LED_OFF);
882
ace4dfee 883 status = (int)chip->read_byte(mtd);
1da177e4
LT		 884 return status;
885}
886
7d70f334 887/**
b6d676db 888 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
7d70f334 889 *
b6d676db
RD		 890 * @mtd: mtd info
891 * @ofs: offset to start unlock from
892 * @len: length to unlock
893 * @invert: when = 0, unlock the range of blocks within the lower and
7d70f334 894 * upper boundary address
b6d676db 895 * when = 1, unlock the range of blocks outside the boundaries
7d70f334
VS		 896 * of the lower and upper boundary address
897 *
b6d676db 898 * return - unlock status
7d70f334
VS		 899 */
900static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
901 uint64_t len, int invert)
902{
903 int ret = 0;
904 int status, page;
905 struct nand_chip *chip = mtd->priv;
906
907 /* Submit address of first page to unlock */
908 page = ofs >> chip->page_shift;
909 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
910
911 /* Submit address of last page to unlock */
912 page = (ofs + len) >> chip->page_shift;
913 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
914 (page | invert) & chip->pagemask);
915
916 /* Call wait ready function */
917 status = chip->waitfunc(mtd, chip);
918 udelay(1000);
919 /* See if device thinks it succeeded */
920 if (status & 0x01) {
921 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
922 __func__, status);
923 ret = -EIO;
924 }
925
926 return ret;
927}
928
929/**
b6d676db 930 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
7d70f334 931 *
b6d676db
RD		 932 * @mtd: mtd info
933 * @ofs: offset to start unlock from
934 * @len: length to unlock
7d70f334 935 *
b6d676db 936 * return - unlock status
7d70f334
VS		 937 */
938int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
939{
940 int ret = 0;
941 int chipnr;
942 struct nand_chip *chip = mtd->priv;
943
944 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
945 __func__, (unsigned long long)ofs, len);
946
947 if (check_offs_len(mtd, ofs, len))
948 ret = -EINVAL;
949
950 /* Align to last block address if size addresses end of the device */
951 if (ofs + len == mtd->size)
952 len -= mtd->erasesize;
953
954 nand_get_device(chip, mtd, FL_UNLOCKING);
955
956 /* Shift to get chip number */
957 chipnr = ofs >> chip->chip_shift;
958
959 chip->select_chip(mtd, chipnr);
960
961 /* Check, if it is write protected */
962 if (nand_check_wp(mtd)) {
963 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
964 __func__);
965 ret = -EIO;
966 goto out;
967 }
968
969 ret = __nand_unlock(mtd, ofs, len, 0);
970
971out:
7d70f334
VS		 972 nand_release_device(mtd);
973
974 return ret;
975}
7351d3a5 976EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 977
978/**
b6d676db 979 * nand_lock - [REPLACEABLE] locks all blocks present in the device
7d70f334 980 *
b6d676db
RD		 981 * @mtd: mtd info
982 * @ofs: offset to start unlock from
983 * @len: length to unlock
7d70f334 984 *
b6d676db 985 * return - lock status
7d70f334 986 *
b6d676db
RD		 987 * This feature is not supported in many NAND parts. 'Micron' NAND parts
988 * do have this feature, but it allows only to lock all blocks, not for
7d70f334
VS		 989 * specified range for block.
990 *
991 * Implementing 'lock' feature by making use of 'unlock', for now.
992 */
993int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
994{
995 int ret = 0;
996 int chipnr, status, page;
997 struct nand_chip *chip = mtd->priv;
998
999 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
1000 __func__, (unsigned long long)ofs, len);
1001
1002 if (check_offs_len(mtd, ofs, len))
1003 ret = -EINVAL;
1004
1005 nand_get_device(chip, mtd, FL_LOCKING);
1006
1007 /* Shift to get chip number */
1008 chipnr = ofs >> chip->chip_shift;
1009
1010 chip->select_chip(mtd, chipnr);
1011
1012 /* Check, if it is write protected */
1013 if (nand_check_wp(mtd)) {
1014 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
1015 __func__);
1016 status = MTD_ERASE_FAILED;
1017 ret = -EIO;
1018 goto out;
1019 }
1020
1021 /* Submit address of first page to lock */
1022 page = ofs >> chip->page_shift;
1023 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1024
1025 /* Call wait ready function */
1026 status = chip->waitfunc(mtd, chip);
1027 udelay(1000);
1028 /* See if device thinks it succeeded */
1029 if (status & 0x01) {
1030 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
1031 __func__, status);
1032 ret = -EIO;
1033 goto out;
1034 }
1035
1036 ret = __nand_unlock(mtd, ofs, len, 0x1);
1037
1038out:
7d70f334
VS		 1039 nand_release_device(mtd);
1040
1041 return ret;
1042}
7351d3a5 1043EXPORT_SYMBOL(nand_lock);
7d70f334 1044
8593fbc6
TG		 1045/**
1046 * nand_read_page_raw - [Intern] read raw page data without ecc
1047 * @mtd: mtd info structure
1048 * @chip: nand chip info structure
1049 * @buf: buffer to store read data
58475fb9 1050 * @page: page number to read
52ff49df
DB		 1051 *
1052 * Not for syndrome calculating ecc controllers, which use a special oob layout
8593fbc6
TG		 1053 */
1054static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1055 uint8_t *buf, int page)
8593fbc6
TG		 1056{
1057 chip->read_buf(mtd, buf, mtd->writesize);
1058 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1059 return 0;
1060}
1061
52ff49df
DB		 1062/**
1063 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
1064 * @mtd: mtd info structure
1065 * @chip: nand chip info structure
1066 * @buf: buffer to store read data
58475fb9 1067 * @page: page number to read
52ff49df
DB		 1068 *
1069 * We need a special oob layout and handling even when OOB isn't used.
1070 */
7351d3a5
FF		 1071static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1072 struct nand_chip *chip,
1073 uint8_t *buf, int page)
52ff49df
DB		 1074{
1075 int eccsize = chip->ecc.size;
1076 int eccbytes = chip->ecc.bytes;
1077 uint8_t *oob = chip->oob_poi;
1078 int steps, size;
1079
1080 for (steps = chip->ecc.steps; steps > 0; steps--) {
1081 chip->read_buf(mtd, buf, eccsize);
1082 buf += eccsize;
1083
1084 if (chip->ecc.prepad) {
1085 chip->read_buf(mtd, oob, chip->ecc.prepad);
1086 oob += chip->ecc.prepad;
1087 }
1088
1089 chip->read_buf(mtd, oob, eccbytes);
1090 oob += eccbytes;
1091
1092 if (chip->ecc.postpad) {
1093 chip->read_buf(mtd, oob, chip->ecc.postpad);
1094 oob += chip->ecc.postpad;
1095 }
1096 }
1097
1098 size = mtd->oobsize - (oob - chip->oob_poi);
1099 if (size)
1100 chip->read_buf(mtd, oob, size);
1101
1102 return 0;
1103}
1104
1da177e4 1105/**
d29ebdbe 1106 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
f5bbdacc
TG		 1107 * @mtd: mtd info structure
1108 * @chip: nand chip info structure
1109 * @buf: buffer to store read data
58475fb9 1110 * @page: page number to read
068e3c0a 1111 */
f5bbdacc 1112static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1113 uint8_t *buf, int page)
1da177e4 1114{
f5bbdacc
TG		 1115 int i, eccsize = chip->ecc.size;
1116 int eccbytes = chip->ecc.bytes;
1117 int eccsteps = chip->ecc.steps;
1118 uint8_t *p = buf;
4bf63fcb
DW		 1119 uint8_t *ecc_calc = chip->buffers->ecccalc;
1120 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1121 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc 1122
46a8cf2d 1123 chip->ecc.read_page_raw(mtd, chip, buf, page);
f5bbdacc
TG		 1124
1125 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1126 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1127
1128 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1129 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1130
1131 eccsteps = chip->ecc.steps;
1132 p = buf;
1133
1134 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1135 int stat;
1136
1137 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1138 if (stat < 0)
f5bbdacc
TG		 1139 mtd->ecc_stats.failed++;
1140 else
1141 mtd->ecc_stats.corrected += stat;
1142 }
1143 return 0;
22c60f5f 1144}
1da177e4 1145
3d459559
AK		 1146/**
1147 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
1148 * @mtd: mtd info structure
1149 * @chip: nand chip info structure
17c1d2be
AK		 1150 * @data_offs: offset of requested data within the page
1151 * @readlen: data length
1152 * @bufpoi: buffer to store read data
3d459559 1153 */
7351d3a5
FF		 1154static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1155 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
3d459559
AK		 1156{
1157 int start_step, end_step, num_steps;
1158 uint32_t *eccpos = chip->ecc.layout->eccpos;
1159 uint8_t *p;
1160 int data_col_addr, i, gaps = 0;
1161 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1162 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
7351d3a5 1163 int index = 0;
3d459559
AK		 1164
1165 /* Column address wihin the page aligned to ECC size (256bytes). */
1166 start_step = data_offs / chip->ecc.size;
1167 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1168 num_steps = end_step - start_step + 1;
1169
1170 /* Data size aligned to ECC ecc.size*/
1171 datafrag_len = num_steps * chip->ecc.size;
1172 eccfrag_len = num_steps * chip->ecc.bytes;
1173
1174 data_col_addr = start_step * chip->ecc.size;
1175 /* If we read not a page aligned data */
1176 if (data_col_addr != 0)
1177 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1178
1179 p = bufpoi + data_col_addr;
1180 chip->read_buf(mtd, p, datafrag_len);
1181
1182 /* Calculate ECC */
1183 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1184 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1185
1186 /* The performance is faster if to position offsets
1187 according to ecc.pos. Let make sure here that
1188 there are no gaps in ecc positions */
1189 for (i = 0; i < eccfrag_len - 1; i++) {
1190 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1191 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1192 gaps = 1;
1193 break;
1194 }
1195 }
1196 if (gaps) {
1197 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1198 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1199 } else {
1200 /* send the command to read the particular ecc bytes */
1201 /* take care about buswidth alignment in read_buf */
7351d3a5
FF		 1202 index = start_step * chip->ecc.bytes;
1203
1204 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1205 aligned_len = eccfrag_len;
7351d3a5 1206 if (eccpos[index] & (busw - 1))
3d459559 1207 aligned_len++;
7351d3a5 1208 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1209 aligned_len++;
1210
7351d3a5
FF		 1211 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1212 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1213 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1214 }
1215
1216 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1217 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1218
1219 p = bufpoi + data_col_addr;
1220 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1221 int stat;
1222
7351d3a5
FF		 1223 stat = chip->ecc.correct(mtd, p,
1224 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
12c8eb98 1225 if (stat < 0)
3d459559
AK		 1226 mtd->ecc_stats.failed++;
1227 else
1228 mtd->ecc_stats.corrected += stat;
1229 }
1230 return 0;
1231}
1232
068e3c0a 1233/**
d29ebdbe 1234 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
f5bbdacc
TG		 1235 * @mtd: mtd info structure
1236 * @chip: nand chip info structure
1237 * @buf: buffer to store read data
58475fb9 1238 * @page: page number to read
068e3c0a 1239 *
f5bbdacc 1240 * Not for syndrome calculating ecc controllers which need a special oob layout
068e3c0a 1241 */
f5bbdacc 1242static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1243 uint8_t *buf, int page)
1da177e4 1244{
f5bbdacc
TG		 1245 int i, eccsize = chip->ecc.size;
1246 int eccbytes = chip->ecc.bytes;
1247 int eccsteps = chip->ecc.steps;
1248 uint8_t *p = buf;
4bf63fcb
DW		 1249 uint8_t *ecc_calc = chip->buffers->ecccalc;
1250 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1251 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc
TG		 1252
1253 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1254 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1255 chip->read_buf(mtd, p, eccsize);
1256 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1257 }
f75e5097 1258 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1259
f5bbdacc 1260 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1261 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1262
f5bbdacc
TG		 1263 eccsteps = chip->ecc.steps;
1264 p = buf;
61b03bd7 1265
f5bbdacc
TG		 1266 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1267 int stat;
1da177e4 1268
f5bbdacc 1269 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1270 if (stat < 0)
f5bbdacc
TG		 1271 mtd->ecc_stats.failed++;
1272 else
1273 mtd->ecc_stats.corrected += stat;
1274 }
1275 return 0;
1276}
1da177e4 1277
6e0cb135
SN		 1278/**
1279 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1280 * @mtd: mtd info structure
1281 * @chip: nand chip info structure
1282 * @buf: buffer to store read data
58475fb9 1283 * @page: page number to read
6e0cb135
SN		 1284 *
1285 * Hardware ECC for large page chips, require OOB to be read first.
1286 * For this ECC mode, the write_page method is re-used from ECC_HW.
1287 * These methods read/write ECC from the OOB area, unlike the
1288 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1289 * "infix ECC" scheme and reads/writes ECC from the data area, by
1290 * overwriting the NAND manufacturer bad block markings.
1291 */
1292static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1293 struct nand_chip *chip, uint8_t *buf, int page)
1294{
1295 int i, eccsize = chip->ecc.size;
1296 int eccbytes = chip->ecc.bytes;
1297 int eccsteps = chip->ecc.steps;
1298 uint8_t *p = buf;
1299 uint8_t *ecc_code = chip->buffers->ecccode;
1300 uint32_t *eccpos = chip->ecc.layout->eccpos;
1301 uint8_t *ecc_calc = chip->buffers->ecccalc;
1302
1303 /* Read the OOB area first */
1304 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1305 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1306 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1307
1308 for (i = 0; i < chip->ecc.total; i++)
1309 ecc_code[i] = chip->oob_poi[eccpos[i]];
1310
1311 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1312 int stat;
1313
1314 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1315 chip->read_buf(mtd, p, eccsize);
1316 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1317
1318 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1319 if (stat < 0)
1320 mtd->ecc_stats.failed++;
1321 else
1322 mtd->ecc_stats.corrected += stat;
1323 }
1324 return 0;
1325}
1326
f5bbdacc 1327/**
d29ebdbe 1328 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
f5bbdacc
TG		 1329 * @mtd: mtd info structure
1330 * @chip: nand chip info structure
1331 * @buf: buffer to store read data
58475fb9 1332 * @page: page number to read
f5bbdacc
TG		 1333 *
1334 * The hw generator calculates the error syndrome automatically. Therefor
f75e5097 1335 * we need a special oob layout and handling.
f5bbdacc
TG		 1336 */
1337static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1338 uint8_t *buf, int page)
f5bbdacc
TG		 1339{
1340 int i, eccsize = chip->ecc.size;
1341 int eccbytes = chip->ecc.bytes;
1342 int eccsteps = chip->ecc.steps;
1343 uint8_t *p = buf;
f75e5097 1344 uint8_t *oob = chip->oob_poi;
1da177e4 1345
f5bbdacc
TG		 1346 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1347 int stat;
61b03bd7 1348
f5bbdacc
TG		 1349 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1350 chip->read_buf(mtd, p, eccsize);
1da177e4 1351
f5bbdacc
TG		 1352 if (chip->ecc.prepad) {
1353 chip->read_buf(mtd, oob, chip->ecc.prepad);
1354 oob += chip->ecc.prepad;
1355 }
1da177e4 1356
f5bbdacc
TG		 1357 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1358 chip->read_buf(mtd, oob, eccbytes);
1359 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1360
c32b8dcc 1361 if (stat < 0)
f5bbdacc 1362 mtd->ecc_stats.failed++;
61b03bd7 1363 else
f5bbdacc 1364 mtd->ecc_stats.corrected += stat;
61b03bd7 1365
f5bbdacc 1366 oob += eccbytes;
1da177e4 1367
f5bbdacc
TG		 1368 if (chip->ecc.postpad) {
1369 chip->read_buf(mtd, oob, chip->ecc.postpad);
1370 oob += chip->ecc.postpad;
61b03bd7 1371 }
f5bbdacc 1372 }
1da177e4 1373
f5bbdacc 1374 /* Calculate remaining oob bytes */
7e4178f9 1375 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1376 if (i)
1377 chip->read_buf(mtd, oob, i);
61b03bd7 1378
f5bbdacc
TG		 1379 return 0;
1380}
1da177e4 1381
f5bbdacc 1382/**
8593fbc6
TG		 1383 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1384 * @chip: nand chip structure
844d3b42 1385 * @oob: oob destination address
8593fbc6 1386 * @ops: oob ops structure
7014568b 1387 * @len: size of oob to transfer
8593fbc6
TG		 1388 */
1389static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1390 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1391{
f8ac0414 1392 switch (ops->mode) {
8593fbc6
TG		 1393
1394 case MTD_OOB_PLACE:
1395 case MTD_OOB_RAW:
1396 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1397 return oob + len;
1398
1399 case MTD_OOB_AUTO: {
1400 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1401 uint32_t boffs = 0, roffs = ops->ooboffs;
1402 size_t bytes = 0;
8593fbc6 1403
f8ac0414 1404 for (; free->length && len; free++, len -= bytes) {
7bc3312b
TG		 1405 /* Read request not from offset 0 ? */
1406 if (unlikely(roffs)) {
1407 if (roffs >= free->length) {
1408 roffs -= free->length;
1409 continue;
1410 }
1411 boffs = free->offset + roffs;
1412 bytes = min_t(size_t, len,
1413 (free->length - roffs));
1414 roffs = 0;
1415 } else {
1416 bytes = min_t(size_t, len, free->length);
1417 boffs = free->offset;
1418 }
1419 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1420 oob += bytes;
1421 }
1422 return oob;
1423 }
1424 default:
1425 BUG();
1426 }
1427 return NULL;
1428}
1429
1430/**
1431 * nand_do_read_ops - [Internal] Read data with ECC
f5bbdacc
TG		 1432 *
1433 * @mtd: MTD device structure
1434 * @from: offset to read from
844d3b42 1435 * @ops: oob ops structure
f5bbdacc
TG		 1436 *
1437 * Internal function. Called with chip held.
1438 */
8593fbc6
TG		 1439static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1440 struct mtd_oob_ops *ops)
f5bbdacc
TG		 1441{
1442 int chipnr, page, realpage, col, bytes, aligned;
1443 struct nand_chip *chip = mtd->priv;
1444 struct mtd_ecc_stats stats;
1445 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1446 int sndcmd = 1;
1447 int ret = 0;
8593fbc6 1448 uint32_t readlen = ops->len;
7014568b 1449 uint32_t oobreadlen = ops->ooblen;
9aca334e
ML		 1450 uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1451 mtd->oobavail : mtd->oobsize;
1452
8593fbc6 1453 uint8_t *bufpoi, *oob, *buf;
1da177e4 1454
f5bbdacc 1455 stats = mtd->ecc_stats;
1da177e4 1456
f5bbdacc
TG		 1457 chipnr = (int)(from >> chip->chip_shift);
1458 chip->select_chip(mtd, chipnr);
61b03bd7 1459
f5bbdacc
TG		 1460 realpage = (int)(from >> chip->page_shift);
1461 page = realpage & chip->pagemask;
1da177e4 1462
f5bbdacc 1463 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1464
8593fbc6
TG		 1465 buf = ops->datbuf;
1466 oob = ops->oobbuf;
1467
f8ac0414 1468 while (1) {
f5bbdacc
TG		 1469 bytes = min(mtd->writesize - col, readlen);
1470 aligned = (bytes == mtd->writesize);
61b03bd7 1471
f5bbdacc 1472 /* Is the current page in the buffer ? */
8593fbc6 1473 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1474 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1475
f5bbdacc
TG		 1476 if (likely(sndcmd)) {
1477 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1478 sndcmd = 0;
1da177e4 1479 }
1da177e4 1480
f5bbdacc 1481 /* Now read the page into the buffer */
956e944c 1482 if (unlikely(ops->mode == MTD_OOB_RAW))
46a8cf2d
SN		 1483 ret = chip->ecc.read_page_raw(mtd, chip,
1484 bufpoi, page);
3d459559 1485 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
7351d3a5
FF		 1486 ret = chip->ecc.read_subpage(mtd, chip,
1487 col, bytes, bufpoi);
956e944c 1488 else
46a8cf2d
SN		 1489 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1490 page);
f5bbdacc 1491 if (ret < 0)
1da177e4 1492 break;
f5bbdacc
TG		 1493
1494 /* Transfer not aligned data */
1495 if (!aligned) {
c1194c79
AB		 1496 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1497 !(mtd->ecc_stats.failed - stats.failed))
3d459559 1498 chip->pagebuf = realpage;
4bf63fcb 1499 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1500 }
1501
8593fbc6
TG		 1502 buf += bytes;
1503
1504 if (unlikely(oob)) {
9aca334e 1505
b64d39d8
ML		 1506 int toread = min(oobreadlen, max_oobsize);
1507
1508 if (toread) {
1509 oob = nand_transfer_oob(chip,
1510 oob, ops, toread);
1511 oobreadlen -= toread;
1512 }
8593fbc6
TG		 1513 }
1514
f5bbdacc
TG		 1515 if (!(chip->options & NAND_NO_READRDY)) {
1516 /*
1517 * Apply delay or wait for ready/busy pin. Do
1518 * this before the AUTOINCR check, so no
1519 * problems arise if a chip which does auto
1520 * increment is marked as NOAUTOINCR by the
1521 * board driver.
1522 */
1523 if (!chip->dev_ready)
1524 udelay(chip->chip_delay);
1525 else
1526 nand_wait_ready(mtd);
1da177e4 1527 }
8593fbc6 1528 } else {
4bf63fcb 1529 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6
TG		 1530 buf += bytes;
1531 }
1da177e4 1532
f5bbdacc 1533 readlen -= bytes;
61b03bd7 1534
f5bbdacc 1535 if (!readlen)
61b03bd7 1536 break;
1da177e4
LT		 1537
1538 /* For subsequent reads align to page boundary. */
1539 col = 0;
1540 /* Increment page address */
1541 realpage++;
1542
ace4dfee 1543 page = realpage & chip->pagemask;
1da177e4
LT		 1544 /* Check, if we cross a chip boundary */
1545 if (!page) {
1546 chipnr++;
ace4dfee
TG		 1547 chip->select_chip(mtd, -1);
1548 chip->select_chip(mtd, chipnr);
1da177e4 1549 }
f5bbdacc 1550
61b03bd7
TG		 1551 /* Check, if the chip supports auto page increment
1552 * or if we have hit a block boundary.
e0c7d767 1553 */
f5bbdacc 1554 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
61b03bd7 1555 sndcmd = 1;
1da177e4
LT		 1556 }
1557
8593fbc6 1558 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1559 if (oob)
1560 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1561
f5bbdacc
TG		 1562 if (ret)
1563 return ret;
1564
9a1fcdfd
TG		 1565 if (mtd->ecc_stats.failed - stats.failed)
1566 return -EBADMSG;
1567
1568 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
f5bbdacc
TG		 1569}
1570
1571/**
25985edc 1572 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
f5bbdacc
TG		 1573 * @mtd: MTD device structure
1574 * @from: offset to read from
1575 * @len: number of bytes to read
1576 * @retlen: pointer to variable to store the number of read bytes
1577 * @buf: the databuffer to put data
1578 *
1579 * Get hold of the chip and call nand_do_read
1580 */
1581static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1582 size_t *retlen, uint8_t *buf)
1583{
8593fbc6 1584 struct nand_chip *chip = mtd->priv;
f5bbdacc
TG		 1585 int ret;
1586
f5bbdacc
TG		 1587 /* Do not allow reads past end of device */
1588 if ((from + len) > mtd->size)
1589 return -EINVAL;
1590 if (!len)
1591 return 0;
1592
8593fbc6 1593 nand_get_device(chip, mtd, FL_READING);
f5bbdacc 1594
8593fbc6
TG		 1595 chip->ops.len = len;
1596 chip->ops.datbuf = buf;
1597 chip->ops.oobbuf = NULL;
1598
1599 ret = nand_do_read_ops(mtd, from, &chip->ops);
f5bbdacc 1600
7fd5aecc
RP		 1601 *retlen = chip->ops.retlen;
1602
f5bbdacc
TG		 1603 nand_release_device(mtd);
1604
1605 return ret;
1da177e4
LT		 1606}
1607
7bc3312b
TG		 1608/**
1609 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1610 * @mtd: mtd info structure
1611 * @chip: nand chip info structure
1612 * @page: page number to read
1613 * @sndcmd: flag whether to issue read command or not
1614 */
1615static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1616 int page, int sndcmd)
1617{
1618 if (sndcmd) {
1619 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1620 sndcmd = 0;
1621 }
1622 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1623 return sndcmd;
1624}
1625
1626/**
1627 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1628 * with syndromes
1629 * @mtd: mtd info structure
1630 * @chip: nand chip info structure
1631 * @page: page number to read
1632 * @sndcmd: flag whether to issue read command or not
1633 */
1634static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1635 int page, int sndcmd)
1636{
1637 uint8_t *buf = chip->oob_poi;
1638 int length = mtd->oobsize;
1639 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1640 int eccsize = chip->ecc.size;
1641 uint8_t *bufpoi = buf;
1642 int i, toread, sndrnd = 0, pos;
1643
1644 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1645 for (i = 0; i < chip->ecc.steps; i++) {
1646 if (sndrnd) {
1647 pos = eccsize + i * (eccsize + chunk);
1648 if (mtd->writesize > 512)
1649 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1650 else
1651 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1652 } else
1653 sndrnd = 1;
1654 toread = min_t(int, length, chunk);
1655 chip->read_buf(mtd, bufpoi, toread);
1656 bufpoi += toread;
1657 length -= toread;
1658 }
1659 if (length > 0)
1660 chip->read_buf(mtd, bufpoi, length);
1661
1662 return 1;
1663}
1664
1665/**
1666 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1667 * @mtd: mtd info structure
1668 * @chip: nand chip info structure
1669 * @page: page number to write
1670 */
1671static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1672 int page)
1673{
1674 int status = 0;
1675 const uint8_t *buf = chip->oob_poi;
1676 int length = mtd->oobsize;
1677
1678 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1679 chip->write_buf(mtd, buf, length);
1680 /* Send command to program the OOB data */
1681 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1682
1683 status = chip->waitfunc(mtd, chip);
1684
0d420f9d 1685 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1686}
1687
1688/**
1689 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1690 * with syndrome - only for large page flash !
1691 * @mtd: mtd info structure
1692 * @chip: nand chip info structure
1693 * @page: page number to write
1694 */
1695static int nand_write_oob_syndrome(struct mtd_info *mtd,
1696 struct nand_chip *chip, int page)
1697{
1698 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1699 int eccsize = chip->ecc.size, length = mtd->oobsize;
1700 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1701 const uint8_t *bufpoi = chip->oob_poi;
1702
1703 /*
1704 * data-ecc-data-ecc ... ecc-oob
1705 * or
1706 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1707 */
1708 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1709 pos = steps * (eccsize + chunk);
1710 steps = 0;
1711 } else
8b0036ee 1712 pos = eccsize;
7bc3312b
TG		 1713
1714 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1715 for (i = 0; i < steps; i++) {
1716 if (sndcmd) {
1717 if (mtd->writesize <= 512) {
1718 uint32_t fill = 0xFFFFFFFF;
1719
1720 len = eccsize;
1721 while (len > 0) {
1722 int num = min_t(int, len, 4);
1723 chip->write_buf(mtd, (uint8_t *)&fill,
1724 num);
1725 len -= num;
1726 }
1727 } else {
1728 pos = eccsize + i * (eccsize + chunk);
1729 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1730 }
1731 } else
1732 sndcmd = 1;
1733 len = min_t(int, length, chunk);
1734 chip->write_buf(mtd, bufpoi, len);
1735 bufpoi += len;
1736 length -= len;
1737 }
1738 if (length > 0)
1739 chip->write_buf(mtd, bufpoi, length);
1740
1741 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1742 status = chip->waitfunc(mtd, chip);
1743
1744 return status & NAND_STATUS_FAIL ? -EIO : 0;
1745}
1746
1da177e4 1747/**
8593fbc6 1748 * nand_do_read_oob - [Intern] NAND read out-of-band
1da177e4
LT		 1749 * @mtd: MTD device structure
1750 * @from: offset to read from
8593fbc6 1751 * @ops: oob operations description structure
1da177e4
LT		 1752 *
1753 * NAND read out-of-band data from the spare area
1754 */
8593fbc6
TG		 1755static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1756 struct mtd_oob_ops *ops)
1da177e4 1757{
7bc3312b 1758 int page, realpage, chipnr, sndcmd = 1;
ace4dfee 1759 struct nand_chip *chip = mtd->priv;
7314e9e7 1760 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
7014568b
VW		 1761 int readlen = ops->ooblen;
1762 int len;
7bc3312b 1763 uint8_t *buf = ops->oobbuf;
61b03bd7 1764
20d8e248 1765 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1766 __func__, (unsigned long long)from, readlen);
1da177e4 1767
03736155 1768 if (ops->mode == MTD_OOB_AUTO)
7014568b 1769 len = chip->ecc.layout->oobavail;
03736155
AH		 1770 else
1771 len = mtd->oobsize;
1772
1773 if (unlikely(ops->ooboffs >= len)) {
20d8e248 1774 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1775 "outside oob\n", __func__);
03736155
AH		 1776 return -EINVAL;
1777 }
1778
1779 /* Do not allow reads past end of device */
1780 if (unlikely(from >= mtd->size ||
1781 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1782 (from >> chip->page_shift)) * len)) {
20d8e248 1783 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1784 "of device\n", __func__);
03736155
AH		 1785 return -EINVAL;
1786 }
7014568b 1787
7314e9e7 1788 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1789 chip->select_chip(mtd, chipnr);
1da177e4 1790
7314e9e7
TG		 1791 /* Shift to get page */
1792 realpage = (int)(from >> chip->page_shift);
1793 page = realpage & chip->pagemask;
1da177e4 1794
f8ac0414 1795 while (1) {
7bc3312b 1796 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
7014568b
VW		 1797
1798 len = min(len, readlen);
1799 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1800
7314e9e7
TG		 1801 if (!(chip->options & NAND_NO_READRDY)) {
1802 /*
1803 * Apply delay or wait for ready/busy pin. Do this
1804 * before the AUTOINCR check, so no problems arise if a
1805 * chip which does auto increment is marked as
1806 * NOAUTOINCR by the board driver.
19870da7 1807 */
ace4dfee
TG		 1808 if (!chip->dev_ready)
1809 udelay(chip->chip_delay);
19870da7
TG		 1810 else
1811 nand_wait_ready(mtd);
7314e9e7 1812 }
19870da7 1813
7014568b 1814 readlen -= len;
0d420f9d
SZ		 1815 if (!readlen)
1816 break;
1817
7314e9e7
TG		 1818 /* Increment page address */
1819 realpage++;
1820
1821 page = realpage & chip->pagemask;
1822 /* Check, if we cross a chip boundary */
1823 if (!page) {
1824 chipnr++;
1825 chip->select_chip(mtd, -1);
1826 chip->select_chip(mtd, chipnr);
1da177e4 1827 }
7314e9e7
TG		 1828
1829 /* Check, if the chip supports auto page increment
1830 * or if we have hit a block boundary.
1831 */
1832 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1833 sndcmd = 1;
1da177e4
LT		 1834 }
1835
7014568b 1836 ops->oobretlen = ops->ooblen;
1da177e4
LT		 1837 return 0;
1838}
1839
1840/**
8593fbc6 1841 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1da177e4 1842 * @mtd: MTD device structure
1da177e4 1843 * @from: offset to read from
8593fbc6 1844 * @ops: oob operation description structure
1da177e4 1845 *
8593fbc6 1846 * NAND read data and/or out-of-band data
1da177e4 1847 */
8593fbc6
TG		 1848static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1849 struct mtd_oob_ops *ops)
1da177e4 1850{
ace4dfee 1851 struct nand_chip *chip = mtd->priv;
8593fbc6
TG		 1852 int ret = -ENOTSUPP;
1853
1854 ops->retlen = 0;
1da177e4
LT		 1855
1856 /* Do not allow reads past end of device */
7014568b 1857 if (ops->datbuf && (from + ops->len) > mtd->size) {
20d8e248 1858 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1859 "beyond end of device\n", __func__);
1da177e4
LT		 1860 return -EINVAL;
1861 }
1862
ace4dfee 1863 nand_get_device(chip, mtd, FL_READING);
1da177e4 1864
f8ac0414 1865 switch (ops->mode) {
8593fbc6
TG		 1866 case MTD_OOB_PLACE:
1867 case MTD_OOB_AUTO:
8593fbc6 1868 case MTD_OOB_RAW:
8593fbc6 1869 break;
1da177e4 1870
8593fbc6
TG		 1871 default:
1872 goto out;
1873 }
1da177e4 1874
8593fbc6
TG		 1875 if (!ops->datbuf)
1876 ret = nand_do_read_oob(mtd, from, ops);
1877 else
1878 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1879
7351d3a5 1880out:
8593fbc6
TG		 1881 nand_release_device(mtd);
1882 return ret;
1883}
61b03bd7 1884
1da177e4 1885
8593fbc6
TG		 1886/**
1887 * nand_write_page_raw - [Intern] raw page write function
1888 * @mtd: mtd info structure
1889 * @chip: nand chip info structure
1890 * @buf: data buffer
52ff49df
DB		 1891 *
1892 * Not for syndrome calculating ecc controllers, which use a special oob layout
8593fbc6
TG		 1893 */
1894static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1895 const uint8_t *buf)
1896{
1897 chip->write_buf(mtd, buf, mtd->writesize);
1898 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4
LT		 1899}
1900
52ff49df
DB		 1901/**
1902 * nand_write_page_raw_syndrome - [Intern] raw page write function
1903 * @mtd: mtd info structure
1904 * @chip: nand chip info structure
1905 * @buf: data buffer
1906 *
1907 * We need a special oob layout and handling even when ECC isn't checked.
1908 */
7351d3a5
FF		 1909static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1910 struct nand_chip *chip,
1911 const uint8_t *buf)
52ff49df
DB		 1912{
1913 int eccsize = chip->ecc.size;
1914 int eccbytes = chip->ecc.bytes;
1915 uint8_t *oob = chip->oob_poi;
1916 int steps, size;
1917
1918 for (steps = chip->ecc.steps; steps > 0; steps--) {
1919 chip->write_buf(mtd, buf, eccsize);
1920 buf += eccsize;
1921
1922 if (chip->ecc.prepad) {
1923 chip->write_buf(mtd, oob, chip->ecc.prepad);
1924 oob += chip->ecc.prepad;
1925 }
1926
1927 chip->read_buf(mtd, oob, eccbytes);
1928 oob += eccbytes;
1929
1930 if (chip->ecc.postpad) {
1931 chip->write_buf(mtd, oob, chip->ecc.postpad);
1932 oob += chip->ecc.postpad;
1933 }
1934 }
1935
1936 size = mtd->oobsize - (oob - chip->oob_poi);
1937 if (size)
1938 chip->write_buf(mtd, oob, size);
1939}
9223a456 1940/**
d29ebdbe 1941 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
f75e5097
TG		 1942 * @mtd: mtd info structure
1943 * @chip: nand chip info structure
1944 * @buf: data buffer
9223a456 1945 */
f75e5097
TG		 1946static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1947 const uint8_t *buf)
9223a456 1948{
f75e5097
TG		 1949 int i, eccsize = chip->ecc.size;
1950 int eccbytes = chip->ecc.bytes;
1951 int eccsteps = chip->ecc.steps;
4bf63fcb 1952 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1953 const uint8_t *p = buf;
8b099a39 1954 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1955
8593fbc6
TG		 1956 /* Software ecc calculation */
1957 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1958 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1959
8593fbc6
TG		 1960 for (i = 0; i < chip->ecc.total; i++)
1961 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 1962
90424de8 1963 chip->ecc.write_page_raw(mtd, chip, buf);
f75e5097 1964}
9223a456 1965
f75e5097 1966/**
d29ebdbe 1967 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
f75e5097
TG		 1968 * @mtd: mtd info structure
1969 * @chip: nand chip info structure
1970 * @buf: data buffer
1971 */
1972static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1973 const uint8_t *buf)
1974{
1975 int i, eccsize = chip->ecc.size;
1976 int eccbytes = chip->ecc.bytes;
1977 int eccsteps = chip->ecc.steps;
4bf63fcb 1978 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1979 const uint8_t *p = buf;
8b099a39 1980 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1981
f75e5097
TG		 1982 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1983 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 1984 chip->write_buf(mtd, p, eccsize);
f75e5097 1985 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 1986 }
1987
f75e5097
TG		 1988 for (i = 0; i < chip->ecc.total; i++)
1989 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1990
1991 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
9223a456
TG		 1992}
1993
61b03bd7 1994/**
d29ebdbe 1995 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
f75e5097
TG		 1996 * @mtd: mtd info structure
1997 * @chip: nand chip info structure
1998 * @buf: data buffer
1da177e4 1999 *
f75e5097
TG		 2000 * The hw generator calculates the error syndrome automatically. Therefor
2001 * we need a special oob layout and handling.
2002 */
2003static void nand_write_page_syndrome(struct mtd_info *mtd,
2004 struct nand_chip *chip, const uint8_t *buf)
1da177e4 2005{
f75e5097
TG		 2006 int i, eccsize = chip->ecc.size;
2007 int eccbytes = chip->ecc.bytes;
2008 int eccsteps = chip->ecc.steps;
2009 const uint8_t *p = buf;
2010 uint8_t *oob = chip->oob_poi;
1da177e4 2011
f75e5097 2012 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2013
f75e5097
TG		 2014 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2015 chip->write_buf(mtd, p, eccsize);
61b03bd7 2016
f75e5097
TG		 2017 if (chip->ecc.prepad) {
2018 chip->write_buf(mtd, oob, chip->ecc.prepad);
2019 oob += chip->ecc.prepad;
2020 }
2021
2022 chip->ecc.calculate(mtd, p, oob);
2023 chip->write_buf(mtd, oob, eccbytes);
2024 oob += eccbytes;
2025
2026 if (chip->ecc.postpad) {
2027 chip->write_buf(mtd, oob, chip->ecc.postpad);
2028 oob += chip->ecc.postpad;
1da177e4 2029 }
1da177e4 2030 }
f75e5097
TG		 2031
2032 /* Calculate remaining oob bytes */
7e4178f9 2033 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2034 if (i)
2035 chip->write_buf(mtd, oob, i);
2036}
2037
2038/**
956e944c 2039 * nand_write_page - [REPLACEABLE] write one page
f75e5097
TG		 2040 * @mtd: MTD device structure
2041 * @chip: NAND chip descriptor
2042 * @buf: the data to write
2043 * @page: page number to write
2044 * @cached: cached programming
efbfe96c 2045 * @raw: use _raw version of write_page
f75e5097
TG		 2046 */
2047static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
956e944c 2048 const uint8_t *buf, int page, int cached, int raw)
f75e5097
TG		 2049{
2050 int status;
2051
2052 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2053
956e944c
DW		 2054 if (unlikely(raw))
2055 chip->ecc.write_page_raw(mtd, chip, buf);
2056 else
2057 chip->ecc.write_page(mtd, chip, buf);
f75e5097
TG		 2058
2059 /*
2060 * Cached progamming disabled for now, Not sure if its worth the
2061 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
2062 */
2063 cached = 0;
2064
2065 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2066
2067 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2068 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2069 /*
2070 * See if operation failed and additional status checks are
2071 * available
2072 */
2073 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2074 status = chip->errstat(mtd, chip, FL_WRITING, status,
2075 page);
2076
2077 if (status & NAND_STATUS_FAIL)
2078 return -EIO;
2079 } else {
2080 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2081 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2082 }
2083
2084#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2085 /* Send command to read back the data */
2086 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2087
2088 if (chip->verify_buf(mtd, buf, mtd->writesize))
2089 return -EIO;
2090#endif
2091 return 0;
1da177e4
LT		 2092}
2093
8593fbc6
TG		 2094/**
2095 * nand_fill_oob - [Internal] Transfer client buffer to oob
2096 * @chip: nand chip structure
2097 * @oob: oob data buffer
b6d676db 2098 * @len: oob data write length
8593fbc6
TG		 2099 * @ops: oob ops structure
2100 */
782ce79a
ML		 2101static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
2102 struct mtd_oob_ops *ops)
8593fbc6 2103{
f8ac0414 2104 switch (ops->mode) {
8593fbc6
TG		 2105
2106 case MTD_OOB_PLACE:
2107 case MTD_OOB_RAW:
2108 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2109 return oob + len;
2110
2111 case MTD_OOB_AUTO: {
2112 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2113 uint32_t boffs = 0, woffs = ops->ooboffs;
2114 size_t bytes = 0;
8593fbc6 2115
f8ac0414 2116 for (; free->length && len; free++, len -= bytes) {
7bc3312b
TG		 2117 /* Write request not from offset 0 ? */
2118 if (unlikely(woffs)) {
2119 if (woffs >= free->length) {
2120 woffs -= free->length;
2121 continue;
2122 }
2123 boffs = free->offset + woffs;
2124 bytes = min_t(size_t, len,
2125 (free->length - woffs));
2126 woffs = 0;
2127 } else {
2128 bytes = min_t(size_t, len, free->length);
2129 boffs = free->offset;
2130 }
8b0036ee 2131 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2132 oob += bytes;
2133 }
2134 return oob;
2135 }
2136 default:
2137 BUG();
2138 }
2139 return NULL;
2140}
2141
f8ac0414 2142#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2143
2144/**
8593fbc6 2145 * nand_do_write_ops - [Internal] NAND write with ECC
1da177e4
LT		 2146 * @mtd: MTD device structure
2147 * @to: offset to write to
8593fbc6 2148 * @ops: oob operations description structure
1da177e4
LT		 2149 *
2150 * NAND write with ECC
2151 */
8593fbc6
TG		 2152static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2153 struct mtd_oob_ops *ops)
1da177e4 2154{
29072b96 2155 int chipnr, realpage, page, blockmask, column;
ace4dfee 2156 struct nand_chip *chip = mtd->priv;
8593fbc6 2157 uint32_t writelen = ops->len;
782ce79a
ML		 2158
2159 uint32_t oobwritelen = ops->ooblen;
2160 uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
2161 mtd->oobavail : mtd->oobsize;
2162
8593fbc6
TG		 2163 uint8_t *oob = ops->oobbuf;
2164 uint8_t *buf = ops->datbuf;
29072b96 2165 int ret, subpage;
1da177e4 2166
8593fbc6 2167 ops->retlen = 0;
29072b96
TG		 2168 if (!writelen)
2169 return 0;
1da177e4 2170
61b03bd7 2171 /* reject writes, which are not page aligned */
8593fbc6 2172 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
20d8e248 2173 printk(KERN_NOTICE "%s: Attempt to write not "
2174 "page aligned data\n", __func__);
1da177e4
LT		 2175 return -EINVAL;
2176 }
2177
29072b96
TG		 2178 column = to & (mtd->writesize - 1);
2179 subpage = column || (writelen & (mtd->writesize - 1));
2180
2181 if (subpage && oob)
2182 return -EINVAL;
1da177e4 2183
6a930961
TG		 2184 chipnr = (int)(to >> chip->chip_shift);
2185 chip->select_chip(mtd, chipnr);
2186
1da177e4
LT		 2187 /* Check, if it is write protected */
2188 if (nand_check_wp(mtd))
8593fbc6 2189 return -EIO;
1da177e4 2190
f75e5097
TG		 2191 realpage = (int)(to >> chip->page_shift);
2192 page = realpage & chip->pagemask;
2193 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2194
2195 /* Invalidate the page cache, when we write to the cached page */
2196 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 2197 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2198 chip->pagebuf = -1;
61b03bd7 2199
7dcdcbef
DW		 2200 /* If we're not given explicit OOB data, let it be 0xFF */
2201 if (likely(!oob))
2202 memset(chip->oob_poi, 0xff, mtd->oobsize);
61b03bd7 2203
782ce79a 2204 /* Don't allow multipage oob writes with offset */
cdcf12b2 2205 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
782ce79a
ML		 2206 return -EINVAL;
2207
f8ac0414 2208 while (1) {
29072b96 2209 int bytes = mtd->writesize;
f75e5097 2210 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 2211 uint8_t *wbuf = buf;
2212
2213 /* Partial page write ? */
2214 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2215 cached = 0;
2216 bytes = min_t(int, bytes - column, (int) writelen);
2217 chip->pagebuf = -1;
2218 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2219 memcpy(&chip->buffers->databuf[column], buf, bytes);
2220 wbuf = chip->buffers->databuf;
2221 }
1da177e4 2222
782ce79a
ML		 2223 if (unlikely(oob)) {
2224 size_t len = min(oobwritelen, oobmaxlen);
2225 oob = nand_fill_oob(chip, oob, len, ops);
2226 oobwritelen -= len;
2227 }
8593fbc6 2228
29072b96 2229 ret = chip->write_page(mtd, chip, wbuf, page, cached,
956e944c 2230 (ops->mode == MTD_OOB_RAW));
f75e5097
TG		 2231 if (ret)
2232 break;
2233
2234 writelen -= bytes;
2235 if (!writelen)
2236 break;
2237
29072b96 2238 column = 0;
f75e5097
TG		 2239 buf += bytes;
2240 realpage++;
2241
2242 page = realpage & chip->pagemask;
2243 /* Check, if we cross a chip boundary */
2244 if (!page) {
2245 chipnr++;
2246 chip->select_chip(mtd, -1);
2247 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2248 }
2249 }
8593fbc6 2250
8593fbc6 2251 ops->retlen = ops->len - writelen;
7014568b
VW		 2252 if (unlikely(oob))
2253 ops->oobretlen = ops->ooblen;
1da177e4
LT		 2254 return ret;
2255}
2256
2af7c653
SK		 2257/**
2258 * panic_nand_write - [MTD Interface] NAND write with ECC
2259 * @mtd: MTD device structure
2260 * @to: offset to write to
2261 * @len: number of bytes to write
2262 * @retlen: pointer to variable to store the number of written bytes
2263 * @buf: the data to write
2264 *
2265 * NAND write with ECC. Used when performing writes in interrupt context, this
2266 * may for example be called by mtdoops when writing an oops while in panic.
2267 */
2268static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2269 size_t *retlen, const uint8_t *buf)
2270{
2271 struct nand_chip *chip = mtd->priv;
2272 int ret;
2273
2274 /* Do not allow reads past end of device */
2275 if ((to + len) > mtd->size)
2276 return -EINVAL;
2277 if (!len)
2278 return 0;
2279
2280 /* Wait for the device to get ready. */
2281 panic_nand_wait(mtd, chip, 400);
2282
2283 /* Grab the device. */
2284 panic_nand_get_device(chip, mtd, FL_WRITING);
2285
2286 chip->ops.len = len;
2287 chip->ops.datbuf = (uint8_t *)buf;
2288 chip->ops.oobbuf = NULL;
2289
2290 ret = nand_do_write_ops(mtd, to, &chip->ops);
2291
2292 *retlen = chip->ops.retlen;
2293 return ret;
2294}
2295
f75e5097 2296/**
8593fbc6 2297 * nand_write - [MTD Interface] NAND write with ECC
f75e5097 2298 * @mtd: MTD device structure
f75e5097
TG		 2299 * @to: offset to write to
2300 * @len: number of bytes to write
8593fbc6
TG		 2301 * @retlen: pointer to variable to store the number of written bytes
2302 * @buf: the data to write
f75e5097 2303 *
8593fbc6 2304 * NAND write with ECC
f75e5097 2305 */
8593fbc6
TG		 2306static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2307 size_t *retlen, const uint8_t *buf)
f75e5097
TG		 2308{
2309 struct nand_chip *chip = mtd->priv;
f75e5097
TG		 2310 int ret;
2311
8593fbc6
TG		 2312 /* Do not allow reads past end of device */
2313 if ((to + len) > mtd->size)
f75e5097 2314 return -EINVAL;
8593fbc6
TG		 2315 if (!len)
2316 return 0;
f75e5097 2317
7bc3312b 2318 nand_get_device(chip, mtd, FL_WRITING);
f75e5097 2319
8593fbc6
TG		 2320 chip->ops.len = len;
2321 chip->ops.datbuf = (uint8_t *)buf;
2322 chip->ops.oobbuf = NULL;
f75e5097 2323
8593fbc6 2324 ret = nand_do_write_ops(mtd, to, &chip->ops);
f75e5097 2325
7fd5aecc
RP		 2326 *retlen = chip->ops.retlen;
2327
f75e5097 2328 nand_release_device(mtd);
8593fbc6 2329
8593fbc6 2330 return ret;
f75e5097 2331}
7314e9e7 2332
1da177e4 2333/**
8593fbc6 2334 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1da177e4
LT		 2335 * @mtd: MTD device structure
2336 * @to: offset to write to
8593fbc6 2337 * @ops: oob operation description structure
1da177e4
LT		 2338 *
2339 * NAND write out-of-band
2340 */
8593fbc6
TG		 2341static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2342 struct mtd_oob_ops *ops)
1da177e4 2343{
03736155 2344 int chipnr, page, status, len;
ace4dfee 2345 struct nand_chip *chip = mtd->priv;
1da177e4 2346
20d8e248 2347 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2348 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2349
03736155
AH		 2350 if (ops->mode == MTD_OOB_AUTO)
2351 len = chip->ecc.layout->oobavail;
2352 else
2353 len = mtd->oobsize;
2354
1da177e4 2355 /* Do not allow write past end of page */
03736155 2356 if ((ops->ooboffs + ops->ooblen) > len) {
20d8e248 2357 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2358 "past end of page\n", __func__);
1da177e4
LT		 2359 return -EINVAL;
2360 }
2361
03736155 2362 if (unlikely(ops->ooboffs >= len)) {
20d8e248 2363 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2364 "write outside oob\n", __func__);
03736155
AH		 2365 return -EINVAL;
2366 }
2367
775adc3d 2368 /* Do not allow write past end of device */
03736155
AH		 2369 if (unlikely(to >= mtd->size ||
2370 ops->ooboffs + ops->ooblen >
2371 ((mtd->size >> chip->page_shift) -
2372 (to >> chip->page_shift)) * len)) {
20d8e248 2373 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2374 "end of device\n", __func__);
03736155
AH		 2375 return -EINVAL;
2376 }
2377
7314e9e7 2378 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2379 chip->select_chip(mtd, chipnr);
1da177e4 2380
7314e9e7
TG		 2381 /* Shift to get page */
2382 page = (int)(to >> chip->page_shift);
2383
2384 /*
2385 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2386 * of my DiskOnChip 2000 test units) will clear the whole data page too
2387 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2388 * it in the doc2000 driver in August 1999. dwmw2.
2389 */
ace4dfee 2390 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2391
2392 /* Check, if it is write protected */
2393 if (nand_check_wp(mtd))
8593fbc6 2394 return -EROFS;
61b03bd7 2395
1da177e4 2396 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2397 if (page == chip->pagebuf)
2398 chip->pagebuf = -1;
1da177e4 2399
7bc3312b 2400 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2401 nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
7bc3312b
TG		 2402 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2403 memset(chip->oob_poi, 0xff, mtd->oobsize);
1da177e4 2404
7bc3312b
TG		 2405 if (status)
2406 return status;
1da177e4 2407
7014568b 2408 ops->oobretlen = ops->ooblen;
1da177e4 2409
7bc3312b 2410 return 0;
8593fbc6
TG		 2411}
2412
2413/**
2414 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2415 * @mtd: MTD device structure
844d3b42 2416 * @to: offset to write to
8593fbc6
TG		 2417 * @ops: oob operation description structure
2418 */
2419static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2420 struct mtd_oob_ops *ops)
2421{
8593fbc6
TG		 2422 struct nand_chip *chip = mtd->priv;
2423 int ret = -ENOTSUPP;
2424
2425 ops->retlen = 0;
2426
2427 /* Do not allow writes past end of device */
7014568b 2428 if (ops->datbuf && (to + ops->len) > mtd->size) {
20d8e248 2429 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2430 "end of device\n", __func__);
8593fbc6
TG		 2431 return -EINVAL;
2432 }
2433
7bc3312b 2434 nand_get_device(chip, mtd, FL_WRITING);
8593fbc6 2435
f8ac0414 2436 switch (ops->mode) {
8593fbc6
TG		 2437 case MTD_OOB_PLACE:
2438 case MTD_OOB_AUTO:
8593fbc6 2439 case MTD_OOB_RAW:
8593fbc6
TG		 2440 break;
2441
2442 default:
2443 goto out;
2444 }
2445
2446 if (!ops->datbuf)
2447 ret = nand_do_write_oob(mtd, to, ops);
2448 else
2449 ret = nand_do_write_ops(mtd, to, ops);
2450
7351d3a5 2451out:
1da177e4 2452 nand_release_device(mtd);
1da177e4
LT		 2453 return ret;
2454}
2455
1da177e4
LT		 2456/**
2457 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2458 * @mtd: MTD device structure
2459 * @page: the page address of the block which will be erased
2460 *
2461 * Standard erase command for NAND chips
2462 */
e0c7d767 2463static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2464{
ace4dfee 2465 struct nand_chip *chip = mtd->priv;
1da177e4 2466 /* Send commands to erase a block */
ace4dfee
TG		 2467 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2468 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2469}
2470
2471/**
2472 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2473 * @mtd: MTD device structure
2474 * @page: the page address of the block which will be erased
2475 *
2476 * AND multi block erase command function
2477 * Erase 4 consecutive blocks
2478 */
e0c7d767 2479static void multi_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2480{
ace4dfee 2481 struct nand_chip *chip = mtd->priv;
1da177e4 2482 /* Send commands to erase a block */
ace4dfee
TG		 2483 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2484 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2485 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2486 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2487 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2488}
2489
2490/**
2491 * nand_erase - [MTD Interface] erase block(s)
2492 * @mtd: MTD device structure
2493 * @instr: erase instruction
2494 *
2495 * Erase one ore more blocks
2496 */
e0c7d767 2497static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2498{
e0c7d767 2499 return nand_erase_nand(mtd, instr, 0);
1da177e4 2500}
61b03bd7 2501
30f464b7 2502#define BBT_PAGE_MASK 0xffffff3f
1da177e4 2503/**
ace4dfee 2504 * nand_erase_nand - [Internal] erase block(s)
1da177e4
LT		 2505 * @mtd: MTD device structure
2506 * @instr: erase instruction
2507 * @allowbbt: allow erasing the bbt area
2508 *
2509 * Erase one ore more blocks
2510 */
ace4dfee
TG		 2511int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2512 int allowbbt)
1da177e4 2513{
69423d99 2514 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2515 struct nand_chip *chip = mtd->priv;
f8ac0414 2516 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
ace4dfee 2517 unsigned int bbt_masked_page = 0xffffffff;
69423d99 2518 loff_t len;
1da177e4 2519
20d8e248 2520 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2521 __func__, (unsigned long long)instr->addr,
2522 (unsigned long long)instr->len);
1da177e4 2523
6fe5a6ac 2524 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2525 return -EINVAL;
1da177e4 2526
bb0eb217 2527 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
1da177e4
LT		 2528
2529 /* Grab the lock and see if the device is available */
ace4dfee 2530 nand_get_device(chip, mtd, FL_ERASING);
1da177e4
LT		 2531
2532 /* Shift to get first page */
ace4dfee
TG		 2533 page = (int)(instr->addr >> chip->page_shift);
2534 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2535
2536 /* Calculate pages in each block */
ace4dfee 2537 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2538
2539 /* Select the NAND device */
ace4dfee 2540 chip->select_chip(mtd, chipnr);
1da177e4 2541
1da177e4
LT		 2542 /* Check, if it is write protected */
2543 if (nand_check_wp(mtd)) {
20d8e248 2544 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2545 __func__);
1da177e4
LT		 2546 instr->state = MTD_ERASE_FAILED;
2547 goto erase_exit;
2548 }
2549
ace4dfee
TG		 2550 /*
2551 * If BBT requires refresh, set the BBT page mask to see if the BBT
2552 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2553 * can not be matched. This is also done when the bbt is actually
2554 * erased to avoid recusrsive updates
2555 */
2556 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2557 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
30f464b7 2558
1da177e4
LT		 2559 /* Loop through the pages */
2560 len = instr->len;
2561
2562 instr->state = MTD_ERASING;
2563
2564 while (len) {
ace4dfee
TG		 2565 /*
2566 * heck if we have a bad block, we do not erase bad blocks !
2567 */
2568 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2569 chip->page_shift, 0, allowbbt)) {
20d8e248 2570 printk(KERN_WARNING "%s: attempt to erase a bad block "
2571 "at page 0x%08x\n", __func__, page);
1da177e4
LT		 2572 instr->state = MTD_ERASE_FAILED;
2573 goto erase_exit;
2574 }
61b03bd7 2575
ace4dfee
TG		 2576 /*
2577 * Invalidate the page cache, if we erase the block which
2578 * contains the current cached page
2579 */
2580 if (page <= chip->pagebuf && chip->pagebuf <
2581 (page + pages_per_block))
2582 chip->pagebuf = -1;
1da177e4 2583
ace4dfee 2584 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2585
7bc3312b 2586 status = chip->waitfunc(mtd, chip);
1da177e4 2587
ace4dfee
TG		 2588 /*
2589 * See if operation failed and additional status checks are
2590 * available
2591 */
2592 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2593 status = chip->errstat(mtd, chip, FL_ERASING,
2594 status, page);
068e3c0a 2595
1da177e4 2596 /* See if block erase succeeded */
a4ab4c5d 2597 if (status & NAND_STATUS_FAIL) {
20d8e248 2598 DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2599 "page 0x%08x\n", __func__, page);
1da177e4 2600 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2601 instr->fail_addr =
2602 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2603 goto erase_exit;
2604 }
30f464b7 2605
ace4dfee
TG		 2606 /*
2607 * If BBT requires refresh, set the BBT rewrite flag to the
2608 * page being erased
2609 */
2610 if (bbt_masked_page != 0xffffffff &&
2611 (page & BBT_PAGE_MASK) == bbt_masked_page)
69423d99
AH		 2612 rewrite_bbt[chipnr] =
2613 ((loff_t)page << chip->page_shift);
61b03bd7 2614
1da177e4 2615 /* Increment page address and decrement length */
ace4dfee 2616 len -= (1 << chip->phys_erase_shift);
1da177e4
LT		 2617 page += pages_per_block;
2618
2619 /* Check, if we cross a chip boundary */
ace4dfee 2620 if (len && !(page & chip->pagemask)) {
1da177e4 2621 chipnr++;
ace4dfee
TG		 2622 chip->select_chip(mtd, -1);
2623 chip->select_chip(mtd, chipnr);
30f464b7 2624
ace4dfee
TG		 2625 /*
2626 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2627 * page mask to see if this BBT should be rewritten
2628 */
2629 if (bbt_masked_page != 0xffffffff &&
2630 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2631 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2632 BBT_PAGE_MASK;
1da177e4
LT		 2633 }
2634 }
2635 instr->state = MTD_ERASE_DONE;
2636
7351d3a5 2637erase_exit:
1da177e4
LT		 2638
2639 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2640
2641 /* Deselect and wake up anyone waiting on the device */
2642 nand_release_device(mtd);
2643
49defc01
DW		 2644 /* Do call back function */
2645 if (!ret)
2646 mtd_erase_callback(instr);
2647
ace4dfee
TG		 2648 /*
2649 * If BBT requires refresh and erase was successful, rewrite any
2650 * selected bad block tables
2651 */
2652 if (bbt_masked_page == 0xffffffff || ret)
2653 return ret;
2654
2655 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2656 if (!rewrite_bbt[chipnr])
2657 continue;
2658 /* update the BBT for chip */
20d8e248 2659 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2660 "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2661 rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
ace4dfee 2662 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
30f464b7
DM		 2663 }
2664
1da177e4
LT		 2665 /* Return more or less happy */
2666 return ret;
2667}
2668
2669/**
2670 * nand_sync - [MTD Interface] sync
2671 * @mtd: MTD device structure
2672 *
2673 * Sync is actually a wait for chip ready function
2674 */
e0c7d767 2675static void nand_sync(struct mtd_info *mtd)
1da177e4 2676{
ace4dfee 2677 struct nand_chip *chip = mtd->priv;
1da177e4 2678
20d8e248 2679 DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
1da177e4
LT		 2680
2681 /* Grab the lock and see if the device is available */
ace4dfee 2682 nand_get_device(chip, mtd, FL_SYNCING);
1da177e4 2683 /* Release it and go back */
e0c7d767 2684 nand_release_device(mtd);
1da177e4
LT		 2685}
2686
1da177e4 2687/**
ace4dfee 2688 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
1da177e4 2689 * @mtd: MTD device structure
844d3b42 2690 * @offs: offset relative to mtd start
1da177e4 2691 */
ace4dfee 2692static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4
LT		 2693{
2694 /* Check for invalid offset */
ace4dfee 2695 if (offs > mtd->size)
1da177e4 2696 return -EINVAL;
61b03bd7 2697
ace4dfee 2698 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2699}
2700
2701/**
ace4dfee 2702 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
1da177e4
LT		 2703 * @mtd: MTD device structure
2704 * @ofs: offset relative to mtd start
2705 */
e0c7d767 2706static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2707{
ace4dfee 2708 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2709 int ret;
2710
f8ac0414
FF		 2711 ret = nand_block_isbad(mtd, ofs);
2712 if (ret) {
e0c7d767 2713 /* If it was bad already, return success and do nothing. */
1da177e4
LT		 2714 if (ret > 0)
2715 return 0;
e0c7d767
DW		 2716 return ret;
2717 }
1da177e4 2718
ace4dfee 2719 return chip->block_markbad(mtd, ofs);
1da177e4
LT		 2720}
2721
962034f4
VW		 2722/**
2723 * nand_suspend - [MTD Interface] Suspend the NAND flash
2724 * @mtd: MTD device structure
2725 */
2726static int nand_suspend(struct mtd_info *mtd)
2727{
ace4dfee 2728 struct nand_chip *chip = mtd->priv;
962034f4 2729
ace4dfee 2730 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
962034f4
VW		 2731}
2732
2733/**
2734 * nand_resume - [MTD Interface] Resume the NAND flash
2735 * @mtd: MTD device structure
2736 */
2737static void nand_resume(struct mtd_info *mtd)
2738{
ace4dfee 2739 struct nand_chip *chip = mtd->priv;
962034f4 2740
ace4dfee 2741 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2742 nand_release_device(mtd);
2743 else
20d8e248 2744 printk(KERN_ERR "%s called for a chip which is not "
2745 "in suspended state\n", __func__);
962034f4
VW		 2746}
2747
7aa65bfd
TG		 2748/*
2749 * Set default functions
2750 */
ace4dfee 2751static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2752{
1da177e4 2753 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2754 if (!chip->chip_delay)
2755 chip->chip_delay = 20;
1da177e4
LT		 2756
2757 /* check, if a user supplied command function given */
ace4dfee
TG		 2758 if (chip->cmdfunc == NULL)
2759 chip->cmdfunc = nand_command;
1da177e4
LT		 2760
2761 /* check, if a user supplied wait function given */
ace4dfee
TG		 2762 if (chip->waitfunc == NULL)
2763 chip->waitfunc = nand_wait;
2764
2765 if (!chip->select_chip)
2766 chip->select_chip = nand_select_chip;
2767 if (!chip->read_byte)
2768 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2769 if (!chip->read_word)
2770 chip->read_word = nand_read_word;
2771 if (!chip->block_bad)
2772 chip->block_bad = nand_block_bad;
2773 if (!chip->block_markbad)
2774 chip->block_markbad = nand_default_block_markbad;
2775 if (!chip->write_buf)
2776 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2777 if (!chip->read_buf)
2778 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2779 if (!chip->verify_buf)
2780 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2781 if (!chip->scan_bbt)
2782 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2783
2784 if (!chip->controller) {
2785 chip->controller = &chip->hwcontrol;
2786 spin_lock_init(&chip->controller->lock);
2787 init_waitqueue_head(&chip->controller->wq);
2788 }
2789
7aa65bfd
TG		 2790}
2791
d1e1f4e4
FF		 2792/*
2793 * sanitize ONFI strings so we can safely print them
2794 */
2795static void sanitize_string(uint8_t *s, size_t len)
2796{
2797 ssize_t i;
2798
2799 /* null terminate */
2800 s[len - 1] = 0;
2801
2802 /* remove non printable chars */
2803 for (i = 0; i < len - 1; i++) {
2804 if (s[i] < ' ' || s[i] > 127)
2805 s[i] = '?';
2806 }
2807
2808 /* remove trailing spaces */
2809 strim(s);
2810}
2811
2812static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2813{
2814 int i;
2815 while (len--) {
2816 crc ^= *p++ << 8;
2817 for (i = 0; i < 8; i++)
2818 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2819 }
2820
2821 return crc;
2822}
2823
6fb277ba
FF		 2824/*
2825 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
2826 */
2827static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2828 int busw)
2829{
2830 struct nand_onfi_params *p = &chip->onfi_params;
2831 int i;
2832 int val;
2833
2834 /* try ONFI for unknow chip or LP */
2835 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2836 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2837 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2838 return 0;
2839
2840 printk(KERN_INFO "ONFI flash detected\n");
2841 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2842 for (i = 0; i < 3; i++) {
2843 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2844 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2845 le16_to_cpu(p->crc)) {
2846 printk(KERN_INFO "ONFI param page %d valid\n", i);
2847 break;
2848 }
2849 }
2850
2851 if (i == 3)
2852 return 0;
2853
2854 /* check version */
2855 val = le16_to_cpu(p->revision);
b7b1a29d
BN		 2856 if (val & (1 << 5))
2857 chip->onfi_version = 23;
2858 else if (val & (1 << 4))
6fb277ba
FF		 2859 chip->onfi_version = 22;
2860 else if (val & (1 << 3))
2861 chip->onfi_version = 21;
2862 else if (val & (1 << 2))
2863 chip->onfi_version = 20;
b7b1a29d 2864 else if (val & (1 << 1))
6fb277ba 2865 chip->onfi_version = 10;
b7b1a29d
BN		 2866 else
2867 chip->onfi_version = 0;
2868
2869 if (!chip->onfi_version) {
2870 printk(KERN_INFO "%s: unsupported ONFI version: %d\n",
2871 __func__, val);
2872 return 0;
2873 }
6fb277ba
FF		 2874
2875 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2876 sanitize_string(p->model, sizeof(p->model));
2877 if (!mtd->name)
2878 mtd->name = p->model;
2879 mtd->writesize = le32_to_cpu(p->byte_per_page);
2880 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2881 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
4ccb3b44 2882 chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
6fb277ba
FF		 2883 busw = 0;
2884 if (le16_to_cpu(p->features) & 1)
2885 busw = NAND_BUSWIDTH_16;
2886
2887 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2888 chip->options |= (NAND_NO_READRDY |
2889 NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2890
2891 return 1;
2892}
2893
7aa65bfd 2894/*
ace4dfee 2895 * Get the flash and manufacturer id and lookup if the type is supported
7aa65bfd
TG		 2896 */
2897static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 2898 struct nand_chip *chip,
7351d3a5
FF		 2899 int busw,
2900 int *maf_id, int *dev_id,
5e81e88a 2901 struct nand_flash_dev *type)
7aa65bfd 2902{
d1e1f4e4 2903 int i, maf_idx;
426c457a 2904 u8 id_data[8];
6fb277ba 2905 int ret;
1da177e4
LT		 2906
2907 /* Select the device */
ace4dfee 2908 chip->select_chip(mtd, 0);
1da177e4 2909
ef89a880
KB		 2910 /*
2911 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2912 * after power-up
2913 */
2914 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2915
1da177e4 2916 /* Send the command for reading device ID */
ace4dfee 2917 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 2918
2919 /* Read manufacturer and device IDs */
ace4dfee 2920 *maf_id = chip->read_byte(mtd);
d1e1f4e4 2921 *dev_id = chip->read_byte(mtd);
1da177e4 2922
ed8165c7
BD		 2923 /* Try again to make sure, as some systems the bus-hold or other
2924 * interface concerns can cause random data which looks like a
2925 * possibly credible NAND flash to appear. If the two results do
2926 * not match, ignore the device completely.
2927 */
2928
2929 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2930
d1e1f4e4 2931 for (i = 0; i < 2; i++)
426c457a 2932 id_data[i] = chip->read_byte(mtd);
ed8165c7 2933
d1e1f4e4 2934 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
ed8165c7
BD		 2935 printk(KERN_INFO "%s: second ID read did not match "
2936 "%02x,%02x against %02x,%02x\n", __func__,
d1e1f4e4 2937 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 2938 return ERR_PTR(-ENODEV);
2939 }
2940
7aa65bfd 2941 if (!type)
5e81e88a
DW		 2942 type = nand_flash_ids;
2943
2944 for (; type->name != NULL; type++)
d1e1f4e4 2945 if (*dev_id == type->id)
f8ac0414 2946 break;
5e81e88a 2947
d1e1f4e4
FF		 2948 chip->onfi_version = 0;
2949 if (!type->name || !type->pagesize) {
6fb277ba
FF		 2950 /* Check is chip is ONFI compliant */
2951 ret = nand_flash_detect_onfi(mtd, chip, busw);
2952 if (ret)
2953 goto ident_done;
d1e1f4e4
FF		 2954 }
2955
2956 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2957
2958 /* Read entire ID string */
2959
2960 for (i = 0; i < 8; i++)
2961 id_data[i] = chip->read_byte(mtd);
2962
5e81e88a 2963 if (!type->name)
7aa65bfd
TG		 2964 return ERR_PTR(-ENODEV);
2965
ba0251fe
TG		 2966 if (!mtd->name)
2967 mtd->name = type->name;
2968
69423d99 2969 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 2970
12a40a57
HS		 2971 if (!type->pagesize && chip->init_size) {
2972 /* set the pagesize, oobsize, erasesize by the driver*/
2973 busw = chip->init_size(mtd, chip, id_data);
2974 } else if (!type->pagesize) {
7aa65bfd 2975 int extid;
29072b96 2976 /* The 3rd id byte holds MLC / multichip data */
426c457a 2977 chip->cellinfo = id_data[2];
7aa65bfd 2978 /* The 4th id byte is the important one */
426c457a 2979 extid = id_data[3];
61b03bd7 2980
426c457a
KC		 2981 /*
2982 * Field definitions are in the following datasheets:
2983 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
34c5bf6c 2984 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
426c457a
KC		 2985 *
2986 * Check for wraparound + Samsung ID + nonzero 6th byte
2987 * to decide what to do.
2988 */
2989 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
2990 id_data[0] == NAND_MFR_SAMSUNG &&
cfe3fdad 2991 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
426c457a
KC		 2992 id_data[5] != 0x00) {
2993 /* Calc pagesize */
2994 mtd->writesize = 2048 << (extid & 0x03);
2995 extid >>= 2;
2996 /* Calc oobsize */
34c5bf6c
BN		 2997 switch (extid & 0x03) {
2998 case 1:
2999 mtd->oobsize = 128;
3000 break;
3001 case 2:
3002 mtd->oobsize = 218;
3003 break;
3004 case 3:
3005 mtd->oobsize = 400;
3006 break;
3007 default:
3008 mtd->oobsize = 436;
3009 break;
3010 }
426c457a
KC		 3011 extid >>= 2;
3012 /* Calc blocksize */
3013 mtd->erasesize = (128 * 1024) <<
3014 (((extid >> 1) & 0x04) | (extid & 0x03));
3015 busw = 0;
3016 } else {
3017 /* Calc pagesize */
3018 mtd->writesize = 1024 << (extid & 0x03);
3019 extid >>= 2;
3020 /* Calc oobsize */
3021 mtd->oobsize = (8 << (extid & 0x01)) *
3022 (mtd->writesize >> 9);
3023 extid >>= 2;
3024 /* Calc blocksize. Blocksize is multiples of 64KiB */
3025 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3026 extid >>= 2;
3027 /* Get buswidth information */
3028 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3029 }
7aa65bfd
TG		 3030 } else {
3031 /*
ace4dfee 3032 * Old devices have chip data hardcoded in the device id table
7aa65bfd 3033 */
ba0251fe
TG		 3034 mtd->erasesize = type->erasesize;
3035 mtd->writesize = type->pagesize;
4cbb9b80 3036 mtd->oobsize = mtd->writesize / 32;
ba0251fe 3037 busw = type->options & NAND_BUSWIDTH_16;
2173bae8
BN		 3038
3039 /*
3040 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3041 * some Spansion chips have erasesize that conflicts with size
3042 * listed in nand_ids table
3043 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3044 */
3045 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3046 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3047 id_data[7] == 0x00 && mtd->writesize == 512) {
3048 mtd->erasesize = 128 * 1024;
3049 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3050 }
7aa65bfd 3051 }
d1e1f4e4
FF		 3052 /* Get chip options, preserve non chip based options */
3053 chip->options &= ~NAND_CHIPOPTIONS_MSK;
3054 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3055
3056 /* Check if chip is a not a samsung device. Do not clear the
3057 * options for chips which are not having an extended id.
3058 */
3059 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3060 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3061ident_done:
3062
3063 /*
3064 * Set chip as a default. Board drivers can override it, if necessary
3065 */
3066 chip->options |= NAND_NO_AUTOINCR;
1da177e4 3067
7aa65bfd 3068 /* Try to identify manufacturer */
9a909867 3069 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3070 if (nand_manuf_ids[maf_idx].id == *maf_id)
3071 break;
3072 }
0ea4a755 3073
7aa65bfd
TG		 3074 /*
3075 * Check, if buswidth is correct. Hardware drivers should set
ace4dfee 3076 * chip correct !
7aa65bfd 3077 */
ace4dfee 3078 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
7aa65bfd
TG		 3079 printk(KERN_INFO "NAND device: Manufacturer ID:"
3080 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
d1e1f4e4 3081 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
7aa65bfd 3082 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
ace4dfee 3083 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
7aa65bfd
TG		 3084 busw ? 16 : 8);
3085 return ERR_PTR(-EINVAL);
3086 }
61b03bd7 3087
7aa65bfd 3088 /* Calculate the address shift from the page size */
ace4dfee 3089 chip->page_shift = ffs(mtd->writesize) - 1;
7aa65bfd 3090 /* Convert chipsize to number of pages per chip -1. */
ace4dfee 3091 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3092
ace4dfee 3093 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3094 ffs(mtd->erasesize) - 1;
69423d99
AH		 3095 if (chip->chipsize & 0xffffffff)
3096 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3097 else {
3098 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3099 chip->chip_shift += 32 - 1;
3100 }
1da177e4 3101
26d9be11
AB		 3102 chip->badblockbits = 8;
3103
7aa65bfd 3104 /* Set the bad block position */
065a1ed8 3105 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
c7b28e25 3106 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
065a1ed8
BN		 3107 else
3108 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
61b03bd7 3109
b60b08b0
KC		 3110 /*
3111 * Bad block marker is stored in the last page of each block
c7b28e25
BN		 3112 * on Samsung and Hynix MLC devices; stored in first two pages
3113 * of each block on Micron devices with 2KiB pages and on
13ed7aed
BN		 3114 * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
3115 * only the first page.
b60b08b0
KC		 3116 */
3117 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3118 (*maf_id == NAND_MFR_SAMSUNG ||
3119 *maf_id == NAND_MFR_HYNIX))
30fe8115 3120 chip->options |= NAND_BBT_SCANLASTPAGE;
c7b28e25
BN		 3121 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3122 (*maf_id == NAND_MFR_SAMSUNG ||
3123 *maf_id == NAND_MFR_HYNIX ||
13ed7aed 3124 *maf_id == NAND_MFR_TOSHIBA ||
c7b28e25
BN		 3125 *maf_id == NAND_MFR_AMD)) ||
3126 (mtd->writesize == 2048 &&
3127 *maf_id == NAND_MFR_MICRON))
3128 chip->options |= NAND_BBT_SCAN2NDPAGE;
3129
7aa65bfd 3130 /* Check for AND chips with 4 page planes */
ace4dfee
TG		 3131 if (chip->options & NAND_4PAGE_ARRAY)
3132 chip->erase_cmd = multi_erase_cmd;
7aa65bfd 3133 else
ace4dfee 3134 chip->erase_cmd = single_erase_cmd;
7aa65bfd
TG		 3135
3136 /* Do not replace user supplied command function ! */
ace4dfee
TG		 3137 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3138 chip->cmdfunc = nand_command_lp;
7aa65bfd 3139
d1e1f4e4 3140 /* TODO onfi flash name */
7aa65bfd 3141 printk(KERN_INFO "NAND device: Manufacturer ID:"
d1e1f4e4
FF		 3142 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
3143 nand_manuf_ids[maf_idx].name,
0b524fb9 3144 chip->onfi_version ? chip->onfi_params.model : type->name);
7aa65bfd
TG		 3145
3146 return type;
3147}
3148
7aa65bfd 3149/**
3b85c321
DW		 3150 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3151 * @mtd: MTD device structure
3152 * @maxchips: Number of chips to scan for
5e81e88a 3153 * @table: Alternative NAND ID table
7aa65bfd 3154 *
3b85c321
DW		 3155 * This is the first phase of the normal nand_scan() function. It
3156 * reads the flash ID and sets up MTD fields accordingly.
7aa65bfd 3157 *
3b85c321 3158 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 3159 */
5e81e88a
DW		 3160int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3161 struct nand_flash_dev *table)
7aa65bfd 3162{
d1e1f4e4 3163 int i, busw, nand_maf_id, nand_dev_id;
ace4dfee 3164 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 3165 struct nand_flash_dev *type;
3166
7aa65bfd 3167 /* Get buswidth to select the correct functions */
ace4dfee 3168 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 3169 /* Set the default functions */
ace4dfee 3170 nand_set_defaults(chip, busw);
7aa65bfd
TG		 3171
3172 /* Read the flash type */
7351d3a5
FF		 3173 type = nand_get_flash_type(mtd, chip, busw,
3174 &nand_maf_id, &nand_dev_id, table);
7aa65bfd
TG		 3175
3176 if (IS_ERR(type)) {
b1c6e6db
BD		 3177 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3178 printk(KERN_WARNING "No NAND device found.\n");
ace4dfee 3179 chip->select_chip(mtd, -1);
7aa65bfd 3180 return PTR_ERR(type);
1da177e4
LT		 3181 }
3182
7aa65bfd 3183 /* Check for a chip array */
e0c7d767 3184 for (i = 1; i < maxchips; i++) {
ace4dfee 3185 chip->select_chip(mtd, i);
ef89a880
KB		 3186 /* See comment in nand_get_flash_type for reset */
3187 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 3188 /* Send the command for reading device ID */
ace4dfee 3189 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 3190 /* Read manufacturer and device IDs */
ace4dfee 3191 if (nand_maf_id != chip->read_byte(mtd) ||
d1e1f4e4 3192 nand_dev_id != chip->read_byte(mtd))
1da177e4
LT		 3193 break;
3194 }
3195 if (i > 1)
3196 printk(KERN_INFO "%d NAND chips detected\n", i);
61b03bd7 3197
1da177e4 3198 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 3199 chip->numchips = i;
3200 mtd->size = i * chip->chipsize;
7aa65bfd 3201
3b85c321
DW		 3202 return 0;
3203}
7351d3a5 3204EXPORT_SYMBOL(nand_scan_ident);
3b85c321
DW		 3205
3206
3207/**
3208 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3209 * @mtd: MTD device structure
3b85c321
DW		 3210 *
3211 * This is the second phase of the normal nand_scan() function. It
3212 * fills out all the uninitialized function pointers with the defaults
3213 * and scans for a bad block table if appropriate.
3214 */
3215int nand_scan_tail(struct mtd_info *mtd)
3216{
3217 int i;
3218 struct nand_chip *chip = mtd->priv;
3219
4bf63fcb
DW		 3220 if (!(chip->options & NAND_OWN_BUFFERS))
3221 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3222 if (!chip->buffers)
3223 return -ENOMEM;
3224
7dcdcbef 3225 /* Set the internal oob buffer location, just after the page data */
784f4d5e 3226 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3227
7aa65bfd
TG		 3228 /*
3229 * If no default placement scheme is given, select an appropriate one
3230 */
193bd400 3231 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
61b03bd7 3232 switch (mtd->oobsize) {
1da177e4 3233 case 8:
5bd34c09 3234 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 3235 break;
3236 case 16:
5bd34c09 3237 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 3238 break;
3239 case 64:
5bd34c09 3240 chip->ecc.layout = &nand_oob_64;
1da177e4 3241 break;
81ec5364
TG		 3242 case 128:
3243 chip->ecc.layout = &nand_oob_128;
3244 break;
1da177e4 3245 default:
7aa65bfd
TG		 3246 printk(KERN_WARNING "No oob scheme defined for "
3247 "oobsize %d\n", mtd->oobsize);
1da177e4
LT		 3248 BUG();
3249 }
3250 }
61b03bd7 3251
956e944c
DW		 3252 if (!chip->write_page)
3253 chip->write_page = nand_write_page;
3254
61b03bd7 3255 /*
7aa65bfd
TG		 3256 * check ECC mode, default to software if 3byte/512byte hardware ECC is
3257 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3258 */
956e944c 3259
ace4dfee 3260 switch (chip->ecc.mode) {
6e0cb135
SN		 3261 case NAND_ECC_HW_OOB_FIRST:
3262 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3263 if (!chip->ecc.calculate || !chip->ecc.correct ||
3264 !chip->ecc.hwctl) {
3265 printk(KERN_WARNING "No ECC functions supplied; "
3266 "Hardware ECC not possible\n");
3267 BUG();
3268 }
3269 if (!chip->ecc.read_page)
3270 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3271
6dfc6d25 3272 case NAND_ECC_HW:
f5bbdacc
TG		 3273 /* Use standard hwecc read page function ? */
3274 if (!chip->ecc.read_page)
3275 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 3276 if (!chip->ecc.write_page)
3277 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 3278 if (!chip->ecc.read_page_raw)
3279 chip->ecc.read_page_raw = nand_read_page_raw;
3280 if (!chip->ecc.write_page_raw)
3281 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3282 if (!chip->ecc.read_oob)
3283 chip->ecc.read_oob = nand_read_oob_std;
3284 if (!chip->ecc.write_oob)
3285 chip->ecc.write_oob = nand_write_oob_std;
f5bbdacc 3286
6dfc6d25 3287 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 3288 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3289 !chip->ecc.hwctl) &&
3290 (!chip->ecc.read_page ||
1c45f604 3291 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 3292 !chip->ecc.write_page ||
1c45f604 3293 chip->ecc.write_page == nand_write_page_hwecc)) {
6e0cb135 3294 printk(KERN_WARNING "No ECC functions supplied; "
6dfc6d25
TG		 3295 "Hardware ECC not possible\n");
3296 BUG();
3297 }
f75e5097 3298 /* Use standard syndrome read/write page function ? */
f5bbdacc
TG		 3299 if (!chip->ecc.read_page)
3300 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 3301 if (!chip->ecc.write_page)
3302 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 3303 if (!chip->ecc.read_page_raw)
3304 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3305 if (!chip->ecc.write_page_raw)
3306 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 3307 if (!chip->ecc.read_oob)
3308 chip->ecc.read_oob = nand_read_oob_syndrome;
3309 if (!chip->ecc.write_oob)
3310 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 3311
ace4dfee 3312 if (mtd->writesize >= chip->ecc.size)
6dfc6d25
TG		 3313 break;
3314 printk(KERN_WARNING "%d byte HW ECC not possible on "
3315 "%d byte page size, fallback to SW ECC\n",
ace4dfee
TG		 3316 chip->ecc.size, mtd->writesize);
3317 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 3318
6dfc6d25 3319 case NAND_ECC_SOFT:
ace4dfee
TG		 3320 chip->ecc.calculate = nand_calculate_ecc;
3321 chip->ecc.correct = nand_correct_data;
f5bbdacc 3322 chip->ecc.read_page = nand_read_page_swecc;
3d459559 3323 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 3324 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 3325 chip->ecc.read_page_raw = nand_read_page_raw;
3326 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3327 chip->ecc.read_oob = nand_read_oob_std;
3328 chip->ecc.write_oob = nand_write_oob_std;
9a73290d
SV		 3329 if (!chip->ecc.size)
3330 chip->ecc.size = 256;
ace4dfee 3331 chip->ecc.bytes = 3;
1da177e4 3332 break;
61b03bd7 3333
193bd400
ID		 3334 case NAND_ECC_SOFT_BCH:
3335 if (!mtd_nand_has_bch()) {
3336 printk(KERN_WARNING "CONFIG_MTD_ECC_BCH not enabled\n");
3337 BUG();
3338 }
3339 chip->ecc.calculate = nand_bch_calculate_ecc;
3340 chip->ecc.correct = nand_bch_correct_data;
3341 chip->ecc.read_page = nand_read_page_swecc;
3342 chip->ecc.read_subpage = nand_read_subpage;
3343 chip->ecc.write_page = nand_write_page_swecc;
3344 chip->ecc.read_page_raw = nand_read_page_raw;
3345 chip->ecc.write_page_raw = nand_write_page_raw;
3346 chip->ecc.read_oob = nand_read_oob_std;
3347 chip->ecc.write_oob = nand_write_oob_std;
3348 /*
3349 * Board driver should supply ecc.size and ecc.bytes values to
3350 * select how many bits are correctable; see nand_bch_init()
3351 * for details.
3352 * Otherwise, default to 4 bits for large page devices
3353 */
3354 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3355 chip->ecc.size = 512;
3356 chip->ecc.bytes = 7;
3357 }
3358 chip->ecc.priv = nand_bch_init(mtd,
3359 chip->ecc.size,
3360 chip->ecc.bytes,
3361 &chip->ecc.layout);
3362 if (!chip->ecc.priv) {
3363 printk(KERN_WARNING "BCH ECC initialization failed!\n");
3364 BUG();
3365 }
3366 break;
3367
61b03bd7 3368 case NAND_ECC_NONE:
7aa65bfd
TG		 3369 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
3370 "This is not recommended !!\n");
8593fbc6
TG		 3371 chip->ecc.read_page = nand_read_page_raw;
3372 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 3373 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 3374 chip->ecc.read_page_raw = nand_read_page_raw;
3375 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 3376 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 3377 chip->ecc.size = mtd->writesize;
3378 chip->ecc.bytes = 0;
1da177e4 3379 break;
956e944c 3380
1da177e4 3381 default:
7aa65bfd 3382 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
ace4dfee 3383 chip->ecc.mode);
61b03bd7 3384 BUG();
1da177e4 3385 }
61b03bd7 3386
5bd34c09
TG		 3387 /*
3388 * The number of bytes available for a client to place data into
3389 * the out of band area
3390 */
3391 chip->ecc.layout->oobavail = 0;
81d19b04
DB		 3392 for (i = 0; chip->ecc.layout->oobfree[i].length
3393 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
5bd34c09
TG		 3394 chip->ecc.layout->oobavail +=
3395 chip->ecc.layout->oobfree[i].length;
1f92267c 3396 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 3397
7aa65bfd
TG		 3398 /*
3399 * Set the number of read / write steps for one page depending on ECC
3400 * mode
3401 */
ace4dfee 3402 chip->ecc.steps = mtd->writesize / chip->ecc.size;
f8ac0414 3403 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
6dfc6d25
TG		 3404 printk(KERN_WARNING "Invalid ecc parameters\n");
3405 BUG();
1da177e4 3406 }
f5bbdacc 3407 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 3408
29072b96
TG		 3409 /*
3410 * Allow subpage writes up to ecc.steps. Not possible for MLC
3411 * FLASH.
3412 */
3413 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3414 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
f8ac0414 3415 switch (chip->ecc.steps) {
29072b96
TG		 3416 case 2:
3417 mtd->subpage_sft = 1;
3418 break;
3419 case 4:
3420 case 8:
81ec5364 3421 case 16:
29072b96
TG		 3422 mtd->subpage_sft = 2;
3423 break;
3424 }
3425 }
3426 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3427
04bbd0ea 3428 /* Initialize state */
ace4dfee 3429 chip->state = FL_READY;
1da177e4
LT		 3430
3431 /* De-select the device */
ace4dfee 3432 chip->select_chip(mtd, -1);
1da177e4
LT		 3433
3434 /* Invalidate the pagebuffer reference */
ace4dfee 3435 chip->pagebuf = -1;
1da177e4
LT		 3436
3437 /* Fill in remaining MTD driver data */
3438 mtd->type = MTD_NANDFLASH;
93edbad6
ML		 3439 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3440 MTD_CAP_NANDFLASH;
1da177e4
LT		 3441 mtd->erase = nand_erase;
3442 mtd->point = NULL;
3443 mtd->unpoint = NULL;
3444 mtd->read = nand_read;
3445 mtd->write = nand_write;
2af7c653 3446 mtd->panic_write = panic_nand_write;
1da177e4
LT		 3447 mtd->read_oob = nand_read_oob;
3448 mtd->write_oob = nand_write_oob;
1da177e4
LT		 3449 mtd->sync = nand_sync;
3450 mtd->lock = NULL;
3451 mtd->unlock = NULL;
962034f4
VW		 3452 mtd->suspend = nand_suspend;
3453 mtd->resume = nand_resume;
1da177e4
LT		 3454 mtd->block_isbad = nand_block_isbad;
3455 mtd->block_markbad = nand_block_markbad;
cbcab65a 3456 mtd->writebufsize = mtd->writesize;
1da177e4 3457
5bd34c09
TG		 3458 /* propagate ecc.layout to mtd_info */
3459 mtd->ecclayout = chip->ecc.layout;
1da177e4 3460
0040bf38 3461 /* Check, if we should skip the bad block table scan */
ace4dfee 3462 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 3463 return 0;
1da177e4
LT		 3464
3465 /* Build bad block table */
ace4dfee 3466 return chip->scan_bbt(mtd);
1da177e4 3467}
7351d3a5 3468EXPORT_SYMBOL(nand_scan_tail);
1da177e4 3469
a6e6abd5 3470/* is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5
FF		 3471 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3472 * to call us from in-kernel code if the core NAND support is modular. */
3b85c321
DW		 3473#ifdef MODULE
3474#define caller_is_module() (1)
3475#else
3476#define caller_is_module() \
a6e6abd5 3477 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 3478#endif
3479
3480/**
3481 * nand_scan - [NAND Interface] Scan for the NAND device
3482 * @mtd: MTD device structure
3483 * @maxchips: Number of chips to scan for
3484 *
3485 * This fills out all the uninitialized function pointers
3486 * with the defaults.
3487 * The flash ID is read and the mtd/chip structures are
3488 * filled with the appropriate values.
3489 * The mtd->owner field must be set to the module of the caller
3490 *
3491 */
3492int nand_scan(struct mtd_info *mtd, int maxchips)
3493{
3494 int ret;
3495
3496 /* Many callers got this wrong, so check for it for a while... */
3497 if (!mtd->owner && caller_is_module()) {
20d8e248 3498 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
3499 __func__);
3b85c321
DW		 3500 BUG();
3501 }
3502
5e81e88a 3503 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 3504 if (!ret)
3505 ret = nand_scan_tail(mtd);
3506 return ret;
3507}
7351d3a5 3508EXPORT_SYMBOL(nand_scan);
3b85c321 3509
1da177e4 3510/**
61b03bd7 3511 * nand_release - [NAND Interface] Free resources held by the NAND device
1da177e4
LT		 3512 * @mtd: MTD device structure
3513*/
e0c7d767 3514void nand_release(struct mtd_info *mtd)
1da177e4 3515{
ace4dfee 3516 struct nand_chip *chip = mtd->priv;
1da177e4 3517
193bd400
ID		 3518 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3519 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3520
5ffcaf3d 3521 mtd_device_unregister(mtd);
1da177e4 3522
fa671646 3523 /* Free bad block table memory */
ace4dfee 3524 kfree(chip->bbt);
4bf63fcb
DW		 3525 if (!(chip->options & NAND_OWN_BUFFERS))
3526 kfree(chip->buffers);
58373ff0
BN		 3527
3528 /* Free bad block descriptor memory */
3529 if (chip->badblock_pattern && chip->badblock_pattern->options
3530 & NAND_BBT_DYNAMICSTRUCT)
3531 kfree(chip->badblock_pattern);
1da177e4 3532}
e0c7d767 3533EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 3534
3535static int __init nand_base_init(void)
3536{
3537 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3538 return 0;
3539}
3540
3541static void __exit nand_base_exit(void)
3542{
3543 led_trigger_unregister_simple(nand_led_trigger);
3544}
3545
3546module_init(nand_base_init);
3547module_exit(nand_base_exit);
3548
e0c7d767 3549MODULE_LICENSE("GPL");
7351d3a5
FF		 3550MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3551MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 3552MODULE_DESCRIPTION("Generic NAND flash driver code");
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