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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand.c | |
3 | * | |
4 | * Overview: | |
5 | * This is the generic MTD driver for NAND flash devices. It should be | |
6 | * capable of working with almost all NAND chips currently available. | |
7 | * Basic support for AG-AND chips is provided. | |
61b03bd7 | 8 | * |
1da177e4 | 9 | * Additional technical information is available on |
8b2b403c | 10 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 11 | * |
1da177e4 | 12 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 13 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 14 | * |
ace4dfee | 15 | * Credits: |
61b03bd7 TG |
16 | * David Woodhouse for adding multichip support |
17 | * | |
1da177e4 LT |
18 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
19 | * rework for 2K page size chips | |
20 | * | |
ace4dfee | 21 | * TODO: |
1da177e4 LT |
22 | * Enable cached programming for 2k page size chips |
23 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
7854d3f7 | 24 | * if we have HW ECC support. |
1da177e4 LT |
25 | * The AG-AND chips have nice features for speed improvement, |
26 | * which are not supported yet. Read / program 4 pages in one go. | |
c0b8ba7b | 27 | * BBT table is not serialized, has to be fixed |
1da177e4 | 28 | * |
1da177e4 LT |
29 | * This program is free software; you can redistribute it and/or modify |
30 | * it under the terms of the GNU General Public License version 2 as | |
31 | * published by the Free Software Foundation. | |
32 | * | |
33 | */ | |
34 | ||
552d9205 | 35 | #include <linux/module.h> |
1da177e4 LT |
36 | #include <linux/delay.h> |
37 | #include <linux/errno.h> | |
7aa65bfd | 38 | #include <linux/err.h> |
1da177e4 LT |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
41 | #include <linux/types.h> | |
42 | #include <linux/mtd/mtd.h> | |
43 | #include <linux/mtd/nand.h> | |
44 | #include <linux/mtd/nand_ecc.h> | |
193bd400 | 45 | #include <linux/mtd/nand_bch.h> |
1da177e4 LT |
46 | #include <linux/interrupt.h> |
47 | #include <linux/bitops.h> | |
8fe833c1 | 48 | #include <linux/leds.h> |
7351d3a5 | 49 | #include <linux/io.h> |
1da177e4 | 50 | #include <linux/mtd/partitions.h> |
1da177e4 LT |
51 | |
52 | /* Define default oob placement schemes for large and small page devices */ | |
5bd34c09 | 53 | static struct nand_ecclayout nand_oob_8 = { |
1da177e4 LT |
54 | .eccbytes = 3, |
55 | .eccpos = {0, 1, 2}, | |
5bd34c09 TG |
56 | .oobfree = { |
57 | {.offset = 3, | |
58 | .length = 2}, | |
59 | {.offset = 6, | |
f8ac0414 | 60 | .length = 2} } |
1da177e4 LT |
61 | }; |
62 | ||
5bd34c09 | 63 | static struct nand_ecclayout nand_oob_16 = { |
1da177e4 LT |
64 | .eccbytes = 6, |
65 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
5bd34c09 TG |
66 | .oobfree = { |
67 | {.offset = 8, | |
f8ac0414 | 68 | . length = 8} } |
1da177e4 LT |
69 | }; |
70 | ||
5bd34c09 | 71 | static struct nand_ecclayout nand_oob_64 = { |
1da177e4 LT |
72 | .eccbytes = 24, |
73 | .eccpos = { | |
e0c7d767 DW |
74 | 40, 41, 42, 43, 44, 45, 46, 47, |
75 | 48, 49, 50, 51, 52, 53, 54, 55, | |
76 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
5bd34c09 TG |
77 | .oobfree = { |
78 | {.offset = 2, | |
f8ac0414 | 79 | .length = 38} } |
1da177e4 LT |
80 | }; |
81 | ||
81ec5364 TG |
82 | static struct nand_ecclayout nand_oob_128 = { |
83 | .eccbytes = 48, | |
84 | .eccpos = { | |
85 | 80, 81, 82, 83, 84, 85, 86, 87, | |
86 | 88, 89, 90, 91, 92, 93, 94, 95, | |
87 | 96, 97, 98, 99, 100, 101, 102, 103, | |
88 | 104, 105, 106, 107, 108, 109, 110, 111, | |
89 | 112, 113, 114, 115, 116, 117, 118, 119, | |
90 | 120, 121, 122, 123, 124, 125, 126, 127}, | |
91 | .oobfree = { | |
92 | {.offset = 2, | |
f8ac0414 | 93 | .length = 78} } |
81ec5364 TG |
94 | }; |
95 | ||
ace4dfee | 96 | static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, |
2c0a2bed | 97 | int new_state); |
1da177e4 | 98 | |
8593fbc6 TG |
99 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
100 | struct mtd_oob_ops *ops); | |
101 | ||
d470a97c | 102 | /* |
8e87d782 | 103 | * For devices which display every fart in the system on a separate LED. Is |
d470a97c TG |
104 | * compiled away when LED support is disabled. |
105 | */ | |
106 | DEFINE_LED_TRIGGER(nand_led_trigger); | |
107 | ||
6fe5a6ac VS |
108 | static int check_offs_len(struct mtd_info *mtd, |
109 | loff_t ofs, uint64_t len) | |
110 | { | |
111 | struct nand_chip *chip = mtd->priv; | |
112 | int ret = 0; | |
113 | ||
114 | /* Start address must align on block boundary */ | |
115 | if (ofs & ((1 << chip->phys_erase_shift) - 1)) { | |
289c0522 | 116 | pr_debug("%s: unaligned address\n", __func__); |
6fe5a6ac VS |
117 | ret = -EINVAL; |
118 | } | |
119 | ||
120 | /* Length must align on block boundary */ | |
121 | if (len & ((1 << chip->phys_erase_shift) - 1)) { | |
289c0522 | 122 | pr_debug("%s: length not block aligned\n", __func__); |
6fe5a6ac VS |
123 | ret = -EINVAL; |
124 | } | |
125 | ||
6fe5a6ac VS |
126 | return ret; |
127 | } | |
128 | ||
1da177e4 LT |
129 | /** |
130 | * nand_release_device - [GENERIC] release chip | |
8b6e50c9 | 131 | * @mtd: MTD device structure |
61b03bd7 | 132 | * |
b0bb6903 | 133 | * Release chip lock and wake up anyone waiting on the device. |
1da177e4 | 134 | */ |
e0c7d767 | 135 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 136 | { |
ace4dfee | 137 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 138 | |
a36ed299 | 139 | /* Release the controller and the chip */ |
ace4dfee TG |
140 | spin_lock(&chip->controller->lock); |
141 | chip->controller->active = NULL; | |
142 | chip->state = FL_READY; | |
143 | wake_up(&chip->controller->wq); | |
144 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
145 | } |
146 | ||
147 | /** | |
148 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
8b6e50c9 | 149 | * @mtd: MTD device structure |
1da177e4 | 150 | * |
7854d3f7 | 151 | * Default read function for 8bit buswidth |
1da177e4 | 152 | */ |
58dd8f2b | 153 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 154 | { |
ace4dfee TG |
155 | struct nand_chip *chip = mtd->priv; |
156 | return readb(chip->IO_ADDR_R); | |
1da177e4 LT |
157 | } |
158 | ||
1da177e4 | 159 | /** |
064a7694 | 160 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
7854d3f7 | 161 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
8b6e50c9 | 162 | * @mtd: MTD device structure |
1da177e4 | 163 | * |
7854d3f7 BN |
164 | * Default read function for 16bit buswidth with endianness conversion. |
165 | * | |
1da177e4 | 166 | */ |
58dd8f2b | 167 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 168 | { |
ace4dfee TG |
169 | struct nand_chip *chip = mtd->priv; |
170 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); | |
1da177e4 LT |
171 | } |
172 | ||
1da177e4 LT |
173 | /** |
174 | * nand_read_word - [DEFAULT] read one word from the chip | |
8b6e50c9 | 175 | * @mtd: MTD device structure |
1da177e4 | 176 | * |
7854d3f7 | 177 | * Default read function for 16bit buswidth without endianness conversion. |
1da177e4 LT |
178 | */ |
179 | static u16 nand_read_word(struct mtd_info *mtd) | |
180 | { | |
ace4dfee TG |
181 | struct nand_chip *chip = mtd->priv; |
182 | return readw(chip->IO_ADDR_R); | |
1da177e4 LT |
183 | } |
184 | ||
1da177e4 LT |
185 | /** |
186 | * nand_select_chip - [DEFAULT] control CE line | |
8b6e50c9 BN |
187 | * @mtd: MTD device structure |
188 | * @chipnr: chipnumber to select, -1 for deselect | |
1da177e4 LT |
189 | * |
190 | * Default select function for 1 chip devices. | |
191 | */ | |
ace4dfee | 192 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 193 | { |
ace4dfee TG |
194 | struct nand_chip *chip = mtd->priv; |
195 | ||
196 | switch (chipnr) { | |
1da177e4 | 197 | case -1: |
ace4dfee | 198 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
199 | break; |
200 | case 0: | |
1da177e4 LT |
201 | break; |
202 | ||
203 | default: | |
204 | BUG(); | |
205 | } | |
206 | } | |
207 | ||
208 | /** | |
209 | * nand_write_buf - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
210 | * @mtd: MTD device structure |
211 | * @buf: data buffer | |
212 | * @len: number of bytes to write | |
1da177e4 | 213 | * |
7854d3f7 | 214 | * Default write function for 8bit buswidth. |
1da177e4 | 215 | */ |
58dd8f2b | 216 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
217 | { |
218 | int i; | |
ace4dfee | 219 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 220 | |
e0c7d767 | 221 | for (i = 0; i < len; i++) |
ace4dfee | 222 | writeb(buf[i], chip->IO_ADDR_W); |
1da177e4 LT |
223 | } |
224 | ||
225 | /** | |
61b03bd7 | 226 | * nand_read_buf - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
227 | * @mtd: MTD device structure |
228 | * @buf: buffer to store date | |
229 | * @len: number of bytes to read | |
1da177e4 | 230 | * |
7854d3f7 | 231 | * Default read function for 8bit buswidth. |
1da177e4 | 232 | */ |
58dd8f2b | 233 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
234 | { |
235 | int i; | |
ace4dfee | 236 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 237 | |
e0c7d767 | 238 | for (i = 0; i < len; i++) |
ace4dfee | 239 | buf[i] = readb(chip->IO_ADDR_R); |
1da177e4 LT |
240 | } |
241 | ||
1da177e4 LT |
242 | /** |
243 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
244 | * @mtd: MTD device structure |
245 | * @buf: data buffer | |
246 | * @len: number of bytes to write | |
1da177e4 | 247 | * |
7854d3f7 | 248 | * Default write function for 16bit buswidth. |
1da177e4 | 249 | */ |
58dd8f2b | 250 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 LT |
251 | { |
252 | int i; | |
ace4dfee | 253 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
254 | u16 *p = (u16 *) buf; |
255 | len >>= 1; | |
61b03bd7 | 256 | |
e0c7d767 | 257 | for (i = 0; i < len; i++) |
ace4dfee | 258 | writew(p[i], chip->IO_ADDR_W); |
61b03bd7 | 259 | |
1da177e4 LT |
260 | } |
261 | ||
262 | /** | |
61b03bd7 | 263 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
264 | * @mtd: MTD device structure |
265 | * @buf: buffer to store date | |
266 | * @len: number of bytes to read | |
1da177e4 | 267 | * |
7854d3f7 | 268 | * Default read function for 16bit buswidth. |
1da177e4 | 269 | */ |
58dd8f2b | 270 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 LT |
271 | { |
272 | int i; | |
ace4dfee | 273 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
274 | u16 *p = (u16 *) buf; |
275 | len >>= 1; | |
276 | ||
e0c7d767 | 277 | for (i = 0; i < len; i++) |
ace4dfee | 278 | p[i] = readw(chip->IO_ADDR_R); |
1da177e4 LT |
279 | } |
280 | ||
1da177e4 LT |
281 | /** |
282 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
8b6e50c9 BN |
283 | * @mtd: MTD device structure |
284 | * @ofs: offset from device start | |
285 | * @getchip: 0, if the chip is already selected | |
1da177e4 | 286 | * |
61b03bd7 | 287 | * Check, if the block is bad. |
1da177e4 LT |
288 | */ |
289 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) | |
290 | { | |
cdbec050 | 291 | int page, chipnr, res = 0, i = 0; |
ace4dfee | 292 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
293 | u16 bad; |
294 | ||
5fb1549d | 295 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
296 | ofs += mtd->erasesize - mtd->writesize; |
297 | ||
1a12f46a TK |
298 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
299 | ||
1da177e4 | 300 | if (getchip) { |
ace4dfee | 301 | chipnr = (int)(ofs >> chip->chip_shift); |
1da177e4 | 302 | |
ace4dfee | 303 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 LT |
304 | |
305 | /* Select the NAND device */ | |
ace4dfee | 306 | chip->select_chip(mtd, chipnr); |
1a12f46a | 307 | } |
1da177e4 | 308 | |
cdbec050 BN |
309 | do { |
310 | if (chip->options & NAND_BUSWIDTH_16) { | |
311 | chip->cmdfunc(mtd, NAND_CMD_READOOB, | |
312 | chip->badblockpos & 0xFE, page); | |
313 | bad = cpu_to_le16(chip->read_word(mtd)); | |
314 | if (chip->badblockpos & 0x1) | |
315 | bad >>= 8; | |
316 | else | |
317 | bad &= 0xFF; | |
318 | } else { | |
319 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, | |
320 | page); | |
321 | bad = chip->read_byte(mtd); | |
322 | } | |
323 | ||
324 | if (likely(chip->badblockbits == 8)) | |
325 | res = bad != 0xFF; | |
e0b58d0a | 326 | else |
cdbec050 BN |
327 | res = hweight8(bad) < chip->badblockbits; |
328 | ofs += mtd->writesize; | |
329 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; | |
330 | i++; | |
331 | } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); | |
e0b58d0a | 332 | |
b0bb6903 HS |
333 | if (getchip) { |
334 | chip->select_chip(mtd, -1); | |
1da177e4 | 335 | nand_release_device(mtd); |
b0bb6903 | 336 | } |
61b03bd7 | 337 | |
1da177e4 LT |
338 | return res; |
339 | } | |
340 | ||
341 | /** | |
342 | * nand_default_block_markbad - [DEFAULT] mark a block bad | |
8b6e50c9 BN |
343 | * @mtd: MTD device structure |
344 | * @ofs: offset from device start | |
1da177e4 | 345 | * |
8b6e50c9 | 346 | * This is the default implementation, which can be overridden by a hardware |
e2414f4c BN |
347 | * specific driver. We try operations in the following order, according to our |
348 | * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH): | |
349 | * (1) erase the affected block, to allow OOB marker to be written cleanly | |
350 | * (2) update in-memory BBT | |
351 | * (3) write bad block marker to OOB area of affected block | |
352 | * (4) update flash-based BBT | |
353 | * Note that we retain the first error encountered in (3) or (4), finish the | |
354 | * procedures, and dump the error in the end. | |
1da177e4 LT |
355 | */ |
356 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
357 | { | |
ace4dfee | 358 | struct nand_chip *chip = mtd->priv; |
58dd8f2b | 359 | uint8_t buf[2] = { 0, 0 }; |
e2414f4c BN |
360 | int block, res, ret = 0, i = 0; |
361 | int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM); | |
61b03bd7 | 362 | |
e2414f4c | 363 | if (write_oob) { |
00918429 BN |
364 | struct erase_info einfo; |
365 | ||
366 | /* Attempt erase before marking OOB */ | |
367 | memset(&einfo, 0, sizeof(einfo)); | |
368 | einfo.mtd = mtd; | |
369 | einfo.addr = ofs; | |
370 | einfo.len = 1 << chip->phys_erase_shift; | |
371 | nand_erase_nand(mtd, &einfo, 0); | |
372 | } | |
373 | ||
1da177e4 | 374 | /* Get block number */ |
4226b510 | 375 | block = (int)(ofs >> chip->bbt_erase_shift); |
e2414f4c | 376 | /* Mark block bad in memory-based BBT */ |
ace4dfee TG |
377 | if (chip->bbt) |
378 | chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); | |
1da177e4 | 379 | |
e2414f4c BN |
380 | /* Write bad block marker to OOB */ |
381 | if (write_oob) { | |
4a89ff88 | 382 | struct mtd_oob_ops ops; |
df698621 | 383 | loff_t wr_ofs = ofs; |
4a89ff88 | 384 | |
c0b8ba7b | 385 | nand_get_device(chip, mtd, FL_WRITING); |
f1a28c02 | 386 | |
4a89ff88 BN |
387 | ops.datbuf = NULL; |
388 | ops.oobbuf = buf; | |
85443319 BN |
389 | ops.ooboffs = chip->badblockpos; |
390 | if (chip->options & NAND_BUSWIDTH_16) { | |
391 | ops.ooboffs &= ~0x01; | |
392 | ops.len = ops.ooblen = 2; | |
393 | } else { | |
394 | ops.len = ops.ooblen = 1; | |
395 | } | |
23b1a99b | 396 | ops.mode = MTD_OPS_PLACE_OOB; |
df698621 | 397 | |
e2414f4c | 398 | /* Write to first/last page(s) if necessary */ |
df698621 BN |
399 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
400 | wr_ofs += mtd->erasesize - mtd->writesize; | |
02ed70bb | 401 | do { |
e2414f4c BN |
402 | res = nand_do_write_oob(mtd, wr_ofs, &ops); |
403 | if (!ret) | |
404 | ret = res; | |
02ed70bb | 405 | |
02ed70bb | 406 | i++; |
df698621 | 407 | wr_ofs += mtd->writesize; |
e2414f4c | 408 | } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); |
02ed70bb | 409 | |
c0b8ba7b | 410 | nand_release_device(mtd); |
f1a28c02 | 411 | } |
e2414f4c BN |
412 | |
413 | /* Update flash-based bad block table */ | |
414 | if (chip->bbt_options & NAND_BBT_USE_FLASH) { | |
415 | res = nand_update_bbt(mtd, ofs); | |
416 | if (!ret) | |
417 | ret = res; | |
418 | } | |
419 | ||
f1a28c02 TG |
420 | if (!ret) |
421 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 422 | |
f1a28c02 | 423 | return ret; |
1da177e4 LT |
424 | } |
425 | ||
61b03bd7 | 426 | /** |
1da177e4 | 427 | * nand_check_wp - [GENERIC] check if the chip is write protected |
8b6e50c9 | 428 | * @mtd: MTD device structure |
1da177e4 | 429 | * |
8b6e50c9 BN |
430 | * Check, if the device is write protected. The function expects, that the |
431 | * device is already selected. | |
1da177e4 | 432 | */ |
e0c7d767 | 433 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 434 | { |
ace4dfee | 435 | struct nand_chip *chip = mtd->priv; |
93edbad6 | 436 | |
8b6e50c9 | 437 | /* Broken xD cards report WP despite being writable */ |
93edbad6 ML |
438 | if (chip->options & NAND_BROKEN_XD) |
439 | return 0; | |
440 | ||
1da177e4 | 441 | /* Check the WP bit */ |
ace4dfee TG |
442 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
443 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
444 | } |
445 | ||
446 | /** | |
447 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
8b6e50c9 BN |
448 | * @mtd: MTD device structure |
449 | * @ofs: offset from device start | |
450 | * @getchip: 0, if the chip is already selected | |
451 | * @allowbbt: 1, if its allowed to access the bbt area | |
1da177e4 LT |
452 | * |
453 | * Check, if the block is bad. Either by reading the bad block table or | |
454 | * calling of the scan function. | |
455 | */ | |
2c0a2bed TG |
456 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, |
457 | int allowbbt) | |
1da177e4 | 458 | { |
ace4dfee | 459 | struct nand_chip *chip = mtd->priv; |
61b03bd7 | 460 | |
ace4dfee TG |
461 | if (!chip->bbt) |
462 | return chip->block_bad(mtd, ofs, getchip); | |
61b03bd7 | 463 | |
1da177e4 | 464 | /* Return info from the table */ |
e0c7d767 | 465 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
466 | } |
467 | ||
2af7c653 SK |
468 | /** |
469 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
8b6e50c9 BN |
470 | * @mtd: MTD device structure |
471 | * @timeo: Timeout | |
2af7c653 SK |
472 | * |
473 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
474 | * context. | |
475 | */ | |
476 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
477 | { | |
478 | struct nand_chip *chip = mtd->priv; | |
479 | int i; | |
480 | ||
481 | /* Wait for the device to get ready */ | |
482 | for (i = 0; i < timeo; i++) { | |
483 | if (chip->dev_ready(mtd)) | |
484 | break; | |
485 | touch_softlockup_watchdog(); | |
486 | mdelay(1); | |
487 | } | |
488 | } | |
489 | ||
7854d3f7 | 490 | /* Wait for the ready pin, after a command. The timeout is caught later. */ |
4b648b02 | 491 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 492 | { |
ace4dfee | 493 | struct nand_chip *chip = mtd->priv; |
e0c7d767 | 494 | unsigned long timeo = jiffies + 2; |
3b88775c | 495 | |
2af7c653 SK |
496 | /* 400ms timeout */ |
497 | if (in_interrupt() || oops_in_progress) | |
498 | return panic_nand_wait_ready(mtd, 400); | |
499 | ||
8fe833c1 | 500 | led_trigger_event(nand_led_trigger, LED_FULL); |
7854d3f7 | 501 | /* Wait until command is processed or timeout occurs */ |
3b88775c | 502 | do { |
ace4dfee | 503 | if (chip->dev_ready(mtd)) |
8fe833c1 | 504 | break; |
8446f1d3 | 505 | touch_softlockup_watchdog(); |
61b03bd7 | 506 | } while (time_before(jiffies, timeo)); |
8fe833c1 | 507 | led_trigger_event(nand_led_trigger, LED_OFF); |
3b88775c | 508 | } |
4b648b02 | 509 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 510 | |
1da177e4 LT |
511 | /** |
512 | * nand_command - [DEFAULT] Send command to NAND device | |
8b6e50c9 BN |
513 | * @mtd: MTD device structure |
514 | * @command: the command to be sent | |
515 | * @column: the column address for this command, -1 if none | |
516 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 517 | * |
8b6e50c9 BN |
518 | * Send command to NAND device. This function is used for small page devices |
519 | * (256/512 Bytes per page). | |
1da177e4 | 520 | */ |
7abd3ef9 TG |
521 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
522 | int column, int page_addr) | |
1da177e4 | 523 | { |
ace4dfee | 524 | register struct nand_chip *chip = mtd->priv; |
7abd3ef9 | 525 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 526 | |
8b6e50c9 | 527 | /* Write out the command to the device */ |
1da177e4 LT |
528 | if (command == NAND_CMD_SEQIN) { |
529 | int readcmd; | |
530 | ||
28318776 | 531 | if (column >= mtd->writesize) { |
1da177e4 | 532 | /* OOB area */ |
28318776 | 533 | column -= mtd->writesize; |
1da177e4 LT |
534 | readcmd = NAND_CMD_READOOB; |
535 | } else if (column < 256) { | |
536 | /* First 256 bytes --> READ0 */ | |
537 | readcmd = NAND_CMD_READ0; | |
538 | } else { | |
539 | column -= 256; | |
540 | readcmd = NAND_CMD_READ1; | |
541 | } | |
ace4dfee | 542 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 543 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 544 | } |
ace4dfee | 545 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 546 | |
8b6e50c9 | 547 | /* Address cycle, when necessary */ |
7abd3ef9 TG |
548 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; |
549 | /* Serially input address */ | |
550 | if (column != -1) { | |
551 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 552 | if (chip->options & NAND_BUSWIDTH_16) |
7abd3ef9 | 553 | column >>= 1; |
ace4dfee | 554 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
555 | ctrl &= ~NAND_CTRL_CHANGE; |
556 | } | |
557 | if (page_addr != -1) { | |
ace4dfee | 558 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 559 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 560 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 561 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
562 | if (chip->chipsize > (32 << 20)) |
563 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 564 | } |
ace4dfee | 565 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
566 | |
567 | /* | |
8b6e50c9 BN |
568 | * Program and erase have their own busy handlers status and sequential |
569 | * in needs no delay | |
e0c7d767 | 570 | */ |
1da177e4 | 571 | switch (command) { |
61b03bd7 | 572 | |
1da177e4 LT |
573 | case NAND_CMD_PAGEPROG: |
574 | case NAND_CMD_ERASE1: | |
575 | case NAND_CMD_ERASE2: | |
576 | case NAND_CMD_SEQIN: | |
577 | case NAND_CMD_STATUS: | |
578 | return; | |
579 | ||
580 | case NAND_CMD_RESET: | |
ace4dfee | 581 | if (chip->dev_ready) |
1da177e4 | 582 | break; |
ace4dfee TG |
583 | udelay(chip->chip_delay); |
584 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 585 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
586 | chip->cmd_ctrl(mtd, |
587 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
588 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
589 | ; | |
1da177e4 LT |
590 | return; |
591 | ||
e0c7d767 | 592 | /* This applies to read commands */ |
1da177e4 | 593 | default: |
61b03bd7 | 594 | /* |
1da177e4 LT |
595 | * If we don't have access to the busy pin, we apply the given |
596 | * command delay | |
e0c7d767 | 597 | */ |
ace4dfee TG |
598 | if (!chip->dev_ready) { |
599 | udelay(chip->chip_delay); | |
1da177e4 | 600 | return; |
61b03bd7 | 601 | } |
1da177e4 | 602 | } |
8b6e50c9 BN |
603 | /* |
604 | * Apply this short delay always to ensure that we do wait tWB in | |
605 | * any case on any machine. | |
606 | */ | |
e0c7d767 | 607 | ndelay(100); |
3b88775c TG |
608 | |
609 | nand_wait_ready(mtd); | |
1da177e4 LT |
610 | } |
611 | ||
612 | /** | |
613 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
8b6e50c9 BN |
614 | * @mtd: MTD device structure |
615 | * @command: the command to be sent | |
616 | * @column: the column address for this command, -1 if none | |
617 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 618 | * |
7abd3ef9 | 619 | * Send command to NAND device. This is the version for the new large page |
7854d3f7 BN |
620 | * devices. We don't have the separate regions as we have in the small page |
621 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 622 | */ |
7abd3ef9 TG |
623 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
624 | int column, int page_addr) | |
1da177e4 | 625 | { |
ace4dfee | 626 | register struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
627 | |
628 | /* Emulate NAND_CMD_READOOB */ | |
629 | if (command == NAND_CMD_READOOB) { | |
28318776 | 630 | column += mtd->writesize; |
1da177e4 LT |
631 | command = NAND_CMD_READ0; |
632 | } | |
61b03bd7 | 633 | |
7abd3ef9 | 634 | /* Command latch cycle */ |
ace4dfee | 635 | chip->cmd_ctrl(mtd, command & 0xff, |
7abd3ef9 | 636 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
637 | |
638 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 639 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
640 | |
641 | /* Serially input address */ | |
642 | if (column != -1) { | |
643 | /* Adjust columns for 16 bit buswidth */ | |
ace4dfee | 644 | if (chip->options & NAND_BUSWIDTH_16) |
1da177e4 | 645 | column >>= 1; |
ace4dfee | 646 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 647 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 648 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 649 | } |
1da177e4 | 650 | if (page_addr != -1) { |
ace4dfee TG |
651 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
652 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 653 | NAND_NCE | NAND_ALE); |
1da177e4 | 654 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
655 | if (chip->chipsize > (128 << 20)) |
656 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 657 | NAND_NCE | NAND_ALE); |
1da177e4 | 658 | } |
1da177e4 | 659 | } |
ace4dfee | 660 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
661 | |
662 | /* | |
8b6e50c9 BN |
663 | * Program and erase have their own busy handlers status, sequential |
664 | * in, and deplete1 need no delay. | |
30f464b7 | 665 | */ |
1da177e4 | 666 | switch (command) { |
61b03bd7 | 667 | |
1da177e4 LT |
668 | case NAND_CMD_CACHEDPROG: |
669 | case NAND_CMD_PAGEPROG: | |
670 | case NAND_CMD_ERASE1: | |
671 | case NAND_CMD_ERASE2: | |
672 | case NAND_CMD_SEQIN: | |
7bc3312b | 673 | case NAND_CMD_RNDIN: |
1da177e4 | 674 | case NAND_CMD_STATUS: |
30f464b7 | 675 | case NAND_CMD_DEPLETE1: |
1da177e4 LT |
676 | return; |
677 | ||
30f464b7 DM |
678 | case NAND_CMD_STATUS_ERROR: |
679 | case NAND_CMD_STATUS_ERROR0: | |
680 | case NAND_CMD_STATUS_ERROR1: | |
681 | case NAND_CMD_STATUS_ERROR2: | |
682 | case NAND_CMD_STATUS_ERROR3: | |
8b6e50c9 | 683 | /* Read error status commands require only a short delay */ |
ace4dfee | 684 | udelay(chip->chip_delay); |
30f464b7 | 685 | return; |
1da177e4 LT |
686 | |
687 | case NAND_CMD_RESET: | |
ace4dfee | 688 | if (chip->dev_ready) |
1da177e4 | 689 | break; |
ace4dfee | 690 | udelay(chip->chip_delay); |
12efdde3 TG |
691 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
692 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
693 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
694 | NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
695 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
696 | ; | |
1da177e4 LT |
697 | return; |
698 | ||
7bc3312b TG |
699 | case NAND_CMD_RNDOUT: |
700 | /* No ready / busy check necessary */ | |
701 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
702 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
703 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
704 | NAND_NCE | NAND_CTRL_CHANGE); | |
705 | return; | |
706 | ||
1da177e4 | 707 | case NAND_CMD_READ0: |
12efdde3 TG |
708 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
709 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
710 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
711 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 712 | |
e0c7d767 | 713 | /* This applies to read commands */ |
1da177e4 | 714 | default: |
61b03bd7 | 715 | /* |
1da177e4 | 716 | * If we don't have access to the busy pin, we apply the given |
8b6e50c9 | 717 | * command delay. |
e0c7d767 | 718 | */ |
ace4dfee TG |
719 | if (!chip->dev_ready) { |
720 | udelay(chip->chip_delay); | |
1da177e4 | 721 | return; |
61b03bd7 | 722 | } |
1da177e4 | 723 | } |
3b88775c | 724 | |
8b6e50c9 BN |
725 | /* |
726 | * Apply this short delay always to ensure that we do wait tWB in | |
727 | * any case on any machine. | |
728 | */ | |
e0c7d767 | 729 | ndelay(100); |
3b88775c TG |
730 | |
731 | nand_wait_ready(mtd); | |
1da177e4 LT |
732 | } |
733 | ||
2af7c653 SK |
734 | /** |
735 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
736 | * @chip: the nand chip descriptor |
737 | * @mtd: MTD device structure | |
738 | * @new_state: the state which is requested | |
2af7c653 SK |
739 | * |
740 | * Used when in panic, no locks are taken. | |
741 | */ | |
742 | static void panic_nand_get_device(struct nand_chip *chip, | |
743 | struct mtd_info *mtd, int new_state) | |
744 | { | |
7854d3f7 | 745 | /* Hardware controller shared among independent devices */ |
2af7c653 SK |
746 | chip->controller->active = chip; |
747 | chip->state = new_state; | |
748 | } | |
749 | ||
1da177e4 LT |
750 | /** |
751 | * nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
752 | * @chip: the nand chip descriptor |
753 | * @mtd: MTD device structure | |
754 | * @new_state: the state which is requested | |
1da177e4 LT |
755 | * |
756 | * Get the device and lock it for exclusive access | |
757 | */ | |
2c0a2bed | 758 | static int |
ace4dfee | 759 | nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state) |
1da177e4 | 760 | { |
ace4dfee TG |
761 | spinlock_t *lock = &chip->controller->lock; |
762 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 763 | DECLARE_WAITQUEUE(wait, current); |
7351d3a5 | 764 | retry: |
0dfc6246 TG |
765 | spin_lock(lock); |
766 | ||
b8b3ee9a | 767 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
768 | if (!chip->controller->active) |
769 | chip->controller->active = chip; | |
a36ed299 | 770 | |
ace4dfee TG |
771 | if (chip->controller->active == chip && chip->state == FL_READY) { |
772 | chip->state = new_state; | |
0dfc6246 | 773 | spin_unlock(lock); |
962034f4 VW |
774 | return 0; |
775 | } | |
776 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
777 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
778 | chip->state = FL_PM_SUSPENDED; | |
779 | spin_unlock(lock); | |
780 | return 0; | |
6b0d9a84 | 781 | } |
0dfc6246 TG |
782 | } |
783 | set_current_state(TASK_UNINTERRUPTIBLE); | |
784 | add_wait_queue(wq, &wait); | |
785 | spin_unlock(lock); | |
786 | schedule(); | |
787 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
788 | goto retry; |
789 | } | |
790 | ||
2af7c653 | 791 | /** |
8b6e50c9 BN |
792 | * panic_nand_wait - [GENERIC] wait until the command is done |
793 | * @mtd: MTD device structure | |
794 | * @chip: NAND chip structure | |
795 | * @timeo: timeout | |
2af7c653 SK |
796 | * |
797 | * Wait for command done. This is a helper function for nand_wait used when | |
798 | * we are in interrupt context. May happen when in panic and trying to write | |
b595076a | 799 | * an oops through mtdoops. |
2af7c653 SK |
800 | */ |
801 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
802 | unsigned long timeo) | |
803 | { | |
804 | int i; | |
805 | for (i = 0; i < timeo; i++) { | |
806 | if (chip->dev_ready) { | |
807 | if (chip->dev_ready(mtd)) | |
808 | break; | |
809 | } else { | |
810 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
811 | break; | |
812 | } | |
813 | mdelay(1); | |
f8ac0414 | 814 | } |
2af7c653 SK |
815 | } |
816 | ||
1da177e4 | 817 | /** |
8b6e50c9 BN |
818 | * nand_wait - [DEFAULT] wait until the command is done |
819 | * @mtd: MTD device structure | |
820 | * @chip: NAND chip structure | |
1da177e4 | 821 | * |
8b6e50c9 BN |
822 | * Wait for command done. This applies to erase and program only. Erase can |
823 | * take up to 400ms and program up to 20ms according to general NAND and | |
824 | * SmartMedia specs. | |
844d3b42 | 825 | */ |
7bc3312b | 826 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
827 | { |
828 | ||
e0c7d767 | 829 | unsigned long timeo = jiffies; |
7bc3312b | 830 | int status, state = chip->state; |
61b03bd7 | 831 | |
1da177e4 | 832 | if (state == FL_ERASING) |
e0c7d767 | 833 | timeo += (HZ * 400) / 1000; |
1da177e4 | 834 | else |
e0c7d767 | 835 | timeo += (HZ * 20) / 1000; |
1da177e4 | 836 | |
8fe833c1 RP |
837 | led_trigger_event(nand_led_trigger, LED_FULL); |
838 | ||
8b6e50c9 BN |
839 | /* |
840 | * Apply this short delay always to ensure that we do wait tWB in any | |
841 | * case on any machine. | |
842 | */ | |
e0c7d767 | 843 | ndelay(100); |
1da177e4 | 844 | |
ace4dfee TG |
845 | if ((state == FL_ERASING) && (chip->options & NAND_IS_AND)) |
846 | chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); | |
61b03bd7 | 847 | else |
ace4dfee | 848 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 849 | |
2af7c653 SK |
850 | if (in_interrupt() || oops_in_progress) |
851 | panic_nand_wait(mtd, chip, timeo); | |
852 | else { | |
853 | while (time_before(jiffies, timeo)) { | |
854 | if (chip->dev_ready) { | |
855 | if (chip->dev_ready(mtd)) | |
856 | break; | |
857 | } else { | |
858 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
859 | break; | |
860 | } | |
861 | cond_resched(); | |
1da177e4 | 862 | } |
1da177e4 | 863 | } |
8fe833c1 RP |
864 | led_trigger_event(nand_led_trigger, LED_OFF); |
865 | ||
ace4dfee | 866 | status = (int)chip->read_byte(mtd); |
f251b8df MC |
867 | /* This can happen if in case of timeout or buggy dev_ready */ |
868 | WARN_ON(!(status & NAND_STATUS_READY)); | |
1da177e4 LT |
869 | return status; |
870 | } | |
871 | ||
7d70f334 | 872 | /** |
b6d676db | 873 | * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
874 | * @mtd: mtd info |
875 | * @ofs: offset to start unlock from | |
876 | * @len: length to unlock | |
8b6e50c9 BN |
877 | * @invert: when = 0, unlock the range of blocks within the lower and |
878 | * upper boundary address | |
879 | * when = 1, unlock the range of blocks outside the boundaries | |
880 | * of the lower and upper boundary address | |
7d70f334 | 881 | * |
8b6e50c9 | 882 | * Returs unlock status. |
7d70f334 VS |
883 | */ |
884 | static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, | |
885 | uint64_t len, int invert) | |
886 | { | |
887 | int ret = 0; | |
888 | int status, page; | |
889 | struct nand_chip *chip = mtd->priv; | |
890 | ||
891 | /* Submit address of first page to unlock */ | |
892 | page = ofs >> chip->page_shift; | |
893 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); | |
894 | ||
895 | /* Submit address of last page to unlock */ | |
896 | page = (ofs + len) >> chip->page_shift; | |
897 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, | |
898 | (page | invert) & chip->pagemask); | |
899 | ||
900 | /* Call wait ready function */ | |
901 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 902 | /* See if device thinks it succeeded */ |
74830966 | 903 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 904 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
905 | __func__, status); |
906 | ret = -EIO; | |
907 | } | |
908 | ||
909 | return ret; | |
910 | } | |
911 | ||
912 | /** | |
b6d676db | 913 | * nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
914 | * @mtd: mtd info |
915 | * @ofs: offset to start unlock from | |
916 | * @len: length to unlock | |
7d70f334 | 917 | * |
8b6e50c9 | 918 | * Returns unlock status. |
7d70f334 VS |
919 | */ |
920 | int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
921 | { | |
922 | int ret = 0; | |
923 | int chipnr; | |
924 | struct nand_chip *chip = mtd->priv; | |
925 | ||
289c0522 | 926 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
927 | __func__, (unsigned long long)ofs, len); |
928 | ||
929 | if (check_offs_len(mtd, ofs, len)) | |
930 | ret = -EINVAL; | |
931 | ||
932 | /* Align to last block address if size addresses end of the device */ | |
933 | if (ofs + len == mtd->size) | |
934 | len -= mtd->erasesize; | |
935 | ||
936 | nand_get_device(chip, mtd, FL_UNLOCKING); | |
937 | ||
938 | /* Shift to get chip number */ | |
939 | chipnr = ofs >> chip->chip_shift; | |
940 | ||
941 | chip->select_chip(mtd, chipnr); | |
942 | ||
943 | /* Check, if it is write protected */ | |
944 | if (nand_check_wp(mtd)) { | |
289c0522 | 945 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
946 | __func__); |
947 | ret = -EIO; | |
948 | goto out; | |
949 | } | |
950 | ||
951 | ret = __nand_unlock(mtd, ofs, len, 0); | |
952 | ||
953 | out: | |
b0bb6903 | 954 | chip->select_chip(mtd, -1); |
7d70f334 VS |
955 | nand_release_device(mtd); |
956 | ||
957 | return ret; | |
958 | } | |
7351d3a5 | 959 | EXPORT_SYMBOL(nand_unlock); |
7d70f334 VS |
960 | |
961 | /** | |
b6d676db | 962 | * nand_lock - [REPLACEABLE] locks all blocks present in the device |
b6d676db RD |
963 | * @mtd: mtd info |
964 | * @ofs: offset to start unlock from | |
965 | * @len: length to unlock | |
7d70f334 | 966 | * |
8b6e50c9 BN |
967 | * This feature is not supported in many NAND parts. 'Micron' NAND parts do |
968 | * have this feature, but it allows only to lock all blocks, not for specified | |
969 | * range for block. Implementing 'lock' feature by making use of 'unlock', for | |
970 | * now. | |
7d70f334 | 971 | * |
8b6e50c9 | 972 | * Returns lock status. |
7d70f334 VS |
973 | */ |
974 | int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
975 | { | |
976 | int ret = 0; | |
977 | int chipnr, status, page; | |
978 | struct nand_chip *chip = mtd->priv; | |
979 | ||
289c0522 | 980 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
981 | __func__, (unsigned long long)ofs, len); |
982 | ||
983 | if (check_offs_len(mtd, ofs, len)) | |
984 | ret = -EINVAL; | |
985 | ||
986 | nand_get_device(chip, mtd, FL_LOCKING); | |
987 | ||
988 | /* Shift to get chip number */ | |
989 | chipnr = ofs >> chip->chip_shift; | |
990 | ||
991 | chip->select_chip(mtd, chipnr); | |
992 | ||
993 | /* Check, if it is write protected */ | |
994 | if (nand_check_wp(mtd)) { | |
289c0522 | 995 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
996 | __func__); |
997 | status = MTD_ERASE_FAILED; | |
998 | ret = -EIO; | |
999 | goto out; | |
1000 | } | |
1001 | ||
1002 | /* Submit address of first page to lock */ | |
1003 | page = ofs >> chip->page_shift; | |
1004 | chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); | |
1005 | ||
1006 | /* Call wait ready function */ | |
1007 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 1008 | /* See if device thinks it succeeded */ |
74830966 | 1009 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 1010 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
1011 | __func__, status); |
1012 | ret = -EIO; | |
1013 | goto out; | |
1014 | } | |
1015 | ||
1016 | ret = __nand_unlock(mtd, ofs, len, 0x1); | |
1017 | ||
1018 | out: | |
b0bb6903 | 1019 | chip->select_chip(mtd, -1); |
7d70f334 VS |
1020 | nand_release_device(mtd); |
1021 | ||
1022 | return ret; | |
1023 | } | |
7351d3a5 | 1024 | EXPORT_SYMBOL(nand_lock); |
7d70f334 | 1025 | |
8593fbc6 | 1026 | /** |
7854d3f7 | 1027 | * nand_read_page_raw - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1028 | * @mtd: mtd info structure |
1029 | * @chip: nand chip info structure | |
1030 | * @buf: buffer to store read data | |
1fbb938d | 1031 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1032 | * @page: page number to read |
52ff49df | 1033 | * |
7854d3f7 | 1034 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 TG |
1035 | */ |
1036 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1037 | uint8_t *buf, int oob_required, int page) |
8593fbc6 TG |
1038 | { |
1039 | chip->read_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
1040 | if (oob_required) |
1041 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
8593fbc6 TG |
1042 | return 0; |
1043 | } | |
1044 | ||
52ff49df | 1045 | /** |
7854d3f7 | 1046 | * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1047 | * @mtd: mtd info structure |
1048 | * @chip: nand chip info structure | |
1049 | * @buf: buffer to store read data | |
1fbb938d | 1050 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1051 | * @page: page number to read |
52ff49df DB |
1052 | * |
1053 | * We need a special oob layout and handling even when OOB isn't used. | |
1054 | */ | |
7351d3a5 | 1055 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
1056 | struct nand_chip *chip, uint8_t *buf, |
1057 | int oob_required, int page) | |
52ff49df DB |
1058 | { |
1059 | int eccsize = chip->ecc.size; | |
1060 | int eccbytes = chip->ecc.bytes; | |
1061 | uint8_t *oob = chip->oob_poi; | |
1062 | int steps, size; | |
1063 | ||
1064 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1065 | chip->read_buf(mtd, buf, eccsize); | |
1066 | buf += eccsize; | |
1067 | ||
1068 | if (chip->ecc.prepad) { | |
1069 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1070 | oob += chip->ecc.prepad; | |
1071 | } | |
1072 | ||
1073 | chip->read_buf(mtd, oob, eccbytes); | |
1074 | oob += eccbytes; | |
1075 | ||
1076 | if (chip->ecc.postpad) { | |
1077 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1078 | oob += chip->ecc.postpad; | |
1079 | } | |
1080 | } | |
1081 | ||
1082 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1083 | if (size) | |
1084 | chip->read_buf(mtd, oob, size); | |
1085 | ||
1086 | return 0; | |
1087 | } | |
1088 | ||
1da177e4 | 1089 | /** |
7854d3f7 | 1090 | * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function |
8b6e50c9 BN |
1091 | * @mtd: mtd info structure |
1092 | * @chip: nand chip info structure | |
1093 | * @buf: buffer to store read data | |
1fbb938d | 1094 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1095 | * @page: page number to read |
068e3c0a | 1096 | */ |
f5bbdacc | 1097 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1098 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1099 | { |
f5bbdacc TG |
1100 | int i, eccsize = chip->ecc.size; |
1101 | int eccbytes = chip->ecc.bytes; | |
1102 | int eccsteps = chip->ecc.steps; | |
1103 | uint8_t *p = buf; | |
4bf63fcb DW |
1104 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1105 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1106 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1107 | unsigned int max_bitflips = 0; |
f5bbdacc | 1108 | |
1fbb938d | 1109 | chip->ecc.read_page_raw(mtd, chip, buf, 1, page); |
f5bbdacc TG |
1110 | |
1111 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1112 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1113 | ||
1114 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 1115 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
1116 | |
1117 | eccsteps = chip->ecc.steps; | |
1118 | p = buf; | |
1119 | ||
1120 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1121 | int stat; | |
1122 | ||
1123 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
3f91e94f | 1124 | if (stat < 0) { |
f5bbdacc | 1125 | mtd->ecc_stats.failed++; |
3f91e94f | 1126 | } else { |
f5bbdacc | 1127 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1128 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1129 | } | |
f5bbdacc | 1130 | } |
3f91e94f | 1131 | return max_bitflips; |
22c60f5f | 1132 | } |
1da177e4 | 1133 | |
3d459559 | 1134 | /** |
7854d3f7 | 1135 | * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function |
8b6e50c9 BN |
1136 | * @mtd: mtd info structure |
1137 | * @chip: nand chip info structure | |
1138 | * @data_offs: offset of requested data within the page | |
1139 | * @readlen: data length | |
1140 | * @bufpoi: buffer to store read data | |
3d459559 | 1141 | */ |
7351d3a5 FF |
1142 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, |
1143 | uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi) | |
3d459559 AK |
1144 | { |
1145 | int start_step, end_step, num_steps; | |
1146 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1147 | uint8_t *p; | |
1148 | int data_col_addr, i, gaps = 0; | |
1149 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
1150 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
7351d3a5 | 1151 | int index = 0; |
3f91e94f | 1152 | unsigned int max_bitflips = 0; |
3d459559 | 1153 | |
7854d3f7 | 1154 | /* Column address within the page aligned to ECC size (256bytes) */ |
3d459559 AK |
1155 | start_step = data_offs / chip->ecc.size; |
1156 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
1157 | num_steps = end_step - start_step + 1; | |
1158 | ||
8b6e50c9 | 1159 | /* Data size aligned to ECC ecc.size */ |
3d459559 AK |
1160 | datafrag_len = num_steps * chip->ecc.size; |
1161 | eccfrag_len = num_steps * chip->ecc.bytes; | |
1162 | ||
1163 | data_col_addr = start_step * chip->ecc.size; | |
1164 | /* If we read not a page aligned data */ | |
1165 | if (data_col_addr != 0) | |
1166 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); | |
1167 | ||
1168 | p = bufpoi + data_col_addr; | |
1169 | chip->read_buf(mtd, p, datafrag_len); | |
1170 | ||
8b6e50c9 | 1171 | /* Calculate ECC */ |
3d459559 AK |
1172 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) |
1173 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); | |
1174 | ||
8b6e50c9 BN |
1175 | /* |
1176 | * The performance is faster if we position offsets according to | |
7854d3f7 | 1177 | * ecc.pos. Let's make sure that there are no gaps in ECC positions. |
8b6e50c9 | 1178 | */ |
3d459559 AK |
1179 | for (i = 0; i < eccfrag_len - 1; i++) { |
1180 | if (eccpos[i + start_step * chip->ecc.bytes] + 1 != | |
1181 | eccpos[i + start_step * chip->ecc.bytes + 1]) { | |
1182 | gaps = 1; | |
1183 | break; | |
1184 | } | |
1185 | } | |
1186 | if (gaps) { | |
1187 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1188 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1189 | } else { | |
8b6e50c9 | 1190 | /* |
7854d3f7 | 1191 | * Send the command to read the particular ECC bytes take care |
8b6e50c9 BN |
1192 | * about buswidth alignment in read_buf. |
1193 | */ | |
7351d3a5 FF |
1194 | index = start_step * chip->ecc.bytes; |
1195 | ||
1196 | aligned_pos = eccpos[index] & ~(busw - 1); | |
3d459559 | 1197 | aligned_len = eccfrag_len; |
7351d3a5 | 1198 | if (eccpos[index] & (busw - 1)) |
3d459559 | 1199 | aligned_len++; |
7351d3a5 | 1200 | if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1)) |
3d459559 AK |
1201 | aligned_len++; |
1202 | ||
7351d3a5 FF |
1203 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, |
1204 | mtd->writesize + aligned_pos, -1); | |
3d459559 AK |
1205 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); |
1206 | } | |
1207 | ||
1208 | for (i = 0; i < eccfrag_len; i++) | |
7351d3a5 | 1209 | chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]]; |
3d459559 AK |
1210 | |
1211 | p = bufpoi + data_col_addr; | |
1212 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
1213 | int stat; | |
1214 | ||
7351d3a5 FF |
1215 | stat = chip->ecc.correct(mtd, p, |
1216 | &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); | |
3f91e94f | 1217 | if (stat < 0) { |
3d459559 | 1218 | mtd->ecc_stats.failed++; |
3f91e94f | 1219 | } else { |
3d459559 | 1220 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1221 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1222 | } | |
3d459559 | 1223 | } |
3f91e94f | 1224 | return max_bitflips; |
3d459559 AK |
1225 | } |
1226 | ||
068e3c0a | 1227 | /** |
7854d3f7 | 1228 | * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function |
8b6e50c9 BN |
1229 | * @mtd: mtd info structure |
1230 | * @chip: nand chip info structure | |
1231 | * @buf: buffer to store read data | |
1fbb938d | 1232 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1233 | * @page: page number to read |
068e3c0a | 1234 | * |
7854d3f7 | 1235 | * Not for syndrome calculating ECC controllers which need a special oob layout. |
068e3c0a | 1236 | */ |
f5bbdacc | 1237 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1238 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1239 | { |
f5bbdacc TG |
1240 | int i, eccsize = chip->ecc.size; |
1241 | int eccbytes = chip->ecc.bytes; | |
1242 | int eccsteps = chip->ecc.steps; | |
1243 | uint8_t *p = buf; | |
4bf63fcb DW |
1244 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1245 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1246 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1247 | unsigned int max_bitflips = 0; |
f5bbdacc TG |
1248 | |
1249 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1250 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1251 | chip->read_buf(mtd, p, eccsize); | |
1252 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 1253 | } |
f75e5097 | 1254 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 1255 | |
f5bbdacc | 1256 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 1257 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 1258 | |
f5bbdacc TG |
1259 | eccsteps = chip->ecc.steps; |
1260 | p = buf; | |
61b03bd7 | 1261 | |
f5bbdacc TG |
1262 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1263 | int stat; | |
1da177e4 | 1264 | |
f5bbdacc | 1265 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
3f91e94f | 1266 | if (stat < 0) { |
f5bbdacc | 1267 | mtd->ecc_stats.failed++; |
3f91e94f | 1268 | } else { |
f5bbdacc | 1269 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1270 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1271 | } | |
f5bbdacc | 1272 | } |
3f91e94f | 1273 | return max_bitflips; |
f5bbdacc | 1274 | } |
1da177e4 | 1275 | |
6e0cb135 | 1276 | /** |
7854d3f7 | 1277 | * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first |
8b6e50c9 BN |
1278 | * @mtd: mtd info structure |
1279 | * @chip: nand chip info structure | |
1280 | * @buf: buffer to store read data | |
1fbb938d | 1281 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1282 | * @page: page number to read |
6e0cb135 | 1283 | * |
8b6e50c9 BN |
1284 | * Hardware ECC for large page chips, require OOB to be read first. For this |
1285 | * ECC mode, the write_page method is re-used from ECC_HW. These methods | |
1286 | * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with | |
1287 | * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from | |
1288 | * the data area, by overwriting the NAND manufacturer bad block markings. | |
6e0cb135 SN |
1289 | */ |
1290 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1fbb938d | 1291 | struct nand_chip *chip, uint8_t *buf, int oob_required, int page) |
6e0cb135 SN |
1292 | { |
1293 | int i, eccsize = chip->ecc.size; | |
1294 | int eccbytes = chip->ecc.bytes; | |
1295 | int eccsteps = chip->ecc.steps; | |
1296 | uint8_t *p = buf; | |
1297 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1298 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1299 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
3f91e94f | 1300 | unsigned int max_bitflips = 0; |
6e0cb135 SN |
1301 | |
1302 | /* Read the OOB area first */ | |
1303 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1304 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1305 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1306 | ||
1307 | for (i = 0; i < chip->ecc.total; i++) | |
1308 | ecc_code[i] = chip->oob_poi[eccpos[i]]; | |
1309 | ||
1310 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1311 | int stat; | |
1312 | ||
1313 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1314 | chip->read_buf(mtd, p, eccsize); | |
1315 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1316 | ||
1317 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
3f91e94f | 1318 | if (stat < 0) { |
6e0cb135 | 1319 | mtd->ecc_stats.failed++; |
3f91e94f | 1320 | } else { |
6e0cb135 | 1321 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1322 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1323 | } | |
6e0cb135 | 1324 | } |
3f91e94f | 1325 | return max_bitflips; |
6e0cb135 SN |
1326 | } |
1327 | ||
f5bbdacc | 1328 | /** |
7854d3f7 | 1329 | * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read |
8b6e50c9 BN |
1330 | * @mtd: mtd info structure |
1331 | * @chip: nand chip info structure | |
1332 | * @buf: buffer to store read data | |
1fbb938d | 1333 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1334 | * @page: page number to read |
f5bbdacc | 1335 | * |
8b6e50c9 BN |
1336 | * The hw generator calculates the error syndrome automatically. Therefore we |
1337 | * need a special oob layout and handling. | |
f5bbdacc TG |
1338 | */ |
1339 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1340 | uint8_t *buf, int oob_required, int page) |
f5bbdacc TG |
1341 | { |
1342 | int i, eccsize = chip->ecc.size; | |
1343 | int eccbytes = chip->ecc.bytes; | |
1344 | int eccsteps = chip->ecc.steps; | |
1345 | uint8_t *p = buf; | |
f75e5097 | 1346 | uint8_t *oob = chip->oob_poi; |
3f91e94f | 1347 | unsigned int max_bitflips = 0; |
1da177e4 | 1348 | |
f5bbdacc TG |
1349 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1350 | int stat; | |
61b03bd7 | 1351 | |
f5bbdacc TG |
1352 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
1353 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 1354 | |
f5bbdacc TG |
1355 | if (chip->ecc.prepad) { |
1356 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1357 | oob += chip->ecc.prepad; | |
1358 | } | |
1da177e4 | 1359 | |
f5bbdacc TG |
1360 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1361 | chip->read_buf(mtd, oob, eccbytes); | |
1362 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 1363 | |
3f91e94f | 1364 | if (stat < 0) { |
f5bbdacc | 1365 | mtd->ecc_stats.failed++; |
3f91e94f | 1366 | } else { |
f5bbdacc | 1367 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1368 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1369 | } | |
61b03bd7 | 1370 | |
f5bbdacc | 1371 | oob += eccbytes; |
1da177e4 | 1372 | |
f5bbdacc TG |
1373 | if (chip->ecc.postpad) { |
1374 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1375 | oob += chip->ecc.postpad; | |
61b03bd7 | 1376 | } |
f5bbdacc | 1377 | } |
1da177e4 | 1378 | |
f5bbdacc | 1379 | /* Calculate remaining oob bytes */ |
7e4178f9 | 1380 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
1381 | if (i) |
1382 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 1383 | |
3f91e94f | 1384 | return max_bitflips; |
f5bbdacc | 1385 | } |
1da177e4 | 1386 | |
f5bbdacc | 1387 | /** |
7854d3f7 | 1388 | * nand_transfer_oob - [INTERN] Transfer oob to client buffer |
8b6e50c9 BN |
1389 | * @chip: nand chip structure |
1390 | * @oob: oob destination address | |
1391 | * @ops: oob ops structure | |
1392 | * @len: size of oob to transfer | |
8593fbc6 TG |
1393 | */ |
1394 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, | |
7014568b | 1395 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 1396 | { |
f8ac0414 | 1397 | switch (ops->mode) { |
8593fbc6 | 1398 | |
0612b9dd BN |
1399 | case MTD_OPS_PLACE_OOB: |
1400 | case MTD_OPS_RAW: | |
8593fbc6 TG |
1401 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); |
1402 | return oob + len; | |
1403 | ||
0612b9dd | 1404 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 1405 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
1406 | uint32_t boffs = 0, roffs = ops->ooboffs; |
1407 | size_t bytes = 0; | |
8593fbc6 | 1408 | |
f8ac0414 | 1409 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 1410 | /* Read request not from offset 0? */ |
7bc3312b TG |
1411 | if (unlikely(roffs)) { |
1412 | if (roffs >= free->length) { | |
1413 | roffs -= free->length; | |
1414 | continue; | |
1415 | } | |
1416 | boffs = free->offset + roffs; | |
1417 | bytes = min_t(size_t, len, | |
1418 | (free->length - roffs)); | |
1419 | roffs = 0; | |
1420 | } else { | |
1421 | bytes = min_t(size_t, len, free->length); | |
1422 | boffs = free->offset; | |
1423 | } | |
1424 | memcpy(oob, chip->oob_poi + boffs, bytes); | |
8593fbc6 TG |
1425 | oob += bytes; |
1426 | } | |
1427 | return oob; | |
1428 | } | |
1429 | default: | |
1430 | BUG(); | |
1431 | } | |
1432 | return NULL; | |
1433 | } | |
1434 | ||
1435 | /** | |
7854d3f7 | 1436 | * nand_do_read_ops - [INTERN] Read data with ECC |
8b6e50c9 BN |
1437 | * @mtd: MTD device structure |
1438 | * @from: offset to read from | |
1439 | * @ops: oob ops structure | |
f5bbdacc TG |
1440 | * |
1441 | * Internal function. Called with chip held. | |
1442 | */ | |
8593fbc6 TG |
1443 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
1444 | struct mtd_oob_ops *ops) | |
f5bbdacc | 1445 | { |
e47f3db4 | 1446 | int chipnr, page, realpage, col, bytes, aligned, oob_required; |
f5bbdacc TG |
1447 | struct nand_chip *chip = mtd->priv; |
1448 | struct mtd_ecc_stats stats; | |
f5bbdacc | 1449 | int ret = 0; |
8593fbc6 | 1450 | uint32_t readlen = ops->len; |
7014568b | 1451 | uint32_t oobreadlen = ops->ooblen; |
0612b9dd | 1452 | uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ? |
9aca334e ML |
1453 | mtd->oobavail : mtd->oobsize; |
1454 | ||
8593fbc6 | 1455 | uint8_t *bufpoi, *oob, *buf; |
edbc4540 | 1456 | unsigned int max_bitflips = 0; |
1da177e4 | 1457 | |
f5bbdacc | 1458 | stats = mtd->ecc_stats; |
1da177e4 | 1459 | |
f5bbdacc TG |
1460 | chipnr = (int)(from >> chip->chip_shift); |
1461 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 1462 | |
f5bbdacc TG |
1463 | realpage = (int)(from >> chip->page_shift); |
1464 | page = realpage & chip->pagemask; | |
1da177e4 | 1465 | |
f5bbdacc | 1466 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 1467 | |
8593fbc6 TG |
1468 | buf = ops->datbuf; |
1469 | oob = ops->oobbuf; | |
e47f3db4 | 1470 | oob_required = oob ? 1 : 0; |
8593fbc6 | 1471 | |
f8ac0414 | 1472 | while (1) { |
f5bbdacc TG |
1473 | bytes = min(mtd->writesize - col, readlen); |
1474 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 1475 | |
8b6e50c9 | 1476 | /* Is the current page in the buffer? */ |
8593fbc6 | 1477 | if (realpage != chip->pagebuf || oob) { |
4bf63fcb | 1478 | bufpoi = aligned ? buf : chip->buffers->databuf; |
61b03bd7 | 1479 | |
c00a0991 | 1480 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); |
1da177e4 | 1481 | |
edbc4540 MD |
1482 | /* |
1483 | * Now read the page into the buffer. Absent an error, | |
1484 | * the read methods return max bitflips per ecc step. | |
1485 | */ | |
0612b9dd | 1486 | if (unlikely(ops->mode == MTD_OPS_RAW)) |
1fbb938d | 1487 | ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, |
e47f3db4 BN |
1488 | oob_required, |
1489 | page); | |
a5ff4f10 JW |
1490 | else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && |
1491 | !oob) | |
7351d3a5 FF |
1492 | ret = chip->ecc.read_subpage(mtd, chip, |
1493 | col, bytes, bufpoi); | |
956e944c | 1494 | else |
46a8cf2d | 1495 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
e47f3db4 | 1496 | oob_required, page); |
6d77b9d0 BN |
1497 | if (ret < 0) { |
1498 | if (!aligned) | |
1499 | /* Invalidate page cache */ | |
1500 | chip->pagebuf = -1; | |
1da177e4 | 1501 | break; |
6d77b9d0 | 1502 | } |
f5bbdacc | 1503 | |
edbc4540 MD |
1504 | max_bitflips = max_t(unsigned int, max_bitflips, ret); |
1505 | ||
f5bbdacc TG |
1506 | /* Transfer not aligned data */ |
1507 | if (!aligned) { | |
a5ff4f10 | 1508 | if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && |
6d77b9d0 | 1509 | !(mtd->ecc_stats.failed - stats.failed) && |
edbc4540 | 1510 | (ops->mode != MTD_OPS_RAW)) { |
3d459559 | 1511 | chip->pagebuf = realpage; |
edbc4540 MD |
1512 | chip->pagebuf_bitflips = ret; |
1513 | } else { | |
6d77b9d0 BN |
1514 | /* Invalidate page cache */ |
1515 | chip->pagebuf = -1; | |
edbc4540 | 1516 | } |
4bf63fcb | 1517 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
1518 | } |
1519 | ||
8593fbc6 TG |
1520 | buf += bytes; |
1521 | ||
1522 | if (unlikely(oob)) { | |
b64d39d8 ML |
1523 | int toread = min(oobreadlen, max_oobsize); |
1524 | ||
1525 | if (toread) { | |
1526 | oob = nand_transfer_oob(chip, | |
1527 | oob, ops, toread); | |
1528 | oobreadlen -= toread; | |
1529 | } | |
8593fbc6 | 1530 | } |
8593fbc6 | 1531 | } else { |
4bf63fcb | 1532 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 | 1533 | buf += bytes; |
edbc4540 MD |
1534 | max_bitflips = max_t(unsigned int, max_bitflips, |
1535 | chip->pagebuf_bitflips); | |
8593fbc6 | 1536 | } |
1da177e4 | 1537 | |
f5bbdacc | 1538 | readlen -= bytes; |
61b03bd7 | 1539 | |
f5bbdacc | 1540 | if (!readlen) |
61b03bd7 | 1541 | break; |
1da177e4 | 1542 | |
8b6e50c9 | 1543 | /* For subsequent reads align to page boundary */ |
1da177e4 LT |
1544 | col = 0; |
1545 | /* Increment page address */ | |
1546 | realpage++; | |
1547 | ||
ace4dfee | 1548 | page = realpage & chip->pagemask; |
1da177e4 LT |
1549 | /* Check, if we cross a chip boundary */ |
1550 | if (!page) { | |
1551 | chipnr++; | |
ace4dfee TG |
1552 | chip->select_chip(mtd, -1); |
1553 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1554 | } |
1da177e4 | 1555 | } |
b0bb6903 | 1556 | chip->select_chip(mtd, -1); |
1da177e4 | 1557 | |
8593fbc6 | 1558 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
1559 | if (oob) |
1560 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 1561 | |
3f91e94f | 1562 | if (ret < 0) |
f5bbdacc TG |
1563 | return ret; |
1564 | ||
9a1fcdfd TG |
1565 | if (mtd->ecc_stats.failed - stats.failed) |
1566 | return -EBADMSG; | |
1567 | ||
edbc4540 | 1568 | return max_bitflips; |
f5bbdacc TG |
1569 | } |
1570 | ||
1571 | /** | |
25985edc | 1572 | * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc |
8b6e50c9 BN |
1573 | * @mtd: MTD device structure |
1574 | * @from: offset to read from | |
1575 | * @len: number of bytes to read | |
1576 | * @retlen: pointer to variable to store the number of read bytes | |
1577 | * @buf: the databuffer to put data | |
f5bbdacc | 1578 | * |
8b6e50c9 | 1579 | * Get hold of the chip and call nand_do_read. |
f5bbdacc TG |
1580 | */ |
1581 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1582 | size_t *retlen, uint8_t *buf) | |
1583 | { | |
8593fbc6 | 1584 | struct nand_chip *chip = mtd->priv; |
4a89ff88 | 1585 | struct mtd_oob_ops ops; |
f5bbdacc TG |
1586 | int ret; |
1587 | ||
8593fbc6 | 1588 | nand_get_device(chip, mtd, FL_READING); |
4a89ff88 BN |
1589 | ops.len = len; |
1590 | ops.datbuf = buf; | |
1591 | ops.oobbuf = NULL; | |
11041ae6 | 1592 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 1593 | ret = nand_do_read_ops(mtd, from, &ops); |
4a89ff88 | 1594 | *retlen = ops.retlen; |
f5bbdacc | 1595 | nand_release_device(mtd); |
f5bbdacc | 1596 | return ret; |
1da177e4 LT |
1597 | } |
1598 | ||
7bc3312b | 1599 | /** |
7854d3f7 | 1600 | * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function |
8b6e50c9 BN |
1601 | * @mtd: mtd info structure |
1602 | * @chip: nand chip info structure | |
1603 | * @page: page number to read | |
7bc3312b TG |
1604 | */ |
1605 | static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1606 | int page) |
7bc3312b | 1607 | { |
5c2ffb11 | 1608 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); |
7bc3312b | 1609 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
5c2ffb11 | 1610 | return 0; |
7bc3312b TG |
1611 | } |
1612 | ||
1613 | /** | |
7854d3f7 | 1614 | * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC |
7bc3312b | 1615 | * with syndromes |
8b6e50c9 BN |
1616 | * @mtd: mtd info structure |
1617 | * @chip: nand chip info structure | |
1618 | * @page: page number to read | |
7bc3312b TG |
1619 | */ |
1620 | static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1621 | int page) |
7bc3312b TG |
1622 | { |
1623 | uint8_t *buf = chip->oob_poi; | |
1624 | int length = mtd->oobsize; | |
1625 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1626 | int eccsize = chip->ecc.size; | |
1627 | uint8_t *bufpoi = buf; | |
1628 | int i, toread, sndrnd = 0, pos; | |
1629 | ||
1630 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
1631 | for (i = 0; i < chip->ecc.steps; i++) { | |
1632 | if (sndrnd) { | |
1633 | pos = eccsize + i * (eccsize + chunk); | |
1634 | if (mtd->writesize > 512) | |
1635 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
1636 | else | |
1637 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
1638 | } else | |
1639 | sndrnd = 1; | |
1640 | toread = min_t(int, length, chunk); | |
1641 | chip->read_buf(mtd, bufpoi, toread); | |
1642 | bufpoi += toread; | |
1643 | length -= toread; | |
1644 | } | |
1645 | if (length > 0) | |
1646 | chip->read_buf(mtd, bufpoi, length); | |
1647 | ||
5c2ffb11 | 1648 | return 0; |
7bc3312b TG |
1649 | } |
1650 | ||
1651 | /** | |
7854d3f7 | 1652 | * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function |
8b6e50c9 BN |
1653 | * @mtd: mtd info structure |
1654 | * @chip: nand chip info structure | |
1655 | * @page: page number to write | |
7bc3312b TG |
1656 | */ |
1657 | static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1658 | int page) | |
1659 | { | |
1660 | int status = 0; | |
1661 | const uint8_t *buf = chip->oob_poi; | |
1662 | int length = mtd->oobsize; | |
1663 | ||
1664 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
1665 | chip->write_buf(mtd, buf, length); | |
1666 | /* Send command to program the OOB data */ | |
1667 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1668 | ||
1669 | status = chip->waitfunc(mtd, chip); | |
1670 | ||
0d420f9d | 1671 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b TG |
1672 | } |
1673 | ||
1674 | /** | |
7854d3f7 | 1675 | * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC |
8b6e50c9 BN |
1676 | * with syndrome - only for large page flash |
1677 | * @mtd: mtd info structure | |
1678 | * @chip: nand chip info structure | |
1679 | * @page: page number to write | |
7bc3312b TG |
1680 | */ |
1681 | static int nand_write_oob_syndrome(struct mtd_info *mtd, | |
1682 | struct nand_chip *chip, int page) | |
1683 | { | |
1684 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1685 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
1686 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
1687 | const uint8_t *bufpoi = chip->oob_poi; | |
1688 | ||
1689 | /* | |
1690 | * data-ecc-data-ecc ... ecc-oob | |
1691 | * or | |
1692 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
1693 | */ | |
1694 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
1695 | pos = steps * (eccsize + chunk); | |
1696 | steps = 0; | |
1697 | } else | |
8b0036ee | 1698 | pos = eccsize; |
7bc3312b TG |
1699 | |
1700 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
1701 | for (i = 0; i < steps; i++) { | |
1702 | if (sndcmd) { | |
1703 | if (mtd->writesize <= 512) { | |
1704 | uint32_t fill = 0xFFFFFFFF; | |
1705 | ||
1706 | len = eccsize; | |
1707 | while (len > 0) { | |
1708 | int num = min_t(int, len, 4); | |
1709 | chip->write_buf(mtd, (uint8_t *)&fill, | |
1710 | num); | |
1711 | len -= num; | |
1712 | } | |
1713 | } else { | |
1714 | pos = eccsize + i * (eccsize + chunk); | |
1715 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
1716 | } | |
1717 | } else | |
1718 | sndcmd = 1; | |
1719 | len = min_t(int, length, chunk); | |
1720 | chip->write_buf(mtd, bufpoi, len); | |
1721 | bufpoi += len; | |
1722 | length -= len; | |
1723 | } | |
1724 | if (length > 0) | |
1725 | chip->write_buf(mtd, bufpoi, length); | |
1726 | ||
1727 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1728 | status = chip->waitfunc(mtd, chip); | |
1729 | ||
1730 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
1731 | } | |
1732 | ||
1da177e4 | 1733 | /** |
7854d3f7 | 1734 | * nand_do_read_oob - [INTERN] NAND read out-of-band |
8b6e50c9 BN |
1735 | * @mtd: MTD device structure |
1736 | * @from: offset to read from | |
1737 | * @ops: oob operations description structure | |
1da177e4 | 1738 | * |
8b6e50c9 | 1739 | * NAND read out-of-band data from the spare area. |
1da177e4 | 1740 | */ |
8593fbc6 TG |
1741 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
1742 | struct mtd_oob_ops *ops) | |
1da177e4 | 1743 | { |
c00a0991 | 1744 | int page, realpage, chipnr; |
ace4dfee | 1745 | struct nand_chip *chip = mtd->priv; |
041e4575 | 1746 | struct mtd_ecc_stats stats; |
7014568b VW |
1747 | int readlen = ops->ooblen; |
1748 | int len; | |
7bc3312b | 1749 | uint8_t *buf = ops->oobbuf; |
1951f2f7 | 1750 | int ret = 0; |
61b03bd7 | 1751 | |
289c0522 | 1752 | pr_debug("%s: from = 0x%08Lx, len = %i\n", |
20d8e248 | 1753 | __func__, (unsigned long long)from, readlen); |
1da177e4 | 1754 | |
041e4575 BN |
1755 | stats = mtd->ecc_stats; |
1756 | ||
0612b9dd | 1757 | if (ops->mode == MTD_OPS_AUTO_OOB) |
7014568b | 1758 | len = chip->ecc.layout->oobavail; |
03736155 AH |
1759 | else |
1760 | len = mtd->oobsize; | |
1761 | ||
1762 | if (unlikely(ops->ooboffs >= len)) { | |
289c0522 BN |
1763 | pr_debug("%s: attempt to start read outside oob\n", |
1764 | __func__); | |
03736155 AH |
1765 | return -EINVAL; |
1766 | } | |
1767 | ||
1768 | /* Do not allow reads past end of device */ | |
1769 | if (unlikely(from >= mtd->size || | |
1770 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
1771 | (from >> chip->page_shift)) * len)) { | |
289c0522 BN |
1772 | pr_debug("%s: attempt to read beyond end of device\n", |
1773 | __func__); | |
03736155 AH |
1774 | return -EINVAL; |
1775 | } | |
7014568b | 1776 | |
7314e9e7 | 1777 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 1778 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1779 | |
7314e9e7 TG |
1780 | /* Shift to get page */ |
1781 | realpage = (int)(from >> chip->page_shift); | |
1782 | page = realpage & chip->pagemask; | |
1da177e4 | 1783 | |
f8ac0414 | 1784 | while (1) { |
0612b9dd | 1785 | if (ops->mode == MTD_OPS_RAW) |
1951f2f7 | 1786 | ret = chip->ecc.read_oob_raw(mtd, chip, page); |
c46f6483 | 1787 | else |
1951f2f7 SL |
1788 | ret = chip->ecc.read_oob(mtd, chip, page); |
1789 | ||
1790 | if (ret < 0) | |
1791 | break; | |
7014568b VW |
1792 | |
1793 | len = min(len, readlen); | |
1794 | buf = nand_transfer_oob(chip, buf, ops, len); | |
8593fbc6 | 1795 | |
7014568b | 1796 | readlen -= len; |
0d420f9d SZ |
1797 | if (!readlen) |
1798 | break; | |
1799 | ||
7314e9e7 TG |
1800 | /* Increment page address */ |
1801 | realpage++; | |
1802 | ||
1803 | page = realpage & chip->pagemask; | |
1804 | /* Check, if we cross a chip boundary */ | |
1805 | if (!page) { | |
1806 | chipnr++; | |
1807 | chip->select_chip(mtd, -1); | |
1808 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
1809 | } |
1810 | } | |
b0bb6903 | 1811 | chip->select_chip(mtd, -1); |
1da177e4 | 1812 | |
1951f2f7 SL |
1813 | ops->oobretlen = ops->ooblen - readlen; |
1814 | ||
1815 | if (ret < 0) | |
1816 | return ret; | |
041e4575 BN |
1817 | |
1818 | if (mtd->ecc_stats.failed - stats.failed) | |
1819 | return -EBADMSG; | |
1820 | ||
1821 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
1da177e4 LT |
1822 | } |
1823 | ||
1824 | /** | |
8593fbc6 | 1825 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
8b6e50c9 BN |
1826 | * @mtd: MTD device structure |
1827 | * @from: offset to read from | |
1828 | * @ops: oob operation description structure | |
1da177e4 | 1829 | * |
8b6e50c9 | 1830 | * NAND read data and/or out-of-band data. |
1da177e4 | 1831 | */ |
8593fbc6 TG |
1832 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
1833 | struct mtd_oob_ops *ops) | |
1da177e4 | 1834 | { |
ace4dfee | 1835 | struct nand_chip *chip = mtd->priv; |
8593fbc6 TG |
1836 | int ret = -ENOTSUPP; |
1837 | ||
1838 | ops->retlen = 0; | |
1da177e4 LT |
1839 | |
1840 | /* Do not allow reads past end of device */ | |
7014568b | 1841 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
289c0522 BN |
1842 | pr_debug("%s: attempt to read beyond end of device\n", |
1843 | __func__); | |
1da177e4 LT |
1844 | return -EINVAL; |
1845 | } | |
1846 | ||
ace4dfee | 1847 | nand_get_device(chip, mtd, FL_READING); |
1da177e4 | 1848 | |
f8ac0414 | 1849 | switch (ops->mode) { |
0612b9dd BN |
1850 | case MTD_OPS_PLACE_OOB: |
1851 | case MTD_OPS_AUTO_OOB: | |
1852 | case MTD_OPS_RAW: | |
8593fbc6 | 1853 | break; |
1da177e4 | 1854 | |
8593fbc6 TG |
1855 | default: |
1856 | goto out; | |
1857 | } | |
1da177e4 | 1858 | |
8593fbc6 TG |
1859 | if (!ops->datbuf) |
1860 | ret = nand_do_read_oob(mtd, from, ops); | |
1861 | else | |
1862 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 1863 | |
7351d3a5 | 1864 | out: |
8593fbc6 TG |
1865 | nand_release_device(mtd); |
1866 | return ret; | |
1867 | } | |
61b03bd7 | 1868 | |
1da177e4 | 1869 | |
8593fbc6 | 1870 | /** |
7854d3f7 | 1871 | * nand_write_page_raw - [INTERN] raw page write function |
8b6e50c9 BN |
1872 | * @mtd: mtd info structure |
1873 | * @chip: nand chip info structure | |
1874 | * @buf: data buffer | |
1fbb938d | 1875 | * @oob_required: must write chip->oob_poi to OOB |
52ff49df | 1876 | * |
7854d3f7 | 1877 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 | 1878 | */ |
fdbad98d | 1879 | static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1880 | const uint8_t *buf, int oob_required) |
8593fbc6 TG |
1881 | { |
1882 | chip->write_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
1883 | if (oob_required) |
1884 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
1885 | |
1886 | return 0; | |
1da177e4 LT |
1887 | } |
1888 | ||
52ff49df | 1889 | /** |
7854d3f7 | 1890 | * nand_write_page_raw_syndrome - [INTERN] raw page write function |
8b6e50c9 BN |
1891 | * @mtd: mtd info structure |
1892 | * @chip: nand chip info structure | |
1893 | * @buf: data buffer | |
1fbb938d | 1894 | * @oob_required: must write chip->oob_poi to OOB |
52ff49df DB |
1895 | * |
1896 | * We need a special oob layout and handling even when ECC isn't checked. | |
1897 | */ | |
fdbad98d | 1898 | static int nand_write_page_raw_syndrome(struct mtd_info *mtd, |
7351d3a5 | 1899 | struct nand_chip *chip, |
1fbb938d | 1900 | const uint8_t *buf, int oob_required) |
52ff49df DB |
1901 | { |
1902 | int eccsize = chip->ecc.size; | |
1903 | int eccbytes = chip->ecc.bytes; | |
1904 | uint8_t *oob = chip->oob_poi; | |
1905 | int steps, size; | |
1906 | ||
1907 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1908 | chip->write_buf(mtd, buf, eccsize); | |
1909 | buf += eccsize; | |
1910 | ||
1911 | if (chip->ecc.prepad) { | |
1912 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
1913 | oob += chip->ecc.prepad; | |
1914 | } | |
1915 | ||
1916 | chip->read_buf(mtd, oob, eccbytes); | |
1917 | oob += eccbytes; | |
1918 | ||
1919 | if (chip->ecc.postpad) { | |
1920 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
1921 | oob += chip->ecc.postpad; | |
1922 | } | |
1923 | } | |
1924 | ||
1925 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1926 | if (size) | |
1927 | chip->write_buf(mtd, oob, size); | |
fdbad98d JW |
1928 | |
1929 | return 0; | |
52ff49df | 1930 | } |
9223a456 | 1931 | /** |
7854d3f7 | 1932 | * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function |
8b6e50c9 BN |
1933 | * @mtd: mtd info structure |
1934 | * @chip: nand chip info structure | |
1935 | * @buf: data buffer | |
1fbb938d | 1936 | * @oob_required: must write chip->oob_poi to OOB |
9223a456 | 1937 | */ |
fdbad98d | 1938 | static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1939 | const uint8_t *buf, int oob_required) |
9223a456 | 1940 | { |
f75e5097 TG |
1941 | int i, eccsize = chip->ecc.size; |
1942 | int eccbytes = chip->ecc.bytes; | |
1943 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 1944 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 1945 | const uint8_t *p = buf; |
8b099a39 | 1946 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1947 | |
7854d3f7 | 1948 | /* Software ECC calculation */ |
8593fbc6 TG |
1949 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
1950 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 1951 | |
8593fbc6 TG |
1952 | for (i = 0; i < chip->ecc.total; i++) |
1953 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 | 1954 | |
fdbad98d | 1955 | return chip->ecc.write_page_raw(mtd, chip, buf, 1); |
f75e5097 | 1956 | } |
9223a456 | 1957 | |
f75e5097 | 1958 | /** |
7854d3f7 | 1959 | * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function |
8b6e50c9 BN |
1960 | * @mtd: mtd info structure |
1961 | * @chip: nand chip info structure | |
1962 | * @buf: data buffer | |
1fbb938d | 1963 | * @oob_required: must write chip->oob_poi to OOB |
f75e5097 | 1964 | */ |
fdbad98d | 1965 | static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1966 | const uint8_t *buf, int oob_required) |
f75e5097 TG |
1967 | { |
1968 | int i, eccsize = chip->ecc.size; | |
1969 | int eccbytes = chip->ecc.bytes; | |
1970 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 1971 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 1972 | const uint8_t *p = buf; |
8b099a39 | 1973 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 1974 | |
f75e5097 TG |
1975 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1976 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 1977 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 1978 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
1979 | } |
1980 | ||
f75e5097 TG |
1981 | for (i = 0; i < chip->ecc.total; i++) |
1982 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
1983 | ||
1984 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
1985 | |
1986 | return 0; | |
9223a456 TG |
1987 | } |
1988 | ||
61b03bd7 | 1989 | /** |
7854d3f7 | 1990 | * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write |
8b6e50c9 BN |
1991 | * @mtd: mtd info structure |
1992 | * @chip: nand chip info structure | |
1993 | * @buf: data buffer | |
1fbb938d | 1994 | * @oob_required: must write chip->oob_poi to OOB |
1da177e4 | 1995 | * |
8b6e50c9 BN |
1996 | * The hw generator calculates the error syndrome automatically. Therefore we |
1997 | * need a special oob layout and handling. | |
f75e5097 | 1998 | */ |
fdbad98d | 1999 | static int nand_write_page_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
2000 | struct nand_chip *chip, |
2001 | const uint8_t *buf, int oob_required) | |
1da177e4 | 2002 | { |
f75e5097 TG |
2003 | int i, eccsize = chip->ecc.size; |
2004 | int eccbytes = chip->ecc.bytes; | |
2005 | int eccsteps = chip->ecc.steps; | |
2006 | const uint8_t *p = buf; | |
2007 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 2008 | |
f75e5097 | 2009 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 2010 | |
f75e5097 TG |
2011 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
2012 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 2013 | |
f75e5097 TG |
2014 | if (chip->ecc.prepad) { |
2015 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2016 | oob += chip->ecc.prepad; | |
2017 | } | |
2018 | ||
2019 | chip->ecc.calculate(mtd, p, oob); | |
2020 | chip->write_buf(mtd, oob, eccbytes); | |
2021 | oob += eccbytes; | |
2022 | ||
2023 | if (chip->ecc.postpad) { | |
2024 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2025 | oob += chip->ecc.postpad; | |
1da177e4 | 2026 | } |
1da177e4 | 2027 | } |
f75e5097 TG |
2028 | |
2029 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 2030 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
2031 | if (i) |
2032 | chip->write_buf(mtd, oob, i); | |
fdbad98d JW |
2033 | |
2034 | return 0; | |
f75e5097 TG |
2035 | } |
2036 | ||
2037 | /** | |
956e944c | 2038 | * nand_write_page - [REPLACEABLE] write one page |
8b6e50c9 BN |
2039 | * @mtd: MTD device structure |
2040 | * @chip: NAND chip descriptor | |
2041 | * @buf: the data to write | |
1fbb938d | 2042 | * @oob_required: must write chip->oob_poi to OOB |
8b6e50c9 BN |
2043 | * @page: page number to write |
2044 | * @cached: cached programming | |
2045 | * @raw: use _raw version of write_page | |
f75e5097 TG |
2046 | */ |
2047 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d BN |
2048 | const uint8_t *buf, int oob_required, int page, |
2049 | int cached, int raw) | |
f75e5097 TG |
2050 | { |
2051 | int status; | |
2052 | ||
2053 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
2054 | ||
956e944c | 2055 | if (unlikely(raw)) |
fdbad98d | 2056 | status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required); |
956e944c | 2057 | else |
fdbad98d JW |
2058 | status = chip->ecc.write_page(mtd, chip, buf, oob_required); |
2059 | ||
2060 | if (status < 0) | |
2061 | return status; | |
f75e5097 TG |
2062 | |
2063 | /* | |
7854d3f7 | 2064 | * Cached progamming disabled for now. Not sure if it's worth the |
8b6e50c9 | 2065 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s). |
f75e5097 TG |
2066 | */ |
2067 | cached = 0; | |
2068 | ||
2069 | if (!cached || !(chip->options & NAND_CACHEPRG)) { | |
2070 | ||
2071 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
7bc3312b | 2072 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2073 | /* |
2074 | * See if operation failed and additional status checks are | |
8b6e50c9 | 2075 | * available. |
f75e5097 TG |
2076 | */ |
2077 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2078 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
2079 | page); | |
2080 | ||
2081 | if (status & NAND_STATUS_FAIL) | |
2082 | return -EIO; | |
2083 | } else { | |
2084 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
7bc3312b | 2085 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2086 | } |
2087 | ||
f75e5097 | 2088 | return 0; |
1da177e4 LT |
2089 | } |
2090 | ||
8593fbc6 | 2091 | /** |
7854d3f7 | 2092 | * nand_fill_oob - [INTERN] Transfer client buffer to oob |
f722013e | 2093 | * @mtd: MTD device structure |
8b6e50c9 BN |
2094 | * @oob: oob data buffer |
2095 | * @len: oob data write length | |
2096 | * @ops: oob ops structure | |
8593fbc6 | 2097 | */ |
f722013e TAA |
2098 | static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, |
2099 | struct mtd_oob_ops *ops) | |
8593fbc6 | 2100 | { |
f722013e TAA |
2101 | struct nand_chip *chip = mtd->priv; |
2102 | ||
2103 | /* | |
2104 | * Initialise to all 0xFF, to avoid the possibility of left over OOB | |
2105 | * data from a previous OOB read. | |
2106 | */ | |
2107 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
2108 | ||
f8ac0414 | 2109 | switch (ops->mode) { |
8593fbc6 | 2110 | |
0612b9dd BN |
2111 | case MTD_OPS_PLACE_OOB: |
2112 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2113 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); |
2114 | return oob + len; | |
2115 | ||
0612b9dd | 2116 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 2117 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
2118 | uint32_t boffs = 0, woffs = ops->ooboffs; |
2119 | size_t bytes = 0; | |
8593fbc6 | 2120 | |
f8ac0414 | 2121 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 2122 | /* Write request not from offset 0? */ |
7bc3312b TG |
2123 | if (unlikely(woffs)) { |
2124 | if (woffs >= free->length) { | |
2125 | woffs -= free->length; | |
2126 | continue; | |
2127 | } | |
2128 | boffs = free->offset + woffs; | |
2129 | bytes = min_t(size_t, len, | |
2130 | (free->length - woffs)); | |
2131 | woffs = 0; | |
2132 | } else { | |
2133 | bytes = min_t(size_t, len, free->length); | |
2134 | boffs = free->offset; | |
2135 | } | |
8b0036ee | 2136 | memcpy(chip->oob_poi + boffs, oob, bytes); |
8593fbc6 TG |
2137 | oob += bytes; |
2138 | } | |
2139 | return oob; | |
2140 | } | |
2141 | default: | |
2142 | BUG(); | |
2143 | } | |
2144 | return NULL; | |
2145 | } | |
2146 | ||
f8ac0414 | 2147 | #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) |
1da177e4 LT |
2148 | |
2149 | /** | |
7854d3f7 | 2150 | * nand_do_write_ops - [INTERN] NAND write with ECC |
8b6e50c9 BN |
2151 | * @mtd: MTD device structure |
2152 | * @to: offset to write to | |
2153 | * @ops: oob operations description structure | |
1da177e4 | 2154 | * |
8b6e50c9 | 2155 | * NAND write with ECC. |
1da177e4 | 2156 | */ |
8593fbc6 TG |
2157 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
2158 | struct mtd_oob_ops *ops) | |
1da177e4 | 2159 | { |
29072b96 | 2160 | int chipnr, realpage, page, blockmask, column; |
ace4dfee | 2161 | struct nand_chip *chip = mtd->priv; |
8593fbc6 | 2162 | uint32_t writelen = ops->len; |
782ce79a ML |
2163 | |
2164 | uint32_t oobwritelen = ops->ooblen; | |
0612b9dd | 2165 | uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ? |
782ce79a ML |
2166 | mtd->oobavail : mtd->oobsize; |
2167 | ||
8593fbc6 TG |
2168 | uint8_t *oob = ops->oobbuf; |
2169 | uint8_t *buf = ops->datbuf; | |
29072b96 | 2170 | int ret, subpage; |
e47f3db4 | 2171 | int oob_required = oob ? 1 : 0; |
1da177e4 | 2172 | |
8593fbc6 | 2173 | ops->retlen = 0; |
29072b96 TG |
2174 | if (!writelen) |
2175 | return 0; | |
1da177e4 | 2176 | |
8b6e50c9 | 2177 | /* Reject writes, which are not page aligned */ |
8593fbc6 | 2178 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
d0370219 BN |
2179 | pr_notice("%s: attempt to write non page aligned data\n", |
2180 | __func__); | |
1da177e4 LT |
2181 | return -EINVAL; |
2182 | } | |
2183 | ||
29072b96 TG |
2184 | column = to & (mtd->writesize - 1); |
2185 | subpage = column || (writelen & (mtd->writesize - 1)); | |
2186 | ||
2187 | if (subpage && oob) | |
2188 | return -EINVAL; | |
1da177e4 | 2189 | |
6a930961 TG |
2190 | chipnr = (int)(to >> chip->chip_shift); |
2191 | chip->select_chip(mtd, chipnr); | |
2192 | ||
1da177e4 | 2193 | /* Check, if it is write protected */ |
b0bb6903 HS |
2194 | if (nand_check_wp(mtd)) { |
2195 | ret = -EIO; | |
2196 | goto err_out; | |
2197 | } | |
1da177e4 | 2198 | |
f75e5097 TG |
2199 | realpage = (int)(to >> chip->page_shift); |
2200 | page = realpage & chip->pagemask; | |
2201 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
2202 | ||
2203 | /* Invalidate the page cache, when we write to the cached page */ | |
2204 | if (to <= (chip->pagebuf << chip->page_shift) && | |
8593fbc6 | 2205 | (chip->pagebuf << chip->page_shift) < (to + ops->len)) |
ace4dfee | 2206 | chip->pagebuf = -1; |
61b03bd7 | 2207 | |
782ce79a | 2208 | /* Don't allow multipage oob writes with offset */ |
b0bb6903 HS |
2209 | if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { |
2210 | ret = -EINVAL; | |
2211 | goto err_out; | |
2212 | } | |
782ce79a | 2213 | |
f8ac0414 | 2214 | while (1) { |
29072b96 | 2215 | int bytes = mtd->writesize; |
f75e5097 | 2216 | int cached = writelen > bytes && page != blockmask; |
29072b96 TG |
2217 | uint8_t *wbuf = buf; |
2218 | ||
8b6e50c9 | 2219 | /* Partial page write? */ |
29072b96 TG |
2220 | if (unlikely(column || writelen < (mtd->writesize - 1))) { |
2221 | cached = 0; | |
2222 | bytes = min_t(int, bytes - column, (int) writelen); | |
2223 | chip->pagebuf = -1; | |
2224 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
2225 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
2226 | wbuf = chip->buffers->databuf; | |
2227 | } | |
1da177e4 | 2228 | |
782ce79a ML |
2229 | if (unlikely(oob)) { |
2230 | size_t len = min(oobwritelen, oobmaxlen); | |
f722013e | 2231 | oob = nand_fill_oob(mtd, oob, len, ops); |
782ce79a | 2232 | oobwritelen -= len; |
f722013e TAA |
2233 | } else { |
2234 | /* We still need to erase leftover OOB data */ | |
2235 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
782ce79a | 2236 | } |
8593fbc6 | 2237 | |
e47f3db4 BN |
2238 | ret = chip->write_page(mtd, chip, wbuf, oob_required, page, |
2239 | cached, (ops->mode == MTD_OPS_RAW)); | |
f75e5097 TG |
2240 | if (ret) |
2241 | break; | |
2242 | ||
2243 | writelen -= bytes; | |
2244 | if (!writelen) | |
2245 | break; | |
2246 | ||
29072b96 | 2247 | column = 0; |
f75e5097 TG |
2248 | buf += bytes; |
2249 | realpage++; | |
2250 | ||
2251 | page = realpage & chip->pagemask; | |
2252 | /* Check, if we cross a chip boundary */ | |
2253 | if (!page) { | |
2254 | chipnr++; | |
2255 | chip->select_chip(mtd, -1); | |
2256 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2257 | } |
2258 | } | |
8593fbc6 | 2259 | |
8593fbc6 | 2260 | ops->retlen = ops->len - writelen; |
7014568b VW |
2261 | if (unlikely(oob)) |
2262 | ops->oobretlen = ops->ooblen; | |
b0bb6903 HS |
2263 | |
2264 | err_out: | |
2265 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
2266 | return ret; |
2267 | } | |
2268 | ||
2af7c653 SK |
2269 | /** |
2270 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
8b6e50c9 BN |
2271 | * @mtd: MTD device structure |
2272 | * @to: offset to write to | |
2273 | * @len: number of bytes to write | |
2274 | * @retlen: pointer to variable to store the number of written bytes | |
2275 | * @buf: the data to write | |
2af7c653 SK |
2276 | * |
2277 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
2278 | * may for example be called by mtdoops when writing an oops while in panic. | |
2279 | */ | |
2280 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
2281 | size_t *retlen, const uint8_t *buf) | |
2282 | { | |
2283 | struct nand_chip *chip = mtd->priv; | |
4a89ff88 | 2284 | struct mtd_oob_ops ops; |
2af7c653 SK |
2285 | int ret; |
2286 | ||
8b6e50c9 | 2287 | /* Wait for the device to get ready */ |
2af7c653 SK |
2288 | panic_nand_wait(mtd, chip, 400); |
2289 | ||
8b6e50c9 | 2290 | /* Grab the device */ |
2af7c653 SK |
2291 | panic_nand_get_device(chip, mtd, FL_WRITING); |
2292 | ||
4a89ff88 BN |
2293 | ops.len = len; |
2294 | ops.datbuf = (uint8_t *)buf; | |
2295 | ops.oobbuf = NULL; | |
11041ae6 | 2296 | ops.mode = MTD_OPS_PLACE_OOB; |
2af7c653 | 2297 | |
4a89ff88 | 2298 | ret = nand_do_write_ops(mtd, to, &ops); |
2af7c653 | 2299 | |
4a89ff88 | 2300 | *retlen = ops.retlen; |
2af7c653 SK |
2301 | return ret; |
2302 | } | |
2303 | ||
f75e5097 | 2304 | /** |
8593fbc6 | 2305 | * nand_write - [MTD Interface] NAND write with ECC |
8b6e50c9 BN |
2306 | * @mtd: MTD device structure |
2307 | * @to: offset to write to | |
2308 | * @len: number of bytes to write | |
2309 | * @retlen: pointer to variable to store the number of written bytes | |
2310 | * @buf: the data to write | |
f75e5097 | 2311 | * |
8b6e50c9 | 2312 | * NAND write with ECC. |
f75e5097 | 2313 | */ |
8593fbc6 TG |
2314 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
2315 | size_t *retlen, const uint8_t *buf) | |
f75e5097 TG |
2316 | { |
2317 | struct nand_chip *chip = mtd->priv; | |
4a89ff88 | 2318 | struct mtd_oob_ops ops; |
f75e5097 TG |
2319 | int ret; |
2320 | ||
7bc3312b | 2321 | nand_get_device(chip, mtd, FL_WRITING); |
4a89ff88 BN |
2322 | ops.len = len; |
2323 | ops.datbuf = (uint8_t *)buf; | |
2324 | ops.oobbuf = NULL; | |
11041ae6 | 2325 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 2326 | ret = nand_do_write_ops(mtd, to, &ops); |
4a89ff88 | 2327 | *retlen = ops.retlen; |
f75e5097 | 2328 | nand_release_device(mtd); |
8593fbc6 | 2329 | return ret; |
f75e5097 | 2330 | } |
7314e9e7 | 2331 | |
1da177e4 | 2332 | /** |
8593fbc6 | 2333 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
8b6e50c9 BN |
2334 | * @mtd: MTD device structure |
2335 | * @to: offset to write to | |
2336 | * @ops: oob operation description structure | |
1da177e4 | 2337 | * |
8b6e50c9 | 2338 | * NAND write out-of-band. |
1da177e4 | 2339 | */ |
8593fbc6 TG |
2340 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
2341 | struct mtd_oob_ops *ops) | |
1da177e4 | 2342 | { |
03736155 | 2343 | int chipnr, page, status, len; |
ace4dfee | 2344 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2345 | |
289c0522 | 2346 | pr_debug("%s: to = 0x%08x, len = %i\n", |
20d8e248 | 2347 | __func__, (unsigned int)to, (int)ops->ooblen); |
1da177e4 | 2348 | |
0612b9dd | 2349 | if (ops->mode == MTD_OPS_AUTO_OOB) |
03736155 AH |
2350 | len = chip->ecc.layout->oobavail; |
2351 | else | |
2352 | len = mtd->oobsize; | |
2353 | ||
1da177e4 | 2354 | /* Do not allow write past end of page */ |
03736155 | 2355 | if ((ops->ooboffs + ops->ooblen) > len) { |
289c0522 BN |
2356 | pr_debug("%s: attempt to write past end of page\n", |
2357 | __func__); | |
1da177e4 LT |
2358 | return -EINVAL; |
2359 | } | |
2360 | ||
03736155 | 2361 | if (unlikely(ops->ooboffs >= len)) { |
289c0522 BN |
2362 | pr_debug("%s: attempt to start write outside oob\n", |
2363 | __func__); | |
03736155 AH |
2364 | return -EINVAL; |
2365 | } | |
2366 | ||
775adc3d | 2367 | /* Do not allow write past end of device */ |
03736155 AH |
2368 | if (unlikely(to >= mtd->size || |
2369 | ops->ooboffs + ops->ooblen > | |
2370 | ((mtd->size >> chip->page_shift) - | |
2371 | (to >> chip->page_shift)) * len)) { | |
289c0522 BN |
2372 | pr_debug("%s: attempt to write beyond end of device\n", |
2373 | __func__); | |
03736155 AH |
2374 | return -EINVAL; |
2375 | } | |
2376 | ||
7314e9e7 | 2377 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 2378 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2379 | |
7314e9e7 TG |
2380 | /* Shift to get page */ |
2381 | page = (int)(to >> chip->page_shift); | |
2382 | ||
2383 | /* | |
2384 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
2385 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
2386 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
2387 | * it in the doc2000 driver in August 1999. dwmw2. | |
2388 | */ | |
ace4dfee | 2389 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
2390 | |
2391 | /* Check, if it is write protected */ | |
b0bb6903 HS |
2392 | if (nand_check_wp(mtd)) { |
2393 | chip->select_chip(mtd, -1); | |
8593fbc6 | 2394 | return -EROFS; |
b0bb6903 | 2395 | } |
61b03bd7 | 2396 | |
1da177e4 | 2397 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
2398 | if (page == chip->pagebuf) |
2399 | chip->pagebuf = -1; | |
1da177e4 | 2400 | |
f722013e | 2401 | nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops); |
9ce244b3 | 2402 | |
0612b9dd | 2403 | if (ops->mode == MTD_OPS_RAW) |
9ce244b3 BN |
2404 | status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask); |
2405 | else | |
2406 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); | |
1da177e4 | 2407 | |
b0bb6903 HS |
2408 | chip->select_chip(mtd, -1); |
2409 | ||
7bc3312b TG |
2410 | if (status) |
2411 | return status; | |
1da177e4 | 2412 | |
7014568b | 2413 | ops->oobretlen = ops->ooblen; |
1da177e4 | 2414 | |
7bc3312b | 2415 | return 0; |
8593fbc6 TG |
2416 | } |
2417 | ||
2418 | /** | |
2419 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
8b6e50c9 BN |
2420 | * @mtd: MTD device structure |
2421 | * @to: offset to write to | |
2422 | * @ops: oob operation description structure | |
8593fbc6 TG |
2423 | */ |
2424 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
2425 | struct mtd_oob_ops *ops) | |
2426 | { | |
8593fbc6 TG |
2427 | struct nand_chip *chip = mtd->priv; |
2428 | int ret = -ENOTSUPP; | |
2429 | ||
2430 | ops->retlen = 0; | |
2431 | ||
2432 | /* Do not allow writes past end of device */ | |
7014568b | 2433 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
289c0522 BN |
2434 | pr_debug("%s: attempt to write beyond end of device\n", |
2435 | __func__); | |
8593fbc6 TG |
2436 | return -EINVAL; |
2437 | } | |
2438 | ||
7bc3312b | 2439 | nand_get_device(chip, mtd, FL_WRITING); |
8593fbc6 | 2440 | |
f8ac0414 | 2441 | switch (ops->mode) { |
0612b9dd BN |
2442 | case MTD_OPS_PLACE_OOB: |
2443 | case MTD_OPS_AUTO_OOB: | |
2444 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2445 | break; |
2446 | ||
2447 | default: | |
2448 | goto out; | |
2449 | } | |
2450 | ||
2451 | if (!ops->datbuf) | |
2452 | ret = nand_do_write_oob(mtd, to, ops); | |
2453 | else | |
2454 | ret = nand_do_write_ops(mtd, to, ops); | |
2455 | ||
7351d3a5 | 2456 | out: |
1da177e4 | 2457 | nand_release_device(mtd); |
1da177e4 LT |
2458 | return ret; |
2459 | } | |
2460 | ||
1da177e4 | 2461 | /** |
7854d3f7 | 2462 | * single_erase_cmd - [GENERIC] NAND standard block erase command function |
8b6e50c9 BN |
2463 | * @mtd: MTD device structure |
2464 | * @page: the page address of the block which will be erased | |
1da177e4 | 2465 | * |
8b6e50c9 | 2466 | * Standard erase command for NAND chips. |
1da177e4 | 2467 | */ |
e0c7d767 | 2468 | static void single_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 2469 | { |
ace4dfee | 2470 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2471 | /* Send commands to erase a block */ |
ace4dfee TG |
2472 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
2473 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
2474 | } |
2475 | ||
2476 | /** | |
7854d3f7 | 2477 | * multi_erase_cmd - [GENERIC] AND specific block erase command function |
8b6e50c9 BN |
2478 | * @mtd: MTD device structure |
2479 | * @page: the page address of the block which will be erased | |
1da177e4 | 2480 | * |
8b6e50c9 | 2481 | * AND multi block erase command function. Erase 4 consecutive blocks. |
1da177e4 | 2482 | */ |
e0c7d767 | 2483 | static void multi_erase_cmd(struct mtd_info *mtd, int page) |
1da177e4 | 2484 | { |
ace4dfee | 2485 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2486 | /* Send commands to erase a block */ |
ace4dfee TG |
2487 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); |
2488 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
2489 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++); | |
2490 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); | |
2491 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
1da177e4 LT |
2492 | } |
2493 | ||
2494 | /** | |
2495 | * nand_erase - [MTD Interface] erase block(s) | |
8b6e50c9 BN |
2496 | * @mtd: MTD device structure |
2497 | * @instr: erase instruction | |
1da177e4 | 2498 | * |
8b6e50c9 | 2499 | * Erase one ore more blocks. |
1da177e4 | 2500 | */ |
e0c7d767 | 2501 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 2502 | { |
e0c7d767 | 2503 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 2504 | } |
61b03bd7 | 2505 | |
30f464b7 | 2506 | #define BBT_PAGE_MASK 0xffffff3f |
1da177e4 | 2507 | /** |
7854d3f7 | 2508 | * nand_erase_nand - [INTERN] erase block(s) |
8b6e50c9 BN |
2509 | * @mtd: MTD device structure |
2510 | * @instr: erase instruction | |
2511 | * @allowbbt: allow erasing the bbt area | |
1da177e4 | 2512 | * |
8b6e50c9 | 2513 | * Erase one ore more blocks. |
1da177e4 | 2514 | */ |
ace4dfee TG |
2515 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
2516 | int allowbbt) | |
1da177e4 | 2517 | { |
69423d99 | 2518 | int page, status, pages_per_block, ret, chipnr; |
ace4dfee | 2519 | struct nand_chip *chip = mtd->priv; |
f8ac0414 | 2520 | loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0}; |
ace4dfee | 2521 | unsigned int bbt_masked_page = 0xffffffff; |
69423d99 | 2522 | loff_t len; |
1da177e4 | 2523 | |
289c0522 BN |
2524 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
2525 | __func__, (unsigned long long)instr->addr, | |
2526 | (unsigned long long)instr->len); | |
1da177e4 | 2527 | |
6fe5a6ac | 2528 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 2529 | return -EINVAL; |
1da177e4 | 2530 | |
1da177e4 | 2531 | /* Grab the lock and see if the device is available */ |
ace4dfee | 2532 | nand_get_device(chip, mtd, FL_ERASING); |
1da177e4 LT |
2533 | |
2534 | /* Shift to get first page */ | |
ace4dfee TG |
2535 | page = (int)(instr->addr >> chip->page_shift); |
2536 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
2537 | |
2538 | /* Calculate pages in each block */ | |
ace4dfee | 2539 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
2540 | |
2541 | /* Select the NAND device */ | |
ace4dfee | 2542 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2543 | |
1da177e4 LT |
2544 | /* Check, if it is write protected */ |
2545 | if (nand_check_wp(mtd)) { | |
289c0522 BN |
2546 | pr_debug("%s: device is write protected!\n", |
2547 | __func__); | |
1da177e4 LT |
2548 | instr->state = MTD_ERASE_FAILED; |
2549 | goto erase_exit; | |
2550 | } | |
2551 | ||
ace4dfee TG |
2552 | /* |
2553 | * If BBT requires refresh, set the BBT page mask to see if the BBT | |
2554 | * should be rewritten. Otherwise the mask is set to 0xffffffff which | |
2555 | * can not be matched. This is also done when the bbt is actually | |
7854d3f7 | 2556 | * erased to avoid recursive updates. |
ace4dfee TG |
2557 | */ |
2558 | if (chip->options & BBT_AUTO_REFRESH && !allowbbt) | |
2559 | bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK; | |
30f464b7 | 2560 | |
1da177e4 LT |
2561 | /* Loop through the pages */ |
2562 | len = instr->len; | |
2563 | ||
2564 | instr->state = MTD_ERASING; | |
2565 | ||
2566 | while (len) { | |
12183a20 | 2567 | /* Check if we have a bad block, we do not erase bad blocks! */ |
ace4dfee TG |
2568 | if (nand_block_checkbad(mtd, ((loff_t) page) << |
2569 | chip->page_shift, 0, allowbbt)) { | |
d0370219 BN |
2570 | pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", |
2571 | __func__, page); | |
1da177e4 LT |
2572 | instr->state = MTD_ERASE_FAILED; |
2573 | goto erase_exit; | |
2574 | } | |
61b03bd7 | 2575 | |
ace4dfee TG |
2576 | /* |
2577 | * Invalidate the page cache, if we erase the block which | |
8b6e50c9 | 2578 | * contains the current cached page. |
ace4dfee TG |
2579 | */ |
2580 | if (page <= chip->pagebuf && chip->pagebuf < | |
2581 | (page + pages_per_block)) | |
2582 | chip->pagebuf = -1; | |
1da177e4 | 2583 | |
ace4dfee | 2584 | chip->erase_cmd(mtd, page & chip->pagemask); |
61b03bd7 | 2585 | |
7bc3312b | 2586 | status = chip->waitfunc(mtd, chip); |
1da177e4 | 2587 | |
ace4dfee TG |
2588 | /* |
2589 | * See if operation failed and additional status checks are | |
2590 | * available | |
2591 | */ | |
2592 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2593 | status = chip->errstat(mtd, chip, FL_ERASING, | |
2594 | status, page); | |
068e3c0a | 2595 | |
1da177e4 | 2596 | /* See if block erase succeeded */ |
a4ab4c5d | 2597 | if (status & NAND_STATUS_FAIL) { |
289c0522 BN |
2598 | pr_debug("%s: failed erase, page 0x%08x\n", |
2599 | __func__, page); | |
1da177e4 | 2600 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
2601 | instr->fail_addr = |
2602 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
2603 | goto erase_exit; |
2604 | } | |
30f464b7 | 2605 | |
ace4dfee TG |
2606 | /* |
2607 | * If BBT requires refresh, set the BBT rewrite flag to the | |
8b6e50c9 | 2608 | * page being erased. |
ace4dfee TG |
2609 | */ |
2610 | if (bbt_masked_page != 0xffffffff && | |
2611 | (page & BBT_PAGE_MASK) == bbt_masked_page) | |
69423d99 AH |
2612 | rewrite_bbt[chipnr] = |
2613 | ((loff_t)page << chip->page_shift); | |
61b03bd7 | 2614 | |
1da177e4 | 2615 | /* Increment page address and decrement length */ |
ace4dfee | 2616 | len -= (1 << chip->phys_erase_shift); |
1da177e4 LT |
2617 | page += pages_per_block; |
2618 | ||
2619 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 2620 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 2621 | chipnr++; |
ace4dfee TG |
2622 | chip->select_chip(mtd, -1); |
2623 | chip->select_chip(mtd, chipnr); | |
30f464b7 | 2624 | |
ace4dfee TG |
2625 | /* |
2626 | * If BBT requires refresh and BBT-PERCHIP, set the BBT | |
8b6e50c9 | 2627 | * page mask to see if this BBT should be rewritten. |
ace4dfee TG |
2628 | */ |
2629 | if (bbt_masked_page != 0xffffffff && | |
2630 | (chip->bbt_td->options & NAND_BBT_PERCHIP)) | |
2631 | bbt_masked_page = chip->bbt_td->pages[chipnr] & | |
2632 | BBT_PAGE_MASK; | |
1da177e4 LT |
2633 | } |
2634 | } | |
2635 | instr->state = MTD_ERASE_DONE; | |
2636 | ||
7351d3a5 | 2637 | erase_exit: |
1da177e4 LT |
2638 | |
2639 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
2640 | |
2641 | /* Deselect and wake up anyone waiting on the device */ | |
b0bb6903 | 2642 | chip->select_chip(mtd, -1); |
1da177e4 LT |
2643 | nand_release_device(mtd); |
2644 | ||
49defc01 DW |
2645 | /* Do call back function */ |
2646 | if (!ret) | |
2647 | mtd_erase_callback(instr); | |
2648 | ||
ace4dfee TG |
2649 | /* |
2650 | * If BBT requires refresh and erase was successful, rewrite any | |
8b6e50c9 | 2651 | * selected bad block tables. |
ace4dfee TG |
2652 | */ |
2653 | if (bbt_masked_page == 0xffffffff || ret) | |
2654 | return ret; | |
2655 | ||
2656 | for (chipnr = 0; chipnr < chip->numchips; chipnr++) { | |
2657 | if (!rewrite_bbt[chipnr]) | |
2658 | continue; | |
8b6e50c9 | 2659 | /* Update the BBT for chip */ |
289c0522 BN |
2660 | pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n", |
2661 | __func__, chipnr, rewrite_bbt[chipnr], | |
2662 | chip->bbt_td->pages[chipnr]); | |
ace4dfee | 2663 | nand_update_bbt(mtd, rewrite_bbt[chipnr]); |
30f464b7 DM |
2664 | } |
2665 | ||
1da177e4 LT |
2666 | /* Return more or less happy */ |
2667 | return ret; | |
2668 | } | |
2669 | ||
2670 | /** | |
2671 | * nand_sync - [MTD Interface] sync | |
8b6e50c9 | 2672 | * @mtd: MTD device structure |
1da177e4 | 2673 | * |
8b6e50c9 | 2674 | * Sync is actually a wait for chip ready function. |
1da177e4 | 2675 | */ |
e0c7d767 | 2676 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 2677 | { |
ace4dfee | 2678 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2679 | |
289c0522 | 2680 | pr_debug("%s: called\n", __func__); |
1da177e4 LT |
2681 | |
2682 | /* Grab the lock and see if the device is available */ | |
ace4dfee | 2683 | nand_get_device(chip, mtd, FL_SYNCING); |
1da177e4 | 2684 | /* Release it and go back */ |
e0c7d767 | 2685 | nand_release_device(mtd); |
1da177e4 LT |
2686 | } |
2687 | ||
1da177e4 | 2688 | /** |
ace4dfee | 2689 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
8b6e50c9 BN |
2690 | * @mtd: MTD device structure |
2691 | * @offs: offset relative to mtd start | |
1da177e4 | 2692 | */ |
ace4dfee | 2693 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 | 2694 | { |
ace4dfee | 2695 | return nand_block_checkbad(mtd, offs, 1, 0); |
1da177e4 LT |
2696 | } |
2697 | ||
2698 | /** | |
ace4dfee | 2699 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
8b6e50c9 BN |
2700 | * @mtd: MTD device structure |
2701 | * @ofs: offset relative to mtd start | |
1da177e4 | 2702 | */ |
e0c7d767 | 2703 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 2704 | { |
ace4dfee | 2705 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
2706 | int ret; |
2707 | ||
f8ac0414 FF |
2708 | ret = nand_block_isbad(mtd, ofs); |
2709 | if (ret) { | |
8b6e50c9 | 2710 | /* If it was bad already, return success and do nothing */ |
1da177e4 LT |
2711 | if (ret > 0) |
2712 | return 0; | |
e0c7d767 DW |
2713 | return ret; |
2714 | } | |
1da177e4 | 2715 | |
ace4dfee | 2716 | return chip->block_markbad(mtd, ofs); |
1da177e4 LT |
2717 | } |
2718 | ||
7db03ecc HS |
2719 | /** |
2720 | * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand | |
2721 | * @mtd: MTD device structure | |
2722 | * @chip: nand chip info structure | |
2723 | * @addr: feature address. | |
2724 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
2725 | */ | |
2726 | static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, | |
2727 | int addr, uint8_t *subfeature_param) | |
2728 | { | |
2729 | int status; | |
2730 | ||
2731 | if (!chip->onfi_version) | |
2732 | return -EINVAL; | |
2733 | ||
2734 | chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1); | |
2735 | chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN); | |
2736 | status = chip->waitfunc(mtd, chip); | |
2737 | if (status & NAND_STATUS_FAIL) | |
2738 | return -EIO; | |
2739 | return 0; | |
2740 | } | |
2741 | ||
2742 | /** | |
2743 | * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand | |
2744 | * @mtd: MTD device structure | |
2745 | * @chip: nand chip info structure | |
2746 | * @addr: feature address. | |
2747 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
2748 | */ | |
2749 | static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, | |
2750 | int addr, uint8_t *subfeature_param) | |
2751 | { | |
2752 | if (!chip->onfi_version) | |
2753 | return -EINVAL; | |
2754 | ||
2755 | /* clear the sub feature parameters */ | |
2756 | memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN); | |
2757 | ||
2758 | chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1); | |
2759 | chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN); | |
2760 | return 0; | |
2761 | } | |
2762 | ||
962034f4 VW |
2763 | /** |
2764 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
8b6e50c9 | 2765 | * @mtd: MTD device structure |
962034f4 VW |
2766 | */ |
2767 | static int nand_suspend(struct mtd_info *mtd) | |
2768 | { | |
ace4dfee | 2769 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2770 | |
ace4dfee | 2771 | return nand_get_device(chip, mtd, FL_PM_SUSPENDED); |
962034f4 VW |
2772 | } |
2773 | ||
2774 | /** | |
2775 | * nand_resume - [MTD Interface] Resume the NAND flash | |
8b6e50c9 | 2776 | * @mtd: MTD device structure |
962034f4 VW |
2777 | */ |
2778 | static void nand_resume(struct mtd_info *mtd) | |
2779 | { | |
ace4dfee | 2780 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2781 | |
ace4dfee | 2782 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
2783 | nand_release_device(mtd); |
2784 | else | |
d0370219 BN |
2785 | pr_err("%s called for a chip which is not in suspended state\n", |
2786 | __func__); | |
962034f4 VW |
2787 | } |
2788 | ||
8b6e50c9 | 2789 | /* Set default functions */ |
ace4dfee | 2790 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 2791 | { |
1da177e4 | 2792 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
2793 | if (!chip->chip_delay) |
2794 | chip->chip_delay = 20; | |
1da177e4 LT |
2795 | |
2796 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
2797 | if (chip->cmdfunc == NULL) |
2798 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
2799 | |
2800 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
2801 | if (chip->waitfunc == NULL) |
2802 | chip->waitfunc = nand_wait; | |
2803 | ||
2804 | if (!chip->select_chip) | |
2805 | chip->select_chip = nand_select_chip; | |
2806 | if (!chip->read_byte) | |
2807 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; | |
2808 | if (!chip->read_word) | |
2809 | chip->read_word = nand_read_word; | |
2810 | if (!chip->block_bad) | |
2811 | chip->block_bad = nand_block_bad; | |
2812 | if (!chip->block_markbad) | |
2813 | chip->block_markbad = nand_default_block_markbad; | |
2814 | if (!chip->write_buf) | |
2815 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; | |
2816 | if (!chip->read_buf) | |
2817 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; | |
ace4dfee TG |
2818 | if (!chip->scan_bbt) |
2819 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
2820 | |
2821 | if (!chip->controller) { | |
2822 | chip->controller = &chip->hwcontrol; | |
2823 | spin_lock_init(&chip->controller->lock); | |
2824 | init_waitqueue_head(&chip->controller->wq); | |
2825 | } | |
2826 | ||
7aa65bfd TG |
2827 | } |
2828 | ||
8b6e50c9 | 2829 | /* Sanitize ONFI strings so we can safely print them */ |
d1e1f4e4 FF |
2830 | static void sanitize_string(uint8_t *s, size_t len) |
2831 | { | |
2832 | ssize_t i; | |
2833 | ||
8b6e50c9 | 2834 | /* Null terminate */ |
d1e1f4e4 FF |
2835 | s[len - 1] = 0; |
2836 | ||
8b6e50c9 | 2837 | /* Remove non printable chars */ |
d1e1f4e4 FF |
2838 | for (i = 0; i < len - 1; i++) { |
2839 | if (s[i] < ' ' || s[i] > 127) | |
2840 | s[i] = '?'; | |
2841 | } | |
2842 | ||
8b6e50c9 | 2843 | /* Remove trailing spaces */ |
d1e1f4e4 FF |
2844 | strim(s); |
2845 | } | |
2846 | ||
2847 | static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) | |
2848 | { | |
2849 | int i; | |
2850 | while (len--) { | |
2851 | crc ^= *p++ << 8; | |
2852 | for (i = 0; i < 8; i++) | |
2853 | crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); | |
2854 | } | |
2855 | ||
2856 | return crc; | |
2857 | } | |
2858 | ||
6fb277ba | 2859 | /* |
8b6e50c9 | 2860 | * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. |
6fb277ba FF |
2861 | */ |
2862 | static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, | |
08c248fb | 2863 | int *busw) |
6fb277ba FF |
2864 | { |
2865 | struct nand_onfi_params *p = &chip->onfi_params; | |
2866 | int i; | |
2867 | int val; | |
2868 | ||
7854d3f7 | 2869 | /* Try ONFI for unknown chip or LP */ |
6fb277ba FF |
2870 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); |
2871 | if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || | |
2872 | chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') | |
2873 | return 0; | |
2874 | ||
6fb277ba FF |
2875 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); |
2876 | for (i = 0; i < 3; i++) { | |
2877 | chip->read_buf(mtd, (uint8_t *)p, sizeof(*p)); | |
2878 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == | |
2879 | le16_to_cpu(p->crc)) { | |
9a4d4d69 | 2880 | pr_info("ONFI param page %d valid\n", i); |
6fb277ba FF |
2881 | break; |
2882 | } | |
2883 | } | |
2884 | ||
2885 | if (i == 3) | |
2886 | return 0; | |
2887 | ||
8b6e50c9 | 2888 | /* Check version */ |
6fb277ba | 2889 | val = le16_to_cpu(p->revision); |
b7b1a29d BN |
2890 | if (val & (1 << 5)) |
2891 | chip->onfi_version = 23; | |
2892 | else if (val & (1 << 4)) | |
6fb277ba FF |
2893 | chip->onfi_version = 22; |
2894 | else if (val & (1 << 3)) | |
2895 | chip->onfi_version = 21; | |
2896 | else if (val & (1 << 2)) | |
2897 | chip->onfi_version = 20; | |
b7b1a29d | 2898 | else if (val & (1 << 1)) |
6fb277ba | 2899 | chip->onfi_version = 10; |
b7b1a29d BN |
2900 | else |
2901 | chip->onfi_version = 0; | |
2902 | ||
2903 | if (!chip->onfi_version) { | |
d0370219 | 2904 | pr_info("%s: unsupported ONFI version: %d\n", __func__, val); |
b7b1a29d BN |
2905 | return 0; |
2906 | } | |
6fb277ba FF |
2907 | |
2908 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
2909 | sanitize_string(p->model, sizeof(p->model)); | |
2910 | if (!mtd->name) | |
2911 | mtd->name = p->model; | |
2912 | mtd->writesize = le32_to_cpu(p->byte_per_page); | |
2913 | mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize; | |
2914 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); | |
63795755 MC |
2915 | chip->chipsize = le32_to_cpu(p->blocks_per_lun); |
2916 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; | |
08c248fb | 2917 | *busw = 0; |
6fb277ba | 2918 | if (le16_to_cpu(p->features) & 1) |
08c248fb | 2919 | *busw = NAND_BUSWIDTH_16; |
6fb277ba | 2920 | |
d42b5de3 | 2921 | pr_info("ONFI flash detected\n"); |
6fb277ba FF |
2922 | return 1; |
2923 | } | |
2924 | ||
e3b88bd6 BN |
2925 | /* |
2926 | * nand_id_has_period - Check if an ID string has a given wraparound period | |
2927 | * @id_data: the ID string | |
2928 | * @arrlen: the length of the @id_data array | |
2929 | * @period: the period of repitition | |
2930 | * | |
2931 | * Check if an ID string is repeated within a given sequence of bytes at | |
2932 | * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a | |
2933 | * period of 2). This is a helper function for nand_id_len(). Returns non-zero | |
2934 | * if the repetition has a period of @period; otherwise, returns zero. | |
2935 | */ | |
2936 | static int nand_id_has_period(u8 *id_data, int arrlen, int period) | |
2937 | { | |
2938 | int i, j; | |
2939 | for (i = 0; i < period; i++) | |
2940 | for (j = i + period; j < arrlen; j += period) | |
2941 | if (id_data[i] != id_data[j]) | |
2942 | return 0; | |
2943 | return 1; | |
2944 | } | |
2945 | ||
2946 | /* | |
2947 | * nand_id_len - Get the length of an ID string returned by CMD_READID | |
2948 | * @id_data: the ID string | |
2949 | * @arrlen: the length of the @id_data array | |
2950 | ||
2951 | * Returns the length of the ID string, according to known wraparound/trailing | |
2952 | * zero patterns. If no pattern exists, returns the length of the array. | |
2953 | */ | |
2954 | static int nand_id_len(u8 *id_data, int arrlen) | |
2955 | { | |
2956 | int last_nonzero, period; | |
2957 | ||
2958 | /* Find last non-zero byte */ | |
2959 | for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) | |
2960 | if (id_data[last_nonzero]) | |
2961 | break; | |
2962 | ||
2963 | /* All zeros */ | |
2964 | if (last_nonzero < 0) | |
2965 | return 0; | |
2966 | ||
2967 | /* Calculate wraparound period */ | |
2968 | for (period = 1; period < arrlen; period++) | |
2969 | if (nand_id_has_period(id_data, arrlen, period)) | |
2970 | break; | |
2971 | ||
2972 | /* There's a repeated pattern */ | |
2973 | if (period < arrlen) | |
2974 | return period; | |
2975 | ||
2976 | /* There are trailing zeros */ | |
2977 | if (last_nonzero < arrlen - 1) | |
2978 | return last_nonzero + 1; | |
2979 | ||
2980 | /* No pattern detected */ | |
2981 | return arrlen; | |
2982 | } | |
2983 | ||
fc09bbc0 BN |
2984 | /* |
2985 | * Many new NAND share similar device ID codes, which represent the size of the | |
2986 | * chip. The rest of the parameters must be decoded according to generic or | |
2987 | * manufacturer-specific "extended ID" decoding patterns. | |
2988 | */ | |
2989 | static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, | |
2990 | u8 id_data[8], int *busw) | |
2991 | { | |
e3b88bd6 | 2992 | int extid, id_len; |
fc09bbc0 BN |
2993 | /* The 3rd id byte holds MLC / multichip data */ |
2994 | chip->cellinfo = id_data[2]; | |
2995 | /* The 4th id byte is the important one */ | |
2996 | extid = id_data[3]; | |
2997 | ||
e3b88bd6 BN |
2998 | id_len = nand_id_len(id_data, 8); |
2999 | ||
fc09bbc0 BN |
3000 | /* |
3001 | * Field definitions are in the following datasheets: | |
3002 | * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) | |
af451af4 | 3003 | * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) |
73ca392f | 3004 | * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) |
fc09bbc0 | 3005 | * |
af451af4 BN |
3006 | * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung |
3007 | * ID to decide what to do. | |
fc09bbc0 | 3008 | */ |
af451af4 | 3009 | if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && |
6924d99f | 3010 | (chip->cellinfo & NAND_CI_CELLTYPE_MSK) && |
af451af4 | 3011 | id_data[5] != 0x00) { |
fc09bbc0 BN |
3012 | /* Calc pagesize */ |
3013 | mtd->writesize = 2048 << (extid & 0x03); | |
3014 | extid >>= 2; | |
3015 | /* Calc oobsize */ | |
e2d3a35e | 3016 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { |
fc09bbc0 BN |
3017 | case 1: |
3018 | mtd->oobsize = 128; | |
3019 | break; | |
3020 | case 2: | |
3021 | mtd->oobsize = 218; | |
3022 | break; | |
3023 | case 3: | |
3024 | mtd->oobsize = 400; | |
3025 | break; | |
e2d3a35e | 3026 | case 4: |
fc09bbc0 BN |
3027 | mtd->oobsize = 436; |
3028 | break; | |
e2d3a35e BN |
3029 | case 5: |
3030 | mtd->oobsize = 512; | |
3031 | break; | |
3032 | case 6: | |
3033 | default: /* Other cases are "reserved" (unknown) */ | |
3034 | mtd->oobsize = 640; | |
3035 | break; | |
fc09bbc0 BN |
3036 | } |
3037 | extid >>= 2; | |
3038 | /* Calc blocksize */ | |
3039 | mtd->erasesize = (128 * 1024) << | |
3040 | (((extid >> 1) & 0x04) | (extid & 0x03)); | |
3041 | *busw = 0; | |
73ca392f BN |
3042 | } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && |
3043 | (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { | |
3044 | unsigned int tmp; | |
3045 | ||
3046 | /* Calc pagesize */ | |
3047 | mtd->writesize = 2048 << (extid & 0x03); | |
3048 | extid >>= 2; | |
3049 | /* Calc oobsize */ | |
3050 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { | |
3051 | case 0: | |
3052 | mtd->oobsize = 128; | |
3053 | break; | |
3054 | case 1: | |
3055 | mtd->oobsize = 224; | |
3056 | break; | |
3057 | case 2: | |
3058 | mtd->oobsize = 448; | |
3059 | break; | |
3060 | case 3: | |
3061 | mtd->oobsize = 64; | |
3062 | break; | |
3063 | case 4: | |
3064 | mtd->oobsize = 32; | |
3065 | break; | |
3066 | case 5: | |
3067 | mtd->oobsize = 16; | |
3068 | break; | |
3069 | default: | |
3070 | mtd->oobsize = 640; | |
3071 | break; | |
3072 | } | |
3073 | extid >>= 2; | |
3074 | /* Calc blocksize */ | |
3075 | tmp = ((extid >> 1) & 0x04) | (extid & 0x03); | |
3076 | if (tmp < 0x03) | |
3077 | mtd->erasesize = (128 * 1024) << tmp; | |
3078 | else if (tmp == 0x03) | |
3079 | mtd->erasesize = 768 * 1024; | |
3080 | else | |
3081 | mtd->erasesize = (64 * 1024) << tmp; | |
3082 | *busw = 0; | |
fc09bbc0 BN |
3083 | } else { |
3084 | /* Calc pagesize */ | |
3085 | mtd->writesize = 1024 << (extid & 0x03); | |
3086 | extid >>= 2; | |
3087 | /* Calc oobsize */ | |
3088 | mtd->oobsize = (8 << (extid & 0x01)) * | |
3089 | (mtd->writesize >> 9); | |
3090 | extid >>= 2; | |
3091 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
3092 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
3093 | extid >>= 2; | |
3094 | /* Get buswidth information */ | |
3095 | *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
3096 | } | |
3097 | } | |
3098 | ||
f23a481c BN |
3099 | /* |
3100 | * Old devices have chip data hardcoded in the device ID table. nand_decode_id | |
3101 | * decodes a matching ID table entry and assigns the MTD size parameters for | |
3102 | * the chip. | |
3103 | */ | |
3104 | static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, | |
3105 | struct nand_flash_dev *type, u8 id_data[8], | |
3106 | int *busw) | |
3107 | { | |
3108 | int maf_id = id_data[0]; | |
3109 | ||
3110 | mtd->erasesize = type->erasesize; | |
3111 | mtd->writesize = type->pagesize; | |
3112 | mtd->oobsize = mtd->writesize / 32; | |
3113 | *busw = type->options & NAND_BUSWIDTH_16; | |
3114 | ||
3115 | /* | |
3116 | * Check for Spansion/AMD ID + repeating 5th, 6th byte since | |
3117 | * some Spansion chips have erasesize that conflicts with size | |
3118 | * listed in nand_ids table. | |
3119 | * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) | |
3120 | */ | |
3121 | if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00 | |
3122 | && id_data[6] == 0x00 && id_data[7] == 0x00 | |
3123 | && mtd->writesize == 512) { | |
3124 | mtd->erasesize = 128 * 1024; | |
3125 | mtd->erasesize <<= ((id_data[3] & 0x03) << 1); | |
3126 | } | |
3127 | } | |
3128 | ||
7e74c2d7 BN |
3129 | /* |
3130 | * Set the bad block marker/indicator (BBM/BBI) patterns according to some | |
3131 | * heuristic patterns using various detected parameters (e.g., manufacturer, | |
3132 | * page size, cell-type information). | |
3133 | */ | |
3134 | static void nand_decode_bbm_options(struct mtd_info *mtd, | |
3135 | struct nand_chip *chip, u8 id_data[8]) | |
3136 | { | |
3137 | int maf_id = id_data[0]; | |
3138 | ||
3139 | /* Set the bad block position */ | |
3140 | if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) | |
3141 | chip->badblockpos = NAND_LARGE_BADBLOCK_POS; | |
3142 | else | |
3143 | chip->badblockpos = NAND_SMALL_BADBLOCK_POS; | |
3144 | ||
3145 | /* | |
3146 | * Bad block marker is stored in the last page of each block on Samsung | |
3147 | * and Hynix MLC devices; stored in first two pages of each block on | |
3148 | * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, | |
3149 | * AMD/Spansion, and Macronix. All others scan only the first page. | |
3150 | */ | |
3151 | if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) && | |
3152 | (maf_id == NAND_MFR_SAMSUNG || | |
3153 | maf_id == NAND_MFR_HYNIX)) | |
3154 | chip->bbt_options |= NAND_BBT_SCANLASTPAGE; | |
3155 | else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) && | |
3156 | (maf_id == NAND_MFR_SAMSUNG || | |
3157 | maf_id == NAND_MFR_HYNIX || | |
3158 | maf_id == NAND_MFR_TOSHIBA || | |
3159 | maf_id == NAND_MFR_AMD || | |
3160 | maf_id == NAND_MFR_MACRONIX)) || | |
3161 | (mtd->writesize == 2048 && | |
3162 | maf_id == NAND_MFR_MICRON)) | |
3163 | chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; | |
3164 | } | |
3165 | ||
7aa65bfd | 3166 | /* |
8b6e50c9 | 3167 | * Get the flash and manufacturer id and lookup if the type is supported. |
7aa65bfd TG |
3168 | */ |
3169 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 3170 | struct nand_chip *chip, |
7351d3a5 FF |
3171 | int busw, |
3172 | int *maf_id, int *dev_id, | |
5e81e88a | 3173 | struct nand_flash_dev *type) |
7aa65bfd | 3174 | { |
d1e1f4e4 | 3175 | int i, maf_idx; |
426c457a | 3176 | u8 id_data[8]; |
1da177e4 LT |
3177 | |
3178 | /* Select the device */ | |
ace4dfee | 3179 | chip->select_chip(mtd, 0); |
1da177e4 | 3180 | |
ef89a880 KB |
3181 | /* |
3182 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
8b6e50c9 | 3183 | * after power-up. |
ef89a880 KB |
3184 | */ |
3185 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
3186 | ||
1da177e4 | 3187 | /* Send the command for reading device ID */ |
ace4dfee | 3188 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
3189 | |
3190 | /* Read manufacturer and device IDs */ | |
ace4dfee | 3191 | *maf_id = chip->read_byte(mtd); |
d1e1f4e4 | 3192 | *dev_id = chip->read_byte(mtd); |
1da177e4 | 3193 | |
8b6e50c9 BN |
3194 | /* |
3195 | * Try again to make sure, as some systems the bus-hold or other | |
ed8165c7 BD |
3196 | * interface concerns can cause random data which looks like a |
3197 | * possibly credible NAND flash to appear. If the two results do | |
3198 | * not match, ignore the device completely. | |
3199 | */ | |
3200 | ||
3201 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
3202 | ||
4aef9b78 BN |
3203 | /* Read entire ID string */ |
3204 | for (i = 0; i < 8; i++) | |
426c457a | 3205 | id_data[i] = chip->read_byte(mtd); |
ed8165c7 | 3206 | |
d1e1f4e4 | 3207 | if (id_data[0] != *maf_id || id_data[1] != *dev_id) { |
9a4d4d69 | 3208 | pr_info("%s: second ID read did not match " |
d0370219 BN |
3209 | "%02x,%02x against %02x,%02x\n", __func__, |
3210 | *maf_id, *dev_id, id_data[0], id_data[1]); | |
ed8165c7 BD |
3211 | return ERR_PTR(-ENODEV); |
3212 | } | |
3213 | ||
7aa65bfd | 3214 | if (!type) |
5e81e88a DW |
3215 | type = nand_flash_ids; |
3216 | ||
3217 | for (; type->name != NULL; type++) | |
d1e1f4e4 | 3218 | if (*dev_id == type->id) |
f8ac0414 | 3219 | break; |
5e81e88a | 3220 | |
d1e1f4e4 FF |
3221 | chip->onfi_version = 0; |
3222 | if (!type->name || !type->pagesize) { | |
6fb277ba | 3223 | /* Check is chip is ONFI compliant */ |
47450b35 | 3224 | if (nand_flash_detect_onfi(mtd, chip, &busw)) |
6fb277ba | 3225 | goto ident_done; |
d1e1f4e4 FF |
3226 | } |
3227 | ||
5e81e88a | 3228 | if (!type->name) |
7aa65bfd TG |
3229 | return ERR_PTR(-ENODEV); |
3230 | ||
ba0251fe TG |
3231 | if (!mtd->name) |
3232 | mtd->name = type->name; | |
3233 | ||
69423d99 | 3234 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd | 3235 | |
12a40a57 | 3236 | if (!type->pagesize && chip->init_size) { |
8b6e50c9 | 3237 | /* Set the pagesize, oobsize, erasesize by the driver */ |
12a40a57 HS |
3238 | busw = chip->init_size(mtd, chip, id_data); |
3239 | } else if (!type->pagesize) { | |
fc09bbc0 BN |
3240 | /* Decode parameters from extended ID */ |
3241 | nand_decode_ext_id(mtd, chip, id_data, &busw); | |
7aa65bfd | 3242 | } else { |
f23a481c | 3243 | nand_decode_id(mtd, chip, type, id_data, &busw); |
7aa65bfd | 3244 | } |
bf7a01bf BN |
3245 | /* Get chip options */ |
3246 | chip->options |= type->options; | |
d1e1f4e4 | 3247 | |
8b6e50c9 BN |
3248 | /* |
3249 | * Check if chip is not a Samsung device. Do not clear the | |
3250 | * options for chips which do not have an extended id. | |
d1e1f4e4 FF |
3251 | */ |
3252 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) | |
3253 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; | |
3254 | ident_done: | |
3255 | ||
7aa65bfd | 3256 | /* Try to identify manufacturer */ |
9a909867 | 3257 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { |
7aa65bfd TG |
3258 | if (nand_manuf_ids[maf_idx].id == *maf_id) |
3259 | break; | |
3260 | } | |
0ea4a755 | 3261 | |
7aa65bfd TG |
3262 | /* |
3263 | * Check, if buswidth is correct. Hardware drivers should set | |
8b6e50c9 | 3264 | * chip correct! |
7aa65bfd | 3265 | */ |
ace4dfee | 3266 | if (busw != (chip->options & NAND_BUSWIDTH_16)) { |
9a4d4d69 | 3267 | pr_info("NAND device: Manufacturer ID:" |
d0370219 BN |
3268 | " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, |
3269 | *dev_id, nand_manuf_ids[maf_idx].name, mtd->name); | |
9a4d4d69 | 3270 | pr_warn("NAND bus width %d instead %d bit\n", |
d0370219 BN |
3271 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
3272 | busw ? 16 : 8); | |
7aa65bfd TG |
3273 | return ERR_PTR(-EINVAL); |
3274 | } | |
61b03bd7 | 3275 | |
7e74c2d7 BN |
3276 | nand_decode_bbm_options(mtd, chip, id_data); |
3277 | ||
7aa65bfd | 3278 | /* Calculate the address shift from the page size */ |
ace4dfee | 3279 | chip->page_shift = ffs(mtd->writesize) - 1; |
8b6e50c9 | 3280 | /* Convert chipsize to number of pages per chip -1 */ |
ace4dfee | 3281 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 3282 | |
ace4dfee | 3283 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 3284 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
3285 | if (chip->chipsize & 0xffffffff) |
3286 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
7351d3a5 FF |
3287 | else { |
3288 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); | |
3289 | chip->chip_shift += 32 - 1; | |
3290 | } | |
1da177e4 | 3291 | |
26d9be11 AB |
3292 | chip->badblockbits = 8; |
3293 | ||
7aa65bfd | 3294 | /* Check for AND chips with 4 page planes */ |
ace4dfee TG |
3295 | if (chip->options & NAND_4PAGE_ARRAY) |
3296 | chip->erase_cmd = multi_erase_cmd; | |
7aa65bfd | 3297 | else |
ace4dfee | 3298 | chip->erase_cmd = single_erase_cmd; |
7aa65bfd | 3299 | |
8b6e50c9 | 3300 | /* Do not replace user supplied command function! */ |
ace4dfee TG |
3301 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
3302 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd | 3303 | |
886bd33d HS |
3304 | pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s)," |
3305 | " page size: %d, OOB size: %d\n", | |
3306 | *maf_id, *dev_id, nand_manuf_ids[maf_idx].name, | |
3307 | chip->onfi_version ? chip->onfi_params.model : type->name, | |
3308 | mtd->writesize, mtd->oobsize); | |
7aa65bfd TG |
3309 | |
3310 | return type; | |
3311 | } | |
3312 | ||
7aa65bfd | 3313 | /** |
3b85c321 | 3314 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
8b6e50c9 BN |
3315 | * @mtd: MTD device structure |
3316 | * @maxchips: number of chips to scan for | |
3317 | * @table: alternative NAND ID table | |
7aa65bfd | 3318 | * |
8b6e50c9 BN |
3319 | * This is the first phase of the normal nand_scan() function. It reads the |
3320 | * flash ID and sets up MTD fields accordingly. | |
7aa65bfd | 3321 | * |
3b85c321 | 3322 | * The mtd->owner field must be set to the module of the caller. |
7aa65bfd | 3323 | */ |
5e81e88a DW |
3324 | int nand_scan_ident(struct mtd_info *mtd, int maxchips, |
3325 | struct nand_flash_dev *table) | |
7aa65bfd | 3326 | { |
d1e1f4e4 | 3327 | int i, busw, nand_maf_id, nand_dev_id; |
ace4dfee | 3328 | struct nand_chip *chip = mtd->priv; |
7aa65bfd TG |
3329 | struct nand_flash_dev *type; |
3330 | ||
7aa65bfd | 3331 | /* Get buswidth to select the correct functions */ |
ace4dfee | 3332 | busw = chip->options & NAND_BUSWIDTH_16; |
7aa65bfd | 3333 | /* Set the default functions */ |
ace4dfee | 3334 | nand_set_defaults(chip, busw); |
7aa65bfd TG |
3335 | |
3336 | /* Read the flash type */ | |
7351d3a5 FF |
3337 | type = nand_get_flash_type(mtd, chip, busw, |
3338 | &nand_maf_id, &nand_dev_id, table); | |
7aa65bfd TG |
3339 | |
3340 | if (IS_ERR(type)) { | |
b1c6e6db | 3341 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
d0370219 | 3342 | pr_warn("No NAND device found\n"); |
ace4dfee | 3343 | chip->select_chip(mtd, -1); |
7aa65bfd | 3344 | return PTR_ERR(type); |
1da177e4 LT |
3345 | } |
3346 | ||
07300164 HS |
3347 | chip->select_chip(mtd, -1); |
3348 | ||
7aa65bfd | 3349 | /* Check for a chip array */ |
e0c7d767 | 3350 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 3351 | chip->select_chip(mtd, i); |
ef89a880 KB |
3352 | /* See comment in nand_get_flash_type for reset */ |
3353 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1da177e4 | 3354 | /* Send the command for reading device ID */ |
ace4dfee | 3355 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 3356 | /* Read manufacturer and device IDs */ |
ace4dfee | 3357 | if (nand_maf_id != chip->read_byte(mtd) || |
07300164 HS |
3358 | nand_dev_id != chip->read_byte(mtd)) { |
3359 | chip->select_chip(mtd, -1); | |
1da177e4 | 3360 | break; |
07300164 HS |
3361 | } |
3362 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
3363 | } |
3364 | if (i > 1) | |
9a4d4d69 | 3365 | pr_info("%d NAND chips detected\n", i); |
61b03bd7 | 3366 | |
1da177e4 | 3367 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
3368 | chip->numchips = i; |
3369 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 3370 | |
3b85c321 DW |
3371 | return 0; |
3372 | } | |
7351d3a5 | 3373 | EXPORT_SYMBOL(nand_scan_ident); |
3b85c321 DW |
3374 | |
3375 | ||
3376 | /** | |
3377 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
8b6e50c9 | 3378 | * @mtd: MTD device structure |
3b85c321 | 3379 | * |
8b6e50c9 BN |
3380 | * This is the second phase of the normal nand_scan() function. It fills out |
3381 | * all the uninitialized function pointers with the defaults and scans for a | |
3382 | * bad block table if appropriate. | |
3b85c321 DW |
3383 | */ |
3384 | int nand_scan_tail(struct mtd_info *mtd) | |
3385 | { | |
3386 | int i; | |
3387 | struct nand_chip *chip = mtd->priv; | |
3388 | ||
e2414f4c BN |
3389 | /* New bad blocks should be marked in OOB, flash-based BBT, or both */ |
3390 | BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && | |
3391 | !(chip->bbt_options & NAND_BBT_USE_FLASH)); | |
3392 | ||
4bf63fcb DW |
3393 | if (!(chip->options & NAND_OWN_BUFFERS)) |
3394 | chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); | |
3395 | if (!chip->buffers) | |
3396 | return -ENOMEM; | |
3397 | ||
7dcdcbef | 3398 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 3399 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 3400 | |
7aa65bfd | 3401 | /* |
8b6e50c9 | 3402 | * If no default placement scheme is given, select an appropriate one. |
7aa65bfd | 3403 | */ |
193bd400 | 3404 | if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) { |
61b03bd7 | 3405 | switch (mtd->oobsize) { |
1da177e4 | 3406 | case 8: |
5bd34c09 | 3407 | chip->ecc.layout = &nand_oob_8; |
1da177e4 LT |
3408 | break; |
3409 | case 16: | |
5bd34c09 | 3410 | chip->ecc.layout = &nand_oob_16; |
1da177e4 LT |
3411 | break; |
3412 | case 64: | |
5bd34c09 | 3413 | chip->ecc.layout = &nand_oob_64; |
1da177e4 | 3414 | break; |
81ec5364 TG |
3415 | case 128: |
3416 | chip->ecc.layout = &nand_oob_128; | |
3417 | break; | |
1da177e4 | 3418 | default: |
d0370219 BN |
3419 | pr_warn("No oob scheme defined for oobsize %d\n", |
3420 | mtd->oobsize); | |
1da177e4 LT |
3421 | BUG(); |
3422 | } | |
3423 | } | |
61b03bd7 | 3424 | |
956e944c DW |
3425 | if (!chip->write_page) |
3426 | chip->write_page = nand_write_page; | |
3427 | ||
7db03ecc HS |
3428 | /* set for ONFI nand */ |
3429 | if (!chip->onfi_set_features) | |
3430 | chip->onfi_set_features = nand_onfi_set_features; | |
3431 | if (!chip->onfi_get_features) | |
3432 | chip->onfi_get_features = nand_onfi_get_features; | |
3433 | ||
61b03bd7 | 3434 | /* |
8b6e50c9 | 3435 | * Check ECC mode, default to software if 3byte/512byte hardware ECC is |
7aa65bfd | 3436 | * selected and we have 256 byte pagesize fallback to software ECC |
e0c7d767 | 3437 | */ |
956e944c | 3438 | |
ace4dfee | 3439 | switch (chip->ecc.mode) { |
6e0cb135 SN |
3440 | case NAND_ECC_HW_OOB_FIRST: |
3441 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
3442 | if (!chip->ecc.calculate || !chip->ecc.correct || | |
3443 | !chip->ecc.hwctl) { | |
9a4d4d69 | 3444 | pr_warn("No ECC functions supplied; " |
d0370219 | 3445 | "hardware ECC not possible\n"); |
6e0cb135 SN |
3446 | BUG(); |
3447 | } | |
3448 | if (!chip->ecc.read_page) | |
3449 | chip->ecc.read_page = nand_read_page_hwecc_oob_first; | |
3450 | ||
6dfc6d25 | 3451 | case NAND_ECC_HW: |
8b6e50c9 | 3452 | /* Use standard hwecc read page function? */ |
f5bbdacc TG |
3453 | if (!chip->ecc.read_page) |
3454 | chip->ecc.read_page = nand_read_page_hwecc; | |
f75e5097 TG |
3455 | if (!chip->ecc.write_page) |
3456 | chip->ecc.write_page = nand_write_page_hwecc; | |
52ff49df DB |
3457 | if (!chip->ecc.read_page_raw) |
3458 | chip->ecc.read_page_raw = nand_read_page_raw; | |
3459 | if (!chip->ecc.write_page_raw) | |
3460 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b TG |
3461 | if (!chip->ecc.read_oob) |
3462 | chip->ecc.read_oob = nand_read_oob_std; | |
3463 | if (!chip->ecc.write_oob) | |
3464 | chip->ecc.write_oob = nand_write_oob_std; | |
f5bbdacc | 3465 | |
6dfc6d25 | 3466 | case NAND_ECC_HW_SYNDROME: |
78b65179 SW |
3467 | if ((!chip->ecc.calculate || !chip->ecc.correct || |
3468 | !chip->ecc.hwctl) && | |
3469 | (!chip->ecc.read_page || | |
1c45f604 | 3470 | chip->ecc.read_page == nand_read_page_hwecc || |
78b65179 | 3471 | !chip->ecc.write_page || |
1c45f604 | 3472 | chip->ecc.write_page == nand_write_page_hwecc)) { |
9a4d4d69 | 3473 | pr_warn("No ECC functions supplied; " |
d0370219 | 3474 | "hardware ECC not possible\n"); |
6dfc6d25 TG |
3475 | BUG(); |
3476 | } | |
8b6e50c9 | 3477 | /* Use standard syndrome read/write page function? */ |
f5bbdacc TG |
3478 | if (!chip->ecc.read_page) |
3479 | chip->ecc.read_page = nand_read_page_syndrome; | |
f75e5097 TG |
3480 | if (!chip->ecc.write_page) |
3481 | chip->ecc.write_page = nand_write_page_syndrome; | |
52ff49df DB |
3482 | if (!chip->ecc.read_page_raw) |
3483 | chip->ecc.read_page_raw = nand_read_page_raw_syndrome; | |
3484 | if (!chip->ecc.write_page_raw) | |
3485 | chip->ecc.write_page_raw = nand_write_page_raw_syndrome; | |
7bc3312b TG |
3486 | if (!chip->ecc.read_oob) |
3487 | chip->ecc.read_oob = nand_read_oob_syndrome; | |
3488 | if (!chip->ecc.write_oob) | |
3489 | chip->ecc.write_oob = nand_write_oob_syndrome; | |
f5bbdacc | 3490 | |
e2788c98 MD |
3491 | if (mtd->writesize >= chip->ecc.size) { |
3492 | if (!chip->ecc.strength) { | |
3493 | pr_warn("Driver must set ecc.strength when using hardware ECC\n"); | |
3494 | BUG(); | |
3495 | } | |
6dfc6d25 | 3496 | break; |
e2788c98 | 3497 | } |
9a4d4d69 | 3498 | pr_warn("%d byte HW ECC not possible on " |
d0370219 BN |
3499 | "%d byte page size, fallback to SW ECC\n", |
3500 | chip->ecc.size, mtd->writesize); | |
ace4dfee | 3501 | chip->ecc.mode = NAND_ECC_SOFT; |
61b03bd7 | 3502 | |
6dfc6d25 | 3503 | case NAND_ECC_SOFT: |
ace4dfee TG |
3504 | chip->ecc.calculate = nand_calculate_ecc; |
3505 | chip->ecc.correct = nand_correct_data; | |
f5bbdacc | 3506 | chip->ecc.read_page = nand_read_page_swecc; |
3d459559 | 3507 | chip->ecc.read_subpage = nand_read_subpage; |
f75e5097 | 3508 | chip->ecc.write_page = nand_write_page_swecc; |
52ff49df DB |
3509 | chip->ecc.read_page_raw = nand_read_page_raw; |
3510 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b TG |
3511 | chip->ecc.read_oob = nand_read_oob_std; |
3512 | chip->ecc.write_oob = nand_write_oob_std; | |
9a73290d SV |
3513 | if (!chip->ecc.size) |
3514 | chip->ecc.size = 256; | |
ace4dfee | 3515 | chip->ecc.bytes = 3; |
6a918bad | 3516 | chip->ecc.strength = 1; |
1da177e4 | 3517 | break; |
61b03bd7 | 3518 | |
193bd400 ID |
3519 | case NAND_ECC_SOFT_BCH: |
3520 | if (!mtd_nand_has_bch()) { | |
9a4d4d69 | 3521 | pr_warn("CONFIG_MTD_ECC_BCH not enabled\n"); |
193bd400 ID |
3522 | BUG(); |
3523 | } | |
3524 | chip->ecc.calculate = nand_bch_calculate_ecc; | |
3525 | chip->ecc.correct = nand_bch_correct_data; | |
3526 | chip->ecc.read_page = nand_read_page_swecc; | |
3527 | chip->ecc.read_subpage = nand_read_subpage; | |
3528 | chip->ecc.write_page = nand_write_page_swecc; | |
3529 | chip->ecc.read_page_raw = nand_read_page_raw; | |
3530 | chip->ecc.write_page_raw = nand_write_page_raw; | |
3531 | chip->ecc.read_oob = nand_read_oob_std; | |
3532 | chip->ecc.write_oob = nand_write_oob_std; | |
3533 | /* | |
3534 | * Board driver should supply ecc.size and ecc.bytes values to | |
3535 | * select how many bits are correctable; see nand_bch_init() | |
8b6e50c9 BN |
3536 | * for details. Otherwise, default to 4 bits for large page |
3537 | * devices. | |
193bd400 ID |
3538 | */ |
3539 | if (!chip->ecc.size && (mtd->oobsize >= 64)) { | |
3540 | chip->ecc.size = 512; | |
3541 | chip->ecc.bytes = 7; | |
3542 | } | |
3543 | chip->ecc.priv = nand_bch_init(mtd, | |
3544 | chip->ecc.size, | |
3545 | chip->ecc.bytes, | |
3546 | &chip->ecc.layout); | |
3547 | if (!chip->ecc.priv) { | |
9a4d4d69 | 3548 | pr_warn("BCH ECC initialization failed!\n"); |
193bd400 ID |
3549 | BUG(); |
3550 | } | |
6a918bad | 3551 | chip->ecc.strength = |
e2788c98 | 3552 | chip->ecc.bytes * 8 / fls(8 * chip->ecc.size); |
193bd400 ID |
3553 | break; |
3554 | ||
61b03bd7 | 3555 | case NAND_ECC_NONE: |
9a4d4d69 | 3556 | pr_warn("NAND_ECC_NONE selected by board driver. " |
d0370219 | 3557 | "This is not recommended!\n"); |
8593fbc6 TG |
3558 | chip->ecc.read_page = nand_read_page_raw; |
3559 | chip->ecc.write_page = nand_write_page_raw; | |
7bc3312b | 3560 | chip->ecc.read_oob = nand_read_oob_std; |
52ff49df DB |
3561 | chip->ecc.read_page_raw = nand_read_page_raw; |
3562 | chip->ecc.write_page_raw = nand_write_page_raw; | |
7bc3312b | 3563 | chip->ecc.write_oob = nand_write_oob_std; |
ace4dfee TG |
3564 | chip->ecc.size = mtd->writesize; |
3565 | chip->ecc.bytes = 0; | |
6a918bad | 3566 | chip->ecc.strength = 0; |
1da177e4 | 3567 | break; |
956e944c | 3568 | |
1da177e4 | 3569 | default: |
d0370219 | 3570 | pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode); |
61b03bd7 | 3571 | BUG(); |
1da177e4 | 3572 | } |
61b03bd7 | 3573 | |
9ce244b3 | 3574 | /* For many systems, the standard OOB write also works for raw */ |
c46f6483 BN |
3575 | if (!chip->ecc.read_oob_raw) |
3576 | chip->ecc.read_oob_raw = chip->ecc.read_oob; | |
9ce244b3 BN |
3577 | if (!chip->ecc.write_oob_raw) |
3578 | chip->ecc.write_oob_raw = chip->ecc.write_oob; | |
3579 | ||
5bd34c09 TG |
3580 | /* |
3581 | * The number of bytes available for a client to place data into | |
8b6e50c9 | 3582 | * the out of band area. |
5bd34c09 TG |
3583 | */ |
3584 | chip->ecc.layout->oobavail = 0; | |
81d19b04 DB |
3585 | for (i = 0; chip->ecc.layout->oobfree[i].length |
3586 | && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++) | |
5bd34c09 TG |
3587 | chip->ecc.layout->oobavail += |
3588 | chip->ecc.layout->oobfree[i].length; | |
1f92267c | 3589 | mtd->oobavail = chip->ecc.layout->oobavail; |
5bd34c09 | 3590 | |
7aa65bfd TG |
3591 | /* |
3592 | * Set the number of read / write steps for one page depending on ECC | |
8b6e50c9 | 3593 | * mode. |
7aa65bfd | 3594 | */ |
ace4dfee | 3595 | chip->ecc.steps = mtd->writesize / chip->ecc.size; |
f8ac0414 | 3596 | if (chip->ecc.steps * chip->ecc.size != mtd->writesize) { |
9a4d4d69 | 3597 | pr_warn("Invalid ECC parameters\n"); |
6dfc6d25 | 3598 | BUG(); |
1da177e4 | 3599 | } |
f5bbdacc | 3600 | chip->ecc.total = chip->ecc.steps * chip->ecc.bytes; |
61b03bd7 | 3601 | |
8b6e50c9 | 3602 | /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ |
29072b96 TG |
3603 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && |
3604 | !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) { | |
f8ac0414 | 3605 | switch (chip->ecc.steps) { |
29072b96 TG |
3606 | case 2: |
3607 | mtd->subpage_sft = 1; | |
3608 | break; | |
3609 | case 4: | |
3610 | case 8: | |
81ec5364 | 3611 | case 16: |
29072b96 TG |
3612 | mtd->subpage_sft = 2; |
3613 | break; | |
3614 | } | |
3615 | } | |
3616 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
3617 | ||
04bbd0ea | 3618 | /* Initialize state */ |
ace4dfee | 3619 | chip->state = FL_READY; |
1da177e4 | 3620 | |
1da177e4 | 3621 | /* Invalidate the pagebuffer reference */ |
ace4dfee | 3622 | chip->pagebuf = -1; |
1da177e4 | 3623 | |
a5ff4f10 JW |
3624 | /* Large page NAND with SOFT_ECC should support subpage reads */ |
3625 | if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9)) | |
3626 | chip->options |= NAND_SUBPAGE_READ; | |
3627 | ||
1da177e4 LT |
3628 | /* Fill in remaining MTD driver data */ |
3629 | mtd->type = MTD_NANDFLASH; | |
93edbad6 ML |
3630 | mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : |
3631 | MTD_CAP_NANDFLASH; | |
3c3c10bb AB |
3632 | mtd->_erase = nand_erase; |
3633 | mtd->_point = NULL; | |
3634 | mtd->_unpoint = NULL; | |
3635 | mtd->_read = nand_read; | |
3636 | mtd->_write = nand_write; | |
3637 | mtd->_panic_write = panic_nand_write; | |
3638 | mtd->_read_oob = nand_read_oob; | |
3639 | mtd->_write_oob = nand_write_oob; | |
3640 | mtd->_sync = nand_sync; | |
3641 | mtd->_lock = NULL; | |
3642 | mtd->_unlock = NULL; | |
3643 | mtd->_suspend = nand_suspend; | |
3644 | mtd->_resume = nand_resume; | |
3645 | mtd->_block_isbad = nand_block_isbad; | |
3646 | mtd->_block_markbad = nand_block_markbad; | |
cbcab65a | 3647 | mtd->writebufsize = mtd->writesize; |
1da177e4 | 3648 | |
6a918bad | 3649 | /* propagate ecc info to mtd_info */ |
5bd34c09 | 3650 | mtd->ecclayout = chip->ecc.layout; |
86c2072b | 3651 | mtd->ecc_strength = chip->ecc.strength; |
ea3b2ea2 SL |
3652 | /* |
3653 | * Initialize bitflip_threshold to its default prior scan_bbt() call. | |
3654 | * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be | |
3655 | * properly set. | |
3656 | */ | |
3657 | if (!mtd->bitflip_threshold) | |
3658 | mtd->bitflip_threshold = mtd->ecc_strength; | |
1da177e4 | 3659 | |
0040bf38 | 3660 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 3661 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 3662 | return 0; |
1da177e4 LT |
3663 | |
3664 | /* Build bad block table */ | |
ace4dfee | 3665 | return chip->scan_bbt(mtd); |
1da177e4 | 3666 | } |
7351d3a5 | 3667 | EXPORT_SYMBOL(nand_scan_tail); |
1da177e4 | 3668 | |
8b6e50c9 BN |
3669 | /* |
3670 | * is_module_text_address() isn't exported, and it's mostly a pointless | |
7351d3a5 | 3671 | * test if this is a module _anyway_ -- they'd have to try _really_ hard |
8b6e50c9 BN |
3672 | * to call us from in-kernel code if the core NAND support is modular. |
3673 | */ | |
3b85c321 DW |
3674 | #ifdef MODULE |
3675 | #define caller_is_module() (1) | |
3676 | #else | |
3677 | #define caller_is_module() \ | |
a6e6abd5 | 3678 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
3679 | #endif |
3680 | ||
3681 | /** | |
3682 | * nand_scan - [NAND Interface] Scan for the NAND device | |
8b6e50c9 BN |
3683 | * @mtd: MTD device structure |
3684 | * @maxchips: number of chips to scan for | |
3b85c321 | 3685 | * |
8b6e50c9 BN |
3686 | * This fills out all the uninitialized function pointers with the defaults. |
3687 | * The flash ID is read and the mtd/chip structures are filled with the | |
3688 | * appropriate values. The mtd->owner field must be set to the module of the | |
3689 | * caller. | |
3b85c321 DW |
3690 | */ |
3691 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
3692 | { | |
3693 | int ret; | |
3694 | ||
3695 | /* Many callers got this wrong, so check for it for a while... */ | |
3696 | if (!mtd->owner && caller_is_module()) { | |
d0370219 | 3697 | pr_crit("%s called with NULL mtd->owner!\n", __func__); |
3b85c321 DW |
3698 | BUG(); |
3699 | } | |
3700 | ||
5e81e88a | 3701 | ret = nand_scan_ident(mtd, maxchips, NULL); |
3b85c321 DW |
3702 | if (!ret) |
3703 | ret = nand_scan_tail(mtd); | |
3704 | return ret; | |
3705 | } | |
7351d3a5 | 3706 | EXPORT_SYMBOL(nand_scan); |
3b85c321 | 3707 | |
1da177e4 | 3708 | /** |
61b03bd7 | 3709 | * nand_release - [NAND Interface] Free resources held by the NAND device |
8b6e50c9 BN |
3710 | * @mtd: MTD device structure |
3711 | */ | |
e0c7d767 | 3712 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 3713 | { |
ace4dfee | 3714 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 3715 | |
193bd400 ID |
3716 | if (chip->ecc.mode == NAND_ECC_SOFT_BCH) |
3717 | nand_bch_free((struct nand_bch_control *)chip->ecc.priv); | |
3718 | ||
5ffcaf3d | 3719 | mtd_device_unregister(mtd); |
1da177e4 | 3720 | |
fa671646 | 3721 | /* Free bad block table memory */ |
ace4dfee | 3722 | kfree(chip->bbt); |
4bf63fcb DW |
3723 | if (!(chip->options & NAND_OWN_BUFFERS)) |
3724 | kfree(chip->buffers); | |
58373ff0 BN |
3725 | |
3726 | /* Free bad block descriptor memory */ | |
3727 | if (chip->badblock_pattern && chip->badblock_pattern->options | |
3728 | & NAND_BBT_DYNAMICSTRUCT) | |
3729 | kfree(chip->badblock_pattern); | |
1da177e4 | 3730 | } |
e0c7d767 | 3731 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 RP |
3732 | |
3733 | static int __init nand_base_init(void) | |
3734 | { | |
3735 | led_trigger_register_simple("nand-disk", &nand_led_trigger); | |
3736 | return 0; | |
3737 | } | |
3738 | ||
3739 | static void __exit nand_base_exit(void) | |
3740 | { | |
3741 | led_trigger_unregister_simple(nand_led_trigger); | |
3742 | } | |
3743 | ||
3744 | module_init(nand_base_init); | |
3745 | module_exit(nand_base_exit); | |
3746 | ||
e0c7d767 | 3747 | MODULE_LICENSE("GPL"); |
7351d3a5 FF |
3748 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); |
3749 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
e0c7d767 | 3750 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |