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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Overview: |
3 | * This is the generic MTD driver for NAND flash devices. It should be | |
4 | * capable of working with almost all NAND chips currently available. | |
61b03bd7 | 5 | * |
1da177e4 | 6 | * Additional technical information is available on |
8b2b403c | 7 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 8 | * |
1da177e4 | 9 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 10 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 11 | * |
ace4dfee | 12 | * Credits: |
61b03bd7 TG |
13 | * David Woodhouse for adding multichip support |
14 | * | |
1da177e4 LT |
15 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
16 | * rework for 2K page size chips | |
17 | * | |
ace4dfee | 18 | * TODO: |
1da177e4 LT |
19 | * Enable cached programming for 2k page size chips |
20 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
7854d3f7 | 21 | * if we have HW ECC support. |
c0b8ba7b | 22 | * BBT table is not serialized, has to be fixed |
1da177e4 | 23 | * |
1da177e4 LT |
24 | * This program is free software; you can redistribute it and/or modify |
25 | * it under the terms of the GNU General Public License version 2 as | |
26 | * published by the Free Software Foundation. | |
27 | * | |
28 | */ | |
29 | ||
20171642 EG |
30 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
31 | ||
552d9205 | 32 | #include <linux/module.h> |
1da177e4 LT |
33 | #include <linux/delay.h> |
34 | #include <linux/errno.h> | |
7aa65bfd | 35 | #include <linux/err.h> |
1da177e4 LT |
36 | #include <linux/sched.h> |
37 | #include <linux/slab.h> | |
66507c7b | 38 | #include <linux/mm.h> |
38b8d208 | 39 | #include <linux/nmi.h> |
1da177e4 LT |
40 | #include <linux/types.h> |
41 | #include <linux/mtd/mtd.h> | |
42 | #include <linux/mtd/nand.h> | |
43 | #include <linux/mtd/nand_ecc.h> | |
193bd400 | 44 | #include <linux/mtd/nand_bch.h> |
1da177e4 LT |
45 | #include <linux/interrupt.h> |
46 | #include <linux/bitops.h> | |
7351d3a5 | 47 | #include <linux/io.h> |
1da177e4 | 48 | #include <linux/mtd/partitions.h> |
d48f62b9 | 49 | #include <linux/of.h> |
1da177e4 | 50 | |
41b207a7 BB |
51 | static int nand_get_device(struct mtd_info *mtd, int new_state); |
52 | ||
53 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, | |
54 | struct mtd_oob_ops *ops); | |
1da177e4 LT |
55 | |
56 | /* Define default oob placement schemes for large and small page devices */ | |
41b207a7 BB |
57 | static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section, |
58 | struct mtd_oob_region *oobregion) | |
59 | { | |
60 | struct nand_chip *chip = mtd_to_nand(mtd); | |
61 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
1da177e4 | 62 | |
41b207a7 BB |
63 | if (section > 1) |
64 | return -ERANGE; | |
1da177e4 | 65 | |
41b207a7 BB |
66 | if (!section) { |
67 | oobregion->offset = 0; | |
68 | oobregion->length = 4; | |
69 | } else { | |
70 | oobregion->offset = 6; | |
71 | oobregion->length = ecc->total - 4; | |
72 | } | |
1da177e4 | 73 | |
41b207a7 BB |
74 | return 0; |
75 | } | |
76 | ||
77 | static int nand_ooblayout_free_sp(struct mtd_info *mtd, int section, | |
78 | struct mtd_oob_region *oobregion) | |
79 | { | |
80 | if (section > 1) | |
81 | return -ERANGE; | |
1da177e4 | 82 | |
41b207a7 BB |
83 | if (mtd->oobsize == 16) { |
84 | if (section) | |
85 | return -ERANGE; | |
86 | ||
87 | oobregion->length = 8; | |
88 | oobregion->offset = 8; | |
89 | } else { | |
90 | oobregion->length = 2; | |
91 | if (!section) | |
92 | oobregion->offset = 3; | |
93 | else | |
94 | oobregion->offset = 6; | |
95 | } | |
96 | ||
97 | return 0; | |
98 | } | |
99 | ||
100 | const struct mtd_ooblayout_ops nand_ooblayout_sp_ops = { | |
101 | .ecc = nand_ooblayout_ecc_sp, | |
102 | .free = nand_ooblayout_free_sp, | |
81ec5364 | 103 | }; |
41b207a7 | 104 | EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops); |
81ec5364 | 105 | |
41b207a7 BB |
106 | static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section, |
107 | struct mtd_oob_region *oobregion) | |
108 | { | |
109 | struct nand_chip *chip = mtd_to_nand(mtd); | |
110 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
1da177e4 | 111 | |
41b207a7 BB |
112 | if (section) |
113 | return -ERANGE; | |
8593fbc6 | 114 | |
41b207a7 BB |
115 | oobregion->length = ecc->total; |
116 | oobregion->offset = mtd->oobsize - oobregion->length; | |
117 | ||
118 | return 0; | |
119 | } | |
120 | ||
121 | static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section, | |
122 | struct mtd_oob_region *oobregion) | |
123 | { | |
124 | struct nand_chip *chip = mtd_to_nand(mtd); | |
125 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
126 | ||
127 | if (section) | |
128 | return -ERANGE; | |
129 | ||
130 | oobregion->length = mtd->oobsize - ecc->total - 2; | |
131 | oobregion->offset = 2; | |
132 | ||
133 | return 0; | |
134 | } | |
135 | ||
136 | const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = { | |
137 | .ecc = nand_ooblayout_ecc_lp, | |
138 | .free = nand_ooblayout_free_lp, | |
139 | }; | |
140 | EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops); | |
d470a97c | 141 | |
6a623e07 AC |
142 | /* |
143 | * Support the old "large page" layout used for 1-bit Hamming ECC where ECC | |
144 | * are placed at a fixed offset. | |
145 | */ | |
146 | static int nand_ooblayout_ecc_lp_hamming(struct mtd_info *mtd, int section, | |
147 | struct mtd_oob_region *oobregion) | |
148 | { | |
149 | struct nand_chip *chip = mtd_to_nand(mtd); | |
150 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
151 | ||
152 | if (section) | |
153 | return -ERANGE; | |
154 | ||
155 | switch (mtd->oobsize) { | |
156 | case 64: | |
157 | oobregion->offset = 40; | |
158 | break; | |
159 | case 128: | |
160 | oobregion->offset = 80; | |
161 | break; | |
162 | default: | |
163 | return -EINVAL; | |
164 | } | |
165 | ||
166 | oobregion->length = ecc->total; | |
167 | if (oobregion->offset + oobregion->length > mtd->oobsize) | |
168 | return -ERANGE; | |
169 | ||
170 | return 0; | |
171 | } | |
172 | ||
173 | static int nand_ooblayout_free_lp_hamming(struct mtd_info *mtd, int section, | |
174 | struct mtd_oob_region *oobregion) | |
175 | { | |
176 | struct nand_chip *chip = mtd_to_nand(mtd); | |
177 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
178 | int ecc_offset = 0; | |
179 | ||
180 | if (section < 0 || section > 1) | |
181 | return -ERANGE; | |
182 | ||
183 | switch (mtd->oobsize) { | |
184 | case 64: | |
185 | ecc_offset = 40; | |
186 | break; | |
187 | case 128: | |
188 | ecc_offset = 80; | |
189 | break; | |
190 | default: | |
191 | return -EINVAL; | |
192 | } | |
193 | ||
194 | if (section == 0) { | |
195 | oobregion->offset = 2; | |
196 | oobregion->length = ecc_offset - 2; | |
197 | } else { | |
198 | oobregion->offset = ecc_offset + ecc->total; | |
199 | oobregion->length = mtd->oobsize - oobregion->offset; | |
200 | } | |
201 | ||
202 | return 0; | |
203 | } | |
204 | ||
d4ed3b90 | 205 | static const struct mtd_ooblayout_ops nand_ooblayout_lp_hamming_ops = { |
6a623e07 AC |
206 | .ecc = nand_ooblayout_ecc_lp_hamming, |
207 | .free = nand_ooblayout_free_lp_hamming, | |
208 | }; | |
209 | ||
6fe5a6ac VS |
210 | static int check_offs_len(struct mtd_info *mtd, |
211 | loff_t ofs, uint64_t len) | |
212 | { | |
862eba51 | 213 | struct nand_chip *chip = mtd_to_nand(mtd); |
6fe5a6ac VS |
214 | int ret = 0; |
215 | ||
216 | /* Start address must align on block boundary */ | |
daae74ca | 217 | if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 218 | pr_debug("%s: unaligned address\n", __func__); |
6fe5a6ac VS |
219 | ret = -EINVAL; |
220 | } | |
221 | ||
222 | /* Length must align on block boundary */ | |
daae74ca | 223 | if (len & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 224 | pr_debug("%s: length not block aligned\n", __func__); |
6fe5a6ac VS |
225 | ret = -EINVAL; |
226 | } | |
227 | ||
6fe5a6ac VS |
228 | return ret; |
229 | } | |
230 | ||
1da177e4 LT |
231 | /** |
232 | * nand_release_device - [GENERIC] release chip | |
8b6e50c9 | 233 | * @mtd: MTD device structure |
61b03bd7 | 234 | * |
b0bb6903 | 235 | * Release chip lock and wake up anyone waiting on the device. |
1da177e4 | 236 | */ |
e0c7d767 | 237 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 238 | { |
862eba51 | 239 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 240 | |
a36ed299 | 241 | /* Release the controller and the chip */ |
ace4dfee TG |
242 | spin_lock(&chip->controller->lock); |
243 | chip->controller->active = NULL; | |
244 | chip->state = FL_READY; | |
245 | wake_up(&chip->controller->wq); | |
246 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
247 | } |
248 | ||
249 | /** | |
250 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
8b6e50c9 | 251 | * @mtd: MTD device structure |
1da177e4 | 252 | * |
7854d3f7 | 253 | * Default read function for 8bit buswidth |
1da177e4 | 254 | */ |
58dd8f2b | 255 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 256 | { |
862eba51 | 257 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee | 258 | return readb(chip->IO_ADDR_R); |
1da177e4 LT |
259 | } |
260 | ||
1da177e4 | 261 | /** |
7854d3f7 | 262 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
8b6e50c9 | 263 | * @mtd: MTD device structure |
1da177e4 | 264 | * |
7854d3f7 BN |
265 | * Default read function for 16bit buswidth with endianness conversion. |
266 | * | |
1da177e4 | 267 | */ |
58dd8f2b | 268 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 269 | { |
862eba51 | 270 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee | 271 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); |
1da177e4 LT |
272 | } |
273 | ||
1da177e4 LT |
274 | /** |
275 | * nand_read_word - [DEFAULT] read one word from the chip | |
8b6e50c9 | 276 | * @mtd: MTD device structure |
1da177e4 | 277 | * |
7854d3f7 | 278 | * Default read function for 16bit buswidth without endianness conversion. |
1da177e4 LT |
279 | */ |
280 | static u16 nand_read_word(struct mtd_info *mtd) | |
281 | { | |
862eba51 | 282 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee | 283 | return readw(chip->IO_ADDR_R); |
1da177e4 LT |
284 | } |
285 | ||
1da177e4 LT |
286 | /** |
287 | * nand_select_chip - [DEFAULT] control CE line | |
8b6e50c9 BN |
288 | * @mtd: MTD device structure |
289 | * @chipnr: chipnumber to select, -1 for deselect | |
1da177e4 LT |
290 | * |
291 | * Default select function for 1 chip devices. | |
292 | */ | |
ace4dfee | 293 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 294 | { |
862eba51 | 295 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee TG |
296 | |
297 | switch (chipnr) { | |
1da177e4 | 298 | case -1: |
ace4dfee | 299 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
300 | break; |
301 | case 0: | |
1da177e4 LT |
302 | break; |
303 | ||
304 | default: | |
305 | BUG(); | |
306 | } | |
307 | } | |
308 | ||
05f78359 UKK |
309 | /** |
310 | * nand_write_byte - [DEFAULT] write single byte to chip | |
311 | * @mtd: MTD device structure | |
312 | * @byte: value to write | |
313 | * | |
314 | * Default function to write a byte to I/O[7:0] | |
315 | */ | |
316 | static void nand_write_byte(struct mtd_info *mtd, uint8_t byte) | |
317 | { | |
862eba51 | 318 | struct nand_chip *chip = mtd_to_nand(mtd); |
05f78359 UKK |
319 | |
320 | chip->write_buf(mtd, &byte, 1); | |
321 | } | |
322 | ||
323 | /** | |
324 | * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16 | |
325 | * @mtd: MTD device structure | |
326 | * @byte: value to write | |
327 | * | |
328 | * Default function to write a byte to I/O[7:0] on a 16-bit wide chip. | |
329 | */ | |
330 | static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) | |
331 | { | |
862eba51 | 332 | struct nand_chip *chip = mtd_to_nand(mtd); |
05f78359 UKK |
333 | uint16_t word = byte; |
334 | ||
335 | /* | |
336 | * It's not entirely clear what should happen to I/O[15:8] when writing | |
337 | * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads: | |
338 | * | |
339 | * When the host supports a 16-bit bus width, only data is | |
340 | * transferred at the 16-bit width. All address and command line | |
341 | * transfers shall use only the lower 8-bits of the data bus. During | |
342 | * command transfers, the host may place any value on the upper | |
343 | * 8-bits of the data bus. During address transfers, the host shall | |
344 | * set the upper 8-bits of the data bus to 00h. | |
345 | * | |
346 | * One user of the write_byte callback is nand_onfi_set_features. The | |
347 | * four parameters are specified to be written to I/O[7:0], but this is | |
348 | * neither an address nor a command transfer. Let's assume a 0 on the | |
349 | * upper I/O lines is OK. | |
350 | */ | |
351 | chip->write_buf(mtd, (uint8_t *)&word, 2); | |
352 | } | |
353 | ||
1da177e4 LT |
354 | /** |
355 | * nand_write_buf - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
356 | * @mtd: MTD device structure |
357 | * @buf: data buffer | |
358 | * @len: number of bytes to write | |
1da177e4 | 359 | * |
7854d3f7 | 360 | * Default write function for 8bit buswidth. |
1da177e4 | 361 | */ |
58dd8f2b | 362 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 363 | { |
862eba51 | 364 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 365 | |
76413839 | 366 | iowrite8_rep(chip->IO_ADDR_W, buf, len); |
1da177e4 LT |
367 | } |
368 | ||
369 | /** | |
61b03bd7 | 370 | * nand_read_buf - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
371 | * @mtd: MTD device structure |
372 | * @buf: buffer to store date | |
373 | * @len: number of bytes to read | |
1da177e4 | 374 | * |
7854d3f7 | 375 | * Default read function for 8bit buswidth. |
1da177e4 | 376 | */ |
58dd8f2b | 377 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 378 | { |
862eba51 | 379 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 380 | |
76413839 | 381 | ioread8_rep(chip->IO_ADDR_R, buf, len); |
1da177e4 LT |
382 | } |
383 | ||
1da177e4 LT |
384 | /** |
385 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
386 | * @mtd: MTD device structure |
387 | * @buf: data buffer | |
388 | * @len: number of bytes to write | |
1da177e4 | 389 | * |
7854d3f7 | 390 | * Default write function for 16bit buswidth. |
1da177e4 | 391 | */ |
58dd8f2b | 392 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 393 | { |
862eba51 | 394 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 395 | u16 *p = (u16 *) buf; |
61b03bd7 | 396 | |
76413839 | 397 | iowrite16_rep(chip->IO_ADDR_W, p, len >> 1); |
1da177e4 LT |
398 | } |
399 | ||
400 | /** | |
61b03bd7 | 401 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
402 | * @mtd: MTD device structure |
403 | * @buf: buffer to store date | |
404 | * @len: number of bytes to read | |
1da177e4 | 405 | * |
7854d3f7 | 406 | * Default read function for 16bit buswidth. |
1da177e4 | 407 | */ |
58dd8f2b | 408 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 409 | { |
862eba51 | 410 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 411 | u16 *p = (u16 *) buf; |
1da177e4 | 412 | |
76413839 | 413 | ioread16_rep(chip->IO_ADDR_R, p, len >> 1); |
1da177e4 LT |
414 | } |
415 | ||
1da177e4 LT |
416 | /** |
417 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
8b6e50c9 BN |
418 | * @mtd: MTD device structure |
419 | * @ofs: offset from device start | |
1da177e4 | 420 | * |
61b03bd7 | 421 | * Check, if the block is bad. |
1da177e4 | 422 | */ |
9f3e0429 | 423 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 424 | { |
c120e75e | 425 | int page, page_end, res; |
862eba51 | 426 | struct nand_chip *chip = mtd_to_nand(mtd); |
c120e75e | 427 | u8 bad; |
1da177e4 | 428 | |
5fb1549d | 429 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
430 | ofs += mtd->erasesize - mtd->writesize; |
431 | ||
1a12f46a | 432 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
c120e75e | 433 | page_end = page + (chip->bbt_options & NAND_BBT_SCAN2NDPAGE ? 2 : 1); |
1a12f46a | 434 | |
c120e75e MY |
435 | for (; page < page_end; page++) { |
436 | res = chip->ecc.read_oob(mtd, chip, page); | |
437 | if (res) | |
438 | return res; | |
439 | ||
440 | bad = chip->oob_poi[chip->badblockpos]; | |
cdbec050 BN |
441 | |
442 | if (likely(chip->badblockbits == 8)) | |
443 | res = bad != 0xFF; | |
e0b58d0a | 444 | else |
cdbec050 | 445 | res = hweight8(bad) < chip->badblockbits; |
c120e75e MY |
446 | if (res) |
447 | return res; | |
448 | } | |
e0b58d0a | 449 | |
c120e75e | 450 | return 0; |
1da177e4 LT |
451 | } |
452 | ||
453 | /** | |
5a0edb25 | 454 | * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker |
8b6e50c9 BN |
455 | * @mtd: MTD device structure |
456 | * @ofs: offset from device start | |
1da177e4 | 457 | * |
8b6e50c9 | 458 | * This is the default implementation, which can be overridden by a hardware |
5a0edb25 BN |
459 | * specific driver. It provides the details for writing a bad block marker to a |
460 | * block. | |
461 | */ | |
462 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
463 | { | |
862eba51 | 464 | struct nand_chip *chip = mtd_to_nand(mtd); |
5a0edb25 BN |
465 | struct mtd_oob_ops ops; |
466 | uint8_t buf[2] = { 0, 0 }; | |
467 | int ret = 0, res, i = 0; | |
468 | ||
0ec56dc4 | 469 | memset(&ops, 0, sizeof(ops)); |
5a0edb25 BN |
470 | ops.oobbuf = buf; |
471 | ops.ooboffs = chip->badblockpos; | |
472 | if (chip->options & NAND_BUSWIDTH_16) { | |
473 | ops.ooboffs &= ~0x01; | |
474 | ops.len = ops.ooblen = 2; | |
475 | } else { | |
476 | ops.len = ops.ooblen = 1; | |
477 | } | |
478 | ops.mode = MTD_OPS_PLACE_OOB; | |
479 | ||
480 | /* Write to first/last page(s) if necessary */ | |
481 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) | |
482 | ofs += mtd->erasesize - mtd->writesize; | |
483 | do { | |
484 | res = nand_do_write_oob(mtd, ofs, &ops); | |
485 | if (!ret) | |
486 | ret = res; | |
487 | ||
488 | i++; | |
489 | ofs += mtd->writesize; | |
490 | } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); | |
491 | ||
492 | return ret; | |
493 | } | |
494 | ||
495 | /** | |
496 | * nand_block_markbad_lowlevel - mark a block bad | |
497 | * @mtd: MTD device structure | |
498 | * @ofs: offset from device start | |
499 | * | |
500 | * This function performs the generic NAND bad block marking steps (i.e., bad | |
501 | * block table(s) and/or marker(s)). We only allow the hardware driver to | |
502 | * specify how to write bad block markers to OOB (chip->block_markbad). | |
503 | * | |
b32843b7 | 504 | * We try operations in the following order: |
e2414f4c | 505 | * (1) erase the affected block, to allow OOB marker to be written cleanly |
b32843b7 BN |
506 | * (2) write bad block marker to OOB area of affected block (unless flag |
507 | * NAND_BBT_NO_OOB_BBM is present) | |
508 | * (3) update the BBT | |
509 | * Note that we retain the first error encountered in (2) or (3), finish the | |
e2414f4c | 510 | * procedures, and dump the error in the end. |
1da177e4 | 511 | */ |
5a0edb25 | 512 | static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 513 | { |
862eba51 | 514 | struct nand_chip *chip = mtd_to_nand(mtd); |
b32843b7 | 515 | int res, ret = 0; |
61b03bd7 | 516 | |
b32843b7 | 517 | if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { |
00918429 BN |
518 | struct erase_info einfo; |
519 | ||
520 | /* Attempt erase before marking OOB */ | |
521 | memset(&einfo, 0, sizeof(einfo)); | |
522 | einfo.mtd = mtd; | |
523 | einfo.addr = ofs; | |
daae74ca | 524 | einfo.len = 1ULL << chip->phys_erase_shift; |
00918429 | 525 | nand_erase_nand(mtd, &einfo, 0); |
1da177e4 | 526 | |
b32843b7 | 527 | /* Write bad block marker to OOB */ |
6a8214aa | 528 | nand_get_device(mtd, FL_WRITING); |
5a0edb25 | 529 | ret = chip->block_markbad(mtd, ofs); |
c0b8ba7b | 530 | nand_release_device(mtd); |
f1a28c02 | 531 | } |
e2414f4c | 532 | |
b32843b7 BN |
533 | /* Mark block bad in BBT */ |
534 | if (chip->bbt) { | |
535 | res = nand_markbad_bbt(mtd, ofs); | |
e2414f4c BN |
536 | if (!ret) |
537 | ret = res; | |
538 | } | |
539 | ||
f1a28c02 TG |
540 | if (!ret) |
541 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 542 | |
f1a28c02 | 543 | return ret; |
1da177e4 LT |
544 | } |
545 | ||
61b03bd7 | 546 | /** |
1da177e4 | 547 | * nand_check_wp - [GENERIC] check if the chip is write protected |
8b6e50c9 | 548 | * @mtd: MTD device structure |
1da177e4 | 549 | * |
8b6e50c9 BN |
550 | * Check, if the device is write protected. The function expects, that the |
551 | * device is already selected. | |
1da177e4 | 552 | */ |
e0c7d767 | 553 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 554 | { |
862eba51 | 555 | struct nand_chip *chip = mtd_to_nand(mtd); |
93edbad6 | 556 | |
8b6e50c9 | 557 | /* Broken xD cards report WP despite being writable */ |
93edbad6 ML |
558 | if (chip->options & NAND_BROKEN_XD) |
559 | return 0; | |
560 | ||
1da177e4 | 561 | /* Check the WP bit */ |
ace4dfee TG |
562 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
563 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
564 | } |
565 | ||
8471bb73 | 566 | /** |
c30e1f79 | 567 | * nand_block_isreserved - [GENERIC] Check if a block is marked reserved. |
8471bb73 EG |
568 | * @mtd: MTD device structure |
569 | * @ofs: offset from device start | |
570 | * | |
c30e1f79 | 571 | * Check if the block is marked as reserved. |
8471bb73 EG |
572 | */ |
573 | static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) | |
574 | { | |
862eba51 | 575 | struct nand_chip *chip = mtd_to_nand(mtd); |
8471bb73 EG |
576 | |
577 | if (!chip->bbt) | |
578 | return 0; | |
579 | /* Return info from the table */ | |
580 | return nand_isreserved_bbt(mtd, ofs); | |
581 | } | |
582 | ||
1da177e4 LT |
583 | /** |
584 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
8b6e50c9 BN |
585 | * @mtd: MTD device structure |
586 | * @ofs: offset from device start | |
8b6e50c9 | 587 | * @allowbbt: 1, if its allowed to access the bbt area |
1da177e4 LT |
588 | * |
589 | * Check, if the block is bad. Either by reading the bad block table or | |
590 | * calling of the scan function. | |
591 | */ | |
9f3e0429 | 592 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt) |
1da177e4 | 593 | { |
862eba51 | 594 | struct nand_chip *chip = mtd_to_nand(mtd); |
61b03bd7 | 595 | |
ace4dfee | 596 | if (!chip->bbt) |
9f3e0429 | 597 | return chip->block_bad(mtd, ofs); |
61b03bd7 | 598 | |
1da177e4 | 599 | /* Return info from the table */ |
e0c7d767 | 600 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
601 | } |
602 | ||
2af7c653 SK |
603 | /** |
604 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
8b6e50c9 BN |
605 | * @mtd: MTD device structure |
606 | * @timeo: Timeout | |
2af7c653 SK |
607 | * |
608 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
609 | * context. | |
610 | */ | |
611 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
612 | { | |
862eba51 | 613 | struct nand_chip *chip = mtd_to_nand(mtd); |
2af7c653 SK |
614 | int i; |
615 | ||
616 | /* Wait for the device to get ready */ | |
617 | for (i = 0; i < timeo; i++) { | |
618 | if (chip->dev_ready(mtd)) | |
619 | break; | |
620 | touch_softlockup_watchdog(); | |
621 | mdelay(1); | |
622 | } | |
623 | } | |
624 | ||
b70af9be AS |
625 | /** |
626 | * nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
627 | * @mtd: MTD device structure | |
628 | * | |
629 | * Wait for the ready pin after a command, and warn if a timeout occurs. | |
630 | */ | |
4b648b02 | 631 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 632 | { |
862eba51 | 633 | struct nand_chip *chip = mtd_to_nand(mtd); |
b70af9be | 634 | unsigned long timeo = 400; |
3b88775c | 635 | |
2af7c653 | 636 | if (in_interrupt() || oops_in_progress) |
b70af9be | 637 | return panic_nand_wait_ready(mtd, timeo); |
2af7c653 | 638 | |
7854d3f7 | 639 | /* Wait until command is processed or timeout occurs */ |
b70af9be | 640 | timeo = jiffies + msecs_to_jiffies(timeo); |
3b88775c | 641 | do { |
ace4dfee | 642 | if (chip->dev_ready(mtd)) |
4c7e054f | 643 | return; |
b70af9be | 644 | cond_resched(); |
61b03bd7 | 645 | } while (time_before(jiffies, timeo)); |
b70af9be | 646 | |
9ebfdf5b BN |
647 | if (!chip->dev_ready(mtd)) |
648 | pr_warn_ratelimited("timeout while waiting for chip to become ready\n"); | |
3b88775c | 649 | } |
4b648b02 | 650 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 651 | |
60c70d66 RQ |
652 | /** |
653 | * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands. | |
654 | * @mtd: MTD device structure | |
655 | * @timeo: Timeout in ms | |
656 | * | |
657 | * Wait for status ready (i.e. command done) or timeout. | |
658 | */ | |
659 | static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo) | |
660 | { | |
862eba51 | 661 | register struct nand_chip *chip = mtd_to_nand(mtd); |
60c70d66 RQ |
662 | |
663 | timeo = jiffies + msecs_to_jiffies(timeo); | |
664 | do { | |
665 | if ((chip->read_byte(mtd) & NAND_STATUS_READY)) | |
666 | break; | |
667 | touch_softlockup_watchdog(); | |
668 | } while (time_before(jiffies, timeo)); | |
669 | }; | |
670 | ||
1da177e4 LT |
671 | /** |
672 | * nand_command - [DEFAULT] Send command to NAND device | |
8b6e50c9 BN |
673 | * @mtd: MTD device structure |
674 | * @command: the command to be sent | |
675 | * @column: the column address for this command, -1 if none | |
676 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 677 | * |
8b6e50c9 | 678 | * Send command to NAND device. This function is used for small page devices |
51148f1f | 679 | * (512 Bytes per page). |
1da177e4 | 680 | */ |
7abd3ef9 TG |
681 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
682 | int column, int page_addr) | |
1da177e4 | 683 | { |
862eba51 | 684 | register struct nand_chip *chip = mtd_to_nand(mtd); |
7abd3ef9 | 685 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 686 | |
8b6e50c9 | 687 | /* Write out the command to the device */ |
1da177e4 LT |
688 | if (command == NAND_CMD_SEQIN) { |
689 | int readcmd; | |
690 | ||
28318776 | 691 | if (column >= mtd->writesize) { |
1da177e4 | 692 | /* OOB area */ |
28318776 | 693 | column -= mtd->writesize; |
1da177e4 LT |
694 | readcmd = NAND_CMD_READOOB; |
695 | } else if (column < 256) { | |
696 | /* First 256 bytes --> READ0 */ | |
697 | readcmd = NAND_CMD_READ0; | |
698 | } else { | |
699 | column -= 256; | |
700 | readcmd = NAND_CMD_READ1; | |
701 | } | |
ace4dfee | 702 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 703 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 704 | } |
ace4dfee | 705 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 706 | |
8b6e50c9 | 707 | /* Address cycle, when necessary */ |
7abd3ef9 TG |
708 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; |
709 | /* Serially input address */ | |
710 | if (column != -1) { | |
711 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
712 | if (chip->options & NAND_BUSWIDTH_16 && |
713 | !nand_opcode_8bits(command)) | |
7abd3ef9 | 714 | column >>= 1; |
ace4dfee | 715 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
716 | ctrl &= ~NAND_CTRL_CHANGE; |
717 | } | |
718 | if (page_addr != -1) { | |
ace4dfee | 719 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 720 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 721 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 722 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
723 | if (chip->chipsize > (32 << 20)) |
724 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 725 | } |
ace4dfee | 726 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
727 | |
728 | /* | |
8b6e50c9 BN |
729 | * Program and erase have their own busy handlers status and sequential |
730 | * in needs no delay | |
e0c7d767 | 731 | */ |
1da177e4 | 732 | switch (command) { |
61b03bd7 | 733 | |
1da177e4 LT |
734 | case NAND_CMD_PAGEPROG: |
735 | case NAND_CMD_ERASE1: | |
736 | case NAND_CMD_ERASE2: | |
737 | case NAND_CMD_SEQIN: | |
738 | case NAND_CMD_STATUS: | |
3158fa0e | 739 | case NAND_CMD_READID: |
c5d664aa | 740 | case NAND_CMD_SET_FEATURES: |
1da177e4 LT |
741 | return; |
742 | ||
743 | case NAND_CMD_RESET: | |
ace4dfee | 744 | if (chip->dev_ready) |
1da177e4 | 745 | break; |
ace4dfee TG |
746 | udelay(chip->chip_delay); |
747 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 748 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
749 | chip->cmd_ctrl(mtd, |
750 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
60c70d66 RQ |
751 | /* EZ-NAND can take upto 250ms as per ONFi v4.0 */ |
752 | nand_wait_status_ready(mtd, 250); | |
1da177e4 LT |
753 | return; |
754 | ||
e0c7d767 | 755 | /* This applies to read commands */ |
1da177e4 | 756 | default: |
61b03bd7 | 757 | /* |
1da177e4 LT |
758 | * If we don't have access to the busy pin, we apply the given |
759 | * command delay | |
e0c7d767 | 760 | */ |
ace4dfee TG |
761 | if (!chip->dev_ready) { |
762 | udelay(chip->chip_delay); | |
1da177e4 | 763 | return; |
61b03bd7 | 764 | } |
1da177e4 | 765 | } |
8b6e50c9 BN |
766 | /* |
767 | * Apply this short delay always to ensure that we do wait tWB in | |
768 | * any case on any machine. | |
769 | */ | |
e0c7d767 | 770 | ndelay(100); |
3b88775c TG |
771 | |
772 | nand_wait_ready(mtd); | |
1da177e4 LT |
773 | } |
774 | ||
6ea40a3b BB |
775 | static void nand_ccs_delay(struct nand_chip *chip) |
776 | { | |
777 | /* | |
778 | * The controller already takes care of waiting for tCCS when the RNDIN | |
779 | * or RNDOUT command is sent, return directly. | |
780 | */ | |
781 | if (!(chip->options & NAND_WAIT_TCCS)) | |
782 | return; | |
783 | ||
784 | /* | |
785 | * Wait tCCS_min if it is correctly defined, otherwise wait 500ns | |
786 | * (which should be safe for all NANDs). | |
787 | */ | |
788 | if (chip->data_interface && chip->data_interface->timings.sdr.tCCS_min) | |
789 | ndelay(chip->data_interface->timings.sdr.tCCS_min / 1000); | |
790 | else | |
791 | ndelay(500); | |
792 | } | |
793 | ||
1da177e4 LT |
794 | /** |
795 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
8b6e50c9 BN |
796 | * @mtd: MTD device structure |
797 | * @command: the command to be sent | |
798 | * @column: the column address for this command, -1 if none | |
799 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 800 | * |
7abd3ef9 | 801 | * Send command to NAND device. This is the version for the new large page |
7854d3f7 BN |
802 | * devices. We don't have the separate regions as we have in the small page |
803 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 804 | */ |
7abd3ef9 TG |
805 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
806 | int column, int page_addr) | |
1da177e4 | 807 | { |
862eba51 | 808 | register struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 LT |
809 | |
810 | /* Emulate NAND_CMD_READOOB */ | |
811 | if (command == NAND_CMD_READOOB) { | |
28318776 | 812 | column += mtd->writesize; |
1da177e4 LT |
813 | command = NAND_CMD_READ0; |
814 | } | |
61b03bd7 | 815 | |
7abd3ef9 | 816 | /* Command latch cycle */ |
fb066ada | 817 | chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
818 | |
819 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 820 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
821 | |
822 | /* Serially input address */ | |
823 | if (column != -1) { | |
824 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
825 | if (chip->options & NAND_BUSWIDTH_16 && |
826 | !nand_opcode_8bits(command)) | |
1da177e4 | 827 | column >>= 1; |
ace4dfee | 828 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 829 | ctrl &= ~NAND_CTRL_CHANGE; |
fde85cfd | 830 | |
f5b88de2 | 831 | /* Only output a single addr cycle for 8bits opcodes. */ |
fde85cfd BB |
832 | if (!nand_opcode_8bits(command)) |
833 | chip->cmd_ctrl(mtd, column >> 8, ctrl); | |
61b03bd7 | 834 | } |
1da177e4 | 835 | if (page_addr != -1) { |
ace4dfee TG |
836 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
837 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 838 | NAND_NCE | NAND_ALE); |
1da177e4 | 839 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
840 | if (chip->chipsize > (128 << 20)) |
841 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 842 | NAND_NCE | NAND_ALE); |
1da177e4 | 843 | } |
1da177e4 | 844 | } |
ace4dfee | 845 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
846 | |
847 | /* | |
8b6e50c9 | 848 | * Program and erase have their own busy handlers status, sequential |
7a442f17 | 849 | * in and status need no delay. |
30f464b7 | 850 | */ |
1da177e4 | 851 | switch (command) { |
61b03bd7 | 852 | |
1da177e4 LT |
853 | case NAND_CMD_CACHEDPROG: |
854 | case NAND_CMD_PAGEPROG: | |
855 | case NAND_CMD_ERASE1: | |
856 | case NAND_CMD_ERASE2: | |
857 | case NAND_CMD_SEQIN: | |
858 | case NAND_CMD_STATUS: | |
3158fa0e | 859 | case NAND_CMD_READID: |
c5d664aa | 860 | case NAND_CMD_SET_FEATURES: |
30f464b7 | 861 | return; |
1da177e4 | 862 | |
6ea40a3b BB |
863 | case NAND_CMD_RNDIN: |
864 | nand_ccs_delay(chip); | |
865 | return; | |
866 | ||
1da177e4 | 867 | case NAND_CMD_RESET: |
ace4dfee | 868 | if (chip->dev_ready) |
1da177e4 | 869 | break; |
ace4dfee | 870 | udelay(chip->chip_delay); |
12efdde3 TG |
871 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
872 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
873 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
874 | NAND_NCE | NAND_CTRL_CHANGE); | |
60c70d66 RQ |
875 | /* EZ-NAND can take upto 250ms as per ONFi v4.0 */ |
876 | nand_wait_status_ready(mtd, 250); | |
1da177e4 LT |
877 | return; |
878 | ||
7bc3312b TG |
879 | case NAND_CMD_RNDOUT: |
880 | /* No ready / busy check necessary */ | |
881 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
882 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
883 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
884 | NAND_NCE | NAND_CTRL_CHANGE); | |
6ea40a3b BB |
885 | |
886 | nand_ccs_delay(chip); | |
7bc3312b TG |
887 | return; |
888 | ||
1da177e4 | 889 | case NAND_CMD_READ0: |
12efdde3 TG |
890 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
891 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
892 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
893 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 894 | |
e0c7d767 | 895 | /* This applies to read commands */ |
1da177e4 | 896 | default: |
61b03bd7 | 897 | /* |
1da177e4 | 898 | * If we don't have access to the busy pin, we apply the given |
8b6e50c9 | 899 | * command delay. |
e0c7d767 | 900 | */ |
ace4dfee TG |
901 | if (!chip->dev_ready) { |
902 | udelay(chip->chip_delay); | |
1da177e4 | 903 | return; |
61b03bd7 | 904 | } |
1da177e4 | 905 | } |
3b88775c | 906 | |
8b6e50c9 BN |
907 | /* |
908 | * Apply this short delay always to ensure that we do wait tWB in | |
909 | * any case on any machine. | |
910 | */ | |
e0c7d767 | 911 | ndelay(100); |
3b88775c TG |
912 | |
913 | nand_wait_ready(mtd); | |
1da177e4 LT |
914 | } |
915 | ||
2af7c653 SK |
916 | /** |
917 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
918 | * @chip: the nand chip descriptor |
919 | * @mtd: MTD device structure | |
920 | * @new_state: the state which is requested | |
2af7c653 SK |
921 | * |
922 | * Used when in panic, no locks are taken. | |
923 | */ | |
924 | static void panic_nand_get_device(struct nand_chip *chip, | |
925 | struct mtd_info *mtd, int new_state) | |
926 | { | |
7854d3f7 | 927 | /* Hardware controller shared among independent devices */ |
2af7c653 SK |
928 | chip->controller->active = chip; |
929 | chip->state = new_state; | |
930 | } | |
931 | ||
1da177e4 LT |
932 | /** |
933 | * nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
934 | * @mtd: MTD device structure |
935 | * @new_state: the state which is requested | |
1da177e4 LT |
936 | * |
937 | * Get the device and lock it for exclusive access | |
938 | */ | |
2c0a2bed | 939 | static int |
6a8214aa | 940 | nand_get_device(struct mtd_info *mtd, int new_state) |
1da177e4 | 941 | { |
862eba51 | 942 | struct nand_chip *chip = mtd_to_nand(mtd); |
ace4dfee TG |
943 | spinlock_t *lock = &chip->controller->lock; |
944 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 945 | DECLARE_WAITQUEUE(wait, current); |
7351d3a5 | 946 | retry: |
0dfc6246 TG |
947 | spin_lock(lock); |
948 | ||
b8b3ee9a | 949 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
950 | if (!chip->controller->active) |
951 | chip->controller->active = chip; | |
a36ed299 | 952 | |
ace4dfee TG |
953 | if (chip->controller->active == chip && chip->state == FL_READY) { |
954 | chip->state = new_state; | |
0dfc6246 | 955 | spin_unlock(lock); |
962034f4 VW |
956 | return 0; |
957 | } | |
958 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
959 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
960 | chip->state = FL_PM_SUSPENDED; | |
961 | spin_unlock(lock); | |
962 | return 0; | |
6b0d9a84 | 963 | } |
0dfc6246 TG |
964 | } |
965 | set_current_state(TASK_UNINTERRUPTIBLE); | |
966 | add_wait_queue(wq, &wait); | |
967 | spin_unlock(lock); | |
968 | schedule(); | |
969 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
970 | goto retry; |
971 | } | |
972 | ||
2af7c653 | 973 | /** |
8b6e50c9 BN |
974 | * panic_nand_wait - [GENERIC] wait until the command is done |
975 | * @mtd: MTD device structure | |
976 | * @chip: NAND chip structure | |
977 | * @timeo: timeout | |
2af7c653 SK |
978 | * |
979 | * Wait for command done. This is a helper function for nand_wait used when | |
980 | * we are in interrupt context. May happen when in panic and trying to write | |
b595076a | 981 | * an oops through mtdoops. |
2af7c653 SK |
982 | */ |
983 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
984 | unsigned long timeo) | |
985 | { | |
986 | int i; | |
987 | for (i = 0; i < timeo; i++) { | |
988 | if (chip->dev_ready) { | |
989 | if (chip->dev_ready(mtd)) | |
990 | break; | |
991 | } else { | |
992 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
993 | break; | |
994 | } | |
995 | mdelay(1); | |
f8ac0414 | 996 | } |
2af7c653 SK |
997 | } |
998 | ||
1da177e4 | 999 | /** |
8b6e50c9 BN |
1000 | * nand_wait - [DEFAULT] wait until the command is done |
1001 | * @mtd: MTD device structure | |
1002 | * @chip: NAND chip structure | |
1da177e4 | 1003 | * |
b70af9be | 1004 | * Wait for command done. This applies to erase and program only. |
844d3b42 | 1005 | */ |
7bc3312b | 1006 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
1007 | { |
1008 | ||
b70af9be AS |
1009 | int status; |
1010 | unsigned long timeo = 400; | |
1da177e4 | 1011 | |
8b6e50c9 BN |
1012 | /* |
1013 | * Apply this short delay always to ensure that we do wait tWB in any | |
1014 | * case on any machine. | |
1015 | */ | |
e0c7d767 | 1016 | ndelay(100); |
1da177e4 | 1017 | |
14c65786 | 1018 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 1019 | |
2af7c653 SK |
1020 | if (in_interrupt() || oops_in_progress) |
1021 | panic_nand_wait(mtd, chip, timeo); | |
1022 | else { | |
6d2559f8 | 1023 | timeo = jiffies + msecs_to_jiffies(timeo); |
b70af9be | 1024 | do { |
2af7c653 SK |
1025 | if (chip->dev_ready) { |
1026 | if (chip->dev_ready(mtd)) | |
1027 | break; | |
1028 | } else { | |
1029 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
1030 | break; | |
1031 | } | |
1032 | cond_resched(); | |
b70af9be | 1033 | } while (time_before(jiffies, timeo)); |
1da177e4 | 1034 | } |
8fe833c1 | 1035 | |
ace4dfee | 1036 | status = (int)chip->read_byte(mtd); |
f251b8df MC |
1037 | /* This can happen if in case of timeout or buggy dev_ready */ |
1038 | WARN_ON(!(status & NAND_STATUS_READY)); | |
1da177e4 LT |
1039 | return status; |
1040 | } | |
1041 | ||
d8e725dd BB |
1042 | /** |
1043 | * nand_reset_data_interface - Reset data interface and timings | |
1044 | * @chip: The NAND chip | |
1045 | * | |
1046 | * Reset the Data interface and timings to ONFI mode 0. | |
1047 | * | |
1048 | * Returns 0 for success or negative error code otherwise. | |
1049 | */ | |
1050 | static int nand_reset_data_interface(struct nand_chip *chip) | |
1051 | { | |
1052 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1053 | const struct nand_data_interface *conf; | |
1054 | int ret; | |
1055 | ||
1056 | if (!chip->setup_data_interface) | |
1057 | return 0; | |
1058 | ||
1059 | /* | |
1060 | * The ONFI specification says: | |
1061 | * " | |
1062 | * To transition from NV-DDR or NV-DDR2 to the SDR data | |
1063 | * interface, the host shall use the Reset (FFh) command | |
1064 | * using SDR timing mode 0. A device in any timing mode is | |
1065 | * required to recognize Reset (FFh) command issued in SDR | |
1066 | * timing mode 0. | |
1067 | * " | |
1068 | * | |
1069 | * Configure the data interface in SDR mode and set the | |
1070 | * timings to timing mode 0. | |
1071 | */ | |
1072 | ||
1073 | conf = nand_get_default_data_interface(); | |
1074 | ret = chip->setup_data_interface(mtd, conf, false); | |
1075 | if (ret) | |
1076 | pr_err("Failed to configure data interface to SDR timing mode 0\n"); | |
1077 | ||
1078 | return ret; | |
1079 | } | |
1080 | ||
1081 | /** | |
1082 | * nand_setup_data_interface - Setup the best data interface and timings | |
1083 | * @chip: The NAND chip | |
1084 | * | |
1085 | * Find and configure the best data interface and NAND timings supported by | |
1086 | * the chip and the driver. | |
1087 | * First tries to retrieve supported timing modes from ONFI information, | |
1088 | * and if the NAND chip does not support ONFI, relies on the | |
1089 | * ->onfi_timing_mode_default specified in the nand_ids table. | |
1090 | * | |
1091 | * Returns 0 for success or negative error code otherwise. | |
1092 | */ | |
1093 | static int nand_setup_data_interface(struct nand_chip *chip) | |
1094 | { | |
1095 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1096 | int ret; | |
1097 | ||
1098 | if (!chip->setup_data_interface || !chip->data_interface) | |
1099 | return 0; | |
1100 | ||
1101 | /* | |
1102 | * Ensure the timing mode has been changed on the chip side | |
1103 | * before changing timings on the controller side. | |
1104 | */ | |
1105 | if (chip->onfi_version) { | |
1106 | u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { | |
1107 | chip->onfi_timing_mode_default, | |
1108 | }; | |
1109 | ||
1110 | ret = chip->onfi_set_features(mtd, chip, | |
1111 | ONFI_FEATURE_ADDR_TIMING_MODE, | |
1112 | tmode_param); | |
1113 | if (ret) | |
1114 | goto err; | |
1115 | } | |
1116 | ||
1117 | ret = chip->setup_data_interface(mtd, chip->data_interface, false); | |
1118 | err: | |
1119 | return ret; | |
1120 | } | |
1121 | ||
1122 | /** | |
1123 | * nand_init_data_interface - find the best data interface and timings | |
1124 | * @chip: The NAND chip | |
1125 | * | |
1126 | * Find the best data interface and NAND timings supported by the chip | |
1127 | * and the driver. | |
1128 | * First tries to retrieve supported timing modes from ONFI information, | |
1129 | * and if the NAND chip does not support ONFI, relies on the | |
1130 | * ->onfi_timing_mode_default specified in the nand_ids table. After this | |
1131 | * function nand_chip->data_interface is initialized with the best timing mode | |
1132 | * available. | |
1133 | * | |
1134 | * Returns 0 for success or negative error code otherwise. | |
1135 | */ | |
1136 | static int nand_init_data_interface(struct nand_chip *chip) | |
1137 | { | |
1138 | struct mtd_info *mtd = nand_to_mtd(chip); | |
1139 | int modes, mode, ret; | |
1140 | ||
1141 | if (!chip->setup_data_interface) | |
1142 | return 0; | |
1143 | ||
1144 | /* | |
1145 | * First try to identify the best timings from ONFI parameters and | |
1146 | * if the NAND does not support ONFI, fallback to the default ONFI | |
1147 | * timing mode. | |
1148 | */ | |
1149 | modes = onfi_get_async_timing_mode(chip); | |
1150 | if (modes == ONFI_TIMING_MODE_UNKNOWN) { | |
1151 | if (!chip->onfi_timing_mode_default) | |
1152 | return 0; | |
1153 | ||
1154 | modes = GENMASK(chip->onfi_timing_mode_default, 0); | |
1155 | } | |
1156 | ||
1157 | chip->data_interface = kzalloc(sizeof(*chip->data_interface), | |
1158 | GFP_KERNEL); | |
1159 | if (!chip->data_interface) | |
1160 | return -ENOMEM; | |
1161 | ||
1162 | for (mode = fls(modes) - 1; mode >= 0; mode--) { | |
1163 | ret = onfi_init_data_interface(chip, chip->data_interface, | |
1164 | NAND_SDR_IFACE, mode); | |
1165 | if (ret) | |
1166 | continue; | |
1167 | ||
1168 | ret = chip->setup_data_interface(mtd, chip->data_interface, | |
1169 | true); | |
1170 | if (!ret) { | |
1171 | chip->onfi_timing_mode_default = mode; | |
1172 | break; | |
1173 | } | |
1174 | } | |
1175 | ||
1176 | return 0; | |
1177 | } | |
1178 | ||
1179 | static void nand_release_data_interface(struct nand_chip *chip) | |
1180 | { | |
1181 | kfree(chip->data_interface); | |
1182 | } | |
1183 | ||
2f94abfe SH |
1184 | /** |
1185 | * nand_reset - Reset and initialize a NAND device | |
1186 | * @chip: The NAND chip | |
73f907fd | 1187 | * @chipnr: Internal die id |
2f94abfe SH |
1188 | * |
1189 | * Returns 0 for success or negative error code otherwise | |
1190 | */ | |
73f907fd | 1191 | int nand_reset(struct nand_chip *chip, int chipnr) |
2f94abfe SH |
1192 | { |
1193 | struct mtd_info *mtd = nand_to_mtd(chip); | |
d8e725dd BB |
1194 | int ret; |
1195 | ||
1196 | ret = nand_reset_data_interface(chip); | |
1197 | if (ret) | |
1198 | return ret; | |
2f94abfe | 1199 | |
73f907fd BB |
1200 | /* |
1201 | * The CS line has to be released before we can apply the new NAND | |
1202 | * interface settings, hence this weird ->select_chip() dance. | |
1203 | */ | |
1204 | chip->select_chip(mtd, chipnr); | |
2f94abfe | 1205 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
73f907fd | 1206 | chip->select_chip(mtd, -1); |
2f94abfe | 1207 | |
73f907fd | 1208 | chip->select_chip(mtd, chipnr); |
d8e725dd | 1209 | ret = nand_setup_data_interface(chip); |
73f907fd | 1210 | chip->select_chip(mtd, -1); |
d8e725dd BB |
1211 | if (ret) |
1212 | return ret; | |
1213 | ||
2f94abfe SH |
1214 | return 0; |
1215 | } | |
1216 | ||
7d70f334 | 1217 | /** |
b6d676db | 1218 | * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
1219 | * @mtd: mtd info |
1220 | * @ofs: offset to start unlock from | |
1221 | * @len: length to unlock | |
8b6e50c9 BN |
1222 | * @invert: when = 0, unlock the range of blocks within the lower and |
1223 | * upper boundary address | |
1224 | * when = 1, unlock the range of blocks outside the boundaries | |
1225 | * of the lower and upper boundary address | |
7d70f334 | 1226 | * |
8b6e50c9 | 1227 | * Returs unlock status. |
7d70f334 VS |
1228 | */ |
1229 | static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, | |
1230 | uint64_t len, int invert) | |
1231 | { | |
1232 | int ret = 0; | |
1233 | int status, page; | |
862eba51 | 1234 | struct nand_chip *chip = mtd_to_nand(mtd); |
7d70f334 VS |
1235 | |
1236 | /* Submit address of first page to unlock */ | |
1237 | page = ofs >> chip->page_shift; | |
1238 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); | |
1239 | ||
1240 | /* Submit address of last page to unlock */ | |
1241 | page = (ofs + len) >> chip->page_shift; | |
1242 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, | |
1243 | (page | invert) & chip->pagemask); | |
1244 | ||
1245 | /* Call wait ready function */ | |
1246 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 1247 | /* See if device thinks it succeeded */ |
74830966 | 1248 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 1249 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
1250 | __func__, status); |
1251 | ret = -EIO; | |
1252 | } | |
1253 | ||
1254 | return ret; | |
1255 | } | |
1256 | ||
1257 | /** | |
b6d676db | 1258 | * nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
1259 | * @mtd: mtd info |
1260 | * @ofs: offset to start unlock from | |
1261 | * @len: length to unlock | |
7d70f334 | 1262 | * |
8b6e50c9 | 1263 | * Returns unlock status. |
7d70f334 VS |
1264 | */ |
1265 | int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
1266 | { | |
1267 | int ret = 0; | |
1268 | int chipnr; | |
862eba51 | 1269 | struct nand_chip *chip = mtd_to_nand(mtd); |
7d70f334 | 1270 | |
289c0522 | 1271 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
1272 | __func__, (unsigned long long)ofs, len); |
1273 | ||
1274 | if (check_offs_len(mtd, ofs, len)) | |
b1a2348a | 1275 | return -EINVAL; |
7d70f334 VS |
1276 | |
1277 | /* Align to last block address if size addresses end of the device */ | |
1278 | if (ofs + len == mtd->size) | |
1279 | len -= mtd->erasesize; | |
1280 | ||
6a8214aa | 1281 | nand_get_device(mtd, FL_UNLOCKING); |
7d70f334 VS |
1282 | |
1283 | /* Shift to get chip number */ | |
1284 | chipnr = ofs >> chip->chip_shift; | |
1285 | ||
57d3a9a8 WD |
1286 | /* |
1287 | * Reset the chip. | |
1288 | * If we want to check the WP through READ STATUS and check the bit 7 | |
1289 | * we must reset the chip | |
1290 | * some operation can also clear the bit 7 of status register | |
1291 | * eg. erase/program a locked block | |
1292 | */ | |
73f907fd BB |
1293 | nand_reset(chip, chipnr); |
1294 | ||
1295 | chip->select_chip(mtd, chipnr); | |
57d3a9a8 | 1296 | |
7d70f334 VS |
1297 | /* Check, if it is write protected */ |
1298 | if (nand_check_wp(mtd)) { | |
289c0522 | 1299 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
1300 | __func__); |
1301 | ret = -EIO; | |
1302 | goto out; | |
1303 | } | |
1304 | ||
1305 | ret = __nand_unlock(mtd, ofs, len, 0); | |
1306 | ||
1307 | out: | |
b0bb6903 | 1308 | chip->select_chip(mtd, -1); |
7d70f334 VS |
1309 | nand_release_device(mtd); |
1310 | ||
1311 | return ret; | |
1312 | } | |
7351d3a5 | 1313 | EXPORT_SYMBOL(nand_unlock); |
7d70f334 VS |
1314 | |
1315 | /** | |
b6d676db | 1316 | * nand_lock - [REPLACEABLE] locks all blocks present in the device |
b6d676db RD |
1317 | * @mtd: mtd info |
1318 | * @ofs: offset to start unlock from | |
1319 | * @len: length to unlock | |
7d70f334 | 1320 | * |
8b6e50c9 BN |
1321 | * This feature is not supported in many NAND parts. 'Micron' NAND parts do |
1322 | * have this feature, but it allows only to lock all blocks, not for specified | |
1323 | * range for block. Implementing 'lock' feature by making use of 'unlock', for | |
1324 | * now. | |
7d70f334 | 1325 | * |
8b6e50c9 | 1326 | * Returns lock status. |
7d70f334 VS |
1327 | */ |
1328 | int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
1329 | { | |
1330 | int ret = 0; | |
1331 | int chipnr, status, page; | |
862eba51 | 1332 | struct nand_chip *chip = mtd_to_nand(mtd); |
7d70f334 | 1333 | |
289c0522 | 1334 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
1335 | __func__, (unsigned long long)ofs, len); |
1336 | ||
1337 | if (check_offs_len(mtd, ofs, len)) | |
b1a2348a | 1338 | return -EINVAL; |
7d70f334 | 1339 | |
6a8214aa | 1340 | nand_get_device(mtd, FL_LOCKING); |
7d70f334 VS |
1341 | |
1342 | /* Shift to get chip number */ | |
1343 | chipnr = ofs >> chip->chip_shift; | |
1344 | ||
57d3a9a8 WD |
1345 | /* |
1346 | * Reset the chip. | |
1347 | * If we want to check the WP through READ STATUS and check the bit 7 | |
1348 | * we must reset the chip | |
1349 | * some operation can also clear the bit 7 of status register | |
1350 | * eg. erase/program a locked block | |
1351 | */ | |
73f907fd BB |
1352 | nand_reset(chip, chipnr); |
1353 | ||
1354 | chip->select_chip(mtd, chipnr); | |
57d3a9a8 | 1355 | |
7d70f334 VS |
1356 | /* Check, if it is write protected */ |
1357 | if (nand_check_wp(mtd)) { | |
289c0522 | 1358 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
1359 | __func__); |
1360 | status = MTD_ERASE_FAILED; | |
1361 | ret = -EIO; | |
1362 | goto out; | |
1363 | } | |
1364 | ||
1365 | /* Submit address of first page to lock */ | |
1366 | page = ofs >> chip->page_shift; | |
1367 | chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); | |
1368 | ||
1369 | /* Call wait ready function */ | |
1370 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 1371 | /* See if device thinks it succeeded */ |
74830966 | 1372 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 1373 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
1374 | __func__, status); |
1375 | ret = -EIO; | |
1376 | goto out; | |
1377 | } | |
1378 | ||
1379 | ret = __nand_unlock(mtd, ofs, len, 0x1); | |
1380 | ||
1381 | out: | |
b0bb6903 | 1382 | chip->select_chip(mtd, -1); |
7d70f334 VS |
1383 | nand_release_device(mtd); |
1384 | ||
1385 | return ret; | |
1386 | } | |
7351d3a5 | 1387 | EXPORT_SYMBOL(nand_lock); |
7d70f334 | 1388 | |
730a43fb BB |
1389 | /** |
1390 | * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data | |
1391 | * @buf: buffer to test | |
1392 | * @len: buffer length | |
1393 | * @bitflips_threshold: maximum number of bitflips | |
1394 | * | |
1395 | * Check if a buffer contains only 0xff, which means the underlying region | |
1396 | * has been erased and is ready to be programmed. | |
1397 | * The bitflips_threshold specify the maximum number of bitflips before | |
1398 | * considering the region is not erased. | |
1399 | * Note: The logic of this function has been extracted from the memweight | |
1400 | * implementation, except that nand_check_erased_buf function exit before | |
1401 | * testing the whole buffer if the number of bitflips exceed the | |
1402 | * bitflips_threshold value. | |
1403 | * | |
1404 | * Returns a positive number of bitflips less than or equal to | |
1405 | * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the | |
1406 | * threshold. | |
1407 | */ | |
1408 | static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold) | |
1409 | { | |
1410 | const unsigned char *bitmap = buf; | |
1411 | int bitflips = 0; | |
1412 | int weight; | |
1413 | ||
1414 | for (; len && ((uintptr_t)bitmap) % sizeof(long); | |
1415 | len--, bitmap++) { | |
1416 | weight = hweight8(*bitmap); | |
1417 | bitflips += BITS_PER_BYTE - weight; | |
1418 | if (unlikely(bitflips > bitflips_threshold)) | |
1419 | return -EBADMSG; | |
1420 | } | |
1421 | ||
1422 | for (; len >= sizeof(long); | |
1423 | len -= sizeof(long), bitmap += sizeof(long)) { | |
1424 | weight = hweight_long(*((unsigned long *)bitmap)); | |
1425 | bitflips += BITS_PER_LONG - weight; | |
1426 | if (unlikely(bitflips > bitflips_threshold)) | |
1427 | return -EBADMSG; | |
1428 | } | |
1429 | ||
1430 | for (; len > 0; len--, bitmap++) { | |
1431 | weight = hweight8(*bitmap); | |
1432 | bitflips += BITS_PER_BYTE - weight; | |
1433 | if (unlikely(bitflips > bitflips_threshold)) | |
1434 | return -EBADMSG; | |
1435 | } | |
1436 | ||
1437 | return bitflips; | |
1438 | } | |
1439 | ||
1440 | /** | |
1441 | * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only | |
1442 | * 0xff data | |
1443 | * @data: data buffer to test | |
1444 | * @datalen: data length | |
1445 | * @ecc: ECC buffer | |
1446 | * @ecclen: ECC length | |
1447 | * @extraoob: extra OOB buffer | |
1448 | * @extraooblen: extra OOB length | |
1449 | * @bitflips_threshold: maximum number of bitflips | |
1450 | * | |
1451 | * Check if a data buffer and its associated ECC and OOB data contains only | |
1452 | * 0xff pattern, which means the underlying region has been erased and is | |
1453 | * ready to be programmed. | |
1454 | * The bitflips_threshold specify the maximum number of bitflips before | |
1455 | * considering the region as not erased. | |
1456 | * | |
1457 | * Note: | |
1458 | * 1/ ECC algorithms are working on pre-defined block sizes which are usually | |
1459 | * different from the NAND page size. When fixing bitflips, ECC engines will | |
1460 | * report the number of errors per chunk, and the NAND core infrastructure | |
1461 | * expect you to return the maximum number of bitflips for the whole page. | |
1462 | * This is why you should always use this function on a single chunk and | |
1463 | * not on the whole page. After checking each chunk you should update your | |
1464 | * max_bitflips value accordingly. | |
1465 | * 2/ When checking for bitflips in erased pages you should not only check | |
1466 | * the payload data but also their associated ECC data, because a user might | |
1467 | * have programmed almost all bits to 1 but a few. In this case, we | |
1468 | * shouldn't consider the chunk as erased, and checking ECC bytes prevent | |
1469 | * this case. | |
1470 | * 3/ The extraoob argument is optional, and should be used if some of your OOB | |
1471 | * data are protected by the ECC engine. | |
1472 | * It could also be used if you support subpages and want to attach some | |
1473 | * extra OOB data to an ECC chunk. | |
1474 | * | |
1475 | * Returns a positive number of bitflips less than or equal to | |
1476 | * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the | |
1477 | * threshold. In case of success, the passed buffers are filled with 0xff. | |
1478 | */ | |
1479 | int nand_check_erased_ecc_chunk(void *data, int datalen, | |
1480 | void *ecc, int ecclen, | |
1481 | void *extraoob, int extraooblen, | |
1482 | int bitflips_threshold) | |
1483 | { | |
1484 | int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0; | |
1485 | ||
1486 | data_bitflips = nand_check_erased_buf(data, datalen, | |
1487 | bitflips_threshold); | |
1488 | if (data_bitflips < 0) | |
1489 | return data_bitflips; | |
1490 | ||
1491 | bitflips_threshold -= data_bitflips; | |
1492 | ||
1493 | ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold); | |
1494 | if (ecc_bitflips < 0) | |
1495 | return ecc_bitflips; | |
1496 | ||
1497 | bitflips_threshold -= ecc_bitflips; | |
1498 | ||
1499 | extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen, | |
1500 | bitflips_threshold); | |
1501 | if (extraoob_bitflips < 0) | |
1502 | return extraoob_bitflips; | |
1503 | ||
1504 | if (data_bitflips) | |
1505 | memset(data, 0xff, datalen); | |
1506 | ||
1507 | if (ecc_bitflips) | |
1508 | memset(ecc, 0xff, ecclen); | |
1509 | ||
1510 | if (extraoob_bitflips) | |
1511 | memset(extraoob, 0xff, extraooblen); | |
1512 | ||
1513 | return data_bitflips + ecc_bitflips + extraoob_bitflips; | |
1514 | } | |
1515 | EXPORT_SYMBOL(nand_check_erased_ecc_chunk); | |
1516 | ||
8593fbc6 | 1517 | /** |
7854d3f7 | 1518 | * nand_read_page_raw - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1519 | * @mtd: mtd info structure |
1520 | * @chip: nand chip info structure | |
1521 | * @buf: buffer to store read data | |
1fbb938d | 1522 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1523 | * @page: page number to read |
52ff49df | 1524 | * |
7854d3f7 | 1525 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 TG |
1526 | */ |
1527 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1528 | uint8_t *buf, int oob_required, int page) |
8593fbc6 TG |
1529 | { |
1530 | chip->read_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
1531 | if (oob_required) |
1532 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
8593fbc6 TG |
1533 | return 0; |
1534 | } | |
1535 | ||
52ff49df | 1536 | /** |
7854d3f7 | 1537 | * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1538 | * @mtd: mtd info structure |
1539 | * @chip: nand chip info structure | |
1540 | * @buf: buffer to store read data | |
1fbb938d | 1541 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1542 | * @page: page number to read |
52ff49df DB |
1543 | * |
1544 | * We need a special oob layout and handling even when OOB isn't used. | |
1545 | */ | |
7351d3a5 | 1546 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
1547 | struct nand_chip *chip, uint8_t *buf, |
1548 | int oob_required, int page) | |
52ff49df DB |
1549 | { |
1550 | int eccsize = chip->ecc.size; | |
1551 | int eccbytes = chip->ecc.bytes; | |
1552 | uint8_t *oob = chip->oob_poi; | |
1553 | int steps, size; | |
1554 | ||
1555 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1556 | chip->read_buf(mtd, buf, eccsize); | |
1557 | buf += eccsize; | |
1558 | ||
1559 | if (chip->ecc.prepad) { | |
1560 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1561 | oob += chip->ecc.prepad; | |
1562 | } | |
1563 | ||
1564 | chip->read_buf(mtd, oob, eccbytes); | |
1565 | oob += eccbytes; | |
1566 | ||
1567 | if (chip->ecc.postpad) { | |
1568 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1569 | oob += chip->ecc.postpad; | |
1570 | } | |
1571 | } | |
1572 | ||
1573 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1574 | if (size) | |
1575 | chip->read_buf(mtd, oob, size); | |
1576 | ||
1577 | return 0; | |
1578 | } | |
1579 | ||
1da177e4 | 1580 | /** |
7854d3f7 | 1581 | * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function |
8b6e50c9 BN |
1582 | * @mtd: mtd info structure |
1583 | * @chip: nand chip info structure | |
1584 | * @buf: buffer to store read data | |
1fbb938d | 1585 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1586 | * @page: page number to read |
068e3c0a | 1587 | */ |
f5bbdacc | 1588 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1589 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1590 | { |
846031d3 | 1591 | int i, eccsize = chip->ecc.size, ret; |
f5bbdacc TG |
1592 | int eccbytes = chip->ecc.bytes; |
1593 | int eccsteps = chip->ecc.steps; | |
1594 | uint8_t *p = buf; | |
4bf63fcb DW |
1595 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1596 | uint8_t *ecc_code = chip->buffers->ecccode; | |
3f91e94f | 1597 | unsigned int max_bitflips = 0; |
f5bbdacc | 1598 | |
1fbb938d | 1599 | chip->ecc.read_page_raw(mtd, chip, buf, 1, page); |
f5bbdacc TG |
1600 | |
1601 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1602 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1603 | ||
846031d3 BB |
1604 | ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, |
1605 | chip->ecc.total); | |
1606 | if (ret) | |
1607 | return ret; | |
f5bbdacc TG |
1608 | |
1609 | eccsteps = chip->ecc.steps; | |
1610 | p = buf; | |
1611 | ||
1612 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1613 | int stat; | |
1614 | ||
1615 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
3f91e94f | 1616 | if (stat < 0) { |
f5bbdacc | 1617 | mtd->ecc_stats.failed++; |
3f91e94f | 1618 | } else { |
f5bbdacc | 1619 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1620 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1621 | } | |
f5bbdacc | 1622 | } |
3f91e94f | 1623 | return max_bitflips; |
22c60f5f | 1624 | } |
1da177e4 | 1625 | |
3d459559 | 1626 | /** |
837a6ba4 | 1627 | * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function |
8b6e50c9 BN |
1628 | * @mtd: mtd info structure |
1629 | * @chip: nand chip info structure | |
1630 | * @data_offs: offset of requested data within the page | |
1631 | * @readlen: data length | |
1632 | * @bufpoi: buffer to store read data | |
e004debd | 1633 | * @page: page number to read |
3d459559 | 1634 | */ |
7351d3a5 | 1635 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, |
e004debd HS |
1636 | uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi, |
1637 | int page) | |
3d459559 | 1638 | { |
846031d3 | 1639 | int start_step, end_step, num_steps, ret; |
3d459559 AK |
1640 | uint8_t *p; |
1641 | int data_col_addr, i, gaps = 0; | |
1642 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
1643 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
846031d3 | 1644 | int index, section = 0; |
3f91e94f | 1645 | unsigned int max_bitflips = 0; |
846031d3 | 1646 | struct mtd_oob_region oobregion = { }; |
3d459559 | 1647 | |
7854d3f7 | 1648 | /* Column address within the page aligned to ECC size (256bytes) */ |
3d459559 AK |
1649 | start_step = data_offs / chip->ecc.size; |
1650 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
1651 | num_steps = end_step - start_step + 1; | |
4a4163ca | 1652 | index = start_step * chip->ecc.bytes; |
3d459559 | 1653 | |
8b6e50c9 | 1654 | /* Data size aligned to ECC ecc.size */ |
3d459559 AK |
1655 | datafrag_len = num_steps * chip->ecc.size; |
1656 | eccfrag_len = num_steps * chip->ecc.bytes; | |
1657 | ||
1658 | data_col_addr = start_step * chip->ecc.size; | |
1659 | /* If we read not a page aligned data */ | |
1660 | if (data_col_addr != 0) | |
1661 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); | |
1662 | ||
1663 | p = bufpoi + data_col_addr; | |
1664 | chip->read_buf(mtd, p, datafrag_len); | |
1665 | ||
8b6e50c9 | 1666 | /* Calculate ECC */ |
3d459559 AK |
1667 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) |
1668 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); | |
1669 | ||
8b6e50c9 BN |
1670 | /* |
1671 | * The performance is faster if we position offsets according to | |
7854d3f7 | 1672 | * ecc.pos. Let's make sure that there are no gaps in ECC positions. |
8b6e50c9 | 1673 | */ |
846031d3 BB |
1674 | ret = mtd_ooblayout_find_eccregion(mtd, index, §ion, &oobregion); |
1675 | if (ret) | |
1676 | return ret; | |
1677 | ||
1678 | if (oobregion.length < eccfrag_len) | |
1679 | gaps = 1; | |
1680 | ||
3d459559 AK |
1681 | if (gaps) { |
1682 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1683 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1684 | } else { | |
8b6e50c9 | 1685 | /* |
7854d3f7 | 1686 | * Send the command to read the particular ECC bytes take care |
8b6e50c9 BN |
1687 | * about buswidth alignment in read_buf. |
1688 | */ | |
846031d3 | 1689 | aligned_pos = oobregion.offset & ~(busw - 1); |
3d459559 | 1690 | aligned_len = eccfrag_len; |
846031d3 | 1691 | if (oobregion.offset & (busw - 1)) |
3d459559 | 1692 | aligned_len++; |
846031d3 BB |
1693 | if ((oobregion.offset + (num_steps * chip->ecc.bytes)) & |
1694 | (busw - 1)) | |
3d459559 AK |
1695 | aligned_len++; |
1696 | ||
7351d3a5 | 1697 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, |
846031d3 | 1698 | mtd->writesize + aligned_pos, -1); |
3d459559 AK |
1699 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); |
1700 | } | |
1701 | ||
846031d3 BB |
1702 | ret = mtd_ooblayout_get_eccbytes(mtd, chip->buffers->ecccode, |
1703 | chip->oob_poi, index, eccfrag_len); | |
1704 | if (ret) | |
1705 | return ret; | |
3d459559 AK |
1706 | |
1707 | p = bufpoi + data_col_addr; | |
1708 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
1709 | int stat; | |
1710 | ||
7351d3a5 FF |
1711 | stat = chip->ecc.correct(mtd, p, |
1712 | &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); | |
40cbe6ee BB |
1713 | if (stat == -EBADMSG && |
1714 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
1715 | /* check for empty pages with bitflips */ | |
1716 | stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, | |
1717 | &chip->buffers->ecccode[i], | |
1718 | chip->ecc.bytes, | |
1719 | NULL, 0, | |
1720 | chip->ecc.strength); | |
1721 | } | |
1722 | ||
3f91e94f | 1723 | if (stat < 0) { |
3d459559 | 1724 | mtd->ecc_stats.failed++; |
3f91e94f | 1725 | } else { |
3d459559 | 1726 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1727 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1728 | } | |
3d459559 | 1729 | } |
3f91e94f | 1730 | return max_bitflips; |
3d459559 AK |
1731 | } |
1732 | ||
068e3c0a | 1733 | /** |
7854d3f7 | 1734 | * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function |
8b6e50c9 BN |
1735 | * @mtd: mtd info structure |
1736 | * @chip: nand chip info structure | |
1737 | * @buf: buffer to store read data | |
1fbb938d | 1738 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1739 | * @page: page number to read |
068e3c0a | 1740 | * |
7854d3f7 | 1741 | * Not for syndrome calculating ECC controllers which need a special oob layout. |
068e3c0a | 1742 | */ |
f5bbdacc | 1743 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1744 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1745 | { |
846031d3 | 1746 | int i, eccsize = chip->ecc.size, ret; |
f5bbdacc TG |
1747 | int eccbytes = chip->ecc.bytes; |
1748 | int eccsteps = chip->ecc.steps; | |
1749 | uint8_t *p = buf; | |
4bf63fcb DW |
1750 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1751 | uint8_t *ecc_code = chip->buffers->ecccode; | |
3f91e94f | 1752 | unsigned int max_bitflips = 0; |
f5bbdacc TG |
1753 | |
1754 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1755 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1756 | chip->read_buf(mtd, p, eccsize); | |
1757 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 1758 | } |
f75e5097 | 1759 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 1760 | |
846031d3 BB |
1761 | ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, |
1762 | chip->ecc.total); | |
1763 | if (ret) | |
1764 | return ret; | |
1da177e4 | 1765 | |
f5bbdacc TG |
1766 | eccsteps = chip->ecc.steps; |
1767 | p = buf; | |
61b03bd7 | 1768 | |
f5bbdacc TG |
1769 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1770 | int stat; | |
1da177e4 | 1771 | |
f5bbdacc | 1772 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
40cbe6ee BB |
1773 | if (stat == -EBADMSG && |
1774 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
1775 | /* check for empty pages with bitflips */ | |
1776 | stat = nand_check_erased_ecc_chunk(p, eccsize, | |
1777 | &ecc_code[i], eccbytes, | |
1778 | NULL, 0, | |
1779 | chip->ecc.strength); | |
1780 | } | |
1781 | ||
3f91e94f | 1782 | if (stat < 0) { |
f5bbdacc | 1783 | mtd->ecc_stats.failed++; |
3f91e94f | 1784 | } else { |
f5bbdacc | 1785 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1786 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1787 | } | |
f5bbdacc | 1788 | } |
3f91e94f | 1789 | return max_bitflips; |
f5bbdacc | 1790 | } |
1da177e4 | 1791 | |
6e0cb135 | 1792 | /** |
7854d3f7 | 1793 | * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first |
8b6e50c9 BN |
1794 | * @mtd: mtd info structure |
1795 | * @chip: nand chip info structure | |
1796 | * @buf: buffer to store read data | |
1fbb938d | 1797 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1798 | * @page: page number to read |
6e0cb135 | 1799 | * |
8b6e50c9 BN |
1800 | * Hardware ECC for large page chips, require OOB to be read first. For this |
1801 | * ECC mode, the write_page method is re-used from ECC_HW. These methods | |
1802 | * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with | |
1803 | * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from | |
1804 | * the data area, by overwriting the NAND manufacturer bad block markings. | |
6e0cb135 SN |
1805 | */ |
1806 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1fbb938d | 1807 | struct nand_chip *chip, uint8_t *buf, int oob_required, int page) |
6e0cb135 | 1808 | { |
846031d3 | 1809 | int i, eccsize = chip->ecc.size, ret; |
6e0cb135 SN |
1810 | int eccbytes = chip->ecc.bytes; |
1811 | int eccsteps = chip->ecc.steps; | |
1812 | uint8_t *p = buf; | |
1813 | uint8_t *ecc_code = chip->buffers->ecccode; | |
6e0cb135 | 1814 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
3f91e94f | 1815 | unsigned int max_bitflips = 0; |
6e0cb135 SN |
1816 | |
1817 | /* Read the OOB area first */ | |
1818 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1819 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1820 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1821 | ||
846031d3 BB |
1822 | ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, |
1823 | chip->ecc.total); | |
1824 | if (ret) | |
1825 | return ret; | |
6e0cb135 SN |
1826 | |
1827 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1828 | int stat; | |
1829 | ||
1830 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1831 | chip->read_buf(mtd, p, eccsize); | |
1832 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1833 | ||
1834 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
40cbe6ee BB |
1835 | if (stat == -EBADMSG && |
1836 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
1837 | /* check for empty pages with bitflips */ | |
1838 | stat = nand_check_erased_ecc_chunk(p, eccsize, | |
1839 | &ecc_code[i], eccbytes, | |
1840 | NULL, 0, | |
1841 | chip->ecc.strength); | |
1842 | } | |
1843 | ||
3f91e94f | 1844 | if (stat < 0) { |
6e0cb135 | 1845 | mtd->ecc_stats.failed++; |
3f91e94f | 1846 | } else { |
6e0cb135 | 1847 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1848 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1849 | } | |
6e0cb135 | 1850 | } |
3f91e94f | 1851 | return max_bitflips; |
6e0cb135 SN |
1852 | } |
1853 | ||
f5bbdacc | 1854 | /** |
7854d3f7 | 1855 | * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read |
8b6e50c9 BN |
1856 | * @mtd: mtd info structure |
1857 | * @chip: nand chip info structure | |
1858 | * @buf: buffer to store read data | |
1fbb938d | 1859 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1860 | * @page: page number to read |
f5bbdacc | 1861 | * |
8b6e50c9 BN |
1862 | * The hw generator calculates the error syndrome automatically. Therefore we |
1863 | * need a special oob layout and handling. | |
f5bbdacc TG |
1864 | */ |
1865 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1866 | uint8_t *buf, int oob_required, int page) |
f5bbdacc TG |
1867 | { |
1868 | int i, eccsize = chip->ecc.size; | |
1869 | int eccbytes = chip->ecc.bytes; | |
1870 | int eccsteps = chip->ecc.steps; | |
40cbe6ee | 1871 | int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad; |
f5bbdacc | 1872 | uint8_t *p = buf; |
f75e5097 | 1873 | uint8_t *oob = chip->oob_poi; |
3f91e94f | 1874 | unsigned int max_bitflips = 0; |
1da177e4 | 1875 | |
f5bbdacc TG |
1876 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1877 | int stat; | |
61b03bd7 | 1878 | |
f5bbdacc TG |
1879 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
1880 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 1881 | |
f5bbdacc TG |
1882 | if (chip->ecc.prepad) { |
1883 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1884 | oob += chip->ecc.prepad; | |
1885 | } | |
1da177e4 | 1886 | |
f5bbdacc TG |
1887 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1888 | chip->read_buf(mtd, oob, eccbytes); | |
1889 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 1890 | |
f5bbdacc | 1891 | oob += eccbytes; |
1da177e4 | 1892 | |
f5bbdacc TG |
1893 | if (chip->ecc.postpad) { |
1894 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1895 | oob += chip->ecc.postpad; | |
61b03bd7 | 1896 | } |
40cbe6ee BB |
1897 | |
1898 | if (stat == -EBADMSG && | |
1899 | (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { | |
1900 | /* check for empty pages with bitflips */ | |
1901 | stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, | |
1902 | oob - eccpadbytes, | |
1903 | eccpadbytes, | |
1904 | NULL, 0, | |
1905 | chip->ecc.strength); | |
1906 | } | |
1907 | ||
1908 | if (stat < 0) { | |
1909 | mtd->ecc_stats.failed++; | |
1910 | } else { | |
1911 | mtd->ecc_stats.corrected += stat; | |
1912 | max_bitflips = max_t(unsigned int, max_bitflips, stat); | |
1913 | } | |
f5bbdacc | 1914 | } |
1da177e4 | 1915 | |
f5bbdacc | 1916 | /* Calculate remaining oob bytes */ |
7e4178f9 | 1917 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
1918 | if (i) |
1919 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 1920 | |
3f91e94f | 1921 | return max_bitflips; |
f5bbdacc | 1922 | } |
1da177e4 | 1923 | |
f5bbdacc | 1924 | /** |
7854d3f7 | 1925 | * nand_transfer_oob - [INTERN] Transfer oob to client buffer |
846031d3 | 1926 | * @mtd: mtd info structure |
8b6e50c9 BN |
1927 | * @oob: oob destination address |
1928 | * @ops: oob ops structure | |
1929 | * @len: size of oob to transfer | |
8593fbc6 | 1930 | */ |
846031d3 | 1931 | static uint8_t *nand_transfer_oob(struct mtd_info *mtd, uint8_t *oob, |
7014568b | 1932 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 1933 | { |
846031d3 BB |
1934 | struct nand_chip *chip = mtd_to_nand(mtd); |
1935 | int ret; | |
1936 | ||
f8ac0414 | 1937 | switch (ops->mode) { |
8593fbc6 | 1938 | |
0612b9dd BN |
1939 | case MTD_OPS_PLACE_OOB: |
1940 | case MTD_OPS_RAW: | |
8593fbc6 TG |
1941 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); |
1942 | return oob + len; | |
1943 | ||
846031d3 BB |
1944 | case MTD_OPS_AUTO_OOB: |
1945 | ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi, | |
1946 | ops->ooboffs, len); | |
1947 | BUG_ON(ret); | |
1948 | return oob + len; | |
1949 | ||
8593fbc6 TG |
1950 | default: |
1951 | BUG(); | |
1952 | } | |
1953 | return NULL; | |
1954 | } | |
1955 | ||
ba84fb59 BN |
1956 | /** |
1957 | * nand_setup_read_retry - [INTERN] Set the READ RETRY mode | |
1958 | * @mtd: MTD device structure | |
1959 | * @retry_mode: the retry mode to use | |
1960 | * | |
1961 | * Some vendors supply a special command to shift the Vt threshold, to be used | |
1962 | * when there are too many bitflips in a page (i.e., ECC error). After setting | |
1963 | * a new threshold, the host should retry reading the page. | |
1964 | */ | |
1965 | static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) | |
1966 | { | |
862eba51 | 1967 | struct nand_chip *chip = mtd_to_nand(mtd); |
ba84fb59 BN |
1968 | |
1969 | pr_debug("setting READ RETRY mode %d\n", retry_mode); | |
1970 | ||
1971 | if (retry_mode >= chip->read_retries) | |
1972 | return -EINVAL; | |
1973 | ||
1974 | if (!chip->setup_read_retry) | |
1975 | return -EOPNOTSUPP; | |
1976 | ||
1977 | return chip->setup_read_retry(mtd, retry_mode); | |
1978 | } | |
1979 | ||
8593fbc6 | 1980 | /** |
7854d3f7 | 1981 | * nand_do_read_ops - [INTERN] Read data with ECC |
8b6e50c9 BN |
1982 | * @mtd: MTD device structure |
1983 | * @from: offset to read from | |
1984 | * @ops: oob ops structure | |
f5bbdacc TG |
1985 | * |
1986 | * Internal function. Called with chip held. | |
1987 | */ | |
8593fbc6 TG |
1988 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
1989 | struct mtd_oob_ops *ops) | |
f5bbdacc | 1990 | { |
e47f3db4 | 1991 | int chipnr, page, realpage, col, bytes, aligned, oob_required; |
862eba51 | 1992 | struct nand_chip *chip = mtd_to_nand(mtd); |
f5bbdacc | 1993 | int ret = 0; |
8593fbc6 | 1994 | uint32_t readlen = ops->len; |
7014568b | 1995 | uint32_t oobreadlen = ops->ooblen; |
29f1058a | 1996 | uint32_t max_oobsize = mtd_oobavail(mtd, ops); |
9aca334e | 1997 | |
8593fbc6 | 1998 | uint8_t *bufpoi, *oob, *buf; |
66507c7b | 1999 | int use_bufpoi; |
edbc4540 | 2000 | unsigned int max_bitflips = 0; |
ba84fb59 | 2001 | int retry_mode = 0; |
b72f3dfb | 2002 | bool ecc_fail = false; |
1da177e4 | 2003 | |
f5bbdacc TG |
2004 | chipnr = (int)(from >> chip->chip_shift); |
2005 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 2006 | |
f5bbdacc TG |
2007 | realpage = (int)(from >> chip->page_shift); |
2008 | page = realpage & chip->pagemask; | |
1da177e4 | 2009 | |
f5bbdacc | 2010 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 2011 | |
8593fbc6 TG |
2012 | buf = ops->datbuf; |
2013 | oob = ops->oobbuf; | |
e47f3db4 | 2014 | oob_required = oob ? 1 : 0; |
8593fbc6 | 2015 | |
f8ac0414 | 2016 | while (1) { |
b72f3dfb BN |
2017 | unsigned int ecc_failures = mtd->ecc_stats.failed; |
2018 | ||
f5bbdacc TG |
2019 | bytes = min(mtd->writesize - col, readlen); |
2020 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 2021 | |
66507c7b KD |
2022 | if (!aligned) |
2023 | use_bufpoi = 1; | |
2024 | else if (chip->options & NAND_USE_BOUNCE_BUFFER) | |
477544c6 MY |
2025 | use_bufpoi = !virt_addr_valid(buf) || |
2026 | !IS_ALIGNED((unsigned long)buf, | |
2027 | chip->buf_align); | |
66507c7b KD |
2028 | else |
2029 | use_bufpoi = 0; | |
2030 | ||
8b6e50c9 | 2031 | /* Is the current page in the buffer? */ |
8593fbc6 | 2032 | if (realpage != chip->pagebuf || oob) { |
66507c7b KD |
2033 | bufpoi = use_bufpoi ? chip->buffers->databuf : buf; |
2034 | ||
2035 | if (use_bufpoi && aligned) | |
2036 | pr_debug("%s: using read bounce buffer for buf@%p\n", | |
2037 | __func__, buf); | |
61b03bd7 | 2038 | |
ba84fb59 | 2039 | read_retry: |
3371d663 MG |
2040 | if (nand_standard_page_accessors(&chip->ecc)) |
2041 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); | |
1da177e4 | 2042 | |
edbc4540 MD |
2043 | /* |
2044 | * Now read the page into the buffer. Absent an error, | |
2045 | * the read methods return max bitflips per ecc step. | |
2046 | */ | |
0612b9dd | 2047 | if (unlikely(ops->mode == MTD_OPS_RAW)) |
1fbb938d | 2048 | ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, |
e47f3db4 BN |
2049 | oob_required, |
2050 | page); | |
a5ff4f10 JW |
2051 | else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && |
2052 | !oob) | |
7351d3a5 | 2053 | ret = chip->ecc.read_subpage(mtd, chip, |
e004debd HS |
2054 | col, bytes, bufpoi, |
2055 | page); | |
956e944c | 2056 | else |
46a8cf2d | 2057 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
e47f3db4 | 2058 | oob_required, page); |
6d77b9d0 | 2059 | if (ret < 0) { |
66507c7b | 2060 | if (use_bufpoi) |
6d77b9d0 BN |
2061 | /* Invalidate page cache */ |
2062 | chip->pagebuf = -1; | |
1da177e4 | 2063 | break; |
6d77b9d0 | 2064 | } |
f5bbdacc TG |
2065 | |
2066 | /* Transfer not aligned data */ | |
66507c7b | 2067 | if (use_bufpoi) { |
a5ff4f10 | 2068 | if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && |
b72f3dfb | 2069 | !(mtd->ecc_stats.failed - ecc_failures) && |
edbc4540 | 2070 | (ops->mode != MTD_OPS_RAW)) { |
3d459559 | 2071 | chip->pagebuf = realpage; |
edbc4540 MD |
2072 | chip->pagebuf_bitflips = ret; |
2073 | } else { | |
6d77b9d0 BN |
2074 | /* Invalidate page cache */ |
2075 | chip->pagebuf = -1; | |
edbc4540 | 2076 | } |
4bf63fcb | 2077 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
2078 | } |
2079 | ||
8593fbc6 | 2080 | if (unlikely(oob)) { |
b64d39d8 ML |
2081 | int toread = min(oobreadlen, max_oobsize); |
2082 | ||
2083 | if (toread) { | |
846031d3 | 2084 | oob = nand_transfer_oob(mtd, |
b64d39d8 ML |
2085 | oob, ops, toread); |
2086 | oobreadlen -= toread; | |
2087 | } | |
8593fbc6 | 2088 | } |
5bc7c33c BN |
2089 | |
2090 | if (chip->options & NAND_NEED_READRDY) { | |
2091 | /* Apply delay or wait for ready/busy pin */ | |
2092 | if (!chip->dev_ready) | |
2093 | udelay(chip->chip_delay); | |
2094 | else | |
2095 | nand_wait_ready(mtd); | |
2096 | } | |
b72f3dfb | 2097 | |
ba84fb59 | 2098 | if (mtd->ecc_stats.failed - ecc_failures) { |
28fa65e6 | 2099 | if (retry_mode + 1 < chip->read_retries) { |
ba84fb59 BN |
2100 | retry_mode++; |
2101 | ret = nand_setup_read_retry(mtd, | |
2102 | retry_mode); | |
2103 | if (ret < 0) | |
2104 | break; | |
2105 | ||
2106 | /* Reset failures; retry */ | |
2107 | mtd->ecc_stats.failed = ecc_failures; | |
2108 | goto read_retry; | |
2109 | } else { | |
2110 | /* No more retry modes; real failure */ | |
2111 | ecc_fail = true; | |
2112 | } | |
2113 | } | |
2114 | ||
2115 | buf += bytes; | |
07604686 | 2116 | max_bitflips = max_t(unsigned int, max_bitflips, ret); |
8593fbc6 | 2117 | } else { |
4bf63fcb | 2118 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 | 2119 | buf += bytes; |
edbc4540 MD |
2120 | max_bitflips = max_t(unsigned int, max_bitflips, |
2121 | chip->pagebuf_bitflips); | |
8593fbc6 | 2122 | } |
1da177e4 | 2123 | |
f5bbdacc | 2124 | readlen -= bytes; |
61b03bd7 | 2125 | |
ba84fb59 BN |
2126 | /* Reset to retry mode 0 */ |
2127 | if (retry_mode) { | |
2128 | ret = nand_setup_read_retry(mtd, 0); | |
2129 | if (ret < 0) | |
2130 | break; | |
2131 | retry_mode = 0; | |
2132 | } | |
2133 | ||
f5bbdacc | 2134 | if (!readlen) |
61b03bd7 | 2135 | break; |
1da177e4 | 2136 | |
8b6e50c9 | 2137 | /* For subsequent reads align to page boundary */ |
1da177e4 LT |
2138 | col = 0; |
2139 | /* Increment page address */ | |
2140 | realpage++; | |
2141 | ||
ace4dfee | 2142 | page = realpage & chip->pagemask; |
1da177e4 LT |
2143 | /* Check, if we cross a chip boundary */ |
2144 | if (!page) { | |
2145 | chipnr++; | |
ace4dfee TG |
2146 | chip->select_chip(mtd, -1); |
2147 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 2148 | } |
1da177e4 | 2149 | } |
b0bb6903 | 2150 | chip->select_chip(mtd, -1); |
1da177e4 | 2151 | |
8593fbc6 | 2152 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
2153 | if (oob) |
2154 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 2155 | |
3f91e94f | 2156 | if (ret < 0) |
f5bbdacc TG |
2157 | return ret; |
2158 | ||
b72f3dfb | 2159 | if (ecc_fail) |
9a1fcdfd TG |
2160 | return -EBADMSG; |
2161 | ||
edbc4540 | 2162 | return max_bitflips; |
f5bbdacc TG |
2163 | } |
2164 | ||
2165 | /** | |
25985edc | 2166 | * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc |
8b6e50c9 BN |
2167 | * @mtd: MTD device structure |
2168 | * @from: offset to read from | |
2169 | * @len: number of bytes to read | |
2170 | * @retlen: pointer to variable to store the number of read bytes | |
2171 | * @buf: the databuffer to put data | |
f5bbdacc | 2172 | * |
8b6e50c9 | 2173 | * Get hold of the chip and call nand_do_read. |
f5bbdacc TG |
2174 | */ |
2175 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
2176 | size_t *retlen, uint8_t *buf) | |
2177 | { | |
4a89ff88 | 2178 | struct mtd_oob_ops ops; |
f5bbdacc TG |
2179 | int ret; |
2180 | ||
6a8214aa | 2181 | nand_get_device(mtd, FL_READING); |
0ec56dc4 | 2182 | memset(&ops, 0, sizeof(ops)); |
4a89ff88 BN |
2183 | ops.len = len; |
2184 | ops.datbuf = buf; | |
11041ae6 | 2185 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 2186 | ret = nand_do_read_ops(mtd, from, &ops); |
4a89ff88 | 2187 | *retlen = ops.retlen; |
f5bbdacc | 2188 | nand_release_device(mtd); |
f5bbdacc | 2189 | return ret; |
1da177e4 LT |
2190 | } |
2191 | ||
7bc3312b | 2192 | /** |
7854d3f7 | 2193 | * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function |
8b6e50c9 BN |
2194 | * @mtd: mtd info structure |
2195 | * @chip: nand chip info structure | |
2196 | * @page: page number to read | |
7bc3312b | 2197 | */ |
9d02fc2a | 2198 | int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page) |
7bc3312b | 2199 | { |
5c2ffb11 | 2200 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); |
7bc3312b | 2201 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
5c2ffb11 | 2202 | return 0; |
7bc3312b | 2203 | } |
9d02fc2a | 2204 | EXPORT_SYMBOL(nand_read_oob_std); |
7bc3312b TG |
2205 | |
2206 | /** | |
7854d3f7 | 2207 | * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC |
7bc3312b | 2208 | * with syndromes |
8b6e50c9 BN |
2209 | * @mtd: mtd info structure |
2210 | * @chip: nand chip info structure | |
2211 | * @page: page number to read | |
7bc3312b | 2212 | */ |
9d02fc2a BB |
2213 | int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, |
2214 | int page) | |
7bc3312b | 2215 | { |
7bc3312b TG |
2216 | int length = mtd->oobsize; |
2217 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
2218 | int eccsize = chip->ecc.size; | |
2ea69d21 | 2219 | uint8_t *bufpoi = chip->oob_poi; |
7bc3312b TG |
2220 | int i, toread, sndrnd = 0, pos; |
2221 | ||
2222 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
2223 | for (i = 0; i < chip->ecc.steps; i++) { | |
2224 | if (sndrnd) { | |
2225 | pos = eccsize + i * (eccsize + chunk); | |
2226 | if (mtd->writesize > 512) | |
2227 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
2228 | else | |
2229 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
2230 | } else | |
2231 | sndrnd = 1; | |
2232 | toread = min_t(int, length, chunk); | |
2233 | chip->read_buf(mtd, bufpoi, toread); | |
2234 | bufpoi += toread; | |
2235 | length -= toread; | |
2236 | } | |
2237 | if (length > 0) | |
2238 | chip->read_buf(mtd, bufpoi, length); | |
2239 | ||
5c2ffb11 | 2240 | return 0; |
7bc3312b | 2241 | } |
9d02fc2a | 2242 | EXPORT_SYMBOL(nand_read_oob_syndrome); |
7bc3312b TG |
2243 | |
2244 | /** | |
7854d3f7 | 2245 | * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function |
8b6e50c9 BN |
2246 | * @mtd: mtd info structure |
2247 | * @chip: nand chip info structure | |
2248 | * @page: page number to write | |
7bc3312b | 2249 | */ |
9d02fc2a | 2250 | int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page) |
7bc3312b TG |
2251 | { |
2252 | int status = 0; | |
2253 | const uint8_t *buf = chip->oob_poi; | |
2254 | int length = mtd->oobsize; | |
2255 | ||
2256 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
2257 | chip->write_buf(mtd, buf, length); | |
2258 | /* Send command to program the OOB data */ | |
2259 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
2260 | ||
2261 | status = chip->waitfunc(mtd, chip); | |
2262 | ||
0d420f9d | 2263 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b | 2264 | } |
9d02fc2a | 2265 | EXPORT_SYMBOL(nand_write_oob_std); |
7bc3312b TG |
2266 | |
2267 | /** | |
7854d3f7 | 2268 | * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC |
8b6e50c9 BN |
2269 | * with syndrome - only for large page flash |
2270 | * @mtd: mtd info structure | |
2271 | * @chip: nand chip info structure | |
2272 | * @page: page number to write | |
7bc3312b | 2273 | */ |
9d02fc2a BB |
2274 | int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, |
2275 | int page) | |
7bc3312b TG |
2276 | { |
2277 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
2278 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
2279 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
2280 | const uint8_t *bufpoi = chip->oob_poi; | |
2281 | ||
2282 | /* | |
2283 | * data-ecc-data-ecc ... ecc-oob | |
2284 | * or | |
2285 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
2286 | */ | |
2287 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
2288 | pos = steps * (eccsize + chunk); | |
2289 | steps = 0; | |
2290 | } else | |
8b0036ee | 2291 | pos = eccsize; |
7bc3312b TG |
2292 | |
2293 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
2294 | for (i = 0; i < steps; i++) { | |
2295 | if (sndcmd) { | |
2296 | if (mtd->writesize <= 512) { | |
2297 | uint32_t fill = 0xFFFFFFFF; | |
2298 | ||
2299 | len = eccsize; | |
2300 | while (len > 0) { | |
2301 | int num = min_t(int, len, 4); | |
2302 | chip->write_buf(mtd, (uint8_t *)&fill, | |
2303 | num); | |
2304 | len -= num; | |
2305 | } | |
2306 | } else { | |
2307 | pos = eccsize + i * (eccsize + chunk); | |
2308 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
2309 | } | |
2310 | } else | |
2311 | sndcmd = 1; | |
2312 | len = min_t(int, length, chunk); | |
2313 | chip->write_buf(mtd, bufpoi, len); | |
2314 | bufpoi += len; | |
2315 | length -= len; | |
2316 | } | |
2317 | if (length > 0) | |
2318 | chip->write_buf(mtd, bufpoi, length); | |
2319 | ||
2320 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
2321 | status = chip->waitfunc(mtd, chip); | |
2322 | ||
2323 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
2324 | } | |
9d02fc2a | 2325 | EXPORT_SYMBOL(nand_write_oob_syndrome); |
7bc3312b | 2326 | |
1da177e4 | 2327 | /** |
7854d3f7 | 2328 | * nand_do_read_oob - [INTERN] NAND read out-of-band |
8b6e50c9 BN |
2329 | * @mtd: MTD device structure |
2330 | * @from: offset to read from | |
2331 | * @ops: oob operations description structure | |
1da177e4 | 2332 | * |
8b6e50c9 | 2333 | * NAND read out-of-band data from the spare area. |
1da177e4 | 2334 | */ |
8593fbc6 TG |
2335 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
2336 | struct mtd_oob_ops *ops) | |
1da177e4 | 2337 | { |
c00a0991 | 2338 | int page, realpage, chipnr; |
862eba51 | 2339 | struct nand_chip *chip = mtd_to_nand(mtd); |
041e4575 | 2340 | struct mtd_ecc_stats stats; |
7014568b VW |
2341 | int readlen = ops->ooblen; |
2342 | int len; | |
7bc3312b | 2343 | uint8_t *buf = ops->oobbuf; |
1951f2f7 | 2344 | int ret = 0; |
61b03bd7 | 2345 | |
289c0522 | 2346 | pr_debug("%s: from = 0x%08Lx, len = %i\n", |
20d8e248 | 2347 | __func__, (unsigned long long)from, readlen); |
1da177e4 | 2348 | |
041e4575 BN |
2349 | stats = mtd->ecc_stats; |
2350 | ||
29f1058a | 2351 | len = mtd_oobavail(mtd, ops); |
03736155 AH |
2352 | |
2353 | if (unlikely(ops->ooboffs >= len)) { | |
289c0522 BN |
2354 | pr_debug("%s: attempt to start read outside oob\n", |
2355 | __func__); | |
03736155 AH |
2356 | return -EINVAL; |
2357 | } | |
2358 | ||
2359 | /* Do not allow reads past end of device */ | |
2360 | if (unlikely(from >= mtd->size || | |
2361 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
2362 | (from >> chip->page_shift)) * len)) { | |
289c0522 BN |
2363 | pr_debug("%s: attempt to read beyond end of device\n", |
2364 | __func__); | |
03736155 AH |
2365 | return -EINVAL; |
2366 | } | |
7014568b | 2367 | |
7314e9e7 | 2368 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 2369 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2370 | |
7314e9e7 TG |
2371 | /* Shift to get page */ |
2372 | realpage = (int)(from >> chip->page_shift); | |
2373 | page = realpage & chip->pagemask; | |
1da177e4 | 2374 | |
f8ac0414 | 2375 | while (1) { |
0612b9dd | 2376 | if (ops->mode == MTD_OPS_RAW) |
1951f2f7 | 2377 | ret = chip->ecc.read_oob_raw(mtd, chip, page); |
c46f6483 | 2378 | else |
1951f2f7 SL |
2379 | ret = chip->ecc.read_oob(mtd, chip, page); |
2380 | ||
2381 | if (ret < 0) | |
2382 | break; | |
7014568b VW |
2383 | |
2384 | len = min(len, readlen); | |
846031d3 | 2385 | buf = nand_transfer_oob(mtd, buf, ops, len); |
8593fbc6 | 2386 | |
5bc7c33c BN |
2387 | if (chip->options & NAND_NEED_READRDY) { |
2388 | /* Apply delay or wait for ready/busy pin */ | |
2389 | if (!chip->dev_ready) | |
2390 | udelay(chip->chip_delay); | |
2391 | else | |
2392 | nand_wait_ready(mtd); | |
2393 | } | |
2394 | ||
7014568b | 2395 | readlen -= len; |
0d420f9d SZ |
2396 | if (!readlen) |
2397 | break; | |
2398 | ||
7314e9e7 TG |
2399 | /* Increment page address */ |
2400 | realpage++; | |
2401 | ||
2402 | page = realpage & chip->pagemask; | |
2403 | /* Check, if we cross a chip boundary */ | |
2404 | if (!page) { | |
2405 | chipnr++; | |
2406 | chip->select_chip(mtd, -1); | |
2407 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2408 | } |
2409 | } | |
b0bb6903 | 2410 | chip->select_chip(mtd, -1); |
1da177e4 | 2411 | |
1951f2f7 SL |
2412 | ops->oobretlen = ops->ooblen - readlen; |
2413 | ||
2414 | if (ret < 0) | |
2415 | return ret; | |
041e4575 BN |
2416 | |
2417 | if (mtd->ecc_stats.failed - stats.failed) | |
2418 | return -EBADMSG; | |
2419 | ||
2420 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
1da177e4 LT |
2421 | } |
2422 | ||
2423 | /** | |
8593fbc6 | 2424 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
8b6e50c9 BN |
2425 | * @mtd: MTD device structure |
2426 | * @from: offset to read from | |
2427 | * @ops: oob operation description structure | |
1da177e4 | 2428 | * |
8b6e50c9 | 2429 | * NAND read data and/or out-of-band data. |
1da177e4 | 2430 | */ |
8593fbc6 TG |
2431 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
2432 | struct mtd_oob_ops *ops) | |
1da177e4 | 2433 | { |
fc6b4d12 | 2434 | int ret; |
8593fbc6 TG |
2435 | |
2436 | ops->retlen = 0; | |
1da177e4 LT |
2437 | |
2438 | /* Do not allow reads past end of device */ | |
7014568b | 2439 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
289c0522 BN |
2440 | pr_debug("%s: attempt to read beyond end of device\n", |
2441 | __func__); | |
1da177e4 LT |
2442 | return -EINVAL; |
2443 | } | |
2444 | ||
fc6b4d12 AS |
2445 | if (ops->mode != MTD_OPS_PLACE_OOB && |
2446 | ops->mode != MTD_OPS_AUTO_OOB && | |
2447 | ops->mode != MTD_OPS_RAW) | |
2448 | return -ENOTSUPP; | |
1da177e4 | 2449 | |
fc6b4d12 | 2450 | nand_get_device(mtd, FL_READING); |
1da177e4 | 2451 | |
8593fbc6 TG |
2452 | if (!ops->datbuf) |
2453 | ret = nand_do_read_oob(mtd, from, ops); | |
2454 | else | |
2455 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 2456 | |
8593fbc6 TG |
2457 | nand_release_device(mtd); |
2458 | return ret; | |
2459 | } | |
61b03bd7 | 2460 | |
1da177e4 | 2461 | |
8593fbc6 | 2462 | /** |
7854d3f7 | 2463 | * nand_write_page_raw - [INTERN] raw page write function |
8b6e50c9 BN |
2464 | * @mtd: mtd info structure |
2465 | * @chip: nand chip info structure | |
2466 | * @buf: data buffer | |
1fbb938d | 2467 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2468 | * @page: page number to write |
52ff49df | 2469 | * |
7854d3f7 | 2470 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 | 2471 | */ |
fdbad98d | 2472 | static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 | 2473 | const uint8_t *buf, int oob_required, int page) |
8593fbc6 TG |
2474 | { |
2475 | chip->write_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
2476 | if (oob_required) |
2477 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
2478 | |
2479 | return 0; | |
1da177e4 LT |
2480 | } |
2481 | ||
52ff49df | 2482 | /** |
7854d3f7 | 2483 | * nand_write_page_raw_syndrome - [INTERN] raw page write function |
8b6e50c9 BN |
2484 | * @mtd: mtd info structure |
2485 | * @chip: nand chip info structure | |
2486 | * @buf: data buffer | |
1fbb938d | 2487 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2488 | * @page: page number to write |
52ff49df DB |
2489 | * |
2490 | * We need a special oob layout and handling even when ECC isn't checked. | |
2491 | */ | |
fdbad98d | 2492 | static int nand_write_page_raw_syndrome(struct mtd_info *mtd, |
7351d3a5 | 2493 | struct nand_chip *chip, |
45aaeff9 BB |
2494 | const uint8_t *buf, int oob_required, |
2495 | int page) | |
52ff49df DB |
2496 | { |
2497 | int eccsize = chip->ecc.size; | |
2498 | int eccbytes = chip->ecc.bytes; | |
2499 | uint8_t *oob = chip->oob_poi; | |
2500 | int steps, size; | |
2501 | ||
2502 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
2503 | chip->write_buf(mtd, buf, eccsize); | |
2504 | buf += eccsize; | |
2505 | ||
2506 | if (chip->ecc.prepad) { | |
2507 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2508 | oob += chip->ecc.prepad; | |
2509 | } | |
2510 | ||
60c3bc1f | 2511 | chip->write_buf(mtd, oob, eccbytes); |
52ff49df DB |
2512 | oob += eccbytes; |
2513 | ||
2514 | if (chip->ecc.postpad) { | |
2515 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2516 | oob += chip->ecc.postpad; | |
2517 | } | |
2518 | } | |
2519 | ||
2520 | size = mtd->oobsize - (oob - chip->oob_poi); | |
2521 | if (size) | |
2522 | chip->write_buf(mtd, oob, size); | |
fdbad98d JW |
2523 | |
2524 | return 0; | |
52ff49df | 2525 | } |
9223a456 | 2526 | /** |
7854d3f7 | 2527 | * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function |
8b6e50c9 BN |
2528 | * @mtd: mtd info structure |
2529 | * @chip: nand chip info structure | |
2530 | * @buf: data buffer | |
1fbb938d | 2531 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2532 | * @page: page number to write |
9223a456 | 2533 | */ |
fdbad98d | 2534 | static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 BB |
2535 | const uint8_t *buf, int oob_required, |
2536 | int page) | |
9223a456 | 2537 | { |
846031d3 | 2538 | int i, eccsize = chip->ecc.size, ret; |
f75e5097 TG |
2539 | int eccbytes = chip->ecc.bytes; |
2540 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2541 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2542 | const uint8_t *p = buf; |
9223a456 | 2543 | |
7854d3f7 | 2544 | /* Software ECC calculation */ |
8593fbc6 TG |
2545 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
2546 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 2547 | |
846031d3 BB |
2548 | ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, |
2549 | chip->ecc.total); | |
2550 | if (ret) | |
2551 | return ret; | |
9223a456 | 2552 | |
45aaeff9 | 2553 | return chip->ecc.write_page_raw(mtd, chip, buf, 1, page); |
f75e5097 | 2554 | } |
9223a456 | 2555 | |
f75e5097 | 2556 | /** |
7854d3f7 | 2557 | * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function |
8b6e50c9 BN |
2558 | * @mtd: mtd info structure |
2559 | * @chip: nand chip info structure | |
2560 | * @buf: data buffer | |
1fbb938d | 2561 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2562 | * @page: page number to write |
f75e5097 | 2563 | */ |
fdbad98d | 2564 | static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
45aaeff9 BB |
2565 | const uint8_t *buf, int oob_required, |
2566 | int page) | |
f75e5097 | 2567 | { |
846031d3 | 2568 | int i, eccsize = chip->ecc.size, ret; |
f75e5097 TG |
2569 | int eccbytes = chip->ecc.bytes; |
2570 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2571 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2572 | const uint8_t *p = buf; |
9223a456 | 2573 | |
f75e5097 TG |
2574 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
2575 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 2576 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 2577 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
2578 | } |
2579 | ||
846031d3 BB |
2580 | ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, |
2581 | chip->ecc.total); | |
2582 | if (ret) | |
2583 | return ret; | |
f75e5097 TG |
2584 | |
2585 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
2586 | |
2587 | return 0; | |
9223a456 TG |
2588 | } |
2589 | ||
837a6ba4 GP |
2590 | |
2591 | /** | |
73c8aaf4 | 2592 | * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write |
837a6ba4 GP |
2593 | * @mtd: mtd info structure |
2594 | * @chip: nand chip info structure | |
d6a95080 | 2595 | * @offset: column address of subpage within the page |
837a6ba4 | 2596 | * @data_len: data length |
d6a95080 | 2597 | * @buf: data buffer |
837a6ba4 | 2598 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2599 | * @page: page number to write |
837a6ba4 GP |
2600 | */ |
2601 | static int nand_write_subpage_hwecc(struct mtd_info *mtd, | |
2602 | struct nand_chip *chip, uint32_t offset, | |
d6a95080 | 2603 | uint32_t data_len, const uint8_t *buf, |
45aaeff9 | 2604 | int oob_required, int page) |
837a6ba4 GP |
2605 | { |
2606 | uint8_t *oob_buf = chip->oob_poi; | |
2607 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
2608 | int ecc_size = chip->ecc.size; | |
2609 | int ecc_bytes = chip->ecc.bytes; | |
2610 | int ecc_steps = chip->ecc.steps; | |
837a6ba4 GP |
2611 | uint32_t start_step = offset / ecc_size; |
2612 | uint32_t end_step = (offset + data_len - 1) / ecc_size; | |
2613 | int oob_bytes = mtd->oobsize / ecc_steps; | |
846031d3 | 2614 | int step, ret; |
837a6ba4 GP |
2615 | |
2616 | for (step = 0; step < ecc_steps; step++) { | |
2617 | /* configure controller for WRITE access */ | |
2618 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
2619 | ||
2620 | /* write data (untouched subpages already masked by 0xFF) */ | |
d6a95080 | 2621 | chip->write_buf(mtd, buf, ecc_size); |
837a6ba4 GP |
2622 | |
2623 | /* mask ECC of un-touched subpages by padding 0xFF */ | |
2624 | if ((step < start_step) || (step > end_step)) | |
2625 | memset(ecc_calc, 0xff, ecc_bytes); | |
2626 | else | |
d6a95080 | 2627 | chip->ecc.calculate(mtd, buf, ecc_calc); |
837a6ba4 GP |
2628 | |
2629 | /* mask OOB of un-touched subpages by padding 0xFF */ | |
2630 | /* if oob_required, preserve OOB metadata of written subpage */ | |
2631 | if (!oob_required || (step < start_step) || (step > end_step)) | |
2632 | memset(oob_buf, 0xff, oob_bytes); | |
2633 | ||
d6a95080 | 2634 | buf += ecc_size; |
837a6ba4 GP |
2635 | ecc_calc += ecc_bytes; |
2636 | oob_buf += oob_bytes; | |
2637 | } | |
2638 | ||
2639 | /* copy calculated ECC for whole page to chip->buffer->oob */ | |
2640 | /* this include masked-value(0xFF) for unwritten subpages */ | |
2641 | ecc_calc = chip->buffers->ecccalc; | |
846031d3 BB |
2642 | ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, |
2643 | chip->ecc.total); | |
2644 | if (ret) | |
2645 | return ret; | |
837a6ba4 GP |
2646 | |
2647 | /* write OOB buffer to NAND device */ | |
2648 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
2649 | ||
2650 | return 0; | |
2651 | } | |
2652 | ||
2653 | ||
61b03bd7 | 2654 | /** |
7854d3f7 | 2655 | * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write |
8b6e50c9 BN |
2656 | * @mtd: mtd info structure |
2657 | * @chip: nand chip info structure | |
2658 | * @buf: data buffer | |
1fbb938d | 2659 | * @oob_required: must write chip->oob_poi to OOB |
45aaeff9 | 2660 | * @page: page number to write |
1da177e4 | 2661 | * |
8b6e50c9 BN |
2662 | * The hw generator calculates the error syndrome automatically. Therefore we |
2663 | * need a special oob layout and handling. | |
f75e5097 | 2664 | */ |
fdbad98d | 2665 | static int nand_write_page_syndrome(struct mtd_info *mtd, |
1fbb938d | 2666 | struct nand_chip *chip, |
45aaeff9 BB |
2667 | const uint8_t *buf, int oob_required, |
2668 | int page) | |
1da177e4 | 2669 | { |
f75e5097 TG |
2670 | int i, eccsize = chip->ecc.size; |
2671 | int eccbytes = chip->ecc.bytes; | |
2672 | int eccsteps = chip->ecc.steps; | |
2673 | const uint8_t *p = buf; | |
2674 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 2675 | |
f75e5097 | 2676 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 2677 | |
f75e5097 TG |
2678 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
2679 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 2680 | |
f75e5097 TG |
2681 | if (chip->ecc.prepad) { |
2682 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2683 | oob += chip->ecc.prepad; | |
2684 | } | |
2685 | ||
2686 | chip->ecc.calculate(mtd, p, oob); | |
2687 | chip->write_buf(mtd, oob, eccbytes); | |
2688 | oob += eccbytes; | |
2689 | ||
2690 | if (chip->ecc.postpad) { | |
2691 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2692 | oob += chip->ecc.postpad; | |
1da177e4 | 2693 | } |
1da177e4 | 2694 | } |
f75e5097 TG |
2695 | |
2696 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 2697 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
2698 | if (i) |
2699 | chip->write_buf(mtd, oob, i); | |
fdbad98d JW |
2700 | |
2701 | return 0; | |
f75e5097 TG |
2702 | } |
2703 | ||
2704 | /** | |
f107d7a4 | 2705 | * nand_write_page - write one page |
8b6e50c9 BN |
2706 | * @mtd: MTD device structure |
2707 | * @chip: NAND chip descriptor | |
837a6ba4 GP |
2708 | * @offset: address offset within the page |
2709 | * @data_len: length of actual data to be written | |
8b6e50c9 | 2710 | * @buf: the data to write |
1fbb938d | 2711 | * @oob_required: must write chip->oob_poi to OOB |
8b6e50c9 BN |
2712 | * @page: page number to write |
2713 | * @cached: cached programming | |
2714 | * @raw: use _raw version of write_page | |
f75e5097 TG |
2715 | */ |
2716 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
837a6ba4 GP |
2717 | uint32_t offset, int data_len, const uint8_t *buf, |
2718 | int oob_required, int page, int cached, int raw) | |
f75e5097 | 2719 | { |
837a6ba4 GP |
2720 | int status, subpage; |
2721 | ||
2722 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && | |
2723 | chip->ecc.write_subpage) | |
2724 | subpage = offset || (data_len < mtd->writesize); | |
2725 | else | |
2726 | subpage = 0; | |
f75e5097 | 2727 | |
3371d663 MG |
2728 | if (nand_standard_page_accessors(&chip->ecc)) |
2729 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
f75e5097 | 2730 | |
956e944c | 2731 | if (unlikely(raw)) |
837a6ba4 | 2732 | status = chip->ecc.write_page_raw(mtd, chip, buf, |
45aaeff9 | 2733 | oob_required, page); |
837a6ba4 GP |
2734 | else if (subpage) |
2735 | status = chip->ecc.write_subpage(mtd, chip, offset, data_len, | |
45aaeff9 | 2736 | buf, oob_required, page); |
956e944c | 2737 | else |
45aaeff9 BB |
2738 | status = chip->ecc.write_page(mtd, chip, buf, oob_required, |
2739 | page); | |
fdbad98d JW |
2740 | |
2741 | if (status < 0) | |
2742 | return status; | |
f75e5097 TG |
2743 | |
2744 | /* | |
7854d3f7 | 2745 | * Cached progamming disabled for now. Not sure if it's worth the |
8b6e50c9 | 2746 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s). |
f75e5097 TG |
2747 | */ |
2748 | cached = 0; | |
2749 | ||
3239a6cd | 2750 | if (!cached || !NAND_HAS_CACHEPROG(chip)) { |
f75e5097 | 2751 | |
3371d663 MG |
2752 | if (nand_standard_page_accessors(&chip->ecc)) |
2753 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
7bc3312b | 2754 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2755 | /* |
2756 | * See if operation failed and additional status checks are | |
8b6e50c9 | 2757 | * available. |
f75e5097 TG |
2758 | */ |
2759 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2760 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
2761 | page); | |
2762 | ||
2763 | if (status & NAND_STATUS_FAIL) | |
2764 | return -EIO; | |
2765 | } else { | |
2766 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
7bc3312b | 2767 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2768 | } |
2769 | ||
f75e5097 | 2770 | return 0; |
1da177e4 LT |
2771 | } |
2772 | ||
8593fbc6 | 2773 | /** |
7854d3f7 | 2774 | * nand_fill_oob - [INTERN] Transfer client buffer to oob |
f722013e | 2775 | * @mtd: MTD device structure |
8b6e50c9 BN |
2776 | * @oob: oob data buffer |
2777 | * @len: oob data write length | |
2778 | * @ops: oob ops structure | |
8593fbc6 | 2779 | */ |
f722013e TAA |
2780 | static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, |
2781 | struct mtd_oob_ops *ops) | |
8593fbc6 | 2782 | { |
862eba51 | 2783 | struct nand_chip *chip = mtd_to_nand(mtd); |
846031d3 | 2784 | int ret; |
f722013e TAA |
2785 | |
2786 | /* | |
2787 | * Initialise to all 0xFF, to avoid the possibility of left over OOB | |
2788 | * data from a previous OOB read. | |
2789 | */ | |
2790 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
2791 | ||
f8ac0414 | 2792 | switch (ops->mode) { |
8593fbc6 | 2793 | |
0612b9dd BN |
2794 | case MTD_OPS_PLACE_OOB: |
2795 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2796 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); |
2797 | return oob + len; | |
2798 | ||
846031d3 BB |
2799 | case MTD_OPS_AUTO_OOB: |
2800 | ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi, | |
2801 | ops->ooboffs, len); | |
2802 | BUG_ON(ret); | |
2803 | return oob + len; | |
2804 | ||
8593fbc6 TG |
2805 | default: |
2806 | BUG(); | |
2807 | } | |
2808 | return NULL; | |
2809 | } | |
2810 | ||
f8ac0414 | 2811 | #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) |
1da177e4 LT |
2812 | |
2813 | /** | |
7854d3f7 | 2814 | * nand_do_write_ops - [INTERN] NAND write with ECC |
8b6e50c9 BN |
2815 | * @mtd: MTD device structure |
2816 | * @to: offset to write to | |
2817 | * @ops: oob operations description structure | |
1da177e4 | 2818 | * |
8b6e50c9 | 2819 | * NAND write with ECC. |
1da177e4 | 2820 | */ |
8593fbc6 TG |
2821 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
2822 | struct mtd_oob_ops *ops) | |
1da177e4 | 2823 | { |
29072b96 | 2824 | int chipnr, realpage, page, blockmask, column; |
862eba51 | 2825 | struct nand_chip *chip = mtd_to_nand(mtd); |
8593fbc6 | 2826 | uint32_t writelen = ops->len; |
782ce79a ML |
2827 | |
2828 | uint32_t oobwritelen = ops->ooblen; | |
29f1058a | 2829 | uint32_t oobmaxlen = mtd_oobavail(mtd, ops); |
782ce79a | 2830 | |
8593fbc6 TG |
2831 | uint8_t *oob = ops->oobbuf; |
2832 | uint8_t *buf = ops->datbuf; | |
837a6ba4 | 2833 | int ret; |
e47f3db4 | 2834 | int oob_required = oob ? 1 : 0; |
1da177e4 | 2835 | |
8593fbc6 | 2836 | ops->retlen = 0; |
29072b96 TG |
2837 | if (!writelen) |
2838 | return 0; | |
1da177e4 | 2839 | |
8b6e50c9 | 2840 | /* Reject writes, which are not page aligned */ |
8593fbc6 | 2841 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
d0370219 BN |
2842 | pr_notice("%s: attempt to write non page aligned data\n", |
2843 | __func__); | |
1da177e4 LT |
2844 | return -EINVAL; |
2845 | } | |
2846 | ||
29072b96 | 2847 | column = to & (mtd->writesize - 1); |
1da177e4 | 2848 | |
6a930961 TG |
2849 | chipnr = (int)(to >> chip->chip_shift); |
2850 | chip->select_chip(mtd, chipnr); | |
2851 | ||
1da177e4 | 2852 | /* Check, if it is write protected */ |
b0bb6903 HS |
2853 | if (nand_check_wp(mtd)) { |
2854 | ret = -EIO; | |
2855 | goto err_out; | |
2856 | } | |
1da177e4 | 2857 | |
f75e5097 TG |
2858 | realpage = (int)(to >> chip->page_shift); |
2859 | page = realpage & chip->pagemask; | |
2860 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
2861 | ||
2862 | /* Invalidate the page cache, when we write to the cached page */ | |
537ab1bd BN |
2863 | if (to <= ((loff_t)chip->pagebuf << chip->page_shift) && |
2864 | ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len)) | |
ace4dfee | 2865 | chip->pagebuf = -1; |
61b03bd7 | 2866 | |
782ce79a | 2867 | /* Don't allow multipage oob writes with offset */ |
b0bb6903 HS |
2868 | if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { |
2869 | ret = -EINVAL; | |
2870 | goto err_out; | |
2871 | } | |
782ce79a | 2872 | |
f8ac0414 | 2873 | while (1) { |
29072b96 | 2874 | int bytes = mtd->writesize; |
f75e5097 | 2875 | int cached = writelen > bytes && page != blockmask; |
29072b96 | 2876 | uint8_t *wbuf = buf; |
66507c7b | 2877 | int use_bufpoi; |
144f4c98 | 2878 | int part_pagewr = (column || writelen < mtd->writesize); |
66507c7b KD |
2879 | |
2880 | if (part_pagewr) | |
2881 | use_bufpoi = 1; | |
2882 | else if (chip->options & NAND_USE_BOUNCE_BUFFER) | |
477544c6 MY |
2883 | use_bufpoi = !virt_addr_valid(buf) || |
2884 | !IS_ALIGNED((unsigned long)buf, | |
2885 | chip->buf_align); | |
66507c7b KD |
2886 | else |
2887 | use_bufpoi = 0; | |
29072b96 | 2888 | |
66507c7b KD |
2889 | /* Partial page write?, or need to use bounce buffer */ |
2890 | if (use_bufpoi) { | |
2891 | pr_debug("%s: using write bounce buffer for buf@%p\n", | |
2892 | __func__, buf); | |
29072b96 | 2893 | cached = 0; |
66507c7b KD |
2894 | if (part_pagewr) |
2895 | bytes = min_t(int, bytes - column, writelen); | |
29072b96 TG |
2896 | chip->pagebuf = -1; |
2897 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
2898 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
2899 | wbuf = chip->buffers->databuf; | |
2900 | } | |
1da177e4 | 2901 | |
782ce79a ML |
2902 | if (unlikely(oob)) { |
2903 | size_t len = min(oobwritelen, oobmaxlen); | |
f722013e | 2904 | oob = nand_fill_oob(mtd, oob, len, ops); |
782ce79a | 2905 | oobwritelen -= len; |
f722013e TAA |
2906 | } else { |
2907 | /* We still need to erase leftover OOB data */ | |
2908 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
782ce79a | 2909 | } |
f107d7a4 BB |
2910 | |
2911 | ret = nand_write_page(mtd, chip, column, bytes, wbuf, | |
2912 | oob_required, page, cached, | |
2913 | (ops->mode == MTD_OPS_RAW)); | |
f75e5097 TG |
2914 | if (ret) |
2915 | break; | |
2916 | ||
2917 | writelen -= bytes; | |
2918 | if (!writelen) | |
2919 | break; | |
2920 | ||
29072b96 | 2921 | column = 0; |
f75e5097 TG |
2922 | buf += bytes; |
2923 | realpage++; | |
2924 | ||
2925 | page = realpage & chip->pagemask; | |
2926 | /* Check, if we cross a chip boundary */ | |
2927 | if (!page) { | |
2928 | chipnr++; | |
2929 | chip->select_chip(mtd, -1); | |
2930 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2931 | } |
2932 | } | |
8593fbc6 | 2933 | |
8593fbc6 | 2934 | ops->retlen = ops->len - writelen; |
7014568b VW |
2935 | if (unlikely(oob)) |
2936 | ops->oobretlen = ops->ooblen; | |
b0bb6903 HS |
2937 | |
2938 | err_out: | |
2939 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
2940 | return ret; |
2941 | } | |
2942 | ||
2af7c653 SK |
2943 | /** |
2944 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
8b6e50c9 BN |
2945 | * @mtd: MTD device structure |
2946 | * @to: offset to write to | |
2947 | * @len: number of bytes to write | |
2948 | * @retlen: pointer to variable to store the number of written bytes | |
2949 | * @buf: the data to write | |
2af7c653 SK |
2950 | * |
2951 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
2952 | * may for example be called by mtdoops when writing an oops while in panic. | |
2953 | */ | |
2954 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
2955 | size_t *retlen, const uint8_t *buf) | |
2956 | { | |
862eba51 | 2957 | struct nand_chip *chip = mtd_to_nand(mtd); |
4a89ff88 | 2958 | struct mtd_oob_ops ops; |
2af7c653 SK |
2959 | int ret; |
2960 | ||
8b6e50c9 | 2961 | /* Wait for the device to get ready */ |
2af7c653 SK |
2962 | panic_nand_wait(mtd, chip, 400); |
2963 | ||
8b6e50c9 | 2964 | /* Grab the device */ |
2af7c653 SK |
2965 | panic_nand_get_device(chip, mtd, FL_WRITING); |
2966 | ||
0ec56dc4 | 2967 | memset(&ops, 0, sizeof(ops)); |
4a89ff88 BN |
2968 | ops.len = len; |
2969 | ops.datbuf = (uint8_t *)buf; | |
11041ae6 | 2970 | ops.mode = MTD_OPS_PLACE_OOB; |
2af7c653 | 2971 | |
4a89ff88 | 2972 | ret = nand_do_write_ops(mtd, to, &ops); |
2af7c653 | 2973 | |
4a89ff88 | 2974 | *retlen = ops.retlen; |
2af7c653 SK |
2975 | return ret; |
2976 | } | |
2977 | ||
f75e5097 | 2978 | /** |
8593fbc6 | 2979 | * nand_write - [MTD Interface] NAND write with ECC |
8b6e50c9 BN |
2980 | * @mtd: MTD device structure |
2981 | * @to: offset to write to | |
2982 | * @len: number of bytes to write | |
2983 | * @retlen: pointer to variable to store the number of written bytes | |
2984 | * @buf: the data to write | |
f75e5097 | 2985 | * |
8b6e50c9 | 2986 | * NAND write with ECC. |
f75e5097 | 2987 | */ |
8593fbc6 TG |
2988 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
2989 | size_t *retlen, const uint8_t *buf) | |
f75e5097 | 2990 | { |
4a89ff88 | 2991 | struct mtd_oob_ops ops; |
f75e5097 TG |
2992 | int ret; |
2993 | ||
6a8214aa | 2994 | nand_get_device(mtd, FL_WRITING); |
0ec56dc4 | 2995 | memset(&ops, 0, sizeof(ops)); |
4a89ff88 BN |
2996 | ops.len = len; |
2997 | ops.datbuf = (uint8_t *)buf; | |
11041ae6 | 2998 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 2999 | ret = nand_do_write_ops(mtd, to, &ops); |
4a89ff88 | 3000 | *retlen = ops.retlen; |
f75e5097 | 3001 | nand_release_device(mtd); |
8593fbc6 | 3002 | return ret; |
f75e5097 | 3003 | } |
7314e9e7 | 3004 | |
1da177e4 | 3005 | /** |
8593fbc6 | 3006 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
8b6e50c9 BN |
3007 | * @mtd: MTD device structure |
3008 | * @to: offset to write to | |
3009 | * @ops: oob operation description structure | |
1da177e4 | 3010 | * |
8b6e50c9 | 3011 | * NAND write out-of-band. |
1da177e4 | 3012 | */ |
8593fbc6 TG |
3013 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
3014 | struct mtd_oob_ops *ops) | |
1da177e4 | 3015 | { |
03736155 | 3016 | int chipnr, page, status, len; |
862eba51 | 3017 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 3018 | |
289c0522 | 3019 | pr_debug("%s: to = 0x%08x, len = %i\n", |
20d8e248 | 3020 | __func__, (unsigned int)to, (int)ops->ooblen); |
1da177e4 | 3021 | |
29f1058a | 3022 | len = mtd_oobavail(mtd, ops); |
03736155 | 3023 | |
1da177e4 | 3024 | /* Do not allow write past end of page */ |
03736155 | 3025 | if ((ops->ooboffs + ops->ooblen) > len) { |
289c0522 BN |
3026 | pr_debug("%s: attempt to write past end of page\n", |
3027 | __func__); | |
1da177e4 LT |
3028 | return -EINVAL; |
3029 | } | |
3030 | ||
03736155 | 3031 | if (unlikely(ops->ooboffs >= len)) { |
289c0522 BN |
3032 | pr_debug("%s: attempt to start write outside oob\n", |
3033 | __func__); | |
03736155 AH |
3034 | return -EINVAL; |
3035 | } | |
3036 | ||
775adc3d | 3037 | /* Do not allow write past end of device */ |
03736155 AH |
3038 | if (unlikely(to >= mtd->size || |
3039 | ops->ooboffs + ops->ooblen > | |
3040 | ((mtd->size >> chip->page_shift) - | |
3041 | (to >> chip->page_shift)) * len)) { | |
289c0522 BN |
3042 | pr_debug("%s: attempt to write beyond end of device\n", |
3043 | __func__); | |
03736155 AH |
3044 | return -EINVAL; |
3045 | } | |
3046 | ||
7314e9e7 | 3047 | chipnr = (int)(to >> chip->chip_shift); |
7314e9e7 TG |
3048 | |
3049 | /* | |
3050 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
3051 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
3052 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
3053 | * it in the doc2000 driver in August 1999. dwmw2. | |
3054 | */ | |
73f907fd BB |
3055 | nand_reset(chip, chipnr); |
3056 | ||
3057 | chip->select_chip(mtd, chipnr); | |
3058 | ||
3059 | /* Shift to get page */ | |
3060 | page = (int)(to >> chip->page_shift); | |
1da177e4 LT |
3061 | |
3062 | /* Check, if it is write protected */ | |
b0bb6903 HS |
3063 | if (nand_check_wp(mtd)) { |
3064 | chip->select_chip(mtd, -1); | |
8593fbc6 | 3065 | return -EROFS; |
b0bb6903 | 3066 | } |
61b03bd7 | 3067 | |
1da177e4 | 3068 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
3069 | if (page == chip->pagebuf) |
3070 | chip->pagebuf = -1; | |
1da177e4 | 3071 | |
f722013e | 3072 | nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops); |
9ce244b3 | 3073 | |
0612b9dd | 3074 | if (ops->mode == MTD_OPS_RAW) |
9ce244b3 BN |
3075 | status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask); |
3076 | else | |
3077 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); | |
1da177e4 | 3078 | |
b0bb6903 HS |
3079 | chip->select_chip(mtd, -1); |
3080 | ||
7bc3312b TG |
3081 | if (status) |
3082 | return status; | |
1da177e4 | 3083 | |
7014568b | 3084 | ops->oobretlen = ops->ooblen; |
1da177e4 | 3085 | |
7bc3312b | 3086 | return 0; |
8593fbc6 TG |
3087 | } |
3088 | ||
3089 | /** | |
3090 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
8b6e50c9 BN |
3091 | * @mtd: MTD device structure |
3092 | * @to: offset to write to | |
3093 | * @ops: oob operation description structure | |
8593fbc6 TG |
3094 | */ |
3095 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
3096 | struct mtd_oob_ops *ops) | |
3097 | { | |
8593fbc6 TG |
3098 | int ret = -ENOTSUPP; |
3099 | ||
3100 | ops->retlen = 0; | |
3101 | ||
3102 | /* Do not allow writes past end of device */ | |
7014568b | 3103 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
289c0522 BN |
3104 | pr_debug("%s: attempt to write beyond end of device\n", |
3105 | __func__); | |
8593fbc6 TG |
3106 | return -EINVAL; |
3107 | } | |
3108 | ||
6a8214aa | 3109 | nand_get_device(mtd, FL_WRITING); |
8593fbc6 | 3110 | |
f8ac0414 | 3111 | switch (ops->mode) { |
0612b9dd BN |
3112 | case MTD_OPS_PLACE_OOB: |
3113 | case MTD_OPS_AUTO_OOB: | |
3114 | case MTD_OPS_RAW: | |
8593fbc6 TG |
3115 | break; |
3116 | ||
3117 | default: | |
3118 | goto out; | |
3119 | } | |
3120 | ||
3121 | if (!ops->datbuf) | |
3122 | ret = nand_do_write_oob(mtd, to, ops); | |
3123 | else | |
3124 | ret = nand_do_write_ops(mtd, to, ops); | |
3125 | ||
7351d3a5 | 3126 | out: |
1da177e4 | 3127 | nand_release_device(mtd); |
1da177e4 LT |
3128 | return ret; |
3129 | } | |
3130 | ||
1da177e4 | 3131 | /** |
49c50b97 | 3132 | * single_erase - [GENERIC] NAND standard block erase command function |
8b6e50c9 BN |
3133 | * @mtd: MTD device structure |
3134 | * @page: the page address of the block which will be erased | |
1da177e4 | 3135 | * |
49c50b97 | 3136 | * Standard erase command for NAND chips. Returns NAND status. |
1da177e4 | 3137 | */ |
49c50b97 | 3138 | static int single_erase(struct mtd_info *mtd, int page) |
1da177e4 | 3139 | { |
862eba51 | 3140 | struct nand_chip *chip = mtd_to_nand(mtd); |
1da177e4 | 3141 | /* Send commands to erase a block */ |
ace4dfee TG |
3142 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
3143 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
49c50b97 BN |
3144 | |
3145 | return chip->waitfunc(mtd, chip); | |
1da177e4 LT |
3146 | } |
3147 | ||
1da177e4 LT |
3148 | /** |
3149 | * nand_erase - [MTD Interface] erase block(s) | |
8b6e50c9 BN |
3150 | * @mtd: MTD device structure |
3151 | * @instr: erase instruction | |
1da177e4 | 3152 | * |
8b6e50c9 | 3153 | * Erase one ore more blocks. |
1da177e4 | 3154 | */ |
e0c7d767 | 3155 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 3156 | { |
e0c7d767 | 3157 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 3158 | } |
61b03bd7 | 3159 | |
1da177e4 | 3160 | /** |
7854d3f7 | 3161 | * nand_erase_nand - [INTERN] erase block(s) |
8b6e50c9 BN |
3162 | * @mtd: MTD device structure |
3163 | * @instr: erase instruction | |
3164 | * @allowbbt: allow erasing the bbt area | |
1da177e4 | 3165 | * |
8b6e50c9 | 3166 | * Erase one ore more blocks. |
1da177e4 | 3167 | */ |
ace4dfee TG |
3168 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
3169 | int allowbbt) | |
1da177e4 | 3170 | { |
69423d99 | 3171 | int page, status, pages_per_block, ret, chipnr; |
862eba51 | 3172 | struct nand_chip *chip = mtd_to_nand(mtd); |
69423d99 | 3173 | loff_t len; |
1da177e4 | 3174 | |
289c0522 BN |
3175 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
3176 | __func__, (unsigned long long)instr->addr, | |
3177 | (unsigned long long)instr->len); | |
1da177e4 | 3178 | |
6fe5a6ac | 3179 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 3180 | return -EINVAL; |
1da177e4 | 3181 | |
1da177e4 | 3182 | /* Grab the lock and see if the device is available */ |
6a8214aa | 3183 | nand_get_device(mtd, FL_ERASING); |
1da177e4 LT |
3184 | |
3185 | /* Shift to get first page */ | |
ace4dfee TG |
3186 | page = (int)(instr->addr >> chip->page_shift); |
3187 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
3188 | |
3189 | /* Calculate pages in each block */ | |
ace4dfee | 3190 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
3191 | |
3192 | /* Select the NAND device */ | |
ace4dfee | 3193 | chip->select_chip(mtd, chipnr); |
1da177e4 | 3194 | |
1da177e4 LT |
3195 | /* Check, if it is write protected */ |
3196 | if (nand_check_wp(mtd)) { | |
289c0522 BN |
3197 | pr_debug("%s: device is write protected!\n", |
3198 | __func__); | |
1da177e4 LT |
3199 | instr->state = MTD_ERASE_FAILED; |
3200 | goto erase_exit; | |
3201 | } | |
3202 | ||
3203 | /* Loop through the pages */ | |
3204 | len = instr->len; | |
3205 | ||
3206 | instr->state = MTD_ERASING; | |
3207 | ||
3208 | while (len) { | |
12183a20 | 3209 | /* Check if we have a bad block, we do not erase bad blocks! */ |
ace4dfee | 3210 | if (nand_block_checkbad(mtd, ((loff_t) page) << |
9f3e0429 | 3211 | chip->page_shift, allowbbt)) { |
d0370219 BN |
3212 | pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", |
3213 | __func__, page); | |
1da177e4 LT |
3214 | instr->state = MTD_ERASE_FAILED; |
3215 | goto erase_exit; | |
3216 | } | |
61b03bd7 | 3217 | |
ace4dfee TG |
3218 | /* |
3219 | * Invalidate the page cache, if we erase the block which | |
8b6e50c9 | 3220 | * contains the current cached page. |
ace4dfee TG |
3221 | */ |
3222 | if (page <= chip->pagebuf && chip->pagebuf < | |
3223 | (page + pages_per_block)) | |
3224 | chip->pagebuf = -1; | |
1da177e4 | 3225 | |
49c50b97 | 3226 | status = chip->erase(mtd, page & chip->pagemask); |
1da177e4 | 3227 | |
ace4dfee TG |
3228 | /* |
3229 | * See if operation failed and additional status checks are | |
3230 | * available | |
3231 | */ | |
3232 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
3233 | status = chip->errstat(mtd, chip, FL_ERASING, | |
3234 | status, page); | |
068e3c0a | 3235 | |
1da177e4 | 3236 | /* See if block erase succeeded */ |
a4ab4c5d | 3237 | if (status & NAND_STATUS_FAIL) { |
289c0522 BN |
3238 | pr_debug("%s: failed erase, page 0x%08x\n", |
3239 | __func__, page); | |
1da177e4 | 3240 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
3241 | instr->fail_addr = |
3242 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
3243 | goto erase_exit; |
3244 | } | |
30f464b7 | 3245 | |
1da177e4 | 3246 | /* Increment page address and decrement length */ |
daae74ca | 3247 | len -= (1ULL << chip->phys_erase_shift); |
1da177e4 LT |
3248 | page += pages_per_block; |
3249 | ||
3250 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 3251 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 3252 | chipnr++; |
ace4dfee TG |
3253 | chip->select_chip(mtd, -1); |
3254 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
3255 | } |
3256 | } | |
3257 | instr->state = MTD_ERASE_DONE; | |
3258 | ||
7351d3a5 | 3259 | erase_exit: |
1da177e4 LT |
3260 | |
3261 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
3262 | |
3263 | /* Deselect and wake up anyone waiting on the device */ | |
b0bb6903 | 3264 | chip->select_chip(mtd, -1); |
1da177e4 LT |
3265 | nand_release_device(mtd); |
3266 | ||
49defc01 DW |
3267 | /* Do call back function */ |
3268 | if (!ret) | |
3269 | mtd_erase_callback(instr); | |
3270 | ||
1da177e4 LT |
3271 | /* Return more or less happy */ |
3272 | return ret; | |
3273 | } | |
3274 | ||
3275 | /** | |
3276 | * nand_sync - [MTD Interface] sync | |
8b6e50c9 | 3277 | * @mtd: MTD device structure |
1da177e4 | 3278 | * |
8b6e50c9 | 3279 | * Sync is actually a wait for chip ready function. |
1da177e4 | 3280 | */ |
e0c7d767 | 3281 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 3282 | { |
289c0522 | 3283 | pr_debug("%s: called\n", __func__); |
1da177e4 LT |
3284 | |
3285 | /* Grab the lock and see if the device is available */ | |
6a8214aa | 3286 | nand_get_device(mtd, FL_SYNCING); |
1da177e4 | 3287 | /* Release it and go back */ |
e0c7d767 | 3288 | nand_release_device(mtd); |
1da177e4 LT |
3289 | } |
3290 | ||
1da177e4 | 3291 | /** |
ace4dfee | 3292 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
8b6e50c9 BN |
3293 | * @mtd: MTD device structure |
3294 | * @offs: offset relative to mtd start | |
1da177e4 | 3295 | */ |
ace4dfee | 3296 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 | 3297 | { |
9f3e0429 AT |
3298 | struct nand_chip *chip = mtd_to_nand(mtd); |
3299 | int chipnr = (int)(offs >> chip->chip_shift); | |
3300 | int ret; | |
3301 | ||
3302 | /* Select the NAND device */ | |
3303 | nand_get_device(mtd, FL_READING); | |
3304 | chip->select_chip(mtd, chipnr); | |
3305 | ||
3306 | ret = nand_block_checkbad(mtd, offs, 0); | |
3307 | ||
3308 | chip->select_chip(mtd, -1); | |
3309 | nand_release_device(mtd); | |
3310 | ||
3311 | return ret; | |
1da177e4 LT |
3312 | } |
3313 | ||
3314 | /** | |
ace4dfee | 3315 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
8b6e50c9 BN |
3316 | * @mtd: MTD device structure |
3317 | * @ofs: offset relative to mtd start | |
1da177e4 | 3318 | */ |
e0c7d767 | 3319 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 3320 | { |
1da177e4 LT |
3321 | int ret; |
3322 | ||
f8ac0414 FF |
3323 | ret = nand_block_isbad(mtd, ofs); |
3324 | if (ret) { | |
8b6e50c9 | 3325 | /* If it was bad already, return success and do nothing */ |
1da177e4 LT |
3326 | if (ret > 0) |
3327 | return 0; | |
e0c7d767 DW |
3328 | return ret; |
3329 | } | |
1da177e4 | 3330 | |
5a0edb25 | 3331 | return nand_block_markbad_lowlevel(mtd, ofs); |
1da177e4 LT |
3332 | } |
3333 | ||
5671842f ZB |
3334 | /** |
3335 | * nand_max_bad_blocks - [MTD Interface] Max number of bad blocks for an mtd | |
3336 | * @mtd: MTD device structure | |
3337 | * @ofs: offset relative to mtd start | |
3338 | * @len: length of mtd | |
3339 | */ | |
3340 | static int nand_max_bad_blocks(struct mtd_info *mtd, loff_t ofs, size_t len) | |
3341 | { | |
3342 | struct nand_chip *chip = mtd_to_nand(mtd); | |
3343 | u32 part_start_block; | |
3344 | u32 part_end_block; | |
3345 | u32 part_start_die; | |
3346 | u32 part_end_die; | |
3347 | ||
3348 | /* | |
3349 | * max_bb_per_die and blocks_per_die used to determine | |
3350 | * the maximum bad block count. | |
3351 | */ | |
3352 | if (!chip->max_bb_per_die || !chip->blocks_per_die) | |
3353 | return -ENOTSUPP; | |
3354 | ||
3355 | /* Get the start and end of the partition in erase blocks. */ | |
3356 | part_start_block = mtd_div_by_eb(ofs, mtd); | |
3357 | part_end_block = mtd_div_by_eb(len, mtd) + part_start_block - 1; | |
3358 | ||
3359 | /* Get the start and end LUNs of the partition. */ | |
3360 | part_start_die = part_start_block / chip->blocks_per_die; | |
3361 | part_end_die = part_end_block / chip->blocks_per_die; | |
3362 | ||
3363 | /* | |
3364 | * Look up the bad blocks per unit and multiply by the number of units | |
3365 | * that the partition spans. | |
3366 | */ | |
3367 | return chip->max_bb_per_die * (part_end_die - part_start_die + 1); | |
3368 | } | |
3369 | ||
7db03ecc HS |
3370 | /** |
3371 | * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand | |
3372 | * @mtd: MTD device structure | |
3373 | * @chip: nand chip info structure | |
3374 | * @addr: feature address. | |
3375 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
3376 | */ | |
3377 | static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, | |
3378 | int addr, uint8_t *subfeature_param) | |
3379 | { | |
3380 | int status; | |
05f78359 | 3381 | int i; |
7db03ecc | 3382 | |
d914c932 DM |
3383 | if (!chip->onfi_version || |
3384 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
3385 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
3386 | return -EINVAL; |
3387 | ||
3388 | chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1); | |
05f78359 UKK |
3389 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
3390 | chip->write_byte(mtd, subfeature_param[i]); | |
3391 | ||
7db03ecc HS |
3392 | status = chip->waitfunc(mtd, chip); |
3393 | if (status & NAND_STATUS_FAIL) | |
3394 | return -EIO; | |
3395 | return 0; | |
3396 | } | |
3397 | ||
3398 | /** | |
3399 | * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand | |
3400 | * @mtd: MTD device structure | |
3401 | * @chip: nand chip info structure | |
3402 | * @addr: feature address. | |
3403 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
3404 | */ | |
3405 | static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, | |
3406 | int addr, uint8_t *subfeature_param) | |
3407 | { | |
05f78359 UKK |
3408 | int i; |
3409 | ||
d914c932 DM |
3410 | if (!chip->onfi_version || |
3411 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
3412 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
3413 | return -EINVAL; |
3414 | ||
7db03ecc | 3415 | chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1); |
05f78359 UKK |
3416 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
3417 | *subfeature_param++ = chip->read_byte(mtd); | |
7db03ecc HS |
3418 | return 0; |
3419 | } | |
3420 | ||
962034f4 VW |
3421 | /** |
3422 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
8b6e50c9 | 3423 | * @mtd: MTD device structure |
962034f4 VW |
3424 | */ |
3425 | static int nand_suspend(struct mtd_info *mtd) | |
3426 | { | |
6a8214aa | 3427 | return nand_get_device(mtd, FL_PM_SUSPENDED); |
962034f4 VW |
3428 | } |
3429 | ||
3430 | /** | |
3431 | * nand_resume - [MTD Interface] Resume the NAND flash | |
8b6e50c9 | 3432 | * @mtd: MTD device structure |
962034f4 VW |
3433 | */ |
3434 | static void nand_resume(struct mtd_info *mtd) | |
3435 | { | |
862eba51 | 3436 | struct nand_chip *chip = mtd_to_nand(mtd); |
962034f4 | 3437 | |
ace4dfee | 3438 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
3439 | nand_release_device(mtd); |
3440 | else | |
d0370219 BN |
3441 | pr_err("%s called for a chip which is not in suspended state\n", |
3442 | __func__); | |
962034f4 VW |
3443 | } |
3444 | ||
72ea4036 SB |
3445 | /** |
3446 | * nand_shutdown - [MTD Interface] Finish the current NAND operation and | |
3447 | * prevent further operations | |
3448 | * @mtd: MTD device structure | |
3449 | */ | |
3450 | static void nand_shutdown(struct mtd_info *mtd) | |
3451 | { | |
9ca641b0 | 3452 | nand_get_device(mtd, FL_PM_SUSPENDED); |
72ea4036 SB |
3453 | } |
3454 | ||
8b6e50c9 | 3455 | /* Set default functions */ |
29a198a1 | 3456 | static void nand_set_defaults(struct nand_chip *chip) |
7aa65bfd | 3457 | { |
29a198a1 BB |
3458 | unsigned int busw = chip->options & NAND_BUSWIDTH_16; |
3459 | ||
1da177e4 | 3460 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
3461 | if (!chip->chip_delay) |
3462 | chip->chip_delay = 20; | |
1da177e4 LT |
3463 | |
3464 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
3465 | if (chip->cmdfunc == NULL) |
3466 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
3467 | |
3468 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
3469 | if (chip->waitfunc == NULL) |
3470 | chip->waitfunc = nand_wait; | |
3471 | ||
3472 | if (!chip->select_chip) | |
3473 | chip->select_chip = nand_select_chip; | |
68e80780 | 3474 | |
4204cccd HS |
3475 | /* set for ONFI nand */ |
3476 | if (!chip->onfi_set_features) | |
3477 | chip->onfi_set_features = nand_onfi_set_features; | |
3478 | if (!chip->onfi_get_features) | |
3479 | chip->onfi_get_features = nand_onfi_get_features; | |
3480 | ||
68e80780 BN |
3481 | /* If called twice, pointers that depend on busw may need to be reset */ |
3482 | if (!chip->read_byte || chip->read_byte == nand_read_byte) | |
ace4dfee TG |
3483 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; |
3484 | if (!chip->read_word) | |
3485 | chip->read_word = nand_read_word; | |
3486 | if (!chip->block_bad) | |
3487 | chip->block_bad = nand_block_bad; | |
3488 | if (!chip->block_markbad) | |
3489 | chip->block_markbad = nand_default_block_markbad; | |
68e80780 | 3490 | if (!chip->write_buf || chip->write_buf == nand_write_buf) |
ace4dfee | 3491 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; |
05f78359 UKK |
3492 | if (!chip->write_byte || chip->write_byte == nand_write_byte) |
3493 | chip->write_byte = busw ? nand_write_byte16 : nand_write_byte; | |
68e80780 | 3494 | if (!chip->read_buf || chip->read_buf == nand_read_buf) |
ace4dfee | 3495 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; |
ace4dfee TG |
3496 | if (!chip->scan_bbt) |
3497 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
3498 | |
3499 | if (!chip->controller) { | |
3500 | chip->controller = &chip->hwcontrol; | |
d45bc58d | 3501 | nand_hw_control_init(chip->controller); |
f75e5097 TG |
3502 | } |
3503 | ||
477544c6 MY |
3504 | if (!chip->buf_align) |
3505 | chip->buf_align = 1; | |
7aa65bfd TG |
3506 | } |
3507 | ||
8b6e50c9 | 3508 | /* Sanitize ONFI strings so we can safely print them */ |
d1e1f4e4 FF |
3509 | static void sanitize_string(uint8_t *s, size_t len) |
3510 | { | |
3511 | ssize_t i; | |
3512 | ||
8b6e50c9 | 3513 | /* Null terminate */ |
d1e1f4e4 FF |
3514 | s[len - 1] = 0; |
3515 | ||
8b6e50c9 | 3516 | /* Remove non printable chars */ |
d1e1f4e4 FF |
3517 | for (i = 0; i < len - 1; i++) { |
3518 | if (s[i] < ' ' || s[i] > 127) | |
3519 | s[i] = '?'; | |
3520 | } | |
3521 | ||
8b6e50c9 | 3522 | /* Remove trailing spaces */ |
d1e1f4e4 FF |
3523 | strim(s); |
3524 | } | |
3525 | ||
3526 | static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) | |
3527 | { | |
3528 | int i; | |
3529 | while (len--) { | |
3530 | crc ^= *p++ << 8; | |
3531 | for (i = 0; i < 8; i++) | |
3532 | crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); | |
3533 | } | |
3534 | ||
3535 | return crc; | |
3536 | } | |
3537 | ||
6dcbe0cd | 3538 | /* Parse the Extended Parameter Page. */ |
cbe435a1 BB |
3539 | static int nand_flash_detect_ext_param_page(struct nand_chip *chip, |
3540 | struct nand_onfi_params *p) | |
6dcbe0cd | 3541 | { |
cbe435a1 | 3542 | struct mtd_info *mtd = nand_to_mtd(chip); |
6dcbe0cd HS |
3543 | struct onfi_ext_param_page *ep; |
3544 | struct onfi_ext_section *s; | |
3545 | struct onfi_ext_ecc_info *ecc; | |
3546 | uint8_t *cursor; | |
3547 | int ret = -EINVAL; | |
3548 | int len; | |
3549 | int i; | |
3550 | ||
3551 | len = le16_to_cpu(p->ext_param_page_length) * 16; | |
3552 | ep = kmalloc(len, GFP_KERNEL); | |
5cb13271 BN |
3553 | if (!ep) |
3554 | return -ENOMEM; | |
6dcbe0cd HS |
3555 | |
3556 | /* Send our own NAND_CMD_PARAM. */ | |
3557 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); | |
3558 | ||
3559 | /* Use the Change Read Column command to skip the ONFI param pages. */ | |
3560 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, | |
3561 | sizeof(*p) * p->num_of_param_pages , -1); | |
3562 | ||
3563 | /* Read out the Extended Parameter Page. */ | |
3564 | chip->read_buf(mtd, (uint8_t *)ep, len); | |
3565 | if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2) | |
3566 | != le16_to_cpu(ep->crc))) { | |
3567 | pr_debug("fail in the CRC.\n"); | |
3568 | goto ext_out; | |
3569 | } | |
3570 | ||
3571 | /* | |
3572 | * Check the signature. | |
3573 | * Do not strictly follow the ONFI spec, maybe changed in future. | |
3574 | */ | |
3575 | if (strncmp(ep->sig, "EPPS", 4)) { | |
3576 | pr_debug("The signature is invalid.\n"); | |
3577 | goto ext_out; | |
3578 | } | |
3579 | ||
3580 | /* find the ECC section. */ | |
3581 | cursor = (uint8_t *)(ep + 1); | |
3582 | for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) { | |
3583 | s = ep->sections + i; | |
3584 | if (s->type == ONFI_SECTION_TYPE_2) | |
3585 | break; | |
3586 | cursor += s->length * 16; | |
3587 | } | |
3588 | if (i == ONFI_EXT_SECTION_MAX) { | |
3589 | pr_debug("We can not find the ECC section.\n"); | |
3590 | goto ext_out; | |
3591 | } | |
3592 | ||
3593 | /* get the info we want. */ | |
3594 | ecc = (struct onfi_ext_ecc_info *)cursor; | |
3595 | ||
4ae7d228 BN |
3596 | if (!ecc->codeword_size) { |
3597 | pr_debug("Invalid codeword size\n"); | |
3598 | goto ext_out; | |
6dcbe0cd HS |
3599 | } |
3600 | ||
4ae7d228 BN |
3601 | chip->ecc_strength_ds = ecc->ecc_bits; |
3602 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
5cb13271 | 3603 | ret = 0; |
6dcbe0cd HS |
3604 | |
3605 | ext_out: | |
3606 | kfree(ep); | |
3607 | return ret; | |
3608 | } | |
3609 | ||
6fb277ba | 3610 | /* |
8b6e50c9 | 3611 | * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. |
6fb277ba | 3612 | */ |
29a198a1 | 3613 | static int nand_flash_detect_onfi(struct nand_chip *chip) |
6fb277ba | 3614 | { |
cbe435a1 | 3615 | struct mtd_info *mtd = nand_to_mtd(chip); |
6fb277ba | 3616 | struct nand_onfi_params *p = &chip->onfi_params; |
bd9c6e99 | 3617 | int i, j; |
6fb277ba FF |
3618 | int val; |
3619 | ||
7854d3f7 | 3620 | /* Try ONFI for unknown chip or LP */ |
6fb277ba FF |
3621 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); |
3622 | if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || | |
3623 | chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') | |
3624 | return 0; | |
3625 | ||
6fb277ba FF |
3626 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); |
3627 | for (i = 0; i < 3; i++) { | |
bd9c6e99 BN |
3628 | for (j = 0; j < sizeof(*p); j++) |
3629 | ((uint8_t *)p)[j] = chip->read_byte(mtd); | |
6fb277ba FF |
3630 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == |
3631 | le16_to_cpu(p->crc)) { | |
6fb277ba FF |
3632 | break; |
3633 | } | |
3634 | } | |
3635 | ||
c7f23a70 BN |
3636 | if (i == 3) { |
3637 | pr_err("Could not find valid ONFI parameter page; aborting\n"); | |
6fb277ba | 3638 | return 0; |
c7f23a70 | 3639 | } |
6fb277ba | 3640 | |
8b6e50c9 | 3641 | /* Check version */ |
6fb277ba | 3642 | val = le16_to_cpu(p->revision); |
b7b1a29d BN |
3643 | if (val & (1 << 5)) |
3644 | chip->onfi_version = 23; | |
3645 | else if (val & (1 << 4)) | |
6fb277ba FF |
3646 | chip->onfi_version = 22; |
3647 | else if (val & (1 << 3)) | |
3648 | chip->onfi_version = 21; | |
3649 | else if (val & (1 << 2)) | |
3650 | chip->onfi_version = 20; | |
b7b1a29d | 3651 | else if (val & (1 << 1)) |
6fb277ba | 3652 | chip->onfi_version = 10; |
b7b1a29d BN |
3653 | |
3654 | if (!chip->onfi_version) { | |
20171642 | 3655 | pr_info("unsupported ONFI version: %d\n", val); |
b7b1a29d BN |
3656 | return 0; |
3657 | } | |
6fb277ba FF |
3658 | |
3659 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3660 | sanitize_string(p->model, sizeof(p->model)); | |
3661 | if (!mtd->name) | |
3662 | mtd->name = p->model; | |
4355b70c | 3663 | |
6fb277ba | 3664 | mtd->writesize = le32_to_cpu(p->byte_per_page); |
4355b70c BN |
3665 | |
3666 | /* | |
3667 | * pages_per_block and blocks_per_lun may not be a power-of-2 size | |
3668 | * (don't ask me who thought of this...). MTD assumes that these | |
3669 | * dimensions will be power-of-2, so just truncate the remaining area. | |
3670 | */ | |
3671 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3672 | mtd->erasesize *= mtd->writesize; | |
3673 | ||
6fb277ba | 3674 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); |
4355b70c BN |
3675 | |
3676 | /* See erasesize comment */ | |
3677 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
63795755 | 3678 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; |
13fbd179 | 3679 | chip->bits_per_cell = p->bits_per_cell; |
e2985fc1 | 3680 | |
34da5f5f ZB |
3681 | chip->max_bb_per_die = le16_to_cpu(p->bb_per_lun); |
3682 | chip->blocks_per_die = le32_to_cpu(p->blocks_per_lun); | |
3683 | ||
e2985fc1 | 3684 | if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) |
29a198a1 | 3685 | chip->options |= NAND_BUSWIDTH_16; |
6fb277ba | 3686 | |
10c86bab HS |
3687 | if (p->ecc_bits != 0xff) { |
3688 | chip->ecc_strength_ds = p->ecc_bits; | |
3689 | chip->ecc_step_ds = 512; | |
6dcbe0cd HS |
3690 | } else if (chip->onfi_version >= 21 && |
3691 | (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) { | |
3692 | ||
3693 | /* | |
3694 | * The nand_flash_detect_ext_param_page() uses the | |
3695 | * Change Read Column command which maybe not supported | |
3696 | * by the chip->cmdfunc. So try to update the chip->cmdfunc | |
3697 | * now. We do not replace user supplied command function. | |
3698 | */ | |
3699 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) | |
3700 | chip->cmdfunc = nand_command_lp; | |
3701 | ||
3702 | /* The Extended Parameter Page is supported since ONFI 2.1. */ | |
cbe435a1 | 3703 | if (nand_flash_detect_ext_param_page(chip, p)) |
c7f23a70 BN |
3704 | pr_warn("Failed to detect ONFI extended param page\n"); |
3705 | } else { | |
3706 | pr_warn("Could not retrieve ONFI ECC requirements\n"); | |
10c86bab HS |
3707 | } |
3708 | ||
6fb277ba FF |
3709 | return 1; |
3710 | } | |
3711 | ||
91361818 HS |
3712 | /* |
3713 | * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise. | |
3714 | */ | |
29a198a1 | 3715 | static int nand_flash_detect_jedec(struct nand_chip *chip) |
91361818 | 3716 | { |
cbe435a1 | 3717 | struct mtd_info *mtd = nand_to_mtd(chip); |
91361818 HS |
3718 | struct nand_jedec_params *p = &chip->jedec_params; |
3719 | struct jedec_ecc_info *ecc; | |
3720 | int val; | |
3721 | int i, j; | |
3722 | ||
3723 | /* Try JEDEC for unknown chip or LP */ | |
3724 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1); | |
3725 | if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' || | |
3726 | chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' || | |
3727 | chip->read_byte(mtd) != 'C') | |
3728 | return 0; | |
3729 | ||
3730 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1); | |
3731 | for (i = 0; i < 3; i++) { | |
3732 | for (j = 0; j < sizeof(*p); j++) | |
3733 | ((uint8_t *)p)[j] = chip->read_byte(mtd); | |
3734 | ||
3735 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) == | |
3736 | le16_to_cpu(p->crc)) | |
3737 | break; | |
3738 | } | |
3739 | ||
3740 | if (i == 3) { | |
3741 | pr_err("Could not find valid JEDEC parameter page; aborting\n"); | |
3742 | return 0; | |
3743 | } | |
3744 | ||
3745 | /* Check version */ | |
3746 | val = le16_to_cpu(p->revision); | |
3747 | if (val & (1 << 2)) | |
3748 | chip->jedec_version = 10; | |
3749 | else if (val & (1 << 1)) | |
3750 | chip->jedec_version = 1; /* vendor specific version */ | |
3751 | ||
3752 | if (!chip->jedec_version) { | |
3753 | pr_info("unsupported JEDEC version: %d\n", val); | |
3754 | return 0; | |
3755 | } | |
3756 | ||
3757 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3758 | sanitize_string(p->model, sizeof(p->model)); | |
3759 | if (!mtd->name) | |
3760 | mtd->name = p->model; | |
3761 | ||
3762 | mtd->writesize = le32_to_cpu(p->byte_per_page); | |
3763 | ||
3764 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
3765 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3766 | mtd->erasesize *= mtd->writesize; | |
3767 | ||
3768 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); | |
3769 | ||
3770 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
3771 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
3772 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; | |
3773 | chip->bits_per_cell = p->bits_per_cell; | |
3774 | ||
3775 | if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS) | |
29a198a1 | 3776 | chip->options |= NAND_BUSWIDTH_16; |
91361818 HS |
3777 | |
3778 | /* ECC info */ | |
3779 | ecc = &p->ecc_info[0]; | |
3780 | ||
3781 | if (ecc->codeword_size >= 9) { | |
3782 | chip->ecc_strength_ds = ecc->ecc_bits; | |
3783 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
3784 | } else { | |
3785 | pr_warn("Invalid codeword size\n"); | |
3786 | } | |
3787 | ||
3788 | return 1; | |
3789 | } | |
3790 | ||
e3b88bd6 BN |
3791 | /* |
3792 | * nand_id_has_period - Check if an ID string has a given wraparound period | |
3793 | * @id_data: the ID string | |
3794 | * @arrlen: the length of the @id_data array | |
3795 | * @period: the period of repitition | |
3796 | * | |
3797 | * Check if an ID string is repeated within a given sequence of bytes at | |
3798 | * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a | |
d4d4f1bf | 3799 | * period of 3). This is a helper function for nand_id_len(). Returns non-zero |
e3b88bd6 BN |
3800 | * if the repetition has a period of @period; otherwise, returns zero. |
3801 | */ | |
3802 | static int nand_id_has_period(u8 *id_data, int arrlen, int period) | |
3803 | { | |
3804 | int i, j; | |
3805 | for (i = 0; i < period; i++) | |
3806 | for (j = i + period; j < arrlen; j += period) | |
3807 | if (id_data[i] != id_data[j]) | |
3808 | return 0; | |
3809 | return 1; | |
3810 | } | |
3811 | ||
3812 | /* | |
3813 | * nand_id_len - Get the length of an ID string returned by CMD_READID | |
3814 | * @id_data: the ID string | |
3815 | * @arrlen: the length of the @id_data array | |
3816 | ||
3817 | * Returns the length of the ID string, according to known wraparound/trailing | |
3818 | * zero patterns. If no pattern exists, returns the length of the array. | |
3819 | */ | |
3820 | static int nand_id_len(u8 *id_data, int arrlen) | |
3821 | { | |
3822 | int last_nonzero, period; | |
3823 | ||
3824 | /* Find last non-zero byte */ | |
3825 | for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) | |
3826 | if (id_data[last_nonzero]) | |
3827 | break; | |
3828 | ||
3829 | /* All zeros */ | |
3830 | if (last_nonzero < 0) | |
3831 | return 0; | |
3832 | ||
3833 | /* Calculate wraparound period */ | |
3834 | for (period = 1; period < arrlen; period++) | |
3835 | if (nand_id_has_period(id_data, arrlen, period)) | |
3836 | break; | |
3837 | ||
3838 | /* There's a repeated pattern */ | |
3839 | if (period < arrlen) | |
3840 | return period; | |
3841 | ||
3842 | /* There are trailing zeros */ | |
3843 | if (last_nonzero < arrlen - 1) | |
3844 | return last_nonzero + 1; | |
3845 | ||
3846 | /* No pattern detected */ | |
3847 | return arrlen; | |
3848 | } | |
3849 | ||
7db906b7 HS |
3850 | /* Extract the bits of per cell from the 3rd byte of the extended ID */ |
3851 | static int nand_get_bits_per_cell(u8 cellinfo) | |
3852 | { | |
3853 | int bits; | |
3854 | ||
3855 | bits = cellinfo & NAND_CI_CELLTYPE_MSK; | |
3856 | bits >>= NAND_CI_CELLTYPE_SHIFT; | |
3857 | return bits + 1; | |
3858 | } | |
3859 | ||
fc09bbc0 BN |
3860 | /* |
3861 | * Many new NAND share similar device ID codes, which represent the size of the | |
3862 | * chip. The rest of the parameters must be decoded according to generic or | |
3863 | * manufacturer-specific "extended ID" decoding patterns. | |
3864 | */ | |
abbe26d1 | 3865 | void nand_decode_ext_id(struct nand_chip *chip) |
fc09bbc0 | 3866 | { |
cbe435a1 | 3867 | struct mtd_info *mtd = nand_to_mtd(chip); |
9b2d61f8 | 3868 | int extid; |
7f501f0a | 3869 | u8 *id_data = chip->id.data; |
fc09bbc0 | 3870 | /* The 3rd id byte holds MLC / multichip data */ |
7db906b7 | 3871 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
fc09bbc0 BN |
3872 | /* The 4th id byte is the important one */ |
3873 | extid = id_data[3]; | |
3874 | ||
01389b6b BB |
3875 | /* Calc pagesize */ |
3876 | mtd->writesize = 1024 << (extid & 0x03); | |
3877 | extid >>= 2; | |
3878 | /* Calc oobsize */ | |
3879 | mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9); | |
3880 | extid >>= 2; | |
3881 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
3882 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
3883 | extid >>= 2; | |
3884 | /* Get buswidth information */ | |
3885 | if (extid & 0x1) | |
3886 | chip->options |= NAND_BUSWIDTH_16; | |
fc09bbc0 | 3887 | } |
abbe26d1 | 3888 | EXPORT_SYMBOL_GPL(nand_decode_ext_id); |
fc09bbc0 | 3889 | |
f23a481c BN |
3890 | /* |
3891 | * Old devices have chip data hardcoded in the device ID table. nand_decode_id | |
3892 | * decodes a matching ID table entry and assigns the MTD size parameters for | |
3893 | * the chip. | |
3894 | */ | |
29a198a1 | 3895 | static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type) |
f23a481c | 3896 | { |
cbe435a1 | 3897 | struct mtd_info *mtd = nand_to_mtd(chip); |
f23a481c BN |
3898 | |
3899 | mtd->erasesize = type->erasesize; | |
3900 | mtd->writesize = type->pagesize; | |
3901 | mtd->oobsize = mtd->writesize / 32; | |
f23a481c | 3902 | |
1c195e90 HS |
3903 | /* All legacy ID NAND are small-page, SLC */ |
3904 | chip->bits_per_cell = 1; | |
f23a481c BN |
3905 | } |
3906 | ||
7e74c2d7 BN |
3907 | /* |
3908 | * Set the bad block marker/indicator (BBM/BBI) patterns according to some | |
3909 | * heuristic patterns using various detected parameters (e.g., manufacturer, | |
3910 | * page size, cell-type information). | |
3911 | */ | |
7f501f0a | 3912 | static void nand_decode_bbm_options(struct nand_chip *chip) |
7e74c2d7 | 3913 | { |
cbe435a1 | 3914 | struct mtd_info *mtd = nand_to_mtd(chip); |
7e74c2d7 BN |
3915 | |
3916 | /* Set the bad block position */ | |
3917 | if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) | |
3918 | chip->badblockpos = NAND_LARGE_BADBLOCK_POS; | |
3919 | else | |
3920 | chip->badblockpos = NAND_SMALL_BADBLOCK_POS; | |
7e74c2d7 BN |
3921 | } |
3922 | ||
ec6e87e3 HS |
3923 | static inline bool is_full_id_nand(struct nand_flash_dev *type) |
3924 | { | |
3925 | return type->id_len; | |
3926 | } | |
3927 | ||
cbe435a1 | 3928 | static bool find_full_id_nand(struct nand_chip *chip, |
29a198a1 | 3929 | struct nand_flash_dev *type) |
ec6e87e3 | 3930 | { |
cbe435a1 | 3931 | struct mtd_info *mtd = nand_to_mtd(chip); |
7f501f0a | 3932 | u8 *id_data = chip->id.data; |
cbe435a1 | 3933 | |
ec6e87e3 HS |
3934 | if (!strncmp(type->id, id_data, type->id_len)) { |
3935 | mtd->writesize = type->pagesize; | |
3936 | mtd->erasesize = type->erasesize; | |
3937 | mtd->oobsize = type->oobsize; | |
3938 | ||
7db906b7 | 3939 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
ec6e87e3 HS |
3940 | chip->chipsize = (uint64_t)type->chipsize << 20; |
3941 | chip->options |= type->options; | |
57219342 HS |
3942 | chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); |
3943 | chip->ecc_step_ds = NAND_ECC_STEP(type); | |
57a94e24 BB |
3944 | chip->onfi_timing_mode_default = |
3945 | type->onfi_timing_mode_default; | |
ec6e87e3 | 3946 | |
092b6a1d CZ |
3947 | if (!mtd->name) |
3948 | mtd->name = type->name; | |
3949 | ||
ec6e87e3 HS |
3950 | return true; |
3951 | } | |
3952 | return false; | |
3953 | } | |
3954 | ||
abbe26d1 BB |
3955 | /* |
3956 | * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC | |
3957 | * compliant and does not have a full-id or legacy-id entry in the nand_ids | |
3958 | * table. | |
3959 | */ | |
3960 | static void nand_manufacturer_detect(struct nand_chip *chip) | |
3961 | { | |
3962 | /* | |
3963 | * Try manufacturer detection if available and use | |
3964 | * nand_decode_ext_id() otherwise. | |
3965 | */ | |
3966 | if (chip->manufacturer.desc && chip->manufacturer.desc->ops && | |
3967 | chip->manufacturer.desc->ops->detect) | |
3968 | chip->manufacturer.desc->ops->detect(chip); | |
3969 | else | |
3970 | nand_decode_ext_id(chip); | |
3971 | } | |
3972 | ||
3973 | /* | |
3974 | * Manufacturer initialization. This function is called for all NANDs including | |
3975 | * ONFI and JEDEC compliant ones. | |
3976 | * Manufacturer drivers should put all their specific initialization code in | |
3977 | * their ->init() hook. | |
3978 | */ | |
3979 | static int nand_manufacturer_init(struct nand_chip *chip) | |
3980 | { | |
3981 | if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops || | |
3982 | !chip->manufacturer.desc->ops->init) | |
3983 | return 0; | |
3984 | ||
3985 | return chip->manufacturer.desc->ops->init(chip); | |
3986 | } | |
3987 | ||
3988 | /* | |
3989 | * Manufacturer cleanup. This function is called for all NANDs including | |
3990 | * ONFI and JEDEC compliant ones. | |
3991 | * Manufacturer drivers should put all their specific cleanup code in their | |
3992 | * ->cleanup() hook. | |
3993 | */ | |
3994 | static void nand_manufacturer_cleanup(struct nand_chip *chip) | |
3995 | { | |
3996 | /* Release manufacturer private data */ | |
3997 | if (chip->manufacturer.desc && chip->manufacturer.desc->ops && | |
3998 | chip->manufacturer.desc->ops->cleanup) | |
3999 | chip->manufacturer.desc->ops->cleanup(chip); | |
4000 | } | |
4001 | ||
7aa65bfd | 4002 | /* |
8b6e50c9 | 4003 | * Get the flash and manufacturer id and lookup if the type is supported. |
7aa65bfd | 4004 | */ |
7bb42799 | 4005 | static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type) |
7aa65bfd | 4006 | { |
bcc678c2 | 4007 | const struct nand_manufacturer *manufacturer; |
cbe435a1 | 4008 | struct mtd_info *mtd = nand_to_mtd(chip); |
bb77082f | 4009 | int busw; |
abbe26d1 | 4010 | int i, ret; |
7f501f0a BB |
4011 | u8 *id_data = chip->id.data; |
4012 | u8 maf_id, dev_id; | |
1da177e4 | 4013 | |
ef89a880 KB |
4014 | /* |
4015 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
8b6e50c9 | 4016 | * after power-up. |
ef89a880 | 4017 | */ |
73f907fd BB |
4018 | nand_reset(chip, 0); |
4019 | ||
4020 | /* Select the device */ | |
4021 | chip->select_chip(mtd, 0); | |
ef89a880 | 4022 | |
1da177e4 | 4023 | /* Send the command for reading device ID */ |
ace4dfee | 4024 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
4025 | |
4026 | /* Read manufacturer and device IDs */ | |
7f501f0a BB |
4027 | maf_id = chip->read_byte(mtd); |
4028 | dev_id = chip->read_byte(mtd); | |
1da177e4 | 4029 | |
8b6e50c9 BN |
4030 | /* |
4031 | * Try again to make sure, as some systems the bus-hold or other | |
ed8165c7 BD |
4032 | * interface concerns can cause random data which looks like a |
4033 | * possibly credible NAND flash to appear. If the two results do | |
4034 | * not match, ignore the device completely. | |
4035 | */ | |
4036 | ||
4037 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
4038 | ||
4aef9b78 BN |
4039 | /* Read entire ID string */ |
4040 | for (i = 0; i < 8; i++) | |
426c457a | 4041 | id_data[i] = chip->read_byte(mtd); |
ed8165c7 | 4042 | |
7f501f0a | 4043 | if (id_data[0] != maf_id || id_data[1] != dev_id) { |
20171642 | 4044 | pr_info("second ID read did not match %02x,%02x against %02x,%02x\n", |
7f501f0a | 4045 | maf_id, dev_id, id_data[0], id_data[1]); |
4722c0e9 | 4046 | return -ENODEV; |
ed8165c7 BD |
4047 | } |
4048 | ||
7f501f0a BB |
4049 | chip->id.len = nand_id_len(id_data, 8); |
4050 | ||
abbe26d1 BB |
4051 | /* Try to identify manufacturer */ |
4052 | manufacturer = nand_get_manufacturer(maf_id); | |
4053 | chip->manufacturer.desc = manufacturer; | |
4054 | ||
7aa65bfd | 4055 | if (!type) |
5e81e88a DW |
4056 | type = nand_flash_ids; |
4057 | ||
29a198a1 BB |
4058 | /* |
4059 | * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic | |
4060 | * override it. | |
4061 | * This is required to make sure initial NAND bus width set by the | |
4062 | * NAND controller driver is coherent with the real NAND bus width | |
4063 | * (extracted by auto-detection code). | |
4064 | */ | |
4065 | busw = chip->options & NAND_BUSWIDTH_16; | |
4066 | ||
4067 | /* | |
4068 | * The flag is only set (never cleared), reset it to its default value | |
4069 | * before starting auto-detection. | |
4070 | */ | |
4071 | chip->options &= ~NAND_BUSWIDTH_16; | |
4072 | ||
ec6e87e3 HS |
4073 | for (; type->name != NULL; type++) { |
4074 | if (is_full_id_nand(type)) { | |
29a198a1 | 4075 | if (find_full_id_nand(chip, type)) |
ec6e87e3 | 4076 | goto ident_done; |
7f501f0a | 4077 | } else if (dev_id == type->dev_id) { |
db5b09f6 | 4078 | break; |
ec6e87e3 HS |
4079 | } |
4080 | } | |
5e81e88a | 4081 | |
d1e1f4e4 FF |
4082 | chip->onfi_version = 0; |
4083 | if (!type->name || !type->pagesize) { | |
35fc5195 | 4084 | /* Check if the chip is ONFI compliant */ |
29a198a1 | 4085 | if (nand_flash_detect_onfi(chip)) |
6fb277ba | 4086 | goto ident_done; |
91361818 HS |
4087 | |
4088 | /* Check if the chip is JEDEC compliant */ | |
29a198a1 | 4089 | if (nand_flash_detect_jedec(chip)) |
91361818 | 4090 | goto ident_done; |
d1e1f4e4 FF |
4091 | } |
4092 | ||
5e81e88a | 4093 | if (!type->name) |
4722c0e9 | 4094 | return -ENODEV; |
7aa65bfd | 4095 | |
ba0251fe TG |
4096 | if (!mtd->name) |
4097 | mtd->name = type->name; | |
4098 | ||
69423d99 | 4099 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd | 4100 | |
abbe26d1 BB |
4101 | if (!type->pagesize) |
4102 | nand_manufacturer_detect(chip); | |
4103 | else | |
29a198a1 | 4104 | nand_decode_id(chip, type); |
abbe26d1 | 4105 | |
bf7a01bf BN |
4106 | /* Get chip options */ |
4107 | chip->options |= type->options; | |
d1e1f4e4 | 4108 | |
d1e1f4e4 FF |
4109 | ident_done: |
4110 | ||
64b37b2a | 4111 | if (chip->options & NAND_BUSWIDTH_AUTO) { |
29a198a1 BB |
4112 | WARN_ON(busw & NAND_BUSWIDTH_16); |
4113 | nand_set_defaults(chip); | |
64b37b2a MC |
4114 | } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { |
4115 | /* | |
4116 | * Check, if buswidth is correct. Hardware drivers should set | |
4117 | * chip correct! | |
4118 | */ | |
20171642 | 4119 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
7f501f0a | 4120 | maf_id, dev_id); |
bcc678c2 BB |
4121 | pr_info("%s %s\n", nand_manufacturer_name(manufacturer), |
4122 | mtd->name); | |
29a198a1 BB |
4123 | pr_warn("bus width %d instead of %d bits\n", busw ? 16 : 8, |
4124 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8); | |
4722c0e9 | 4125 | return -EINVAL; |
7aa65bfd | 4126 | } |
61b03bd7 | 4127 | |
7f501f0a | 4128 | nand_decode_bbm_options(chip); |
7e74c2d7 | 4129 | |
7aa65bfd | 4130 | /* Calculate the address shift from the page size */ |
ace4dfee | 4131 | chip->page_shift = ffs(mtd->writesize) - 1; |
8b6e50c9 | 4132 | /* Convert chipsize to number of pages per chip -1 */ |
ace4dfee | 4133 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 4134 | |
ace4dfee | 4135 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 4136 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
4137 | if (chip->chipsize & 0xffffffff) |
4138 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
7351d3a5 FF |
4139 | else { |
4140 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); | |
4141 | chip->chip_shift += 32 - 1; | |
4142 | } | |
1da177e4 | 4143 | |
26d9be11 | 4144 | chip->badblockbits = 8; |
49c50b97 | 4145 | chip->erase = single_erase; |
7aa65bfd | 4146 | |
8b6e50c9 | 4147 | /* Do not replace user supplied command function! */ |
ace4dfee TG |
4148 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
4149 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd | 4150 | |
abbe26d1 BB |
4151 | ret = nand_manufacturer_init(chip); |
4152 | if (ret) | |
4153 | return ret; | |
4154 | ||
20171642 | 4155 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
7f501f0a | 4156 | maf_id, dev_id); |
ffdac6cd HS |
4157 | |
4158 | if (chip->onfi_version) | |
bcc678c2 BB |
4159 | pr_info("%s %s\n", nand_manufacturer_name(manufacturer), |
4160 | chip->onfi_params.model); | |
ffdac6cd | 4161 | else if (chip->jedec_version) |
bcc678c2 BB |
4162 | pr_info("%s %s\n", nand_manufacturer_name(manufacturer), |
4163 | chip->jedec_params.model); | |
ffdac6cd | 4164 | else |
bcc678c2 BB |
4165 | pr_info("%s %s\n", nand_manufacturer_name(manufacturer), |
4166 | type->name); | |
ffdac6cd | 4167 | |
3755a991 | 4168 | pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n", |
3723e93c | 4169 | (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", |
3755a991 | 4170 | mtd->erasesize >> 10, mtd->writesize, mtd->oobsize); |
4722c0e9 | 4171 | return 0; |
7aa65bfd TG |
4172 | } |
4173 | ||
d48f62b9 BB |
4174 | static const char * const nand_ecc_modes[] = { |
4175 | [NAND_ECC_NONE] = "none", | |
4176 | [NAND_ECC_SOFT] = "soft", | |
4177 | [NAND_ECC_HW] = "hw", | |
4178 | [NAND_ECC_HW_SYNDROME] = "hw_syndrome", | |
4179 | [NAND_ECC_HW_OOB_FIRST] = "hw_oob_first", | |
d48f62b9 BB |
4180 | }; |
4181 | ||
4182 | static int of_get_nand_ecc_mode(struct device_node *np) | |
4183 | { | |
4184 | const char *pm; | |
4185 | int err, i; | |
4186 | ||
4187 | err = of_property_read_string(np, "nand-ecc-mode", &pm); | |
4188 | if (err < 0) | |
4189 | return err; | |
4190 | ||
4191 | for (i = 0; i < ARRAY_SIZE(nand_ecc_modes); i++) | |
4192 | if (!strcasecmp(pm, nand_ecc_modes[i])) | |
4193 | return i; | |
4194 | ||
ae211bcf RM |
4195 | /* |
4196 | * For backward compatibility we support few obsoleted values that don't | |
4197 | * have their mappings into nand_ecc_modes_t anymore (they were merged | |
4198 | * with other enums). | |
4199 | */ | |
4200 | if (!strcasecmp(pm, "soft_bch")) | |
4201 | return NAND_ECC_SOFT; | |
4202 | ||
d48f62b9 BB |
4203 | return -ENODEV; |
4204 | } | |
4205 | ||
ba4f46b2 RM |
4206 | static const char * const nand_ecc_algos[] = { |
4207 | [NAND_ECC_HAMMING] = "hamming", | |
4208 | [NAND_ECC_BCH] = "bch", | |
4209 | }; | |
4210 | ||
d48f62b9 BB |
4211 | static int of_get_nand_ecc_algo(struct device_node *np) |
4212 | { | |
4213 | const char *pm; | |
ba4f46b2 | 4214 | int err, i; |
d48f62b9 | 4215 | |
ba4f46b2 RM |
4216 | err = of_property_read_string(np, "nand-ecc-algo", &pm); |
4217 | if (!err) { | |
4218 | for (i = NAND_ECC_HAMMING; i < ARRAY_SIZE(nand_ecc_algos); i++) | |
4219 | if (!strcasecmp(pm, nand_ecc_algos[i])) | |
4220 | return i; | |
4221 | return -ENODEV; | |
4222 | } | |
d48f62b9 BB |
4223 | |
4224 | /* | |
4225 | * For backward compatibility we also read "nand-ecc-mode" checking | |
4226 | * for some obsoleted values that were specifying ECC algorithm. | |
4227 | */ | |
4228 | err = of_property_read_string(np, "nand-ecc-mode", &pm); | |
4229 | if (err < 0) | |
4230 | return err; | |
4231 | ||
4232 | if (!strcasecmp(pm, "soft")) | |
4233 | return NAND_ECC_HAMMING; | |
4234 | else if (!strcasecmp(pm, "soft_bch")) | |
4235 | return NAND_ECC_BCH; | |
4236 | ||
4237 | return -ENODEV; | |
4238 | } | |
4239 | ||
4240 | static int of_get_nand_ecc_step_size(struct device_node *np) | |
4241 | { | |
4242 | int ret; | |
4243 | u32 val; | |
4244 | ||
4245 | ret = of_property_read_u32(np, "nand-ecc-step-size", &val); | |
4246 | return ret ? ret : val; | |
4247 | } | |
4248 | ||
4249 | static int of_get_nand_ecc_strength(struct device_node *np) | |
4250 | { | |
4251 | int ret; | |
4252 | u32 val; | |
4253 | ||
4254 | ret = of_property_read_u32(np, "nand-ecc-strength", &val); | |
4255 | return ret ? ret : val; | |
4256 | } | |
4257 | ||
4258 | static int of_get_nand_bus_width(struct device_node *np) | |
4259 | { | |
4260 | u32 val; | |
4261 | ||
4262 | if (of_property_read_u32(np, "nand-bus-width", &val)) | |
4263 | return 8; | |
4264 | ||
4265 | switch (val) { | |
4266 | case 8: | |
4267 | case 16: | |
4268 | return val; | |
4269 | default: | |
4270 | return -EIO; | |
4271 | } | |
4272 | } | |
4273 | ||
4274 | static bool of_get_nand_on_flash_bbt(struct device_node *np) | |
4275 | { | |
4276 | return of_property_read_bool(np, "nand-on-flash-bbt"); | |
4277 | } | |
4278 | ||
7194a29a | 4279 | static int nand_dt_init(struct nand_chip *chip) |
5844feea | 4280 | { |
7194a29a | 4281 | struct device_node *dn = nand_get_flash_node(chip); |
79082457 | 4282 | int ecc_mode, ecc_algo, ecc_strength, ecc_step; |
5844feea | 4283 | |
7194a29a BB |
4284 | if (!dn) |
4285 | return 0; | |
4286 | ||
5844feea BN |
4287 | if (of_get_nand_bus_width(dn) == 16) |
4288 | chip->options |= NAND_BUSWIDTH_16; | |
4289 | ||
4290 | if (of_get_nand_on_flash_bbt(dn)) | |
4291 | chip->bbt_options |= NAND_BBT_USE_FLASH; | |
4292 | ||
4293 | ecc_mode = of_get_nand_ecc_mode(dn); | |
79082457 | 4294 | ecc_algo = of_get_nand_ecc_algo(dn); |
5844feea BN |
4295 | ecc_strength = of_get_nand_ecc_strength(dn); |
4296 | ecc_step = of_get_nand_ecc_step_size(dn); | |
4297 | ||
5844feea BN |
4298 | if (ecc_mode >= 0) |
4299 | chip->ecc.mode = ecc_mode; | |
4300 | ||
79082457 RM |
4301 | if (ecc_algo >= 0) |
4302 | chip->ecc.algo = ecc_algo; | |
4303 | ||
5844feea BN |
4304 | if (ecc_strength >= 0) |
4305 | chip->ecc.strength = ecc_strength; | |
4306 | ||
4307 | if (ecc_step > 0) | |
4308 | chip->ecc.size = ecc_step; | |
4309 | ||
ba78ee00 BB |
4310 | if (of_property_read_bool(dn, "nand-ecc-maximize")) |
4311 | chip->ecc.options |= NAND_ECC_MAXIMIZE; | |
4312 | ||
5844feea BN |
4313 | return 0; |
4314 | } | |
4315 | ||
7aa65bfd | 4316 | /** |
3b85c321 | 4317 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
8b6e50c9 BN |
4318 | * @mtd: MTD device structure |
4319 | * @maxchips: number of chips to scan for | |
4320 | * @table: alternative NAND ID table | |
7aa65bfd | 4321 | * |
8b6e50c9 BN |
4322 | * This is the first phase of the normal nand_scan() function. It reads the |
4323 | * flash ID and sets up MTD fields accordingly. | |
7aa65bfd TG |
4324 | * |
4325 | */ | |
5e81e88a DW |
4326 | int nand_scan_ident(struct mtd_info *mtd, int maxchips, |
4327 | struct nand_flash_dev *table) | |
7aa65bfd | 4328 | { |
bb77082f | 4329 | int i, nand_maf_id, nand_dev_id; |
862eba51 | 4330 | struct nand_chip *chip = mtd_to_nand(mtd); |
5844feea BN |
4331 | int ret; |
4332 | ||
7194a29a BB |
4333 | ret = nand_dt_init(chip); |
4334 | if (ret) | |
4335 | return ret; | |
7aa65bfd | 4336 | |
f7a8e38f BN |
4337 | if (!mtd->name && mtd->dev.parent) |
4338 | mtd->name = dev_name(mtd->dev.parent); | |
4339 | ||
76fe334f AS |
4340 | if ((!chip->cmdfunc || !chip->select_chip) && !chip->cmd_ctrl) { |
4341 | /* | |
4342 | * Default functions assigned for chip_select() and | |
4343 | * cmdfunc() both expect cmd_ctrl() to be populated, | |
4344 | * so we need to check that that's the case | |
4345 | */ | |
4346 | pr_err("chip.cmd_ctrl() callback is not provided"); | |
4347 | return -EINVAL; | |
4348 | } | |
7aa65bfd | 4349 | /* Set the default functions */ |
29a198a1 | 4350 | nand_set_defaults(chip); |
7aa65bfd TG |
4351 | |
4352 | /* Read the flash type */ | |
7bb42799 | 4353 | ret = nand_detect(chip, table); |
4722c0e9 | 4354 | if (ret) { |
b1c6e6db | 4355 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
d0370219 | 4356 | pr_warn("No NAND device found\n"); |
ace4dfee | 4357 | chip->select_chip(mtd, -1); |
4722c0e9 | 4358 | return ret; |
1da177e4 LT |
4359 | } |
4360 | ||
73f907fd | 4361 | /* Initialize the ->data_interface field. */ |
d8e725dd BB |
4362 | ret = nand_init_data_interface(chip); |
4363 | if (ret) | |
78771049 | 4364 | goto err_nand_init; |
d8e725dd | 4365 | |
73f907fd BB |
4366 | /* |
4367 | * Setup the data interface correctly on the chip and controller side. | |
4368 | * This explicit call to nand_setup_data_interface() is only required | |
4369 | * for the first die, because nand_reset() has been called before | |
4370 | * ->data_interface and ->default_onfi_timing_mode were set. | |
4371 | * For the other dies, nand_reset() will automatically switch to the | |
4372 | * best mode for us. | |
4373 | */ | |
4374 | ret = nand_setup_data_interface(chip); | |
4375 | if (ret) | |
78771049 | 4376 | goto err_nand_init; |
73f907fd | 4377 | |
7f501f0a BB |
4378 | nand_maf_id = chip->id.data[0]; |
4379 | nand_dev_id = chip->id.data[1]; | |
4380 | ||
07300164 HS |
4381 | chip->select_chip(mtd, -1); |
4382 | ||
7aa65bfd | 4383 | /* Check for a chip array */ |
e0c7d767 | 4384 | for (i = 1; i < maxchips; i++) { |
ef89a880 | 4385 | /* See comment in nand_get_flash_type for reset */ |
73f907fd BB |
4386 | nand_reset(chip, i); |
4387 | ||
4388 | chip->select_chip(mtd, i); | |
1da177e4 | 4389 | /* Send the command for reading device ID */ |
ace4dfee | 4390 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 4391 | /* Read manufacturer and device IDs */ |
ace4dfee | 4392 | if (nand_maf_id != chip->read_byte(mtd) || |
07300164 HS |
4393 | nand_dev_id != chip->read_byte(mtd)) { |
4394 | chip->select_chip(mtd, -1); | |
1da177e4 | 4395 | break; |
07300164 HS |
4396 | } |
4397 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
4398 | } |
4399 | if (i > 1) | |
20171642 | 4400 | pr_info("%d chips detected\n", i); |
61b03bd7 | 4401 | |
1da177e4 | 4402 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
4403 | chip->numchips = i; |
4404 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 4405 | |
3b85c321 | 4406 | return 0; |
78771049 BN |
4407 | |
4408 | err_nand_init: | |
4409 | /* Free manufacturer priv data. */ | |
4410 | nand_manufacturer_cleanup(chip); | |
4411 | ||
4412 | return ret; | |
3b85c321 | 4413 | } |
7351d3a5 | 4414 | EXPORT_SYMBOL(nand_scan_ident); |
3b85c321 | 4415 | |
06f384c9 RM |
4416 | static int nand_set_ecc_soft_ops(struct mtd_info *mtd) |
4417 | { | |
4418 | struct nand_chip *chip = mtd_to_nand(mtd); | |
4419 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
4420 | ||
e4225ae8 | 4421 | if (WARN_ON(ecc->mode != NAND_ECC_SOFT)) |
06f384c9 RM |
4422 | return -EINVAL; |
4423 | ||
4424 | switch (ecc->algo) { | |
4425 | case NAND_ECC_HAMMING: | |
4426 | ecc->calculate = nand_calculate_ecc; | |
4427 | ecc->correct = nand_correct_data; | |
4428 | ecc->read_page = nand_read_page_swecc; | |
4429 | ecc->read_subpage = nand_read_subpage; | |
4430 | ecc->write_page = nand_write_page_swecc; | |
4431 | ecc->read_page_raw = nand_read_page_raw; | |
4432 | ecc->write_page_raw = nand_write_page_raw; | |
4433 | ecc->read_oob = nand_read_oob_std; | |
4434 | ecc->write_oob = nand_write_oob_std; | |
4435 | if (!ecc->size) | |
4436 | ecc->size = 256; | |
4437 | ecc->bytes = 3; | |
4438 | ecc->strength = 1; | |
4439 | return 0; | |
4440 | case NAND_ECC_BCH: | |
4441 | if (!mtd_nand_has_bch()) { | |
4442 | WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n"); | |
4443 | return -EINVAL; | |
4444 | } | |
4445 | ecc->calculate = nand_bch_calculate_ecc; | |
4446 | ecc->correct = nand_bch_correct_data; | |
4447 | ecc->read_page = nand_read_page_swecc; | |
4448 | ecc->read_subpage = nand_read_subpage; | |
4449 | ecc->write_page = nand_write_page_swecc; | |
4450 | ecc->read_page_raw = nand_read_page_raw; | |
4451 | ecc->write_page_raw = nand_write_page_raw; | |
4452 | ecc->read_oob = nand_read_oob_std; | |
4453 | ecc->write_oob = nand_write_oob_std; | |
8bbba481 | 4454 | |
06f384c9 RM |
4455 | /* |
4456 | * Board driver should supply ecc.size and ecc.strength | |
4457 | * values to select how many bits are correctable. | |
4458 | * Otherwise, default to 4 bits for large page devices. | |
4459 | */ | |
4460 | if (!ecc->size && (mtd->oobsize >= 64)) { | |
4461 | ecc->size = 512; | |
4462 | ecc->strength = 4; | |
4463 | } | |
4464 | ||
4465 | /* | |
4466 | * if no ecc placement scheme was provided pickup the default | |
4467 | * large page one. | |
4468 | */ | |
4469 | if (!mtd->ooblayout) { | |
4470 | /* handle large page devices only */ | |
4471 | if (mtd->oobsize < 64) { | |
4472 | WARN(1, "OOB layout is required when using software BCH on small pages\n"); | |
4473 | return -EINVAL; | |
4474 | } | |
4475 | ||
4476 | mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops); | |
8bbba481 BB |
4477 | |
4478 | } | |
4479 | ||
4480 | /* | |
4481 | * We can only maximize ECC config when the default layout is | |
4482 | * used, otherwise we don't know how many bytes can really be | |
4483 | * used. | |
4484 | */ | |
4485 | if (mtd->ooblayout == &nand_ooblayout_lp_ops && | |
4486 | ecc->options & NAND_ECC_MAXIMIZE) { | |
4487 | int steps, bytes; | |
4488 | ||
4489 | /* Always prefer 1k blocks over 512bytes ones */ | |
4490 | ecc->size = 1024; | |
4491 | steps = mtd->writesize / ecc->size; | |
4492 | ||
4493 | /* Reserve 2 bytes for the BBM */ | |
4494 | bytes = (mtd->oobsize - 2) / steps; | |
4495 | ecc->strength = bytes * 8 / fls(8 * ecc->size); | |
06f384c9 RM |
4496 | } |
4497 | ||
4498 | /* See nand_bch_init() for details. */ | |
4499 | ecc->bytes = 0; | |
4500 | ecc->priv = nand_bch_init(mtd); | |
4501 | if (!ecc->priv) { | |
4502 | WARN(1, "BCH ECC initialization failed!\n"); | |
4503 | return -EINVAL; | |
4504 | } | |
4505 | return 0; | |
4506 | default: | |
4507 | WARN(1, "Unsupported ECC algorithm!\n"); | |
4508 | return -EINVAL; | |
4509 | } | |
4510 | } | |
4511 | ||
67a9ad9b EG |
4512 | /* |
4513 | * Check if the chip configuration meet the datasheet requirements. | |
4514 | ||
4515 | * If our configuration corrects A bits per B bytes and the minimum | |
4516 | * required correction level is X bits per Y bytes, then we must ensure | |
4517 | * both of the following are true: | |
4518 | * | |
4519 | * (1) A / B >= X / Y | |
4520 | * (2) A >= X | |
4521 | * | |
4522 | * Requirement (1) ensures we can correct for the required bitflip density. | |
4523 | * Requirement (2) ensures we can correct even when all bitflips are clumped | |
4524 | * in the same sector. | |
4525 | */ | |
4526 | static bool nand_ecc_strength_good(struct mtd_info *mtd) | |
4527 | { | |
862eba51 | 4528 | struct nand_chip *chip = mtd_to_nand(mtd); |
67a9ad9b EG |
4529 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
4530 | int corr, ds_corr; | |
4531 | ||
4532 | if (ecc->size == 0 || chip->ecc_step_ds == 0) | |
4533 | /* Not enough information */ | |
4534 | return true; | |
4535 | ||
4536 | /* | |
4537 | * We get the number of corrected bits per page to compare | |
4538 | * the correction density. | |
4539 | */ | |
4540 | corr = (mtd->writesize * ecc->strength) / ecc->size; | |
4541 | ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds; | |
4542 | ||
4543 | return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds; | |
4544 | } | |
3b85c321 | 4545 | |
3371d663 MG |
4546 | static bool invalid_ecc_page_accessors(struct nand_chip *chip) |
4547 | { | |
4548 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
4549 | ||
4550 | if (nand_standard_page_accessors(ecc)) | |
4551 | return false; | |
4552 | ||
4553 | /* | |
4554 | * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND | |
4555 | * controller driver implements all the page accessors because | |
4556 | * default helpers are not suitable when the core does not | |
4557 | * send the READ0/PAGEPROG commands. | |
4558 | */ | |
4559 | return (!ecc->read_page || !ecc->write_page || | |
4560 | !ecc->read_page_raw || !ecc->write_page_raw || | |
4561 | (NAND_HAS_SUBPAGE_READ(chip) && !ecc->read_subpage) || | |
4562 | (NAND_HAS_SUBPAGE_WRITE(chip) && !ecc->write_subpage && | |
4563 | ecc->hwctl && ecc->calculate)); | |
4564 | } | |
4565 | ||
3b85c321 DW |
4566 | /** |
4567 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
8b6e50c9 | 4568 | * @mtd: MTD device structure |
3b85c321 | 4569 | * |
8b6e50c9 BN |
4570 | * This is the second phase of the normal nand_scan() function. It fills out |
4571 | * all the uninitialized function pointers with the defaults and scans for a | |
4572 | * bad block table if appropriate. | |
3b85c321 DW |
4573 | */ |
4574 | int nand_scan_tail(struct mtd_info *mtd) | |
4575 | { | |
862eba51 | 4576 | struct nand_chip *chip = mtd_to_nand(mtd); |
97de79e0 | 4577 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
3deb9979 | 4578 | struct nand_buffers *nbuf = NULL; |
11eaf6df | 4579 | int ret; |
3b85c321 | 4580 | |
e2414f4c | 4581 | /* New bad blocks should be marked in OOB, flash-based BBT, or both */ |
11eaf6df | 4582 | if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && |
78771049 BN |
4583 | !(chip->bbt_options & NAND_BBT_USE_FLASH))) { |
4584 | ret = -EINVAL; | |
4585 | goto err_ident; | |
4586 | } | |
e2414f4c | 4587 | |
3371d663 MG |
4588 | if (invalid_ecc_page_accessors(chip)) { |
4589 | pr_err("Invalid ECC page accessors setup\n"); | |
78771049 BN |
4590 | ret = -EINVAL; |
4591 | goto err_ident; | |
3371d663 MG |
4592 | } |
4593 | ||
f02ea4e6 | 4594 | if (!(chip->options & NAND_OWN_BUFFERS)) { |
3deb9979 | 4595 | nbuf = kzalloc(sizeof(*nbuf), GFP_KERNEL); |
78771049 BN |
4596 | if (!nbuf) { |
4597 | ret = -ENOMEM; | |
4598 | goto err_ident; | |
4599 | } | |
3deb9979 MY |
4600 | |
4601 | nbuf->ecccalc = kmalloc(mtd->oobsize, GFP_KERNEL); | |
4602 | if (!nbuf->ecccalc) { | |
4603 | ret = -ENOMEM; | |
4604 | goto err_free; | |
4605 | } | |
4606 | ||
4607 | nbuf->ecccode = kmalloc(mtd->oobsize, GFP_KERNEL); | |
4608 | if (!nbuf->ecccode) { | |
4609 | ret = -ENOMEM; | |
4610 | goto err_free; | |
4611 | } | |
4612 | ||
4613 | nbuf->databuf = kmalloc(mtd->writesize + mtd->oobsize, | |
4614 | GFP_KERNEL); | |
4615 | if (!nbuf->databuf) { | |
4616 | ret = -ENOMEM; | |
4617 | goto err_free; | |
4618 | } | |
f02ea4e6 HS |
4619 | |
4620 | chip->buffers = nbuf; | |
4621 | } else { | |
78771049 BN |
4622 | if (!chip->buffers) { |
4623 | ret = -ENOMEM; | |
4624 | goto err_ident; | |
4625 | } | |
f02ea4e6 | 4626 | } |
4bf63fcb | 4627 | |
7dcdcbef | 4628 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 4629 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 4630 | |
7aa65bfd | 4631 | /* |
8b6e50c9 | 4632 | * If no default placement scheme is given, select an appropriate one. |
7aa65bfd | 4633 | */ |
06f384c9 | 4634 | if (!mtd->ooblayout && |
e4225ae8 | 4635 | !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_BCH)) { |
61b03bd7 | 4636 | switch (mtd->oobsize) { |
1da177e4 | 4637 | case 8: |
1da177e4 | 4638 | case 16: |
41b207a7 | 4639 | mtd_set_ooblayout(mtd, &nand_ooblayout_sp_ops); |
1da177e4 LT |
4640 | break; |
4641 | case 64: | |
81ec5364 | 4642 | case 128: |
6a623e07 | 4643 | mtd_set_ooblayout(mtd, &nand_ooblayout_lp_hamming_ops); |
81ec5364 | 4644 | break; |
1da177e4 | 4645 | default: |
11eaf6df EG |
4646 | WARN(1, "No oob scheme defined for oobsize %d\n", |
4647 | mtd->oobsize); | |
4648 | ret = -EINVAL; | |
4649 | goto err_free; | |
1da177e4 LT |
4650 | } |
4651 | } | |
61b03bd7 | 4652 | |
61b03bd7 | 4653 | /* |
8b6e50c9 | 4654 | * Check ECC mode, default to software if 3byte/512byte hardware ECC is |
7aa65bfd | 4655 | * selected and we have 256 byte pagesize fallback to software ECC |
e0c7d767 | 4656 | */ |
956e944c | 4657 | |
97de79e0 | 4658 | switch (ecc->mode) { |
6e0cb135 SN |
4659 | case NAND_ECC_HW_OOB_FIRST: |
4660 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
97de79e0 | 4661 | if (!ecc->calculate || !ecc->correct || !ecc->hwctl) { |
11eaf6df EG |
4662 | WARN(1, "No ECC functions supplied; hardware ECC not possible\n"); |
4663 | ret = -EINVAL; | |
4664 | goto err_free; | |
6e0cb135 | 4665 | } |
97de79e0 HS |
4666 | if (!ecc->read_page) |
4667 | ecc->read_page = nand_read_page_hwecc_oob_first; | |
6e0cb135 | 4668 | |
6dfc6d25 | 4669 | case NAND_ECC_HW: |
8b6e50c9 | 4670 | /* Use standard hwecc read page function? */ |
97de79e0 HS |
4671 | if (!ecc->read_page) |
4672 | ecc->read_page = nand_read_page_hwecc; | |
4673 | if (!ecc->write_page) | |
4674 | ecc->write_page = nand_write_page_hwecc; | |
4675 | if (!ecc->read_page_raw) | |
4676 | ecc->read_page_raw = nand_read_page_raw; | |
4677 | if (!ecc->write_page_raw) | |
4678 | ecc->write_page_raw = nand_write_page_raw; | |
4679 | if (!ecc->read_oob) | |
4680 | ecc->read_oob = nand_read_oob_std; | |
4681 | if (!ecc->write_oob) | |
4682 | ecc->write_oob = nand_write_oob_std; | |
4683 | if (!ecc->read_subpage) | |
4684 | ecc->read_subpage = nand_read_subpage; | |
44991b3d | 4685 | if (!ecc->write_subpage && ecc->hwctl && ecc->calculate) |
97de79e0 | 4686 | ecc->write_subpage = nand_write_subpage_hwecc; |
f5bbdacc | 4687 | |
6dfc6d25 | 4688 | case NAND_ECC_HW_SYNDROME: |
97de79e0 HS |
4689 | if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && |
4690 | (!ecc->read_page || | |
4691 | ecc->read_page == nand_read_page_hwecc || | |
4692 | !ecc->write_page || | |
4693 | ecc->write_page == nand_write_page_hwecc)) { | |
11eaf6df EG |
4694 | WARN(1, "No ECC functions supplied; hardware ECC not possible\n"); |
4695 | ret = -EINVAL; | |
4696 | goto err_free; | |
6dfc6d25 | 4697 | } |
8b6e50c9 | 4698 | /* Use standard syndrome read/write page function? */ |
97de79e0 HS |
4699 | if (!ecc->read_page) |
4700 | ecc->read_page = nand_read_page_syndrome; | |
4701 | if (!ecc->write_page) | |
4702 | ecc->write_page = nand_write_page_syndrome; | |
4703 | if (!ecc->read_page_raw) | |
4704 | ecc->read_page_raw = nand_read_page_raw_syndrome; | |
4705 | if (!ecc->write_page_raw) | |
4706 | ecc->write_page_raw = nand_write_page_raw_syndrome; | |
4707 | if (!ecc->read_oob) | |
4708 | ecc->read_oob = nand_read_oob_syndrome; | |
4709 | if (!ecc->write_oob) | |
4710 | ecc->write_oob = nand_write_oob_syndrome; | |
4711 | ||
4712 | if (mtd->writesize >= ecc->size) { | |
4713 | if (!ecc->strength) { | |
11eaf6df EG |
4714 | WARN(1, "Driver must set ecc.strength when using hardware ECC\n"); |
4715 | ret = -EINVAL; | |
4716 | goto err_free; | |
e2788c98 | 4717 | } |
6dfc6d25 | 4718 | break; |
e2788c98 | 4719 | } |
2ac63d90 RM |
4720 | pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", |
4721 | ecc->size, mtd->writesize); | |
97de79e0 | 4722 | ecc->mode = NAND_ECC_SOFT; |
e9d4faed | 4723 | ecc->algo = NAND_ECC_HAMMING; |
61b03bd7 | 4724 | |
6dfc6d25 | 4725 | case NAND_ECC_SOFT: |
06f384c9 RM |
4726 | ret = nand_set_ecc_soft_ops(mtd); |
4727 | if (ret) { | |
11eaf6df EG |
4728 | ret = -EINVAL; |
4729 | goto err_free; | |
193bd400 ID |
4730 | } |
4731 | break; | |
4732 | ||
61b03bd7 | 4733 | case NAND_ECC_NONE: |
2ac63d90 | 4734 | pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n"); |
97de79e0 HS |
4735 | ecc->read_page = nand_read_page_raw; |
4736 | ecc->write_page = nand_write_page_raw; | |
4737 | ecc->read_oob = nand_read_oob_std; | |
4738 | ecc->read_page_raw = nand_read_page_raw; | |
4739 | ecc->write_page_raw = nand_write_page_raw; | |
4740 | ecc->write_oob = nand_write_oob_std; | |
4741 | ecc->size = mtd->writesize; | |
4742 | ecc->bytes = 0; | |
4743 | ecc->strength = 0; | |
1da177e4 | 4744 | break; |
956e944c | 4745 | |
1da177e4 | 4746 | default: |
11eaf6df EG |
4747 | WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->mode); |
4748 | ret = -EINVAL; | |
4749 | goto err_free; | |
1da177e4 | 4750 | } |
61b03bd7 | 4751 | |
9ce244b3 | 4752 | /* For many systems, the standard OOB write also works for raw */ |
97de79e0 HS |
4753 | if (!ecc->read_oob_raw) |
4754 | ecc->read_oob_raw = ecc->read_oob; | |
4755 | if (!ecc->write_oob_raw) | |
4756 | ecc->write_oob_raw = ecc->write_oob; | |
9ce244b3 | 4757 | |
846031d3 | 4758 | /* propagate ecc info to mtd_info */ |
846031d3 BB |
4759 | mtd->ecc_strength = ecc->strength; |
4760 | mtd->ecc_step_size = ecc->size; | |
67a9ad9b | 4761 | |
7aa65bfd TG |
4762 | /* |
4763 | * Set the number of read / write steps for one page depending on ECC | |
8b6e50c9 | 4764 | * mode. |
7aa65bfd | 4765 | */ |
97de79e0 HS |
4766 | ecc->steps = mtd->writesize / ecc->size; |
4767 | if (ecc->steps * ecc->size != mtd->writesize) { | |
11eaf6df EG |
4768 | WARN(1, "Invalid ECC parameters\n"); |
4769 | ret = -EINVAL; | |
4770 | goto err_free; | |
1da177e4 | 4771 | } |
97de79e0 | 4772 | ecc->total = ecc->steps * ecc->bytes; |
61b03bd7 | 4773 | |
846031d3 BB |
4774 | /* |
4775 | * The number of bytes available for a client to place data into | |
4776 | * the out of band area. | |
4777 | */ | |
4778 | ret = mtd_ooblayout_count_freebytes(mtd); | |
4779 | if (ret < 0) | |
4780 | ret = 0; | |
4781 | ||
4782 | mtd->oobavail = ret; | |
4783 | ||
4784 | /* ECC sanity check: warn if it's too weak */ | |
4785 | if (!nand_ecc_strength_good(mtd)) | |
4786 | pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n", | |
4787 | mtd->name); | |
4788 | ||
8b6e50c9 | 4789 | /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ |
1d0ed69d | 4790 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { |
97de79e0 | 4791 | switch (ecc->steps) { |
29072b96 TG |
4792 | case 2: |
4793 | mtd->subpage_sft = 1; | |
4794 | break; | |
4795 | case 4: | |
4796 | case 8: | |
81ec5364 | 4797 | case 16: |
29072b96 TG |
4798 | mtd->subpage_sft = 2; |
4799 | break; | |
4800 | } | |
4801 | } | |
4802 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
4803 | ||
04bbd0ea | 4804 | /* Initialize state */ |
ace4dfee | 4805 | chip->state = FL_READY; |
1da177e4 | 4806 | |
1da177e4 | 4807 | /* Invalidate the pagebuffer reference */ |
ace4dfee | 4808 | chip->pagebuf = -1; |
1da177e4 | 4809 | |
a5ff4f10 | 4810 | /* Large page NAND with SOFT_ECC should support subpage reads */ |
4007e2d1 RL |
4811 | switch (ecc->mode) { |
4812 | case NAND_ECC_SOFT: | |
4007e2d1 RL |
4813 | if (chip->page_shift > 9) |
4814 | chip->options |= NAND_SUBPAGE_READ; | |
4815 | break; | |
4816 | ||
4817 | default: | |
4818 | break; | |
4819 | } | |
a5ff4f10 | 4820 | |
1da177e4 | 4821 | /* Fill in remaining MTD driver data */ |
963d1c28 | 4822 | mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH; |
93edbad6 ML |
4823 | mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : |
4824 | MTD_CAP_NANDFLASH; | |
3c3c10bb AB |
4825 | mtd->_erase = nand_erase; |
4826 | mtd->_point = NULL; | |
4827 | mtd->_unpoint = NULL; | |
4828 | mtd->_read = nand_read; | |
4829 | mtd->_write = nand_write; | |
4830 | mtd->_panic_write = panic_nand_write; | |
4831 | mtd->_read_oob = nand_read_oob; | |
4832 | mtd->_write_oob = nand_write_oob; | |
4833 | mtd->_sync = nand_sync; | |
4834 | mtd->_lock = NULL; | |
4835 | mtd->_unlock = NULL; | |
4836 | mtd->_suspend = nand_suspend; | |
4837 | mtd->_resume = nand_resume; | |
72ea4036 | 4838 | mtd->_reboot = nand_shutdown; |
8471bb73 | 4839 | mtd->_block_isreserved = nand_block_isreserved; |
3c3c10bb AB |
4840 | mtd->_block_isbad = nand_block_isbad; |
4841 | mtd->_block_markbad = nand_block_markbad; | |
5671842f | 4842 | mtd->_max_bad_blocks = nand_max_bad_blocks; |
cbcab65a | 4843 | mtd->writebufsize = mtd->writesize; |
1da177e4 | 4844 | |
ea3b2ea2 SL |
4845 | /* |
4846 | * Initialize bitflip_threshold to its default prior scan_bbt() call. | |
4847 | * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be | |
4848 | * properly set. | |
4849 | */ | |
4850 | if (!mtd->bitflip_threshold) | |
240181fd | 4851 | mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4); |
1da177e4 | 4852 | |
0040bf38 | 4853 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 4854 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 4855 | return 0; |
1da177e4 LT |
4856 | |
4857 | /* Build bad block table */ | |
44d4182e BN |
4858 | ret = chip->scan_bbt(mtd); |
4859 | if (ret) | |
4860 | goto err_free; | |
4861 | return 0; | |
4862 | ||
11eaf6df | 4863 | err_free: |
3deb9979 MY |
4864 | if (nbuf) { |
4865 | kfree(nbuf->databuf); | |
4866 | kfree(nbuf->ecccode); | |
4867 | kfree(nbuf->ecccalc); | |
4868 | kfree(nbuf); | |
4869 | } | |
78771049 BN |
4870 | |
4871 | err_ident: | |
4872 | /* Clean up nand_scan_ident(). */ | |
4873 | ||
4874 | /* Free manufacturer priv data. */ | |
4875 | nand_manufacturer_cleanup(chip); | |
4876 | ||
11eaf6df | 4877 | return ret; |
1da177e4 | 4878 | } |
7351d3a5 | 4879 | EXPORT_SYMBOL(nand_scan_tail); |
1da177e4 | 4880 | |
8b6e50c9 BN |
4881 | /* |
4882 | * is_module_text_address() isn't exported, and it's mostly a pointless | |
7351d3a5 | 4883 | * test if this is a module _anyway_ -- they'd have to try _really_ hard |
8b6e50c9 BN |
4884 | * to call us from in-kernel code if the core NAND support is modular. |
4885 | */ | |
3b85c321 DW |
4886 | #ifdef MODULE |
4887 | #define caller_is_module() (1) | |
4888 | #else | |
4889 | #define caller_is_module() \ | |
a6e6abd5 | 4890 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
4891 | #endif |
4892 | ||
4893 | /** | |
4894 | * nand_scan - [NAND Interface] Scan for the NAND device | |
8b6e50c9 BN |
4895 | * @mtd: MTD device structure |
4896 | * @maxchips: number of chips to scan for | |
3b85c321 | 4897 | * |
8b6e50c9 BN |
4898 | * This fills out all the uninitialized function pointers with the defaults. |
4899 | * The flash ID is read and the mtd/chip structures are filled with the | |
20c07a5b | 4900 | * appropriate values. |
3b85c321 DW |
4901 | */ |
4902 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
4903 | { | |
4904 | int ret; | |
4905 | ||
5e81e88a | 4906 | ret = nand_scan_ident(mtd, maxchips, NULL); |
3b85c321 DW |
4907 | if (!ret) |
4908 | ret = nand_scan_tail(mtd); | |
4909 | return ret; | |
4910 | } | |
7351d3a5 | 4911 | EXPORT_SYMBOL(nand_scan); |
3b85c321 | 4912 | |
1da177e4 | 4913 | /** |
d44154f9 RW |
4914 | * nand_cleanup - [NAND Interface] Free resources held by the NAND device |
4915 | * @chip: NAND chip object | |
8b6e50c9 | 4916 | */ |
d44154f9 | 4917 | void nand_cleanup(struct nand_chip *chip) |
1da177e4 | 4918 | { |
e4225ae8 | 4919 | if (chip->ecc.mode == NAND_ECC_SOFT && |
06f384c9 | 4920 | chip->ecc.algo == NAND_ECC_BCH) |
193bd400 ID |
4921 | nand_bch_free((struct nand_bch_control *)chip->ecc.priv); |
4922 | ||
d8e725dd BB |
4923 | nand_release_data_interface(chip); |
4924 | ||
fa671646 | 4925 | /* Free bad block table memory */ |
ace4dfee | 4926 | kfree(chip->bbt); |
3deb9979 MY |
4927 | if (!(chip->options & NAND_OWN_BUFFERS) && chip->buffers) { |
4928 | kfree(chip->buffers->databuf); | |
4929 | kfree(chip->buffers->ecccode); | |
4930 | kfree(chip->buffers->ecccalc); | |
4bf63fcb | 4931 | kfree(chip->buffers); |
3deb9979 | 4932 | } |
58373ff0 BN |
4933 | |
4934 | /* Free bad block descriptor memory */ | |
4935 | if (chip->badblock_pattern && chip->badblock_pattern->options | |
4936 | & NAND_BBT_DYNAMICSTRUCT) | |
4937 | kfree(chip->badblock_pattern); | |
abbe26d1 BB |
4938 | |
4939 | /* Free manufacturer priv data. */ | |
4940 | nand_manufacturer_cleanup(chip); | |
1da177e4 | 4941 | } |
d44154f9 RW |
4942 | EXPORT_SYMBOL_GPL(nand_cleanup); |
4943 | ||
4944 | /** | |
4945 | * nand_release - [NAND Interface] Unregister the MTD device and free resources | |
4946 | * held by the NAND device | |
4947 | * @mtd: MTD device structure | |
4948 | */ | |
4949 | void nand_release(struct mtd_info *mtd) | |
4950 | { | |
4951 | mtd_device_unregister(mtd); | |
4952 | nand_cleanup(mtd_to_nand(mtd)); | |
4953 | } | |
e0c7d767 | 4954 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 | 4955 | |
e0c7d767 | 4956 | MODULE_LICENSE("GPL"); |
7351d3a5 FF |
4957 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); |
4958 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
e0c7d767 | 4959 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |