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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand.c | |
3 | * | |
4 | * Overview: | |
5 | * This is the generic MTD driver for NAND flash devices. It should be | |
6 | * capable of working with almost all NAND chips currently available. | |
61b03bd7 | 7 | * |
1da177e4 | 8 | * Additional technical information is available on |
8b2b403c | 9 | * http://www.linux-mtd.infradead.org/doc/nand.html |
61b03bd7 | 10 | * |
1da177e4 | 11 | * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) |
ace4dfee | 12 | * 2002-2006 Thomas Gleixner (tglx@linutronix.de) |
1da177e4 | 13 | * |
ace4dfee | 14 | * Credits: |
61b03bd7 TG |
15 | * David Woodhouse for adding multichip support |
16 | * | |
1da177e4 LT |
17 | * Aleph One Ltd. and Toby Churchill Ltd. for supporting the |
18 | * rework for 2K page size chips | |
19 | * | |
ace4dfee | 20 | * TODO: |
1da177e4 LT |
21 | * Enable cached programming for 2k page size chips |
22 | * Check, if mtd->ecctype should be set to MTD_ECC_HW | |
7854d3f7 | 23 | * if we have HW ECC support. |
c0b8ba7b | 24 | * BBT table is not serialized, has to be fixed |
1da177e4 | 25 | * |
1da177e4 LT |
26 | * This program is free software; you can redistribute it and/or modify |
27 | * it under the terms of the GNU General Public License version 2 as | |
28 | * published by the Free Software Foundation. | |
29 | * | |
30 | */ | |
31 | ||
20171642 EG |
32 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
33 | ||
552d9205 | 34 | #include <linux/module.h> |
1da177e4 LT |
35 | #include <linux/delay.h> |
36 | #include <linux/errno.h> | |
7aa65bfd | 37 | #include <linux/err.h> |
1da177e4 LT |
38 | #include <linux/sched.h> |
39 | #include <linux/slab.h> | |
66507c7b | 40 | #include <linux/mm.h> |
1da177e4 LT |
41 | #include <linux/types.h> |
42 | #include <linux/mtd/mtd.h> | |
43 | #include <linux/mtd/nand.h> | |
44 | #include <linux/mtd/nand_ecc.h> | |
193bd400 | 45 | #include <linux/mtd/nand_bch.h> |
1da177e4 LT |
46 | #include <linux/interrupt.h> |
47 | #include <linux/bitops.h> | |
8fe833c1 | 48 | #include <linux/leds.h> |
7351d3a5 | 49 | #include <linux/io.h> |
1da177e4 | 50 | #include <linux/mtd/partitions.h> |
1da177e4 LT |
51 | |
52 | /* Define default oob placement schemes for large and small page devices */ | |
5bd34c09 | 53 | static struct nand_ecclayout nand_oob_8 = { |
1da177e4 LT |
54 | .eccbytes = 3, |
55 | .eccpos = {0, 1, 2}, | |
5bd34c09 TG |
56 | .oobfree = { |
57 | {.offset = 3, | |
58 | .length = 2}, | |
59 | {.offset = 6, | |
f8ac0414 | 60 | .length = 2} } |
1da177e4 LT |
61 | }; |
62 | ||
5bd34c09 | 63 | static struct nand_ecclayout nand_oob_16 = { |
1da177e4 LT |
64 | .eccbytes = 6, |
65 | .eccpos = {0, 1, 2, 3, 6, 7}, | |
5bd34c09 TG |
66 | .oobfree = { |
67 | {.offset = 8, | |
f8ac0414 | 68 | . length = 8} } |
1da177e4 LT |
69 | }; |
70 | ||
5bd34c09 | 71 | static struct nand_ecclayout nand_oob_64 = { |
1da177e4 LT |
72 | .eccbytes = 24, |
73 | .eccpos = { | |
e0c7d767 DW |
74 | 40, 41, 42, 43, 44, 45, 46, 47, |
75 | 48, 49, 50, 51, 52, 53, 54, 55, | |
76 | 56, 57, 58, 59, 60, 61, 62, 63}, | |
5bd34c09 TG |
77 | .oobfree = { |
78 | {.offset = 2, | |
f8ac0414 | 79 | .length = 38} } |
1da177e4 LT |
80 | }; |
81 | ||
81ec5364 TG |
82 | static struct nand_ecclayout nand_oob_128 = { |
83 | .eccbytes = 48, | |
84 | .eccpos = { | |
85 | 80, 81, 82, 83, 84, 85, 86, 87, | |
86 | 88, 89, 90, 91, 92, 93, 94, 95, | |
87 | 96, 97, 98, 99, 100, 101, 102, 103, | |
88 | 104, 105, 106, 107, 108, 109, 110, 111, | |
89 | 112, 113, 114, 115, 116, 117, 118, 119, | |
90 | 120, 121, 122, 123, 124, 125, 126, 127}, | |
91 | .oobfree = { | |
92 | {.offset = 2, | |
f8ac0414 | 93 | .length = 78} } |
81ec5364 TG |
94 | }; |
95 | ||
6a8214aa | 96 | static int nand_get_device(struct mtd_info *mtd, int new_state); |
1da177e4 | 97 | |
8593fbc6 TG |
98 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
99 | struct mtd_oob_ops *ops); | |
100 | ||
d470a97c | 101 | /* |
8e87d782 | 102 | * For devices which display every fart in the system on a separate LED. Is |
d470a97c TG |
103 | * compiled away when LED support is disabled. |
104 | */ | |
105 | DEFINE_LED_TRIGGER(nand_led_trigger); | |
106 | ||
6fe5a6ac VS |
107 | static int check_offs_len(struct mtd_info *mtd, |
108 | loff_t ofs, uint64_t len) | |
109 | { | |
110 | struct nand_chip *chip = mtd->priv; | |
111 | int ret = 0; | |
112 | ||
113 | /* Start address must align on block boundary */ | |
daae74ca | 114 | if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 115 | pr_debug("%s: unaligned address\n", __func__); |
6fe5a6ac VS |
116 | ret = -EINVAL; |
117 | } | |
118 | ||
119 | /* Length must align on block boundary */ | |
daae74ca | 120 | if (len & ((1ULL << chip->phys_erase_shift) - 1)) { |
289c0522 | 121 | pr_debug("%s: length not block aligned\n", __func__); |
6fe5a6ac VS |
122 | ret = -EINVAL; |
123 | } | |
124 | ||
6fe5a6ac VS |
125 | return ret; |
126 | } | |
127 | ||
1da177e4 LT |
128 | /** |
129 | * nand_release_device - [GENERIC] release chip | |
8b6e50c9 | 130 | * @mtd: MTD device structure |
61b03bd7 | 131 | * |
b0bb6903 | 132 | * Release chip lock and wake up anyone waiting on the device. |
1da177e4 | 133 | */ |
e0c7d767 | 134 | static void nand_release_device(struct mtd_info *mtd) |
1da177e4 | 135 | { |
ace4dfee | 136 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 137 | |
a36ed299 | 138 | /* Release the controller and the chip */ |
ace4dfee TG |
139 | spin_lock(&chip->controller->lock); |
140 | chip->controller->active = NULL; | |
141 | chip->state = FL_READY; | |
142 | wake_up(&chip->controller->wq); | |
143 | spin_unlock(&chip->controller->lock); | |
1da177e4 LT |
144 | } |
145 | ||
146 | /** | |
147 | * nand_read_byte - [DEFAULT] read one byte from the chip | |
8b6e50c9 | 148 | * @mtd: MTD device structure |
1da177e4 | 149 | * |
7854d3f7 | 150 | * Default read function for 8bit buswidth |
1da177e4 | 151 | */ |
58dd8f2b | 152 | static uint8_t nand_read_byte(struct mtd_info *mtd) |
1da177e4 | 153 | { |
ace4dfee TG |
154 | struct nand_chip *chip = mtd->priv; |
155 | return readb(chip->IO_ADDR_R); | |
1da177e4 LT |
156 | } |
157 | ||
1da177e4 | 158 | /** |
064a7694 | 159 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
7854d3f7 | 160 | * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip |
8b6e50c9 | 161 | * @mtd: MTD device structure |
1da177e4 | 162 | * |
7854d3f7 BN |
163 | * Default read function for 16bit buswidth with endianness conversion. |
164 | * | |
1da177e4 | 165 | */ |
58dd8f2b | 166 | static uint8_t nand_read_byte16(struct mtd_info *mtd) |
1da177e4 | 167 | { |
ace4dfee TG |
168 | struct nand_chip *chip = mtd->priv; |
169 | return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); | |
1da177e4 LT |
170 | } |
171 | ||
1da177e4 LT |
172 | /** |
173 | * nand_read_word - [DEFAULT] read one word from the chip | |
8b6e50c9 | 174 | * @mtd: MTD device structure |
1da177e4 | 175 | * |
7854d3f7 | 176 | * Default read function for 16bit buswidth without endianness conversion. |
1da177e4 LT |
177 | */ |
178 | static u16 nand_read_word(struct mtd_info *mtd) | |
179 | { | |
ace4dfee TG |
180 | struct nand_chip *chip = mtd->priv; |
181 | return readw(chip->IO_ADDR_R); | |
1da177e4 LT |
182 | } |
183 | ||
1da177e4 LT |
184 | /** |
185 | * nand_select_chip - [DEFAULT] control CE line | |
8b6e50c9 BN |
186 | * @mtd: MTD device structure |
187 | * @chipnr: chipnumber to select, -1 for deselect | |
1da177e4 LT |
188 | * |
189 | * Default select function for 1 chip devices. | |
190 | */ | |
ace4dfee | 191 | static void nand_select_chip(struct mtd_info *mtd, int chipnr) |
1da177e4 | 192 | { |
ace4dfee TG |
193 | struct nand_chip *chip = mtd->priv; |
194 | ||
195 | switch (chipnr) { | |
1da177e4 | 196 | case -1: |
ace4dfee | 197 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
1da177e4 LT |
198 | break; |
199 | case 0: | |
1da177e4 LT |
200 | break; |
201 | ||
202 | default: | |
203 | BUG(); | |
204 | } | |
205 | } | |
206 | ||
05f78359 UKK |
207 | /** |
208 | * nand_write_byte - [DEFAULT] write single byte to chip | |
209 | * @mtd: MTD device structure | |
210 | * @byte: value to write | |
211 | * | |
212 | * Default function to write a byte to I/O[7:0] | |
213 | */ | |
214 | static void nand_write_byte(struct mtd_info *mtd, uint8_t byte) | |
215 | { | |
216 | struct nand_chip *chip = mtd->priv; | |
217 | ||
218 | chip->write_buf(mtd, &byte, 1); | |
219 | } | |
220 | ||
221 | /** | |
222 | * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16 | |
223 | * @mtd: MTD device structure | |
224 | * @byte: value to write | |
225 | * | |
226 | * Default function to write a byte to I/O[7:0] on a 16-bit wide chip. | |
227 | */ | |
228 | static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) | |
229 | { | |
230 | struct nand_chip *chip = mtd->priv; | |
231 | uint16_t word = byte; | |
232 | ||
233 | /* | |
234 | * It's not entirely clear what should happen to I/O[15:8] when writing | |
235 | * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads: | |
236 | * | |
237 | * When the host supports a 16-bit bus width, only data is | |
238 | * transferred at the 16-bit width. All address and command line | |
239 | * transfers shall use only the lower 8-bits of the data bus. During | |
240 | * command transfers, the host may place any value on the upper | |
241 | * 8-bits of the data bus. During address transfers, the host shall | |
242 | * set the upper 8-bits of the data bus to 00h. | |
243 | * | |
244 | * One user of the write_byte callback is nand_onfi_set_features. The | |
245 | * four parameters are specified to be written to I/O[7:0], but this is | |
246 | * neither an address nor a command transfer. Let's assume a 0 on the | |
247 | * upper I/O lines is OK. | |
248 | */ | |
249 | chip->write_buf(mtd, (uint8_t *)&word, 2); | |
250 | } | |
251 | ||
1da177e4 LT |
252 | /** |
253 | * nand_write_buf - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
254 | * @mtd: MTD device structure |
255 | * @buf: data buffer | |
256 | * @len: number of bytes to write | |
1da177e4 | 257 | * |
7854d3f7 | 258 | * Default write function for 8bit buswidth. |
1da177e4 | 259 | */ |
58dd8f2b | 260 | static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 261 | { |
ace4dfee | 262 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 263 | |
76413839 | 264 | iowrite8_rep(chip->IO_ADDR_W, buf, len); |
1da177e4 LT |
265 | } |
266 | ||
267 | /** | |
61b03bd7 | 268 | * nand_read_buf - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
269 | * @mtd: MTD device structure |
270 | * @buf: buffer to store date | |
271 | * @len: number of bytes to read | |
1da177e4 | 272 | * |
7854d3f7 | 273 | * Default read function for 8bit buswidth. |
1da177e4 | 274 | */ |
58dd8f2b | 275 | static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 276 | { |
ace4dfee | 277 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 278 | |
76413839 | 279 | ioread8_rep(chip->IO_ADDR_R, buf, len); |
1da177e4 LT |
280 | } |
281 | ||
1da177e4 LT |
282 | /** |
283 | * nand_write_buf16 - [DEFAULT] write buffer to chip | |
8b6e50c9 BN |
284 | * @mtd: MTD device structure |
285 | * @buf: data buffer | |
286 | * @len: number of bytes to write | |
1da177e4 | 287 | * |
7854d3f7 | 288 | * Default write function for 16bit buswidth. |
1da177e4 | 289 | */ |
58dd8f2b | 290 | static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) |
1da177e4 | 291 | { |
ace4dfee | 292 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 293 | u16 *p = (u16 *) buf; |
61b03bd7 | 294 | |
76413839 | 295 | iowrite16_rep(chip->IO_ADDR_W, p, len >> 1); |
1da177e4 LT |
296 | } |
297 | ||
298 | /** | |
61b03bd7 | 299 | * nand_read_buf16 - [DEFAULT] read chip data into buffer |
8b6e50c9 BN |
300 | * @mtd: MTD device structure |
301 | * @buf: buffer to store date | |
302 | * @len: number of bytes to read | |
1da177e4 | 303 | * |
7854d3f7 | 304 | * Default read function for 16bit buswidth. |
1da177e4 | 305 | */ |
58dd8f2b | 306 | static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) |
1da177e4 | 307 | { |
ace4dfee | 308 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 309 | u16 *p = (u16 *) buf; |
1da177e4 | 310 | |
76413839 | 311 | ioread16_rep(chip->IO_ADDR_R, p, len >> 1); |
1da177e4 LT |
312 | } |
313 | ||
1da177e4 LT |
314 | /** |
315 | * nand_block_bad - [DEFAULT] Read bad block marker from the chip | |
8b6e50c9 BN |
316 | * @mtd: MTD device structure |
317 | * @ofs: offset from device start | |
318 | * @getchip: 0, if the chip is already selected | |
1da177e4 | 319 | * |
61b03bd7 | 320 | * Check, if the block is bad. |
1da177e4 LT |
321 | */ |
322 | static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) | |
323 | { | |
cdbec050 | 324 | int page, chipnr, res = 0, i = 0; |
ace4dfee | 325 | struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
326 | u16 bad; |
327 | ||
5fb1549d | 328 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) |
b60b08b0 KC |
329 | ofs += mtd->erasesize - mtd->writesize; |
330 | ||
1a12f46a TK |
331 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; |
332 | ||
1da177e4 | 333 | if (getchip) { |
ace4dfee | 334 | chipnr = (int)(ofs >> chip->chip_shift); |
1da177e4 | 335 | |
6a8214aa | 336 | nand_get_device(mtd, FL_READING); |
1da177e4 LT |
337 | |
338 | /* Select the NAND device */ | |
ace4dfee | 339 | chip->select_chip(mtd, chipnr); |
1a12f46a | 340 | } |
1da177e4 | 341 | |
cdbec050 BN |
342 | do { |
343 | if (chip->options & NAND_BUSWIDTH_16) { | |
344 | chip->cmdfunc(mtd, NAND_CMD_READOOB, | |
345 | chip->badblockpos & 0xFE, page); | |
346 | bad = cpu_to_le16(chip->read_word(mtd)); | |
347 | if (chip->badblockpos & 0x1) | |
348 | bad >>= 8; | |
349 | else | |
350 | bad &= 0xFF; | |
351 | } else { | |
352 | chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, | |
353 | page); | |
354 | bad = chip->read_byte(mtd); | |
355 | } | |
356 | ||
357 | if (likely(chip->badblockbits == 8)) | |
358 | res = bad != 0xFF; | |
e0b58d0a | 359 | else |
cdbec050 BN |
360 | res = hweight8(bad) < chip->badblockbits; |
361 | ofs += mtd->writesize; | |
362 | page = (int)(ofs >> chip->page_shift) & chip->pagemask; | |
363 | i++; | |
364 | } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); | |
e0b58d0a | 365 | |
b0bb6903 HS |
366 | if (getchip) { |
367 | chip->select_chip(mtd, -1); | |
1da177e4 | 368 | nand_release_device(mtd); |
b0bb6903 | 369 | } |
61b03bd7 | 370 | |
1da177e4 LT |
371 | return res; |
372 | } | |
373 | ||
374 | /** | |
5a0edb25 | 375 | * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker |
8b6e50c9 BN |
376 | * @mtd: MTD device structure |
377 | * @ofs: offset from device start | |
1da177e4 | 378 | * |
8b6e50c9 | 379 | * This is the default implementation, which can be overridden by a hardware |
5a0edb25 BN |
380 | * specific driver. It provides the details for writing a bad block marker to a |
381 | * block. | |
382 | */ | |
383 | static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
384 | { | |
385 | struct nand_chip *chip = mtd->priv; | |
386 | struct mtd_oob_ops ops; | |
387 | uint8_t buf[2] = { 0, 0 }; | |
388 | int ret = 0, res, i = 0; | |
389 | ||
390 | ops.datbuf = NULL; | |
391 | ops.oobbuf = buf; | |
392 | ops.ooboffs = chip->badblockpos; | |
393 | if (chip->options & NAND_BUSWIDTH_16) { | |
394 | ops.ooboffs &= ~0x01; | |
395 | ops.len = ops.ooblen = 2; | |
396 | } else { | |
397 | ops.len = ops.ooblen = 1; | |
398 | } | |
399 | ops.mode = MTD_OPS_PLACE_OOB; | |
400 | ||
401 | /* Write to first/last page(s) if necessary */ | |
402 | if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) | |
403 | ofs += mtd->erasesize - mtd->writesize; | |
404 | do { | |
405 | res = nand_do_write_oob(mtd, ofs, &ops); | |
406 | if (!ret) | |
407 | ret = res; | |
408 | ||
409 | i++; | |
410 | ofs += mtd->writesize; | |
411 | } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); | |
412 | ||
413 | return ret; | |
414 | } | |
415 | ||
416 | /** | |
417 | * nand_block_markbad_lowlevel - mark a block bad | |
418 | * @mtd: MTD device structure | |
419 | * @ofs: offset from device start | |
420 | * | |
421 | * This function performs the generic NAND bad block marking steps (i.e., bad | |
422 | * block table(s) and/or marker(s)). We only allow the hardware driver to | |
423 | * specify how to write bad block markers to OOB (chip->block_markbad). | |
424 | * | |
b32843b7 | 425 | * We try operations in the following order: |
e2414f4c | 426 | * (1) erase the affected block, to allow OOB marker to be written cleanly |
b32843b7 BN |
427 | * (2) write bad block marker to OOB area of affected block (unless flag |
428 | * NAND_BBT_NO_OOB_BBM is present) | |
429 | * (3) update the BBT | |
430 | * Note that we retain the first error encountered in (2) or (3), finish the | |
e2414f4c | 431 | * procedures, and dump the error in the end. |
1da177e4 | 432 | */ |
5a0edb25 | 433 | static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 434 | { |
ace4dfee | 435 | struct nand_chip *chip = mtd->priv; |
b32843b7 | 436 | int res, ret = 0; |
61b03bd7 | 437 | |
b32843b7 | 438 | if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { |
00918429 BN |
439 | struct erase_info einfo; |
440 | ||
441 | /* Attempt erase before marking OOB */ | |
442 | memset(&einfo, 0, sizeof(einfo)); | |
443 | einfo.mtd = mtd; | |
444 | einfo.addr = ofs; | |
daae74ca | 445 | einfo.len = 1ULL << chip->phys_erase_shift; |
00918429 | 446 | nand_erase_nand(mtd, &einfo, 0); |
1da177e4 | 447 | |
b32843b7 | 448 | /* Write bad block marker to OOB */ |
6a8214aa | 449 | nand_get_device(mtd, FL_WRITING); |
5a0edb25 | 450 | ret = chip->block_markbad(mtd, ofs); |
c0b8ba7b | 451 | nand_release_device(mtd); |
f1a28c02 | 452 | } |
e2414f4c | 453 | |
b32843b7 BN |
454 | /* Mark block bad in BBT */ |
455 | if (chip->bbt) { | |
456 | res = nand_markbad_bbt(mtd, ofs); | |
e2414f4c BN |
457 | if (!ret) |
458 | ret = res; | |
459 | } | |
460 | ||
f1a28c02 TG |
461 | if (!ret) |
462 | mtd->ecc_stats.badblocks++; | |
c0b8ba7b | 463 | |
f1a28c02 | 464 | return ret; |
1da177e4 LT |
465 | } |
466 | ||
61b03bd7 | 467 | /** |
1da177e4 | 468 | * nand_check_wp - [GENERIC] check if the chip is write protected |
8b6e50c9 | 469 | * @mtd: MTD device structure |
1da177e4 | 470 | * |
8b6e50c9 BN |
471 | * Check, if the device is write protected. The function expects, that the |
472 | * device is already selected. | |
1da177e4 | 473 | */ |
e0c7d767 | 474 | static int nand_check_wp(struct mtd_info *mtd) |
1da177e4 | 475 | { |
ace4dfee | 476 | struct nand_chip *chip = mtd->priv; |
93edbad6 | 477 | |
8b6e50c9 | 478 | /* Broken xD cards report WP despite being writable */ |
93edbad6 ML |
479 | if (chip->options & NAND_BROKEN_XD) |
480 | return 0; | |
481 | ||
1da177e4 | 482 | /* Check the WP bit */ |
ace4dfee TG |
483 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
484 | return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1; | |
1da177e4 LT |
485 | } |
486 | ||
487 | /** | |
488 | * nand_block_checkbad - [GENERIC] Check if a block is marked bad | |
8b6e50c9 BN |
489 | * @mtd: MTD device structure |
490 | * @ofs: offset from device start | |
491 | * @getchip: 0, if the chip is already selected | |
492 | * @allowbbt: 1, if its allowed to access the bbt area | |
1da177e4 LT |
493 | * |
494 | * Check, if the block is bad. Either by reading the bad block table or | |
495 | * calling of the scan function. | |
496 | */ | |
2c0a2bed TG |
497 | static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, |
498 | int allowbbt) | |
1da177e4 | 499 | { |
ace4dfee | 500 | struct nand_chip *chip = mtd->priv; |
61b03bd7 | 501 | |
ace4dfee TG |
502 | if (!chip->bbt) |
503 | return chip->block_bad(mtd, ofs, getchip); | |
61b03bd7 | 504 | |
1da177e4 | 505 | /* Return info from the table */ |
e0c7d767 | 506 | return nand_isbad_bbt(mtd, ofs, allowbbt); |
1da177e4 LT |
507 | } |
508 | ||
2af7c653 SK |
509 | /** |
510 | * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands. | |
8b6e50c9 BN |
511 | * @mtd: MTD device structure |
512 | * @timeo: Timeout | |
2af7c653 SK |
513 | * |
514 | * Helper function for nand_wait_ready used when needing to wait in interrupt | |
515 | * context. | |
516 | */ | |
517 | static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo) | |
518 | { | |
519 | struct nand_chip *chip = mtd->priv; | |
520 | int i; | |
521 | ||
522 | /* Wait for the device to get ready */ | |
523 | for (i = 0; i < timeo; i++) { | |
524 | if (chip->dev_ready(mtd)) | |
525 | break; | |
526 | touch_softlockup_watchdog(); | |
527 | mdelay(1); | |
528 | } | |
529 | } | |
530 | ||
7854d3f7 | 531 | /* Wait for the ready pin, after a command. The timeout is caught later. */ |
4b648b02 | 532 | void nand_wait_ready(struct mtd_info *mtd) |
3b88775c | 533 | { |
ace4dfee | 534 | struct nand_chip *chip = mtd->priv; |
ca6a2489 | 535 | unsigned long timeo = jiffies + msecs_to_jiffies(20); |
3b88775c | 536 | |
2af7c653 SK |
537 | /* 400ms timeout */ |
538 | if (in_interrupt() || oops_in_progress) | |
539 | return panic_nand_wait_ready(mtd, 400); | |
540 | ||
8fe833c1 | 541 | led_trigger_event(nand_led_trigger, LED_FULL); |
7854d3f7 | 542 | /* Wait until command is processed or timeout occurs */ |
3b88775c | 543 | do { |
ace4dfee | 544 | if (chip->dev_ready(mtd)) |
8fe833c1 | 545 | break; |
8446f1d3 | 546 | touch_softlockup_watchdog(); |
61b03bd7 | 547 | } while (time_before(jiffies, timeo)); |
8fe833c1 | 548 | led_trigger_event(nand_led_trigger, LED_OFF); |
3b88775c | 549 | } |
4b648b02 | 550 | EXPORT_SYMBOL_GPL(nand_wait_ready); |
3b88775c | 551 | |
1da177e4 LT |
552 | /** |
553 | * nand_command - [DEFAULT] Send command to NAND device | |
8b6e50c9 BN |
554 | * @mtd: MTD device structure |
555 | * @command: the command to be sent | |
556 | * @column: the column address for this command, -1 if none | |
557 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 558 | * |
8b6e50c9 | 559 | * Send command to NAND device. This function is used for small page devices |
51148f1f | 560 | * (512 Bytes per page). |
1da177e4 | 561 | */ |
7abd3ef9 TG |
562 | static void nand_command(struct mtd_info *mtd, unsigned int command, |
563 | int column, int page_addr) | |
1da177e4 | 564 | { |
ace4dfee | 565 | register struct nand_chip *chip = mtd->priv; |
7abd3ef9 | 566 | int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; |
1da177e4 | 567 | |
8b6e50c9 | 568 | /* Write out the command to the device */ |
1da177e4 LT |
569 | if (command == NAND_CMD_SEQIN) { |
570 | int readcmd; | |
571 | ||
28318776 | 572 | if (column >= mtd->writesize) { |
1da177e4 | 573 | /* OOB area */ |
28318776 | 574 | column -= mtd->writesize; |
1da177e4 LT |
575 | readcmd = NAND_CMD_READOOB; |
576 | } else if (column < 256) { | |
577 | /* First 256 bytes --> READ0 */ | |
578 | readcmd = NAND_CMD_READ0; | |
579 | } else { | |
580 | column -= 256; | |
581 | readcmd = NAND_CMD_READ1; | |
582 | } | |
ace4dfee | 583 | chip->cmd_ctrl(mtd, readcmd, ctrl); |
7abd3ef9 | 584 | ctrl &= ~NAND_CTRL_CHANGE; |
1da177e4 | 585 | } |
ace4dfee | 586 | chip->cmd_ctrl(mtd, command, ctrl); |
1da177e4 | 587 | |
8b6e50c9 | 588 | /* Address cycle, when necessary */ |
7abd3ef9 TG |
589 | ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; |
590 | /* Serially input address */ | |
591 | if (column != -1) { | |
592 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
593 | if (chip->options & NAND_BUSWIDTH_16 && |
594 | !nand_opcode_8bits(command)) | |
7abd3ef9 | 595 | column >>= 1; |
ace4dfee | 596 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 TG |
597 | ctrl &= ~NAND_CTRL_CHANGE; |
598 | } | |
599 | if (page_addr != -1) { | |
ace4dfee | 600 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
7abd3ef9 | 601 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 602 | chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); |
7abd3ef9 | 603 | /* One more address cycle for devices > 32MiB */ |
ace4dfee TG |
604 | if (chip->chipsize > (32 << 20)) |
605 | chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); | |
1da177e4 | 606 | } |
ace4dfee | 607 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
608 | |
609 | /* | |
8b6e50c9 BN |
610 | * Program and erase have their own busy handlers status and sequential |
611 | * in needs no delay | |
e0c7d767 | 612 | */ |
1da177e4 | 613 | switch (command) { |
61b03bd7 | 614 | |
1da177e4 LT |
615 | case NAND_CMD_PAGEPROG: |
616 | case NAND_CMD_ERASE1: | |
617 | case NAND_CMD_ERASE2: | |
618 | case NAND_CMD_SEQIN: | |
619 | case NAND_CMD_STATUS: | |
620 | return; | |
621 | ||
622 | case NAND_CMD_RESET: | |
ace4dfee | 623 | if (chip->dev_ready) |
1da177e4 | 624 | break; |
ace4dfee TG |
625 | udelay(chip->chip_delay); |
626 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, | |
7abd3ef9 | 627 | NAND_CTRL_CLE | NAND_CTRL_CHANGE); |
12efdde3 TG |
628 | chip->cmd_ctrl(mtd, |
629 | NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
630 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
631 | ; | |
1da177e4 LT |
632 | return; |
633 | ||
e0c7d767 | 634 | /* This applies to read commands */ |
1da177e4 | 635 | default: |
61b03bd7 | 636 | /* |
1da177e4 LT |
637 | * If we don't have access to the busy pin, we apply the given |
638 | * command delay | |
e0c7d767 | 639 | */ |
ace4dfee TG |
640 | if (!chip->dev_ready) { |
641 | udelay(chip->chip_delay); | |
1da177e4 | 642 | return; |
61b03bd7 | 643 | } |
1da177e4 | 644 | } |
8b6e50c9 BN |
645 | /* |
646 | * Apply this short delay always to ensure that we do wait tWB in | |
647 | * any case on any machine. | |
648 | */ | |
e0c7d767 | 649 | ndelay(100); |
3b88775c TG |
650 | |
651 | nand_wait_ready(mtd); | |
1da177e4 LT |
652 | } |
653 | ||
654 | /** | |
655 | * nand_command_lp - [DEFAULT] Send command to NAND large page device | |
8b6e50c9 BN |
656 | * @mtd: MTD device structure |
657 | * @command: the command to be sent | |
658 | * @column: the column address for this command, -1 if none | |
659 | * @page_addr: the page address for this command, -1 if none | |
1da177e4 | 660 | * |
7abd3ef9 | 661 | * Send command to NAND device. This is the version for the new large page |
7854d3f7 BN |
662 | * devices. We don't have the separate regions as we have in the small page |
663 | * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. | |
1da177e4 | 664 | */ |
7abd3ef9 TG |
665 | static void nand_command_lp(struct mtd_info *mtd, unsigned int command, |
666 | int column, int page_addr) | |
1da177e4 | 667 | { |
ace4dfee | 668 | register struct nand_chip *chip = mtd->priv; |
1da177e4 LT |
669 | |
670 | /* Emulate NAND_CMD_READOOB */ | |
671 | if (command == NAND_CMD_READOOB) { | |
28318776 | 672 | column += mtd->writesize; |
1da177e4 LT |
673 | command = NAND_CMD_READ0; |
674 | } | |
61b03bd7 | 675 | |
7abd3ef9 | 676 | /* Command latch cycle */ |
fb066ada | 677 | chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); |
1da177e4 LT |
678 | |
679 | if (column != -1 || page_addr != -1) { | |
7abd3ef9 | 680 | int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; |
1da177e4 LT |
681 | |
682 | /* Serially input address */ | |
683 | if (column != -1) { | |
684 | /* Adjust columns for 16 bit buswidth */ | |
3dad2344 BN |
685 | if (chip->options & NAND_BUSWIDTH_16 && |
686 | !nand_opcode_8bits(command)) | |
1da177e4 | 687 | column >>= 1; |
ace4dfee | 688 | chip->cmd_ctrl(mtd, column, ctrl); |
7abd3ef9 | 689 | ctrl &= ~NAND_CTRL_CHANGE; |
ace4dfee | 690 | chip->cmd_ctrl(mtd, column >> 8, ctrl); |
61b03bd7 | 691 | } |
1da177e4 | 692 | if (page_addr != -1) { |
ace4dfee TG |
693 | chip->cmd_ctrl(mtd, page_addr, ctrl); |
694 | chip->cmd_ctrl(mtd, page_addr >> 8, | |
7abd3ef9 | 695 | NAND_NCE | NAND_ALE); |
1da177e4 | 696 | /* One more address cycle for devices > 128MiB */ |
ace4dfee TG |
697 | if (chip->chipsize > (128 << 20)) |
698 | chip->cmd_ctrl(mtd, page_addr >> 16, | |
7abd3ef9 | 699 | NAND_NCE | NAND_ALE); |
1da177e4 | 700 | } |
1da177e4 | 701 | } |
ace4dfee | 702 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); |
61b03bd7 TG |
703 | |
704 | /* | |
8b6e50c9 BN |
705 | * Program and erase have their own busy handlers status, sequential |
706 | * in, and deplete1 need no delay. | |
30f464b7 | 707 | */ |
1da177e4 | 708 | switch (command) { |
61b03bd7 | 709 | |
1da177e4 LT |
710 | case NAND_CMD_CACHEDPROG: |
711 | case NAND_CMD_PAGEPROG: | |
712 | case NAND_CMD_ERASE1: | |
713 | case NAND_CMD_ERASE2: | |
714 | case NAND_CMD_SEQIN: | |
7bc3312b | 715 | case NAND_CMD_RNDIN: |
1da177e4 | 716 | case NAND_CMD_STATUS: |
30f464b7 | 717 | return; |
1da177e4 LT |
718 | |
719 | case NAND_CMD_RESET: | |
ace4dfee | 720 | if (chip->dev_ready) |
1da177e4 | 721 | break; |
ace4dfee | 722 | udelay(chip->chip_delay); |
12efdde3 TG |
723 | chip->cmd_ctrl(mtd, NAND_CMD_STATUS, |
724 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
725 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
726 | NAND_NCE | NAND_CTRL_CHANGE); | |
f8ac0414 FF |
727 | while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) |
728 | ; | |
1da177e4 LT |
729 | return; |
730 | ||
7bc3312b TG |
731 | case NAND_CMD_RNDOUT: |
732 | /* No ready / busy check necessary */ | |
733 | chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, | |
734 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
735 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
736 | NAND_NCE | NAND_CTRL_CHANGE); | |
737 | return; | |
738 | ||
1da177e4 | 739 | case NAND_CMD_READ0: |
12efdde3 TG |
740 | chip->cmd_ctrl(mtd, NAND_CMD_READSTART, |
741 | NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); | |
742 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, | |
743 | NAND_NCE | NAND_CTRL_CHANGE); | |
61b03bd7 | 744 | |
e0c7d767 | 745 | /* This applies to read commands */ |
1da177e4 | 746 | default: |
61b03bd7 | 747 | /* |
1da177e4 | 748 | * If we don't have access to the busy pin, we apply the given |
8b6e50c9 | 749 | * command delay. |
e0c7d767 | 750 | */ |
ace4dfee TG |
751 | if (!chip->dev_ready) { |
752 | udelay(chip->chip_delay); | |
1da177e4 | 753 | return; |
61b03bd7 | 754 | } |
1da177e4 | 755 | } |
3b88775c | 756 | |
8b6e50c9 BN |
757 | /* |
758 | * Apply this short delay always to ensure that we do wait tWB in | |
759 | * any case on any machine. | |
760 | */ | |
e0c7d767 | 761 | ndelay(100); |
3b88775c TG |
762 | |
763 | nand_wait_ready(mtd); | |
1da177e4 LT |
764 | } |
765 | ||
2af7c653 SK |
766 | /** |
767 | * panic_nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
768 | * @chip: the nand chip descriptor |
769 | * @mtd: MTD device structure | |
770 | * @new_state: the state which is requested | |
2af7c653 SK |
771 | * |
772 | * Used when in panic, no locks are taken. | |
773 | */ | |
774 | static void panic_nand_get_device(struct nand_chip *chip, | |
775 | struct mtd_info *mtd, int new_state) | |
776 | { | |
7854d3f7 | 777 | /* Hardware controller shared among independent devices */ |
2af7c653 SK |
778 | chip->controller->active = chip; |
779 | chip->state = new_state; | |
780 | } | |
781 | ||
1da177e4 LT |
782 | /** |
783 | * nand_get_device - [GENERIC] Get chip for selected access | |
8b6e50c9 BN |
784 | * @mtd: MTD device structure |
785 | * @new_state: the state which is requested | |
1da177e4 LT |
786 | * |
787 | * Get the device and lock it for exclusive access | |
788 | */ | |
2c0a2bed | 789 | static int |
6a8214aa | 790 | nand_get_device(struct mtd_info *mtd, int new_state) |
1da177e4 | 791 | { |
6a8214aa | 792 | struct nand_chip *chip = mtd->priv; |
ace4dfee TG |
793 | spinlock_t *lock = &chip->controller->lock; |
794 | wait_queue_head_t *wq = &chip->controller->wq; | |
e0c7d767 | 795 | DECLARE_WAITQUEUE(wait, current); |
7351d3a5 | 796 | retry: |
0dfc6246 TG |
797 | spin_lock(lock); |
798 | ||
b8b3ee9a | 799 | /* Hardware controller shared among independent devices */ |
ace4dfee TG |
800 | if (!chip->controller->active) |
801 | chip->controller->active = chip; | |
a36ed299 | 802 | |
ace4dfee TG |
803 | if (chip->controller->active == chip && chip->state == FL_READY) { |
804 | chip->state = new_state; | |
0dfc6246 | 805 | spin_unlock(lock); |
962034f4 VW |
806 | return 0; |
807 | } | |
808 | if (new_state == FL_PM_SUSPENDED) { | |
6b0d9a84 LY |
809 | if (chip->controller->active->state == FL_PM_SUSPENDED) { |
810 | chip->state = FL_PM_SUSPENDED; | |
811 | spin_unlock(lock); | |
812 | return 0; | |
6b0d9a84 | 813 | } |
0dfc6246 TG |
814 | } |
815 | set_current_state(TASK_UNINTERRUPTIBLE); | |
816 | add_wait_queue(wq, &wait); | |
817 | spin_unlock(lock); | |
818 | schedule(); | |
819 | remove_wait_queue(wq, &wait); | |
1da177e4 LT |
820 | goto retry; |
821 | } | |
822 | ||
2af7c653 | 823 | /** |
8b6e50c9 BN |
824 | * panic_nand_wait - [GENERIC] wait until the command is done |
825 | * @mtd: MTD device structure | |
826 | * @chip: NAND chip structure | |
827 | * @timeo: timeout | |
2af7c653 SK |
828 | * |
829 | * Wait for command done. This is a helper function for nand_wait used when | |
830 | * we are in interrupt context. May happen when in panic and trying to write | |
b595076a | 831 | * an oops through mtdoops. |
2af7c653 SK |
832 | */ |
833 | static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, | |
834 | unsigned long timeo) | |
835 | { | |
836 | int i; | |
837 | for (i = 0; i < timeo; i++) { | |
838 | if (chip->dev_ready) { | |
839 | if (chip->dev_ready(mtd)) | |
840 | break; | |
841 | } else { | |
842 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
843 | break; | |
844 | } | |
845 | mdelay(1); | |
f8ac0414 | 846 | } |
2af7c653 SK |
847 | } |
848 | ||
1da177e4 | 849 | /** |
8b6e50c9 BN |
850 | * nand_wait - [DEFAULT] wait until the command is done |
851 | * @mtd: MTD device structure | |
852 | * @chip: NAND chip structure | |
1da177e4 | 853 | * |
8b6e50c9 BN |
854 | * Wait for command done. This applies to erase and program only. Erase can |
855 | * take up to 400ms and program up to 20ms according to general NAND and | |
856 | * SmartMedia specs. | |
844d3b42 | 857 | */ |
7bc3312b | 858 | static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) |
1da177e4 LT |
859 | { |
860 | ||
7bc3312b | 861 | int status, state = chip->state; |
6d2559f8 | 862 | unsigned long timeo = (state == FL_ERASING ? 400 : 20); |
1da177e4 | 863 | |
8fe833c1 RP |
864 | led_trigger_event(nand_led_trigger, LED_FULL); |
865 | ||
8b6e50c9 BN |
866 | /* |
867 | * Apply this short delay always to ensure that we do wait tWB in any | |
868 | * case on any machine. | |
869 | */ | |
e0c7d767 | 870 | ndelay(100); |
1da177e4 | 871 | |
14c65786 | 872 | chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); |
1da177e4 | 873 | |
2af7c653 SK |
874 | if (in_interrupt() || oops_in_progress) |
875 | panic_nand_wait(mtd, chip, timeo); | |
876 | else { | |
6d2559f8 | 877 | timeo = jiffies + msecs_to_jiffies(timeo); |
2af7c653 SK |
878 | while (time_before(jiffies, timeo)) { |
879 | if (chip->dev_ready) { | |
880 | if (chip->dev_ready(mtd)) | |
881 | break; | |
882 | } else { | |
883 | if (chip->read_byte(mtd) & NAND_STATUS_READY) | |
884 | break; | |
885 | } | |
886 | cond_resched(); | |
1da177e4 | 887 | } |
1da177e4 | 888 | } |
8fe833c1 RP |
889 | led_trigger_event(nand_led_trigger, LED_OFF); |
890 | ||
ace4dfee | 891 | status = (int)chip->read_byte(mtd); |
f251b8df MC |
892 | /* This can happen if in case of timeout or buggy dev_ready */ |
893 | WARN_ON(!(status & NAND_STATUS_READY)); | |
1da177e4 LT |
894 | return status; |
895 | } | |
896 | ||
7d70f334 | 897 | /** |
b6d676db | 898 | * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
899 | * @mtd: mtd info |
900 | * @ofs: offset to start unlock from | |
901 | * @len: length to unlock | |
8b6e50c9 BN |
902 | * @invert: when = 0, unlock the range of blocks within the lower and |
903 | * upper boundary address | |
904 | * when = 1, unlock the range of blocks outside the boundaries | |
905 | * of the lower and upper boundary address | |
7d70f334 | 906 | * |
8b6e50c9 | 907 | * Returs unlock status. |
7d70f334 VS |
908 | */ |
909 | static int __nand_unlock(struct mtd_info *mtd, loff_t ofs, | |
910 | uint64_t len, int invert) | |
911 | { | |
912 | int ret = 0; | |
913 | int status, page; | |
914 | struct nand_chip *chip = mtd->priv; | |
915 | ||
916 | /* Submit address of first page to unlock */ | |
917 | page = ofs >> chip->page_shift; | |
918 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask); | |
919 | ||
920 | /* Submit address of last page to unlock */ | |
921 | page = (ofs + len) >> chip->page_shift; | |
922 | chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1, | |
923 | (page | invert) & chip->pagemask); | |
924 | ||
925 | /* Call wait ready function */ | |
926 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 927 | /* See if device thinks it succeeded */ |
74830966 | 928 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 929 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
930 | __func__, status); |
931 | ret = -EIO; | |
932 | } | |
933 | ||
934 | return ret; | |
935 | } | |
936 | ||
937 | /** | |
b6d676db | 938 | * nand_unlock - [REPLACEABLE] unlocks specified locked blocks |
b6d676db RD |
939 | * @mtd: mtd info |
940 | * @ofs: offset to start unlock from | |
941 | * @len: length to unlock | |
7d70f334 | 942 | * |
8b6e50c9 | 943 | * Returns unlock status. |
7d70f334 VS |
944 | */ |
945 | int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
946 | { | |
947 | int ret = 0; | |
948 | int chipnr; | |
949 | struct nand_chip *chip = mtd->priv; | |
950 | ||
289c0522 | 951 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
952 | __func__, (unsigned long long)ofs, len); |
953 | ||
954 | if (check_offs_len(mtd, ofs, len)) | |
955 | ret = -EINVAL; | |
956 | ||
957 | /* Align to last block address if size addresses end of the device */ | |
958 | if (ofs + len == mtd->size) | |
959 | len -= mtd->erasesize; | |
960 | ||
6a8214aa | 961 | nand_get_device(mtd, FL_UNLOCKING); |
7d70f334 VS |
962 | |
963 | /* Shift to get chip number */ | |
964 | chipnr = ofs >> chip->chip_shift; | |
965 | ||
966 | chip->select_chip(mtd, chipnr); | |
967 | ||
968 | /* Check, if it is write protected */ | |
969 | if (nand_check_wp(mtd)) { | |
289c0522 | 970 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
971 | __func__); |
972 | ret = -EIO; | |
973 | goto out; | |
974 | } | |
975 | ||
976 | ret = __nand_unlock(mtd, ofs, len, 0); | |
977 | ||
978 | out: | |
b0bb6903 | 979 | chip->select_chip(mtd, -1); |
7d70f334 VS |
980 | nand_release_device(mtd); |
981 | ||
982 | return ret; | |
983 | } | |
7351d3a5 | 984 | EXPORT_SYMBOL(nand_unlock); |
7d70f334 VS |
985 | |
986 | /** | |
b6d676db | 987 | * nand_lock - [REPLACEABLE] locks all blocks present in the device |
b6d676db RD |
988 | * @mtd: mtd info |
989 | * @ofs: offset to start unlock from | |
990 | * @len: length to unlock | |
7d70f334 | 991 | * |
8b6e50c9 BN |
992 | * This feature is not supported in many NAND parts. 'Micron' NAND parts do |
993 | * have this feature, but it allows only to lock all blocks, not for specified | |
994 | * range for block. Implementing 'lock' feature by making use of 'unlock', for | |
995 | * now. | |
7d70f334 | 996 | * |
8b6e50c9 | 997 | * Returns lock status. |
7d70f334 VS |
998 | */ |
999 | int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
1000 | { | |
1001 | int ret = 0; | |
1002 | int chipnr, status, page; | |
1003 | struct nand_chip *chip = mtd->priv; | |
1004 | ||
289c0522 | 1005 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
7d70f334 VS |
1006 | __func__, (unsigned long long)ofs, len); |
1007 | ||
1008 | if (check_offs_len(mtd, ofs, len)) | |
1009 | ret = -EINVAL; | |
1010 | ||
6a8214aa | 1011 | nand_get_device(mtd, FL_LOCKING); |
7d70f334 VS |
1012 | |
1013 | /* Shift to get chip number */ | |
1014 | chipnr = ofs >> chip->chip_shift; | |
1015 | ||
1016 | chip->select_chip(mtd, chipnr); | |
1017 | ||
1018 | /* Check, if it is write protected */ | |
1019 | if (nand_check_wp(mtd)) { | |
289c0522 | 1020 | pr_debug("%s: device is write protected!\n", |
7d70f334 VS |
1021 | __func__); |
1022 | status = MTD_ERASE_FAILED; | |
1023 | ret = -EIO; | |
1024 | goto out; | |
1025 | } | |
1026 | ||
1027 | /* Submit address of first page to lock */ | |
1028 | page = ofs >> chip->page_shift; | |
1029 | chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask); | |
1030 | ||
1031 | /* Call wait ready function */ | |
1032 | status = chip->waitfunc(mtd, chip); | |
7d70f334 | 1033 | /* See if device thinks it succeeded */ |
74830966 | 1034 | if (status & NAND_STATUS_FAIL) { |
289c0522 | 1035 | pr_debug("%s: error status = 0x%08x\n", |
7d70f334 VS |
1036 | __func__, status); |
1037 | ret = -EIO; | |
1038 | goto out; | |
1039 | } | |
1040 | ||
1041 | ret = __nand_unlock(mtd, ofs, len, 0x1); | |
1042 | ||
1043 | out: | |
b0bb6903 | 1044 | chip->select_chip(mtd, -1); |
7d70f334 VS |
1045 | nand_release_device(mtd); |
1046 | ||
1047 | return ret; | |
1048 | } | |
7351d3a5 | 1049 | EXPORT_SYMBOL(nand_lock); |
7d70f334 | 1050 | |
8593fbc6 | 1051 | /** |
7854d3f7 | 1052 | * nand_read_page_raw - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1053 | * @mtd: mtd info structure |
1054 | * @chip: nand chip info structure | |
1055 | * @buf: buffer to store read data | |
1fbb938d | 1056 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1057 | * @page: page number to read |
52ff49df | 1058 | * |
7854d3f7 | 1059 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 TG |
1060 | */ |
1061 | static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1062 | uint8_t *buf, int oob_required, int page) |
8593fbc6 TG |
1063 | { |
1064 | chip->read_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
1065 | if (oob_required) |
1066 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
8593fbc6 TG |
1067 | return 0; |
1068 | } | |
1069 | ||
52ff49df | 1070 | /** |
7854d3f7 | 1071 | * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc |
8b6e50c9 BN |
1072 | * @mtd: mtd info structure |
1073 | * @chip: nand chip info structure | |
1074 | * @buf: buffer to store read data | |
1fbb938d | 1075 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1076 | * @page: page number to read |
52ff49df DB |
1077 | * |
1078 | * We need a special oob layout and handling even when OOB isn't used. | |
1079 | */ | |
7351d3a5 | 1080 | static int nand_read_page_raw_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
1081 | struct nand_chip *chip, uint8_t *buf, |
1082 | int oob_required, int page) | |
52ff49df DB |
1083 | { |
1084 | int eccsize = chip->ecc.size; | |
1085 | int eccbytes = chip->ecc.bytes; | |
1086 | uint8_t *oob = chip->oob_poi; | |
1087 | int steps, size; | |
1088 | ||
1089 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
1090 | chip->read_buf(mtd, buf, eccsize); | |
1091 | buf += eccsize; | |
1092 | ||
1093 | if (chip->ecc.prepad) { | |
1094 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1095 | oob += chip->ecc.prepad; | |
1096 | } | |
1097 | ||
1098 | chip->read_buf(mtd, oob, eccbytes); | |
1099 | oob += eccbytes; | |
1100 | ||
1101 | if (chip->ecc.postpad) { | |
1102 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1103 | oob += chip->ecc.postpad; | |
1104 | } | |
1105 | } | |
1106 | ||
1107 | size = mtd->oobsize - (oob - chip->oob_poi); | |
1108 | if (size) | |
1109 | chip->read_buf(mtd, oob, size); | |
1110 | ||
1111 | return 0; | |
1112 | } | |
1113 | ||
1da177e4 | 1114 | /** |
7854d3f7 | 1115 | * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function |
8b6e50c9 BN |
1116 | * @mtd: mtd info structure |
1117 | * @chip: nand chip info structure | |
1118 | * @buf: buffer to store read data | |
1fbb938d | 1119 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1120 | * @page: page number to read |
068e3c0a | 1121 | */ |
f5bbdacc | 1122 | static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1123 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1124 | { |
f5bbdacc TG |
1125 | int i, eccsize = chip->ecc.size; |
1126 | int eccbytes = chip->ecc.bytes; | |
1127 | int eccsteps = chip->ecc.steps; | |
1128 | uint8_t *p = buf; | |
4bf63fcb DW |
1129 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1130 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1131 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1132 | unsigned int max_bitflips = 0; |
f5bbdacc | 1133 | |
1fbb938d | 1134 | chip->ecc.read_page_raw(mtd, chip, buf, 1, page); |
f5bbdacc TG |
1135 | |
1136 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) | |
1137 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1138 | ||
1139 | for (i = 0; i < chip->ecc.total; i++) | |
f75e5097 | 1140 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
f5bbdacc TG |
1141 | |
1142 | eccsteps = chip->ecc.steps; | |
1143 | p = buf; | |
1144 | ||
1145 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1146 | int stat; | |
1147 | ||
1148 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); | |
3f91e94f | 1149 | if (stat < 0) { |
f5bbdacc | 1150 | mtd->ecc_stats.failed++; |
3f91e94f | 1151 | } else { |
f5bbdacc | 1152 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1153 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1154 | } | |
f5bbdacc | 1155 | } |
3f91e94f | 1156 | return max_bitflips; |
22c60f5f | 1157 | } |
1da177e4 | 1158 | |
3d459559 | 1159 | /** |
837a6ba4 | 1160 | * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function |
8b6e50c9 BN |
1161 | * @mtd: mtd info structure |
1162 | * @chip: nand chip info structure | |
1163 | * @data_offs: offset of requested data within the page | |
1164 | * @readlen: data length | |
1165 | * @bufpoi: buffer to store read data | |
e004debd | 1166 | * @page: page number to read |
3d459559 | 1167 | */ |
7351d3a5 | 1168 | static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, |
e004debd HS |
1169 | uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi, |
1170 | int page) | |
3d459559 AK |
1171 | { |
1172 | int start_step, end_step, num_steps; | |
1173 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1174 | uint8_t *p; | |
1175 | int data_col_addr, i, gaps = 0; | |
1176 | int datafrag_len, eccfrag_len, aligned_len, aligned_pos; | |
1177 | int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; | |
4a4163ca | 1178 | int index; |
3f91e94f | 1179 | unsigned int max_bitflips = 0; |
3d459559 | 1180 | |
7854d3f7 | 1181 | /* Column address within the page aligned to ECC size (256bytes) */ |
3d459559 AK |
1182 | start_step = data_offs / chip->ecc.size; |
1183 | end_step = (data_offs + readlen - 1) / chip->ecc.size; | |
1184 | num_steps = end_step - start_step + 1; | |
4a4163ca | 1185 | index = start_step * chip->ecc.bytes; |
3d459559 | 1186 | |
8b6e50c9 | 1187 | /* Data size aligned to ECC ecc.size */ |
3d459559 AK |
1188 | datafrag_len = num_steps * chip->ecc.size; |
1189 | eccfrag_len = num_steps * chip->ecc.bytes; | |
1190 | ||
1191 | data_col_addr = start_step * chip->ecc.size; | |
1192 | /* If we read not a page aligned data */ | |
1193 | if (data_col_addr != 0) | |
1194 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); | |
1195 | ||
1196 | p = bufpoi + data_col_addr; | |
1197 | chip->read_buf(mtd, p, datafrag_len); | |
1198 | ||
8b6e50c9 | 1199 | /* Calculate ECC */ |
3d459559 AK |
1200 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) |
1201 | chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); | |
1202 | ||
8b6e50c9 BN |
1203 | /* |
1204 | * The performance is faster if we position offsets according to | |
7854d3f7 | 1205 | * ecc.pos. Let's make sure that there are no gaps in ECC positions. |
8b6e50c9 | 1206 | */ |
3d459559 | 1207 | for (i = 0; i < eccfrag_len - 1; i++) { |
47570bb1 | 1208 | if (eccpos[i + index] + 1 != eccpos[i + index + 1]) { |
3d459559 AK |
1209 | gaps = 1; |
1210 | break; | |
1211 | } | |
1212 | } | |
1213 | if (gaps) { | |
1214 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); | |
1215 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1216 | } else { | |
8b6e50c9 | 1217 | /* |
7854d3f7 | 1218 | * Send the command to read the particular ECC bytes take care |
8b6e50c9 BN |
1219 | * about buswidth alignment in read_buf. |
1220 | */ | |
7351d3a5 | 1221 | aligned_pos = eccpos[index] & ~(busw - 1); |
3d459559 | 1222 | aligned_len = eccfrag_len; |
7351d3a5 | 1223 | if (eccpos[index] & (busw - 1)) |
3d459559 | 1224 | aligned_len++; |
7351d3a5 | 1225 | if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1)) |
3d459559 AK |
1226 | aligned_len++; |
1227 | ||
7351d3a5 FF |
1228 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, |
1229 | mtd->writesize + aligned_pos, -1); | |
3d459559 AK |
1230 | chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len); |
1231 | } | |
1232 | ||
1233 | for (i = 0; i < eccfrag_len; i++) | |
7351d3a5 | 1234 | chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]]; |
3d459559 AK |
1235 | |
1236 | p = bufpoi + data_col_addr; | |
1237 | for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { | |
1238 | int stat; | |
1239 | ||
7351d3a5 FF |
1240 | stat = chip->ecc.correct(mtd, p, |
1241 | &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); | |
3f91e94f | 1242 | if (stat < 0) { |
3d459559 | 1243 | mtd->ecc_stats.failed++; |
3f91e94f | 1244 | } else { |
3d459559 | 1245 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1246 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1247 | } | |
3d459559 | 1248 | } |
3f91e94f | 1249 | return max_bitflips; |
3d459559 AK |
1250 | } |
1251 | ||
068e3c0a | 1252 | /** |
7854d3f7 | 1253 | * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function |
8b6e50c9 BN |
1254 | * @mtd: mtd info structure |
1255 | * @chip: nand chip info structure | |
1256 | * @buf: buffer to store read data | |
1fbb938d | 1257 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1258 | * @page: page number to read |
068e3c0a | 1259 | * |
7854d3f7 | 1260 | * Not for syndrome calculating ECC controllers which need a special oob layout. |
068e3c0a | 1261 | */ |
f5bbdacc | 1262 | static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1263 | uint8_t *buf, int oob_required, int page) |
1da177e4 | 1264 | { |
f5bbdacc TG |
1265 | int i, eccsize = chip->ecc.size; |
1266 | int eccbytes = chip->ecc.bytes; | |
1267 | int eccsteps = chip->ecc.steps; | |
1268 | uint8_t *p = buf; | |
4bf63fcb DW |
1269 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
1270 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8b099a39 | 1271 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
3f91e94f | 1272 | unsigned int max_bitflips = 0; |
f5bbdacc TG |
1273 | |
1274 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1275 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1276 | chip->read_buf(mtd, p, eccsize); | |
1277 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1da177e4 | 1278 | } |
f75e5097 | 1279 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
1da177e4 | 1280 | |
f5bbdacc | 1281 | for (i = 0; i < chip->ecc.total; i++) |
f75e5097 | 1282 | ecc_code[i] = chip->oob_poi[eccpos[i]]; |
1da177e4 | 1283 | |
f5bbdacc TG |
1284 | eccsteps = chip->ecc.steps; |
1285 | p = buf; | |
61b03bd7 | 1286 | |
f5bbdacc TG |
1287 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1288 | int stat; | |
1da177e4 | 1289 | |
f5bbdacc | 1290 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
3f91e94f | 1291 | if (stat < 0) { |
f5bbdacc | 1292 | mtd->ecc_stats.failed++; |
3f91e94f | 1293 | } else { |
f5bbdacc | 1294 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1295 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1296 | } | |
f5bbdacc | 1297 | } |
3f91e94f | 1298 | return max_bitflips; |
f5bbdacc | 1299 | } |
1da177e4 | 1300 | |
6e0cb135 | 1301 | /** |
7854d3f7 | 1302 | * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first |
8b6e50c9 BN |
1303 | * @mtd: mtd info structure |
1304 | * @chip: nand chip info structure | |
1305 | * @buf: buffer to store read data | |
1fbb938d | 1306 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1307 | * @page: page number to read |
6e0cb135 | 1308 | * |
8b6e50c9 BN |
1309 | * Hardware ECC for large page chips, require OOB to be read first. For this |
1310 | * ECC mode, the write_page method is re-used from ECC_HW. These methods | |
1311 | * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with | |
1312 | * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from | |
1313 | * the data area, by overwriting the NAND manufacturer bad block markings. | |
6e0cb135 SN |
1314 | */ |
1315 | static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, | |
1fbb938d | 1316 | struct nand_chip *chip, uint8_t *buf, int oob_required, int page) |
6e0cb135 SN |
1317 | { |
1318 | int i, eccsize = chip->ecc.size; | |
1319 | int eccbytes = chip->ecc.bytes; | |
1320 | int eccsteps = chip->ecc.steps; | |
1321 | uint8_t *p = buf; | |
1322 | uint8_t *ecc_code = chip->buffers->ecccode; | |
1323 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
1324 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
3f91e94f | 1325 | unsigned int max_bitflips = 0; |
6e0cb135 SN |
1326 | |
1327 | /* Read the OOB area first */ | |
1328 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); | |
1329 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1330 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
1331 | ||
1332 | for (i = 0; i < chip->ecc.total; i++) | |
1333 | ecc_code[i] = chip->oob_poi[eccpos[i]]; | |
1334 | ||
1335 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
1336 | int stat; | |
1337 | ||
1338 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1339 | chip->read_buf(mtd, p, eccsize); | |
1340 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
1341 | ||
1342 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); | |
3f91e94f | 1343 | if (stat < 0) { |
6e0cb135 | 1344 | mtd->ecc_stats.failed++; |
3f91e94f | 1345 | } else { |
6e0cb135 | 1346 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1347 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1348 | } | |
6e0cb135 | 1349 | } |
3f91e94f | 1350 | return max_bitflips; |
6e0cb135 SN |
1351 | } |
1352 | ||
f5bbdacc | 1353 | /** |
7854d3f7 | 1354 | * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read |
8b6e50c9 BN |
1355 | * @mtd: mtd info structure |
1356 | * @chip: nand chip info structure | |
1357 | * @buf: buffer to store read data | |
1fbb938d | 1358 | * @oob_required: caller requires OOB data read to chip->oob_poi |
8b6e50c9 | 1359 | * @page: page number to read |
f5bbdacc | 1360 | * |
8b6e50c9 BN |
1361 | * The hw generator calculates the error syndrome automatically. Therefore we |
1362 | * need a special oob layout and handling. | |
f5bbdacc TG |
1363 | */ |
1364 | static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 1365 | uint8_t *buf, int oob_required, int page) |
f5bbdacc TG |
1366 | { |
1367 | int i, eccsize = chip->ecc.size; | |
1368 | int eccbytes = chip->ecc.bytes; | |
1369 | int eccsteps = chip->ecc.steps; | |
1370 | uint8_t *p = buf; | |
f75e5097 | 1371 | uint8_t *oob = chip->oob_poi; |
3f91e94f | 1372 | unsigned int max_bitflips = 0; |
1da177e4 | 1373 | |
f5bbdacc TG |
1374 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1375 | int stat; | |
61b03bd7 | 1376 | |
f5bbdacc TG |
1377 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
1378 | chip->read_buf(mtd, p, eccsize); | |
1da177e4 | 1379 | |
f5bbdacc TG |
1380 | if (chip->ecc.prepad) { |
1381 | chip->read_buf(mtd, oob, chip->ecc.prepad); | |
1382 | oob += chip->ecc.prepad; | |
1383 | } | |
1da177e4 | 1384 | |
f5bbdacc TG |
1385 | chip->ecc.hwctl(mtd, NAND_ECC_READSYN); |
1386 | chip->read_buf(mtd, oob, eccbytes); | |
1387 | stat = chip->ecc.correct(mtd, p, oob, NULL); | |
61b03bd7 | 1388 | |
3f91e94f | 1389 | if (stat < 0) { |
f5bbdacc | 1390 | mtd->ecc_stats.failed++; |
3f91e94f | 1391 | } else { |
f5bbdacc | 1392 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
1393 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1394 | } | |
61b03bd7 | 1395 | |
f5bbdacc | 1396 | oob += eccbytes; |
1da177e4 | 1397 | |
f5bbdacc TG |
1398 | if (chip->ecc.postpad) { |
1399 | chip->read_buf(mtd, oob, chip->ecc.postpad); | |
1400 | oob += chip->ecc.postpad; | |
61b03bd7 | 1401 | } |
f5bbdacc | 1402 | } |
1da177e4 | 1403 | |
f5bbdacc | 1404 | /* Calculate remaining oob bytes */ |
7e4178f9 | 1405 | i = mtd->oobsize - (oob - chip->oob_poi); |
f5bbdacc TG |
1406 | if (i) |
1407 | chip->read_buf(mtd, oob, i); | |
61b03bd7 | 1408 | |
3f91e94f | 1409 | return max_bitflips; |
f5bbdacc | 1410 | } |
1da177e4 | 1411 | |
f5bbdacc | 1412 | /** |
7854d3f7 | 1413 | * nand_transfer_oob - [INTERN] Transfer oob to client buffer |
8b6e50c9 BN |
1414 | * @chip: nand chip structure |
1415 | * @oob: oob destination address | |
1416 | * @ops: oob ops structure | |
1417 | * @len: size of oob to transfer | |
8593fbc6 TG |
1418 | */ |
1419 | static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, | |
7014568b | 1420 | struct mtd_oob_ops *ops, size_t len) |
8593fbc6 | 1421 | { |
f8ac0414 | 1422 | switch (ops->mode) { |
8593fbc6 | 1423 | |
0612b9dd BN |
1424 | case MTD_OPS_PLACE_OOB: |
1425 | case MTD_OPS_RAW: | |
8593fbc6 TG |
1426 | memcpy(oob, chip->oob_poi + ops->ooboffs, len); |
1427 | return oob + len; | |
1428 | ||
0612b9dd | 1429 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 1430 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
1431 | uint32_t boffs = 0, roffs = ops->ooboffs; |
1432 | size_t bytes = 0; | |
8593fbc6 | 1433 | |
f8ac0414 | 1434 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 1435 | /* Read request not from offset 0? */ |
7bc3312b TG |
1436 | if (unlikely(roffs)) { |
1437 | if (roffs >= free->length) { | |
1438 | roffs -= free->length; | |
1439 | continue; | |
1440 | } | |
1441 | boffs = free->offset + roffs; | |
1442 | bytes = min_t(size_t, len, | |
1443 | (free->length - roffs)); | |
1444 | roffs = 0; | |
1445 | } else { | |
1446 | bytes = min_t(size_t, len, free->length); | |
1447 | boffs = free->offset; | |
1448 | } | |
1449 | memcpy(oob, chip->oob_poi + boffs, bytes); | |
8593fbc6 TG |
1450 | oob += bytes; |
1451 | } | |
1452 | return oob; | |
1453 | } | |
1454 | default: | |
1455 | BUG(); | |
1456 | } | |
1457 | return NULL; | |
1458 | } | |
1459 | ||
ba84fb59 BN |
1460 | /** |
1461 | * nand_setup_read_retry - [INTERN] Set the READ RETRY mode | |
1462 | * @mtd: MTD device structure | |
1463 | * @retry_mode: the retry mode to use | |
1464 | * | |
1465 | * Some vendors supply a special command to shift the Vt threshold, to be used | |
1466 | * when there are too many bitflips in a page (i.e., ECC error). After setting | |
1467 | * a new threshold, the host should retry reading the page. | |
1468 | */ | |
1469 | static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) | |
1470 | { | |
1471 | struct nand_chip *chip = mtd->priv; | |
1472 | ||
1473 | pr_debug("setting READ RETRY mode %d\n", retry_mode); | |
1474 | ||
1475 | if (retry_mode >= chip->read_retries) | |
1476 | return -EINVAL; | |
1477 | ||
1478 | if (!chip->setup_read_retry) | |
1479 | return -EOPNOTSUPP; | |
1480 | ||
1481 | return chip->setup_read_retry(mtd, retry_mode); | |
1482 | } | |
1483 | ||
8593fbc6 | 1484 | /** |
7854d3f7 | 1485 | * nand_do_read_ops - [INTERN] Read data with ECC |
8b6e50c9 BN |
1486 | * @mtd: MTD device structure |
1487 | * @from: offset to read from | |
1488 | * @ops: oob ops structure | |
f5bbdacc TG |
1489 | * |
1490 | * Internal function. Called with chip held. | |
1491 | */ | |
8593fbc6 TG |
1492 | static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, |
1493 | struct mtd_oob_ops *ops) | |
f5bbdacc | 1494 | { |
e47f3db4 | 1495 | int chipnr, page, realpage, col, bytes, aligned, oob_required; |
f5bbdacc | 1496 | struct nand_chip *chip = mtd->priv; |
f5bbdacc | 1497 | int ret = 0; |
8593fbc6 | 1498 | uint32_t readlen = ops->len; |
7014568b | 1499 | uint32_t oobreadlen = ops->ooblen; |
0612b9dd | 1500 | uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ? |
9aca334e ML |
1501 | mtd->oobavail : mtd->oobsize; |
1502 | ||
8593fbc6 | 1503 | uint8_t *bufpoi, *oob, *buf; |
66507c7b | 1504 | int use_bufpoi; |
edbc4540 | 1505 | unsigned int max_bitflips = 0; |
ba84fb59 | 1506 | int retry_mode = 0; |
b72f3dfb | 1507 | bool ecc_fail = false; |
1da177e4 | 1508 | |
f5bbdacc TG |
1509 | chipnr = (int)(from >> chip->chip_shift); |
1510 | chip->select_chip(mtd, chipnr); | |
61b03bd7 | 1511 | |
f5bbdacc TG |
1512 | realpage = (int)(from >> chip->page_shift); |
1513 | page = realpage & chip->pagemask; | |
1da177e4 | 1514 | |
f5bbdacc | 1515 | col = (int)(from & (mtd->writesize - 1)); |
61b03bd7 | 1516 | |
8593fbc6 TG |
1517 | buf = ops->datbuf; |
1518 | oob = ops->oobbuf; | |
e47f3db4 | 1519 | oob_required = oob ? 1 : 0; |
8593fbc6 | 1520 | |
f8ac0414 | 1521 | while (1) { |
b72f3dfb BN |
1522 | unsigned int ecc_failures = mtd->ecc_stats.failed; |
1523 | ||
f5bbdacc TG |
1524 | bytes = min(mtd->writesize - col, readlen); |
1525 | aligned = (bytes == mtd->writesize); | |
61b03bd7 | 1526 | |
66507c7b KD |
1527 | if (!aligned) |
1528 | use_bufpoi = 1; | |
1529 | else if (chip->options & NAND_USE_BOUNCE_BUFFER) | |
1530 | use_bufpoi = !virt_addr_valid(buf); | |
1531 | else | |
1532 | use_bufpoi = 0; | |
1533 | ||
8b6e50c9 | 1534 | /* Is the current page in the buffer? */ |
8593fbc6 | 1535 | if (realpage != chip->pagebuf || oob) { |
66507c7b KD |
1536 | bufpoi = use_bufpoi ? chip->buffers->databuf : buf; |
1537 | ||
1538 | if (use_bufpoi && aligned) | |
1539 | pr_debug("%s: using read bounce buffer for buf@%p\n", | |
1540 | __func__, buf); | |
61b03bd7 | 1541 | |
ba84fb59 | 1542 | read_retry: |
c00a0991 | 1543 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); |
1da177e4 | 1544 | |
edbc4540 MD |
1545 | /* |
1546 | * Now read the page into the buffer. Absent an error, | |
1547 | * the read methods return max bitflips per ecc step. | |
1548 | */ | |
0612b9dd | 1549 | if (unlikely(ops->mode == MTD_OPS_RAW)) |
1fbb938d | 1550 | ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, |
e47f3db4 BN |
1551 | oob_required, |
1552 | page); | |
a5ff4f10 JW |
1553 | else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && |
1554 | !oob) | |
7351d3a5 | 1555 | ret = chip->ecc.read_subpage(mtd, chip, |
e004debd HS |
1556 | col, bytes, bufpoi, |
1557 | page); | |
956e944c | 1558 | else |
46a8cf2d | 1559 | ret = chip->ecc.read_page(mtd, chip, bufpoi, |
e47f3db4 | 1560 | oob_required, page); |
6d77b9d0 | 1561 | if (ret < 0) { |
66507c7b | 1562 | if (use_bufpoi) |
6d77b9d0 BN |
1563 | /* Invalidate page cache */ |
1564 | chip->pagebuf = -1; | |
1da177e4 | 1565 | break; |
6d77b9d0 | 1566 | } |
f5bbdacc | 1567 | |
edbc4540 MD |
1568 | max_bitflips = max_t(unsigned int, max_bitflips, ret); |
1569 | ||
f5bbdacc | 1570 | /* Transfer not aligned data */ |
66507c7b | 1571 | if (use_bufpoi) { |
a5ff4f10 | 1572 | if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && |
b72f3dfb | 1573 | !(mtd->ecc_stats.failed - ecc_failures) && |
edbc4540 | 1574 | (ops->mode != MTD_OPS_RAW)) { |
3d459559 | 1575 | chip->pagebuf = realpage; |
edbc4540 MD |
1576 | chip->pagebuf_bitflips = ret; |
1577 | } else { | |
6d77b9d0 BN |
1578 | /* Invalidate page cache */ |
1579 | chip->pagebuf = -1; | |
edbc4540 | 1580 | } |
4bf63fcb | 1581 | memcpy(buf, chip->buffers->databuf + col, bytes); |
f5bbdacc TG |
1582 | } |
1583 | ||
8593fbc6 | 1584 | if (unlikely(oob)) { |
b64d39d8 ML |
1585 | int toread = min(oobreadlen, max_oobsize); |
1586 | ||
1587 | if (toread) { | |
1588 | oob = nand_transfer_oob(chip, | |
1589 | oob, ops, toread); | |
1590 | oobreadlen -= toread; | |
1591 | } | |
8593fbc6 | 1592 | } |
5bc7c33c BN |
1593 | |
1594 | if (chip->options & NAND_NEED_READRDY) { | |
1595 | /* Apply delay or wait for ready/busy pin */ | |
1596 | if (!chip->dev_ready) | |
1597 | udelay(chip->chip_delay); | |
1598 | else | |
1599 | nand_wait_ready(mtd); | |
1600 | } | |
b72f3dfb | 1601 | |
ba84fb59 | 1602 | if (mtd->ecc_stats.failed - ecc_failures) { |
28fa65e6 | 1603 | if (retry_mode + 1 < chip->read_retries) { |
ba84fb59 BN |
1604 | retry_mode++; |
1605 | ret = nand_setup_read_retry(mtd, | |
1606 | retry_mode); | |
1607 | if (ret < 0) | |
1608 | break; | |
1609 | ||
1610 | /* Reset failures; retry */ | |
1611 | mtd->ecc_stats.failed = ecc_failures; | |
1612 | goto read_retry; | |
1613 | } else { | |
1614 | /* No more retry modes; real failure */ | |
1615 | ecc_fail = true; | |
1616 | } | |
1617 | } | |
1618 | ||
1619 | buf += bytes; | |
8593fbc6 | 1620 | } else { |
4bf63fcb | 1621 | memcpy(buf, chip->buffers->databuf + col, bytes); |
8593fbc6 | 1622 | buf += bytes; |
edbc4540 MD |
1623 | max_bitflips = max_t(unsigned int, max_bitflips, |
1624 | chip->pagebuf_bitflips); | |
8593fbc6 | 1625 | } |
1da177e4 | 1626 | |
f5bbdacc | 1627 | readlen -= bytes; |
61b03bd7 | 1628 | |
ba84fb59 BN |
1629 | /* Reset to retry mode 0 */ |
1630 | if (retry_mode) { | |
1631 | ret = nand_setup_read_retry(mtd, 0); | |
1632 | if (ret < 0) | |
1633 | break; | |
1634 | retry_mode = 0; | |
1635 | } | |
1636 | ||
f5bbdacc | 1637 | if (!readlen) |
61b03bd7 | 1638 | break; |
1da177e4 | 1639 | |
8b6e50c9 | 1640 | /* For subsequent reads align to page boundary */ |
1da177e4 LT |
1641 | col = 0; |
1642 | /* Increment page address */ | |
1643 | realpage++; | |
1644 | ||
ace4dfee | 1645 | page = realpage & chip->pagemask; |
1da177e4 LT |
1646 | /* Check, if we cross a chip boundary */ |
1647 | if (!page) { | |
1648 | chipnr++; | |
ace4dfee TG |
1649 | chip->select_chip(mtd, -1); |
1650 | chip->select_chip(mtd, chipnr); | |
1da177e4 | 1651 | } |
1da177e4 | 1652 | } |
b0bb6903 | 1653 | chip->select_chip(mtd, -1); |
1da177e4 | 1654 | |
8593fbc6 | 1655 | ops->retlen = ops->len - (size_t) readlen; |
7014568b VW |
1656 | if (oob) |
1657 | ops->oobretlen = ops->ooblen - oobreadlen; | |
1da177e4 | 1658 | |
3f91e94f | 1659 | if (ret < 0) |
f5bbdacc TG |
1660 | return ret; |
1661 | ||
b72f3dfb | 1662 | if (ecc_fail) |
9a1fcdfd TG |
1663 | return -EBADMSG; |
1664 | ||
edbc4540 | 1665 | return max_bitflips; |
f5bbdacc TG |
1666 | } |
1667 | ||
1668 | /** | |
25985edc | 1669 | * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc |
8b6e50c9 BN |
1670 | * @mtd: MTD device structure |
1671 | * @from: offset to read from | |
1672 | * @len: number of bytes to read | |
1673 | * @retlen: pointer to variable to store the number of read bytes | |
1674 | * @buf: the databuffer to put data | |
f5bbdacc | 1675 | * |
8b6e50c9 | 1676 | * Get hold of the chip and call nand_do_read. |
f5bbdacc TG |
1677 | */ |
1678 | static int nand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1679 | size_t *retlen, uint8_t *buf) | |
1680 | { | |
4a89ff88 | 1681 | struct mtd_oob_ops ops; |
f5bbdacc TG |
1682 | int ret; |
1683 | ||
6a8214aa | 1684 | nand_get_device(mtd, FL_READING); |
4a89ff88 BN |
1685 | ops.len = len; |
1686 | ops.datbuf = buf; | |
1687 | ops.oobbuf = NULL; | |
11041ae6 | 1688 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 1689 | ret = nand_do_read_ops(mtd, from, &ops); |
4a89ff88 | 1690 | *retlen = ops.retlen; |
f5bbdacc | 1691 | nand_release_device(mtd); |
f5bbdacc | 1692 | return ret; |
1da177e4 LT |
1693 | } |
1694 | ||
7bc3312b | 1695 | /** |
7854d3f7 | 1696 | * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function |
8b6e50c9 BN |
1697 | * @mtd: mtd info structure |
1698 | * @chip: nand chip info structure | |
1699 | * @page: page number to read | |
7bc3312b TG |
1700 | */ |
1701 | static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1702 | int page) |
7bc3312b | 1703 | { |
5c2ffb11 | 1704 | chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); |
7bc3312b | 1705 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
5c2ffb11 | 1706 | return 0; |
7bc3312b TG |
1707 | } |
1708 | ||
1709 | /** | |
7854d3f7 | 1710 | * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC |
7bc3312b | 1711 | * with syndromes |
8b6e50c9 BN |
1712 | * @mtd: mtd info structure |
1713 | * @chip: nand chip info structure | |
1714 | * @page: page number to read | |
7bc3312b TG |
1715 | */ |
1716 | static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, | |
5c2ffb11 | 1717 | int page) |
7bc3312b TG |
1718 | { |
1719 | uint8_t *buf = chip->oob_poi; | |
1720 | int length = mtd->oobsize; | |
1721 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1722 | int eccsize = chip->ecc.size; | |
1723 | uint8_t *bufpoi = buf; | |
1724 | int i, toread, sndrnd = 0, pos; | |
1725 | ||
1726 | chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page); | |
1727 | for (i = 0; i < chip->ecc.steps; i++) { | |
1728 | if (sndrnd) { | |
1729 | pos = eccsize + i * (eccsize + chunk); | |
1730 | if (mtd->writesize > 512) | |
1731 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1); | |
1732 | else | |
1733 | chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page); | |
1734 | } else | |
1735 | sndrnd = 1; | |
1736 | toread = min_t(int, length, chunk); | |
1737 | chip->read_buf(mtd, bufpoi, toread); | |
1738 | bufpoi += toread; | |
1739 | length -= toread; | |
1740 | } | |
1741 | if (length > 0) | |
1742 | chip->read_buf(mtd, bufpoi, length); | |
1743 | ||
5c2ffb11 | 1744 | return 0; |
7bc3312b TG |
1745 | } |
1746 | ||
1747 | /** | |
7854d3f7 | 1748 | * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function |
8b6e50c9 BN |
1749 | * @mtd: mtd info structure |
1750 | * @chip: nand chip info structure | |
1751 | * @page: page number to write | |
7bc3312b TG |
1752 | */ |
1753 | static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, | |
1754 | int page) | |
1755 | { | |
1756 | int status = 0; | |
1757 | const uint8_t *buf = chip->oob_poi; | |
1758 | int length = mtd->oobsize; | |
1759 | ||
1760 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); | |
1761 | chip->write_buf(mtd, buf, length); | |
1762 | /* Send command to program the OOB data */ | |
1763 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1764 | ||
1765 | status = chip->waitfunc(mtd, chip); | |
1766 | ||
0d420f9d | 1767 | return status & NAND_STATUS_FAIL ? -EIO : 0; |
7bc3312b TG |
1768 | } |
1769 | ||
1770 | /** | |
7854d3f7 | 1771 | * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC |
8b6e50c9 BN |
1772 | * with syndrome - only for large page flash |
1773 | * @mtd: mtd info structure | |
1774 | * @chip: nand chip info structure | |
1775 | * @page: page number to write | |
7bc3312b TG |
1776 | */ |
1777 | static int nand_write_oob_syndrome(struct mtd_info *mtd, | |
1778 | struct nand_chip *chip, int page) | |
1779 | { | |
1780 | int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; | |
1781 | int eccsize = chip->ecc.size, length = mtd->oobsize; | |
1782 | int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps; | |
1783 | const uint8_t *bufpoi = chip->oob_poi; | |
1784 | ||
1785 | /* | |
1786 | * data-ecc-data-ecc ... ecc-oob | |
1787 | * or | |
1788 | * data-pad-ecc-pad-data-pad .... ecc-pad-oob | |
1789 | */ | |
1790 | if (!chip->ecc.prepad && !chip->ecc.postpad) { | |
1791 | pos = steps * (eccsize + chunk); | |
1792 | steps = 0; | |
1793 | } else | |
8b0036ee | 1794 | pos = eccsize; |
7bc3312b TG |
1795 | |
1796 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page); | |
1797 | for (i = 0; i < steps; i++) { | |
1798 | if (sndcmd) { | |
1799 | if (mtd->writesize <= 512) { | |
1800 | uint32_t fill = 0xFFFFFFFF; | |
1801 | ||
1802 | len = eccsize; | |
1803 | while (len > 0) { | |
1804 | int num = min_t(int, len, 4); | |
1805 | chip->write_buf(mtd, (uint8_t *)&fill, | |
1806 | num); | |
1807 | len -= num; | |
1808 | } | |
1809 | } else { | |
1810 | pos = eccsize + i * (eccsize + chunk); | |
1811 | chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1); | |
1812 | } | |
1813 | } else | |
1814 | sndcmd = 1; | |
1815 | len = min_t(int, length, chunk); | |
1816 | chip->write_buf(mtd, bufpoi, len); | |
1817 | bufpoi += len; | |
1818 | length -= len; | |
1819 | } | |
1820 | if (length > 0) | |
1821 | chip->write_buf(mtd, bufpoi, length); | |
1822 | ||
1823 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
1824 | status = chip->waitfunc(mtd, chip); | |
1825 | ||
1826 | return status & NAND_STATUS_FAIL ? -EIO : 0; | |
1827 | } | |
1828 | ||
1da177e4 | 1829 | /** |
7854d3f7 | 1830 | * nand_do_read_oob - [INTERN] NAND read out-of-band |
8b6e50c9 BN |
1831 | * @mtd: MTD device structure |
1832 | * @from: offset to read from | |
1833 | * @ops: oob operations description structure | |
1da177e4 | 1834 | * |
8b6e50c9 | 1835 | * NAND read out-of-band data from the spare area. |
1da177e4 | 1836 | */ |
8593fbc6 TG |
1837 | static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, |
1838 | struct mtd_oob_ops *ops) | |
1da177e4 | 1839 | { |
c00a0991 | 1840 | int page, realpage, chipnr; |
ace4dfee | 1841 | struct nand_chip *chip = mtd->priv; |
041e4575 | 1842 | struct mtd_ecc_stats stats; |
7014568b VW |
1843 | int readlen = ops->ooblen; |
1844 | int len; | |
7bc3312b | 1845 | uint8_t *buf = ops->oobbuf; |
1951f2f7 | 1846 | int ret = 0; |
61b03bd7 | 1847 | |
289c0522 | 1848 | pr_debug("%s: from = 0x%08Lx, len = %i\n", |
20d8e248 | 1849 | __func__, (unsigned long long)from, readlen); |
1da177e4 | 1850 | |
041e4575 BN |
1851 | stats = mtd->ecc_stats; |
1852 | ||
0612b9dd | 1853 | if (ops->mode == MTD_OPS_AUTO_OOB) |
7014568b | 1854 | len = chip->ecc.layout->oobavail; |
03736155 AH |
1855 | else |
1856 | len = mtd->oobsize; | |
1857 | ||
1858 | if (unlikely(ops->ooboffs >= len)) { | |
289c0522 BN |
1859 | pr_debug("%s: attempt to start read outside oob\n", |
1860 | __func__); | |
03736155 AH |
1861 | return -EINVAL; |
1862 | } | |
1863 | ||
1864 | /* Do not allow reads past end of device */ | |
1865 | if (unlikely(from >= mtd->size || | |
1866 | ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - | |
1867 | (from >> chip->page_shift)) * len)) { | |
289c0522 BN |
1868 | pr_debug("%s: attempt to read beyond end of device\n", |
1869 | __func__); | |
03736155 AH |
1870 | return -EINVAL; |
1871 | } | |
7014568b | 1872 | |
7314e9e7 | 1873 | chipnr = (int)(from >> chip->chip_shift); |
ace4dfee | 1874 | chip->select_chip(mtd, chipnr); |
1da177e4 | 1875 | |
7314e9e7 TG |
1876 | /* Shift to get page */ |
1877 | realpage = (int)(from >> chip->page_shift); | |
1878 | page = realpage & chip->pagemask; | |
1da177e4 | 1879 | |
f8ac0414 | 1880 | while (1) { |
0612b9dd | 1881 | if (ops->mode == MTD_OPS_RAW) |
1951f2f7 | 1882 | ret = chip->ecc.read_oob_raw(mtd, chip, page); |
c46f6483 | 1883 | else |
1951f2f7 SL |
1884 | ret = chip->ecc.read_oob(mtd, chip, page); |
1885 | ||
1886 | if (ret < 0) | |
1887 | break; | |
7014568b VW |
1888 | |
1889 | len = min(len, readlen); | |
1890 | buf = nand_transfer_oob(chip, buf, ops, len); | |
8593fbc6 | 1891 | |
5bc7c33c BN |
1892 | if (chip->options & NAND_NEED_READRDY) { |
1893 | /* Apply delay or wait for ready/busy pin */ | |
1894 | if (!chip->dev_ready) | |
1895 | udelay(chip->chip_delay); | |
1896 | else | |
1897 | nand_wait_ready(mtd); | |
1898 | } | |
1899 | ||
7014568b | 1900 | readlen -= len; |
0d420f9d SZ |
1901 | if (!readlen) |
1902 | break; | |
1903 | ||
7314e9e7 TG |
1904 | /* Increment page address */ |
1905 | realpage++; | |
1906 | ||
1907 | page = realpage & chip->pagemask; | |
1908 | /* Check, if we cross a chip boundary */ | |
1909 | if (!page) { | |
1910 | chipnr++; | |
1911 | chip->select_chip(mtd, -1); | |
1912 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
1913 | } |
1914 | } | |
b0bb6903 | 1915 | chip->select_chip(mtd, -1); |
1da177e4 | 1916 | |
1951f2f7 SL |
1917 | ops->oobretlen = ops->ooblen - readlen; |
1918 | ||
1919 | if (ret < 0) | |
1920 | return ret; | |
041e4575 BN |
1921 | |
1922 | if (mtd->ecc_stats.failed - stats.failed) | |
1923 | return -EBADMSG; | |
1924 | ||
1925 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; | |
1da177e4 LT |
1926 | } |
1927 | ||
1928 | /** | |
8593fbc6 | 1929 | * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band |
8b6e50c9 BN |
1930 | * @mtd: MTD device structure |
1931 | * @from: offset to read from | |
1932 | * @ops: oob operation description structure | |
1da177e4 | 1933 | * |
8b6e50c9 | 1934 | * NAND read data and/or out-of-band data. |
1da177e4 | 1935 | */ |
8593fbc6 TG |
1936 | static int nand_read_oob(struct mtd_info *mtd, loff_t from, |
1937 | struct mtd_oob_ops *ops) | |
1da177e4 | 1938 | { |
8593fbc6 TG |
1939 | int ret = -ENOTSUPP; |
1940 | ||
1941 | ops->retlen = 0; | |
1da177e4 LT |
1942 | |
1943 | /* Do not allow reads past end of device */ | |
7014568b | 1944 | if (ops->datbuf && (from + ops->len) > mtd->size) { |
289c0522 BN |
1945 | pr_debug("%s: attempt to read beyond end of device\n", |
1946 | __func__); | |
1da177e4 LT |
1947 | return -EINVAL; |
1948 | } | |
1949 | ||
6a8214aa | 1950 | nand_get_device(mtd, FL_READING); |
1da177e4 | 1951 | |
f8ac0414 | 1952 | switch (ops->mode) { |
0612b9dd BN |
1953 | case MTD_OPS_PLACE_OOB: |
1954 | case MTD_OPS_AUTO_OOB: | |
1955 | case MTD_OPS_RAW: | |
8593fbc6 | 1956 | break; |
1da177e4 | 1957 | |
8593fbc6 TG |
1958 | default: |
1959 | goto out; | |
1960 | } | |
1da177e4 | 1961 | |
8593fbc6 TG |
1962 | if (!ops->datbuf) |
1963 | ret = nand_do_read_oob(mtd, from, ops); | |
1964 | else | |
1965 | ret = nand_do_read_ops(mtd, from, ops); | |
61b03bd7 | 1966 | |
7351d3a5 | 1967 | out: |
8593fbc6 TG |
1968 | nand_release_device(mtd); |
1969 | return ret; | |
1970 | } | |
61b03bd7 | 1971 | |
1da177e4 | 1972 | |
8593fbc6 | 1973 | /** |
7854d3f7 | 1974 | * nand_write_page_raw - [INTERN] raw page write function |
8b6e50c9 BN |
1975 | * @mtd: mtd info structure |
1976 | * @chip: nand chip info structure | |
1977 | * @buf: data buffer | |
1fbb938d | 1978 | * @oob_required: must write chip->oob_poi to OOB |
52ff49df | 1979 | * |
7854d3f7 | 1980 | * Not for syndrome calculating ECC controllers, which use a special oob layout. |
8593fbc6 | 1981 | */ |
fdbad98d | 1982 | static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 1983 | const uint8_t *buf, int oob_required) |
8593fbc6 TG |
1984 | { |
1985 | chip->write_buf(mtd, buf, mtd->writesize); | |
279f08d4 BN |
1986 | if (oob_required) |
1987 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
1988 | |
1989 | return 0; | |
1da177e4 LT |
1990 | } |
1991 | ||
52ff49df | 1992 | /** |
7854d3f7 | 1993 | * nand_write_page_raw_syndrome - [INTERN] raw page write function |
8b6e50c9 BN |
1994 | * @mtd: mtd info structure |
1995 | * @chip: nand chip info structure | |
1996 | * @buf: data buffer | |
1fbb938d | 1997 | * @oob_required: must write chip->oob_poi to OOB |
52ff49df DB |
1998 | * |
1999 | * We need a special oob layout and handling even when ECC isn't checked. | |
2000 | */ | |
fdbad98d | 2001 | static int nand_write_page_raw_syndrome(struct mtd_info *mtd, |
7351d3a5 | 2002 | struct nand_chip *chip, |
1fbb938d | 2003 | const uint8_t *buf, int oob_required) |
52ff49df DB |
2004 | { |
2005 | int eccsize = chip->ecc.size; | |
2006 | int eccbytes = chip->ecc.bytes; | |
2007 | uint8_t *oob = chip->oob_poi; | |
2008 | int steps, size; | |
2009 | ||
2010 | for (steps = chip->ecc.steps; steps > 0; steps--) { | |
2011 | chip->write_buf(mtd, buf, eccsize); | |
2012 | buf += eccsize; | |
2013 | ||
2014 | if (chip->ecc.prepad) { | |
2015 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2016 | oob += chip->ecc.prepad; | |
2017 | } | |
2018 | ||
60c3bc1f | 2019 | chip->write_buf(mtd, oob, eccbytes); |
52ff49df DB |
2020 | oob += eccbytes; |
2021 | ||
2022 | if (chip->ecc.postpad) { | |
2023 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2024 | oob += chip->ecc.postpad; | |
2025 | } | |
2026 | } | |
2027 | ||
2028 | size = mtd->oobsize - (oob - chip->oob_poi); | |
2029 | if (size) | |
2030 | chip->write_buf(mtd, oob, size); | |
fdbad98d JW |
2031 | |
2032 | return 0; | |
52ff49df | 2033 | } |
9223a456 | 2034 | /** |
7854d3f7 | 2035 | * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function |
8b6e50c9 BN |
2036 | * @mtd: mtd info structure |
2037 | * @chip: nand chip info structure | |
2038 | * @buf: data buffer | |
1fbb938d | 2039 | * @oob_required: must write chip->oob_poi to OOB |
9223a456 | 2040 | */ |
fdbad98d | 2041 | static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 2042 | const uint8_t *buf, int oob_required) |
9223a456 | 2043 | { |
f75e5097 TG |
2044 | int i, eccsize = chip->ecc.size; |
2045 | int eccbytes = chip->ecc.bytes; | |
2046 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2047 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2048 | const uint8_t *p = buf; |
8b099a39 | 2049 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 2050 | |
7854d3f7 | 2051 | /* Software ECC calculation */ |
8593fbc6 TG |
2052 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) |
2053 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
9223a456 | 2054 | |
8593fbc6 TG |
2055 | for (i = 0; i < chip->ecc.total; i++) |
2056 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
9223a456 | 2057 | |
fdbad98d | 2058 | return chip->ecc.write_page_raw(mtd, chip, buf, 1); |
f75e5097 | 2059 | } |
9223a456 | 2060 | |
f75e5097 | 2061 | /** |
7854d3f7 | 2062 | * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function |
8b6e50c9 BN |
2063 | * @mtd: mtd info structure |
2064 | * @chip: nand chip info structure | |
2065 | * @buf: data buffer | |
1fbb938d | 2066 | * @oob_required: must write chip->oob_poi to OOB |
f75e5097 | 2067 | */ |
fdbad98d | 2068 | static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 2069 | const uint8_t *buf, int oob_required) |
f75e5097 TG |
2070 | { |
2071 | int i, eccsize = chip->ecc.size; | |
2072 | int eccbytes = chip->ecc.bytes; | |
2073 | int eccsteps = chip->ecc.steps; | |
4bf63fcb | 2074 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
f75e5097 | 2075 | const uint8_t *p = buf; |
8b099a39 | 2076 | uint32_t *eccpos = chip->ecc.layout->eccpos; |
9223a456 | 2077 | |
f75e5097 TG |
2078 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
2079 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
29da9cea | 2080 | chip->write_buf(mtd, p, eccsize); |
f75e5097 | 2081 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
9223a456 TG |
2082 | } |
2083 | ||
f75e5097 TG |
2084 | for (i = 0; i < chip->ecc.total; i++) |
2085 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
2086 | ||
2087 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
2088 | |
2089 | return 0; | |
9223a456 TG |
2090 | } |
2091 | ||
837a6ba4 GP |
2092 | |
2093 | /** | |
2094 | * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write | |
2095 | * @mtd: mtd info structure | |
2096 | * @chip: nand chip info structure | |
d6a95080 | 2097 | * @offset: column address of subpage within the page |
837a6ba4 | 2098 | * @data_len: data length |
d6a95080 | 2099 | * @buf: data buffer |
837a6ba4 GP |
2100 | * @oob_required: must write chip->oob_poi to OOB |
2101 | */ | |
2102 | static int nand_write_subpage_hwecc(struct mtd_info *mtd, | |
2103 | struct nand_chip *chip, uint32_t offset, | |
d6a95080 | 2104 | uint32_t data_len, const uint8_t *buf, |
837a6ba4 GP |
2105 | int oob_required) |
2106 | { | |
2107 | uint8_t *oob_buf = chip->oob_poi; | |
2108 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
2109 | int ecc_size = chip->ecc.size; | |
2110 | int ecc_bytes = chip->ecc.bytes; | |
2111 | int ecc_steps = chip->ecc.steps; | |
2112 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
2113 | uint32_t start_step = offset / ecc_size; | |
2114 | uint32_t end_step = (offset + data_len - 1) / ecc_size; | |
2115 | int oob_bytes = mtd->oobsize / ecc_steps; | |
2116 | int step, i; | |
2117 | ||
2118 | for (step = 0; step < ecc_steps; step++) { | |
2119 | /* configure controller for WRITE access */ | |
2120 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
2121 | ||
2122 | /* write data (untouched subpages already masked by 0xFF) */ | |
d6a95080 | 2123 | chip->write_buf(mtd, buf, ecc_size); |
837a6ba4 GP |
2124 | |
2125 | /* mask ECC of un-touched subpages by padding 0xFF */ | |
2126 | if ((step < start_step) || (step > end_step)) | |
2127 | memset(ecc_calc, 0xff, ecc_bytes); | |
2128 | else | |
d6a95080 | 2129 | chip->ecc.calculate(mtd, buf, ecc_calc); |
837a6ba4 GP |
2130 | |
2131 | /* mask OOB of un-touched subpages by padding 0xFF */ | |
2132 | /* if oob_required, preserve OOB metadata of written subpage */ | |
2133 | if (!oob_required || (step < start_step) || (step > end_step)) | |
2134 | memset(oob_buf, 0xff, oob_bytes); | |
2135 | ||
d6a95080 | 2136 | buf += ecc_size; |
837a6ba4 GP |
2137 | ecc_calc += ecc_bytes; |
2138 | oob_buf += oob_bytes; | |
2139 | } | |
2140 | ||
2141 | /* copy calculated ECC for whole page to chip->buffer->oob */ | |
2142 | /* this include masked-value(0xFF) for unwritten subpages */ | |
2143 | ecc_calc = chip->buffers->ecccalc; | |
2144 | for (i = 0; i < chip->ecc.total; i++) | |
2145 | chip->oob_poi[eccpos[i]] = ecc_calc[i]; | |
2146 | ||
2147 | /* write OOB buffer to NAND device */ | |
2148 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
2149 | ||
2150 | return 0; | |
2151 | } | |
2152 | ||
2153 | ||
61b03bd7 | 2154 | /** |
7854d3f7 | 2155 | * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write |
8b6e50c9 BN |
2156 | * @mtd: mtd info structure |
2157 | * @chip: nand chip info structure | |
2158 | * @buf: data buffer | |
1fbb938d | 2159 | * @oob_required: must write chip->oob_poi to OOB |
1da177e4 | 2160 | * |
8b6e50c9 BN |
2161 | * The hw generator calculates the error syndrome automatically. Therefore we |
2162 | * need a special oob layout and handling. | |
f75e5097 | 2163 | */ |
fdbad98d | 2164 | static int nand_write_page_syndrome(struct mtd_info *mtd, |
1fbb938d BN |
2165 | struct nand_chip *chip, |
2166 | const uint8_t *buf, int oob_required) | |
1da177e4 | 2167 | { |
f75e5097 TG |
2168 | int i, eccsize = chip->ecc.size; |
2169 | int eccbytes = chip->ecc.bytes; | |
2170 | int eccsteps = chip->ecc.steps; | |
2171 | const uint8_t *p = buf; | |
2172 | uint8_t *oob = chip->oob_poi; | |
1da177e4 | 2173 | |
f75e5097 | 2174 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { |
1da177e4 | 2175 | |
f75e5097 TG |
2176 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); |
2177 | chip->write_buf(mtd, p, eccsize); | |
61b03bd7 | 2178 | |
f75e5097 TG |
2179 | if (chip->ecc.prepad) { |
2180 | chip->write_buf(mtd, oob, chip->ecc.prepad); | |
2181 | oob += chip->ecc.prepad; | |
2182 | } | |
2183 | ||
2184 | chip->ecc.calculate(mtd, p, oob); | |
2185 | chip->write_buf(mtd, oob, eccbytes); | |
2186 | oob += eccbytes; | |
2187 | ||
2188 | if (chip->ecc.postpad) { | |
2189 | chip->write_buf(mtd, oob, chip->ecc.postpad); | |
2190 | oob += chip->ecc.postpad; | |
1da177e4 | 2191 | } |
1da177e4 | 2192 | } |
f75e5097 TG |
2193 | |
2194 | /* Calculate remaining oob bytes */ | |
7e4178f9 | 2195 | i = mtd->oobsize - (oob - chip->oob_poi); |
f75e5097 TG |
2196 | if (i) |
2197 | chip->write_buf(mtd, oob, i); | |
fdbad98d JW |
2198 | |
2199 | return 0; | |
f75e5097 TG |
2200 | } |
2201 | ||
2202 | /** | |
956e944c | 2203 | * nand_write_page - [REPLACEABLE] write one page |
8b6e50c9 BN |
2204 | * @mtd: MTD device structure |
2205 | * @chip: NAND chip descriptor | |
837a6ba4 GP |
2206 | * @offset: address offset within the page |
2207 | * @data_len: length of actual data to be written | |
8b6e50c9 | 2208 | * @buf: the data to write |
1fbb938d | 2209 | * @oob_required: must write chip->oob_poi to OOB |
8b6e50c9 BN |
2210 | * @page: page number to write |
2211 | * @cached: cached programming | |
2212 | * @raw: use _raw version of write_page | |
f75e5097 TG |
2213 | */ |
2214 | static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
837a6ba4 GP |
2215 | uint32_t offset, int data_len, const uint8_t *buf, |
2216 | int oob_required, int page, int cached, int raw) | |
f75e5097 | 2217 | { |
837a6ba4 GP |
2218 | int status, subpage; |
2219 | ||
2220 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && | |
2221 | chip->ecc.write_subpage) | |
2222 | subpage = offset || (data_len < mtd->writesize); | |
2223 | else | |
2224 | subpage = 0; | |
f75e5097 TG |
2225 | |
2226 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); | |
2227 | ||
956e944c | 2228 | if (unlikely(raw)) |
837a6ba4 GP |
2229 | status = chip->ecc.write_page_raw(mtd, chip, buf, |
2230 | oob_required); | |
2231 | else if (subpage) | |
2232 | status = chip->ecc.write_subpage(mtd, chip, offset, data_len, | |
2233 | buf, oob_required); | |
956e944c | 2234 | else |
fdbad98d JW |
2235 | status = chip->ecc.write_page(mtd, chip, buf, oob_required); |
2236 | ||
2237 | if (status < 0) | |
2238 | return status; | |
f75e5097 TG |
2239 | |
2240 | /* | |
7854d3f7 | 2241 | * Cached progamming disabled for now. Not sure if it's worth the |
8b6e50c9 | 2242 | * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s). |
f75e5097 TG |
2243 | */ |
2244 | cached = 0; | |
2245 | ||
3239a6cd | 2246 | if (!cached || !NAND_HAS_CACHEPROG(chip)) { |
f75e5097 TG |
2247 | |
2248 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
7bc3312b | 2249 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2250 | /* |
2251 | * See if operation failed and additional status checks are | |
8b6e50c9 | 2252 | * available. |
f75e5097 TG |
2253 | */ |
2254 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2255 | status = chip->errstat(mtd, chip, FL_WRITING, status, | |
2256 | page); | |
2257 | ||
2258 | if (status & NAND_STATUS_FAIL) | |
2259 | return -EIO; | |
2260 | } else { | |
2261 | chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1); | |
7bc3312b | 2262 | status = chip->waitfunc(mtd, chip); |
f75e5097 TG |
2263 | } |
2264 | ||
f75e5097 | 2265 | return 0; |
1da177e4 LT |
2266 | } |
2267 | ||
8593fbc6 | 2268 | /** |
7854d3f7 | 2269 | * nand_fill_oob - [INTERN] Transfer client buffer to oob |
f722013e | 2270 | * @mtd: MTD device structure |
8b6e50c9 BN |
2271 | * @oob: oob data buffer |
2272 | * @len: oob data write length | |
2273 | * @ops: oob ops structure | |
8593fbc6 | 2274 | */ |
f722013e TAA |
2275 | static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, |
2276 | struct mtd_oob_ops *ops) | |
8593fbc6 | 2277 | { |
f722013e TAA |
2278 | struct nand_chip *chip = mtd->priv; |
2279 | ||
2280 | /* | |
2281 | * Initialise to all 0xFF, to avoid the possibility of left over OOB | |
2282 | * data from a previous OOB read. | |
2283 | */ | |
2284 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
2285 | ||
f8ac0414 | 2286 | switch (ops->mode) { |
8593fbc6 | 2287 | |
0612b9dd BN |
2288 | case MTD_OPS_PLACE_OOB: |
2289 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2290 | memcpy(chip->oob_poi + ops->ooboffs, oob, len); |
2291 | return oob + len; | |
2292 | ||
0612b9dd | 2293 | case MTD_OPS_AUTO_OOB: { |
8593fbc6 | 2294 | struct nand_oobfree *free = chip->ecc.layout->oobfree; |
7bc3312b TG |
2295 | uint32_t boffs = 0, woffs = ops->ooboffs; |
2296 | size_t bytes = 0; | |
8593fbc6 | 2297 | |
f8ac0414 | 2298 | for (; free->length && len; free++, len -= bytes) { |
8b6e50c9 | 2299 | /* Write request not from offset 0? */ |
7bc3312b TG |
2300 | if (unlikely(woffs)) { |
2301 | if (woffs >= free->length) { | |
2302 | woffs -= free->length; | |
2303 | continue; | |
2304 | } | |
2305 | boffs = free->offset + woffs; | |
2306 | bytes = min_t(size_t, len, | |
2307 | (free->length - woffs)); | |
2308 | woffs = 0; | |
2309 | } else { | |
2310 | bytes = min_t(size_t, len, free->length); | |
2311 | boffs = free->offset; | |
2312 | } | |
8b0036ee | 2313 | memcpy(chip->oob_poi + boffs, oob, bytes); |
8593fbc6 TG |
2314 | oob += bytes; |
2315 | } | |
2316 | return oob; | |
2317 | } | |
2318 | default: | |
2319 | BUG(); | |
2320 | } | |
2321 | return NULL; | |
2322 | } | |
2323 | ||
f8ac0414 | 2324 | #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) |
1da177e4 LT |
2325 | |
2326 | /** | |
7854d3f7 | 2327 | * nand_do_write_ops - [INTERN] NAND write with ECC |
8b6e50c9 BN |
2328 | * @mtd: MTD device structure |
2329 | * @to: offset to write to | |
2330 | * @ops: oob operations description structure | |
1da177e4 | 2331 | * |
8b6e50c9 | 2332 | * NAND write with ECC. |
1da177e4 | 2333 | */ |
8593fbc6 TG |
2334 | static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, |
2335 | struct mtd_oob_ops *ops) | |
1da177e4 | 2336 | { |
29072b96 | 2337 | int chipnr, realpage, page, blockmask, column; |
ace4dfee | 2338 | struct nand_chip *chip = mtd->priv; |
8593fbc6 | 2339 | uint32_t writelen = ops->len; |
782ce79a ML |
2340 | |
2341 | uint32_t oobwritelen = ops->ooblen; | |
0612b9dd | 2342 | uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ? |
782ce79a ML |
2343 | mtd->oobavail : mtd->oobsize; |
2344 | ||
8593fbc6 TG |
2345 | uint8_t *oob = ops->oobbuf; |
2346 | uint8_t *buf = ops->datbuf; | |
837a6ba4 | 2347 | int ret; |
e47f3db4 | 2348 | int oob_required = oob ? 1 : 0; |
1da177e4 | 2349 | |
8593fbc6 | 2350 | ops->retlen = 0; |
29072b96 TG |
2351 | if (!writelen) |
2352 | return 0; | |
1da177e4 | 2353 | |
8b6e50c9 | 2354 | /* Reject writes, which are not page aligned */ |
8593fbc6 | 2355 | if (NOTALIGNED(to) || NOTALIGNED(ops->len)) { |
d0370219 BN |
2356 | pr_notice("%s: attempt to write non page aligned data\n", |
2357 | __func__); | |
1da177e4 LT |
2358 | return -EINVAL; |
2359 | } | |
2360 | ||
29072b96 | 2361 | column = to & (mtd->writesize - 1); |
1da177e4 | 2362 | |
6a930961 TG |
2363 | chipnr = (int)(to >> chip->chip_shift); |
2364 | chip->select_chip(mtd, chipnr); | |
2365 | ||
1da177e4 | 2366 | /* Check, if it is write protected */ |
b0bb6903 HS |
2367 | if (nand_check_wp(mtd)) { |
2368 | ret = -EIO; | |
2369 | goto err_out; | |
2370 | } | |
1da177e4 | 2371 | |
f75e5097 TG |
2372 | realpage = (int)(to >> chip->page_shift); |
2373 | page = realpage & chip->pagemask; | |
2374 | blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1; | |
2375 | ||
2376 | /* Invalidate the page cache, when we write to the cached page */ | |
2377 | if (to <= (chip->pagebuf << chip->page_shift) && | |
8593fbc6 | 2378 | (chip->pagebuf << chip->page_shift) < (to + ops->len)) |
ace4dfee | 2379 | chip->pagebuf = -1; |
61b03bd7 | 2380 | |
782ce79a | 2381 | /* Don't allow multipage oob writes with offset */ |
b0bb6903 HS |
2382 | if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { |
2383 | ret = -EINVAL; | |
2384 | goto err_out; | |
2385 | } | |
782ce79a | 2386 | |
f8ac0414 | 2387 | while (1) { |
29072b96 | 2388 | int bytes = mtd->writesize; |
f75e5097 | 2389 | int cached = writelen > bytes && page != blockmask; |
29072b96 | 2390 | uint8_t *wbuf = buf; |
66507c7b KD |
2391 | int use_bufpoi; |
2392 | int part_pagewr = (column || writelen < (mtd->writesize - 1)); | |
2393 | ||
2394 | if (part_pagewr) | |
2395 | use_bufpoi = 1; | |
2396 | else if (chip->options & NAND_USE_BOUNCE_BUFFER) | |
2397 | use_bufpoi = !virt_addr_valid(buf); | |
2398 | else | |
2399 | use_bufpoi = 0; | |
29072b96 | 2400 | |
66507c7b KD |
2401 | /* Partial page write?, or need to use bounce buffer */ |
2402 | if (use_bufpoi) { | |
2403 | pr_debug("%s: using write bounce buffer for buf@%p\n", | |
2404 | __func__, buf); | |
29072b96 | 2405 | cached = 0; |
66507c7b KD |
2406 | if (part_pagewr) |
2407 | bytes = min_t(int, bytes - column, writelen); | |
29072b96 TG |
2408 | chip->pagebuf = -1; |
2409 | memset(chip->buffers->databuf, 0xff, mtd->writesize); | |
2410 | memcpy(&chip->buffers->databuf[column], buf, bytes); | |
2411 | wbuf = chip->buffers->databuf; | |
2412 | } | |
1da177e4 | 2413 | |
782ce79a ML |
2414 | if (unlikely(oob)) { |
2415 | size_t len = min(oobwritelen, oobmaxlen); | |
f722013e | 2416 | oob = nand_fill_oob(mtd, oob, len, ops); |
782ce79a | 2417 | oobwritelen -= len; |
f722013e TAA |
2418 | } else { |
2419 | /* We still need to erase leftover OOB data */ | |
2420 | memset(chip->oob_poi, 0xff, mtd->oobsize); | |
782ce79a | 2421 | } |
837a6ba4 GP |
2422 | ret = chip->write_page(mtd, chip, column, bytes, wbuf, |
2423 | oob_required, page, cached, | |
2424 | (ops->mode == MTD_OPS_RAW)); | |
f75e5097 TG |
2425 | if (ret) |
2426 | break; | |
2427 | ||
2428 | writelen -= bytes; | |
2429 | if (!writelen) | |
2430 | break; | |
2431 | ||
29072b96 | 2432 | column = 0; |
f75e5097 TG |
2433 | buf += bytes; |
2434 | realpage++; | |
2435 | ||
2436 | page = realpage & chip->pagemask; | |
2437 | /* Check, if we cross a chip boundary */ | |
2438 | if (!page) { | |
2439 | chipnr++; | |
2440 | chip->select_chip(mtd, -1); | |
2441 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2442 | } |
2443 | } | |
8593fbc6 | 2444 | |
8593fbc6 | 2445 | ops->retlen = ops->len - writelen; |
7014568b VW |
2446 | if (unlikely(oob)) |
2447 | ops->oobretlen = ops->ooblen; | |
b0bb6903 HS |
2448 | |
2449 | err_out: | |
2450 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
2451 | return ret; |
2452 | } | |
2453 | ||
2af7c653 SK |
2454 | /** |
2455 | * panic_nand_write - [MTD Interface] NAND write with ECC | |
8b6e50c9 BN |
2456 | * @mtd: MTD device structure |
2457 | * @to: offset to write to | |
2458 | * @len: number of bytes to write | |
2459 | * @retlen: pointer to variable to store the number of written bytes | |
2460 | * @buf: the data to write | |
2af7c653 SK |
2461 | * |
2462 | * NAND write with ECC. Used when performing writes in interrupt context, this | |
2463 | * may for example be called by mtdoops when writing an oops while in panic. | |
2464 | */ | |
2465 | static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, | |
2466 | size_t *retlen, const uint8_t *buf) | |
2467 | { | |
2468 | struct nand_chip *chip = mtd->priv; | |
4a89ff88 | 2469 | struct mtd_oob_ops ops; |
2af7c653 SK |
2470 | int ret; |
2471 | ||
8b6e50c9 | 2472 | /* Wait for the device to get ready */ |
2af7c653 SK |
2473 | panic_nand_wait(mtd, chip, 400); |
2474 | ||
8b6e50c9 | 2475 | /* Grab the device */ |
2af7c653 SK |
2476 | panic_nand_get_device(chip, mtd, FL_WRITING); |
2477 | ||
4a89ff88 BN |
2478 | ops.len = len; |
2479 | ops.datbuf = (uint8_t *)buf; | |
2480 | ops.oobbuf = NULL; | |
11041ae6 | 2481 | ops.mode = MTD_OPS_PLACE_OOB; |
2af7c653 | 2482 | |
4a89ff88 | 2483 | ret = nand_do_write_ops(mtd, to, &ops); |
2af7c653 | 2484 | |
4a89ff88 | 2485 | *retlen = ops.retlen; |
2af7c653 SK |
2486 | return ret; |
2487 | } | |
2488 | ||
f75e5097 | 2489 | /** |
8593fbc6 | 2490 | * nand_write - [MTD Interface] NAND write with ECC |
8b6e50c9 BN |
2491 | * @mtd: MTD device structure |
2492 | * @to: offset to write to | |
2493 | * @len: number of bytes to write | |
2494 | * @retlen: pointer to variable to store the number of written bytes | |
2495 | * @buf: the data to write | |
f75e5097 | 2496 | * |
8b6e50c9 | 2497 | * NAND write with ECC. |
f75e5097 | 2498 | */ |
8593fbc6 TG |
2499 | static int nand_write(struct mtd_info *mtd, loff_t to, size_t len, |
2500 | size_t *retlen, const uint8_t *buf) | |
f75e5097 | 2501 | { |
4a89ff88 | 2502 | struct mtd_oob_ops ops; |
f75e5097 TG |
2503 | int ret; |
2504 | ||
6a8214aa | 2505 | nand_get_device(mtd, FL_WRITING); |
4a89ff88 BN |
2506 | ops.len = len; |
2507 | ops.datbuf = (uint8_t *)buf; | |
2508 | ops.oobbuf = NULL; | |
11041ae6 | 2509 | ops.mode = MTD_OPS_PLACE_OOB; |
4a89ff88 | 2510 | ret = nand_do_write_ops(mtd, to, &ops); |
4a89ff88 | 2511 | *retlen = ops.retlen; |
f75e5097 | 2512 | nand_release_device(mtd); |
8593fbc6 | 2513 | return ret; |
f75e5097 | 2514 | } |
7314e9e7 | 2515 | |
1da177e4 | 2516 | /** |
8593fbc6 | 2517 | * nand_do_write_oob - [MTD Interface] NAND write out-of-band |
8b6e50c9 BN |
2518 | * @mtd: MTD device structure |
2519 | * @to: offset to write to | |
2520 | * @ops: oob operation description structure | |
1da177e4 | 2521 | * |
8b6e50c9 | 2522 | * NAND write out-of-band. |
1da177e4 | 2523 | */ |
8593fbc6 TG |
2524 | static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, |
2525 | struct mtd_oob_ops *ops) | |
1da177e4 | 2526 | { |
03736155 | 2527 | int chipnr, page, status, len; |
ace4dfee | 2528 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2529 | |
289c0522 | 2530 | pr_debug("%s: to = 0x%08x, len = %i\n", |
20d8e248 | 2531 | __func__, (unsigned int)to, (int)ops->ooblen); |
1da177e4 | 2532 | |
0612b9dd | 2533 | if (ops->mode == MTD_OPS_AUTO_OOB) |
03736155 AH |
2534 | len = chip->ecc.layout->oobavail; |
2535 | else | |
2536 | len = mtd->oobsize; | |
2537 | ||
1da177e4 | 2538 | /* Do not allow write past end of page */ |
03736155 | 2539 | if ((ops->ooboffs + ops->ooblen) > len) { |
289c0522 BN |
2540 | pr_debug("%s: attempt to write past end of page\n", |
2541 | __func__); | |
1da177e4 LT |
2542 | return -EINVAL; |
2543 | } | |
2544 | ||
03736155 | 2545 | if (unlikely(ops->ooboffs >= len)) { |
289c0522 BN |
2546 | pr_debug("%s: attempt to start write outside oob\n", |
2547 | __func__); | |
03736155 AH |
2548 | return -EINVAL; |
2549 | } | |
2550 | ||
775adc3d | 2551 | /* Do not allow write past end of device */ |
03736155 AH |
2552 | if (unlikely(to >= mtd->size || |
2553 | ops->ooboffs + ops->ooblen > | |
2554 | ((mtd->size >> chip->page_shift) - | |
2555 | (to >> chip->page_shift)) * len)) { | |
289c0522 BN |
2556 | pr_debug("%s: attempt to write beyond end of device\n", |
2557 | __func__); | |
03736155 AH |
2558 | return -EINVAL; |
2559 | } | |
2560 | ||
7314e9e7 | 2561 | chipnr = (int)(to >> chip->chip_shift); |
ace4dfee | 2562 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2563 | |
7314e9e7 TG |
2564 | /* Shift to get page */ |
2565 | page = (int)(to >> chip->page_shift); | |
2566 | ||
2567 | /* | |
2568 | * Reset the chip. Some chips (like the Toshiba TC5832DC found in one | |
2569 | * of my DiskOnChip 2000 test units) will clear the whole data page too | |
2570 | * if we don't do this. I have no clue why, but I seem to have 'fixed' | |
2571 | * it in the doc2000 driver in August 1999. dwmw2. | |
2572 | */ | |
ace4dfee | 2573 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); |
1da177e4 LT |
2574 | |
2575 | /* Check, if it is write protected */ | |
b0bb6903 HS |
2576 | if (nand_check_wp(mtd)) { |
2577 | chip->select_chip(mtd, -1); | |
8593fbc6 | 2578 | return -EROFS; |
b0bb6903 | 2579 | } |
61b03bd7 | 2580 | |
1da177e4 | 2581 | /* Invalidate the page cache, if we write to the cached page */ |
ace4dfee TG |
2582 | if (page == chip->pagebuf) |
2583 | chip->pagebuf = -1; | |
1da177e4 | 2584 | |
f722013e | 2585 | nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops); |
9ce244b3 | 2586 | |
0612b9dd | 2587 | if (ops->mode == MTD_OPS_RAW) |
9ce244b3 BN |
2588 | status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask); |
2589 | else | |
2590 | status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); | |
1da177e4 | 2591 | |
b0bb6903 HS |
2592 | chip->select_chip(mtd, -1); |
2593 | ||
7bc3312b TG |
2594 | if (status) |
2595 | return status; | |
1da177e4 | 2596 | |
7014568b | 2597 | ops->oobretlen = ops->ooblen; |
1da177e4 | 2598 | |
7bc3312b | 2599 | return 0; |
8593fbc6 TG |
2600 | } |
2601 | ||
2602 | /** | |
2603 | * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
8b6e50c9 BN |
2604 | * @mtd: MTD device structure |
2605 | * @to: offset to write to | |
2606 | * @ops: oob operation description structure | |
8593fbc6 TG |
2607 | */ |
2608 | static int nand_write_oob(struct mtd_info *mtd, loff_t to, | |
2609 | struct mtd_oob_ops *ops) | |
2610 | { | |
8593fbc6 TG |
2611 | int ret = -ENOTSUPP; |
2612 | ||
2613 | ops->retlen = 0; | |
2614 | ||
2615 | /* Do not allow writes past end of device */ | |
7014568b | 2616 | if (ops->datbuf && (to + ops->len) > mtd->size) { |
289c0522 BN |
2617 | pr_debug("%s: attempt to write beyond end of device\n", |
2618 | __func__); | |
8593fbc6 TG |
2619 | return -EINVAL; |
2620 | } | |
2621 | ||
6a8214aa | 2622 | nand_get_device(mtd, FL_WRITING); |
8593fbc6 | 2623 | |
f8ac0414 | 2624 | switch (ops->mode) { |
0612b9dd BN |
2625 | case MTD_OPS_PLACE_OOB: |
2626 | case MTD_OPS_AUTO_OOB: | |
2627 | case MTD_OPS_RAW: | |
8593fbc6 TG |
2628 | break; |
2629 | ||
2630 | default: | |
2631 | goto out; | |
2632 | } | |
2633 | ||
2634 | if (!ops->datbuf) | |
2635 | ret = nand_do_write_oob(mtd, to, ops); | |
2636 | else | |
2637 | ret = nand_do_write_ops(mtd, to, ops); | |
2638 | ||
7351d3a5 | 2639 | out: |
1da177e4 | 2640 | nand_release_device(mtd); |
1da177e4 LT |
2641 | return ret; |
2642 | } | |
2643 | ||
1da177e4 | 2644 | /** |
49c50b97 | 2645 | * single_erase - [GENERIC] NAND standard block erase command function |
8b6e50c9 BN |
2646 | * @mtd: MTD device structure |
2647 | * @page: the page address of the block which will be erased | |
1da177e4 | 2648 | * |
49c50b97 | 2649 | * Standard erase command for NAND chips. Returns NAND status. |
1da177e4 | 2650 | */ |
49c50b97 | 2651 | static int single_erase(struct mtd_info *mtd, int page) |
1da177e4 | 2652 | { |
ace4dfee | 2653 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 2654 | /* Send commands to erase a block */ |
ace4dfee TG |
2655 | chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); |
2656 | chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); | |
49c50b97 BN |
2657 | |
2658 | return chip->waitfunc(mtd, chip); | |
1da177e4 LT |
2659 | } |
2660 | ||
1da177e4 LT |
2661 | /** |
2662 | * nand_erase - [MTD Interface] erase block(s) | |
8b6e50c9 BN |
2663 | * @mtd: MTD device structure |
2664 | * @instr: erase instruction | |
1da177e4 | 2665 | * |
8b6e50c9 | 2666 | * Erase one ore more blocks. |
1da177e4 | 2667 | */ |
e0c7d767 | 2668 | static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) |
1da177e4 | 2669 | { |
e0c7d767 | 2670 | return nand_erase_nand(mtd, instr, 0); |
1da177e4 | 2671 | } |
61b03bd7 | 2672 | |
1da177e4 | 2673 | /** |
7854d3f7 | 2674 | * nand_erase_nand - [INTERN] erase block(s) |
8b6e50c9 BN |
2675 | * @mtd: MTD device structure |
2676 | * @instr: erase instruction | |
2677 | * @allowbbt: allow erasing the bbt area | |
1da177e4 | 2678 | * |
8b6e50c9 | 2679 | * Erase one ore more blocks. |
1da177e4 | 2680 | */ |
ace4dfee TG |
2681 | int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, |
2682 | int allowbbt) | |
1da177e4 | 2683 | { |
69423d99 | 2684 | int page, status, pages_per_block, ret, chipnr; |
ace4dfee | 2685 | struct nand_chip *chip = mtd->priv; |
69423d99 | 2686 | loff_t len; |
1da177e4 | 2687 | |
289c0522 BN |
2688 | pr_debug("%s: start = 0x%012llx, len = %llu\n", |
2689 | __func__, (unsigned long long)instr->addr, | |
2690 | (unsigned long long)instr->len); | |
1da177e4 | 2691 | |
6fe5a6ac | 2692 | if (check_offs_len(mtd, instr->addr, instr->len)) |
1da177e4 | 2693 | return -EINVAL; |
1da177e4 | 2694 | |
1da177e4 | 2695 | /* Grab the lock and see if the device is available */ |
6a8214aa | 2696 | nand_get_device(mtd, FL_ERASING); |
1da177e4 LT |
2697 | |
2698 | /* Shift to get first page */ | |
ace4dfee TG |
2699 | page = (int)(instr->addr >> chip->page_shift); |
2700 | chipnr = (int)(instr->addr >> chip->chip_shift); | |
1da177e4 LT |
2701 | |
2702 | /* Calculate pages in each block */ | |
ace4dfee | 2703 | pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); |
1da177e4 LT |
2704 | |
2705 | /* Select the NAND device */ | |
ace4dfee | 2706 | chip->select_chip(mtd, chipnr); |
1da177e4 | 2707 | |
1da177e4 LT |
2708 | /* Check, if it is write protected */ |
2709 | if (nand_check_wp(mtd)) { | |
289c0522 BN |
2710 | pr_debug("%s: device is write protected!\n", |
2711 | __func__); | |
1da177e4 LT |
2712 | instr->state = MTD_ERASE_FAILED; |
2713 | goto erase_exit; | |
2714 | } | |
2715 | ||
2716 | /* Loop through the pages */ | |
2717 | len = instr->len; | |
2718 | ||
2719 | instr->state = MTD_ERASING; | |
2720 | ||
2721 | while (len) { | |
12183a20 | 2722 | /* Check if we have a bad block, we do not erase bad blocks! */ |
ace4dfee TG |
2723 | if (nand_block_checkbad(mtd, ((loff_t) page) << |
2724 | chip->page_shift, 0, allowbbt)) { | |
d0370219 BN |
2725 | pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", |
2726 | __func__, page); | |
1da177e4 LT |
2727 | instr->state = MTD_ERASE_FAILED; |
2728 | goto erase_exit; | |
2729 | } | |
61b03bd7 | 2730 | |
ace4dfee TG |
2731 | /* |
2732 | * Invalidate the page cache, if we erase the block which | |
8b6e50c9 | 2733 | * contains the current cached page. |
ace4dfee TG |
2734 | */ |
2735 | if (page <= chip->pagebuf && chip->pagebuf < | |
2736 | (page + pages_per_block)) | |
2737 | chip->pagebuf = -1; | |
1da177e4 | 2738 | |
49c50b97 | 2739 | status = chip->erase(mtd, page & chip->pagemask); |
1da177e4 | 2740 | |
ace4dfee TG |
2741 | /* |
2742 | * See if operation failed and additional status checks are | |
2743 | * available | |
2744 | */ | |
2745 | if ((status & NAND_STATUS_FAIL) && (chip->errstat)) | |
2746 | status = chip->errstat(mtd, chip, FL_ERASING, | |
2747 | status, page); | |
068e3c0a | 2748 | |
1da177e4 | 2749 | /* See if block erase succeeded */ |
a4ab4c5d | 2750 | if (status & NAND_STATUS_FAIL) { |
289c0522 BN |
2751 | pr_debug("%s: failed erase, page 0x%08x\n", |
2752 | __func__, page); | |
1da177e4 | 2753 | instr->state = MTD_ERASE_FAILED; |
69423d99 AH |
2754 | instr->fail_addr = |
2755 | ((loff_t)page << chip->page_shift); | |
1da177e4 LT |
2756 | goto erase_exit; |
2757 | } | |
30f464b7 | 2758 | |
1da177e4 | 2759 | /* Increment page address and decrement length */ |
daae74ca | 2760 | len -= (1ULL << chip->phys_erase_shift); |
1da177e4 LT |
2761 | page += pages_per_block; |
2762 | ||
2763 | /* Check, if we cross a chip boundary */ | |
ace4dfee | 2764 | if (len && !(page & chip->pagemask)) { |
1da177e4 | 2765 | chipnr++; |
ace4dfee TG |
2766 | chip->select_chip(mtd, -1); |
2767 | chip->select_chip(mtd, chipnr); | |
1da177e4 LT |
2768 | } |
2769 | } | |
2770 | instr->state = MTD_ERASE_DONE; | |
2771 | ||
7351d3a5 | 2772 | erase_exit: |
1da177e4 LT |
2773 | |
2774 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1da177e4 LT |
2775 | |
2776 | /* Deselect and wake up anyone waiting on the device */ | |
b0bb6903 | 2777 | chip->select_chip(mtd, -1); |
1da177e4 LT |
2778 | nand_release_device(mtd); |
2779 | ||
49defc01 DW |
2780 | /* Do call back function */ |
2781 | if (!ret) | |
2782 | mtd_erase_callback(instr); | |
2783 | ||
1da177e4 LT |
2784 | /* Return more or less happy */ |
2785 | return ret; | |
2786 | } | |
2787 | ||
2788 | /** | |
2789 | * nand_sync - [MTD Interface] sync | |
8b6e50c9 | 2790 | * @mtd: MTD device structure |
1da177e4 | 2791 | * |
8b6e50c9 | 2792 | * Sync is actually a wait for chip ready function. |
1da177e4 | 2793 | */ |
e0c7d767 | 2794 | static void nand_sync(struct mtd_info *mtd) |
1da177e4 | 2795 | { |
289c0522 | 2796 | pr_debug("%s: called\n", __func__); |
1da177e4 LT |
2797 | |
2798 | /* Grab the lock and see if the device is available */ | |
6a8214aa | 2799 | nand_get_device(mtd, FL_SYNCING); |
1da177e4 | 2800 | /* Release it and go back */ |
e0c7d767 | 2801 | nand_release_device(mtd); |
1da177e4 LT |
2802 | } |
2803 | ||
1da177e4 | 2804 | /** |
ace4dfee | 2805 | * nand_block_isbad - [MTD Interface] Check if block at offset is bad |
8b6e50c9 BN |
2806 | * @mtd: MTD device structure |
2807 | * @offs: offset relative to mtd start | |
1da177e4 | 2808 | */ |
ace4dfee | 2809 | static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) |
1da177e4 | 2810 | { |
ace4dfee | 2811 | return nand_block_checkbad(mtd, offs, 1, 0); |
1da177e4 LT |
2812 | } |
2813 | ||
2814 | /** | |
ace4dfee | 2815 | * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad |
8b6e50c9 BN |
2816 | * @mtd: MTD device structure |
2817 | * @ofs: offset relative to mtd start | |
1da177e4 | 2818 | */ |
e0c7d767 | 2819 | static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) |
1da177e4 | 2820 | { |
1da177e4 LT |
2821 | int ret; |
2822 | ||
f8ac0414 FF |
2823 | ret = nand_block_isbad(mtd, ofs); |
2824 | if (ret) { | |
8b6e50c9 | 2825 | /* If it was bad already, return success and do nothing */ |
1da177e4 LT |
2826 | if (ret > 0) |
2827 | return 0; | |
e0c7d767 DW |
2828 | return ret; |
2829 | } | |
1da177e4 | 2830 | |
5a0edb25 | 2831 | return nand_block_markbad_lowlevel(mtd, ofs); |
1da177e4 LT |
2832 | } |
2833 | ||
7db03ecc HS |
2834 | /** |
2835 | * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand | |
2836 | * @mtd: MTD device structure | |
2837 | * @chip: nand chip info structure | |
2838 | * @addr: feature address. | |
2839 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
2840 | */ | |
2841 | static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, | |
2842 | int addr, uint8_t *subfeature_param) | |
2843 | { | |
2844 | int status; | |
05f78359 | 2845 | int i; |
7db03ecc | 2846 | |
d914c932 DM |
2847 | if (!chip->onfi_version || |
2848 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
2849 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
2850 | return -EINVAL; |
2851 | ||
2852 | chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1); | |
05f78359 UKK |
2853 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
2854 | chip->write_byte(mtd, subfeature_param[i]); | |
2855 | ||
7db03ecc HS |
2856 | status = chip->waitfunc(mtd, chip); |
2857 | if (status & NAND_STATUS_FAIL) | |
2858 | return -EIO; | |
2859 | return 0; | |
2860 | } | |
2861 | ||
2862 | /** | |
2863 | * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand | |
2864 | * @mtd: MTD device structure | |
2865 | * @chip: nand chip info structure | |
2866 | * @addr: feature address. | |
2867 | * @subfeature_param: the subfeature parameters, a four bytes array. | |
2868 | */ | |
2869 | static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, | |
2870 | int addr, uint8_t *subfeature_param) | |
2871 | { | |
05f78359 UKK |
2872 | int i; |
2873 | ||
d914c932 DM |
2874 | if (!chip->onfi_version || |
2875 | !(le16_to_cpu(chip->onfi_params.opt_cmd) | |
2876 | & ONFI_OPT_CMD_SET_GET_FEATURES)) | |
7db03ecc HS |
2877 | return -EINVAL; |
2878 | ||
2879 | /* clear the sub feature parameters */ | |
2880 | memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN); | |
2881 | ||
2882 | chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1); | |
05f78359 UKK |
2883 | for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) |
2884 | *subfeature_param++ = chip->read_byte(mtd); | |
7db03ecc HS |
2885 | return 0; |
2886 | } | |
2887 | ||
962034f4 VW |
2888 | /** |
2889 | * nand_suspend - [MTD Interface] Suspend the NAND flash | |
8b6e50c9 | 2890 | * @mtd: MTD device structure |
962034f4 VW |
2891 | */ |
2892 | static int nand_suspend(struct mtd_info *mtd) | |
2893 | { | |
6a8214aa | 2894 | return nand_get_device(mtd, FL_PM_SUSPENDED); |
962034f4 VW |
2895 | } |
2896 | ||
2897 | /** | |
2898 | * nand_resume - [MTD Interface] Resume the NAND flash | |
8b6e50c9 | 2899 | * @mtd: MTD device structure |
962034f4 VW |
2900 | */ |
2901 | static void nand_resume(struct mtd_info *mtd) | |
2902 | { | |
ace4dfee | 2903 | struct nand_chip *chip = mtd->priv; |
962034f4 | 2904 | |
ace4dfee | 2905 | if (chip->state == FL_PM_SUSPENDED) |
962034f4 VW |
2906 | nand_release_device(mtd); |
2907 | else | |
d0370219 BN |
2908 | pr_err("%s called for a chip which is not in suspended state\n", |
2909 | __func__); | |
962034f4 VW |
2910 | } |
2911 | ||
8b6e50c9 | 2912 | /* Set default functions */ |
ace4dfee | 2913 | static void nand_set_defaults(struct nand_chip *chip, int busw) |
7aa65bfd | 2914 | { |
1da177e4 | 2915 | /* check for proper chip_delay setup, set 20us if not */ |
ace4dfee TG |
2916 | if (!chip->chip_delay) |
2917 | chip->chip_delay = 20; | |
1da177e4 LT |
2918 | |
2919 | /* check, if a user supplied command function given */ | |
ace4dfee TG |
2920 | if (chip->cmdfunc == NULL) |
2921 | chip->cmdfunc = nand_command; | |
1da177e4 LT |
2922 | |
2923 | /* check, if a user supplied wait function given */ | |
ace4dfee TG |
2924 | if (chip->waitfunc == NULL) |
2925 | chip->waitfunc = nand_wait; | |
2926 | ||
2927 | if (!chip->select_chip) | |
2928 | chip->select_chip = nand_select_chip; | |
68e80780 | 2929 | |
4204cccd HS |
2930 | /* set for ONFI nand */ |
2931 | if (!chip->onfi_set_features) | |
2932 | chip->onfi_set_features = nand_onfi_set_features; | |
2933 | if (!chip->onfi_get_features) | |
2934 | chip->onfi_get_features = nand_onfi_get_features; | |
2935 | ||
68e80780 BN |
2936 | /* If called twice, pointers that depend on busw may need to be reset */ |
2937 | if (!chip->read_byte || chip->read_byte == nand_read_byte) | |
ace4dfee TG |
2938 | chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; |
2939 | if (!chip->read_word) | |
2940 | chip->read_word = nand_read_word; | |
2941 | if (!chip->block_bad) | |
2942 | chip->block_bad = nand_block_bad; | |
2943 | if (!chip->block_markbad) | |
2944 | chip->block_markbad = nand_default_block_markbad; | |
68e80780 | 2945 | if (!chip->write_buf || chip->write_buf == nand_write_buf) |
ace4dfee | 2946 | chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; |
05f78359 UKK |
2947 | if (!chip->write_byte || chip->write_byte == nand_write_byte) |
2948 | chip->write_byte = busw ? nand_write_byte16 : nand_write_byte; | |
68e80780 | 2949 | if (!chip->read_buf || chip->read_buf == nand_read_buf) |
ace4dfee | 2950 | chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; |
ace4dfee TG |
2951 | if (!chip->scan_bbt) |
2952 | chip->scan_bbt = nand_default_bbt; | |
f75e5097 TG |
2953 | |
2954 | if (!chip->controller) { | |
2955 | chip->controller = &chip->hwcontrol; | |
2956 | spin_lock_init(&chip->controller->lock); | |
2957 | init_waitqueue_head(&chip->controller->wq); | |
2958 | } | |
2959 | ||
7aa65bfd TG |
2960 | } |
2961 | ||
8b6e50c9 | 2962 | /* Sanitize ONFI strings so we can safely print them */ |
d1e1f4e4 FF |
2963 | static void sanitize_string(uint8_t *s, size_t len) |
2964 | { | |
2965 | ssize_t i; | |
2966 | ||
8b6e50c9 | 2967 | /* Null terminate */ |
d1e1f4e4 FF |
2968 | s[len - 1] = 0; |
2969 | ||
8b6e50c9 | 2970 | /* Remove non printable chars */ |
d1e1f4e4 FF |
2971 | for (i = 0; i < len - 1; i++) { |
2972 | if (s[i] < ' ' || s[i] > 127) | |
2973 | s[i] = '?'; | |
2974 | } | |
2975 | ||
8b6e50c9 | 2976 | /* Remove trailing spaces */ |
d1e1f4e4 FF |
2977 | strim(s); |
2978 | } | |
2979 | ||
2980 | static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) | |
2981 | { | |
2982 | int i; | |
2983 | while (len--) { | |
2984 | crc ^= *p++ << 8; | |
2985 | for (i = 0; i < 8; i++) | |
2986 | crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); | |
2987 | } | |
2988 | ||
2989 | return crc; | |
2990 | } | |
2991 | ||
6dcbe0cd HS |
2992 | /* Parse the Extended Parameter Page. */ |
2993 | static int nand_flash_detect_ext_param_page(struct mtd_info *mtd, | |
2994 | struct nand_chip *chip, struct nand_onfi_params *p) | |
2995 | { | |
2996 | struct onfi_ext_param_page *ep; | |
2997 | struct onfi_ext_section *s; | |
2998 | struct onfi_ext_ecc_info *ecc; | |
2999 | uint8_t *cursor; | |
3000 | int ret = -EINVAL; | |
3001 | int len; | |
3002 | int i; | |
3003 | ||
3004 | len = le16_to_cpu(p->ext_param_page_length) * 16; | |
3005 | ep = kmalloc(len, GFP_KERNEL); | |
5cb13271 BN |
3006 | if (!ep) |
3007 | return -ENOMEM; | |
6dcbe0cd HS |
3008 | |
3009 | /* Send our own NAND_CMD_PARAM. */ | |
3010 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); | |
3011 | ||
3012 | /* Use the Change Read Column command to skip the ONFI param pages. */ | |
3013 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, | |
3014 | sizeof(*p) * p->num_of_param_pages , -1); | |
3015 | ||
3016 | /* Read out the Extended Parameter Page. */ | |
3017 | chip->read_buf(mtd, (uint8_t *)ep, len); | |
3018 | if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2) | |
3019 | != le16_to_cpu(ep->crc))) { | |
3020 | pr_debug("fail in the CRC.\n"); | |
3021 | goto ext_out; | |
3022 | } | |
3023 | ||
3024 | /* | |
3025 | * Check the signature. | |
3026 | * Do not strictly follow the ONFI spec, maybe changed in future. | |
3027 | */ | |
3028 | if (strncmp(ep->sig, "EPPS", 4)) { | |
3029 | pr_debug("The signature is invalid.\n"); | |
3030 | goto ext_out; | |
3031 | } | |
3032 | ||
3033 | /* find the ECC section. */ | |
3034 | cursor = (uint8_t *)(ep + 1); | |
3035 | for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) { | |
3036 | s = ep->sections + i; | |
3037 | if (s->type == ONFI_SECTION_TYPE_2) | |
3038 | break; | |
3039 | cursor += s->length * 16; | |
3040 | } | |
3041 | if (i == ONFI_EXT_SECTION_MAX) { | |
3042 | pr_debug("We can not find the ECC section.\n"); | |
3043 | goto ext_out; | |
3044 | } | |
3045 | ||
3046 | /* get the info we want. */ | |
3047 | ecc = (struct onfi_ext_ecc_info *)cursor; | |
3048 | ||
4ae7d228 BN |
3049 | if (!ecc->codeword_size) { |
3050 | pr_debug("Invalid codeword size\n"); | |
3051 | goto ext_out; | |
6dcbe0cd HS |
3052 | } |
3053 | ||
4ae7d228 BN |
3054 | chip->ecc_strength_ds = ecc->ecc_bits; |
3055 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
5cb13271 | 3056 | ret = 0; |
6dcbe0cd HS |
3057 | |
3058 | ext_out: | |
3059 | kfree(ep); | |
3060 | return ret; | |
3061 | } | |
3062 | ||
8429bb39 BN |
3063 | static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode) |
3064 | { | |
3065 | struct nand_chip *chip = mtd->priv; | |
3066 | uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode}; | |
3067 | ||
3068 | return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY, | |
3069 | feature); | |
3070 | } | |
3071 | ||
3072 | /* | |
3073 | * Configure chip properties from Micron vendor-specific ONFI table | |
3074 | */ | |
3075 | static void nand_onfi_detect_micron(struct nand_chip *chip, | |
3076 | struct nand_onfi_params *p) | |
3077 | { | |
3078 | struct nand_onfi_vendor_micron *micron = (void *)p->vendor; | |
3079 | ||
3080 | if (le16_to_cpu(p->vendor_revision) < 1) | |
3081 | return; | |
3082 | ||
3083 | chip->read_retries = micron->read_retry_options; | |
3084 | chip->setup_read_retry = nand_setup_read_retry_micron; | |
3085 | } | |
3086 | ||
6fb277ba | 3087 | /* |
8b6e50c9 | 3088 | * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. |
6fb277ba FF |
3089 | */ |
3090 | static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, | |
08c248fb | 3091 | int *busw) |
6fb277ba FF |
3092 | { |
3093 | struct nand_onfi_params *p = &chip->onfi_params; | |
bd9c6e99 | 3094 | int i, j; |
6fb277ba FF |
3095 | int val; |
3096 | ||
7854d3f7 | 3097 | /* Try ONFI for unknown chip or LP */ |
6fb277ba FF |
3098 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); |
3099 | if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || | |
3100 | chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') | |
3101 | return 0; | |
3102 | ||
6fb277ba FF |
3103 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); |
3104 | for (i = 0; i < 3; i++) { | |
bd9c6e99 BN |
3105 | for (j = 0; j < sizeof(*p); j++) |
3106 | ((uint8_t *)p)[j] = chip->read_byte(mtd); | |
6fb277ba FF |
3107 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == |
3108 | le16_to_cpu(p->crc)) { | |
6fb277ba FF |
3109 | break; |
3110 | } | |
3111 | } | |
3112 | ||
c7f23a70 BN |
3113 | if (i == 3) { |
3114 | pr_err("Could not find valid ONFI parameter page; aborting\n"); | |
6fb277ba | 3115 | return 0; |
c7f23a70 | 3116 | } |
6fb277ba | 3117 | |
8b6e50c9 | 3118 | /* Check version */ |
6fb277ba | 3119 | val = le16_to_cpu(p->revision); |
b7b1a29d BN |
3120 | if (val & (1 << 5)) |
3121 | chip->onfi_version = 23; | |
3122 | else if (val & (1 << 4)) | |
6fb277ba FF |
3123 | chip->onfi_version = 22; |
3124 | else if (val & (1 << 3)) | |
3125 | chip->onfi_version = 21; | |
3126 | else if (val & (1 << 2)) | |
3127 | chip->onfi_version = 20; | |
b7b1a29d | 3128 | else if (val & (1 << 1)) |
6fb277ba | 3129 | chip->onfi_version = 10; |
b7b1a29d BN |
3130 | |
3131 | if (!chip->onfi_version) { | |
20171642 | 3132 | pr_info("unsupported ONFI version: %d\n", val); |
b7b1a29d BN |
3133 | return 0; |
3134 | } | |
6fb277ba FF |
3135 | |
3136 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3137 | sanitize_string(p->model, sizeof(p->model)); | |
3138 | if (!mtd->name) | |
3139 | mtd->name = p->model; | |
4355b70c | 3140 | |
6fb277ba | 3141 | mtd->writesize = le32_to_cpu(p->byte_per_page); |
4355b70c BN |
3142 | |
3143 | /* | |
3144 | * pages_per_block and blocks_per_lun may not be a power-of-2 size | |
3145 | * (don't ask me who thought of this...). MTD assumes that these | |
3146 | * dimensions will be power-of-2, so just truncate the remaining area. | |
3147 | */ | |
3148 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3149 | mtd->erasesize *= mtd->writesize; | |
3150 | ||
6fb277ba | 3151 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); |
4355b70c BN |
3152 | |
3153 | /* See erasesize comment */ | |
3154 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
63795755 | 3155 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; |
13fbd179 | 3156 | chip->bits_per_cell = p->bits_per_cell; |
e2985fc1 HS |
3157 | |
3158 | if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) | |
08c248fb | 3159 | *busw = NAND_BUSWIDTH_16; |
e2985fc1 HS |
3160 | else |
3161 | *busw = 0; | |
6fb277ba | 3162 | |
10c86bab HS |
3163 | if (p->ecc_bits != 0xff) { |
3164 | chip->ecc_strength_ds = p->ecc_bits; | |
3165 | chip->ecc_step_ds = 512; | |
6dcbe0cd HS |
3166 | } else if (chip->onfi_version >= 21 && |
3167 | (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) { | |
3168 | ||
3169 | /* | |
3170 | * The nand_flash_detect_ext_param_page() uses the | |
3171 | * Change Read Column command which maybe not supported | |
3172 | * by the chip->cmdfunc. So try to update the chip->cmdfunc | |
3173 | * now. We do not replace user supplied command function. | |
3174 | */ | |
3175 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) | |
3176 | chip->cmdfunc = nand_command_lp; | |
3177 | ||
3178 | /* The Extended Parameter Page is supported since ONFI 2.1. */ | |
3179 | if (nand_flash_detect_ext_param_page(mtd, chip, p)) | |
c7f23a70 BN |
3180 | pr_warn("Failed to detect ONFI extended param page\n"); |
3181 | } else { | |
3182 | pr_warn("Could not retrieve ONFI ECC requirements\n"); | |
10c86bab HS |
3183 | } |
3184 | ||
8429bb39 BN |
3185 | if (p->jedec_id == NAND_MFR_MICRON) |
3186 | nand_onfi_detect_micron(chip, p); | |
3187 | ||
6fb277ba FF |
3188 | return 1; |
3189 | } | |
3190 | ||
91361818 HS |
3191 | /* |
3192 | * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise. | |
3193 | */ | |
3194 | static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip, | |
3195 | int *busw) | |
3196 | { | |
3197 | struct nand_jedec_params *p = &chip->jedec_params; | |
3198 | struct jedec_ecc_info *ecc; | |
3199 | int val; | |
3200 | int i, j; | |
3201 | ||
3202 | /* Try JEDEC for unknown chip or LP */ | |
3203 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1); | |
3204 | if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' || | |
3205 | chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' || | |
3206 | chip->read_byte(mtd) != 'C') | |
3207 | return 0; | |
3208 | ||
3209 | chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1); | |
3210 | for (i = 0; i < 3; i++) { | |
3211 | for (j = 0; j < sizeof(*p); j++) | |
3212 | ((uint8_t *)p)[j] = chip->read_byte(mtd); | |
3213 | ||
3214 | if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) == | |
3215 | le16_to_cpu(p->crc)) | |
3216 | break; | |
3217 | } | |
3218 | ||
3219 | if (i == 3) { | |
3220 | pr_err("Could not find valid JEDEC parameter page; aborting\n"); | |
3221 | return 0; | |
3222 | } | |
3223 | ||
3224 | /* Check version */ | |
3225 | val = le16_to_cpu(p->revision); | |
3226 | if (val & (1 << 2)) | |
3227 | chip->jedec_version = 10; | |
3228 | else if (val & (1 << 1)) | |
3229 | chip->jedec_version = 1; /* vendor specific version */ | |
3230 | ||
3231 | if (!chip->jedec_version) { | |
3232 | pr_info("unsupported JEDEC version: %d\n", val); | |
3233 | return 0; | |
3234 | } | |
3235 | ||
3236 | sanitize_string(p->manufacturer, sizeof(p->manufacturer)); | |
3237 | sanitize_string(p->model, sizeof(p->model)); | |
3238 | if (!mtd->name) | |
3239 | mtd->name = p->model; | |
3240 | ||
3241 | mtd->writesize = le32_to_cpu(p->byte_per_page); | |
3242 | ||
3243 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
3244 | mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); | |
3245 | mtd->erasesize *= mtd->writesize; | |
3246 | ||
3247 | mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); | |
3248 | ||
3249 | /* Please reference to the comment for nand_flash_detect_onfi. */ | |
3250 | chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); | |
3251 | chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; | |
3252 | chip->bits_per_cell = p->bits_per_cell; | |
3253 | ||
3254 | if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS) | |
3255 | *busw = NAND_BUSWIDTH_16; | |
3256 | else | |
3257 | *busw = 0; | |
3258 | ||
3259 | /* ECC info */ | |
3260 | ecc = &p->ecc_info[0]; | |
3261 | ||
3262 | if (ecc->codeword_size >= 9) { | |
3263 | chip->ecc_strength_ds = ecc->ecc_bits; | |
3264 | chip->ecc_step_ds = 1 << ecc->codeword_size; | |
3265 | } else { | |
3266 | pr_warn("Invalid codeword size\n"); | |
3267 | } | |
3268 | ||
3269 | return 1; | |
3270 | } | |
3271 | ||
e3b88bd6 BN |
3272 | /* |
3273 | * nand_id_has_period - Check if an ID string has a given wraparound period | |
3274 | * @id_data: the ID string | |
3275 | * @arrlen: the length of the @id_data array | |
3276 | * @period: the period of repitition | |
3277 | * | |
3278 | * Check if an ID string is repeated within a given sequence of bytes at | |
3279 | * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a | |
d4d4f1bf | 3280 | * period of 3). This is a helper function for nand_id_len(). Returns non-zero |
e3b88bd6 BN |
3281 | * if the repetition has a period of @period; otherwise, returns zero. |
3282 | */ | |
3283 | static int nand_id_has_period(u8 *id_data, int arrlen, int period) | |
3284 | { | |
3285 | int i, j; | |
3286 | for (i = 0; i < period; i++) | |
3287 | for (j = i + period; j < arrlen; j += period) | |
3288 | if (id_data[i] != id_data[j]) | |
3289 | return 0; | |
3290 | return 1; | |
3291 | } | |
3292 | ||
3293 | /* | |
3294 | * nand_id_len - Get the length of an ID string returned by CMD_READID | |
3295 | * @id_data: the ID string | |
3296 | * @arrlen: the length of the @id_data array | |
3297 | ||
3298 | * Returns the length of the ID string, according to known wraparound/trailing | |
3299 | * zero patterns. If no pattern exists, returns the length of the array. | |
3300 | */ | |
3301 | static int nand_id_len(u8 *id_data, int arrlen) | |
3302 | { | |
3303 | int last_nonzero, period; | |
3304 | ||
3305 | /* Find last non-zero byte */ | |
3306 | for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) | |
3307 | if (id_data[last_nonzero]) | |
3308 | break; | |
3309 | ||
3310 | /* All zeros */ | |
3311 | if (last_nonzero < 0) | |
3312 | return 0; | |
3313 | ||
3314 | /* Calculate wraparound period */ | |
3315 | for (period = 1; period < arrlen; period++) | |
3316 | if (nand_id_has_period(id_data, arrlen, period)) | |
3317 | break; | |
3318 | ||
3319 | /* There's a repeated pattern */ | |
3320 | if (period < arrlen) | |
3321 | return period; | |
3322 | ||
3323 | /* There are trailing zeros */ | |
3324 | if (last_nonzero < arrlen - 1) | |
3325 | return last_nonzero + 1; | |
3326 | ||
3327 | /* No pattern detected */ | |
3328 | return arrlen; | |
3329 | } | |
3330 | ||
7db906b7 HS |
3331 | /* Extract the bits of per cell from the 3rd byte of the extended ID */ |
3332 | static int nand_get_bits_per_cell(u8 cellinfo) | |
3333 | { | |
3334 | int bits; | |
3335 | ||
3336 | bits = cellinfo & NAND_CI_CELLTYPE_MSK; | |
3337 | bits >>= NAND_CI_CELLTYPE_SHIFT; | |
3338 | return bits + 1; | |
3339 | } | |
3340 | ||
fc09bbc0 BN |
3341 | /* |
3342 | * Many new NAND share similar device ID codes, which represent the size of the | |
3343 | * chip. The rest of the parameters must be decoded according to generic or | |
3344 | * manufacturer-specific "extended ID" decoding patterns. | |
3345 | */ | |
3346 | static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, | |
3347 | u8 id_data[8], int *busw) | |
3348 | { | |
e3b88bd6 | 3349 | int extid, id_len; |
fc09bbc0 | 3350 | /* The 3rd id byte holds MLC / multichip data */ |
7db906b7 | 3351 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
fc09bbc0 BN |
3352 | /* The 4th id byte is the important one */ |
3353 | extid = id_data[3]; | |
3354 | ||
e3b88bd6 BN |
3355 | id_len = nand_id_len(id_data, 8); |
3356 | ||
fc09bbc0 BN |
3357 | /* |
3358 | * Field definitions are in the following datasheets: | |
3359 | * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) | |
af451af4 | 3360 | * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) |
73ca392f | 3361 | * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22) |
fc09bbc0 | 3362 | * |
af451af4 BN |
3363 | * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung |
3364 | * ID to decide what to do. | |
fc09bbc0 | 3365 | */ |
af451af4 | 3366 | if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG && |
1d0ed69d | 3367 | !nand_is_slc(chip) && id_data[5] != 0x00) { |
fc09bbc0 BN |
3368 | /* Calc pagesize */ |
3369 | mtd->writesize = 2048 << (extid & 0x03); | |
3370 | extid >>= 2; | |
3371 | /* Calc oobsize */ | |
e2d3a35e | 3372 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { |
fc09bbc0 BN |
3373 | case 1: |
3374 | mtd->oobsize = 128; | |
3375 | break; | |
3376 | case 2: | |
3377 | mtd->oobsize = 218; | |
3378 | break; | |
3379 | case 3: | |
3380 | mtd->oobsize = 400; | |
3381 | break; | |
e2d3a35e | 3382 | case 4: |
fc09bbc0 BN |
3383 | mtd->oobsize = 436; |
3384 | break; | |
e2d3a35e BN |
3385 | case 5: |
3386 | mtd->oobsize = 512; | |
3387 | break; | |
3388 | case 6: | |
e2d3a35e BN |
3389 | mtd->oobsize = 640; |
3390 | break; | |
94d04e82 HS |
3391 | case 7: |
3392 | default: /* Other cases are "reserved" (unknown) */ | |
3393 | mtd->oobsize = 1024; | |
3394 | break; | |
fc09bbc0 BN |
3395 | } |
3396 | extid >>= 2; | |
3397 | /* Calc blocksize */ | |
3398 | mtd->erasesize = (128 * 1024) << | |
3399 | (((extid >> 1) & 0x04) | (extid & 0x03)); | |
3400 | *busw = 0; | |
73ca392f | 3401 | } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX && |
1d0ed69d | 3402 | !nand_is_slc(chip)) { |
73ca392f BN |
3403 | unsigned int tmp; |
3404 | ||
3405 | /* Calc pagesize */ | |
3406 | mtd->writesize = 2048 << (extid & 0x03); | |
3407 | extid >>= 2; | |
3408 | /* Calc oobsize */ | |
3409 | switch (((extid >> 2) & 0x04) | (extid & 0x03)) { | |
3410 | case 0: | |
3411 | mtd->oobsize = 128; | |
3412 | break; | |
3413 | case 1: | |
3414 | mtd->oobsize = 224; | |
3415 | break; | |
3416 | case 2: | |
3417 | mtd->oobsize = 448; | |
3418 | break; | |
3419 | case 3: | |
3420 | mtd->oobsize = 64; | |
3421 | break; | |
3422 | case 4: | |
3423 | mtd->oobsize = 32; | |
3424 | break; | |
3425 | case 5: | |
3426 | mtd->oobsize = 16; | |
3427 | break; | |
3428 | default: | |
3429 | mtd->oobsize = 640; | |
3430 | break; | |
3431 | } | |
3432 | extid >>= 2; | |
3433 | /* Calc blocksize */ | |
3434 | tmp = ((extid >> 1) & 0x04) | (extid & 0x03); | |
3435 | if (tmp < 0x03) | |
3436 | mtd->erasesize = (128 * 1024) << tmp; | |
3437 | else if (tmp == 0x03) | |
3438 | mtd->erasesize = 768 * 1024; | |
3439 | else | |
3440 | mtd->erasesize = (64 * 1024) << tmp; | |
3441 | *busw = 0; | |
fc09bbc0 BN |
3442 | } else { |
3443 | /* Calc pagesize */ | |
3444 | mtd->writesize = 1024 << (extid & 0x03); | |
3445 | extid >>= 2; | |
3446 | /* Calc oobsize */ | |
3447 | mtd->oobsize = (8 << (extid & 0x01)) * | |
3448 | (mtd->writesize >> 9); | |
3449 | extid >>= 2; | |
3450 | /* Calc blocksize. Blocksize is multiples of 64KiB */ | |
3451 | mtd->erasesize = (64 * 1024) << (extid & 0x03); | |
3452 | extid >>= 2; | |
3453 | /* Get buswidth information */ | |
3454 | *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; | |
60c67382 BN |
3455 | |
3456 | /* | |
3457 | * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per | |
3458 | * 512B page. For Toshiba SLC, we decode the 5th/6th byte as | |
3459 | * follows: | |
3460 | * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, | |
3461 | * 110b -> 24nm | |
3462 | * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC | |
3463 | */ | |
3464 | if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA && | |
1d0ed69d | 3465 | nand_is_slc(chip) && |
60c67382 BN |
3466 | (id_data[5] & 0x7) == 0x6 /* 24nm */ && |
3467 | !(id_data[4] & 0x80) /* !BENAND */) { | |
3468 | mtd->oobsize = 32 * mtd->writesize >> 9; | |
3469 | } | |
3470 | ||
fc09bbc0 BN |
3471 | } |
3472 | } | |
3473 | ||
f23a481c BN |
3474 | /* |
3475 | * Old devices have chip data hardcoded in the device ID table. nand_decode_id | |
3476 | * decodes a matching ID table entry and assigns the MTD size parameters for | |
3477 | * the chip. | |
3478 | */ | |
3479 | static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip, | |
3480 | struct nand_flash_dev *type, u8 id_data[8], | |
3481 | int *busw) | |
3482 | { | |
3483 | int maf_id = id_data[0]; | |
3484 | ||
3485 | mtd->erasesize = type->erasesize; | |
3486 | mtd->writesize = type->pagesize; | |
3487 | mtd->oobsize = mtd->writesize / 32; | |
3488 | *busw = type->options & NAND_BUSWIDTH_16; | |
3489 | ||
1c195e90 HS |
3490 | /* All legacy ID NAND are small-page, SLC */ |
3491 | chip->bits_per_cell = 1; | |
3492 | ||
f23a481c BN |
3493 | /* |
3494 | * Check for Spansion/AMD ID + repeating 5th, 6th byte since | |
3495 | * some Spansion chips have erasesize that conflicts with size | |
3496 | * listed in nand_ids table. | |
3497 | * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) | |
3498 | */ | |
3499 | if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00 | |
3500 | && id_data[6] == 0x00 && id_data[7] == 0x00 | |
3501 | && mtd->writesize == 512) { | |
3502 | mtd->erasesize = 128 * 1024; | |
3503 | mtd->erasesize <<= ((id_data[3] & 0x03) << 1); | |
3504 | } | |
3505 | } | |
3506 | ||
7e74c2d7 BN |
3507 | /* |
3508 | * Set the bad block marker/indicator (BBM/BBI) patterns according to some | |
3509 | * heuristic patterns using various detected parameters (e.g., manufacturer, | |
3510 | * page size, cell-type information). | |
3511 | */ | |
3512 | static void nand_decode_bbm_options(struct mtd_info *mtd, | |
3513 | struct nand_chip *chip, u8 id_data[8]) | |
3514 | { | |
3515 | int maf_id = id_data[0]; | |
3516 | ||
3517 | /* Set the bad block position */ | |
3518 | if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) | |
3519 | chip->badblockpos = NAND_LARGE_BADBLOCK_POS; | |
3520 | else | |
3521 | chip->badblockpos = NAND_SMALL_BADBLOCK_POS; | |
3522 | ||
3523 | /* | |
3524 | * Bad block marker is stored in the last page of each block on Samsung | |
3525 | * and Hynix MLC devices; stored in first two pages of each block on | |
3526 | * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba, | |
3527 | * AMD/Spansion, and Macronix. All others scan only the first page. | |
3528 | */ | |
1d0ed69d | 3529 | if (!nand_is_slc(chip) && |
7e74c2d7 BN |
3530 | (maf_id == NAND_MFR_SAMSUNG || |
3531 | maf_id == NAND_MFR_HYNIX)) | |
3532 | chip->bbt_options |= NAND_BBT_SCANLASTPAGE; | |
1d0ed69d | 3533 | else if ((nand_is_slc(chip) && |
7e74c2d7 BN |
3534 | (maf_id == NAND_MFR_SAMSUNG || |
3535 | maf_id == NAND_MFR_HYNIX || | |
3536 | maf_id == NAND_MFR_TOSHIBA || | |
3537 | maf_id == NAND_MFR_AMD || | |
3538 | maf_id == NAND_MFR_MACRONIX)) || | |
3539 | (mtd->writesize == 2048 && | |
3540 | maf_id == NAND_MFR_MICRON)) | |
3541 | chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; | |
3542 | } | |
3543 | ||
ec6e87e3 HS |
3544 | static inline bool is_full_id_nand(struct nand_flash_dev *type) |
3545 | { | |
3546 | return type->id_len; | |
3547 | } | |
3548 | ||
3549 | static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, | |
3550 | struct nand_flash_dev *type, u8 *id_data, int *busw) | |
3551 | { | |
3552 | if (!strncmp(type->id, id_data, type->id_len)) { | |
3553 | mtd->writesize = type->pagesize; | |
3554 | mtd->erasesize = type->erasesize; | |
3555 | mtd->oobsize = type->oobsize; | |
3556 | ||
7db906b7 | 3557 | chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]); |
ec6e87e3 HS |
3558 | chip->chipsize = (uint64_t)type->chipsize << 20; |
3559 | chip->options |= type->options; | |
57219342 HS |
3560 | chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); |
3561 | chip->ecc_step_ds = NAND_ECC_STEP(type); | |
ec6e87e3 HS |
3562 | |
3563 | *busw = type->options & NAND_BUSWIDTH_16; | |
3564 | ||
092b6a1d CZ |
3565 | if (!mtd->name) |
3566 | mtd->name = type->name; | |
3567 | ||
ec6e87e3 HS |
3568 | return true; |
3569 | } | |
3570 | return false; | |
3571 | } | |
3572 | ||
7aa65bfd | 3573 | /* |
8b6e50c9 | 3574 | * Get the flash and manufacturer id and lookup if the type is supported. |
7aa65bfd TG |
3575 | */ |
3576 | static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, | |
ace4dfee | 3577 | struct nand_chip *chip, |
7351d3a5 | 3578 | int *maf_id, int *dev_id, |
5e81e88a | 3579 | struct nand_flash_dev *type) |
7aa65bfd | 3580 | { |
bb77082f | 3581 | int busw; |
d1e1f4e4 | 3582 | int i, maf_idx; |
426c457a | 3583 | u8 id_data[8]; |
1da177e4 LT |
3584 | |
3585 | /* Select the device */ | |
ace4dfee | 3586 | chip->select_chip(mtd, 0); |
1da177e4 | 3587 | |
ef89a880 KB |
3588 | /* |
3589 | * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) | |
8b6e50c9 | 3590 | * after power-up. |
ef89a880 KB |
3591 | */ |
3592 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
3593 | ||
1da177e4 | 3594 | /* Send the command for reading device ID */ |
ace4dfee | 3595 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 LT |
3596 | |
3597 | /* Read manufacturer and device IDs */ | |
ace4dfee | 3598 | *maf_id = chip->read_byte(mtd); |
d1e1f4e4 | 3599 | *dev_id = chip->read_byte(mtd); |
1da177e4 | 3600 | |
8b6e50c9 BN |
3601 | /* |
3602 | * Try again to make sure, as some systems the bus-hold or other | |
ed8165c7 BD |
3603 | * interface concerns can cause random data which looks like a |
3604 | * possibly credible NAND flash to appear. If the two results do | |
3605 | * not match, ignore the device completely. | |
3606 | */ | |
3607 | ||
3608 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); | |
3609 | ||
4aef9b78 BN |
3610 | /* Read entire ID string */ |
3611 | for (i = 0; i < 8; i++) | |
426c457a | 3612 | id_data[i] = chip->read_byte(mtd); |
ed8165c7 | 3613 | |
d1e1f4e4 | 3614 | if (id_data[0] != *maf_id || id_data[1] != *dev_id) { |
20171642 | 3615 | pr_info("second ID read did not match %02x,%02x against %02x,%02x\n", |
d0370219 | 3616 | *maf_id, *dev_id, id_data[0], id_data[1]); |
ed8165c7 BD |
3617 | return ERR_PTR(-ENODEV); |
3618 | } | |
3619 | ||
7aa65bfd | 3620 | if (!type) |
5e81e88a DW |
3621 | type = nand_flash_ids; |
3622 | ||
ec6e87e3 HS |
3623 | for (; type->name != NULL; type++) { |
3624 | if (is_full_id_nand(type)) { | |
3625 | if (find_full_id_nand(mtd, chip, type, id_data, &busw)) | |
3626 | goto ident_done; | |
3627 | } else if (*dev_id == type->dev_id) { | |
3628 | break; | |
3629 | } | |
3630 | } | |
5e81e88a | 3631 | |
d1e1f4e4 FF |
3632 | chip->onfi_version = 0; |
3633 | if (!type->name || !type->pagesize) { | |
35fc5195 | 3634 | /* Check if the chip is ONFI compliant */ |
47450b35 | 3635 | if (nand_flash_detect_onfi(mtd, chip, &busw)) |
6fb277ba | 3636 | goto ident_done; |
91361818 HS |
3637 | |
3638 | /* Check if the chip is JEDEC compliant */ | |
3639 | if (nand_flash_detect_jedec(mtd, chip, &busw)) | |
3640 | goto ident_done; | |
d1e1f4e4 FF |
3641 | } |
3642 | ||
5e81e88a | 3643 | if (!type->name) |
7aa65bfd TG |
3644 | return ERR_PTR(-ENODEV); |
3645 | ||
ba0251fe TG |
3646 | if (!mtd->name) |
3647 | mtd->name = type->name; | |
3648 | ||
69423d99 | 3649 | chip->chipsize = (uint64_t)type->chipsize << 20; |
7aa65bfd | 3650 | |
12a40a57 | 3651 | if (!type->pagesize && chip->init_size) { |
8b6e50c9 | 3652 | /* Set the pagesize, oobsize, erasesize by the driver */ |
12a40a57 HS |
3653 | busw = chip->init_size(mtd, chip, id_data); |
3654 | } else if (!type->pagesize) { | |
fc09bbc0 BN |
3655 | /* Decode parameters from extended ID */ |
3656 | nand_decode_ext_id(mtd, chip, id_data, &busw); | |
7aa65bfd | 3657 | } else { |
f23a481c | 3658 | nand_decode_id(mtd, chip, type, id_data, &busw); |
7aa65bfd | 3659 | } |
bf7a01bf BN |
3660 | /* Get chip options */ |
3661 | chip->options |= type->options; | |
d1e1f4e4 | 3662 | |
8b6e50c9 BN |
3663 | /* |
3664 | * Check if chip is not a Samsung device. Do not clear the | |
3665 | * options for chips which do not have an extended id. | |
d1e1f4e4 FF |
3666 | */ |
3667 | if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize) | |
3668 | chip->options &= ~NAND_SAMSUNG_LP_OPTIONS; | |
3669 | ident_done: | |
3670 | ||
7aa65bfd | 3671 | /* Try to identify manufacturer */ |
9a909867 | 3672 | for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) { |
7aa65bfd TG |
3673 | if (nand_manuf_ids[maf_idx].id == *maf_id) |
3674 | break; | |
3675 | } | |
0ea4a755 | 3676 | |
64b37b2a MC |
3677 | if (chip->options & NAND_BUSWIDTH_AUTO) { |
3678 | WARN_ON(chip->options & NAND_BUSWIDTH_16); | |
3679 | chip->options |= busw; | |
3680 | nand_set_defaults(chip, busw); | |
3681 | } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { | |
3682 | /* | |
3683 | * Check, if buswidth is correct. Hardware drivers should set | |
3684 | * chip correct! | |
3685 | */ | |
20171642 EG |
3686 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
3687 | *maf_id, *dev_id); | |
3688 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name); | |
3689 | pr_warn("bus width %d instead %d bit\n", | |
d0370219 BN |
3690 | (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, |
3691 | busw ? 16 : 8); | |
7aa65bfd TG |
3692 | return ERR_PTR(-EINVAL); |
3693 | } | |
61b03bd7 | 3694 | |
7e74c2d7 BN |
3695 | nand_decode_bbm_options(mtd, chip, id_data); |
3696 | ||
7aa65bfd | 3697 | /* Calculate the address shift from the page size */ |
ace4dfee | 3698 | chip->page_shift = ffs(mtd->writesize) - 1; |
8b6e50c9 | 3699 | /* Convert chipsize to number of pages per chip -1 */ |
ace4dfee | 3700 | chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; |
61b03bd7 | 3701 | |
ace4dfee | 3702 | chip->bbt_erase_shift = chip->phys_erase_shift = |
7aa65bfd | 3703 | ffs(mtd->erasesize) - 1; |
69423d99 AH |
3704 | if (chip->chipsize & 0xffffffff) |
3705 | chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; | |
7351d3a5 FF |
3706 | else { |
3707 | chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); | |
3708 | chip->chip_shift += 32 - 1; | |
3709 | } | |
1da177e4 | 3710 | |
26d9be11 | 3711 | chip->badblockbits = 8; |
49c50b97 | 3712 | chip->erase = single_erase; |
7aa65bfd | 3713 | |
8b6e50c9 | 3714 | /* Do not replace user supplied command function! */ |
ace4dfee TG |
3715 | if (mtd->writesize > 512 && chip->cmdfunc == nand_command) |
3716 | chip->cmdfunc = nand_command_lp; | |
7aa65bfd | 3717 | |
20171642 EG |
3718 | pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", |
3719 | *maf_id, *dev_id); | |
ffdac6cd HS |
3720 | |
3721 | if (chip->onfi_version) | |
3722 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3723 | chip->onfi_params.model); | |
3724 | else if (chip->jedec_version) | |
3725 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3726 | chip->jedec_params.model); | |
3727 | else | |
3728 | pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, | |
3729 | type->name); | |
3730 | ||
20171642 | 3731 | pr_info("%dMiB, %s, page size: %d, OOB size: %d\n", |
3723e93c HS |
3732 | (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", |
3733 | mtd->writesize, mtd->oobsize); | |
7aa65bfd TG |
3734 | return type; |
3735 | } | |
3736 | ||
7aa65bfd | 3737 | /** |
3b85c321 | 3738 | * nand_scan_ident - [NAND Interface] Scan for the NAND device |
8b6e50c9 BN |
3739 | * @mtd: MTD device structure |
3740 | * @maxchips: number of chips to scan for | |
3741 | * @table: alternative NAND ID table | |
7aa65bfd | 3742 | * |
8b6e50c9 BN |
3743 | * This is the first phase of the normal nand_scan() function. It reads the |
3744 | * flash ID and sets up MTD fields accordingly. | |
7aa65bfd | 3745 | * |
3b85c321 | 3746 | * The mtd->owner field must be set to the module of the caller. |
7aa65bfd | 3747 | */ |
5e81e88a DW |
3748 | int nand_scan_ident(struct mtd_info *mtd, int maxchips, |
3749 | struct nand_flash_dev *table) | |
7aa65bfd | 3750 | { |
bb77082f | 3751 | int i, nand_maf_id, nand_dev_id; |
ace4dfee | 3752 | struct nand_chip *chip = mtd->priv; |
7aa65bfd TG |
3753 | struct nand_flash_dev *type; |
3754 | ||
7aa65bfd | 3755 | /* Set the default functions */ |
bb77082f | 3756 | nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16); |
7aa65bfd TG |
3757 | |
3758 | /* Read the flash type */ | |
bb77082f CZ |
3759 | type = nand_get_flash_type(mtd, chip, &nand_maf_id, |
3760 | &nand_dev_id, table); | |
7aa65bfd TG |
3761 | |
3762 | if (IS_ERR(type)) { | |
b1c6e6db | 3763 | if (!(chip->options & NAND_SCAN_SILENT_NODEV)) |
d0370219 | 3764 | pr_warn("No NAND device found\n"); |
ace4dfee | 3765 | chip->select_chip(mtd, -1); |
7aa65bfd | 3766 | return PTR_ERR(type); |
1da177e4 LT |
3767 | } |
3768 | ||
07300164 HS |
3769 | chip->select_chip(mtd, -1); |
3770 | ||
7aa65bfd | 3771 | /* Check for a chip array */ |
e0c7d767 | 3772 | for (i = 1; i < maxchips; i++) { |
ace4dfee | 3773 | chip->select_chip(mtd, i); |
ef89a880 KB |
3774 | /* See comment in nand_get_flash_type for reset */ |
3775 | chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); | |
1da177e4 | 3776 | /* Send the command for reading device ID */ |
ace4dfee | 3777 | chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); |
1da177e4 | 3778 | /* Read manufacturer and device IDs */ |
ace4dfee | 3779 | if (nand_maf_id != chip->read_byte(mtd) || |
07300164 HS |
3780 | nand_dev_id != chip->read_byte(mtd)) { |
3781 | chip->select_chip(mtd, -1); | |
1da177e4 | 3782 | break; |
07300164 HS |
3783 | } |
3784 | chip->select_chip(mtd, -1); | |
1da177e4 LT |
3785 | } |
3786 | if (i > 1) | |
20171642 | 3787 | pr_info("%d chips detected\n", i); |
61b03bd7 | 3788 | |
1da177e4 | 3789 | /* Store the number of chips and calc total size for mtd */ |
ace4dfee TG |
3790 | chip->numchips = i; |
3791 | mtd->size = i * chip->chipsize; | |
7aa65bfd | 3792 | |
3b85c321 DW |
3793 | return 0; |
3794 | } | |
7351d3a5 | 3795 | EXPORT_SYMBOL(nand_scan_ident); |
3b85c321 DW |
3796 | |
3797 | ||
3798 | /** | |
3799 | * nand_scan_tail - [NAND Interface] Scan for the NAND device | |
8b6e50c9 | 3800 | * @mtd: MTD device structure |
3b85c321 | 3801 | * |
8b6e50c9 BN |
3802 | * This is the second phase of the normal nand_scan() function. It fills out |
3803 | * all the uninitialized function pointers with the defaults and scans for a | |
3804 | * bad block table if appropriate. | |
3b85c321 DW |
3805 | */ |
3806 | int nand_scan_tail(struct mtd_info *mtd) | |
3807 | { | |
3808 | int i; | |
3809 | struct nand_chip *chip = mtd->priv; | |
97de79e0 | 3810 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
f02ea4e6 | 3811 | struct nand_buffers *nbuf; |
3b85c321 | 3812 | |
e2414f4c BN |
3813 | /* New bad blocks should be marked in OOB, flash-based BBT, or both */ |
3814 | BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && | |
3815 | !(chip->bbt_options & NAND_BBT_USE_FLASH)); | |
3816 | ||
f02ea4e6 HS |
3817 | if (!(chip->options & NAND_OWN_BUFFERS)) { |
3818 | nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize | |
3819 | + mtd->oobsize * 3, GFP_KERNEL); | |
3820 | if (!nbuf) | |
3821 | return -ENOMEM; | |
3822 | nbuf->ecccalc = (uint8_t *)(nbuf + 1); | |
3823 | nbuf->ecccode = nbuf->ecccalc + mtd->oobsize; | |
3824 | nbuf->databuf = nbuf->ecccode + mtd->oobsize; | |
3825 | ||
3826 | chip->buffers = nbuf; | |
3827 | } else { | |
3828 | if (!chip->buffers) | |
3829 | return -ENOMEM; | |
3830 | } | |
4bf63fcb | 3831 | |
7dcdcbef | 3832 | /* Set the internal oob buffer location, just after the page data */ |
784f4d5e | 3833 | chip->oob_poi = chip->buffers->databuf + mtd->writesize; |
1da177e4 | 3834 | |
7aa65bfd | 3835 | /* |
8b6e50c9 | 3836 | * If no default placement scheme is given, select an appropriate one. |
7aa65bfd | 3837 | */ |
97de79e0 | 3838 | if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) { |
61b03bd7 | 3839 | switch (mtd->oobsize) { |
1da177e4 | 3840 | case 8: |
97de79e0 | 3841 | ecc->layout = &nand_oob_8; |
1da177e4 LT |
3842 | break; |
3843 | case 16: | |
97de79e0 | 3844 | ecc->layout = &nand_oob_16; |
1da177e4 LT |
3845 | break; |
3846 | case 64: | |
97de79e0 | 3847 | ecc->layout = &nand_oob_64; |
1da177e4 | 3848 | break; |
81ec5364 | 3849 | case 128: |
97de79e0 | 3850 | ecc->layout = &nand_oob_128; |
81ec5364 | 3851 | break; |
1da177e4 | 3852 | default: |
d0370219 BN |
3853 | pr_warn("No oob scheme defined for oobsize %d\n", |
3854 | mtd->oobsize); | |
1da177e4 LT |
3855 | BUG(); |
3856 | } | |
3857 | } | |
61b03bd7 | 3858 | |
956e944c DW |
3859 | if (!chip->write_page) |
3860 | chip->write_page = nand_write_page; | |
3861 | ||
61b03bd7 | 3862 | /* |
8b6e50c9 | 3863 | * Check ECC mode, default to software if 3byte/512byte hardware ECC is |
7aa65bfd | 3864 | * selected and we have 256 byte pagesize fallback to software ECC |
e0c7d767 | 3865 | */ |
956e944c | 3866 | |
97de79e0 | 3867 | switch (ecc->mode) { |
6e0cb135 SN |
3868 | case NAND_ECC_HW_OOB_FIRST: |
3869 | /* Similar to NAND_ECC_HW, but a separate read_page handle */ | |
97de79e0 | 3870 | if (!ecc->calculate || !ecc->correct || !ecc->hwctl) { |
9a4d4d69 | 3871 | pr_warn("No ECC functions supplied; " |
d0370219 | 3872 | "hardware ECC not possible\n"); |
6e0cb135 SN |
3873 | BUG(); |
3874 | } | |
97de79e0 HS |
3875 | if (!ecc->read_page) |
3876 | ecc->read_page = nand_read_page_hwecc_oob_first; | |
6e0cb135 | 3877 | |
6dfc6d25 | 3878 | case NAND_ECC_HW: |
8b6e50c9 | 3879 | /* Use standard hwecc read page function? */ |
97de79e0 HS |
3880 | if (!ecc->read_page) |
3881 | ecc->read_page = nand_read_page_hwecc; | |
3882 | if (!ecc->write_page) | |
3883 | ecc->write_page = nand_write_page_hwecc; | |
3884 | if (!ecc->read_page_raw) | |
3885 | ecc->read_page_raw = nand_read_page_raw; | |
3886 | if (!ecc->write_page_raw) | |
3887 | ecc->write_page_raw = nand_write_page_raw; | |
3888 | if (!ecc->read_oob) | |
3889 | ecc->read_oob = nand_read_oob_std; | |
3890 | if (!ecc->write_oob) | |
3891 | ecc->write_oob = nand_write_oob_std; | |
3892 | if (!ecc->read_subpage) | |
3893 | ecc->read_subpage = nand_read_subpage; | |
3894 | if (!ecc->write_subpage) | |
3895 | ecc->write_subpage = nand_write_subpage_hwecc; | |
f5bbdacc | 3896 | |
6dfc6d25 | 3897 | case NAND_ECC_HW_SYNDROME: |
97de79e0 HS |
3898 | if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && |
3899 | (!ecc->read_page || | |
3900 | ecc->read_page == nand_read_page_hwecc || | |
3901 | !ecc->write_page || | |
3902 | ecc->write_page == nand_write_page_hwecc)) { | |
9a4d4d69 | 3903 | pr_warn("No ECC functions supplied; " |
d0370219 | 3904 | "hardware ECC not possible\n"); |
6dfc6d25 TG |
3905 | BUG(); |
3906 | } | |
8b6e50c9 | 3907 | /* Use standard syndrome read/write page function? */ |
97de79e0 HS |
3908 | if (!ecc->read_page) |
3909 | ecc->read_page = nand_read_page_syndrome; | |
3910 | if (!ecc->write_page) | |
3911 | ecc->write_page = nand_write_page_syndrome; | |
3912 | if (!ecc->read_page_raw) | |
3913 | ecc->read_page_raw = nand_read_page_raw_syndrome; | |
3914 | if (!ecc->write_page_raw) | |
3915 | ecc->write_page_raw = nand_write_page_raw_syndrome; | |
3916 | if (!ecc->read_oob) | |
3917 | ecc->read_oob = nand_read_oob_syndrome; | |
3918 | if (!ecc->write_oob) | |
3919 | ecc->write_oob = nand_write_oob_syndrome; | |
3920 | ||
3921 | if (mtd->writesize >= ecc->size) { | |
3922 | if (!ecc->strength) { | |
e2788c98 MD |
3923 | pr_warn("Driver must set ecc.strength when using hardware ECC\n"); |
3924 | BUG(); | |
3925 | } | |
6dfc6d25 | 3926 | break; |
e2788c98 | 3927 | } |
9a4d4d69 | 3928 | pr_warn("%d byte HW ECC not possible on " |
d0370219 | 3929 | "%d byte page size, fallback to SW ECC\n", |
97de79e0 HS |
3930 | ecc->size, mtd->writesize); |
3931 | ecc->mode = NAND_ECC_SOFT; | |
61b03bd7 | 3932 | |
6dfc6d25 | 3933 | case NAND_ECC_SOFT: |
97de79e0 HS |
3934 | ecc->calculate = nand_calculate_ecc; |
3935 | ecc->correct = nand_correct_data; | |
3936 | ecc->read_page = nand_read_page_swecc; | |
3937 | ecc->read_subpage = nand_read_subpage; | |
3938 | ecc->write_page = nand_write_page_swecc; | |
3939 | ecc->read_page_raw = nand_read_page_raw; | |
3940 | ecc->write_page_raw = nand_write_page_raw; | |
3941 | ecc->read_oob = nand_read_oob_std; | |
3942 | ecc->write_oob = nand_write_oob_std; | |
3943 | if (!ecc->size) | |
3944 | ecc->size = 256; | |
3945 | ecc->bytes = 3; | |
3946 | ecc->strength = 1; | |
1da177e4 | 3947 | break; |
61b03bd7 | 3948 | |
193bd400 ID |
3949 | case NAND_ECC_SOFT_BCH: |
3950 | if (!mtd_nand_has_bch()) { | |
148256fa | 3951 | pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n"); |
193bd400 ID |
3952 | BUG(); |
3953 | } | |
97de79e0 HS |
3954 | ecc->calculate = nand_bch_calculate_ecc; |
3955 | ecc->correct = nand_bch_correct_data; | |
3956 | ecc->read_page = nand_read_page_swecc; | |
3957 | ecc->read_subpage = nand_read_subpage; | |
3958 | ecc->write_page = nand_write_page_swecc; | |
3959 | ecc->read_page_raw = nand_read_page_raw; | |
3960 | ecc->write_page_raw = nand_write_page_raw; | |
3961 | ecc->read_oob = nand_read_oob_std; | |
3962 | ecc->write_oob = nand_write_oob_std; | |
193bd400 ID |
3963 | /* |
3964 | * Board driver should supply ecc.size and ecc.bytes values to | |
3965 | * select how many bits are correctable; see nand_bch_init() | |
8b6e50c9 BN |
3966 | * for details. Otherwise, default to 4 bits for large page |
3967 | * devices. | |
193bd400 | 3968 | */ |
97de79e0 HS |
3969 | if (!ecc->size && (mtd->oobsize >= 64)) { |
3970 | ecc->size = 512; | |
3971 | ecc->bytes = 7; | |
193bd400 | 3972 | } |
97de79e0 HS |
3973 | ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes, |
3974 | &ecc->layout); | |
3975 | if (!ecc->priv) { | |
9a4d4d69 | 3976 | pr_warn("BCH ECC initialization failed!\n"); |
193bd400 ID |
3977 | BUG(); |
3978 | } | |
97de79e0 | 3979 | ecc->strength = ecc->bytes * 8 / fls(8 * ecc->size); |
193bd400 ID |
3980 | break; |
3981 | ||
61b03bd7 | 3982 | case NAND_ECC_NONE: |
9a4d4d69 | 3983 | pr_warn("NAND_ECC_NONE selected by board driver. " |
d0370219 | 3984 | "This is not recommended!\n"); |
97de79e0 HS |
3985 | ecc->read_page = nand_read_page_raw; |
3986 | ecc->write_page = nand_write_page_raw; | |
3987 | ecc->read_oob = nand_read_oob_std; | |
3988 | ecc->read_page_raw = nand_read_page_raw; | |
3989 | ecc->write_page_raw = nand_write_page_raw; | |
3990 | ecc->write_oob = nand_write_oob_std; | |
3991 | ecc->size = mtd->writesize; | |
3992 | ecc->bytes = 0; | |
3993 | ecc->strength = 0; | |
1da177e4 | 3994 | break; |
956e944c | 3995 | |
1da177e4 | 3996 | default: |
97de79e0 | 3997 | pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode); |
61b03bd7 | 3998 | BUG(); |
1da177e4 | 3999 | } |
61b03bd7 | 4000 | |
9ce244b3 | 4001 | /* For many systems, the standard OOB write also works for raw */ |
97de79e0 HS |
4002 | if (!ecc->read_oob_raw) |
4003 | ecc->read_oob_raw = ecc->read_oob; | |
4004 | if (!ecc->write_oob_raw) | |
4005 | ecc->write_oob_raw = ecc->write_oob; | |
9ce244b3 | 4006 | |
5bd34c09 TG |
4007 | /* |
4008 | * The number of bytes available for a client to place data into | |
8b6e50c9 | 4009 | * the out of band area. |
5bd34c09 | 4010 | */ |
97de79e0 HS |
4011 | ecc->layout->oobavail = 0; |
4012 | for (i = 0; ecc->layout->oobfree[i].length | |
4013 | && i < ARRAY_SIZE(ecc->layout->oobfree); i++) | |
4014 | ecc->layout->oobavail += ecc->layout->oobfree[i].length; | |
4015 | mtd->oobavail = ecc->layout->oobavail; | |
5bd34c09 | 4016 | |
7aa65bfd TG |
4017 | /* |
4018 | * Set the number of read / write steps for one page depending on ECC | |
8b6e50c9 | 4019 | * mode. |
7aa65bfd | 4020 | */ |
97de79e0 HS |
4021 | ecc->steps = mtd->writesize / ecc->size; |
4022 | if (ecc->steps * ecc->size != mtd->writesize) { | |
9a4d4d69 | 4023 | pr_warn("Invalid ECC parameters\n"); |
6dfc6d25 | 4024 | BUG(); |
1da177e4 | 4025 | } |
97de79e0 | 4026 | ecc->total = ecc->steps * ecc->bytes; |
61b03bd7 | 4027 | |
8b6e50c9 | 4028 | /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ |
1d0ed69d | 4029 | if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { |
97de79e0 | 4030 | switch (ecc->steps) { |
29072b96 TG |
4031 | case 2: |
4032 | mtd->subpage_sft = 1; | |
4033 | break; | |
4034 | case 4: | |
4035 | case 8: | |
81ec5364 | 4036 | case 16: |
29072b96 TG |
4037 | mtd->subpage_sft = 2; |
4038 | break; | |
4039 | } | |
4040 | } | |
4041 | chip->subpagesize = mtd->writesize >> mtd->subpage_sft; | |
4042 | ||
04bbd0ea | 4043 | /* Initialize state */ |
ace4dfee | 4044 | chip->state = FL_READY; |
1da177e4 | 4045 | |
1da177e4 | 4046 | /* Invalidate the pagebuffer reference */ |
ace4dfee | 4047 | chip->pagebuf = -1; |
1da177e4 | 4048 | |
a5ff4f10 | 4049 | /* Large page NAND with SOFT_ECC should support subpage reads */ |
4007e2d1 RL |
4050 | switch (ecc->mode) { |
4051 | case NAND_ECC_SOFT: | |
4052 | case NAND_ECC_SOFT_BCH: | |
4053 | if (chip->page_shift > 9) | |
4054 | chip->options |= NAND_SUBPAGE_READ; | |
4055 | break; | |
4056 | ||
4057 | default: | |
4058 | break; | |
4059 | } | |
a5ff4f10 | 4060 | |
1da177e4 | 4061 | /* Fill in remaining MTD driver data */ |
963d1c28 | 4062 | mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH; |
93edbad6 ML |
4063 | mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : |
4064 | MTD_CAP_NANDFLASH; | |
3c3c10bb AB |
4065 | mtd->_erase = nand_erase; |
4066 | mtd->_point = NULL; | |
4067 | mtd->_unpoint = NULL; | |
4068 | mtd->_read = nand_read; | |
4069 | mtd->_write = nand_write; | |
4070 | mtd->_panic_write = panic_nand_write; | |
4071 | mtd->_read_oob = nand_read_oob; | |
4072 | mtd->_write_oob = nand_write_oob; | |
4073 | mtd->_sync = nand_sync; | |
4074 | mtd->_lock = NULL; | |
4075 | mtd->_unlock = NULL; | |
4076 | mtd->_suspend = nand_suspend; | |
4077 | mtd->_resume = nand_resume; | |
4078 | mtd->_block_isbad = nand_block_isbad; | |
4079 | mtd->_block_markbad = nand_block_markbad; | |
cbcab65a | 4080 | mtd->writebufsize = mtd->writesize; |
1da177e4 | 4081 | |
6a918bad | 4082 | /* propagate ecc info to mtd_info */ |
97de79e0 HS |
4083 | mtd->ecclayout = ecc->layout; |
4084 | mtd->ecc_strength = ecc->strength; | |
4085 | mtd->ecc_step_size = ecc->size; | |
ea3b2ea2 SL |
4086 | /* |
4087 | * Initialize bitflip_threshold to its default prior scan_bbt() call. | |
4088 | * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be | |
4089 | * properly set. | |
4090 | */ | |
4091 | if (!mtd->bitflip_threshold) | |
4092 | mtd->bitflip_threshold = mtd->ecc_strength; | |
1da177e4 | 4093 | |
0040bf38 | 4094 | /* Check, if we should skip the bad block table scan */ |
ace4dfee | 4095 | if (chip->options & NAND_SKIP_BBTSCAN) |
0040bf38 | 4096 | return 0; |
1da177e4 LT |
4097 | |
4098 | /* Build bad block table */ | |
ace4dfee | 4099 | return chip->scan_bbt(mtd); |
1da177e4 | 4100 | } |
7351d3a5 | 4101 | EXPORT_SYMBOL(nand_scan_tail); |
1da177e4 | 4102 | |
8b6e50c9 BN |
4103 | /* |
4104 | * is_module_text_address() isn't exported, and it's mostly a pointless | |
7351d3a5 | 4105 | * test if this is a module _anyway_ -- they'd have to try _really_ hard |
8b6e50c9 BN |
4106 | * to call us from in-kernel code if the core NAND support is modular. |
4107 | */ | |
3b85c321 DW |
4108 | #ifdef MODULE |
4109 | #define caller_is_module() (1) | |
4110 | #else | |
4111 | #define caller_is_module() \ | |
a6e6abd5 | 4112 | is_module_text_address((unsigned long)__builtin_return_address(0)) |
3b85c321 DW |
4113 | #endif |
4114 | ||
4115 | /** | |
4116 | * nand_scan - [NAND Interface] Scan for the NAND device | |
8b6e50c9 BN |
4117 | * @mtd: MTD device structure |
4118 | * @maxchips: number of chips to scan for | |
3b85c321 | 4119 | * |
8b6e50c9 BN |
4120 | * This fills out all the uninitialized function pointers with the defaults. |
4121 | * The flash ID is read and the mtd/chip structures are filled with the | |
4122 | * appropriate values. The mtd->owner field must be set to the module of the | |
4123 | * caller. | |
3b85c321 DW |
4124 | */ |
4125 | int nand_scan(struct mtd_info *mtd, int maxchips) | |
4126 | { | |
4127 | int ret; | |
4128 | ||
4129 | /* Many callers got this wrong, so check for it for a while... */ | |
4130 | if (!mtd->owner && caller_is_module()) { | |
d0370219 | 4131 | pr_crit("%s called with NULL mtd->owner!\n", __func__); |
3b85c321 DW |
4132 | BUG(); |
4133 | } | |
4134 | ||
5e81e88a | 4135 | ret = nand_scan_ident(mtd, maxchips, NULL); |
3b85c321 DW |
4136 | if (!ret) |
4137 | ret = nand_scan_tail(mtd); | |
4138 | return ret; | |
4139 | } | |
7351d3a5 | 4140 | EXPORT_SYMBOL(nand_scan); |
3b85c321 | 4141 | |
1da177e4 | 4142 | /** |
61b03bd7 | 4143 | * nand_release - [NAND Interface] Free resources held by the NAND device |
8b6e50c9 BN |
4144 | * @mtd: MTD device structure |
4145 | */ | |
e0c7d767 | 4146 | void nand_release(struct mtd_info *mtd) |
1da177e4 | 4147 | { |
ace4dfee | 4148 | struct nand_chip *chip = mtd->priv; |
1da177e4 | 4149 | |
193bd400 ID |
4150 | if (chip->ecc.mode == NAND_ECC_SOFT_BCH) |
4151 | nand_bch_free((struct nand_bch_control *)chip->ecc.priv); | |
4152 | ||
5ffcaf3d | 4153 | mtd_device_unregister(mtd); |
1da177e4 | 4154 | |
fa671646 | 4155 | /* Free bad block table memory */ |
ace4dfee | 4156 | kfree(chip->bbt); |
4bf63fcb DW |
4157 | if (!(chip->options & NAND_OWN_BUFFERS)) |
4158 | kfree(chip->buffers); | |
58373ff0 BN |
4159 | |
4160 | /* Free bad block descriptor memory */ | |
4161 | if (chip->badblock_pattern && chip->badblock_pattern->options | |
4162 | & NAND_BBT_DYNAMICSTRUCT) | |
4163 | kfree(chip->badblock_pattern); | |
1da177e4 | 4164 | } |
e0c7d767 | 4165 | EXPORT_SYMBOL_GPL(nand_release); |
8fe833c1 RP |
4166 | |
4167 | static int __init nand_base_init(void) | |
4168 | { | |
4169 | led_trigger_register_simple("nand-disk", &nand_led_trigger); | |
4170 | return 0; | |
4171 | } | |
4172 | ||
4173 | static void __exit nand_base_exit(void) | |
4174 | { | |
4175 | led_trigger_unregister_simple(nand_led_trigger); | |
4176 | } | |
4177 | ||
4178 | module_init(nand_base_init); | |
4179 | module_exit(nand_base_exit); | |
4180 | ||
e0c7d767 | 4181 | MODULE_LICENSE("GPL"); |
7351d3a5 FF |
4182 | MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); |
4183 | MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); | |
e0c7d767 | 4184 | MODULE_DESCRIPTION("Generic NAND flash driver code"); |