]>
Commit | Line | Data |
---|---|---|
67ce04bf VS |
1 | /* |
2 | * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com> | |
3 | * Copyright © 2004 Micron Technology Inc. | |
4 | * Copyright © 2004 David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/platform_device.h> | |
763e7359 | 12 | #include <linux/dmaengine.h> |
67ce04bf VS |
13 | #include <linux/dma-mapping.h> |
14 | #include <linux/delay.h> | |
10f22ee3 | 15 | #include <linux/gpio/consumer.h> |
a0e5cc58 | 16 | #include <linux/module.h> |
4e070376 | 17 | #include <linux/interrupt.h> |
c276aca4 | 18 | #include <linux/jiffies.h> |
19 | #include <linux/sched.h> | |
67ce04bf VS |
20 | #include <linux/mtd/mtd.h> |
21 | #include <linux/mtd/nand.h> | |
22 | #include <linux/mtd/partitions.h> | |
763e7359 | 23 | #include <linux/omap-dma.h> |
67ce04bf | 24 | #include <linux/io.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
62116e51 PA |
26 | #include <linux/of.h> |
27 | #include <linux/of_device.h> | |
67ce04bf | 28 | |
32d42a85 | 29 | #include <linux/mtd/nand_bch.h> |
62116e51 | 30 | #include <linux/platform_data/elm.h> |
0e618ef0 | 31 | |
c509aefd | 32 | #include <linux/omap-gpmc.h> |
2203747c | 33 | #include <linux/platform_data/mtd-nand-omap2.h> |
67ce04bf | 34 | |
67ce04bf | 35 | #define DRIVER_NAME "omap2-nand" |
4e070376 | 36 | #define OMAP_NAND_TIMEOUT_MS 5000 |
67ce04bf | 37 | |
67ce04bf VS |
38 | #define NAND_Ecc_P1e (1 << 0) |
39 | #define NAND_Ecc_P2e (1 << 1) | |
40 | #define NAND_Ecc_P4e (1 << 2) | |
41 | #define NAND_Ecc_P8e (1 << 3) | |
42 | #define NAND_Ecc_P16e (1 << 4) | |
43 | #define NAND_Ecc_P32e (1 << 5) | |
44 | #define NAND_Ecc_P64e (1 << 6) | |
45 | #define NAND_Ecc_P128e (1 << 7) | |
46 | #define NAND_Ecc_P256e (1 << 8) | |
47 | #define NAND_Ecc_P512e (1 << 9) | |
48 | #define NAND_Ecc_P1024e (1 << 10) | |
49 | #define NAND_Ecc_P2048e (1 << 11) | |
50 | ||
51 | #define NAND_Ecc_P1o (1 << 16) | |
52 | #define NAND_Ecc_P2o (1 << 17) | |
53 | #define NAND_Ecc_P4o (1 << 18) | |
54 | #define NAND_Ecc_P8o (1 << 19) | |
55 | #define NAND_Ecc_P16o (1 << 20) | |
56 | #define NAND_Ecc_P32o (1 << 21) | |
57 | #define NAND_Ecc_P64o (1 << 22) | |
58 | #define NAND_Ecc_P128o (1 << 23) | |
59 | #define NAND_Ecc_P256o (1 << 24) | |
60 | #define NAND_Ecc_P512o (1 << 25) | |
61 | #define NAND_Ecc_P1024o (1 << 26) | |
62 | #define NAND_Ecc_P2048o (1 << 27) | |
63 | ||
64 | #define TF(value) (value ? 1 : 0) | |
65 | ||
66 | #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0) | |
67 | #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1) | |
68 | #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2) | |
69 | #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3) | |
70 | #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4) | |
71 | #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5) | |
72 | #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6) | |
73 | #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7) | |
74 | ||
75 | #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0) | |
76 | #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1) | |
77 | #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2) | |
78 | #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3) | |
79 | #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4) | |
80 | #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5) | |
81 | #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6) | |
82 | #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7) | |
83 | ||
84 | #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0) | |
85 | #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1) | |
86 | #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2) | |
87 | #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3) | |
88 | #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4) | |
89 | #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5) | |
90 | #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6) | |
91 | #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7) | |
92 | ||
93 | #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0) | |
94 | #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1) | |
95 | #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2) | |
96 | #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3) | |
97 | #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4) | |
98 | #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5) | |
99 | #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6) | |
100 | #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7) | |
101 | ||
102 | #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) | |
103 | #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) | |
104 | ||
65b97cf6 AM |
105 | #define PREFETCH_CONFIG1_CS_SHIFT 24 |
106 | #define ECC_CONFIG_CS_SHIFT 1 | |
107 | #define CS_MASK 0x7 | |
108 | #define ENABLE_PREFETCH (0x1 << 7) | |
109 | #define DMA_MPU_MODE_SHIFT 2 | |
2ef9f3dd | 110 | #define ECCSIZE0_SHIFT 12 |
65b97cf6 AM |
111 | #define ECCSIZE1_SHIFT 22 |
112 | #define ECC1RESULTSIZE 0x1 | |
113 | #define ECCCLEAR 0x100 | |
114 | #define ECC1 0x1 | |
47f88af4 AM |
115 | #define PREFETCH_FIFOTHRESHOLD_MAX 0x40 |
116 | #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) | |
117 | #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) | |
118 | #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) | |
119 | #define STATUS_BUFF_EMPTY 0x00000001 | |
65b97cf6 | 120 | |
62116e51 PA |
121 | #define SECTOR_BYTES 512 |
122 | /* 4 bit padding to make byte aligned, 56 = 52 + 4 */ | |
123 | #define BCH4_BIT_PAD 4 | |
62116e51 PA |
124 | |
125 | /* GPMC ecc engine settings for read */ | |
126 | #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */ | |
127 | #define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */ | |
128 | #define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */ | |
129 | #define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */ | |
130 | #define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */ | |
131 | ||
132 | /* GPMC ecc engine settings for write */ | |
133 | #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */ | |
134 | #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */ | |
135 | #define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */ | |
136 | ||
b491da72 | 137 | #define BADBLOCK_MARKER_LENGTH 2 |
a919e511 | 138 | |
9748fff9 | 139 | static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55, |
140 | 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78, | |
141 | 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93, | |
142 | 0x07, 0x0e}; | |
62116e51 PA |
143 | static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc, |
144 | 0xac, 0x6b, 0xff, 0x99, 0x7b}; | |
145 | static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10}; | |
62116e51 | 146 | |
1dc338e8 RL |
147 | /* Shared among all NAND instances to synchronize access to the ECC Engine */ |
148 | static struct nand_hw_control omap_gpmc_controller = { | |
149 | .lock = __SPIN_LOCK_UNLOCKED(omap_gpmc_controller.lock), | |
150 | .wq = __WAIT_QUEUE_HEAD_INITIALIZER(omap_gpmc_controller.wq), | |
151 | }; | |
59e9c5ae | 152 | |
67ce04bf | 153 | struct omap_nand_info { |
67ce04bf VS |
154 | struct nand_chip nand; |
155 | struct platform_device *pdev; | |
156 | ||
157 | int gpmc_cs; | |
01b95fc6 RQ |
158 | bool dev_ready; |
159 | enum nand_io xfer_type; | |
160 | int devsize; | |
4e558072 | 161 | enum omap_ecc ecc_opt; |
01b95fc6 RQ |
162 | struct device_node *elm_of_node; |
163 | ||
164 | unsigned long phys_base; | |
dfe32893 | 165 | struct completion comp; |
763e7359 | 166 | struct dma_chan *dma; |
5c468455 AM |
167 | int gpmc_irq_fifo; |
168 | int gpmc_irq_count; | |
4e070376 SG |
169 | enum { |
170 | OMAP_NAND_IO_READ = 0, /* read */ | |
171 | OMAP_NAND_IO_WRITE, /* write */ | |
172 | } iomode; | |
173 | u_char *buf; | |
174 | int buf_len; | |
c509aefd | 175 | /* Interface to GPMC */ |
65b97cf6 | 176 | struct gpmc_nand_regs reg; |
c509aefd | 177 | struct gpmc_nand_ops *ops; |
c9711ec5 | 178 | bool flash_bbt; |
a919e511 | 179 | /* fields specific for BCHx_HW ECC scheme */ |
62116e51 | 180 | struct device *elm_dev; |
10f22ee3 RQ |
181 | /* NAND ready gpio */ |
182 | struct gpio_desc *ready_gpiod; | |
67ce04bf VS |
183 | }; |
184 | ||
4578ea9a BB |
185 | static inline struct omap_nand_info *mtd_to_omap(struct mtd_info *mtd) |
186 | { | |
432420c0 | 187 | return container_of(mtd_to_nand(mtd), struct omap_nand_info, nand); |
4578ea9a | 188 | } |
432420c0 | 189 | |
65b97cf6 AM |
190 | /** |
191 | * omap_prefetch_enable - configures and starts prefetch transfer | |
192 | * @cs: cs (chip select) number | |
193 | * @fifo_th: fifo threshold to be used for read/ write | |
194 | * @dma_mode: dma mode enable (1) or disable (0) | |
195 | * @u32_count: number of bytes to be transferred | |
196 | * @is_write: prefetch read(0) or write post(1) mode | |
197 | */ | |
198 | static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode, | |
199 | unsigned int u32_count, int is_write, struct omap_nand_info *info) | |
200 | { | |
201 | u32 val; | |
202 | ||
203 | if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) | |
204 | return -1; | |
205 | ||
206 | if (readl(info->reg.gpmc_prefetch_control)) | |
207 | return -EBUSY; | |
208 | ||
209 | /* Set the amount of bytes to be prefetched */ | |
210 | writel(u32_count, info->reg.gpmc_prefetch_config2); | |
211 | ||
212 | /* Set dma/mpu mode, the prefetch read / post write and | |
213 | * enable the engine. Set which cs is has requested for. | |
214 | */ | |
215 | val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) | | |
216 | PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH | | |
57a605b1 | 217 | (dma_mode << DMA_MPU_MODE_SHIFT) | (is_write & 0x1)); |
65b97cf6 AM |
218 | writel(val, info->reg.gpmc_prefetch_config1); |
219 | ||
220 | /* Start the prefetch engine */ | |
221 | writel(0x1, info->reg.gpmc_prefetch_control); | |
222 | ||
223 | return 0; | |
224 | } | |
225 | ||
226 | /** | |
227 | * omap_prefetch_reset - disables and stops the prefetch engine | |
228 | */ | |
229 | static int omap_prefetch_reset(int cs, struct omap_nand_info *info) | |
230 | { | |
231 | u32 config1; | |
232 | ||
233 | /* check if the same module/cs is trying to reset */ | |
234 | config1 = readl(info->reg.gpmc_prefetch_config1); | |
235 | if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs) | |
236 | return -EINVAL; | |
237 | ||
238 | /* Stop the PFPW engine */ | |
239 | writel(0x0, info->reg.gpmc_prefetch_control); | |
240 | ||
241 | /* Reset/disable the PFPW engine */ | |
242 | writel(0x0, info->reg.gpmc_prefetch_config1); | |
243 | ||
244 | return 0; | |
245 | } | |
246 | ||
67ce04bf VS |
247 | /** |
248 | * omap_hwcontrol - hardware specific access to control-lines | |
249 | * @mtd: MTD device structure | |
250 | * @cmd: command to device | |
251 | * @ctrl: | |
252 | * NAND_NCE: bit 0 -> don't care | |
253 | * NAND_CLE: bit 1 -> Command Latch | |
254 | * NAND_ALE: bit 2 -> Address Latch | |
255 | * | |
256 | * NOTE: boards may use different bits for these!! | |
257 | */ | |
258 | static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
259 | { | |
4578ea9a | 260 | struct omap_nand_info *info = mtd_to_omap(mtd); |
67ce04bf | 261 | |
2c01946c SG |
262 | if (cmd != NAND_CMD_NONE) { |
263 | if (ctrl & NAND_CLE) | |
65b97cf6 | 264 | writeb(cmd, info->reg.gpmc_nand_command); |
2c01946c SG |
265 | |
266 | else if (ctrl & NAND_ALE) | |
65b97cf6 | 267 | writeb(cmd, info->reg.gpmc_nand_address); |
2c01946c SG |
268 | |
269 | else /* NAND_NCE */ | |
65b97cf6 | 270 | writeb(cmd, info->reg.gpmc_nand_data); |
2c01946c | 271 | } |
67ce04bf VS |
272 | } |
273 | ||
59e9c5ae | 274 | /** |
275 | * omap_read_buf8 - read data from NAND controller into buffer | |
276 | * @mtd: MTD device structure | |
277 | * @buf: buffer to store date | |
278 | * @len: number of bytes to read | |
279 | */ | |
280 | static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len) | |
281 | { | |
4bd4ebcc | 282 | struct nand_chip *nand = mtd_to_nand(mtd); |
59e9c5ae | 283 | |
284 | ioread8_rep(nand->IO_ADDR_R, buf, len); | |
285 | } | |
286 | ||
287 | /** | |
288 | * omap_write_buf8 - write buffer to NAND controller | |
289 | * @mtd: MTD device structure | |
290 | * @buf: data buffer | |
291 | * @len: number of bytes to write | |
292 | */ | |
293 | static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len) | |
294 | { | |
4578ea9a | 295 | struct omap_nand_info *info = mtd_to_omap(mtd); |
59e9c5ae | 296 | u_char *p = (u_char *)buf; |
d6e55216 | 297 | bool status; |
59e9c5ae | 298 | |
299 | while (len--) { | |
300 | iowrite8(*p++, info->nand.IO_ADDR_W); | |
2c01946c SG |
301 | /* wait until buffer is available for write */ |
302 | do { | |
d6e55216 | 303 | status = info->ops->nand_writebuffer_empty(); |
2c01946c | 304 | } while (!status); |
59e9c5ae | 305 | } |
306 | } | |
307 | ||
67ce04bf VS |
308 | /** |
309 | * omap_read_buf16 - read data from NAND controller into buffer | |
310 | * @mtd: MTD device structure | |
311 | * @buf: buffer to store date | |
312 | * @len: number of bytes to read | |
313 | */ | |
314 | static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len) | |
315 | { | |
4bd4ebcc | 316 | struct nand_chip *nand = mtd_to_nand(mtd); |
67ce04bf | 317 | |
59e9c5ae | 318 | ioread16_rep(nand->IO_ADDR_R, buf, len / 2); |
67ce04bf VS |
319 | } |
320 | ||
321 | /** | |
322 | * omap_write_buf16 - write buffer to NAND controller | |
323 | * @mtd: MTD device structure | |
324 | * @buf: data buffer | |
325 | * @len: number of bytes to write | |
326 | */ | |
327 | static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len) | |
328 | { | |
4578ea9a | 329 | struct omap_nand_info *info = mtd_to_omap(mtd); |
67ce04bf | 330 | u16 *p = (u16 *) buf; |
d6e55216 | 331 | bool status; |
67ce04bf VS |
332 | /* FIXME try bursts of writesw() or DMA ... */ |
333 | len >>= 1; | |
334 | ||
335 | while (len--) { | |
59e9c5ae | 336 | iowrite16(*p++, info->nand.IO_ADDR_W); |
2c01946c SG |
337 | /* wait until buffer is available for write */ |
338 | do { | |
d6e55216 | 339 | status = info->ops->nand_writebuffer_empty(); |
2c01946c | 340 | } while (!status); |
67ce04bf VS |
341 | } |
342 | } | |
59e9c5ae | 343 | |
344 | /** | |
345 | * omap_read_buf_pref - read data from NAND controller into buffer | |
346 | * @mtd: MTD device structure | |
347 | * @buf: buffer to store date | |
348 | * @len: number of bytes to read | |
349 | */ | |
350 | static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) | |
351 | { | |
4578ea9a | 352 | struct omap_nand_info *info = mtd_to_omap(mtd); |
2c01946c | 353 | uint32_t r_count = 0; |
59e9c5ae | 354 | int ret = 0; |
355 | u32 *p = (u32 *)buf; | |
356 | ||
357 | /* take care of subpage reads */ | |
c3341d0c VS |
358 | if (len % 4) { |
359 | if (info->nand.options & NAND_BUSWIDTH_16) | |
360 | omap_read_buf16(mtd, buf, len % 4); | |
361 | else | |
362 | omap_read_buf8(mtd, buf, len % 4); | |
363 | p = (u32 *) (buf + len % 4); | |
364 | len -= len % 4; | |
59e9c5ae | 365 | } |
59e9c5ae | 366 | |
367 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
368 | ret = omap_prefetch_enable(info->gpmc_cs, |
369 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info); | |
59e9c5ae | 370 | if (ret) { |
371 | /* PFPW engine is busy, use cpu copy method */ | |
372 | if (info->nand.options & NAND_BUSWIDTH_16) | |
c5d8c0ca | 373 | omap_read_buf16(mtd, (u_char *)p, len); |
59e9c5ae | 374 | else |
c5d8c0ca | 375 | omap_read_buf8(mtd, (u_char *)p, len); |
59e9c5ae | 376 | } else { |
377 | do { | |
65b97cf6 | 378 | r_count = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 379 | r_count = PREFETCH_STATUS_FIFO_CNT(r_count); |
2c01946c SG |
380 | r_count = r_count >> 2; |
381 | ioread32_rep(info->nand.IO_ADDR_R, p, r_count); | |
59e9c5ae | 382 | p += r_count; |
383 | len -= r_count << 2; | |
384 | } while (len); | |
59e9c5ae | 385 | /* disable and stop the PFPW engine */ |
65b97cf6 | 386 | omap_prefetch_reset(info->gpmc_cs, info); |
59e9c5ae | 387 | } |
388 | } | |
389 | ||
390 | /** | |
391 | * omap_write_buf_pref - write buffer to NAND controller | |
392 | * @mtd: MTD device structure | |
393 | * @buf: data buffer | |
394 | * @len: number of bytes to write | |
395 | */ | |
396 | static void omap_write_buf_pref(struct mtd_info *mtd, | |
397 | const u_char *buf, int len) | |
398 | { | |
4578ea9a | 399 | struct omap_nand_info *info = mtd_to_omap(mtd); |
4e070376 | 400 | uint32_t w_count = 0; |
59e9c5ae | 401 | int i = 0, ret = 0; |
c5d8c0ca | 402 | u16 *p = (u16 *)buf; |
4e070376 | 403 | unsigned long tim, limit; |
65b97cf6 | 404 | u32 val; |
59e9c5ae | 405 | |
406 | /* take care of subpage writes */ | |
407 | if (len % 2 != 0) { | |
2c01946c | 408 | writeb(*buf, info->nand.IO_ADDR_W); |
59e9c5ae | 409 | p = (u16 *)(buf + 1); |
410 | len--; | |
411 | } | |
412 | ||
413 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
414 | ret = omap_prefetch_enable(info->gpmc_cs, |
415 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info); | |
59e9c5ae | 416 | if (ret) { |
417 | /* PFPW engine is busy, use cpu copy method */ | |
418 | if (info->nand.options & NAND_BUSWIDTH_16) | |
c5d8c0ca | 419 | omap_write_buf16(mtd, (u_char *)p, len); |
59e9c5ae | 420 | else |
c5d8c0ca | 421 | omap_write_buf8(mtd, (u_char *)p, len); |
59e9c5ae | 422 | } else { |
2c01946c | 423 | while (len) { |
65b97cf6 | 424 | w_count = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 425 | w_count = PREFETCH_STATUS_FIFO_CNT(w_count); |
2c01946c | 426 | w_count = w_count >> 1; |
59e9c5ae | 427 | for (i = 0; (i < w_count) && len; i++, len -= 2) |
2c01946c | 428 | iowrite16(*p++, info->nand.IO_ADDR_W); |
59e9c5ae | 429 | } |
2c01946c | 430 | /* wait for data to flushed-out before reset the prefetch */ |
4e070376 SG |
431 | tim = 0; |
432 | limit = (loops_per_jiffy * | |
433 | msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 | 434 | do { |
4e070376 | 435 | cpu_relax(); |
65b97cf6 | 436 | val = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 437 | val = PREFETCH_STATUS_COUNT(val); |
65b97cf6 | 438 | } while (val && (tim++ < limit)); |
4e070376 | 439 | |
59e9c5ae | 440 | /* disable and stop the PFPW engine */ |
65b97cf6 | 441 | omap_prefetch_reset(info->gpmc_cs, info); |
59e9c5ae | 442 | } |
443 | } | |
444 | ||
dfe32893 | 445 | /* |
2df41d05 | 446 | * omap_nand_dma_callback: callback on the completion of dma transfer |
dfe32893 | 447 | * @data: pointer to completion data structure |
448 | */ | |
763e7359 RK |
449 | static void omap_nand_dma_callback(void *data) |
450 | { | |
451 | complete((struct completion *) data); | |
452 | } | |
dfe32893 | 453 | |
454 | /* | |
4cacbe22 | 455 | * omap_nand_dma_transfer: configure and start dma transfer |
dfe32893 | 456 | * @mtd: MTD device structure |
457 | * @addr: virtual address in RAM of source/destination | |
458 | * @len: number of data bytes to be transferred | |
459 | * @is_write: flag for read/write operation | |
460 | */ | |
461 | static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, | |
462 | unsigned int len, int is_write) | |
463 | { | |
4578ea9a | 464 | struct omap_nand_info *info = mtd_to_omap(mtd); |
2df41d05 | 465 | struct dma_async_tx_descriptor *tx; |
dfe32893 | 466 | enum dma_data_direction dir = is_write ? DMA_TO_DEVICE : |
467 | DMA_FROM_DEVICE; | |
2df41d05 | 468 | struct scatterlist sg; |
4e070376 | 469 | unsigned long tim, limit; |
2df41d05 RK |
470 | unsigned n; |
471 | int ret; | |
65b97cf6 | 472 | u32 val; |
dfe32893 | 473 | |
8c6f0fc4 CJF |
474 | if (!virt_addr_valid(addr)) |
475 | goto out_copy; | |
dfe32893 | 476 | |
2df41d05 RK |
477 | sg_init_one(&sg, addr, len); |
478 | n = dma_map_sg(info->dma->device->dev, &sg, 1, dir); | |
479 | if (n == 0) { | |
dfe32893 | 480 | dev_err(&info->pdev->dev, |
481 | "Couldn't DMA map a %d byte buffer\n", len); | |
482 | goto out_copy; | |
483 | } | |
484 | ||
2df41d05 RK |
485 | tx = dmaengine_prep_slave_sg(info->dma, &sg, n, |
486 | is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, | |
487 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
488 | if (!tx) | |
489 | goto out_copy_unmap; | |
490 | ||
491 | tx->callback = omap_nand_dma_callback; | |
492 | tx->callback_param = &info->comp; | |
493 | dmaengine_submit(tx); | |
494 | ||
03d3a1df CJF |
495 | init_completion(&info->comp); |
496 | ||
497 | /* setup and start DMA using dma_addr */ | |
498 | dma_async_issue_pending(info->dma); | |
499 | ||
65b97cf6 AM |
500 | /* configure and start prefetch transfer */ |
501 | ret = omap_prefetch_enable(info->gpmc_cs, | |
502 | PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info); | |
dfe32893 | 503 | if (ret) |
4e070376 | 504 | /* PFPW engine is busy, use cpu copy method */ |
d7efe228 | 505 | goto out_copy_unmap; |
dfe32893 | 506 | |
dfe32893 | 507 | wait_for_completion(&info->comp); |
4e070376 SG |
508 | tim = 0; |
509 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 AM |
510 | |
511 | do { | |
4e070376 | 512 | cpu_relax(); |
65b97cf6 | 513 | val = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 514 | val = PREFETCH_STATUS_COUNT(val); |
65b97cf6 | 515 | } while (val && (tim++ < limit)); |
dfe32893 | 516 | |
dfe32893 | 517 | /* disable and stop the PFPW engine */ |
65b97cf6 | 518 | omap_prefetch_reset(info->gpmc_cs, info); |
dfe32893 | 519 | |
2df41d05 | 520 | dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); |
dfe32893 | 521 | return 0; |
522 | ||
d7efe228 | 523 | out_copy_unmap: |
2df41d05 | 524 | dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); |
dfe32893 | 525 | out_copy: |
526 | if (info->nand.options & NAND_BUSWIDTH_16) | |
527 | is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len) | |
528 | : omap_write_buf16(mtd, (u_char *) addr, len); | |
529 | else | |
530 | is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len) | |
531 | : omap_write_buf8(mtd, (u_char *) addr, len); | |
532 | return 0; | |
533 | } | |
dfe32893 | 534 | |
535 | /** | |
536 | * omap_read_buf_dma_pref - read data from NAND controller into buffer | |
537 | * @mtd: MTD device structure | |
538 | * @buf: buffer to store date | |
539 | * @len: number of bytes to read | |
540 | */ | |
541 | static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len) | |
542 | { | |
543 | if (len <= mtd->oobsize) | |
544 | omap_read_buf_pref(mtd, buf, len); | |
545 | else | |
546 | /* start transfer in DMA mode */ | |
547 | omap_nand_dma_transfer(mtd, buf, len, 0x0); | |
548 | } | |
549 | ||
550 | /** | |
551 | * omap_write_buf_dma_pref - write buffer to NAND controller | |
552 | * @mtd: MTD device structure | |
553 | * @buf: data buffer | |
554 | * @len: number of bytes to write | |
555 | */ | |
556 | static void omap_write_buf_dma_pref(struct mtd_info *mtd, | |
557 | const u_char *buf, int len) | |
558 | { | |
559 | if (len <= mtd->oobsize) | |
560 | omap_write_buf_pref(mtd, buf, len); | |
561 | else | |
562 | /* start transfer in DMA mode */ | |
bdaefc41 | 563 | omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1); |
dfe32893 | 564 | } |
565 | ||
4e070376 | 566 | /* |
4cacbe22 | 567 | * omap_nand_irq - GPMC irq handler |
4e070376 SG |
568 | * @this_irq: gpmc irq number |
569 | * @dev: omap_nand_info structure pointer is passed here | |
570 | */ | |
571 | static irqreturn_t omap_nand_irq(int this_irq, void *dev) | |
572 | { | |
573 | struct omap_nand_info *info = (struct omap_nand_info *) dev; | |
574 | u32 bytes; | |
4e070376 | 575 | |
65b97cf6 | 576 | bytes = readl(info->reg.gpmc_prefetch_status); |
47f88af4 | 577 | bytes = PREFETCH_STATUS_FIFO_CNT(bytes); |
4e070376 SG |
578 | bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ |
579 | if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ | |
5c468455 | 580 | if (this_irq == info->gpmc_irq_count) |
4e070376 SG |
581 | goto done; |
582 | ||
583 | if (info->buf_len && (info->buf_len < bytes)) | |
584 | bytes = info->buf_len; | |
585 | else if (!info->buf_len) | |
586 | bytes = 0; | |
587 | iowrite32_rep(info->nand.IO_ADDR_W, | |
588 | (u32 *)info->buf, bytes >> 2); | |
589 | info->buf = info->buf + bytes; | |
590 | info->buf_len -= bytes; | |
591 | ||
592 | } else { | |
593 | ioread32_rep(info->nand.IO_ADDR_R, | |
594 | (u32 *)info->buf, bytes >> 2); | |
595 | info->buf = info->buf + bytes; | |
596 | ||
5c468455 | 597 | if (this_irq == info->gpmc_irq_count) |
4e070376 SG |
598 | goto done; |
599 | } | |
4e070376 SG |
600 | |
601 | return IRQ_HANDLED; | |
602 | ||
603 | done: | |
604 | complete(&info->comp); | |
4e070376 | 605 | |
5c468455 AM |
606 | disable_irq_nosync(info->gpmc_irq_fifo); |
607 | disable_irq_nosync(info->gpmc_irq_count); | |
4e070376 SG |
608 | |
609 | return IRQ_HANDLED; | |
610 | } | |
611 | ||
612 | /* | |
613 | * omap_read_buf_irq_pref - read data from NAND controller into buffer | |
614 | * @mtd: MTD device structure | |
615 | * @buf: buffer to store date | |
616 | * @len: number of bytes to read | |
617 | */ | |
618 | static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) | |
619 | { | |
4578ea9a | 620 | struct omap_nand_info *info = mtd_to_omap(mtd); |
4e070376 SG |
621 | int ret = 0; |
622 | ||
623 | if (len <= mtd->oobsize) { | |
624 | omap_read_buf_pref(mtd, buf, len); | |
625 | return; | |
626 | } | |
627 | ||
628 | info->iomode = OMAP_NAND_IO_READ; | |
629 | info->buf = buf; | |
630 | init_completion(&info->comp); | |
631 | ||
632 | /* configure and start prefetch transfer */ | |
65b97cf6 AM |
633 | ret = omap_prefetch_enable(info->gpmc_cs, |
634 | PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info); | |
4e070376 SG |
635 | if (ret) |
636 | /* PFPW engine is busy, use cpu copy method */ | |
637 | goto out_copy; | |
638 | ||
639 | info->buf_len = len; | |
5c468455 AM |
640 | |
641 | enable_irq(info->gpmc_irq_count); | |
642 | enable_irq(info->gpmc_irq_fifo); | |
4e070376 SG |
643 | |
644 | /* waiting for read to complete */ | |
645 | wait_for_completion(&info->comp); | |
646 | ||
647 | /* disable and stop the PFPW engine */ | |
65b97cf6 | 648 | omap_prefetch_reset(info->gpmc_cs, info); |
4e070376 SG |
649 | return; |
650 | ||
651 | out_copy: | |
652 | if (info->nand.options & NAND_BUSWIDTH_16) | |
653 | omap_read_buf16(mtd, buf, len); | |
654 | else | |
655 | omap_read_buf8(mtd, buf, len); | |
656 | } | |
657 | ||
658 | /* | |
659 | * omap_write_buf_irq_pref - write buffer to NAND controller | |
660 | * @mtd: MTD device structure | |
661 | * @buf: data buffer | |
662 | * @len: number of bytes to write | |
663 | */ | |
664 | static void omap_write_buf_irq_pref(struct mtd_info *mtd, | |
665 | const u_char *buf, int len) | |
666 | { | |
4578ea9a | 667 | struct omap_nand_info *info = mtd_to_omap(mtd); |
4e070376 SG |
668 | int ret = 0; |
669 | unsigned long tim, limit; | |
65b97cf6 | 670 | u32 val; |
4e070376 SG |
671 | |
672 | if (len <= mtd->oobsize) { | |
673 | omap_write_buf_pref(mtd, buf, len); | |
674 | return; | |
675 | } | |
676 | ||
677 | info->iomode = OMAP_NAND_IO_WRITE; | |
678 | info->buf = (u_char *) buf; | |
679 | init_completion(&info->comp); | |
680 | ||
317379a9 | 681 | /* configure and start prefetch transfer : size=24 */ |
65b97cf6 AM |
682 | ret = omap_prefetch_enable(info->gpmc_cs, |
683 | (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info); | |
4e070376 SG |
684 | if (ret) |
685 | /* PFPW engine is busy, use cpu copy method */ | |
686 | goto out_copy; | |
687 | ||
688 | info->buf_len = len; | |
5c468455 AM |
689 | |
690 | enable_irq(info->gpmc_irq_count); | |
691 | enable_irq(info->gpmc_irq_fifo); | |
4e070376 SG |
692 | |
693 | /* waiting for write to complete */ | |
694 | wait_for_completion(&info->comp); | |
5c468455 | 695 | |
4e070376 SG |
696 | /* wait for data to flushed-out before reset the prefetch */ |
697 | tim = 0; | |
698 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
65b97cf6 AM |
699 | do { |
700 | val = readl(info->reg.gpmc_prefetch_status); | |
47f88af4 | 701 | val = PREFETCH_STATUS_COUNT(val); |
4e070376 | 702 | cpu_relax(); |
65b97cf6 | 703 | } while (val && (tim++ < limit)); |
4e070376 SG |
704 | |
705 | /* disable and stop the PFPW engine */ | |
65b97cf6 | 706 | omap_prefetch_reset(info->gpmc_cs, info); |
4e070376 SG |
707 | return; |
708 | ||
709 | out_copy: | |
710 | if (info->nand.options & NAND_BUSWIDTH_16) | |
711 | omap_write_buf16(mtd, buf, len); | |
712 | else | |
713 | omap_write_buf8(mtd, buf, len); | |
714 | } | |
715 | ||
67ce04bf VS |
716 | /** |
717 | * gen_true_ecc - This function will generate true ECC value | |
718 | * @ecc_buf: buffer to store ecc code | |
719 | * | |
720 | * This generated true ECC value can be used when correcting | |
721 | * data read from NAND flash memory core | |
722 | */ | |
723 | static void gen_true_ecc(u8 *ecc_buf) | |
724 | { | |
725 | u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) | | |
726 | ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8); | |
727 | ||
728 | ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | | |
729 | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); | |
730 | ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | | |
731 | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); | |
732 | ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | | |
733 | P1e(tmp) | P2048o(tmp) | P2048e(tmp)); | |
734 | } | |
735 | ||
736 | /** | |
737 | * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data | |
738 | * @ecc_data1: ecc code from nand spare area | |
739 | * @ecc_data2: ecc code from hardware register obtained from hardware ecc | |
740 | * @page_data: page data | |
741 | * | |
742 | * This function compares two ECC's and indicates if there is an error. | |
743 | * If the error can be corrected it will be corrected to the buffer. | |
74f1b724 JO |
744 | * If there is no error, %0 is returned. If there is an error but it |
745 | * was corrected, %1 is returned. Otherwise, %-1 is returned. | |
67ce04bf VS |
746 | */ |
747 | static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */ | |
748 | u8 *ecc_data2, /* read from register */ | |
749 | u8 *page_data) | |
750 | { | |
751 | uint i; | |
752 | u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; | |
753 | u8 comp0_bit[8], comp1_bit[8], comp2_bit[8]; | |
754 | u8 ecc_bit[24]; | |
755 | u8 ecc_sum = 0; | |
756 | u8 find_bit = 0; | |
757 | uint find_byte = 0; | |
758 | int isEccFF; | |
759 | ||
760 | isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF); | |
761 | ||
762 | gen_true_ecc(ecc_data1); | |
763 | gen_true_ecc(ecc_data2); | |
764 | ||
765 | for (i = 0; i <= 2; i++) { | |
766 | *(ecc_data1 + i) = ~(*(ecc_data1 + i)); | |
767 | *(ecc_data2 + i) = ~(*(ecc_data2 + i)); | |
768 | } | |
769 | ||
770 | for (i = 0; i < 8; i++) { | |
771 | tmp0_bit[i] = *ecc_data1 % 2; | |
772 | *ecc_data1 = *ecc_data1 / 2; | |
773 | } | |
774 | ||
775 | for (i = 0; i < 8; i++) { | |
776 | tmp1_bit[i] = *(ecc_data1 + 1) % 2; | |
777 | *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2; | |
778 | } | |
779 | ||
780 | for (i = 0; i < 8; i++) { | |
781 | tmp2_bit[i] = *(ecc_data1 + 2) % 2; | |
782 | *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2; | |
783 | } | |
784 | ||
785 | for (i = 0; i < 8; i++) { | |
786 | comp0_bit[i] = *ecc_data2 % 2; | |
787 | *ecc_data2 = *ecc_data2 / 2; | |
788 | } | |
789 | ||
790 | for (i = 0; i < 8; i++) { | |
791 | comp1_bit[i] = *(ecc_data2 + 1) % 2; | |
792 | *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2; | |
793 | } | |
794 | ||
795 | for (i = 0; i < 8; i++) { | |
796 | comp2_bit[i] = *(ecc_data2 + 2) % 2; | |
797 | *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2; | |
798 | } | |
799 | ||
800 | for (i = 0; i < 6; i++) | |
801 | ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; | |
802 | ||
803 | for (i = 0; i < 8; i++) | |
804 | ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; | |
805 | ||
806 | for (i = 0; i < 8; i++) | |
807 | ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; | |
808 | ||
809 | ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; | |
810 | ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; | |
811 | ||
812 | for (i = 0; i < 24; i++) | |
813 | ecc_sum += ecc_bit[i]; | |
814 | ||
815 | switch (ecc_sum) { | |
816 | case 0: | |
817 | /* Not reached because this function is not called if | |
818 | * ECC values are equal | |
819 | */ | |
820 | return 0; | |
821 | ||
822 | case 1: | |
823 | /* Uncorrectable error */ | |
289c0522 | 824 | pr_debug("ECC UNCORRECTED_ERROR 1\n"); |
6e941192 | 825 | return -EBADMSG; |
67ce04bf VS |
826 | |
827 | case 11: | |
828 | /* UN-Correctable error */ | |
289c0522 | 829 | pr_debug("ECC UNCORRECTED_ERROR B\n"); |
6e941192 | 830 | return -EBADMSG; |
67ce04bf VS |
831 | |
832 | case 12: | |
833 | /* Correctable error */ | |
834 | find_byte = (ecc_bit[23] << 8) + | |
835 | (ecc_bit[21] << 7) + | |
836 | (ecc_bit[19] << 6) + | |
837 | (ecc_bit[17] << 5) + | |
838 | (ecc_bit[15] << 4) + | |
839 | (ecc_bit[13] << 3) + | |
840 | (ecc_bit[11] << 2) + | |
841 | (ecc_bit[9] << 1) + | |
842 | ecc_bit[7]; | |
843 | ||
844 | find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; | |
845 | ||
0a32a102 BN |
846 | pr_debug("Correcting single bit ECC error at offset: " |
847 | "%d, bit: %d\n", find_byte, find_bit); | |
67ce04bf VS |
848 | |
849 | page_data[find_byte] ^= (1 << find_bit); | |
850 | ||
74f1b724 | 851 | return 1; |
67ce04bf VS |
852 | default: |
853 | if (isEccFF) { | |
854 | if (ecc_data2[0] == 0 && | |
855 | ecc_data2[1] == 0 && | |
856 | ecc_data2[2] == 0) | |
857 | return 0; | |
858 | } | |
289c0522 | 859 | pr_debug("UNCORRECTED_ERROR default\n"); |
6e941192 | 860 | return -EBADMSG; |
67ce04bf VS |
861 | } |
862 | } | |
863 | ||
864 | /** | |
865 | * omap_correct_data - Compares the ECC read with HW generated ECC | |
866 | * @mtd: MTD device structure | |
867 | * @dat: page data | |
868 | * @read_ecc: ecc read from nand flash | |
869 | * @calc_ecc: ecc read from HW ECC registers | |
870 | * | |
871 | * Compares the ecc read from nand spare area with ECC registers values | |
74f1b724 JO |
872 | * and if ECC's mismatched, it will call 'omap_compare_ecc' for error |
873 | * detection and correction. If there are no errors, %0 is returned. If | |
874 | * there were errors and all of the errors were corrected, the number of | |
875 | * corrected errors is returned. If uncorrectable errors exist, %-1 is | |
876 | * returned. | |
67ce04bf VS |
877 | */ |
878 | static int omap_correct_data(struct mtd_info *mtd, u_char *dat, | |
879 | u_char *read_ecc, u_char *calc_ecc) | |
880 | { | |
4578ea9a | 881 | struct omap_nand_info *info = mtd_to_omap(mtd); |
67ce04bf | 882 | int blockCnt = 0, i = 0, ret = 0; |
74f1b724 | 883 | int stat = 0; |
67ce04bf VS |
884 | |
885 | /* Ex NAND_ECC_HW12_2048 */ | |
886 | if ((info->nand.ecc.mode == NAND_ECC_HW) && | |
887 | (info->nand.ecc.size == 2048)) | |
888 | blockCnt = 4; | |
889 | else | |
890 | blockCnt = 1; | |
891 | ||
892 | for (i = 0; i < blockCnt; i++) { | |
893 | if (memcmp(read_ecc, calc_ecc, 3) != 0) { | |
894 | ret = omap_compare_ecc(read_ecc, calc_ecc, dat); | |
895 | if (ret < 0) | |
896 | return ret; | |
74f1b724 JO |
897 | /* keep track of the number of corrected errors */ |
898 | stat += ret; | |
67ce04bf VS |
899 | } |
900 | read_ecc += 3; | |
901 | calc_ecc += 3; | |
902 | dat += 512; | |
903 | } | |
74f1b724 | 904 | return stat; |
67ce04bf VS |
905 | } |
906 | ||
907 | /** | |
908 | * omap_calcuate_ecc - Generate non-inverted ECC bytes. | |
909 | * @mtd: MTD device structure | |
910 | * @dat: The pointer to data on which ecc is computed | |
911 | * @ecc_code: The ecc_code buffer | |
912 | * | |
913 | * Using noninverted ECC can be considered ugly since writing a blank | |
914 | * page ie. padding will clear the ECC bytes. This is no problem as long | |
915 | * nobody is trying to write data on the seemingly unused page. Reading | |
916 | * an erased page will produce an ECC mismatch between generated and read | |
917 | * ECC bytes that has to be dealt with separately. | |
918 | */ | |
919 | static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, | |
920 | u_char *ecc_code) | |
921 | { | |
4578ea9a | 922 | struct omap_nand_info *info = mtd_to_omap(mtd); |
65b97cf6 AM |
923 | u32 val; |
924 | ||
925 | val = readl(info->reg.gpmc_ecc_config); | |
40ddbf50 | 926 | if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs) |
65b97cf6 AM |
927 | return -EINVAL; |
928 | ||
929 | /* read ecc result */ | |
930 | val = readl(info->reg.gpmc_ecc1_result); | |
931 | *ecc_code++ = val; /* P128e, ..., P1e */ | |
932 | *ecc_code++ = val >> 16; /* P128o, ..., P1o */ | |
933 | /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ | |
934 | *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); | |
935 | ||
936 | return 0; | |
67ce04bf VS |
937 | } |
938 | ||
939 | /** | |
940 | * omap_enable_hwecc - This function enables the hardware ecc functionality | |
941 | * @mtd: MTD device structure | |
942 | * @mode: Read/Write mode | |
943 | */ | |
944 | static void omap_enable_hwecc(struct mtd_info *mtd, int mode) | |
945 | { | |
4578ea9a | 946 | struct omap_nand_info *info = mtd_to_omap(mtd); |
4bd4ebcc | 947 | struct nand_chip *chip = mtd_to_nand(mtd); |
67ce04bf | 948 | unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; |
65b97cf6 AM |
949 | u32 val; |
950 | ||
951 | /* clear ecc and enable bits */ | |
952 | val = ECCCLEAR | ECC1; | |
953 | writel(val, info->reg.gpmc_ecc_control); | |
67ce04bf | 954 | |
65b97cf6 AM |
955 | /* program ecc and result sizes */ |
956 | val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) | | |
957 | ECC1RESULTSIZE); | |
958 | writel(val, info->reg.gpmc_ecc_size_config); | |
959 | ||
960 | switch (mode) { | |
961 | case NAND_ECC_READ: | |
962 | case NAND_ECC_WRITE: | |
963 | writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); | |
964 | break; | |
965 | case NAND_ECC_READSYN: | |
966 | writel(ECCCLEAR, info->reg.gpmc_ecc_control); | |
967 | break; | |
968 | default: | |
969 | dev_info(&info->pdev->dev, | |
970 | "error: unrecognized Mode[%d]!\n", mode); | |
971 | break; | |
972 | } | |
67ce04bf | 973 | |
65b97cf6 AM |
974 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ |
975 | val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); | |
976 | writel(val, info->reg.gpmc_ecc_config); | |
67ce04bf | 977 | } |
2c01946c | 978 | |
67ce04bf VS |
979 | /** |
980 | * omap_wait - wait until the command is done | |
981 | * @mtd: MTD device structure | |
982 | * @chip: NAND Chip structure | |
983 | * | |
984 | * Wait function is called during Program and erase operations and | |
985 | * the way it is called from MTD layer, we should wait till the NAND | |
986 | * chip is ready after the programming/erase operation has completed. | |
987 | * | |
988 | * Erase can take up to 400ms and program up to 20ms according to | |
989 | * general NAND and SmartMedia specs | |
990 | */ | |
991 | static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
992 | { | |
4bd4ebcc | 993 | struct nand_chip *this = mtd_to_nand(mtd); |
4578ea9a | 994 | struct omap_nand_info *info = mtd_to_omap(mtd); |
67ce04bf | 995 | unsigned long timeo = jiffies; |
a9c465f0 | 996 | int status, state = this->state; |
67ce04bf VS |
997 | |
998 | if (state == FL_ERASING) | |
4ff6772b | 999 | timeo += msecs_to_jiffies(400); |
67ce04bf | 1000 | else |
4ff6772b | 1001 | timeo += msecs_to_jiffies(20); |
67ce04bf | 1002 | |
65b97cf6 | 1003 | writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command); |
67ce04bf | 1004 | while (time_before(jiffies, timeo)) { |
65b97cf6 | 1005 | status = readb(info->reg.gpmc_nand_data); |
c276aca4 | 1006 | if (status & NAND_STATUS_READY) |
67ce04bf | 1007 | break; |
c276aca4 | 1008 | cond_resched(); |
67ce04bf | 1009 | } |
a9c465f0 | 1010 | |
4ea1e4ba | 1011 | status = readb(info->reg.gpmc_nand_data); |
67ce04bf VS |
1012 | return status; |
1013 | } | |
1014 | ||
1015 | /** | |
10f22ee3 | 1016 | * omap_dev_ready - checks the NAND Ready GPIO line |
67ce04bf | 1017 | * @mtd: MTD device structure |
10f22ee3 RQ |
1018 | * |
1019 | * Returns true if ready and false if busy. | |
67ce04bf VS |
1020 | */ |
1021 | static int omap_dev_ready(struct mtd_info *mtd) | |
1022 | { | |
4578ea9a | 1023 | struct omap_nand_info *info = mtd_to_omap(mtd); |
67ce04bf | 1024 | |
10f22ee3 | 1025 | return gpiod_get_value(info->ready_gpiod); |
67ce04bf VS |
1026 | } |
1027 | ||
0e618ef0 | 1028 | /** |
7c977c3e | 1029 | * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation |
0e618ef0 ID |
1030 | * @mtd: MTD device structure |
1031 | * @mode: Read/Write mode | |
62116e51 | 1032 | * |
0760e818 NMG |
1033 | * When using BCH with SW correction (i.e. no ELM), sector size is set |
1034 | * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode | |
1035 | * for both reading and writing with: | |
62116e51 PA |
1036 | * eccsize0 = 0 (no additional protected byte in spare area) |
1037 | * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) | |
0e618ef0 | 1038 | */ |
7c977c3e | 1039 | static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, int mode) |
0e618ef0 | 1040 | { |
16e69322 | 1041 | unsigned int bch_type; |
2ef9f3dd | 1042 | unsigned int dev_width, nsectors; |
4578ea9a | 1043 | struct omap_nand_info *info = mtd_to_omap(mtd); |
c5957a32 | 1044 | enum omap_ecc ecc_opt = info->ecc_opt; |
4bd4ebcc | 1045 | struct nand_chip *chip = mtd_to_nand(mtd); |
62116e51 PA |
1046 | u32 val, wr_mode; |
1047 | unsigned int ecc_size1, ecc_size0; | |
1048 | ||
c5957a32 PG |
1049 | /* GPMC configurations for calculating ECC */ |
1050 | switch (ecc_opt) { | |
1051 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: | |
16e69322 PG |
1052 | bch_type = 0; |
1053 | nsectors = 1; | |
0760e818 NMG |
1054 | wr_mode = BCH_WRAPMODE_6; |
1055 | ecc_size0 = BCH_ECC_SIZE0; | |
1056 | ecc_size1 = BCH_ECC_SIZE1; | |
c5957a32 PG |
1057 | break; |
1058 | case OMAP_ECC_BCH4_CODE_HW: | |
16e69322 PG |
1059 | bch_type = 0; |
1060 | nsectors = chip->ecc.steps; | |
c5957a32 PG |
1061 | if (mode == NAND_ECC_READ) { |
1062 | wr_mode = BCH_WRAPMODE_1; | |
1063 | ecc_size0 = BCH4R_ECC_SIZE0; | |
1064 | ecc_size1 = BCH4R_ECC_SIZE1; | |
1065 | } else { | |
1066 | wr_mode = BCH_WRAPMODE_6; | |
1067 | ecc_size0 = BCH_ECC_SIZE0; | |
1068 | ecc_size1 = BCH_ECC_SIZE1; | |
1069 | } | |
1070 | break; | |
1071 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
16e69322 PG |
1072 | bch_type = 1; |
1073 | nsectors = 1; | |
0760e818 NMG |
1074 | wr_mode = BCH_WRAPMODE_6; |
1075 | ecc_size0 = BCH_ECC_SIZE0; | |
1076 | ecc_size1 = BCH_ECC_SIZE1; | |
c5957a32 PG |
1077 | break; |
1078 | case OMAP_ECC_BCH8_CODE_HW: | |
16e69322 PG |
1079 | bch_type = 1; |
1080 | nsectors = chip->ecc.steps; | |
c5957a32 PG |
1081 | if (mode == NAND_ECC_READ) { |
1082 | wr_mode = BCH_WRAPMODE_1; | |
1083 | ecc_size0 = BCH8R_ECC_SIZE0; | |
1084 | ecc_size1 = BCH8R_ECC_SIZE1; | |
1085 | } else { | |
1086 | wr_mode = BCH_WRAPMODE_6; | |
1087 | ecc_size0 = BCH_ECC_SIZE0; | |
1088 | ecc_size1 = BCH_ECC_SIZE1; | |
1089 | } | |
1090 | break; | |
9748fff9 | 1091 | case OMAP_ECC_BCH16_CODE_HW: |
1092 | bch_type = 0x2; | |
1093 | nsectors = chip->ecc.steps; | |
1094 | if (mode == NAND_ECC_READ) { | |
1095 | wr_mode = 0x01; | |
1096 | ecc_size0 = 52; /* ECC bits in nibbles per sector */ | |
1097 | ecc_size1 = 0; /* non-ECC bits in nibbles per sector */ | |
1098 | } else { | |
1099 | wr_mode = 0x01; | |
1100 | ecc_size0 = 0; /* extra bits in nibbles per sector */ | |
1101 | ecc_size1 = 52; /* OOB bits in nibbles per sector */ | |
1102 | } | |
1103 | break; | |
c5957a32 PG |
1104 | default: |
1105 | return; | |
1106 | } | |
2ef9f3dd AM |
1107 | |
1108 | writel(ECC1, info->reg.gpmc_ecc_control); | |
1109 | ||
62116e51 PA |
1110 | /* Configure ecc size for BCH */ |
1111 | val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT); | |
2ef9f3dd AM |
1112 | writel(val, info->reg.gpmc_ecc_size_config); |
1113 | ||
62116e51 PA |
1114 | dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; |
1115 | ||
2ef9f3dd AM |
1116 | /* BCH configuration */ |
1117 | val = ((1 << 16) | /* enable BCH */ | |
16e69322 | 1118 | (bch_type << 12) | /* BCH4/BCH8/BCH16 */ |
62116e51 | 1119 | (wr_mode << 8) | /* wrap mode */ |
2ef9f3dd AM |
1120 | (dev_width << 7) | /* bus width */ |
1121 | (((nsectors-1) & 0x7) << 4) | /* number of sectors */ | |
1122 | (info->gpmc_cs << 1) | /* ECC CS */ | |
1123 | (0x1)); /* enable ECC */ | |
1124 | ||
1125 | writel(val, info->reg.gpmc_ecc_config); | |
1126 | ||
62116e51 | 1127 | /* Clear ecc and enable bits */ |
2ef9f3dd | 1128 | writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control); |
0e618ef0 | 1129 | } |
7c977c3e | 1130 | |
2c9f2365 | 1131 | static u8 bch4_polynomial[] = {0x28, 0x13, 0xcc, 0x39, 0x96, 0xac, 0x7f}; |
7bcd1dca PG |
1132 | static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2, |
1133 | 0x97, 0x79, 0xe5, 0x24, 0xb5}; | |
0e618ef0 | 1134 | |
62116e51 | 1135 | /** |
a4c7ca00 | 1136 | * omap_calculate_ecc_bch - Generate bytes of ECC bytes |
62116e51 PA |
1137 | * @mtd: MTD device structure |
1138 | * @dat: The pointer to data on which ecc is computed | |
1139 | * @ecc_code: The ecc_code buffer | |
1140 | * | |
1141 | * Support calculating of BCH4/8 ecc vectors for the page | |
1142 | */ | |
a4c7ca00 | 1143 | static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd, |
f5dc06fb | 1144 | const u_char *dat, u_char *ecc_calc) |
62116e51 | 1145 | { |
4578ea9a | 1146 | struct omap_nand_info *info = mtd_to_omap(mtd); |
f5dc06fb PG |
1147 | int eccbytes = info->nand.ecc.bytes; |
1148 | struct gpmc_nand_regs *gpmc_regs = &info->reg; | |
1149 | u8 *ecc_code; | |
62116e51 | 1150 | unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4; |
9748fff9 | 1151 | u32 val; |
2913aae5 | 1152 | int i, j; |
62116e51 PA |
1153 | |
1154 | nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1; | |
62116e51 | 1155 | for (i = 0; i < nsectors; i++) { |
f5dc06fb PG |
1156 | ecc_code = ecc_calc; |
1157 | switch (info->ecc_opt) { | |
7bcd1dca | 1158 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: |
f5dc06fb PG |
1159 | case OMAP_ECC_BCH8_CODE_HW: |
1160 | bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]); | |
1161 | bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]); | |
1162 | bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]); | |
1163 | bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]); | |
62116e51 PA |
1164 | *ecc_code++ = (bch_val4 & 0xFF); |
1165 | *ecc_code++ = ((bch_val3 >> 24) & 0xFF); | |
1166 | *ecc_code++ = ((bch_val3 >> 16) & 0xFF); | |
1167 | *ecc_code++ = ((bch_val3 >> 8) & 0xFF); | |
1168 | *ecc_code++ = (bch_val3 & 0xFF); | |
1169 | *ecc_code++ = ((bch_val2 >> 24) & 0xFF); | |
1170 | *ecc_code++ = ((bch_val2 >> 16) & 0xFF); | |
1171 | *ecc_code++ = ((bch_val2 >> 8) & 0xFF); | |
1172 | *ecc_code++ = (bch_val2 & 0xFF); | |
1173 | *ecc_code++ = ((bch_val1 >> 24) & 0xFF); | |
1174 | *ecc_code++ = ((bch_val1 >> 16) & 0xFF); | |
1175 | *ecc_code++ = ((bch_val1 >> 8) & 0xFF); | |
1176 | *ecc_code++ = (bch_val1 & 0xFF); | |
f5dc06fb | 1177 | break; |
2c9f2365 | 1178 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: |
f5dc06fb PG |
1179 | case OMAP_ECC_BCH4_CODE_HW: |
1180 | bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]); | |
1181 | bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]); | |
62116e51 PA |
1182 | *ecc_code++ = ((bch_val2 >> 12) & 0xFF); |
1183 | *ecc_code++ = ((bch_val2 >> 4) & 0xFF); | |
1184 | *ecc_code++ = ((bch_val2 & 0xF) << 4) | | |
1185 | ((bch_val1 >> 28) & 0xF); | |
1186 | *ecc_code++ = ((bch_val1 >> 20) & 0xFF); | |
1187 | *ecc_code++ = ((bch_val1 >> 12) & 0xFF); | |
1188 | *ecc_code++ = ((bch_val1 >> 4) & 0xFF); | |
1189 | *ecc_code++ = ((bch_val1 & 0xF) << 4); | |
f5dc06fb | 1190 | break; |
9748fff9 | 1191 | case OMAP_ECC_BCH16_CODE_HW: |
1192 | val = readl(gpmc_regs->gpmc_bch_result6[i]); | |
1193 | ecc_code[0] = ((val >> 8) & 0xFF); | |
1194 | ecc_code[1] = ((val >> 0) & 0xFF); | |
1195 | val = readl(gpmc_regs->gpmc_bch_result5[i]); | |
1196 | ecc_code[2] = ((val >> 24) & 0xFF); | |
1197 | ecc_code[3] = ((val >> 16) & 0xFF); | |
1198 | ecc_code[4] = ((val >> 8) & 0xFF); | |
1199 | ecc_code[5] = ((val >> 0) & 0xFF); | |
1200 | val = readl(gpmc_regs->gpmc_bch_result4[i]); | |
1201 | ecc_code[6] = ((val >> 24) & 0xFF); | |
1202 | ecc_code[7] = ((val >> 16) & 0xFF); | |
1203 | ecc_code[8] = ((val >> 8) & 0xFF); | |
1204 | ecc_code[9] = ((val >> 0) & 0xFF); | |
1205 | val = readl(gpmc_regs->gpmc_bch_result3[i]); | |
1206 | ecc_code[10] = ((val >> 24) & 0xFF); | |
1207 | ecc_code[11] = ((val >> 16) & 0xFF); | |
1208 | ecc_code[12] = ((val >> 8) & 0xFF); | |
1209 | ecc_code[13] = ((val >> 0) & 0xFF); | |
1210 | val = readl(gpmc_regs->gpmc_bch_result2[i]); | |
1211 | ecc_code[14] = ((val >> 24) & 0xFF); | |
1212 | ecc_code[15] = ((val >> 16) & 0xFF); | |
1213 | ecc_code[16] = ((val >> 8) & 0xFF); | |
1214 | ecc_code[17] = ((val >> 0) & 0xFF); | |
1215 | val = readl(gpmc_regs->gpmc_bch_result1[i]); | |
1216 | ecc_code[18] = ((val >> 24) & 0xFF); | |
1217 | ecc_code[19] = ((val >> 16) & 0xFF); | |
1218 | ecc_code[20] = ((val >> 8) & 0xFF); | |
1219 | ecc_code[21] = ((val >> 0) & 0xFF); | |
1220 | val = readl(gpmc_regs->gpmc_bch_result0[i]); | |
1221 | ecc_code[22] = ((val >> 24) & 0xFF); | |
1222 | ecc_code[23] = ((val >> 16) & 0xFF); | |
1223 | ecc_code[24] = ((val >> 8) & 0xFF); | |
1224 | ecc_code[25] = ((val >> 0) & 0xFF); | |
1225 | break; | |
f5dc06fb PG |
1226 | default: |
1227 | return -EINVAL; | |
62116e51 | 1228 | } |
f5dc06fb PG |
1229 | |
1230 | /* ECC scheme specific syndrome customizations */ | |
1231 | switch (info->ecc_opt) { | |
2c9f2365 PG |
1232 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: |
1233 | /* Add constant polynomial to remainder, so that | |
1234 | * ECC of blank pages results in 0x0 on reading back */ | |
2913aae5 TJ |
1235 | for (j = 0; j < eccbytes; j++) |
1236 | ecc_calc[j] ^= bch4_polynomial[j]; | |
2c9f2365 | 1237 | break; |
f5dc06fb PG |
1238 | case OMAP_ECC_BCH4_CODE_HW: |
1239 | /* Set 8th ECC byte as 0x0 for ROM compatibility */ | |
1240 | ecc_calc[eccbytes - 1] = 0x0; | |
1241 | break; | |
7bcd1dca PG |
1242 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: |
1243 | /* Add constant polynomial to remainder, so that | |
1244 | * ECC of blank pages results in 0x0 on reading back */ | |
2913aae5 TJ |
1245 | for (j = 0; j < eccbytes; j++) |
1246 | ecc_calc[j] ^= bch8_polynomial[j]; | |
7bcd1dca | 1247 | break; |
f5dc06fb PG |
1248 | case OMAP_ECC_BCH8_CODE_HW: |
1249 | /* Set 14th ECC byte as 0x0 for ROM compatibility */ | |
1250 | ecc_calc[eccbytes - 1] = 0x0; | |
1251 | break; | |
9748fff9 | 1252 | case OMAP_ECC_BCH16_CODE_HW: |
1253 | break; | |
f5dc06fb PG |
1254 | default: |
1255 | return -EINVAL; | |
1256 | } | |
1257 | ||
1258 | ecc_calc += eccbytes; | |
62116e51 PA |
1259 | } |
1260 | ||
1261 | return 0; | |
1262 | } | |
1263 | ||
1264 | /** | |
1265 | * erased_sector_bitflips - count bit flips | |
1266 | * @data: data sector buffer | |
1267 | * @oob: oob buffer | |
1268 | * @info: omap_nand_info | |
1269 | * | |
1270 | * Check the bit flips in erased page falls below correctable level. | |
1271 | * If falls below, report the page as erased with correctable bit | |
1272 | * flip, else report as uncorrectable page. | |
1273 | */ | |
1274 | static int erased_sector_bitflips(u_char *data, u_char *oob, | |
1275 | struct omap_nand_info *info) | |
1276 | { | |
1277 | int flip_bits = 0, i; | |
1278 | ||
1279 | for (i = 0; i < info->nand.ecc.size; i++) { | |
1280 | flip_bits += hweight8(~data[i]); | |
1281 | if (flip_bits > info->nand.ecc.strength) | |
1282 | return 0; | |
1283 | } | |
1284 | ||
1285 | for (i = 0; i < info->nand.ecc.bytes - 1; i++) { | |
1286 | flip_bits += hweight8(~oob[i]); | |
1287 | if (flip_bits > info->nand.ecc.strength) | |
1288 | return 0; | |
1289 | } | |
1290 | ||
1291 | /* | |
1292 | * Bit flips falls in correctable level. | |
1293 | * Fill data area with 0xFF | |
1294 | */ | |
1295 | if (flip_bits) { | |
1296 | memset(data, 0xFF, info->nand.ecc.size); | |
1297 | memset(oob, 0xFF, info->nand.ecc.bytes); | |
1298 | } | |
1299 | ||
1300 | return flip_bits; | |
1301 | } | |
1302 | ||
1303 | /** | |
1304 | * omap_elm_correct_data - corrects page data area in case error reported | |
1305 | * @mtd: MTD device structure | |
1306 | * @data: page data | |
1307 | * @read_ecc: ecc read from nand flash | |
1308 | * @calc_ecc: ecc read from HW ECC registers | |
1309 | * | |
1310 | * Calculated ecc vector reported as zero in case of non-error pages. | |
78f43c53 PG |
1311 | * In case of non-zero ecc vector, first filter out erased-pages, and |
1312 | * then process data via ELM to detect bit-flips. | |
62116e51 PA |
1313 | */ |
1314 | static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data, | |
1315 | u_char *read_ecc, u_char *calc_ecc) | |
1316 | { | |
4578ea9a | 1317 | struct omap_nand_info *info = mtd_to_omap(mtd); |
de0a4d69 | 1318 | struct nand_ecc_ctrl *ecc = &info->nand.ecc; |
62116e51 PA |
1319 | int eccsteps = info->nand.ecc.steps; |
1320 | int i , j, stat = 0; | |
de0a4d69 | 1321 | int eccflag, actual_eccbytes; |
62116e51 PA |
1322 | struct elm_errorvec err_vec[ERROR_VECTOR_MAX]; |
1323 | u_char *ecc_vec = calc_ecc; | |
1324 | u_char *spare_ecc = read_ecc; | |
1325 | u_char *erased_ecc_vec; | |
78f43c53 PG |
1326 | u_char *buf; |
1327 | int bitflip_count; | |
62116e51 | 1328 | bool is_error_reported = false; |
b08e1f63 | 1329 | u32 bit_pos, byte_pos, error_max, pos; |
13fbe064 | 1330 | int err; |
62116e51 | 1331 | |
de0a4d69 PG |
1332 | switch (info->ecc_opt) { |
1333 | case OMAP_ECC_BCH4_CODE_HW: | |
1334 | /* omit 7th ECC byte reserved for ROM code compatibility */ | |
1335 | actual_eccbytes = ecc->bytes - 1; | |
78f43c53 | 1336 | erased_ecc_vec = bch4_vector; |
de0a4d69 PG |
1337 | break; |
1338 | case OMAP_ECC_BCH8_CODE_HW: | |
1339 | /* omit 14th ECC byte reserved for ROM code compatibility */ | |
1340 | actual_eccbytes = ecc->bytes - 1; | |
78f43c53 | 1341 | erased_ecc_vec = bch8_vector; |
de0a4d69 | 1342 | break; |
9748fff9 | 1343 | case OMAP_ECC_BCH16_CODE_HW: |
1344 | actual_eccbytes = ecc->bytes; | |
1345 | erased_ecc_vec = bch16_vector; | |
1346 | break; | |
de0a4d69 | 1347 | default: |
d2f08c75 | 1348 | dev_err(&info->pdev->dev, "invalid driver configuration\n"); |
de0a4d69 PG |
1349 | return -EINVAL; |
1350 | } | |
1351 | ||
62116e51 PA |
1352 | /* Initialize elm error vector to zero */ |
1353 | memset(err_vec, 0, sizeof(err_vec)); | |
1354 | ||
62116e51 PA |
1355 | for (i = 0; i < eccsteps ; i++) { |
1356 | eccflag = 0; /* initialize eccflag */ | |
1357 | ||
1358 | /* | |
1359 | * Check any error reported, | |
1360 | * In case of error, non zero ecc reported. | |
1361 | */ | |
de0a4d69 | 1362 | for (j = 0; j < actual_eccbytes; j++) { |
62116e51 PA |
1363 | if (calc_ecc[j] != 0) { |
1364 | eccflag = 1; /* non zero ecc, error present */ | |
1365 | break; | |
1366 | } | |
1367 | } | |
1368 | ||
1369 | if (eccflag == 1) { | |
78f43c53 PG |
1370 | if (memcmp(calc_ecc, erased_ecc_vec, |
1371 | actual_eccbytes) == 0) { | |
62116e51 | 1372 | /* |
78f43c53 PG |
1373 | * calc_ecc[] matches pattern for ECC(all 0xff) |
1374 | * so this is definitely an erased-page | |
62116e51 | 1375 | */ |
62116e51 | 1376 | } else { |
78f43c53 PG |
1377 | buf = &data[info->nand.ecc.size * i]; |
1378 | /* | |
1379 | * count number of 0-bits in read_buf. | |
1380 | * This check can be removed once a similar | |
1381 | * check is introduced in generic NAND driver | |
1382 | */ | |
1383 | bitflip_count = erased_sector_bitflips( | |
1384 | buf, read_ecc, info); | |
1385 | if (bitflip_count) { | |
1386 | /* | |
1387 | * number of 0-bits within ECC limits | |
1388 | * So this may be an erased-page | |
1389 | */ | |
1390 | stat += bitflip_count; | |
1391 | } else { | |
1392 | /* | |
1393 | * Too many 0-bits. It may be a | |
1394 | * - programmed-page, OR | |
1395 | * - erased-page with many bit-flips | |
1396 | * So this page requires check by ELM | |
1397 | */ | |
1398 | err_vec[i].error_reported = true; | |
1399 | is_error_reported = true; | |
62116e51 PA |
1400 | } |
1401 | } | |
1402 | } | |
1403 | ||
1404 | /* Update the ecc vector */ | |
de0a4d69 PG |
1405 | calc_ecc += ecc->bytes; |
1406 | read_ecc += ecc->bytes; | |
62116e51 PA |
1407 | } |
1408 | ||
1409 | /* Check if any error reported */ | |
1410 | if (!is_error_reported) | |
f306e8c3 | 1411 | return stat; |
62116e51 PA |
1412 | |
1413 | /* Decode BCH error using ELM module */ | |
1414 | elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec); | |
1415 | ||
13fbe064 | 1416 | err = 0; |
62116e51 | 1417 | for (i = 0; i < eccsteps; i++) { |
13fbe064 | 1418 | if (err_vec[i].error_uncorrectable) { |
d2f08c75 EG |
1419 | dev_err(&info->pdev->dev, |
1420 | "uncorrectable bit-flips found\n"); | |
13fbe064 PG |
1421 | err = -EBADMSG; |
1422 | } else if (err_vec[i].error_reported) { | |
62116e51 | 1423 | for (j = 0; j < err_vec[i].error_count; j++) { |
b08e1f63 PG |
1424 | switch (info->ecc_opt) { |
1425 | case OMAP_ECC_BCH4_CODE_HW: | |
1426 | /* Add 4 bits to take care of padding */ | |
62116e51 PA |
1427 | pos = err_vec[i].error_loc[j] + |
1428 | BCH4_BIT_PAD; | |
b08e1f63 PG |
1429 | break; |
1430 | case OMAP_ECC_BCH8_CODE_HW: | |
9748fff9 | 1431 | case OMAP_ECC_BCH16_CODE_HW: |
b08e1f63 PG |
1432 | pos = err_vec[i].error_loc[j]; |
1433 | break; | |
1434 | default: | |
1435 | return -EINVAL; | |
1436 | } | |
1437 | error_max = (ecc->size + actual_eccbytes) * 8; | |
62116e51 PA |
1438 | /* Calculate bit position of error */ |
1439 | bit_pos = pos % 8; | |
1440 | ||
1441 | /* Calculate byte position of error */ | |
1442 | byte_pos = (error_max - pos - 1) / 8; | |
1443 | ||
1444 | if (pos < error_max) { | |
13fbe064 PG |
1445 | if (byte_pos < 512) { |
1446 | pr_debug("bitflip@dat[%d]=%x\n", | |
1447 | byte_pos, data[byte_pos]); | |
62116e51 | 1448 | data[byte_pos] ^= 1 << bit_pos; |
13fbe064 PG |
1449 | } else { |
1450 | pr_debug("bitflip@oob[%d]=%x\n", | |
1451 | (byte_pos - 512), | |
1452 | spare_ecc[byte_pos - 512]); | |
62116e51 PA |
1453 | spare_ecc[byte_pos - 512] ^= |
1454 | 1 << bit_pos; | |
13fbe064 PG |
1455 | } |
1456 | } else { | |
d2f08c75 EG |
1457 | dev_err(&info->pdev->dev, |
1458 | "invalid bit-flip @ %d:%d\n", | |
1459 | byte_pos, bit_pos); | |
13fbe064 | 1460 | err = -EBADMSG; |
62116e51 | 1461 | } |
62116e51 PA |
1462 | } |
1463 | } | |
1464 | ||
1465 | /* Update number of correctable errors */ | |
1466 | stat += err_vec[i].error_count; | |
1467 | ||
1468 | /* Update page data with sector size */ | |
b08e1f63 | 1469 | data += ecc->size; |
de0a4d69 | 1470 | spare_ecc += ecc->bytes; |
62116e51 PA |
1471 | } |
1472 | ||
13fbe064 | 1473 | return (err) ? err : stat; |
62116e51 PA |
1474 | } |
1475 | ||
62116e51 PA |
1476 | /** |
1477 | * omap_write_page_bch - BCH ecc based write page function for entire page | |
1478 | * @mtd: mtd info structure | |
1479 | * @chip: nand chip info structure | |
1480 | * @buf: data buffer | |
1481 | * @oob_required: must write chip->oob_poi to OOB | |
45aaeff9 | 1482 | * @page: page |
62116e51 PA |
1483 | * |
1484 | * Custom write page method evolved to support multi sector writing in one shot | |
1485 | */ | |
1486 | static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip, | |
45aaeff9 | 1487 | const uint8_t *buf, int oob_required, int page) |
62116e51 | 1488 | { |
8cfc1e8b | 1489 | int ret; |
62116e51 | 1490 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
62116e51 PA |
1491 | |
1492 | /* Enable GPMC ecc engine */ | |
1493 | chip->ecc.hwctl(mtd, NAND_ECC_WRITE); | |
1494 | ||
1495 | /* Write data */ | |
1496 | chip->write_buf(mtd, buf, mtd->writesize); | |
1497 | ||
1498 | /* Update ecc vector from GPMC result registers */ | |
1499 | chip->ecc.calculate(mtd, buf, &ecc_calc[0]); | |
1500 | ||
8cfc1e8b BB |
1501 | ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, |
1502 | chip->ecc.total); | |
1503 | if (ret) | |
1504 | return ret; | |
62116e51 PA |
1505 | |
1506 | /* Write ecc vector to OOB area */ | |
1507 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
1508 | return 0; | |
1509 | } | |
1510 | ||
1511 | /** | |
1512 | * omap_read_page_bch - BCH ecc based page read function for entire page | |
1513 | * @mtd: mtd info structure | |
1514 | * @chip: nand chip info structure | |
1515 | * @buf: buffer to store read data | |
1516 | * @oob_required: caller requires OOB data read to chip->oob_poi | |
1517 | * @page: page number to read | |
1518 | * | |
1519 | * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module | |
1520 | * used for error correction. | |
1521 | * Custom method evolved to support ELM error correction & multi sector | |
1522 | * reading. On reading page data area is read along with OOB data with | |
1523 | * ecc engine enabled. ecc vector updated after read of OOB data. | |
1524 | * For non error pages ecc vector reported as zero. | |
1525 | */ | |
1526 | static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, | |
1527 | uint8_t *buf, int oob_required, int page) | |
1528 | { | |
1529 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
1530 | uint8_t *ecc_code = chip->buffers->ecccode; | |
8cfc1e8b | 1531 | int stat, ret; |
62116e51 PA |
1532 | unsigned int max_bitflips = 0; |
1533 | ||
1534 | /* Enable GPMC ecc engine */ | |
1535 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
1536 | ||
1537 | /* Read data */ | |
1538 | chip->read_buf(mtd, buf, mtd->writesize); | |
1539 | ||
1540 | /* Read oob bytes */ | |
8cfc1e8b BB |
1541 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, |
1542 | mtd->writesize + BADBLOCK_MARKER_LENGTH, -1); | |
1543 | chip->read_buf(mtd, chip->oob_poi + BADBLOCK_MARKER_LENGTH, | |
1544 | chip->ecc.total); | |
62116e51 PA |
1545 | |
1546 | /* Calculate ecc bytes */ | |
1547 | chip->ecc.calculate(mtd, buf, ecc_calc); | |
1548 | ||
8cfc1e8b BB |
1549 | ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, |
1550 | chip->ecc.total); | |
1551 | if (ret) | |
1552 | return ret; | |
62116e51 PA |
1553 | |
1554 | stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc); | |
1555 | ||
1556 | if (stat < 0) { | |
1557 | mtd->ecc_stats.failed++; | |
1558 | } else { | |
1559 | mtd->ecc_stats.corrected += stat; | |
1560 | max_bitflips = max_t(unsigned int, max_bitflips, stat); | |
1561 | } | |
1562 | ||
1563 | return max_bitflips; | |
1564 | } | |
1565 | ||
0e618ef0 | 1566 | /** |
a919e511 PG |
1567 | * is_elm_present - checks for presence of ELM module by scanning DT nodes |
1568 | * @omap_nand_info: NAND device structure containing platform data | |
0e618ef0 | 1569 | */ |
93af53b8 EG |
1570 | static bool is_elm_present(struct omap_nand_info *info, |
1571 | struct device_node *elm_node) | |
0e618ef0 | 1572 | { |
a919e511 | 1573 | struct platform_device *pdev; |
93af53b8 | 1574 | |
a919e511 PG |
1575 | /* check whether elm-id is passed via DT */ |
1576 | if (!elm_node) { | |
d2f08c75 | 1577 | dev_err(&info->pdev->dev, "ELM devicetree node not found\n"); |
93af53b8 | 1578 | return false; |
a919e511 PG |
1579 | } |
1580 | pdev = of_find_device_by_node(elm_node); | |
1581 | /* check whether ELM device is registered */ | |
1582 | if (!pdev) { | |
d2f08c75 | 1583 | dev_err(&info->pdev->dev, "ELM device not found\n"); |
93af53b8 | 1584 | return false; |
0e618ef0 | 1585 | } |
a919e511 PG |
1586 | /* ELM module available, now configure it */ |
1587 | info->elm_dev = &pdev->dev; | |
93af53b8 EG |
1588 | return true; |
1589 | } | |
3f4eb14b | 1590 | |
93af53b8 EG |
1591 | static bool omap2_nand_ecc_check(struct omap_nand_info *info, |
1592 | struct omap_nand_platform_data *pdata) | |
1593 | { | |
1594 | bool ecc_needs_bch, ecc_needs_omap_bch, ecc_needs_elm; | |
1595 | ||
1596 | switch (info->ecc_opt) { | |
1597 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: | |
1598 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
1599 | ecc_needs_omap_bch = false; | |
1600 | ecc_needs_bch = true; | |
1601 | ecc_needs_elm = false; | |
1602 | break; | |
1603 | case OMAP_ECC_BCH4_CODE_HW: | |
1604 | case OMAP_ECC_BCH8_CODE_HW: | |
1605 | case OMAP_ECC_BCH16_CODE_HW: | |
1606 | ecc_needs_omap_bch = true; | |
1607 | ecc_needs_bch = false; | |
1608 | ecc_needs_elm = true; | |
1609 | break; | |
1610 | default: | |
1611 | ecc_needs_omap_bch = false; | |
1612 | ecc_needs_bch = false; | |
1613 | ecc_needs_elm = false; | |
1614 | break; | |
1615 | } | |
1616 | ||
1617 | if (ecc_needs_bch && !IS_ENABLED(CONFIG_MTD_NAND_ECC_BCH)) { | |
1618 | dev_err(&info->pdev->dev, | |
1619 | "CONFIG_MTD_NAND_ECC_BCH not enabled\n"); | |
1620 | return false; | |
1621 | } | |
1622 | if (ecc_needs_omap_bch && !IS_ENABLED(CONFIG_MTD_NAND_OMAP_BCH)) { | |
1623 | dev_err(&info->pdev->dev, | |
1624 | "CONFIG_MTD_NAND_OMAP_BCH not enabled\n"); | |
1625 | return false; | |
1626 | } | |
01b95fc6 | 1627 | if (ecc_needs_elm && !is_elm_present(info, info->elm_of_node)) { |
93af53b8 EG |
1628 | dev_err(&info->pdev->dev, "ELM not available\n"); |
1629 | return false; | |
1630 | } | |
1631 | ||
1632 | return true; | |
0e618ef0 ID |
1633 | } |
1634 | ||
c9711ec5 RQ |
1635 | static const char * const nand_xfer_types[] = { |
1636 | [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled", | |
1637 | [NAND_OMAP_POLLED] = "polled", | |
1638 | [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma", | |
1639 | [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq", | |
1640 | }; | |
1641 | ||
1642 | static int omap_get_dt_info(struct device *dev, struct omap_nand_info *info) | |
1643 | { | |
1644 | struct device_node *child = dev->of_node; | |
1645 | int i; | |
1646 | const char *s; | |
1647 | u32 cs; | |
1648 | ||
1649 | if (of_property_read_u32(child, "reg", &cs) < 0) { | |
1650 | dev_err(dev, "reg not found in DT\n"); | |
1651 | return -EINVAL; | |
1652 | } | |
1653 | ||
1654 | info->gpmc_cs = cs; | |
1655 | ||
1656 | /* detect availability of ELM module. Won't be present pre-OMAP4 */ | |
1657 | info->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0); | |
7ce9ea7e TR |
1658 | if (!info->elm_of_node) { |
1659 | info->elm_of_node = of_parse_phandle(child, "elm_id", 0); | |
1660 | if (!info->elm_of_node) | |
1661 | dev_dbg(dev, "ti,elm-id not in DT\n"); | |
1662 | } | |
c9711ec5 RQ |
1663 | |
1664 | /* select ecc-scheme for NAND */ | |
1665 | if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) { | |
1666 | dev_err(dev, "ti,nand-ecc-opt not found\n"); | |
1667 | return -EINVAL; | |
1668 | } | |
1669 | ||
1670 | if (!strcmp(s, "sw")) { | |
1671 | info->ecc_opt = OMAP_ECC_HAM1_CODE_SW; | |
1672 | } else if (!strcmp(s, "ham1") || | |
1673 | !strcmp(s, "hw") || !strcmp(s, "hw-romcode")) { | |
1674 | info->ecc_opt = OMAP_ECC_HAM1_CODE_HW; | |
1675 | } else if (!strcmp(s, "bch4")) { | |
1676 | if (info->elm_of_node) | |
1677 | info->ecc_opt = OMAP_ECC_BCH4_CODE_HW; | |
1678 | else | |
1679 | info->ecc_opt = OMAP_ECC_BCH4_CODE_HW_DETECTION_SW; | |
1680 | } else if (!strcmp(s, "bch8")) { | |
1681 | if (info->elm_of_node) | |
1682 | info->ecc_opt = OMAP_ECC_BCH8_CODE_HW; | |
1683 | else | |
1684 | info->ecc_opt = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW; | |
1685 | } else if (!strcmp(s, "bch16")) { | |
1686 | info->ecc_opt = OMAP_ECC_BCH16_CODE_HW; | |
1687 | } else { | |
1688 | dev_err(dev, "unrecognized value for ti,nand-ecc-opt\n"); | |
1689 | return -EINVAL; | |
1690 | } | |
1691 | ||
1692 | /* select data transfer mode */ | |
1693 | if (!of_property_read_string(child, "ti,nand-xfer-type", &s)) { | |
1694 | for (i = 0; i < ARRAY_SIZE(nand_xfer_types); i++) { | |
1695 | if (!strcasecmp(s, nand_xfer_types[i])) { | |
1696 | info->xfer_type = i; | |
f679888f | 1697 | return 0; |
c9711ec5 RQ |
1698 | } |
1699 | } | |
1700 | ||
1701 | dev_err(dev, "unrecognized value for ti,nand-xfer-type\n"); | |
1702 | return -EINVAL; | |
1703 | } | |
1704 | ||
c9711ec5 RQ |
1705 | return 0; |
1706 | } | |
1707 | ||
e04dbf35 BB |
1708 | static int omap_ooblayout_ecc(struct mtd_info *mtd, int section, |
1709 | struct mtd_oob_region *oobregion) | |
1710 | { | |
1711 | struct omap_nand_info *info = mtd_to_omap(mtd); | |
1712 | struct nand_chip *chip = &info->nand; | |
1713 | int off = BADBLOCK_MARKER_LENGTH; | |
1714 | ||
1715 | if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW && | |
1716 | !(chip->options & NAND_BUSWIDTH_16)) | |
1717 | off = 1; | |
1718 | ||
1719 | if (section) | |
1720 | return -ERANGE; | |
1721 | ||
1722 | oobregion->offset = off; | |
1723 | oobregion->length = chip->ecc.total; | |
1724 | ||
1725 | return 0; | |
1726 | } | |
1727 | ||
1728 | static int omap_ooblayout_free(struct mtd_info *mtd, int section, | |
1729 | struct mtd_oob_region *oobregion) | |
1730 | { | |
1731 | struct omap_nand_info *info = mtd_to_omap(mtd); | |
1732 | struct nand_chip *chip = &info->nand; | |
1733 | int off = BADBLOCK_MARKER_LENGTH; | |
1734 | ||
1735 | if (info->ecc_opt == OMAP_ECC_HAM1_CODE_HW && | |
1736 | !(chip->options & NAND_BUSWIDTH_16)) | |
1737 | off = 1; | |
1738 | ||
1739 | if (section) | |
1740 | return -ERANGE; | |
1741 | ||
1742 | off += chip->ecc.total; | |
1743 | if (off >= mtd->oobsize) | |
1744 | return -ERANGE; | |
1745 | ||
1746 | oobregion->offset = off; | |
1747 | oobregion->length = mtd->oobsize - off; | |
1748 | ||
1749 | return 0; | |
1750 | } | |
1751 | ||
1752 | static const struct mtd_ooblayout_ops omap_ooblayout_ops = { | |
1753 | .ecc = omap_ooblayout_ecc, | |
1754 | .free = omap_ooblayout_free, | |
1755 | }; | |
1756 | ||
1757 | static int omap_sw_ooblayout_ecc(struct mtd_info *mtd, int section, | |
1758 | struct mtd_oob_region *oobregion) | |
1759 | { | |
1760 | struct nand_chip *chip = mtd_to_nand(mtd); | |
1761 | int off = BADBLOCK_MARKER_LENGTH; | |
1762 | ||
1763 | if (section >= chip->ecc.steps) | |
1764 | return -ERANGE; | |
1765 | ||
1766 | /* | |
1767 | * When SW correction is employed, one OMAP specific marker byte is | |
1768 | * reserved after each ECC step. | |
1769 | */ | |
1770 | oobregion->offset = off + (section * (chip->ecc.bytes + 1)); | |
1771 | oobregion->length = chip->ecc.bytes; | |
1772 | ||
1773 | return 0; | |
1774 | } | |
1775 | ||
1776 | static int omap_sw_ooblayout_free(struct mtd_info *mtd, int section, | |
1777 | struct mtd_oob_region *oobregion) | |
1778 | { | |
1779 | struct nand_chip *chip = mtd_to_nand(mtd); | |
1780 | int off = BADBLOCK_MARKER_LENGTH; | |
1781 | ||
1782 | if (section) | |
1783 | return -ERANGE; | |
1784 | ||
1785 | /* | |
1786 | * When SW correction is employed, one OMAP specific marker byte is | |
1787 | * reserved after each ECC step. | |
1788 | */ | |
1789 | off += ((chip->ecc.bytes + 1) * chip->ecc.steps); | |
1790 | if (off >= mtd->oobsize) | |
1791 | return -ERANGE; | |
1792 | ||
1793 | oobregion->offset = off; | |
1794 | oobregion->length = mtd->oobsize - off; | |
1795 | ||
1796 | return 0; | |
1797 | } | |
1798 | ||
1799 | static const struct mtd_ooblayout_ops omap_sw_ooblayout_ops = { | |
1800 | .ecc = omap_sw_ooblayout_ecc, | |
1801 | .free = omap_sw_ooblayout_free, | |
1802 | }; | |
1803 | ||
06f25510 | 1804 | static int omap_nand_probe(struct platform_device *pdev) |
67ce04bf VS |
1805 | { |
1806 | struct omap_nand_info *info; | |
c9711ec5 | 1807 | struct omap_nand_platform_data *pdata = NULL; |
633deb58 PG |
1808 | struct mtd_info *mtd; |
1809 | struct nand_chip *nand_chip; | |
67ce04bf | 1810 | int err; |
633deb58 | 1811 | dma_cap_mask_t mask; |
9c4c2f8b | 1812 | struct resource *res; |
c9711ec5 | 1813 | struct device *dev = &pdev->dev; |
e04dbf35 BB |
1814 | int min_oobbytes = BADBLOCK_MARKER_LENGTH; |
1815 | int oobbytes_per_step; | |
67ce04bf | 1816 | |
70ba6d71 PG |
1817 | info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info), |
1818 | GFP_KERNEL); | |
67ce04bf VS |
1819 | if (!info) |
1820 | return -ENOMEM; | |
1821 | ||
c9711ec5 | 1822 | info->pdev = pdev; |
67ce04bf | 1823 | |
c9711ec5 RQ |
1824 | if (dev->of_node) { |
1825 | if (omap_get_dt_info(dev, info)) | |
1826 | return -EINVAL; | |
1827 | } else { | |
1828 | pdata = dev_get_platdata(&pdev->dev); | |
1829 | if (!pdata) { | |
1830 | dev_err(&pdev->dev, "platform data missing\n"); | |
1831 | return -EINVAL; | |
1832 | } | |
1833 | ||
1834 | info->gpmc_cs = pdata->cs; | |
1835 | info->reg = pdata->reg; | |
1836 | info->ecc_opt = pdata->ecc_opt; | |
10f22ee3 RQ |
1837 | if (pdata->dev_ready) |
1838 | dev_info(&pdev->dev, "pdata->dev_ready is deprecated\n"); | |
1839 | ||
c9711ec5 RQ |
1840 | info->xfer_type = pdata->xfer_type; |
1841 | info->devsize = pdata->devsize; | |
1842 | info->elm_of_node = pdata->elm_of_node; | |
1843 | info->flash_bbt = pdata->flash_bbt; | |
1844 | } | |
1845 | ||
1846 | platform_set_drvdata(pdev, info); | |
c509aefd RQ |
1847 | info->ops = gpmc_omap_get_nand_ops(&info->reg, info->gpmc_cs); |
1848 | if (!info->ops) { | |
1849 | dev_err(&pdev->dev, "Failed to get GPMC->NAND interface\n"); | |
1850 | return -ENODEV; | |
1851 | } | |
01b95fc6 | 1852 | |
432420c0 BB |
1853 | nand_chip = &info->nand; |
1854 | mtd = nand_to_mtd(nand_chip); | |
853f1c58 | 1855 | mtd->dev.parent = &pdev->dev; |
32d42a85 | 1856 | nand_chip->ecc.priv = NULL; |
c9711ec5 | 1857 | nand_set_flash_node(nand_chip, dev->of_node); |
67ce04bf | 1858 | |
2d283ede RQ |
1859 | if (!mtd->name) { |
1860 | mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, | |
1861 | "omap2-nand.%d", info->gpmc_cs); | |
1862 | if (!mtd->name) { | |
1863 | dev_err(&pdev->dev, "Failed to set MTD name\n"); | |
1864 | return -ENOMEM; | |
1865 | } | |
1866 | } | |
1867 | ||
9c4c2f8b | 1868 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
00d09891 JH |
1869 | nand_chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res); |
1870 | if (IS_ERR(nand_chip->IO_ADDR_R)) | |
1871 | return PTR_ERR(nand_chip->IO_ADDR_R); | |
67ce04bf | 1872 | |
9c4c2f8b | 1873 | info->phys_base = res->start; |
59e9c5ae | 1874 | |
1dc338e8 | 1875 | nand_chip->controller = &omap_gpmc_controller; |
67ce04bf | 1876 | |
633deb58 PG |
1877 | nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R; |
1878 | nand_chip->cmd_ctrl = omap_hwcontrol; | |
67ce04bf | 1879 | |
10f22ee3 RQ |
1880 | info->ready_gpiod = devm_gpiod_get_optional(&pdev->dev, "rb", |
1881 | GPIOD_IN); | |
1882 | if (IS_ERR(info->ready_gpiod)) { | |
1883 | dev_err(dev, "failed to get ready gpio\n"); | |
1884 | return PTR_ERR(info->ready_gpiod); | |
1885 | } | |
1886 | ||
67ce04bf VS |
1887 | /* |
1888 | * If RDY/BSY line is connected to OMAP then use the omap ready | |
4cacbe22 PM |
1889 | * function and the generic nand_wait function which reads the status |
1890 | * register after monitoring the RDY/BSY line. Otherwise use a standard | |
67ce04bf VS |
1891 | * chip delay which is slightly more than tR (AC Timing) of the NAND |
1892 | * device and read status register until you get a failure or success | |
1893 | */ | |
10f22ee3 | 1894 | if (info->ready_gpiod) { |
633deb58 PG |
1895 | nand_chip->dev_ready = omap_dev_ready; |
1896 | nand_chip->chip_delay = 0; | |
67ce04bf | 1897 | } else { |
633deb58 PG |
1898 | nand_chip->waitfunc = omap_wait; |
1899 | nand_chip->chip_delay = 50; | |
67ce04bf VS |
1900 | } |
1901 | ||
c9711ec5 | 1902 | if (info->flash_bbt) |
f679888f | 1903 | nand_chip->bbt_options |= NAND_BBT_USE_FLASH; |
fef775ca | 1904 | |
f18befb5 | 1905 | /* scan NAND device connected to chip controller */ |
01b95fc6 | 1906 | nand_chip->options |= info->devsize & NAND_BUSWIDTH_16; |
bd93a3af MY |
1907 | err = nand_scan_ident(mtd, 1, NULL); |
1908 | if (err) { | |
01b95fc6 RQ |
1909 | dev_err(&info->pdev->dev, |
1910 | "scan failed, may be bus-width mismatch\n"); | |
70ba6d71 | 1911 | goto return_error; |
f18befb5 PG |
1912 | } |
1913 | ||
f679888f BB |
1914 | if (nand_chip->bbt_options & NAND_BBT_USE_FLASH) |
1915 | nand_chip->bbt_options |= NAND_BBT_NO_OOB; | |
1916 | else | |
1917 | nand_chip->options |= NAND_SKIP_BBTSCAN; | |
1918 | ||
f18befb5 | 1919 | /* re-populate low-level callbacks based on xfer modes */ |
01b95fc6 | 1920 | switch (info->xfer_type) { |
1b0b323c | 1921 | case NAND_OMAP_PREFETCH_POLLED: |
633deb58 PG |
1922 | nand_chip->read_buf = omap_read_buf_pref; |
1923 | nand_chip->write_buf = omap_write_buf_pref; | |
1b0b323c SG |
1924 | break; |
1925 | ||
1926 | case NAND_OMAP_POLLED: | |
cf0e4d2b | 1927 | /* Use nand_base defaults for {read,write}_buf */ |
1b0b323c SG |
1928 | break; |
1929 | ||
1930 | case NAND_OMAP_PREFETCH_DMA: | |
763e7359 RK |
1931 | dma_cap_zero(mask); |
1932 | dma_cap_set(DMA_SLAVE, mask); | |
aa7abd31 CJF |
1933 | info->dma = dma_request_chan(pdev->dev.parent, "rxtx"); |
1934 | ||
de3bfc4a | 1935 | if (IS_ERR(info->dma)) { |
2df41d05 | 1936 | dev_err(&pdev->dev, "DMA engine request failed\n"); |
de3bfc4a | 1937 | err = PTR_ERR(info->dma); |
70ba6d71 | 1938 | goto return_error; |
763e7359 RK |
1939 | } else { |
1940 | struct dma_slave_config cfg; | |
763e7359 RK |
1941 | |
1942 | memset(&cfg, 0, sizeof(cfg)); | |
1943 | cfg.src_addr = info->phys_base; | |
1944 | cfg.dst_addr = info->phys_base; | |
1945 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1946 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1947 | cfg.src_maxburst = 16; | |
1948 | cfg.dst_maxburst = 16; | |
d680e2c1 AB |
1949 | err = dmaengine_slave_config(info->dma, &cfg); |
1950 | if (err) { | |
763e7359 | 1951 | dev_err(&pdev->dev, "DMA engine slave config failed: %d\n", |
d680e2c1 | 1952 | err); |
70ba6d71 | 1953 | goto return_error; |
763e7359 | 1954 | } |
633deb58 PG |
1955 | nand_chip->read_buf = omap_read_buf_dma_pref; |
1956 | nand_chip->write_buf = omap_write_buf_dma_pref; | |
1b0b323c SG |
1957 | } |
1958 | break; | |
1959 | ||
4e070376 | 1960 | case NAND_OMAP_PREFETCH_IRQ: |
5c468455 AM |
1961 | info->gpmc_irq_fifo = platform_get_irq(pdev, 0); |
1962 | if (info->gpmc_irq_fifo <= 0) { | |
1963 | dev_err(&pdev->dev, "error getting fifo irq\n"); | |
1964 | err = -ENODEV; | |
70ba6d71 | 1965 | goto return_error; |
5c468455 | 1966 | } |
70ba6d71 PG |
1967 | err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo, |
1968 | omap_nand_irq, IRQF_SHARED, | |
1969 | "gpmc-nand-fifo", info); | |
4e070376 SG |
1970 | if (err) { |
1971 | dev_err(&pdev->dev, "requesting irq(%d) error:%d", | |
5c468455 AM |
1972 | info->gpmc_irq_fifo, err); |
1973 | info->gpmc_irq_fifo = 0; | |
70ba6d71 | 1974 | goto return_error; |
5c468455 AM |
1975 | } |
1976 | ||
1977 | info->gpmc_irq_count = platform_get_irq(pdev, 1); | |
1978 | if (info->gpmc_irq_count <= 0) { | |
1979 | dev_err(&pdev->dev, "error getting count irq\n"); | |
1980 | err = -ENODEV; | |
70ba6d71 | 1981 | goto return_error; |
5c468455 | 1982 | } |
70ba6d71 PG |
1983 | err = devm_request_irq(&pdev->dev, info->gpmc_irq_count, |
1984 | omap_nand_irq, IRQF_SHARED, | |
1985 | "gpmc-nand-count", info); | |
5c468455 AM |
1986 | if (err) { |
1987 | dev_err(&pdev->dev, "requesting irq(%d) error:%d", | |
1988 | info->gpmc_irq_count, err); | |
1989 | info->gpmc_irq_count = 0; | |
70ba6d71 | 1990 | goto return_error; |
4e070376 | 1991 | } |
5c468455 | 1992 | |
633deb58 PG |
1993 | nand_chip->read_buf = omap_read_buf_irq_pref; |
1994 | nand_chip->write_buf = omap_write_buf_irq_pref; | |
5c468455 | 1995 | |
4e070376 SG |
1996 | break; |
1997 | ||
1b0b323c SG |
1998 | default: |
1999 | dev_err(&pdev->dev, | |
01b95fc6 | 2000 | "xfer_type(%d) not supported!\n", info->xfer_type); |
1b0b323c | 2001 | err = -EINVAL; |
70ba6d71 | 2002 | goto return_error; |
59e9c5ae | 2003 | } |
59e9c5ae | 2004 | |
93af53b8 EG |
2005 | if (!omap2_nand_ecc_check(info, pdata)) { |
2006 | err = -EINVAL; | |
2007 | goto return_error; | |
2008 | } | |
2009 | ||
a8c65d50 BB |
2010 | /* |
2011 | * Bail out earlier to let NAND_ECC_SOFT code create its own | |
e04dbf35 | 2012 | * ooblayout instead of using ours. |
a8c65d50 BB |
2013 | */ |
2014 | if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) { | |
2015 | nand_chip->ecc.mode = NAND_ECC_SOFT; | |
d7b83b8a | 2016 | nand_chip->ecc.algo = NAND_ECC_HAMMING; |
a8c65d50 BB |
2017 | goto scan_tail; |
2018 | } | |
2019 | ||
a919e511 | 2020 | /* populate MTD interface based on ECC scheme */ |
4e558072 | 2021 | switch (info->ecc_opt) { |
a919e511 PG |
2022 | case OMAP_ECC_HAM1_CODE_HW: |
2023 | pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n"); | |
2024 | nand_chip->ecc.mode = NAND_ECC_HW; | |
633deb58 PG |
2025 | nand_chip->ecc.bytes = 3; |
2026 | nand_chip->ecc.size = 512; | |
2027 | nand_chip->ecc.strength = 1; | |
2028 | nand_chip->ecc.calculate = omap_calculate_ecc; | |
2029 | nand_chip->ecc.hwctl = omap_enable_hwecc; | |
2030 | nand_chip->ecc.correct = omap_correct_data; | |
e04dbf35 BB |
2031 | mtd_set_ooblayout(mtd, &omap_ooblayout_ops); |
2032 | oobbytes_per_step = nand_chip->ecc.bytes; | |
2033 | ||
2034 | if (!(nand_chip->options & NAND_BUSWIDTH_16)) | |
2035 | min_oobbytes = 1; | |
2036 | ||
a919e511 PG |
2037 | break; |
2038 | ||
2039 | case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: | |
a919e511 PG |
2040 | pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n"); |
2041 | nand_chip->ecc.mode = NAND_ECC_HW; | |
2042 | nand_chip->ecc.size = 512; | |
2043 | nand_chip->ecc.bytes = 7; | |
2044 | nand_chip->ecc.strength = 4; | |
7c977c3e | 2045 | nand_chip->ecc.hwctl = omap_enable_hwecc_bch; |
32d42a85 | 2046 | nand_chip->ecc.correct = nand_bch_correct_data; |
2c9f2365 | 2047 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; |
e04dbf35 BB |
2048 | mtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops); |
2049 | /* Reserve one byte for the OMAP marker */ | |
2050 | oobbytes_per_step = nand_chip->ecc.bytes + 1; | |
a919e511 | 2051 | /* software bch library is used for locating errors */ |
a8c65d50 | 2052 | nand_chip->ecc.priv = nand_bch_init(mtd); |
32d42a85 | 2053 | if (!nand_chip->ecc.priv) { |
d2f08c75 | 2054 | dev_err(&info->pdev->dev, "unable to use BCH library\n"); |
0e618ef0 | 2055 | err = -EINVAL; |
d2f08c75 | 2056 | goto return_error; |
a919e511 PG |
2057 | } |
2058 | break; | |
a919e511 PG |
2059 | |
2060 | case OMAP_ECC_BCH4_CODE_HW: | |
a919e511 PG |
2061 | pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n"); |
2062 | nand_chip->ecc.mode = NAND_ECC_HW; | |
2063 | nand_chip->ecc.size = 512; | |
2064 | /* 14th bit is kept reserved for ROM-code compatibility */ | |
2065 | nand_chip->ecc.bytes = 7 + 1; | |
2066 | nand_chip->ecc.strength = 4; | |
7c977c3e | 2067 | nand_chip->ecc.hwctl = omap_enable_hwecc_bch; |
a919e511 | 2068 | nand_chip->ecc.correct = omap_elm_correct_data; |
a4c7ca00 | 2069 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; |
a919e511 PG |
2070 | nand_chip->ecc.read_page = omap_read_page_bch; |
2071 | nand_chip->ecc.write_page = omap_write_page_bch; | |
e04dbf35 BB |
2072 | mtd_set_ooblayout(mtd, &omap_ooblayout_ops); |
2073 | oobbytes_per_step = nand_chip->ecc.bytes; | |
93af53b8 EG |
2074 | |
2075 | err = elm_config(info->elm_dev, BCH4_ECC, | |
432420c0 | 2076 | mtd->writesize / nand_chip->ecc.size, |
93af53b8 EG |
2077 | nand_chip->ecc.size, nand_chip->ecc.bytes); |
2078 | if (err < 0) | |
70ba6d71 | 2079 | goto return_error; |
a919e511 | 2080 | break; |
a919e511 PG |
2081 | |
2082 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
a919e511 PG |
2083 | pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n"); |
2084 | nand_chip->ecc.mode = NAND_ECC_HW; | |
2085 | nand_chip->ecc.size = 512; | |
2086 | nand_chip->ecc.bytes = 13; | |
2087 | nand_chip->ecc.strength = 8; | |
7c977c3e | 2088 | nand_chip->ecc.hwctl = omap_enable_hwecc_bch; |
32d42a85 | 2089 | nand_chip->ecc.correct = nand_bch_correct_data; |
7bcd1dca | 2090 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; |
e04dbf35 BB |
2091 | mtd_set_ooblayout(mtd, &omap_sw_ooblayout_ops); |
2092 | /* Reserve one byte for the OMAP marker */ | |
2093 | oobbytes_per_step = nand_chip->ecc.bytes + 1; | |
a919e511 | 2094 | /* software bch library is used for locating errors */ |
a8c65d50 | 2095 | nand_chip->ecc.priv = nand_bch_init(mtd); |
32d42a85 | 2096 | if (!nand_chip->ecc.priv) { |
d2f08c75 | 2097 | dev_err(&info->pdev->dev, "unable to use BCH library\n"); |
a919e511 | 2098 | err = -EINVAL; |
70ba6d71 | 2099 | goto return_error; |
a919e511 PG |
2100 | } |
2101 | break; | |
a919e511 PG |
2102 | |
2103 | case OMAP_ECC_BCH8_CODE_HW: | |
a919e511 PG |
2104 | pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n"); |
2105 | nand_chip->ecc.mode = NAND_ECC_HW; | |
2106 | nand_chip->ecc.size = 512; | |
2107 | /* 14th bit is kept reserved for ROM-code compatibility */ | |
2108 | nand_chip->ecc.bytes = 13 + 1; | |
2109 | nand_chip->ecc.strength = 8; | |
7c977c3e | 2110 | nand_chip->ecc.hwctl = omap_enable_hwecc_bch; |
a919e511 | 2111 | nand_chip->ecc.correct = omap_elm_correct_data; |
a4c7ca00 | 2112 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; |
a919e511 PG |
2113 | nand_chip->ecc.read_page = omap_read_page_bch; |
2114 | nand_chip->ecc.write_page = omap_write_page_bch; | |
e04dbf35 BB |
2115 | mtd_set_ooblayout(mtd, &omap_ooblayout_ops); |
2116 | oobbytes_per_step = nand_chip->ecc.bytes; | |
93af53b8 EG |
2117 | |
2118 | err = elm_config(info->elm_dev, BCH8_ECC, | |
432420c0 | 2119 | mtd->writesize / nand_chip->ecc.size, |
93af53b8 EG |
2120 | nand_chip->ecc.size, nand_chip->ecc.bytes); |
2121 | if (err < 0) | |
70ba6d71 | 2122 | goto return_error; |
93af53b8 | 2123 | |
a919e511 | 2124 | break; |
a919e511 | 2125 | |
9748fff9 | 2126 | case OMAP_ECC_BCH16_CODE_HW: |
9748fff9 | 2127 | pr_info("using OMAP_ECC_BCH16_CODE_HW ECC scheme\n"); |
2128 | nand_chip->ecc.mode = NAND_ECC_HW; | |
2129 | nand_chip->ecc.size = 512; | |
2130 | nand_chip->ecc.bytes = 26; | |
2131 | nand_chip->ecc.strength = 16; | |
2132 | nand_chip->ecc.hwctl = omap_enable_hwecc_bch; | |
2133 | nand_chip->ecc.correct = omap_elm_correct_data; | |
2134 | nand_chip->ecc.calculate = omap_calculate_ecc_bch; | |
2135 | nand_chip->ecc.read_page = omap_read_page_bch; | |
2136 | nand_chip->ecc.write_page = omap_write_page_bch; | |
e04dbf35 BB |
2137 | mtd_set_ooblayout(mtd, &omap_ooblayout_ops); |
2138 | oobbytes_per_step = nand_chip->ecc.bytes; | |
93af53b8 EG |
2139 | |
2140 | err = elm_config(info->elm_dev, BCH16_ECC, | |
432420c0 | 2141 | mtd->writesize / nand_chip->ecc.size, |
93af53b8 EG |
2142 | nand_chip->ecc.size, nand_chip->ecc.bytes); |
2143 | if (err < 0) | |
9748fff9 | 2144 | goto return_error; |
93af53b8 | 2145 | |
9748fff9 | 2146 | break; |
a919e511 | 2147 | default: |
d2f08c75 | 2148 | dev_err(&info->pdev->dev, "invalid or unsupported ECC scheme\n"); |
a919e511 | 2149 | err = -EINVAL; |
70ba6d71 | 2150 | goto return_error; |
f3d73f36 | 2151 | } |
67ce04bf | 2152 | |
b491da72 | 2153 | /* check if NAND device's OOB is enough to store ECC signatures */ |
e04dbf35 BB |
2154 | min_oobbytes += (oobbytes_per_step * |
2155 | (mtd->writesize / nand_chip->ecc.size)); | |
2156 | if (mtd->oobsize < min_oobbytes) { | |
d2f08c75 EG |
2157 | dev_err(&info->pdev->dev, |
2158 | "not enough OOB bytes required = %d, available=%d\n", | |
e04dbf35 | 2159 | min_oobbytes, mtd->oobsize); |
b491da72 | 2160 | err = -EINVAL; |
70ba6d71 | 2161 | goto return_error; |
f040d332 | 2162 | } |
1b0b323c | 2163 | |
7d5929c1 | 2164 | scan_tail: |
a80f1c1f | 2165 | /* second phase scan */ |
bd93a3af MY |
2166 | err = nand_scan_tail(mtd); |
2167 | if (err) | |
70ba6d71 | 2168 | goto return_error; |
a80f1c1f | 2169 | |
c9711ec5 RQ |
2170 | if (dev->of_node) |
2171 | mtd_device_register(mtd, NULL, 0); | |
2172 | else | |
2173 | mtd_device_register(mtd, pdata->parts, pdata->nr_parts); | |
67ce04bf | 2174 | |
633deb58 | 2175 | platform_set_drvdata(pdev, mtd); |
67ce04bf VS |
2176 | |
2177 | return 0; | |
2178 | ||
70ba6d71 | 2179 | return_error: |
a93295a7 | 2180 | if (!IS_ERR_OR_NULL(info->dma)) |
763e7359 | 2181 | dma_release_channel(info->dma); |
32d42a85 PG |
2182 | if (nand_chip->ecc.priv) { |
2183 | nand_bch_free(nand_chip->ecc.priv); | |
2184 | nand_chip->ecc.priv = NULL; | |
2185 | } | |
67ce04bf VS |
2186 | return err; |
2187 | } | |
2188 | ||
2189 | static int omap_nand_remove(struct platform_device *pdev) | |
2190 | { | |
2191 | struct mtd_info *mtd = platform_get_drvdata(pdev); | |
4bd4ebcc | 2192 | struct nand_chip *nand_chip = mtd_to_nand(mtd); |
4578ea9a | 2193 | struct omap_nand_info *info = mtd_to_omap(mtd); |
32d42a85 PG |
2194 | if (nand_chip->ecc.priv) { |
2195 | nand_bch_free(nand_chip->ecc.priv); | |
2196 | nand_chip->ecc.priv = NULL; | |
2197 | } | |
763e7359 RK |
2198 | if (info->dma) |
2199 | dma_release_channel(info->dma); | |
633deb58 | 2200 | nand_release(mtd); |
67ce04bf VS |
2201 | return 0; |
2202 | } | |
2203 | ||
c9711ec5 RQ |
2204 | static const struct of_device_id omap_nand_ids[] = { |
2205 | { .compatible = "ti,omap2-nand", }, | |
2206 | {}, | |
2207 | }; | |
b156b7f2 | 2208 | MODULE_DEVICE_TABLE(of, omap_nand_ids); |
c9711ec5 | 2209 | |
67ce04bf VS |
2210 | static struct platform_driver omap_nand_driver = { |
2211 | .probe = omap_nand_probe, | |
2212 | .remove = omap_nand_remove, | |
2213 | .driver = { | |
2214 | .name = DRIVER_NAME, | |
c9711ec5 | 2215 | .of_match_table = of_match_ptr(omap_nand_ids), |
67ce04bf VS |
2216 | }, |
2217 | }; | |
2218 | ||
f99640de | 2219 | module_platform_driver(omap_nand_driver); |
67ce04bf | 2220 | |
c804c733 | 2221 | MODULE_ALIAS("platform:" DRIVER_NAME); |
67ce04bf VS |
2222 | MODULE_LICENSE("GPL"); |
2223 | MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards"); |