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67ce04bf VS |
1 | /* |
2 | * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com> | |
3 | * Copyright © 2004 Micron Technology Inc. | |
4 | * Copyright © 2004 David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/platform_device.h> | |
12 | #include <linux/dma-mapping.h> | |
13 | #include <linux/delay.h> | |
c276aca4 | 14 | #include <linux/jiffies.h> |
15 | #include <linux/sched.h> | |
67ce04bf VS |
16 | #include <linux/mtd/mtd.h> |
17 | #include <linux/mtd/nand.h> | |
18 | #include <linux/mtd/partitions.h> | |
19 | #include <linux/io.h> | |
20 | ||
dfe32893 | 21 | #include <mach/dma.h> |
67ce04bf VS |
22 | #include <mach/gpmc.h> |
23 | #include <mach/nand.h> | |
24 | ||
25 | #define GPMC_IRQ_STATUS 0x18 | |
26 | #define GPMC_ECC_CONFIG 0x1F4 | |
27 | #define GPMC_ECC_CONTROL 0x1F8 | |
28 | #define GPMC_ECC_SIZE_CONFIG 0x1FC | |
29 | #define GPMC_ECC1_RESULT 0x200 | |
30 | ||
31 | #define DRIVER_NAME "omap2-nand" | |
32 | ||
33 | /* size (4 KiB) for IO mapping */ | |
34 | #define NAND_IO_SIZE SZ_4K | |
35 | ||
36 | #define NAND_WP_OFF 0 | |
37 | #define NAND_WP_BIT 0x00000010 | |
38 | #define WR_RD_PIN_MONITORING 0x00600000 | |
39 | ||
40 | #define GPMC_BUF_FULL 0x00000001 | |
41 | #define GPMC_BUF_EMPTY 0x00000000 | |
42 | ||
43 | #define NAND_Ecc_P1e (1 << 0) | |
44 | #define NAND_Ecc_P2e (1 << 1) | |
45 | #define NAND_Ecc_P4e (1 << 2) | |
46 | #define NAND_Ecc_P8e (1 << 3) | |
47 | #define NAND_Ecc_P16e (1 << 4) | |
48 | #define NAND_Ecc_P32e (1 << 5) | |
49 | #define NAND_Ecc_P64e (1 << 6) | |
50 | #define NAND_Ecc_P128e (1 << 7) | |
51 | #define NAND_Ecc_P256e (1 << 8) | |
52 | #define NAND_Ecc_P512e (1 << 9) | |
53 | #define NAND_Ecc_P1024e (1 << 10) | |
54 | #define NAND_Ecc_P2048e (1 << 11) | |
55 | ||
56 | #define NAND_Ecc_P1o (1 << 16) | |
57 | #define NAND_Ecc_P2o (1 << 17) | |
58 | #define NAND_Ecc_P4o (1 << 18) | |
59 | #define NAND_Ecc_P8o (1 << 19) | |
60 | #define NAND_Ecc_P16o (1 << 20) | |
61 | #define NAND_Ecc_P32o (1 << 21) | |
62 | #define NAND_Ecc_P64o (1 << 22) | |
63 | #define NAND_Ecc_P128o (1 << 23) | |
64 | #define NAND_Ecc_P256o (1 << 24) | |
65 | #define NAND_Ecc_P512o (1 << 25) | |
66 | #define NAND_Ecc_P1024o (1 << 26) | |
67 | #define NAND_Ecc_P2048o (1 << 27) | |
68 | ||
69 | #define TF(value) (value ? 1 : 0) | |
70 | ||
71 | #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0) | |
72 | #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1) | |
73 | #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2) | |
74 | #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3) | |
75 | #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4) | |
76 | #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5) | |
77 | #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6) | |
78 | #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7) | |
79 | ||
80 | #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0) | |
81 | #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1) | |
82 | #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2) | |
83 | #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3) | |
84 | #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4) | |
85 | #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5) | |
86 | #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6) | |
87 | #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7) | |
88 | ||
89 | #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0) | |
90 | #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1) | |
91 | #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2) | |
92 | #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3) | |
93 | #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4) | |
94 | #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5) | |
95 | #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6) | |
96 | #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7) | |
97 | ||
98 | #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0) | |
99 | #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1) | |
100 | #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2) | |
101 | #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3) | |
102 | #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4) | |
103 | #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5) | |
104 | #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6) | |
105 | #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7) | |
106 | ||
107 | #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) | |
108 | #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) | |
109 | ||
110 | #ifdef CONFIG_MTD_PARTITIONS | |
111 | static const char *part_probes[] = { "cmdlinepart", NULL }; | |
112 | #endif | |
113 | ||
59e9c5ae | 114 | #ifdef CONFIG_MTD_NAND_OMAP_PREFETCH |
115 | static int use_prefetch = 1; | |
116 | ||
117 | /* "modprobe ... use_prefetch=0" etc */ | |
118 | module_param(use_prefetch, bool, 0); | |
119 | MODULE_PARM_DESC(use_prefetch, "enable/disable use of PREFETCH"); | |
dfe32893 | 120 | |
121 | #ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA | |
122 | static int use_dma = 1; | |
123 | ||
124 | /* "modprobe ... use_dma=0" etc */ | |
125 | module_param(use_dma, bool, 0); | |
126 | MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); | |
127 | #else | |
128 | const int use_dma; | |
129 | #endif | |
59e9c5ae | 130 | #else |
131 | const int use_prefetch; | |
dfe32893 | 132 | const int use_dma; |
59e9c5ae | 133 | #endif |
134 | ||
67ce04bf VS |
135 | struct omap_nand_info { |
136 | struct nand_hw_control controller; | |
137 | struct omap_nand_platform_data *pdata; | |
138 | struct mtd_info mtd; | |
139 | struct mtd_partition *parts; | |
140 | struct nand_chip nand; | |
141 | struct platform_device *pdev; | |
142 | ||
143 | int gpmc_cs; | |
144 | unsigned long phys_base; | |
145 | void __iomem *gpmc_cs_baseaddr; | |
146 | void __iomem *gpmc_baseaddr; | |
59e9c5ae | 147 | void __iomem *nand_pref_fifo_add; |
dfe32893 | 148 | struct completion comp; |
149 | int dma_ch; | |
67ce04bf VS |
150 | }; |
151 | ||
152 | /** | |
153 | * omap_nand_wp - This function enable or disable the Write Protect feature | |
154 | * @mtd: MTD device structure | |
155 | * @mode: WP ON/OFF | |
156 | */ | |
157 | static void omap_nand_wp(struct mtd_info *mtd, int mode) | |
158 | { | |
159 | struct omap_nand_info *info = container_of(mtd, | |
160 | struct omap_nand_info, mtd); | |
161 | ||
162 | unsigned long config = __raw_readl(info->gpmc_baseaddr + GPMC_CONFIG); | |
163 | ||
164 | if (mode) | |
165 | config &= ~(NAND_WP_BIT); /* WP is ON */ | |
166 | else | |
167 | config |= (NAND_WP_BIT); /* WP is OFF */ | |
168 | ||
169 | __raw_writel(config, (info->gpmc_baseaddr + GPMC_CONFIG)); | |
170 | } | |
171 | ||
172 | /** | |
173 | * omap_hwcontrol - hardware specific access to control-lines | |
174 | * @mtd: MTD device structure | |
175 | * @cmd: command to device | |
176 | * @ctrl: | |
177 | * NAND_NCE: bit 0 -> don't care | |
178 | * NAND_CLE: bit 1 -> Command Latch | |
179 | * NAND_ALE: bit 2 -> Address Latch | |
180 | * | |
181 | * NOTE: boards may use different bits for these!! | |
182 | */ | |
183 | static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
184 | { | |
185 | struct omap_nand_info *info = container_of(mtd, | |
186 | struct omap_nand_info, mtd); | |
187 | switch (ctrl) { | |
188 | case NAND_CTRL_CHANGE | NAND_CTRL_CLE: | |
189 | info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr + | |
190 | GPMC_CS_NAND_COMMAND; | |
191 | info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr + | |
192 | GPMC_CS_NAND_DATA; | |
193 | break; | |
194 | ||
195 | case NAND_CTRL_CHANGE | NAND_CTRL_ALE: | |
196 | info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr + | |
197 | GPMC_CS_NAND_ADDRESS; | |
198 | info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr + | |
199 | GPMC_CS_NAND_DATA; | |
200 | break; | |
201 | ||
202 | case NAND_CTRL_CHANGE | NAND_NCE: | |
203 | info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr + | |
204 | GPMC_CS_NAND_DATA; | |
205 | info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr + | |
206 | GPMC_CS_NAND_DATA; | |
207 | break; | |
208 | } | |
209 | ||
210 | if (cmd != NAND_CMD_NONE) | |
211 | __raw_writeb(cmd, info->nand.IO_ADDR_W); | |
212 | } | |
213 | ||
59e9c5ae | 214 | /** |
215 | * omap_read_buf8 - read data from NAND controller into buffer | |
216 | * @mtd: MTD device structure | |
217 | * @buf: buffer to store date | |
218 | * @len: number of bytes to read | |
219 | */ | |
220 | static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len) | |
221 | { | |
222 | struct nand_chip *nand = mtd->priv; | |
223 | ||
224 | ioread8_rep(nand->IO_ADDR_R, buf, len); | |
225 | } | |
226 | ||
227 | /** | |
228 | * omap_write_buf8 - write buffer to NAND controller | |
229 | * @mtd: MTD device structure | |
230 | * @buf: data buffer | |
231 | * @len: number of bytes to write | |
232 | */ | |
233 | static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len) | |
234 | { | |
235 | struct omap_nand_info *info = container_of(mtd, | |
236 | struct omap_nand_info, mtd); | |
237 | u_char *p = (u_char *)buf; | |
238 | ||
239 | while (len--) { | |
240 | iowrite8(*p++, info->nand.IO_ADDR_W); | |
241 | while (GPMC_BUF_EMPTY == (readl(info->gpmc_baseaddr + | |
242 | GPMC_STATUS) & GPMC_BUF_FULL)); | |
243 | } | |
244 | } | |
245 | ||
67ce04bf VS |
246 | /** |
247 | * omap_read_buf16 - read data from NAND controller into buffer | |
248 | * @mtd: MTD device structure | |
249 | * @buf: buffer to store date | |
250 | * @len: number of bytes to read | |
251 | */ | |
252 | static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len) | |
253 | { | |
254 | struct nand_chip *nand = mtd->priv; | |
255 | ||
59e9c5ae | 256 | ioread16_rep(nand->IO_ADDR_R, buf, len / 2); |
67ce04bf VS |
257 | } |
258 | ||
259 | /** | |
260 | * omap_write_buf16 - write buffer to NAND controller | |
261 | * @mtd: MTD device structure | |
262 | * @buf: data buffer | |
263 | * @len: number of bytes to write | |
264 | */ | |
265 | static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len) | |
266 | { | |
267 | struct omap_nand_info *info = container_of(mtd, | |
268 | struct omap_nand_info, mtd); | |
269 | u16 *p = (u16 *) buf; | |
270 | ||
271 | /* FIXME try bursts of writesw() or DMA ... */ | |
272 | len >>= 1; | |
273 | ||
274 | while (len--) { | |
59e9c5ae | 275 | iowrite16(*p++, info->nand.IO_ADDR_W); |
67ce04bf VS |
276 | |
277 | while (GPMC_BUF_EMPTY == (readl(info->gpmc_baseaddr + | |
278 | GPMC_STATUS) & GPMC_BUF_FULL)) | |
279 | ; | |
280 | } | |
281 | } | |
59e9c5ae | 282 | |
283 | /** | |
284 | * omap_read_buf_pref - read data from NAND controller into buffer | |
285 | * @mtd: MTD device structure | |
286 | * @buf: buffer to store date | |
287 | * @len: number of bytes to read | |
288 | */ | |
289 | static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) | |
290 | { | |
291 | struct omap_nand_info *info = container_of(mtd, | |
292 | struct omap_nand_info, mtd); | |
293 | uint32_t pfpw_status = 0, r_count = 0; | |
294 | int ret = 0; | |
295 | u32 *p = (u32 *)buf; | |
296 | ||
297 | /* take care of subpage reads */ | |
298 | for (; len % 4 != 0; ) { | |
299 | *buf++ = __raw_readb(info->nand.IO_ADDR_R); | |
300 | len--; | |
301 | } | |
302 | p = (u32 *) buf; | |
303 | ||
304 | /* configure and start prefetch transfer */ | |
305 | ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0); | |
306 | if (ret) { | |
307 | /* PFPW engine is busy, use cpu copy method */ | |
308 | if (info->nand.options & NAND_BUSWIDTH_16) | |
309 | omap_read_buf16(mtd, buf, len); | |
310 | else | |
311 | omap_read_buf8(mtd, buf, len); | |
312 | } else { | |
313 | do { | |
314 | pfpw_status = gpmc_prefetch_status(); | |
315 | r_count = ((pfpw_status >> 24) & 0x7F) >> 2; | |
316 | ioread32_rep(info->nand_pref_fifo_add, p, r_count); | |
317 | p += r_count; | |
318 | len -= r_count << 2; | |
319 | } while (len); | |
320 | ||
321 | /* disable and stop the PFPW engine */ | |
322 | gpmc_prefetch_reset(); | |
323 | } | |
324 | } | |
325 | ||
326 | /** | |
327 | * omap_write_buf_pref - write buffer to NAND controller | |
328 | * @mtd: MTD device structure | |
329 | * @buf: data buffer | |
330 | * @len: number of bytes to write | |
331 | */ | |
332 | static void omap_write_buf_pref(struct mtd_info *mtd, | |
333 | const u_char *buf, int len) | |
334 | { | |
335 | struct omap_nand_info *info = container_of(mtd, | |
336 | struct omap_nand_info, mtd); | |
337 | uint32_t pfpw_status = 0, w_count = 0; | |
338 | int i = 0, ret = 0; | |
339 | u16 *p = (u16 *) buf; | |
340 | ||
341 | /* take care of subpage writes */ | |
342 | if (len % 2 != 0) { | |
343 | writeb(*buf, info->nand.IO_ADDR_R); | |
344 | p = (u16 *)(buf + 1); | |
345 | len--; | |
346 | } | |
347 | ||
348 | /* configure and start prefetch transfer */ | |
349 | ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1); | |
350 | if (ret) { | |
351 | /* PFPW engine is busy, use cpu copy method */ | |
352 | if (info->nand.options & NAND_BUSWIDTH_16) | |
353 | omap_write_buf16(mtd, buf, len); | |
354 | else | |
355 | omap_write_buf8(mtd, buf, len); | |
356 | } else { | |
357 | pfpw_status = gpmc_prefetch_status(); | |
358 | while (pfpw_status & 0x3FFF) { | |
359 | w_count = ((pfpw_status >> 24) & 0x7F) >> 1; | |
360 | for (i = 0; (i < w_count) && len; i++, len -= 2) | |
361 | iowrite16(*p++, info->nand_pref_fifo_add); | |
362 | pfpw_status = gpmc_prefetch_status(); | |
363 | } | |
364 | ||
365 | /* disable and stop the PFPW engine */ | |
366 | gpmc_prefetch_reset(); | |
367 | } | |
368 | } | |
369 | ||
dfe32893 | 370 | #ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA |
371 | /* | |
372 | * omap_nand_dma_cb: callback on the completion of dma transfer | |
373 | * @lch: logical channel | |
374 | * @ch_satuts: channel status | |
375 | * @data: pointer to completion data structure | |
376 | */ | |
377 | static void omap_nand_dma_cb(int lch, u16 ch_status, void *data) | |
378 | { | |
379 | complete((struct completion *) data); | |
380 | } | |
381 | ||
382 | /* | |
383 | * omap_nand_dma_transfer: configer and start dma transfer | |
384 | * @mtd: MTD device structure | |
385 | * @addr: virtual address in RAM of source/destination | |
386 | * @len: number of data bytes to be transferred | |
387 | * @is_write: flag for read/write operation | |
388 | */ | |
389 | static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, | |
390 | unsigned int len, int is_write) | |
391 | { | |
392 | struct omap_nand_info *info = container_of(mtd, | |
393 | struct omap_nand_info, mtd); | |
394 | uint32_t prefetch_status = 0; | |
395 | enum dma_data_direction dir = is_write ? DMA_TO_DEVICE : | |
396 | DMA_FROM_DEVICE; | |
397 | dma_addr_t dma_addr; | |
398 | int ret; | |
399 | ||
400 | /* The fifo depth is 64 bytes. We have a sync at each frame and frame | |
401 | * length is 64 bytes. | |
402 | */ | |
403 | int buf_len = len >> 6; | |
404 | ||
405 | if (addr >= high_memory) { | |
406 | struct page *p1; | |
407 | ||
408 | if (((size_t)addr & PAGE_MASK) != | |
409 | ((size_t)(addr + len - 1) & PAGE_MASK)) | |
410 | goto out_copy; | |
411 | p1 = vmalloc_to_page(addr); | |
412 | if (!p1) | |
413 | goto out_copy; | |
414 | addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK); | |
415 | } | |
416 | ||
417 | dma_addr = dma_map_single(&info->pdev->dev, addr, len, dir); | |
418 | if (dma_mapping_error(&info->pdev->dev, dma_addr)) { | |
419 | dev_err(&info->pdev->dev, | |
420 | "Couldn't DMA map a %d byte buffer\n", len); | |
421 | goto out_copy; | |
422 | } | |
423 | ||
424 | if (is_write) { | |
425 | omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, | |
426 | info->phys_base, 0, 0); | |
427 | omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC, | |
428 | dma_addr, 0, 0); | |
429 | omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32, | |
430 | 0x10, buf_len, OMAP_DMA_SYNC_FRAME, | |
431 | OMAP24XX_DMA_GPMC, OMAP_DMA_DST_SYNC); | |
432 | } else { | |
433 | omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, | |
434 | info->phys_base, 0, 0); | |
435 | omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC, | |
436 | dma_addr, 0, 0); | |
437 | omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32, | |
438 | 0x10, buf_len, OMAP_DMA_SYNC_FRAME, | |
439 | OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC); | |
440 | } | |
441 | /* configure and start prefetch transfer */ | |
442 | ret = gpmc_prefetch_enable(info->gpmc_cs, 0x1, len, is_write); | |
443 | if (ret) | |
444 | /* PFPW engine is busy, use cpu copy methode */ | |
445 | goto out_copy; | |
446 | ||
447 | init_completion(&info->comp); | |
448 | ||
449 | omap_start_dma(info->dma_ch); | |
450 | ||
451 | /* setup and start DMA using dma_addr */ | |
452 | wait_for_completion(&info->comp); | |
453 | ||
454 | while (0x3fff & (prefetch_status = gpmc_prefetch_status())) | |
455 | ; | |
456 | /* disable and stop the PFPW engine */ | |
457 | gpmc_prefetch_reset(); | |
458 | ||
459 | dma_unmap_single(&info->pdev->dev, dma_addr, len, dir); | |
460 | return 0; | |
461 | ||
462 | out_copy: | |
463 | if (info->nand.options & NAND_BUSWIDTH_16) | |
464 | is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len) | |
465 | : omap_write_buf16(mtd, (u_char *) addr, len); | |
466 | else | |
467 | is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len) | |
468 | : omap_write_buf8(mtd, (u_char *) addr, len); | |
469 | return 0; | |
470 | } | |
471 | #else | |
472 | static void omap_nand_dma_cb(int lch, u16 ch_status, void *data) {} | |
473 | static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, | |
474 | unsigned int len, int is_write) | |
475 | { | |
476 | return 0; | |
477 | } | |
478 | #endif | |
479 | ||
480 | /** | |
481 | * omap_read_buf_dma_pref - read data from NAND controller into buffer | |
482 | * @mtd: MTD device structure | |
483 | * @buf: buffer to store date | |
484 | * @len: number of bytes to read | |
485 | */ | |
486 | static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len) | |
487 | { | |
488 | if (len <= mtd->oobsize) | |
489 | omap_read_buf_pref(mtd, buf, len); | |
490 | else | |
491 | /* start transfer in DMA mode */ | |
492 | omap_nand_dma_transfer(mtd, buf, len, 0x0); | |
493 | } | |
494 | ||
495 | /** | |
496 | * omap_write_buf_dma_pref - write buffer to NAND controller | |
497 | * @mtd: MTD device structure | |
498 | * @buf: data buffer | |
499 | * @len: number of bytes to write | |
500 | */ | |
501 | static void omap_write_buf_dma_pref(struct mtd_info *mtd, | |
502 | const u_char *buf, int len) | |
503 | { | |
504 | if (len <= mtd->oobsize) | |
505 | omap_write_buf_pref(mtd, buf, len); | |
506 | else | |
507 | /* start transfer in DMA mode */ | |
508 | omap_nand_dma_transfer(mtd, buf, len, 0x1); | |
509 | } | |
510 | ||
67ce04bf VS |
511 | /** |
512 | * omap_verify_buf - Verify chip data against buffer | |
513 | * @mtd: MTD device structure | |
514 | * @buf: buffer containing the data to compare | |
515 | * @len: number of bytes to compare | |
516 | */ | |
517 | static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len) | |
518 | { | |
519 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
520 | mtd); | |
521 | u16 *p = (u16 *) buf; | |
522 | ||
523 | len >>= 1; | |
524 | while (len--) { | |
525 | if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R))) | |
526 | return -EFAULT; | |
527 | } | |
528 | ||
529 | return 0; | |
530 | } | |
531 | ||
532 | #ifdef CONFIG_MTD_NAND_OMAP_HWECC | |
533 | /** | |
534 | * omap_hwecc_init - Initialize the HW ECC for NAND flash in GPMC controller | |
535 | * @mtd: MTD device structure | |
536 | */ | |
537 | static void omap_hwecc_init(struct mtd_info *mtd) | |
538 | { | |
539 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
540 | mtd); | |
541 | struct nand_chip *chip = mtd->priv; | |
542 | unsigned long val = 0x0; | |
543 | ||
544 | /* Read from ECC Control Register */ | |
545 | val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONTROL); | |
546 | /* Clear all ECC | Enable Reg1 */ | |
547 | val = ((0x00000001<<8) | 0x00000001); | |
548 | __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONTROL); | |
549 | ||
550 | /* Read from ECC Size Config Register */ | |
551 | val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG); | |
552 | /* ECCSIZE1=512 | Select eccResultsize[0-3] */ | |
553 | val = ((((chip->ecc.size >> 1) - 1) << 22) | (0x0000000F)); | |
554 | __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG); | |
555 | } | |
556 | ||
557 | /** | |
558 | * gen_true_ecc - This function will generate true ECC value | |
559 | * @ecc_buf: buffer to store ecc code | |
560 | * | |
561 | * This generated true ECC value can be used when correcting | |
562 | * data read from NAND flash memory core | |
563 | */ | |
564 | static void gen_true_ecc(u8 *ecc_buf) | |
565 | { | |
566 | u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) | | |
567 | ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8); | |
568 | ||
569 | ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | | |
570 | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); | |
571 | ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | | |
572 | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); | |
573 | ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | | |
574 | P1e(tmp) | P2048o(tmp) | P2048e(tmp)); | |
575 | } | |
576 | ||
577 | /** | |
578 | * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data | |
579 | * @ecc_data1: ecc code from nand spare area | |
580 | * @ecc_data2: ecc code from hardware register obtained from hardware ecc | |
581 | * @page_data: page data | |
582 | * | |
583 | * This function compares two ECC's and indicates if there is an error. | |
584 | * If the error can be corrected it will be corrected to the buffer. | |
585 | */ | |
586 | static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */ | |
587 | u8 *ecc_data2, /* read from register */ | |
588 | u8 *page_data) | |
589 | { | |
590 | uint i; | |
591 | u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; | |
592 | u8 comp0_bit[8], comp1_bit[8], comp2_bit[8]; | |
593 | u8 ecc_bit[24]; | |
594 | u8 ecc_sum = 0; | |
595 | u8 find_bit = 0; | |
596 | uint find_byte = 0; | |
597 | int isEccFF; | |
598 | ||
599 | isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF); | |
600 | ||
601 | gen_true_ecc(ecc_data1); | |
602 | gen_true_ecc(ecc_data2); | |
603 | ||
604 | for (i = 0; i <= 2; i++) { | |
605 | *(ecc_data1 + i) = ~(*(ecc_data1 + i)); | |
606 | *(ecc_data2 + i) = ~(*(ecc_data2 + i)); | |
607 | } | |
608 | ||
609 | for (i = 0; i < 8; i++) { | |
610 | tmp0_bit[i] = *ecc_data1 % 2; | |
611 | *ecc_data1 = *ecc_data1 / 2; | |
612 | } | |
613 | ||
614 | for (i = 0; i < 8; i++) { | |
615 | tmp1_bit[i] = *(ecc_data1 + 1) % 2; | |
616 | *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2; | |
617 | } | |
618 | ||
619 | for (i = 0; i < 8; i++) { | |
620 | tmp2_bit[i] = *(ecc_data1 + 2) % 2; | |
621 | *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2; | |
622 | } | |
623 | ||
624 | for (i = 0; i < 8; i++) { | |
625 | comp0_bit[i] = *ecc_data2 % 2; | |
626 | *ecc_data2 = *ecc_data2 / 2; | |
627 | } | |
628 | ||
629 | for (i = 0; i < 8; i++) { | |
630 | comp1_bit[i] = *(ecc_data2 + 1) % 2; | |
631 | *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2; | |
632 | } | |
633 | ||
634 | for (i = 0; i < 8; i++) { | |
635 | comp2_bit[i] = *(ecc_data2 + 2) % 2; | |
636 | *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2; | |
637 | } | |
638 | ||
639 | for (i = 0; i < 6; i++) | |
640 | ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; | |
641 | ||
642 | for (i = 0; i < 8; i++) | |
643 | ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; | |
644 | ||
645 | for (i = 0; i < 8; i++) | |
646 | ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; | |
647 | ||
648 | ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; | |
649 | ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; | |
650 | ||
651 | for (i = 0; i < 24; i++) | |
652 | ecc_sum += ecc_bit[i]; | |
653 | ||
654 | switch (ecc_sum) { | |
655 | case 0: | |
656 | /* Not reached because this function is not called if | |
657 | * ECC values are equal | |
658 | */ | |
659 | return 0; | |
660 | ||
661 | case 1: | |
662 | /* Uncorrectable error */ | |
663 | DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n"); | |
664 | return -1; | |
665 | ||
666 | case 11: | |
667 | /* UN-Correctable error */ | |
668 | DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR B\n"); | |
669 | return -1; | |
670 | ||
671 | case 12: | |
672 | /* Correctable error */ | |
673 | find_byte = (ecc_bit[23] << 8) + | |
674 | (ecc_bit[21] << 7) + | |
675 | (ecc_bit[19] << 6) + | |
676 | (ecc_bit[17] << 5) + | |
677 | (ecc_bit[15] << 4) + | |
678 | (ecc_bit[13] << 3) + | |
679 | (ecc_bit[11] << 2) + | |
680 | (ecc_bit[9] << 1) + | |
681 | ecc_bit[7]; | |
682 | ||
683 | find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; | |
684 | ||
685 | DEBUG(MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at " | |
686 | "offset: %d, bit: %d\n", find_byte, find_bit); | |
687 | ||
688 | page_data[find_byte] ^= (1 << find_bit); | |
689 | ||
690 | return 0; | |
691 | default: | |
692 | if (isEccFF) { | |
693 | if (ecc_data2[0] == 0 && | |
694 | ecc_data2[1] == 0 && | |
695 | ecc_data2[2] == 0) | |
696 | return 0; | |
697 | } | |
698 | DEBUG(MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n"); | |
699 | return -1; | |
700 | } | |
701 | } | |
702 | ||
703 | /** | |
704 | * omap_correct_data - Compares the ECC read with HW generated ECC | |
705 | * @mtd: MTD device structure | |
706 | * @dat: page data | |
707 | * @read_ecc: ecc read from nand flash | |
708 | * @calc_ecc: ecc read from HW ECC registers | |
709 | * | |
710 | * Compares the ecc read from nand spare area with ECC registers values | |
711 | * and if ECC's mismached, it will call 'omap_compare_ecc' for error detection | |
712 | * and correction. | |
713 | */ | |
714 | static int omap_correct_data(struct mtd_info *mtd, u_char *dat, | |
715 | u_char *read_ecc, u_char *calc_ecc) | |
716 | { | |
717 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
718 | mtd); | |
719 | int blockCnt = 0, i = 0, ret = 0; | |
720 | ||
721 | /* Ex NAND_ECC_HW12_2048 */ | |
722 | if ((info->nand.ecc.mode == NAND_ECC_HW) && | |
723 | (info->nand.ecc.size == 2048)) | |
724 | blockCnt = 4; | |
725 | else | |
726 | blockCnt = 1; | |
727 | ||
728 | for (i = 0; i < blockCnt; i++) { | |
729 | if (memcmp(read_ecc, calc_ecc, 3) != 0) { | |
730 | ret = omap_compare_ecc(read_ecc, calc_ecc, dat); | |
731 | if (ret < 0) | |
732 | return ret; | |
733 | } | |
734 | read_ecc += 3; | |
735 | calc_ecc += 3; | |
736 | dat += 512; | |
737 | } | |
738 | return 0; | |
739 | } | |
740 | ||
741 | /** | |
742 | * omap_calcuate_ecc - Generate non-inverted ECC bytes. | |
743 | * @mtd: MTD device structure | |
744 | * @dat: The pointer to data on which ecc is computed | |
745 | * @ecc_code: The ecc_code buffer | |
746 | * | |
747 | * Using noninverted ECC can be considered ugly since writing a blank | |
748 | * page ie. padding will clear the ECC bytes. This is no problem as long | |
749 | * nobody is trying to write data on the seemingly unused page. Reading | |
750 | * an erased page will produce an ECC mismatch between generated and read | |
751 | * ECC bytes that has to be dealt with separately. | |
752 | */ | |
753 | static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, | |
754 | u_char *ecc_code) | |
755 | { | |
756 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
757 | mtd); | |
758 | unsigned long val = 0x0; | |
759 | unsigned long reg; | |
760 | ||
761 | /* Start Reading from HW ECC1_Result = 0x200 */ | |
762 | reg = (unsigned long)(info->gpmc_baseaddr + GPMC_ECC1_RESULT); | |
763 | val = __raw_readl(reg); | |
764 | *ecc_code++ = val; /* P128e, ..., P1e */ | |
765 | *ecc_code++ = val >> 16; /* P128o, ..., P1o */ | |
766 | /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ | |
767 | *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); | |
768 | reg += 4; | |
769 | ||
770 | return 0; | |
771 | } | |
772 | ||
773 | /** | |
774 | * omap_enable_hwecc - This function enables the hardware ecc functionality | |
775 | * @mtd: MTD device structure | |
776 | * @mode: Read/Write mode | |
777 | */ | |
778 | static void omap_enable_hwecc(struct mtd_info *mtd, int mode) | |
779 | { | |
780 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
781 | mtd); | |
782 | struct nand_chip *chip = mtd->priv; | |
783 | unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; | |
784 | unsigned long val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONFIG); | |
785 | ||
786 | switch (mode) { | |
787 | case NAND_ECC_READ: | |
788 | __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL); | |
789 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ | |
790 | val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); | |
791 | break; | |
792 | case NAND_ECC_READSYN: | |
793 | __raw_writel(0x100, info->gpmc_baseaddr + GPMC_ECC_CONTROL); | |
794 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ | |
795 | val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); | |
796 | break; | |
797 | case NAND_ECC_WRITE: | |
798 | __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL); | |
799 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ | |
800 | val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); | |
801 | break; | |
802 | default: | |
803 | DEBUG(MTD_DEBUG_LEVEL0, "Error: Unrecognized Mode[%d]!\n", | |
804 | mode); | |
805 | break; | |
806 | } | |
807 | ||
808 | __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONFIG); | |
809 | } | |
810 | #endif | |
811 | ||
812 | /** | |
813 | * omap_wait - wait until the command is done | |
814 | * @mtd: MTD device structure | |
815 | * @chip: NAND Chip structure | |
816 | * | |
817 | * Wait function is called during Program and erase operations and | |
818 | * the way it is called from MTD layer, we should wait till the NAND | |
819 | * chip is ready after the programming/erase operation has completed. | |
820 | * | |
821 | * Erase can take up to 400ms and program up to 20ms according to | |
822 | * general NAND and SmartMedia specs | |
823 | */ | |
824 | static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
825 | { | |
826 | struct nand_chip *this = mtd->priv; | |
827 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
828 | mtd); | |
829 | unsigned long timeo = jiffies; | |
c276aca4 | 830 | int status = NAND_STATUS_FAIL, state = this->state; |
67ce04bf VS |
831 | |
832 | if (state == FL_ERASING) | |
833 | timeo += (HZ * 400) / 1000; | |
834 | else | |
835 | timeo += (HZ * 20) / 1000; | |
836 | ||
837 | this->IO_ADDR_W = (void *) info->gpmc_cs_baseaddr + | |
838 | GPMC_CS_NAND_COMMAND; | |
839 | this->IO_ADDR_R = (void *) info->gpmc_cs_baseaddr + GPMC_CS_NAND_DATA; | |
840 | ||
841 | __raw_writeb(NAND_CMD_STATUS & 0xFF, this->IO_ADDR_W); | |
842 | ||
843 | while (time_before(jiffies, timeo)) { | |
844 | status = __raw_readb(this->IO_ADDR_R); | |
c276aca4 | 845 | if (status & NAND_STATUS_READY) |
67ce04bf | 846 | break; |
c276aca4 | 847 | cond_resched(); |
67ce04bf VS |
848 | } |
849 | return status; | |
850 | } | |
851 | ||
852 | /** | |
853 | * omap_dev_ready - calls the platform specific dev_ready function | |
854 | * @mtd: MTD device structure | |
855 | */ | |
856 | static int omap_dev_ready(struct mtd_info *mtd) | |
857 | { | |
858 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
859 | mtd); | |
860 | unsigned int val = __raw_readl(info->gpmc_baseaddr + GPMC_IRQ_STATUS); | |
861 | ||
862 | if ((val & 0x100) == 0x100) { | |
863 | /* Clear IRQ Interrupt */ | |
864 | val |= 0x100; | |
865 | val &= ~(0x0); | |
866 | __raw_writel(val, info->gpmc_baseaddr + GPMC_IRQ_STATUS); | |
867 | } else { | |
868 | unsigned int cnt = 0; | |
869 | while (cnt++ < 0x1FF) { | |
870 | if ((val & 0x100) == 0x100) | |
871 | return 0; | |
872 | val = __raw_readl(info->gpmc_baseaddr + | |
873 | GPMC_IRQ_STATUS); | |
874 | } | |
875 | } | |
876 | ||
877 | return 1; | |
878 | } | |
879 | ||
880 | static int __devinit omap_nand_probe(struct platform_device *pdev) | |
881 | { | |
882 | struct omap_nand_info *info; | |
883 | struct omap_nand_platform_data *pdata; | |
884 | int err; | |
885 | unsigned long val; | |
886 | ||
887 | ||
888 | pdata = pdev->dev.platform_data; | |
889 | if (pdata == NULL) { | |
890 | dev_err(&pdev->dev, "platform data missing\n"); | |
891 | return -ENODEV; | |
892 | } | |
893 | ||
894 | info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL); | |
895 | if (!info) | |
896 | return -ENOMEM; | |
897 | ||
898 | platform_set_drvdata(pdev, info); | |
899 | ||
900 | spin_lock_init(&info->controller.lock); | |
901 | init_waitqueue_head(&info->controller.wq); | |
902 | ||
903 | info->pdev = pdev; | |
904 | ||
905 | info->gpmc_cs = pdata->cs; | |
906 | info->gpmc_baseaddr = pdata->gpmc_baseaddr; | |
907 | info->gpmc_cs_baseaddr = pdata->gpmc_cs_baseaddr; | |
908 | ||
909 | info->mtd.priv = &info->nand; | |
910 | info->mtd.name = dev_name(&pdev->dev); | |
911 | info->mtd.owner = THIS_MODULE; | |
912 | ||
913 | err = gpmc_cs_request(info->gpmc_cs, NAND_IO_SIZE, &info->phys_base); | |
914 | if (err < 0) { | |
915 | dev_err(&pdev->dev, "Cannot request GPMC CS\n"); | |
916 | goto out_free_info; | |
917 | } | |
918 | ||
919 | /* Enable RD PIN Monitoring Reg */ | |
920 | if (pdata->dev_ready) { | |
921 | val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1); | |
922 | val |= WR_RD_PIN_MONITORING; | |
923 | gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val); | |
924 | } | |
925 | ||
926 | val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG7); | |
927 | val &= ~(0xf << 8); | |
928 | val |= (0xc & 0xf) << 8; | |
929 | gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG7, val); | |
930 | ||
931 | /* NAND write protect off */ | |
932 | omap_nand_wp(&info->mtd, NAND_WP_OFF); | |
933 | ||
934 | if (!request_mem_region(info->phys_base, NAND_IO_SIZE, | |
935 | pdev->dev.driver->name)) { | |
936 | err = -EBUSY; | |
937 | goto out_free_cs; | |
938 | } | |
939 | ||
940 | info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE); | |
941 | if (!info->nand.IO_ADDR_R) { | |
942 | err = -ENOMEM; | |
943 | goto out_release_mem_region; | |
944 | } | |
59e9c5ae | 945 | |
67ce04bf VS |
946 | info->nand.controller = &info->controller; |
947 | ||
948 | info->nand.IO_ADDR_W = info->nand.IO_ADDR_R; | |
949 | info->nand.cmd_ctrl = omap_hwcontrol; | |
950 | ||
67ce04bf VS |
951 | /* |
952 | * If RDY/BSY line is connected to OMAP then use the omap ready | |
953 | * funcrtion and the generic nand_wait function which reads the status | |
954 | * register after monitoring the RDY/BSY line.Otherwise use a standard | |
955 | * chip delay which is slightly more than tR (AC Timing) of the NAND | |
956 | * device and read status register until you get a failure or success | |
957 | */ | |
958 | if (pdata->dev_ready) { | |
959 | info->nand.dev_ready = omap_dev_ready; | |
960 | info->nand.chip_delay = 0; | |
961 | } else { | |
962 | info->nand.waitfunc = omap_wait; | |
963 | info->nand.chip_delay = 50; | |
964 | } | |
965 | ||
966 | info->nand.options |= NAND_SKIP_BBTSCAN; | |
967 | if ((gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1) & 0x3000) | |
968 | == 0x1000) | |
969 | info->nand.options |= NAND_BUSWIDTH_16; | |
970 | ||
59e9c5ae | 971 | if (use_prefetch) { |
972 | /* copy the virtual address of nand base for fifo access */ | |
973 | info->nand_pref_fifo_add = info->nand.IO_ADDR_R; | |
974 | ||
975 | info->nand.read_buf = omap_read_buf_pref; | |
976 | info->nand.write_buf = omap_write_buf_pref; | |
dfe32893 | 977 | if (use_dma) { |
978 | err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND", | |
979 | omap_nand_dma_cb, &info->comp, &info->dma_ch); | |
980 | if (err < 0) { | |
981 | info->dma_ch = -1; | |
982 | printk(KERN_WARNING "DMA request failed." | |
983 | " Non-dma data transfer mode\n"); | |
984 | } else { | |
985 | omap_set_dma_dest_burst_mode(info->dma_ch, | |
986 | OMAP_DMA_DATA_BURST_16); | |
987 | omap_set_dma_src_burst_mode(info->dma_ch, | |
988 | OMAP_DMA_DATA_BURST_16); | |
989 | ||
990 | info->nand.read_buf = omap_read_buf_dma_pref; | |
991 | info->nand.write_buf = omap_write_buf_dma_pref; | |
992 | } | |
993 | } | |
59e9c5ae | 994 | } else { |
995 | if (info->nand.options & NAND_BUSWIDTH_16) { | |
996 | info->nand.read_buf = omap_read_buf16; | |
997 | info->nand.write_buf = omap_write_buf16; | |
998 | } else { | |
999 | info->nand.read_buf = omap_read_buf8; | |
1000 | info->nand.write_buf = omap_write_buf8; | |
1001 | } | |
1002 | } | |
1003 | info->nand.verify_buf = omap_verify_buf; | |
1004 | ||
67ce04bf VS |
1005 | #ifdef CONFIG_MTD_NAND_OMAP_HWECC |
1006 | info->nand.ecc.bytes = 3; | |
1007 | info->nand.ecc.size = 512; | |
1008 | info->nand.ecc.calculate = omap_calculate_ecc; | |
1009 | info->nand.ecc.hwctl = omap_enable_hwecc; | |
1010 | info->nand.ecc.correct = omap_correct_data; | |
1011 | info->nand.ecc.mode = NAND_ECC_HW; | |
1012 | ||
1013 | /* init HW ECC */ | |
1014 | omap_hwecc_init(&info->mtd); | |
1015 | #else | |
1016 | info->nand.ecc.mode = NAND_ECC_SOFT; | |
1017 | #endif | |
1018 | ||
1019 | /* DIP switches on some boards change between 8 and 16 bit | |
1020 | * bus widths for flash. Try the other width if the first try fails. | |
1021 | */ | |
1022 | if (nand_scan(&info->mtd, 1)) { | |
1023 | info->nand.options ^= NAND_BUSWIDTH_16; | |
1024 | if (nand_scan(&info->mtd, 1)) { | |
1025 | err = -ENXIO; | |
1026 | goto out_release_mem_region; | |
1027 | } | |
1028 | } | |
1029 | ||
1030 | #ifdef CONFIG_MTD_PARTITIONS | |
1031 | err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0); | |
1032 | if (err > 0) | |
1033 | add_mtd_partitions(&info->mtd, info->parts, err); | |
1034 | else if (pdata->parts) | |
1035 | add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts); | |
1036 | else | |
1037 | #endif | |
1038 | add_mtd_device(&info->mtd); | |
1039 | ||
1040 | platform_set_drvdata(pdev, &info->mtd); | |
1041 | ||
1042 | return 0; | |
1043 | ||
1044 | out_release_mem_region: | |
1045 | release_mem_region(info->phys_base, NAND_IO_SIZE); | |
1046 | out_free_cs: | |
1047 | gpmc_cs_free(info->gpmc_cs); | |
1048 | out_free_info: | |
1049 | kfree(info); | |
1050 | ||
1051 | return err; | |
1052 | } | |
1053 | ||
1054 | static int omap_nand_remove(struct platform_device *pdev) | |
1055 | { | |
1056 | struct mtd_info *mtd = platform_get_drvdata(pdev); | |
1057 | struct omap_nand_info *info = mtd->priv; | |
1058 | ||
1059 | platform_set_drvdata(pdev, NULL); | |
dfe32893 | 1060 | if (use_dma) |
1061 | omap_free_dma(info->dma_ch); | |
1062 | ||
67ce04bf VS |
1063 | /* Release NAND device, its internal structures and partitions */ |
1064 | nand_release(&info->mtd); | |
59e9c5ae | 1065 | iounmap(info->nand_pref_fifo_add); |
67ce04bf VS |
1066 | kfree(&info->mtd); |
1067 | return 0; | |
1068 | } | |
1069 | ||
1070 | static struct platform_driver omap_nand_driver = { | |
1071 | .probe = omap_nand_probe, | |
1072 | .remove = omap_nand_remove, | |
1073 | .driver = { | |
1074 | .name = DRIVER_NAME, | |
1075 | .owner = THIS_MODULE, | |
1076 | }, | |
1077 | }; | |
1078 | ||
1079 | static int __init omap_nand_init(void) | |
1080 | { | |
1081 | printk(KERN_INFO "%s driver initializing\n", DRIVER_NAME); | |
dfe32893 | 1082 | |
1083 | /* This check is required if driver is being | |
1084 | * loaded run time as a module | |
1085 | */ | |
1086 | if ((1 == use_dma) && (0 == use_prefetch)) { | |
1087 | printk(KERN_INFO"Wrong parameters: 'use_dma' can not be 1 " | |
1088 | "without use_prefetch'. Prefetch will not be" | |
1089 | " used in either mode (mpu or dma)\n"); | |
1090 | } | |
67ce04bf VS |
1091 | return platform_driver_register(&omap_nand_driver); |
1092 | } | |
1093 | ||
1094 | static void __exit omap_nand_exit(void) | |
1095 | { | |
1096 | platform_driver_unregister(&omap_nand_driver); | |
1097 | } | |
1098 | ||
1099 | module_init(omap_nand_init); | |
1100 | module_exit(omap_nand_exit); | |
1101 | ||
1102 | MODULE_ALIAS(DRIVER_NAME); | |
1103 | MODULE_LICENSE("GPL"); | |
1104 | MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards"); |