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67ce04bf VS |
1 | /* |
2 | * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com> | |
3 | * Copyright © 2004 Micron Technology Inc. | |
4 | * Copyright © 2004 David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/platform_device.h> | |
12 | #include <linux/dma-mapping.h> | |
13 | #include <linux/delay.h> | |
a0e5cc58 | 14 | #include <linux/module.h> |
4e070376 | 15 | #include <linux/interrupt.h> |
c276aca4 | 16 | #include <linux/jiffies.h> |
17 | #include <linux/sched.h> | |
67ce04bf VS |
18 | #include <linux/mtd/mtd.h> |
19 | #include <linux/mtd/nand.h> | |
20 | #include <linux/mtd/partitions.h> | |
21 | #include <linux/io.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
67ce04bf | 23 | |
ce491cf8 TL |
24 | #include <plat/dma.h> |
25 | #include <plat/gpmc.h> | |
26 | #include <plat/nand.h> | |
67ce04bf | 27 | |
67ce04bf | 28 | #define DRIVER_NAME "omap2-nand" |
4e070376 | 29 | #define OMAP_NAND_TIMEOUT_MS 5000 |
67ce04bf | 30 | |
67ce04bf VS |
31 | #define NAND_Ecc_P1e (1 << 0) |
32 | #define NAND_Ecc_P2e (1 << 1) | |
33 | #define NAND_Ecc_P4e (1 << 2) | |
34 | #define NAND_Ecc_P8e (1 << 3) | |
35 | #define NAND_Ecc_P16e (1 << 4) | |
36 | #define NAND_Ecc_P32e (1 << 5) | |
37 | #define NAND_Ecc_P64e (1 << 6) | |
38 | #define NAND_Ecc_P128e (1 << 7) | |
39 | #define NAND_Ecc_P256e (1 << 8) | |
40 | #define NAND_Ecc_P512e (1 << 9) | |
41 | #define NAND_Ecc_P1024e (1 << 10) | |
42 | #define NAND_Ecc_P2048e (1 << 11) | |
43 | ||
44 | #define NAND_Ecc_P1o (1 << 16) | |
45 | #define NAND_Ecc_P2o (1 << 17) | |
46 | #define NAND_Ecc_P4o (1 << 18) | |
47 | #define NAND_Ecc_P8o (1 << 19) | |
48 | #define NAND_Ecc_P16o (1 << 20) | |
49 | #define NAND_Ecc_P32o (1 << 21) | |
50 | #define NAND_Ecc_P64o (1 << 22) | |
51 | #define NAND_Ecc_P128o (1 << 23) | |
52 | #define NAND_Ecc_P256o (1 << 24) | |
53 | #define NAND_Ecc_P512o (1 << 25) | |
54 | #define NAND_Ecc_P1024o (1 << 26) | |
55 | #define NAND_Ecc_P2048o (1 << 27) | |
56 | ||
57 | #define TF(value) (value ? 1 : 0) | |
58 | ||
59 | #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0) | |
60 | #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1) | |
61 | #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2) | |
62 | #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3) | |
63 | #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4) | |
64 | #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5) | |
65 | #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6) | |
66 | #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7) | |
67 | ||
68 | #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0) | |
69 | #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1) | |
70 | #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2) | |
71 | #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3) | |
72 | #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4) | |
73 | #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5) | |
74 | #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6) | |
75 | #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7) | |
76 | ||
77 | #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0) | |
78 | #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1) | |
79 | #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2) | |
80 | #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3) | |
81 | #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4) | |
82 | #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5) | |
83 | #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6) | |
84 | #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7) | |
85 | ||
86 | #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0) | |
87 | #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1) | |
88 | #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2) | |
89 | #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3) | |
90 | #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4) | |
91 | #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5) | |
92 | #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6) | |
93 | #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7) | |
94 | ||
95 | #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) | |
96 | #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) | |
97 | ||
67ce04bf | 98 | static const char *part_probes[] = { "cmdlinepart", NULL }; |
67ce04bf | 99 | |
f040d332 SG |
100 | /* oob info generated runtime depending on ecc algorithm and layout selected */ |
101 | static struct nand_ecclayout omap_oobinfo; | |
102 | /* Define some generic bad / good block scan pattern which are used | |
103 | * while scanning a device for factory marked good / bad blocks | |
104 | */ | |
105 | static uint8_t scan_ff_pattern[] = { 0xff }; | |
106 | static struct nand_bbt_descr bb_descrip_flashbased = { | |
107 | .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, | |
108 | .offs = 0, | |
109 | .len = 1, | |
110 | .pattern = scan_ff_pattern, | |
111 | }; | |
dfe32893 | 112 | |
59e9c5ae | 113 | |
67ce04bf VS |
114 | struct omap_nand_info { |
115 | struct nand_hw_control controller; | |
116 | struct omap_nand_platform_data *pdata; | |
117 | struct mtd_info mtd; | |
118 | struct mtd_partition *parts; | |
119 | struct nand_chip nand; | |
120 | struct platform_device *pdev; | |
121 | ||
122 | int gpmc_cs; | |
123 | unsigned long phys_base; | |
dfe32893 | 124 | struct completion comp; |
125 | int dma_ch; | |
4e070376 SG |
126 | int gpmc_irq; |
127 | enum { | |
128 | OMAP_NAND_IO_READ = 0, /* read */ | |
129 | OMAP_NAND_IO_WRITE, /* write */ | |
130 | } iomode; | |
131 | u_char *buf; | |
132 | int buf_len; | |
67ce04bf VS |
133 | }; |
134 | ||
67ce04bf VS |
135 | /** |
136 | * omap_hwcontrol - hardware specific access to control-lines | |
137 | * @mtd: MTD device structure | |
138 | * @cmd: command to device | |
139 | * @ctrl: | |
140 | * NAND_NCE: bit 0 -> don't care | |
141 | * NAND_CLE: bit 1 -> Command Latch | |
142 | * NAND_ALE: bit 2 -> Address Latch | |
143 | * | |
144 | * NOTE: boards may use different bits for these!! | |
145 | */ | |
146 | static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
147 | { | |
148 | struct omap_nand_info *info = container_of(mtd, | |
149 | struct omap_nand_info, mtd); | |
67ce04bf | 150 | |
2c01946c SG |
151 | if (cmd != NAND_CMD_NONE) { |
152 | if (ctrl & NAND_CLE) | |
153 | gpmc_nand_write(info->gpmc_cs, GPMC_NAND_COMMAND, cmd); | |
154 | ||
155 | else if (ctrl & NAND_ALE) | |
156 | gpmc_nand_write(info->gpmc_cs, GPMC_NAND_ADDRESS, cmd); | |
157 | ||
158 | else /* NAND_NCE */ | |
159 | gpmc_nand_write(info->gpmc_cs, GPMC_NAND_DATA, cmd); | |
160 | } | |
67ce04bf VS |
161 | } |
162 | ||
59e9c5ae | 163 | /** |
164 | * omap_read_buf8 - read data from NAND controller into buffer | |
165 | * @mtd: MTD device structure | |
166 | * @buf: buffer to store date | |
167 | * @len: number of bytes to read | |
168 | */ | |
169 | static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len) | |
170 | { | |
171 | struct nand_chip *nand = mtd->priv; | |
172 | ||
173 | ioread8_rep(nand->IO_ADDR_R, buf, len); | |
174 | } | |
175 | ||
176 | /** | |
177 | * omap_write_buf8 - write buffer to NAND controller | |
178 | * @mtd: MTD device structure | |
179 | * @buf: data buffer | |
180 | * @len: number of bytes to write | |
181 | */ | |
182 | static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len) | |
183 | { | |
184 | struct omap_nand_info *info = container_of(mtd, | |
185 | struct omap_nand_info, mtd); | |
186 | u_char *p = (u_char *)buf; | |
2c01946c | 187 | u32 status = 0; |
59e9c5ae | 188 | |
189 | while (len--) { | |
190 | iowrite8(*p++, info->nand.IO_ADDR_W); | |
2c01946c SG |
191 | /* wait until buffer is available for write */ |
192 | do { | |
193 | status = gpmc_read_status(GPMC_STATUS_BUFFER); | |
194 | } while (!status); | |
59e9c5ae | 195 | } |
196 | } | |
197 | ||
67ce04bf VS |
198 | /** |
199 | * omap_read_buf16 - read data from NAND controller into buffer | |
200 | * @mtd: MTD device structure | |
201 | * @buf: buffer to store date | |
202 | * @len: number of bytes to read | |
203 | */ | |
204 | static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len) | |
205 | { | |
206 | struct nand_chip *nand = mtd->priv; | |
207 | ||
59e9c5ae | 208 | ioread16_rep(nand->IO_ADDR_R, buf, len / 2); |
67ce04bf VS |
209 | } |
210 | ||
211 | /** | |
212 | * omap_write_buf16 - write buffer to NAND controller | |
213 | * @mtd: MTD device structure | |
214 | * @buf: data buffer | |
215 | * @len: number of bytes to write | |
216 | */ | |
217 | static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len) | |
218 | { | |
219 | struct omap_nand_info *info = container_of(mtd, | |
220 | struct omap_nand_info, mtd); | |
221 | u16 *p = (u16 *) buf; | |
2c01946c | 222 | u32 status = 0; |
67ce04bf VS |
223 | /* FIXME try bursts of writesw() or DMA ... */ |
224 | len >>= 1; | |
225 | ||
226 | while (len--) { | |
59e9c5ae | 227 | iowrite16(*p++, info->nand.IO_ADDR_W); |
2c01946c SG |
228 | /* wait until buffer is available for write */ |
229 | do { | |
230 | status = gpmc_read_status(GPMC_STATUS_BUFFER); | |
231 | } while (!status); | |
67ce04bf VS |
232 | } |
233 | } | |
59e9c5ae | 234 | |
235 | /** | |
236 | * omap_read_buf_pref - read data from NAND controller into buffer | |
237 | * @mtd: MTD device structure | |
238 | * @buf: buffer to store date | |
239 | * @len: number of bytes to read | |
240 | */ | |
241 | static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len) | |
242 | { | |
243 | struct omap_nand_info *info = container_of(mtd, | |
244 | struct omap_nand_info, mtd); | |
2c01946c | 245 | uint32_t r_count = 0; |
59e9c5ae | 246 | int ret = 0; |
247 | u32 *p = (u32 *)buf; | |
248 | ||
249 | /* take care of subpage reads */ | |
c3341d0c VS |
250 | if (len % 4) { |
251 | if (info->nand.options & NAND_BUSWIDTH_16) | |
252 | omap_read_buf16(mtd, buf, len % 4); | |
253 | else | |
254 | omap_read_buf8(mtd, buf, len % 4); | |
255 | p = (u32 *) (buf + len % 4); | |
256 | len -= len % 4; | |
59e9c5ae | 257 | } |
59e9c5ae | 258 | |
259 | /* configure and start prefetch transfer */ | |
317379a9 SG |
260 | ret = gpmc_prefetch_enable(info->gpmc_cs, |
261 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0); | |
59e9c5ae | 262 | if (ret) { |
263 | /* PFPW engine is busy, use cpu copy method */ | |
264 | if (info->nand.options & NAND_BUSWIDTH_16) | |
c5d8c0ca | 265 | omap_read_buf16(mtd, (u_char *)p, len); |
59e9c5ae | 266 | else |
c5d8c0ca | 267 | omap_read_buf8(mtd, (u_char *)p, len); |
59e9c5ae | 268 | } else { |
269 | do { | |
2c01946c SG |
270 | r_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT); |
271 | r_count = r_count >> 2; | |
272 | ioread32_rep(info->nand.IO_ADDR_R, p, r_count); | |
59e9c5ae | 273 | p += r_count; |
274 | len -= r_count << 2; | |
275 | } while (len); | |
59e9c5ae | 276 | /* disable and stop the PFPW engine */ |
948d38e7 | 277 | gpmc_prefetch_reset(info->gpmc_cs); |
59e9c5ae | 278 | } |
279 | } | |
280 | ||
281 | /** | |
282 | * omap_write_buf_pref - write buffer to NAND controller | |
283 | * @mtd: MTD device structure | |
284 | * @buf: data buffer | |
285 | * @len: number of bytes to write | |
286 | */ | |
287 | static void omap_write_buf_pref(struct mtd_info *mtd, | |
288 | const u_char *buf, int len) | |
289 | { | |
290 | struct omap_nand_info *info = container_of(mtd, | |
291 | struct omap_nand_info, mtd); | |
4e070376 | 292 | uint32_t w_count = 0; |
59e9c5ae | 293 | int i = 0, ret = 0; |
c5d8c0ca | 294 | u16 *p = (u16 *)buf; |
4e070376 | 295 | unsigned long tim, limit; |
59e9c5ae | 296 | |
297 | /* take care of subpage writes */ | |
298 | if (len % 2 != 0) { | |
2c01946c | 299 | writeb(*buf, info->nand.IO_ADDR_W); |
59e9c5ae | 300 | p = (u16 *)(buf + 1); |
301 | len--; | |
302 | } | |
303 | ||
304 | /* configure and start prefetch transfer */ | |
317379a9 SG |
305 | ret = gpmc_prefetch_enable(info->gpmc_cs, |
306 | PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1); | |
59e9c5ae | 307 | if (ret) { |
308 | /* PFPW engine is busy, use cpu copy method */ | |
309 | if (info->nand.options & NAND_BUSWIDTH_16) | |
c5d8c0ca | 310 | omap_write_buf16(mtd, (u_char *)p, len); |
59e9c5ae | 311 | else |
c5d8c0ca | 312 | omap_write_buf8(mtd, (u_char *)p, len); |
59e9c5ae | 313 | } else { |
2c01946c SG |
314 | while (len) { |
315 | w_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT); | |
316 | w_count = w_count >> 1; | |
59e9c5ae | 317 | for (i = 0; (i < w_count) && len; i++, len -= 2) |
2c01946c | 318 | iowrite16(*p++, info->nand.IO_ADDR_W); |
59e9c5ae | 319 | } |
2c01946c | 320 | /* wait for data to flushed-out before reset the prefetch */ |
4e070376 SG |
321 | tim = 0; |
322 | limit = (loops_per_jiffy * | |
323 | msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
324 | while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) | |
325 | cpu_relax(); | |
326 | ||
59e9c5ae | 327 | /* disable and stop the PFPW engine */ |
948d38e7 | 328 | gpmc_prefetch_reset(info->gpmc_cs); |
59e9c5ae | 329 | } |
330 | } | |
331 | ||
dfe32893 | 332 | /* |
333 | * omap_nand_dma_cb: callback on the completion of dma transfer | |
334 | * @lch: logical channel | |
335 | * @ch_satuts: channel status | |
336 | * @data: pointer to completion data structure | |
337 | */ | |
338 | static void omap_nand_dma_cb(int lch, u16 ch_status, void *data) | |
339 | { | |
340 | complete((struct completion *) data); | |
341 | } | |
342 | ||
343 | /* | |
344 | * omap_nand_dma_transfer: configer and start dma transfer | |
345 | * @mtd: MTD device structure | |
346 | * @addr: virtual address in RAM of source/destination | |
347 | * @len: number of data bytes to be transferred | |
348 | * @is_write: flag for read/write operation | |
349 | */ | |
350 | static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, | |
351 | unsigned int len, int is_write) | |
352 | { | |
353 | struct omap_nand_info *info = container_of(mtd, | |
354 | struct omap_nand_info, mtd); | |
dfe32893 | 355 | enum dma_data_direction dir = is_write ? DMA_TO_DEVICE : |
356 | DMA_FROM_DEVICE; | |
357 | dma_addr_t dma_addr; | |
358 | int ret; | |
4e070376 | 359 | unsigned long tim, limit; |
dfe32893 | 360 | |
317379a9 SG |
361 | /* The fifo depth is 64 bytes max. |
362 | * But configure the FIFO-threahold to 32 to get a sync at each frame | |
363 | * and frame length is 32 bytes. | |
dfe32893 | 364 | */ |
365 | int buf_len = len >> 6; | |
366 | ||
367 | if (addr >= high_memory) { | |
368 | struct page *p1; | |
369 | ||
370 | if (((size_t)addr & PAGE_MASK) != | |
371 | ((size_t)(addr + len - 1) & PAGE_MASK)) | |
372 | goto out_copy; | |
373 | p1 = vmalloc_to_page(addr); | |
374 | if (!p1) | |
375 | goto out_copy; | |
376 | addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK); | |
377 | } | |
378 | ||
379 | dma_addr = dma_map_single(&info->pdev->dev, addr, len, dir); | |
380 | if (dma_mapping_error(&info->pdev->dev, dma_addr)) { | |
381 | dev_err(&info->pdev->dev, | |
382 | "Couldn't DMA map a %d byte buffer\n", len); | |
383 | goto out_copy; | |
384 | } | |
385 | ||
386 | if (is_write) { | |
387 | omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, | |
388 | info->phys_base, 0, 0); | |
389 | omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC, | |
390 | dma_addr, 0, 0); | |
391 | omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32, | |
392 | 0x10, buf_len, OMAP_DMA_SYNC_FRAME, | |
393 | OMAP24XX_DMA_GPMC, OMAP_DMA_DST_SYNC); | |
394 | } else { | |
395 | omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, | |
396 | info->phys_base, 0, 0); | |
397 | omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC, | |
398 | dma_addr, 0, 0); | |
399 | omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32, | |
400 | 0x10, buf_len, OMAP_DMA_SYNC_FRAME, | |
401 | OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC); | |
402 | } | |
403 | /* configure and start prefetch transfer */ | |
317379a9 SG |
404 | ret = gpmc_prefetch_enable(info->gpmc_cs, |
405 | PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write); | |
dfe32893 | 406 | if (ret) |
4e070376 | 407 | /* PFPW engine is busy, use cpu copy method */ |
dfe32893 | 408 | goto out_copy; |
409 | ||
410 | init_completion(&info->comp); | |
411 | ||
412 | omap_start_dma(info->dma_ch); | |
413 | ||
414 | /* setup and start DMA using dma_addr */ | |
415 | wait_for_completion(&info->comp); | |
4e070376 SG |
416 | tim = 0; |
417 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
418 | while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) | |
419 | cpu_relax(); | |
dfe32893 | 420 | |
dfe32893 | 421 | /* disable and stop the PFPW engine */ |
f12f662f | 422 | gpmc_prefetch_reset(info->gpmc_cs); |
dfe32893 | 423 | |
424 | dma_unmap_single(&info->pdev->dev, dma_addr, len, dir); | |
425 | return 0; | |
426 | ||
427 | out_copy: | |
428 | if (info->nand.options & NAND_BUSWIDTH_16) | |
429 | is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len) | |
430 | : omap_write_buf16(mtd, (u_char *) addr, len); | |
431 | else | |
432 | is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len) | |
433 | : omap_write_buf8(mtd, (u_char *) addr, len); | |
434 | return 0; | |
435 | } | |
dfe32893 | 436 | |
437 | /** | |
438 | * omap_read_buf_dma_pref - read data from NAND controller into buffer | |
439 | * @mtd: MTD device structure | |
440 | * @buf: buffer to store date | |
441 | * @len: number of bytes to read | |
442 | */ | |
443 | static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len) | |
444 | { | |
445 | if (len <= mtd->oobsize) | |
446 | omap_read_buf_pref(mtd, buf, len); | |
447 | else | |
448 | /* start transfer in DMA mode */ | |
449 | omap_nand_dma_transfer(mtd, buf, len, 0x0); | |
450 | } | |
451 | ||
452 | /** | |
453 | * omap_write_buf_dma_pref - write buffer to NAND controller | |
454 | * @mtd: MTD device structure | |
455 | * @buf: data buffer | |
456 | * @len: number of bytes to write | |
457 | */ | |
458 | static void omap_write_buf_dma_pref(struct mtd_info *mtd, | |
459 | const u_char *buf, int len) | |
460 | { | |
461 | if (len <= mtd->oobsize) | |
462 | omap_write_buf_pref(mtd, buf, len); | |
463 | else | |
464 | /* start transfer in DMA mode */ | |
bdaefc41 | 465 | omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1); |
dfe32893 | 466 | } |
467 | ||
4e070376 SG |
468 | /* |
469 | * omap_nand_irq - GMPC irq handler | |
470 | * @this_irq: gpmc irq number | |
471 | * @dev: omap_nand_info structure pointer is passed here | |
472 | */ | |
473 | static irqreturn_t omap_nand_irq(int this_irq, void *dev) | |
474 | { | |
475 | struct omap_nand_info *info = (struct omap_nand_info *) dev; | |
476 | u32 bytes; | |
477 | u32 irq_stat; | |
478 | ||
479 | irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS); | |
480 | bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT); | |
481 | bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ | |
482 | if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ | |
483 | if (irq_stat & 0x2) | |
484 | goto done; | |
485 | ||
486 | if (info->buf_len && (info->buf_len < bytes)) | |
487 | bytes = info->buf_len; | |
488 | else if (!info->buf_len) | |
489 | bytes = 0; | |
490 | iowrite32_rep(info->nand.IO_ADDR_W, | |
491 | (u32 *)info->buf, bytes >> 2); | |
492 | info->buf = info->buf + bytes; | |
493 | info->buf_len -= bytes; | |
494 | ||
495 | } else { | |
496 | ioread32_rep(info->nand.IO_ADDR_R, | |
497 | (u32 *)info->buf, bytes >> 2); | |
498 | info->buf = info->buf + bytes; | |
499 | ||
500 | if (irq_stat & 0x2) | |
501 | goto done; | |
502 | } | |
503 | gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat); | |
504 | ||
505 | return IRQ_HANDLED; | |
506 | ||
507 | done: | |
508 | complete(&info->comp); | |
509 | /* disable irq */ | |
510 | gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0); | |
511 | ||
512 | /* clear status */ | |
513 | gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat); | |
514 | ||
515 | return IRQ_HANDLED; | |
516 | } | |
517 | ||
518 | /* | |
519 | * omap_read_buf_irq_pref - read data from NAND controller into buffer | |
520 | * @mtd: MTD device structure | |
521 | * @buf: buffer to store date | |
522 | * @len: number of bytes to read | |
523 | */ | |
524 | static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) | |
525 | { | |
526 | struct omap_nand_info *info = container_of(mtd, | |
527 | struct omap_nand_info, mtd); | |
528 | int ret = 0; | |
529 | ||
530 | if (len <= mtd->oobsize) { | |
531 | omap_read_buf_pref(mtd, buf, len); | |
532 | return; | |
533 | } | |
534 | ||
535 | info->iomode = OMAP_NAND_IO_READ; | |
536 | info->buf = buf; | |
537 | init_completion(&info->comp); | |
538 | ||
539 | /* configure and start prefetch transfer */ | |
317379a9 SG |
540 | ret = gpmc_prefetch_enable(info->gpmc_cs, |
541 | PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0); | |
4e070376 SG |
542 | if (ret) |
543 | /* PFPW engine is busy, use cpu copy method */ | |
544 | goto out_copy; | |
545 | ||
546 | info->buf_len = len; | |
547 | /* enable irq */ | |
548 | gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, | |
549 | (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT)); | |
550 | ||
551 | /* waiting for read to complete */ | |
552 | wait_for_completion(&info->comp); | |
553 | ||
554 | /* disable and stop the PFPW engine */ | |
555 | gpmc_prefetch_reset(info->gpmc_cs); | |
556 | return; | |
557 | ||
558 | out_copy: | |
559 | if (info->nand.options & NAND_BUSWIDTH_16) | |
560 | omap_read_buf16(mtd, buf, len); | |
561 | else | |
562 | omap_read_buf8(mtd, buf, len); | |
563 | } | |
564 | ||
565 | /* | |
566 | * omap_write_buf_irq_pref - write buffer to NAND controller | |
567 | * @mtd: MTD device structure | |
568 | * @buf: data buffer | |
569 | * @len: number of bytes to write | |
570 | */ | |
571 | static void omap_write_buf_irq_pref(struct mtd_info *mtd, | |
572 | const u_char *buf, int len) | |
573 | { | |
574 | struct omap_nand_info *info = container_of(mtd, | |
575 | struct omap_nand_info, mtd); | |
576 | int ret = 0; | |
577 | unsigned long tim, limit; | |
578 | ||
579 | if (len <= mtd->oobsize) { | |
580 | omap_write_buf_pref(mtd, buf, len); | |
581 | return; | |
582 | } | |
583 | ||
584 | info->iomode = OMAP_NAND_IO_WRITE; | |
585 | info->buf = (u_char *) buf; | |
586 | init_completion(&info->comp); | |
587 | ||
317379a9 SG |
588 | /* configure and start prefetch transfer : size=24 */ |
589 | ret = gpmc_prefetch_enable(info->gpmc_cs, | |
590 | (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1); | |
4e070376 SG |
591 | if (ret) |
592 | /* PFPW engine is busy, use cpu copy method */ | |
593 | goto out_copy; | |
594 | ||
595 | info->buf_len = len; | |
596 | /* enable irq */ | |
597 | gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, | |
598 | (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT)); | |
599 | ||
600 | /* waiting for write to complete */ | |
601 | wait_for_completion(&info->comp); | |
602 | /* wait for data to flushed-out before reset the prefetch */ | |
603 | tim = 0; | |
604 | limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); | |
605 | while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) | |
606 | cpu_relax(); | |
607 | ||
608 | /* disable and stop the PFPW engine */ | |
609 | gpmc_prefetch_reset(info->gpmc_cs); | |
610 | return; | |
611 | ||
612 | out_copy: | |
613 | if (info->nand.options & NAND_BUSWIDTH_16) | |
614 | omap_write_buf16(mtd, buf, len); | |
615 | else | |
616 | omap_write_buf8(mtd, buf, len); | |
617 | } | |
618 | ||
67ce04bf VS |
619 | /** |
620 | * omap_verify_buf - Verify chip data against buffer | |
621 | * @mtd: MTD device structure | |
622 | * @buf: buffer containing the data to compare | |
623 | * @len: number of bytes to compare | |
624 | */ | |
625 | static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len) | |
626 | { | |
627 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
628 | mtd); | |
629 | u16 *p = (u16 *) buf; | |
630 | ||
631 | len >>= 1; | |
632 | while (len--) { | |
633 | if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R))) | |
634 | return -EFAULT; | |
635 | } | |
636 | ||
637 | return 0; | |
638 | } | |
639 | ||
67ce04bf VS |
640 | /** |
641 | * gen_true_ecc - This function will generate true ECC value | |
642 | * @ecc_buf: buffer to store ecc code | |
643 | * | |
644 | * This generated true ECC value can be used when correcting | |
645 | * data read from NAND flash memory core | |
646 | */ | |
647 | static void gen_true_ecc(u8 *ecc_buf) | |
648 | { | |
649 | u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) | | |
650 | ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8); | |
651 | ||
652 | ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | | |
653 | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); | |
654 | ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | | |
655 | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); | |
656 | ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | | |
657 | P1e(tmp) | P2048o(tmp) | P2048e(tmp)); | |
658 | } | |
659 | ||
660 | /** | |
661 | * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data | |
662 | * @ecc_data1: ecc code from nand spare area | |
663 | * @ecc_data2: ecc code from hardware register obtained from hardware ecc | |
664 | * @page_data: page data | |
665 | * | |
666 | * This function compares two ECC's and indicates if there is an error. | |
667 | * If the error can be corrected it will be corrected to the buffer. | |
74f1b724 JO |
668 | * If there is no error, %0 is returned. If there is an error but it |
669 | * was corrected, %1 is returned. Otherwise, %-1 is returned. | |
67ce04bf VS |
670 | */ |
671 | static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */ | |
672 | u8 *ecc_data2, /* read from register */ | |
673 | u8 *page_data) | |
674 | { | |
675 | uint i; | |
676 | u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; | |
677 | u8 comp0_bit[8], comp1_bit[8], comp2_bit[8]; | |
678 | u8 ecc_bit[24]; | |
679 | u8 ecc_sum = 0; | |
680 | u8 find_bit = 0; | |
681 | uint find_byte = 0; | |
682 | int isEccFF; | |
683 | ||
684 | isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF); | |
685 | ||
686 | gen_true_ecc(ecc_data1); | |
687 | gen_true_ecc(ecc_data2); | |
688 | ||
689 | for (i = 0; i <= 2; i++) { | |
690 | *(ecc_data1 + i) = ~(*(ecc_data1 + i)); | |
691 | *(ecc_data2 + i) = ~(*(ecc_data2 + i)); | |
692 | } | |
693 | ||
694 | for (i = 0; i < 8; i++) { | |
695 | tmp0_bit[i] = *ecc_data1 % 2; | |
696 | *ecc_data1 = *ecc_data1 / 2; | |
697 | } | |
698 | ||
699 | for (i = 0; i < 8; i++) { | |
700 | tmp1_bit[i] = *(ecc_data1 + 1) % 2; | |
701 | *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2; | |
702 | } | |
703 | ||
704 | for (i = 0; i < 8; i++) { | |
705 | tmp2_bit[i] = *(ecc_data1 + 2) % 2; | |
706 | *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2; | |
707 | } | |
708 | ||
709 | for (i = 0; i < 8; i++) { | |
710 | comp0_bit[i] = *ecc_data2 % 2; | |
711 | *ecc_data2 = *ecc_data2 / 2; | |
712 | } | |
713 | ||
714 | for (i = 0; i < 8; i++) { | |
715 | comp1_bit[i] = *(ecc_data2 + 1) % 2; | |
716 | *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2; | |
717 | } | |
718 | ||
719 | for (i = 0; i < 8; i++) { | |
720 | comp2_bit[i] = *(ecc_data2 + 2) % 2; | |
721 | *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2; | |
722 | } | |
723 | ||
724 | for (i = 0; i < 6; i++) | |
725 | ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; | |
726 | ||
727 | for (i = 0; i < 8; i++) | |
728 | ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; | |
729 | ||
730 | for (i = 0; i < 8; i++) | |
731 | ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; | |
732 | ||
733 | ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; | |
734 | ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; | |
735 | ||
736 | for (i = 0; i < 24; i++) | |
737 | ecc_sum += ecc_bit[i]; | |
738 | ||
739 | switch (ecc_sum) { | |
740 | case 0: | |
741 | /* Not reached because this function is not called if | |
742 | * ECC values are equal | |
743 | */ | |
744 | return 0; | |
745 | ||
746 | case 1: | |
747 | /* Uncorrectable error */ | |
748 | DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n"); | |
749 | return -1; | |
750 | ||
751 | case 11: | |
752 | /* UN-Correctable error */ | |
753 | DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR B\n"); | |
754 | return -1; | |
755 | ||
756 | case 12: | |
757 | /* Correctable error */ | |
758 | find_byte = (ecc_bit[23] << 8) + | |
759 | (ecc_bit[21] << 7) + | |
760 | (ecc_bit[19] << 6) + | |
761 | (ecc_bit[17] << 5) + | |
762 | (ecc_bit[15] << 4) + | |
763 | (ecc_bit[13] << 3) + | |
764 | (ecc_bit[11] << 2) + | |
765 | (ecc_bit[9] << 1) + | |
766 | ecc_bit[7]; | |
767 | ||
768 | find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; | |
769 | ||
770 | DEBUG(MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at " | |
771 | "offset: %d, bit: %d\n", find_byte, find_bit); | |
772 | ||
773 | page_data[find_byte] ^= (1 << find_bit); | |
774 | ||
74f1b724 | 775 | return 1; |
67ce04bf VS |
776 | default: |
777 | if (isEccFF) { | |
778 | if (ecc_data2[0] == 0 && | |
779 | ecc_data2[1] == 0 && | |
780 | ecc_data2[2] == 0) | |
781 | return 0; | |
782 | } | |
783 | DEBUG(MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n"); | |
784 | return -1; | |
785 | } | |
786 | } | |
787 | ||
788 | /** | |
789 | * omap_correct_data - Compares the ECC read with HW generated ECC | |
790 | * @mtd: MTD device structure | |
791 | * @dat: page data | |
792 | * @read_ecc: ecc read from nand flash | |
793 | * @calc_ecc: ecc read from HW ECC registers | |
794 | * | |
795 | * Compares the ecc read from nand spare area with ECC registers values | |
74f1b724 JO |
796 | * and if ECC's mismatched, it will call 'omap_compare_ecc' for error |
797 | * detection and correction. If there are no errors, %0 is returned. If | |
798 | * there were errors and all of the errors were corrected, the number of | |
799 | * corrected errors is returned. If uncorrectable errors exist, %-1 is | |
800 | * returned. | |
67ce04bf VS |
801 | */ |
802 | static int omap_correct_data(struct mtd_info *mtd, u_char *dat, | |
803 | u_char *read_ecc, u_char *calc_ecc) | |
804 | { | |
805 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
806 | mtd); | |
807 | int blockCnt = 0, i = 0, ret = 0; | |
74f1b724 | 808 | int stat = 0; |
67ce04bf VS |
809 | |
810 | /* Ex NAND_ECC_HW12_2048 */ | |
811 | if ((info->nand.ecc.mode == NAND_ECC_HW) && | |
812 | (info->nand.ecc.size == 2048)) | |
813 | blockCnt = 4; | |
814 | else | |
815 | blockCnt = 1; | |
816 | ||
817 | for (i = 0; i < blockCnt; i++) { | |
818 | if (memcmp(read_ecc, calc_ecc, 3) != 0) { | |
819 | ret = omap_compare_ecc(read_ecc, calc_ecc, dat); | |
820 | if (ret < 0) | |
821 | return ret; | |
74f1b724 JO |
822 | /* keep track of the number of corrected errors */ |
823 | stat += ret; | |
67ce04bf VS |
824 | } |
825 | read_ecc += 3; | |
826 | calc_ecc += 3; | |
827 | dat += 512; | |
828 | } | |
74f1b724 | 829 | return stat; |
67ce04bf VS |
830 | } |
831 | ||
832 | /** | |
833 | * omap_calcuate_ecc - Generate non-inverted ECC bytes. | |
834 | * @mtd: MTD device structure | |
835 | * @dat: The pointer to data on which ecc is computed | |
836 | * @ecc_code: The ecc_code buffer | |
837 | * | |
838 | * Using noninverted ECC can be considered ugly since writing a blank | |
839 | * page ie. padding will clear the ECC bytes. This is no problem as long | |
840 | * nobody is trying to write data on the seemingly unused page. Reading | |
841 | * an erased page will produce an ECC mismatch between generated and read | |
842 | * ECC bytes that has to be dealt with separately. | |
843 | */ | |
844 | static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, | |
845 | u_char *ecc_code) | |
846 | { | |
847 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
848 | mtd); | |
2c01946c | 849 | return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code); |
67ce04bf VS |
850 | } |
851 | ||
852 | /** | |
853 | * omap_enable_hwecc - This function enables the hardware ecc functionality | |
854 | * @mtd: MTD device structure | |
855 | * @mode: Read/Write mode | |
856 | */ | |
857 | static void omap_enable_hwecc(struct mtd_info *mtd, int mode) | |
858 | { | |
859 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
860 | mtd); | |
861 | struct nand_chip *chip = mtd->priv; | |
862 | unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; | |
67ce04bf | 863 | |
2c01946c | 864 | gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size); |
67ce04bf | 865 | } |
2c01946c | 866 | |
67ce04bf VS |
867 | /** |
868 | * omap_wait - wait until the command is done | |
869 | * @mtd: MTD device structure | |
870 | * @chip: NAND Chip structure | |
871 | * | |
872 | * Wait function is called during Program and erase operations and | |
873 | * the way it is called from MTD layer, we should wait till the NAND | |
874 | * chip is ready after the programming/erase operation has completed. | |
875 | * | |
876 | * Erase can take up to 400ms and program up to 20ms according to | |
877 | * general NAND and SmartMedia specs | |
878 | */ | |
879 | static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
880 | { | |
881 | struct nand_chip *this = mtd->priv; | |
882 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
883 | mtd); | |
884 | unsigned long timeo = jiffies; | |
c276aca4 | 885 | int status = NAND_STATUS_FAIL, state = this->state; |
67ce04bf VS |
886 | |
887 | if (state == FL_ERASING) | |
888 | timeo += (HZ * 400) / 1000; | |
889 | else | |
890 | timeo += (HZ * 20) / 1000; | |
891 | ||
2c01946c SG |
892 | gpmc_nand_write(info->gpmc_cs, |
893 | GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF)); | |
67ce04bf | 894 | while (time_before(jiffies, timeo)) { |
2c01946c | 895 | status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA); |
c276aca4 | 896 | if (status & NAND_STATUS_READY) |
67ce04bf | 897 | break; |
c276aca4 | 898 | cond_resched(); |
67ce04bf VS |
899 | } |
900 | return status; | |
901 | } | |
902 | ||
903 | /** | |
904 | * omap_dev_ready - calls the platform specific dev_ready function | |
905 | * @mtd: MTD device structure | |
906 | */ | |
907 | static int omap_dev_ready(struct mtd_info *mtd) | |
908 | { | |
2c01946c | 909 | unsigned int val = 0; |
67ce04bf VS |
910 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
911 | mtd); | |
67ce04bf | 912 | |
2c01946c | 913 | val = gpmc_read_status(GPMC_GET_IRQ_STATUS); |
67ce04bf VS |
914 | if ((val & 0x100) == 0x100) { |
915 | /* Clear IRQ Interrupt */ | |
916 | val |= 0x100; | |
917 | val &= ~(0x0); | |
2c01946c | 918 | gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val); |
67ce04bf VS |
919 | } else { |
920 | unsigned int cnt = 0; | |
921 | while (cnt++ < 0x1FF) { | |
922 | if ((val & 0x100) == 0x100) | |
923 | return 0; | |
2c01946c | 924 | val = gpmc_read_status(GPMC_GET_IRQ_STATUS); |
67ce04bf VS |
925 | } |
926 | } | |
927 | ||
928 | return 1; | |
929 | } | |
930 | ||
931 | static int __devinit omap_nand_probe(struct platform_device *pdev) | |
932 | { | |
933 | struct omap_nand_info *info; | |
934 | struct omap_nand_platform_data *pdata; | |
935 | int err; | |
f040d332 | 936 | int i, offset; |
67ce04bf VS |
937 | |
938 | pdata = pdev->dev.platform_data; | |
939 | if (pdata == NULL) { | |
940 | dev_err(&pdev->dev, "platform data missing\n"); | |
941 | return -ENODEV; | |
942 | } | |
943 | ||
944 | info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL); | |
945 | if (!info) | |
946 | return -ENOMEM; | |
947 | ||
948 | platform_set_drvdata(pdev, info); | |
949 | ||
950 | spin_lock_init(&info->controller.lock); | |
951 | init_waitqueue_head(&info->controller.wq); | |
952 | ||
953 | info->pdev = pdev; | |
954 | ||
955 | info->gpmc_cs = pdata->cs; | |
2f70a1e9 | 956 | info->phys_base = pdata->phys_base; |
67ce04bf VS |
957 | |
958 | info->mtd.priv = &info->nand; | |
959 | info->mtd.name = dev_name(&pdev->dev); | |
960 | info->mtd.owner = THIS_MODULE; | |
961 | ||
d5ce2b65 | 962 | info->nand.options = pdata->devsize; |
2f70a1e9 | 963 | info->nand.options |= NAND_SKIP_BBTSCAN; |
67ce04bf VS |
964 | |
965 | /* NAND write protect off */ | |
2c01946c | 966 | gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0); |
67ce04bf VS |
967 | |
968 | if (!request_mem_region(info->phys_base, NAND_IO_SIZE, | |
969 | pdev->dev.driver->name)) { | |
970 | err = -EBUSY; | |
2f70a1e9 | 971 | goto out_free_info; |
67ce04bf VS |
972 | } |
973 | ||
974 | info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE); | |
975 | if (!info->nand.IO_ADDR_R) { | |
976 | err = -ENOMEM; | |
977 | goto out_release_mem_region; | |
978 | } | |
59e9c5ae | 979 | |
67ce04bf VS |
980 | info->nand.controller = &info->controller; |
981 | ||
982 | info->nand.IO_ADDR_W = info->nand.IO_ADDR_R; | |
983 | info->nand.cmd_ctrl = omap_hwcontrol; | |
984 | ||
67ce04bf VS |
985 | /* |
986 | * If RDY/BSY line is connected to OMAP then use the omap ready | |
987 | * funcrtion and the generic nand_wait function which reads the status | |
988 | * register after monitoring the RDY/BSY line.Otherwise use a standard | |
989 | * chip delay which is slightly more than tR (AC Timing) of the NAND | |
990 | * device and read status register until you get a failure or success | |
991 | */ | |
992 | if (pdata->dev_ready) { | |
993 | info->nand.dev_ready = omap_dev_ready; | |
994 | info->nand.chip_delay = 0; | |
995 | } else { | |
996 | info->nand.waitfunc = omap_wait; | |
997 | info->nand.chip_delay = 50; | |
998 | } | |
999 | ||
1b0b323c SG |
1000 | switch (pdata->xfer_type) { |
1001 | case NAND_OMAP_PREFETCH_POLLED: | |
59e9c5ae | 1002 | info->nand.read_buf = omap_read_buf_pref; |
1003 | info->nand.write_buf = omap_write_buf_pref; | |
1b0b323c SG |
1004 | break; |
1005 | ||
1006 | case NAND_OMAP_POLLED: | |
59e9c5ae | 1007 | if (info->nand.options & NAND_BUSWIDTH_16) { |
1008 | info->nand.read_buf = omap_read_buf16; | |
1009 | info->nand.write_buf = omap_write_buf16; | |
1010 | } else { | |
1011 | info->nand.read_buf = omap_read_buf8; | |
1012 | info->nand.write_buf = omap_write_buf8; | |
1013 | } | |
1b0b323c SG |
1014 | break; |
1015 | ||
1016 | case NAND_OMAP_PREFETCH_DMA: | |
1017 | err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND", | |
1018 | omap_nand_dma_cb, &info->comp, &info->dma_ch); | |
1019 | if (err < 0) { | |
1020 | info->dma_ch = -1; | |
1021 | dev_err(&pdev->dev, "DMA request failed!\n"); | |
1022 | goto out_release_mem_region; | |
1023 | } else { | |
1024 | omap_set_dma_dest_burst_mode(info->dma_ch, | |
1025 | OMAP_DMA_DATA_BURST_16); | |
1026 | omap_set_dma_src_burst_mode(info->dma_ch, | |
1027 | OMAP_DMA_DATA_BURST_16); | |
1028 | ||
1029 | info->nand.read_buf = omap_read_buf_dma_pref; | |
1030 | info->nand.write_buf = omap_write_buf_dma_pref; | |
1031 | } | |
1032 | break; | |
1033 | ||
4e070376 SG |
1034 | case NAND_OMAP_PREFETCH_IRQ: |
1035 | err = request_irq(pdata->gpmc_irq, | |
1036 | omap_nand_irq, IRQF_SHARED, "gpmc-nand", info); | |
1037 | if (err) { | |
1038 | dev_err(&pdev->dev, "requesting irq(%d) error:%d", | |
1039 | pdata->gpmc_irq, err); | |
1040 | goto out_release_mem_region; | |
1041 | } else { | |
1042 | info->gpmc_irq = pdata->gpmc_irq; | |
1043 | info->nand.read_buf = omap_read_buf_irq_pref; | |
1044 | info->nand.write_buf = omap_write_buf_irq_pref; | |
1045 | } | |
1046 | break; | |
1047 | ||
1b0b323c SG |
1048 | default: |
1049 | dev_err(&pdev->dev, | |
1050 | "xfer_type(%d) not supported!\n", pdata->xfer_type); | |
1051 | err = -EINVAL; | |
1052 | goto out_release_mem_region; | |
59e9c5ae | 1053 | } |
59e9c5ae | 1054 | |
59e9c5ae | 1055 | info->nand.verify_buf = omap_verify_buf; |
67ce04bf | 1056 | |
f3d73f36 SG |
1057 | /* selsect the ecc type */ |
1058 | if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT) | |
1059 | info->nand.ecc.mode = NAND_ECC_SOFT; | |
f040d332 SG |
1060 | else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) || |
1061 | (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) { | |
f3d73f36 SG |
1062 | info->nand.ecc.bytes = 3; |
1063 | info->nand.ecc.size = 512; | |
1064 | info->nand.ecc.calculate = omap_calculate_ecc; | |
1065 | info->nand.ecc.hwctl = omap_enable_hwecc; | |
1066 | info->nand.ecc.correct = omap_correct_data; | |
1067 | info->nand.ecc.mode = NAND_ECC_HW; | |
1068 | } | |
67ce04bf VS |
1069 | |
1070 | /* DIP switches on some boards change between 8 and 16 bit | |
1071 | * bus widths for flash. Try the other width if the first try fails. | |
1072 | */ | |
a80f1c1f | 1073 | if (nand_scan_ident(&info->mtd, 1, NULL)) { |
67ce04bf | 1074 | info->nand.options ^= NAND_BUSWIDTH_16; |
a80f1c1f | 1075 | if (nand_scan_ident(&info->mtd, 1, NULL)) { |
67ce04bf VS |
1076 | err = -ENXIO; |
1077 | goto out_release_mem_region; | |
1078 | } | |
1079 | } | |
1080 | ||
f040d332 SG |
1081 | /* rom code layout */ |
1082 | if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) { | |
1083 | ||
1084 | if (info->nand.options & NAND_BUSWIDTH_16) | |
1085 | offset = 2; | |
1086 | else { | |
1087 | offset = 1; | |
1088 | info->nand.badblock_pattern = &bb_descrip_flashbased; | |
1089 | } | |
1090 | omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16); | |
1091 | for (i = 0; i < omap_oobinfo.eccbytes; i++) | |
1092 | omap_oobinfo.eccpos[i] = i+offset; | |
1093 | ||
1094 | omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes; | |
1095 | omap_oobinfo.oobfree->length = info->mtd.oobsize - | |
1096 | (offset + omap_oobinfo.eccbytes); | |
1097 | ||
1098 | info->nand.ecc.layout = &omap_oobinfo; | |
1099 | } | |
1b0b323c | 1100 | |
a80f1c1f JW |
1101 | /* second phase scan */ |
1102 | if (nand_scan_tail(&info->mtd)) { | |
1103 | err = -ENXIO; | |
1104 | goto out_release_mem_region; | |
1105 | } | |
1106 | ||
67ce04bf VS |
1107 | err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0); |
1108 | if (err > 0) | |
54e07f54 | 1109 | mtd_device_register(&info->mtd, info->parts, err); |
67ce04bf | 1110 | else if (pdata->parts) |
54e07f54 | 1111 | mtd_device_register(&info->mtd, pdata->parts, pdata->nr_parts); |
67ce04bf | 1112 | else |
54e07f54 | 1113 | mtd_device_register(&info->mtd, NULL, 0); |
67ce04bf VS |
1114 | |
1115 | platform_set_drvdata(pdev, &info->mtd); | |
1116 | ||
1117 | return 0; | |
1118 | ||
1119 | out_release_mem_region: | |
1120 | release_mem_region(info->phys_base, NAND_IO_SIZE); | |
67ce04bf VS |
1121 | out_free_info: |
1122 | kfree(info); | |
1123 | ||
1124 | return err; | |
1125 | } | |
1126 | ||
1127 | static int omap_nand_remove(struct platform_device *pdev) | |
1128 | { | |
1129 | struct mtd_info *mtd = platform_get_drvdata(pdev); | |
f35b6eda VS |
1130 | struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, |
1131 | mtd); | |
67ce04bf VS |
1132 | |
1133 | platform_set_drvdata(pdev, NULL); | |
1b0b323c | 1134 | if (info->dma_ch != -1) |
dfe32893 | 1135 | omap_free_dma(info->dma_ch); |
1136 | ||
4e070376 SG |
1137 | if (info->gpmc_irq) |
1138 | free_irq(info->gpmc_irq, info); | |
1139 | ||
67ce04bf VS |
1140 | /* Release NAND device, its internal structures and partitions */ |
1141 | nand_release(&info->mtd); | |
2c01946c | 1142 | iounmap(info->nand.IO_ADDR_R); |
67ce04bf VS |
1143 | kfree(&info->mtd); |
1144 | return 0; | |
1145 | } | |
1146 | ||
1147 | static struct platform_driver omap_nand_driver = { | |
1148 | .probe = omap_nand_probe, | |
1149 | .remove = omap_nand_remove, | |
1150 | .driver = { | |
1151 | .name = DRIVER_NAME, | |
1152 | .owner = THIS_MODULE, | |
1153 | }, | |
1154 | }; | |
1155 | ||
1156 | static int __init omap_nand_init(void) | |
1157 | { | |
1b0b323c | 1158 | pr_info("%s driver initializing\n", DRIVER_NAME); |
dfe32893 | 1159 | |
67ce04bf VS |
1160 | return platform_driver_register(&omap_nand_driver); |
1161 | } | |
1162 | ||
1163 | static void __exit omap_nand_exit(void) | |
1164 | { | |
1165 | platform_driver_unregister(&omap_nand_driver); | |
1166 | } | |
1167 | ||
1168 | module_init(omap_nand_init); | |
1169 | module_exit(omap_nand_exit); | |
1170 | ||
c804c733 | 1171 | MODULE_ALIAS("platform:" DRIVER_NAME); |
67ce04bf VS |
1172 | MODULE_LICENSE("GPL"); |
1173 | MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards"); |