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2a1dba29 TP |
1 | /* |
2 | * drivers/mtd/nand/orion_nand.c | |
3 | * | |
4 | * NAND support for Marvell Orion SoC platforms | |
5 | * | |
6 | * Tzachi Perelstein <tzachi@marvell.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
13 | #include <linux/slab.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/platform_device.h> | |
a0fabf72 | 16 | #include <linux/of.h> |
2a1dba29 TP |
17 | #include <linux/mtd/mtd.h> |
18 | #include <linux/mtd/nand.h> | |
19 | #include <linux/mtd/partitions.h> | |
9c2bd504 AL |
20 | #include <linux/clk.h> |
21 | #include <linux/err.h> | |
a0fa0b66 | 22 | #include <linux/io.h> |
2a1dba29 | 23 | #include <asm/sizes.h> |
c02cecb9 | 24 | #include <linux/platform_data/mtd-orion_nand.h> |
2a1dba29 | 25 | |
675b11d9 SB |
26 | struct orion_nand_info { |
27 | struct nand_chip chip; | |
28 | struct clk *clk; | |
29 | }; | |
30 | ||
2a1dba29 TP |
31 | static void orion_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
32 | { | |
4bd4ebcc | 33 | struct nand_chip *nc = mtd_to_nand(mtd); |
d699ed25 | 34 | struct orion_nand_data *board = nand_get_controller_data(nc); |
2a1dba29 TP |
35 | u32 offs; |
36 | ||
37 | if (cmd == NAND_CMD_NONE) | |
38 | return; | |
39 | ||
40 | if (ctrl & NAND_CLE) | |
41 | offs = (1 << board->cle); | |
42 | else if (ctrl & NAND_ALE) | |
43 | offs = (1 << board->ale); | |
44 | else | |
45 | return; | |
46 | ||
47 | if (nc->options & NAND_BUSWIDTH_16) | |
48 | offs <<= 1; | |
49 | ||
50 | writeb(cmd, nc->IO_ADDR_W + offs); | |
51 | } | |
52 | ||
bfee1a43 NP |
53 | static void orion_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
54 | { | |
4bd4ebcc | 55 | struct nand_chip *chip = mtd_to_nand(mtd); |
bfee1a43 NP |
56 | void __iomem *io_base = chip->IO_ADDR_R; |
57 | uint64_t *buf64; | |
58 | int i = 0; | |
59 | ||
60 | while (len && (unsigned long)buf & 7) { | |
61 | *buf++ = readb(io_base); | |
62 | len--; | |
63 | } | |
64 | buf64 = (uint64_t *)buf; | |
65 | while (i < len/8) { | |
a88a2b88 PZ |
66 | /* |
67 | * Since GCC has no proper constraint (PR 43518) | |
68 | * force x variable to r2/r3 registers as ldrd instruction | |
69 | * requires first register to be even. | |
70 | */ | |
71 | register uint64_t x asm ("r2"); | |
72 | ||
94da210a | 73 | asm volatile ("ldrd\t%0, [%1]" : "=&r" (x) : "r" (io_base)); |
bfee1a43 NP |
74 | buf64[i++] = x; |
75 | } | |
76 | i *= 8; | |
77 | while (i < len) | |
78 | buf[i++] = readb(io_base); | |
79 | } | |
80 | ||
2a1dba29 TP |
81 | static int __init orion_nand_probe(struct platform_device *pdev) |
82 | { | |
675b11d9 | 83 | struct orion_nand_info *info; |
2a1dba29 TP |
84 | struct mtd_info *mtd; |
85 | struct nand_chip *nc; | |
86 | struct orion_nand_data *board; | |
e9903060 | 87 | struct resource *res; |
2a1dba29 TP |
88 | void __iomem *io_base; |
89 | int ret = 0; | |
a0fabf72 | 90 | u32 val = 0; |
2a1dba29 | 91 | |
675b11d9 SB |
92 | info = devm_kzalloc(&pdev->dev, |
93 | sizeof(struct orion_nand_info), | |
a0fa0b66 | 94 | GFP_KERNEL); |
675b11d9 | 95 | if (!info) |
a0fa0b66 | 96 | return -ENOMEM; |
675b11d9 | 97 | nc = &info->chip; |
53cd2681 | 98 | mtd = nand_to_mtd(nc); |
2a1dba29 | 99 | |
e9903060 | 100 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
a0fa0b66 | 101 | io_base = devm_ioremap_resource(&pdev->dev, res); |
e9903060 | 102 | |
a0fa0b66 MO |
103 | if (IS_ERR(io_base)) |
104 | return PTR_ERR(io_base); | |
2a1dba29 | 105 | |
a0fabf72 JL |
106 | if (pdev->dev.of_node) { |
107 | board = devm_kzalloc(&pdev->dev, sizeof(struct orion_nand_data), | |
108 | GFP_KERNEL); | |
a0fa0b66 MO |
109 | if (!board) |
110 | return -ENOMEM; | |
a0fabf72 JL |
111 | if (!of_property_read_u32(pdev->dev.of_node, "cle", &val)) |
112 | board->cle = (u8)val; | |
113 | else | |
114 | board->cle = 0; | |
115 | if (!of_property_read_u32(pdev->dev.of_node, "ale", &val)) | |
116 | board->ale = (u8)val; | |
117 | else | |
118 | board->ale = 1; | |
119 | if (!of_property_read_u32(pdev->dev.of_node, | |
120 | "bank-width", &val)) | |
121 | board->width = (u8)val * 8; | |
122 | else | |
123 | board->width = 8; | |
124 | if (!of_property_read_u32(pdev->dev.of_node, | |
125 | "chip-delay", &val)) | |
126 | board->chip_delay = (u8)val; | |
453810b7 JH |
127 | } else { |
128 | board = dev_get_platdata(&pdev->dev); | |
129 | } | |
2a1dba29 | 130 | |
84630994 | 131 | mtd->dev.parent = &pdev->dev; |
2a1dba29 | 132 | |
d699ed25 | 133 | nand_set_controller_data(nc, board); |
a61ae81a | 134 | nand_set_flash_node(nc, pdev->dev.of_node); |
2a1dba29 TP |
135 | nc->IO_ADDR_R = nc->IO_ADDR_W = io_base; |
136 | nc->cmd_ctrl = orion_nand_cmd_ctrl; | |
bfee1a43 | 137 | nc->read_buf = orion_nand_read_buf; |
2a1dba29 | 138 | nc->ecc.mode = NAND_ECC_SOFT; |
ac7efcbe | 139 | nc->ecc.algo = NAND_ECC_HAMMING; |
2a1dba29 | 140 | |
f4db56ff SB |
141 | if (board->chip_delay) |
142 | nc->chip_delay = board->chip_delay; | |
143 | ||
a0fabf72 JL |
144 | WARN(board->width > 16, |
145 | "%d bit bus width out of range", | |
146 | board->width); | |
147 | ||
2a1dba29 TP |
148 | if (board->width == 16) |
149 | nc->options |= NAND_BUSWIDTH_16; | |
150 | ||
eedfea25 BD |
151 | if (board->dev_ready) |
152 | nc->dev_ready = board->dev_ready; | |
153 | ||
675b11d9 | 154 | platform_set_drvdata(pdev, info); |
2a1dba29 | 155 | |
9c2bd504 AL |
156 | /* Not all platforms can gate the clock, so it is not |
157 | an error if the clock does not exists. */ | |
675b11d9 | 158 | info->clk = devm_clk_get(&pdev->dev, NULL); |
ef980cf8 SB |
159 | if (IS_ERR(info->clk)) { |
160 | ret = PTR_ERR(info->clk); | |
161 | if (ret == -ENOENT) { | |
162 | info->clk = NULL; | |
163 | } else { | |
164 | dev_err(&pdev->dev, "failed to get clock!\n"); | |
165 | return ret; | |
166 | } | |
167 | } | |
168 | ||
3762a33b AY |
169 | ret = clk_prepare_enable(info->clk); |
170 | if (ret) { | |
171 | dev_err(&pdev->dev, "failed to prepare clock!\n"); | |
172 | return ret; | |
173 | } | |
9c2bd504 | 174 | |
6c34ad7d MY |
175 | ret = nand_scan(mtd, 1); |
176 | if (ret) | |
2a1dba29 | 177 | goto no_dev; |
2a1dba29 | 178 | |
2a1dba29 | 179 | mtd->name = "orion_nand"; |
a61ae81a | 180 | ret = mtd_device_register(mtd, board->parts, board->nr_parts); |
2a1dba29 TP |
181 | if (ret) { |
182 | nand_release(mtd); | |
183 | goto no_dev; | |
184 | } | |
185 | ||
186 | return 0; | |
187 | ||
188 | no_dev: | |
ef980cf8 | 189 | clk_disable_unprepare(info->clk); |
2a1dba29 TP |
190 | return ret; |
191 | } | |
192 | ||
810b7e06 | 193 | static int orion_nand_remove(struct platform_device *pdev) |
2a1dba29 | 194 | { |
675b11d9 SB |
195 | struct orion_nand_info *info = platform_get_drvdata(pdev); |
196 | struct nand_chip *chip = &info->chip; | |
197 | struct mtd_info *mtd = nand_to_mtd(chip); | |
2a1dba29 TP |
198 | |
199 | nand_release(mtd); | |
200 | ||
ef980cf8 | 201 | clk_disable_unprepare(info->clk); |
9c2bd504 | 202 | |
2a1dba29 TP |
203 | return 0; |
204 | } | |
205 | ||
a0fabf72 | 206 | #ifdef CONFIG_OF |
cb3346ac | 207 | static const struct of_device_id orion_nand_of_match_table[] = { |
77843504 | 208 | { .compatible = "marvell,orion-nand", }, |
a0fabf72 JL |
209 | {}, |
210 | }; | |
98d1a5ee | 211 | MODULE_DEVICE_TABLE(of, orion_nand_of_match_table); |
a0fabf72 JL |
212 | #endif |
213 | ||
2a1dba29 | 214 | static struct platform_driver orion_nand_driver = { |
5153b88c | 215 | .remove = orion_nand_remove, |
2a1dba29 TP |
216 | .driver = { |
217 | .name = "orion_nand", | |
a0fabf72 | 218 | .of_match_table = of_match_ptr(orion_nand_of_match_table), |
2a1dba29 TP |
219 | }, |
220 | }; | |
221 | ||
d9ba3109 | 222 | module_platform_driver_probe(orion_nand_driver, orion_nand_probe); |
2a1dba29 TP |
223 | |
224 | MODULE_LICENSE("GPL"); | |
225 | MODULE_AUTHOR("Tzachi Perelstein"); | |
226 | MODULE_DESCRIPTION("NAND glue for Orion platforms"); | |
1ff18422 | 227 | MODULE_ALIAS("platform:orion_nand"); |