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1da177e4 LT |
1 | /* |
2 | * drivers/mtd/nand/ppchameleonevb.c | |
3 | * | |
4 | * Copyright (C) 2003 DAVE Srl (info@wawnet.biz) | |
5 | * | |
6 | * Derived from drivers/mtd/nand/edb7312.c | |
7 | * | |
8 | * | |
61b03bd7 | 9 | * $Id: ppchameleonevb.c,v 1.7 2005/11/07 11:14:31 gleixner Exp $ |
1da177e4 LT |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * Overview: | |
16 | * This is a device driver for the NAND flash devices found on the | |
17 | * PPChameleon/PPChameleonEVB system. | |
18 | * PPChameleon options (autodetected): | |
19 | * - BA model: no NAND | |
20 | * - ME model: 32MB (Samsung K9F5608U0B) | |
21 | * - HI model: 128MB (Samsung K9F1G08UOM) | |
22 | * PPChameleonEVB options: | |
23 | * - 32MB (Samsung K9F5608U0B) | |
24 | */ | |
25 | ||
26 | #include <linux/init.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/mtd/mtd.h> | |
30 | #include <linux/mtd/nand.h> | |
31 | #include <linux/mtd/partitions.h> | |
32 | #include <asm/io.h> | |
33 | #include <platforms/PPChameleonEVB.h> | |
34 | ||
35 | #undef USE_READY_BUSY_PIN | |
36 | #define USE_READY_BUSY_PIN | |
37 | /* see datasheets (tR) */ | |
38 | #define NAND_BIG_DELAY_US 25 | |
39 | #define NAND_SMALL_DELAY_US 10 | |
40 | ||
41 | /* handy sizes */ | |
42 | #define SZ_4M 0x00400000 | |
43 | #define NAND_SMALL_SIZE 0x02000000 | |
44 | #define NAND_MTD_NAME "ppchameleon-nand" | |
45 | #define NAND_EVB_MTD_NAME "ppchameleonevb-nand" | |
46 | ||
47 | /* GPIO pins used to drive NAND chip mounted on processor module */ | |
48 | #define NAND_nCE_GPIO_PIN (0x80000000 >> 1) | |
49 | #define NAND_CLE_GPIO_PIN (0x80000000 >> 2) | |
50 | #define NAND_ALE_GPIO_PIN (0x80000000 >> 3) | |
51 | #define NAND_RB_GPIO_PIN (0x80000000 >> 4) | |
52 | /* GPIO pins used to drive NAND chip mounted on EVB */ | |
53 | #define NAND_EVB_nCE_GPIO_PIN (0x80000000 >> 14) | |
54 | #define NAND_EVB_CLE_GPIO_PIN (0x80000000 >> 15) | |
55 | #define NAND_EVB_ALE_GPIO_PIN (0x80000000 >> 16) | |
56 | #define NAND_EVB_RB_GPIO_PIN (0x80000000 >> 31) | |
57 | ||
58 | /* | |
59 | * MTD structure for PPChameleonEVB board | |
60 | */ | |
e0c7d767 | 61 | static struct mtd_info *ppchameleon_mtd = NULL; |
1da177e4 LT |
62 | static struct mtd_info *ppchameleonevb_mtd = NULL; |
63 | ||
64 | /* | |
65 | * Module stuff | |
66 | */ | |
e0c7d767 | 67 | static unsigned long ppchameleon_fio_pbase = CFG_NAND0_PADDR; |
1da177e4 LT |
68 | static unsigned long ppchameleonevb_fio_pbase = CFG_NAND1_PADDR; |
69 | ||
70 | #ifdef MODULE | |
71 | module_param(ppchameleon_fio_pbase, ulong, 0); | |
72 | module_param(ppchameleonevb_fio_pbase, ulong, 0); | |
73 | #else | |
e0c7d767 DW |
74 | __setup("ppchameleon_fio_pbase=", ppchameleon_fio_pbase); |
75 | __setup("ppchameleonevb_fio_pbase=", ppchameleonevb_fio_pbase); | |
1da177e4 LT |
76 | #endif |
77 | ||
78 | #ifdef CONFIG_MTD_PARTITIONS | |
79 | /* | |
80 | * Define static partitions for flash devices | |
81 | */ | |
82 | static struct mtd_partition partition_info_hi[] = { | |
e0c7d767 | 83 | { .name = "PPChameleon HI Nand Flash", |
632155e6 | 84 | .offset = 0, |
e0c7d767 DW |
85 | .size = 128 * 1024 * 1024 |
86 | } | |
1da177e4 LT |
87 | }; |
88 | ||
89 | static struct mtd_partition partition_info_me[] = { | |
e0c7d767 DW |
90 | { .name = "PPChameleon ME Nand Flash", |
91 | .offset = 0, | |
92 | .size = 32 * 1024 * 1024 | |
93 | } | |
1da177e4 LT |
94 | }; |
95 | ||
96 | static struct mtd_partition partition_info_evb[] = { | |
e0c7d767 DW |
97 | { .name = "PPChameleonEVB Nand Flash", |
98 | .offset = 0, | |
99 | .size = 32 * 1024 * 1024 | |
100 | } | |
1da177e4 LT |
101 | }; |
102 | ||
103 | #define NUM_PARTITIONS 1 | |
104 | ||
e0c7d767 | 105 | extern int parse_cmdline_partitions(struct mtd_info *master, struct mtd_partition **pparts, const char *mtd_id); |
1da177e4 LT |
106 | #endif |
107 | ||
1da177e4 LT |
108 | /* |
109 | * hardware specific access to control-lines | |
110 | */ | |
7abd3ef9 TG |
111 | static void ppchameleon_hwcontrol(struct mtd_info *mtdinfo, int cmd, |
112 | unsigned int ctrl) | |
1da177e4 | 113 | { |
7abd3ef9 TG |
114 | struct nand_chip *chip = mtd->priv; |
115 | ||
116 | if (ctrl & NAND_CTRL_CHANGE) { | |
117 | #error Missing headerfiles. No way to fix this. -tglx | |
118 | switch (cmd) { | |
119 | case NAND_CTL_SETCLE: | |
120 | MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND0_PADDR); | |
121 | break; | |
122 | case NAND_CTL_CLRCLE: | |
123 | MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND0_PADDR); | |
124 | break; | |
125 | case NAND_CTL_SETALE: | |
126 | MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND0_PADDR); | |
127 | break; | |
128 | case NAND_CTL_CLRALE: | |
129 | MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND0_PADDR); | |
130 | break; | |
131 | case NAND_CTL_SETNCE: | |
132 | MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND0_PADDR); | |
133 | break; | |
134 | case NAND_CTL_CLRNCE: | |
135 | MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND0_PADDR); | |
136 | break; | |
137 | } | |
1da177e4 | 138 | } |
7abd3ef9 TG |
139 | if (cmd != NAND_CMD_NONE) |
140 | writeb(cmd, chip->IO_ADDR_W); | |
1da177e4 LT |
141 | } |
142 | ||
7abd3ef9 TG |
143 | static void ppchameleonevb_hwcontrol(struct mtd_info *mtdinfo, int cmd, |
144 | unsigned int ctrl) | |
1da177e4 | 145 | { |
7abd3ef9 TG |
146 | struct nand_chip *chip = mtd->priv; |
147 | ||
148 | if (ctrl & NAND_CTRL_CHANGE) { | |
149 | #error Missing headerfiles. No way to fix this. -tglx | |
150 | switch (cmd) { | |
151 | case NAND_CTL_SETCLE: | |
152 | MACRO_NAND_CTL_SETCLE((unsigned long)CFG_NAND1_PADDR); | |
153 | break; | |
154 | case NAND_CTL_CLRCLE: | |
155 | MACRO_NAND_CTL_CLRCLE((unsigned long)CFG_NAND1_PADDR); | |
156 | break; | |
157 | case NAND_CTL_SETALE: | |
158 | MACRO_NAND_CTL_SETALE((unsigned long)CFG_NAND1_PADDR); | |
159 | break; | |
160 | case NAND_CTL_CLRALE: | |
161 | MACRO_NAND_CTL_CLRALE((unsigned long)CFG_NAND1_PADDR); | |
162 | break; | |
163 | case NAND_CTL_SETNCE: | |
164 | MACRO_NAND_ENABLE_CE((unsigned long)CFG_NAND1_PADDR); | |
165 | break; | |
166 | case NAND_CTL_CLRNCE: | |
167 | MACRO_NAND_DISABLE_CE((unsigned long)CFG_NAND1_PADDR); | |
168 | break; | |
169 | } | |
1da177e4 | 170 | } |
7abd3ef9 TG |
171 | if (cmd != NAND_CMD_NONE) |
172 | writeb(cmd, chip->IO_ADDR_W); | |
1da177e4 LT |
173 | } |
174 | ||
175 | #ifdef USE_READY_BUSY_PIN | |
176 | /* | |
177 | * read device ready pin | |
178 | */ | |
179 | static int ppchameleon_device_ready(struct mtd_info *minfo) | |
180 | { | |
e0c7d767 | 181 | if (in_be32((volatile unsigned *)GPIO0_IR) & NAND_RB_GPIO_PIN) |
1da177e4 LT |
182 | return 1; |
183 | return 0; | |
184 | } | |
185 | ||
186 | static int ppchameleonevb_device_ready(struct mtd_info *minfo) | |
187 | { | |
e0c7d767 DW |
188 | if (in_be32((volatile unsigned *)GPIO0_IR) & NAND_EVB_RB_GPIO_PIN) |
189 | return 1; | |
1da177e4 LT |
190 | return 0; |
191 | } | |
192 | #endif | |
193 | ||
194 | #ifdef CONFIG_MTD_PARTITIONS | |
195 | const char *part_probes[] = { "cmdlinepart", NULL }; | |
196 | const char *part_probes_evb[] = { "cmdlinepart", NULL }; | |
197 | #endif | |
198 | ||
199 | /* | |
200 | * Main initialization routine | |
201 | */ | |
e0c7d767 | 202 | static int __init ppchameleonevb_init(void) |
1da177e4 LT |
203 | { |
204 | struct nand_chip *this; | |
205 | const char *part_type = 0; | |
206 | int mtd_parts_nb = 0; | |
207 | struct mtd_partition *mtd_parts = 0; | |
208 | void __iomem *ppchameleon_fio_base; | |
209 | void __iomem *ppchameleonevb_fio_base; | |
210 | ||
1da177e4 LT |
211 | /********************************* |
212 | * Processor module NAND (if any) * | |
213 | *********************************/ | |
214 | /* Allocate memory for MTD device structure and private data */ | |
e0c7d767 | 215 | ppchameleon_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL); |
1da177e4 LT |
216 | if (!ppchameleon_mtd) { |
217 | printk("Unable to allocate PPChameleon NAND MTD device structure.\n"); | |
218 | return -ENOMEM; | |
219 | } | |
220 | ||
221 | /* map physical address */ | |
222 | ppchameleon_fio_base = ioremap(ppchameleon_fio_pbase, SZ_4M); | |
e0c7d767 | 223 | if (!ppchameleon_fio_base) { |
1da177e4 LT |
224 | printk("ioremap PPChameleon NAND flash failed\n"); |
225 | kfree(ppchameleon_mtd); | |
226 | return -EIO; | |
227 | } | |
228 | ||
229 | /* Get pointer to private data */ | |
e0c7d767 | 230 | this = (struct nand_chip *)(&ppchameleon_mtd[1]); |
1da177e4 LT |
231 | |
232 | /* Initialize structures */ | |
e0c7d767 DW |
233 | memset(ppchameleon_mtd, 0, sizeof(struct mtd_info)); |
234 | memset(this, 0, sizeof(struct nand_chip)); | |
1da177e4 LT |
235 | |
236 | /* Link the private data with the MTD structure */ | |
237 | ppchameleon_mtd->priv = this; | |
552d9205 | 238 | ppchameleon_mtd->owner = THIS_MODULE; |
1da177e4 | 239 | |
e0c7d767 | 240 | /* Initialize GPIOs */ |
1da177e4 LT |
241 | /* Pin mapping for NAND chip */ |
242 | /* | |
e0c7d767 DW |
243 | CE GPIO_01 |
244 | CLE GPIO_02 | |
245 | ALE GPIO_03 | |
246 | R/B GPIO_04 | |
247 | */ | |
1da177e4 | 248 | /* output select */ |
e0c7d767 | 249 | out_be32((volatile unsigned *)GPIO0_OSRH, in_be32((volatile unsigned *)GPIO0_OSRH) & 0xC0FFFFFF); |
1da177e4 | 250 | /* three-state select */ |
e0c7d767 | 251 | out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xC0FFFFFF); |
1da177e4 | 252 | /* enable output driver */ |
e0c7d767 DW |
253 | out_be32((volatile unsigned *)GPIO0_TCR, |
254 | in_be32((volatile unsigned *)GPIO0_TCR) | NAND_nCE_GPIO_PIN | NAND_CLE_GPIO_PIN | NAND_ALE_GPIO_PIN); | |
1da177e4 LT |
255 | #ifdef USE_READY_BUSY_PIN |
256 | /* three-state select */ | |
e0c7d767 | 257 | out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xFF3FFFFF); |
1da177e4 | 258 | /* high-impedecence */ |
e0c7d767 | 259 | out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) & (~NAND_RB_GPIO_PIN)); |
1da177e4 | 260 | /* input select */ |
e0c7d767 DW |
261 | out_be32((volatile unsigned *)GPIO0_ISR1H, |
262 | (in_be32((volatile unsigned *)GPIO0_ISR1H) & 0xFF3FFFFF) | 0x00400000); | |
1da177e4 LT |
263 | #endif |
264 | ||
265 | /* insert callbacks */ | |
266 | this->IO_ADDR_R = ppchameleon_fio_base; | |
267 | this->IO_ADDR_W = ppchameleon_fio_base; | |
7abd3ef9 | 268 | this->cmd_ctrl = ppchameleon_hwcontrol; |
1da177e4 LT |
269 | #ifdef USE_READY_BUSY_PIN |
270 | this->dev_ready = ppchameleon_device_ready; | |
271 | #endif | |
272 | this->chip_delay = NAND_BIG_DELAY_US; | |
273 | /* ECC mode */ | |
6dfc6d25 | 274 | this->ecc.mode = NAND_ECC_SOFT; |
1da177e4 LT |
275 | |
276 | /* Scan to find existence of the device (it could not be mounted) */ | |
e0c7d767 | 277 | if (nand_scan(ppchameleon_mtd, 1)) { |
1da177e4 | 278 | iounmap((void *)ppchameleon_fio_base); |
25f0c659 | 279 | ppchameleon_fio_base = NULL; |
e0c7d767 | 280 | kfree(ppchameleon_mtd); |
1da177e4 LT |
281 | goto nand_evb_init; |
282 | } | |
1da177e4 LT |
283 | #ifndef USE_READY_BUSY_PIN |
284 | /* Adjust delay if necessary */ | |
285 | if (ppchameleon_mtd->size == NAND_SMALL_SIZE) | |
286 | this->chip_delay = NAND_SMALL_DELAY_US; | |
287 | #endif | |
288 | ||
289 | #ifdef CONFIG_MTD_PARTITIONS | |
290 | ppchameleon_mtd->name = "ppchameleon-nand"; | |
291 | mtd_parts_nb = parse_mtd_partitions(ppchameleon_mtd, part_probes, &mtd_parts, 0); | |
292 | if (mtd_parts_nb > 0) | |
e0c7d767 | 293 | part_type = "command line"; |
1da177e4 | 294 | else |
e0c7d767 | 295 | mtd_parts_nb = 0; |
1da177e4 | 296 | #endif |
e0c7d767 | 297 | if (mtd_parts_nb == 0) { |
1da177e4 LT |
298 | if (ppchameleon_mtd->size == NAND_SMALL_SIZE) |
299 | mtd_parts = partition_info_me; | |
300 | else | |
301 | mtd_parts = partition_info_hi; | |
302 | mtd_parts_nb = NUM_PARTITIONS; | |
303 | part_type = "static"; | |
304 | } | |
305 | ||
306 | /* Register the partitions */ | |
307 | printk(KERN_NOTICE "Using %s partition definition\n", part_type); | |
308 | add_mtd_partitions(ppchameleon_mtd, mtd_parts, mtd_parts_nb); | |
309 | ||
e0c7d767 | 310 | nand_evb_init: |
1da177e4 LT |
311 | /**************************** |
312 | * EVB NAND (always present) * | |
313 | ****************************/ | |
314 | /* Allocate memory for MTD device structure and private data */ | |
e0c7d767 | 315 | ppchameleonevb_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL); |
1da177e4 LT |
316 | if (!ppchameleonevb_mtd) { |
317 | printk("Unable to allocate PPChameleonEVB NAND MTD device structure.\n"); | |
25f0c659 AL |
318 | if (ppchameleon_fio_base) |
319 | iounmap(ppchameleon_fio_base); | |
1da177e4 LT |
320 | return -ENOMEM; |
321 | } | |
322 | ||
323 | /* map physical address */ | |
324 | ppchameleonevb_fio_base = ioremap(ppchameleonevb_fio_pbase, SZ_4M); | |
e0c7d767 | 325 | if (!ppchameleonevb_fio_base) { |
1da177e4 LT |
326 | printk("ioremap PPChameleonEVB NAND flash failed\n"); |
327 | kfree(ppchameleonevb_mtd); | |
25f0c659 AL |
328 | if (ppchameleon_fio_base) |
329 | iounmap(ppchameleon_fio_base); | |
1da177e4 LT |
330 | return -EIO; |
331 | } | |
332 | ||
333 | /* Get pointer to private data */ | |
e0c7d767 | 334 | this = (struct nand_chip *)(&ppchameleonevb_mtd[1]); |
1da177e4 LT |
335 | |
336 | /* Initialize structures */ | |
e0c7d767 DW |
337 | memset(ppchameleonevb_mtd, 0, sizeof(struct mtd_info)); |
338 | memset(this, 0, sizeof(struct nand_chip)); | |
1da177e4 LT |
339 | |
340 | /* Link the private data with the MTD structure */ | |
341 | ppchameleonevb_mtd->priv = this; | |
342 | ||
e0c7d767 | 343 | /* Initialize GPIOs */ |
1da177e4 LT |
344 | /* Pin mapping for NAND chip */ |
345 | /* | |
e0c7d767 DW |
346 | CE GPIO_14 |
347 | CLE GPIO_15 | |
348 | ALE GPIO_16 | |
349 | R/B GPIO_31 | |
350 | */ | |
1da177e4 | 351 | /* output select */ |
e0c7d767 DW |
352 | out_be32((volatile unsigned *)GPIO0_OSRH, in_be32((volatile unsigned *)GPIO0_OSRH) & 0xFFFFFFF0); |
353 | out_be32((volatile unsigned *)GPIO0_OSRL, in_be32((volatile unsigned *)GPIO0_OSRL) & 0x3FFFFFFF); | |
1da177e4 | 354 | /* three-state select */ |
e0c7d767 DW |
355 | out_be32((volatile unsigned *)GPIO0_TSRH, in_be32((volatile unsigned *)GPIO0_TSRH) & 0xFFFFFFF0); |
356 | out_be32((volatile unsigned *)GPIO0_TSRL, in_be32((volatile unsigned *)GPIO0_TSRL) & 0x3FFFFFFF); | |
1da177e4 | 357 | /* enable output driver */ |
e0c7d767 | 358 | out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) | NAND_EVB_nCE_GPIO_PIN | |
1da177e4 LT |
359 | NAND_EVB_CLE_GPIO_PIN | NAND_EVB_ALE_GPIO_PIN); |
360 | #ifdef USE_READY_BUSY_PIN | |
361 | /* three-state select */ | |
e0c7d767 | 362 | out_be32((volatile unsigned *)GPIO0_TSRL, in_be32((volatile unsigned *)GPIO0_TSRL) & 0xFFFFFFFC); |
1da177e4 | 363 | /* high-impedecence */ |
e0c7d767 | 364 | out_be32((volatile unsigned *)GPIO0_TCR, in_be32((volatile unsigned *)GPIO0_TCR) & (~NAND_EVB_RB_GPIO_PIN)); |
1da177e4 | 365 | /* input select */ |
e0c7d767 DW |
366 | out_be32((volatile unsigned *)GPIO0_ISR1L, |
367 | (in_be32((volatile unsigned *)GPIO0_ISR1L) & 0xFFFFFFFC) | 0x00000001); | |
1da177e4 LT |
368 | #endif |
369 | ||
370 | /* insert callbacks */ | |
371 | this->IO_ADDR_R = ppchameleonevb_fio_base; | |
372 | this->IO_ADDR_W = ppchameleonevb_fio_base; | |
7abd3ef9 | 373 | this->cmd_ctrl = ppchameleonevb_hwcontrol; |
1da177e4 LT |
374 | #ifdef USE_READY_BUSY_PIN |
375 | this->dev_ready = ppchameleonevb_device_ready; | |
376 | #endif | |
377 | this->chip_delay = NAND_SMALL_DELAY_US; | |
378 | ||
379 | /* ECC mode */ | |
6dfc6d25 | 380 | this->ecc.mode = NAND_ECC_SOFT; |
1da177e4 LT |
381 | |
382 | /* Scan to find existence of the device */ | |
e0c7d767 | 383 | if (nand_scan(ppchameleonevb_mtd, 1)) { |
1da177e4 | 384 | iounmap((void *)ppchameleonevb_fio_base); |
e0c7d767 | 385 | kfree(ppchameleonevb_mtd); |
25f0c659 AL |
386 | if (ppchameleon_fio_base) |
387 | iounmap(ppchameleon_fio_base); | |
1da177e4 LT |
388 | return -ENXIO; |
389 | } | |
1da177e4 LT |
390 | #ifdef CONFIG_MTD_PARTITIONS |
391 | ppchameleonevb_mtd->name = NAND_EVB_MTD_NAME; | |
392 | mtd_parts_nb = parse_mtd_partitions(ppchameleonevb_mtd, part_probes_evb, &mtd_parts, 0); | |
393 | if (mtd_parts_nb > 0) | |
e0c7d767 | 394 | part_type = "command line"; |
1da177e4 | 395 | else |
e0c7d767 | 396 | mtd_parts_nb = 0; |
1da177e4 | 397 | #endif |
e0c7d767 | 398 | if (mtd_parts_nb == 0) { |
1da177e4 LT |
399 | mtd_parts = partition_info_evb; |
400 | mtd_parts_nb = NUM_PARTITIONS; | |
401 | part_type = "static"; | |
402 | } | |
403 | ||
404 | /* Register the partitions */ | |
405 | printk(KERN_NOTICE "Using %s partition definition\n", part_type); | |
406 | add_mtd_partitions(ppchameleonevb_mtd, mtd_parts, mtd_parts_nb); | |
407 | ||
408 | /* Return happy */ | |
409 | return 0; | |
410 | } | |
e0c7d767 | 411 | |
1da177e4 LT |
412 | module_init(ppchameleonevb_init); |
413 | ||
414 | /* | |
415 | * Clean up routine | |
416 | */ | |
e0c7d767 | 417 | static void __exit ppchameleonevb_cleanup(void) |
1da177e4 LT |
418 | { |
419 | struct nand_chip *this; | |
420 | ||
421 | /* Release resources, unregister device(s) */ | |
e0c7d767 DW |
422 | nand_release(ppchameleon_mtd); |
423 | nand_release(ppchameleonevb_mtd); | |
61b03bd7 | 424 | |
1da177e4 LT |
425 | /* Release iomaps */ |
426 | this = (struct nand_chip *) &ppchameleon_mtd[1]; | |
427 | iounmap((void *) this->IO_ADDR_R; | |
428 | this = (struct nand_chip *) &ppchameleonevb_mtd[1]; | |
429 | iounmap((void *) this->IO_ADDR_R; | |
430 | ||
431 | /* Free the MTD device structure */ | |
432 | kfree (ppchameleon_mtd); | |
433 | kfree (ppchameleonevb_mtd); | |
434 | } | |
435 | module_exit(ppchameleonevb_cleanup); | |
436 | ||
437 | MODULE_LICENSE("GPL"); | |
438 | MODULE_AUTHOR("DAVE Srl <support-ppchameleon@dave-tech.it>"); | |
439 | MODULE_DESCRIPTION("MTD map driver for DAVE Srl PPChameleonEVB board"); |