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fe69af00 | 1 | /* |
2 | * drivers/mtd/nand/pxa3xx_nand.c | |
3 | * | |
4 | * Copyright © 2005 Intel Corporation | |
5 | * Copyright © 2006 Marvell International Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
a88bdbb5 | 12 | #include <linux/kernel.h> |
fe69af00 | 13 | #include <linux/module.h> |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/mtd/mtd.h> | |
20 | #include <linux/mtd/nand.h> | |
21 | #include <linux/mtd/partitions.h> | |
a1c06ee1 DW |
22 | #include <linux/io.h> |
23 | #include <linux/irq.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
fe69af00 | 25 | |
afb5b5c9 | 26 | #include <mach/dma.h> |
82b95ecb | 27 | #include <plat/pxa3xx_nand.h> |
fe69af00 | 28 | |
29 | #define CHIP_DELAY_TIMEOUT (2 * HZ/10) | |
f8155a40 | 30 | #define NAND_STOP_DELAY (2 * HZ/50) |
4eb2da89 | 31 | #define PAGE_CHUNK_SIZE (2048) |
fe69af00 | 32 | |
33 | /* registers and bit definitions */ | |
34 | #define NDCR (0x00) /* Control register */ | |
35 | #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */ | |
36 | #define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */ | |
37 | #define NDSR (0x14) /* Status Register */ | |
38 | #define NDPCR (0x18) /* Page Count Register */ | |
39 | #define NDBDR0 (0x1C) /* Bad Block Register 0 */ | |
40 | #define NDBDR1 (0x20) /* Bad Block Register 1 */ | |
41 | #define NDDB (0x40) /* Data Buffer */ | |
42 | #define NDCB0 (0x48) /* Command Buffer0 */ | |
43 | #define NDCB1 (0x4C) /* Command Buffer1 */ | |
44 | #define NDCB2 (0x50) /* Command Buffer2 */ | |
45 | ||
46 | #define NDCR_SPARE_EN (0x1 << 31) | |
47 | #define NDCR_ECC_EN (0x1 << 30) | |
48 | #define NDCR_DMA_EN (0x1 << 29) | |
49 | #define NDCR_ND_RUN (0x1 << 28) | |
50 | #define NDCR_DWIDTH_C (0x1 << 27) | |
51 | #define NDCR_DWIDTH_M (0x1 << 26) | |
52 | #define NDCR_PAGE_SZ (0x1 << 24) | |
53 | #define NDCR_NCSX (0x1 << 23) | |
54 | #define NDCR_ND_MODE (0x3 << 21) | |
55 | #define NDCR_NAND_MODE (0x0) | |
56 | #define NDCR_CLR_PG_CNT (0x1 << 20) | |
f8155a40 | 57 | #define NDCR_STOP_ON_UNCOR (0x1 << 19) |
fe69af00 | 58 | #define NDCR_RD_ID_CNT_MASK (0x7 << 16) |
59 | #define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK) | |
60 | ||
61 | #define NDCR_RA_START (0x1 << 15) | |
62 | #define NDCR_PG_PER_BLK (0x1 << 14) | |
63 | #define NDCR_ND_ARB_EN (0x1 << 12) | |
f8155a40 | 64 | #define NDCR_INT_MASK (0xFFF) |
fe69af00 | 65 | |
66 | #define NDSR_MASK (0xfff) | |
f8155a40 LW |
67 | #define NDSR_RDY (0x1 << 12) |
68 | #define NDSR_FLASH_RDY (0x1 << 11) | |
fe69af00 | 69 | #define NDSR_CS0_PAGED (0x1 << 10) |
70 | #define NDSR_CS1_PAGED (0x1 << 9) | |
71 | #define NDSR_CS0_CMDD (0x1 << 8) | |
72 | #define NDSR_CS1_CMDD (0x1 << 7) | |
73 | #define NDSR_CS0_BBD (0x1 << 6) | |
74 | #define NDSR_CS1_BBD (0x1 << 5) | |
75 | #define NDSR_DBERR (0x1 << 4) | |
76 | #define NDSR_SBERR (0x1 << 3) | |
77 | #define NDSR_WRDREQ (0x1 << 2) | |
78 | #define NDSR_RDDREQ (0x1 << 1) | |
79 | #define NDSR_WRCMDREQ (0x1) | |
80 | ||
4eb2da89 | 81 | #define NDCB0_ST_ROW_EN (0x1 << 26) |
fe69af00 | 82 | #define NDCB0_AUTO_RS (0x1 << 25) |
83 | #define NDCB0_CSEL (0x1 << 24) | |
84 | #define NDCB0_CMD_TYPE_MASK (0x7 << 21) | |
85 | #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK) | |
86 | #define NDCB0_NC (0x1 << 20) | |
87 | #define NDCB0_DBC (0x1 << 19) | |
88 | #define NDCB0_ADDR_CYC_MASK (0x7 << 16) | |
89 | #define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK) | |
90 | #define NDCB0_CMD2_MASK (0xff << 8) | |
91 | #define NDCB0_CMD1_MASK (0xff) | |
92 | #define NDCB0_ADDR_CYC_SHIFT (16) | |
93 | ||
fe69af00 | 94 | /* macros for registers read/write */ |
95 | #define nand_writel(info, off, val) \ | |
96 | __raw_writel((val), (info)->mmio_base + (off)) | |
97 | ||
98 | #define nand_readl(info, off) \ | |
99 | __raw_readl((info)->mmio_base + (off)) | |
100 | ||
101 | /* error code and state */ | |
102 | enum { | |
103 | ERR_NONE = 0, | |
104 | ERR_DMABUSERR = -1, | |
105 | ERR_SENDCMD = -2, | |
106 | ERR_DBERR = -3, | |
107 | ERR_BBERR = -4, | |
223cf6c3 | 108 | ERR_SBERR = -5, |
fe69af00 | 109 | }; |
110 | ||
111 | enum { | |
f8155a40 | 112 | STATE_IDLE = 0, |
fe69af00 | 113 | STATE_CMD_HANDLE, |
114 | STATE_DMA_READING, | |
115 | STATE_DMA_WRITING, | |
116 | STATE_DMA_DONE, | |
117 | STATE_PIO_READING, | |
118 | STATE_PIO_WRITING, | |
f8155a40 LW |
119 | STATE_CMD_DONE, |
120 | STATE_READY, | |
fe69af00 | 121 | }; |
122 | ||
fe69af00 | 123 | struct pxa3xx_nand_info { |
124 | struct nand_chip nand_chip; | |
125 | ||
401e67e2 | 126 | struct nand_hw_control controller; |
fe69af00 | 127 | struct platform_device *pdev; |
18c81b18 | 128 | struct pxa3xx_nand_cmdset *cmdset; |
fe69af00 | 129 | |
130 | struct clk *clk; | |
131 | void __iomem *mmio_base; | |
8638fac8 | 132 | unsigned long mmio_phys; |
fe69af00 | 133 | |
134 | unsigned int buf_start; | |
135 | unsigned int buf_count; | |
136 | ||
e353a20a | 137 | struct mtd_info *mtd; |
fe69af00 | 138 | /* DMA information */ |
139 | int drcmr_dat; | |
140 | int drcmr_cmd; | |
141 | ||
142 | unsigned char *data_buff; | |
18c81b18 | 143 | unsigned char *oob_buff; |
fe69af00 | 144 | dma_addr_t data_buff_phys; |
145 | size_t data_buff_size; | |
146 | int data_dma_ch; | |
147 | struct pxa_dma_desc *data_desc; | |
148 | dma_addr_t data_desc_addr; | |
149 | ||
150 | uint32_t reg_ndcr; | |
151 | ||
152 | /* saved column/page_addr during CMD_SEQIN */ | |
153 | int seqin_column; | |
154 | int seqin_page_addr; | |
155 | ||
156 | /* relate to the command */ | |
157 | unsigned int state; | |
158 | ||
159 | int use_ecc; /* use HW ECC ? */ | |
160 | int use_dma; /* use DMA ? */ | |
401e67e2 | 161 | int is_ready; |
fe69af00 | 162 | |
18c81b18 LW |
163 | unsigned int page_size; /* page size of attached chip */ |
164 | unsigned int data_size; /* data size in FIFO */ | |
fe69af00 | 165 | int retcode; |
166 | struct completion cmd_complete; | |
167 | ||
168 | /* generated NDCBx register values */ | |
169 | uint32_t ndcb0; | |
170 | uint32_t ndcb1; | |
171 | uint32_t ndcb2; | |
c8c17c88 | 172 | |
18c81b18 LW |
173 | /* timing calcuted from setting */ |
174 | uint32_t ndtr0cs0; | |
175 | uint32_t ndtr1cs0; | |
176 | ||
c8c17c88 ES |
177 | /* calculated from pxa3xx_nand_flash data */ |
178 | size_t oob_size; | |
179 | size_t read_id_bytes; | |
180 | ||
181 | unsigned int col_addr_cycles; | |
182 | unsigned int row_addr_cycles; | |
fe69af00 | 183 | }; |
184 | ||
185 | static int use_dma = 1; | |
186 | module_param(use_dma, bool, 0444); | |
25985edc | 187 | MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW"); |
fe69af00 | 188 | |
f271049e MR |
189 | /* |
190 | * Default NAND flash controller configuration setup by the | |
191 | * bootloader. This configuration is used only when pdata->keep_config is set | |
192 | */ | |
c1f82478 | 193 | static struct pxa3xx_nand_cmdset default_cmdset = { |
fe69af00 | 194 | .read1 = 0x3000, |
195 | .read2 = 0x0050, | |
196 | .program = 0x1080, | |
197 | .read_status = 0x0070, | |
198 | .read_id = 0x0090, | |
199 | .erase = 0xD060, | |
200 | .reset = 0x00FF, | |
201 | .lock = 0x002A, | |
202 | .unlock = 0x2423, | |
203 | .lock_status = 0x007A, | |
204 | }; | |
205 | ||
c1f82478 | 206 | static struct pxa3xx_nand_timing timing[] = { |
227a886c LW |
207 | { 40, 80, 60, 100, 80, 100, 90000, 400, 40, }, |
208 | { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, | |
209 | { 10, 25, 15, 25, 15, 30, 25000, 60, 10, }, | |
210 | { 10, 35, 15, 25, 15, 25, 25000, 60, 10, }, | |
d3490dfd HZ |
211 | }; |
212 | ||
c1f82478 | 213 | static struct pxa3xx_nand_flash builtin_flash_types[] = { |
4332c116 LW |
214 | { "DEFAULT FLASH", 0, 0, 2048, 8, 8, 0, &timing[0] }, |
215 | { "64MiB 16-bit", 0x46ec, 32, 512, 16, 16, 4096, &timing[1] }, | |
216 | { "256MiB 8-bit", 0xdaec, 64, 2048, 8, 8, 2048, &timing[1] }, | |
217 | { "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] }, | |
218 | { "128MiB 8-bit", 0xa12c, 64, 2048, 8, 8, 1024, &timing[2] }, | |
219 | { "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, 1024, &timing[2] }, | |
220 | { "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, 4096, &timing[2] }, | |
221 | { "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, 4096, &timing[2] }, | |
222 | { "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, &timing[3] }, | |
d3490dfd HZ |
223 | }; |
224 | ||
227a886c LW |
225 | /* Define a default flash type setting serve as flash detecting only */ |
226 | #define DEFAULT_FLASH_TYPE (&builtin_flash_types[0]) | |
227 | ||
401e67e2 LW |
228 | const char *mtd_names[] = {"pxa3xx_nand-0", NULL}; |
229 | ||
fe69af00 | 230 | #define NDTR0_tCH(c) (min((c), 7) << 19) |
231 | #define NDTR0_tCS(c) (min((c), 7) << 16) | |
232 | #define NDTR0_tWH(c) (min((c), 7) << 11) | |
233 | #define NDTR0_tWP(c) (min((c), 7) << 8) | |
234 | #define NDTR0_tRH(c) (min((c), 7) << 3) | |
235 | #define NDTR0_tRP(c) (min((c), 7) << 0) | |
236 | ||
237 | #define NDTR1_tR(c) (min((c), 65535) << 16) | |
238 | #define NDTR1_tWHR(c) (min((c), 15) << 4) | |
239 | #define NDTR1_tAR(c) (min((c), 15) << 0) | |
240 | ||
241 | /* convert nano-seconds to nand flash controller clock cycles */ | |
93b352fc | 242 | #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000) |
fe69af00 | 243 | |
244 | static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info, | |
7dad482e | 245 | const struct pxa3xx_nand_timing *t) |
fe69af00 | 246 | { |
247 | unsigned long nand_clk = clk_get_rate(info->clk); | |
248 | uint32_t ndtr0, ndtr1; | |
249 | ||
250 | ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) | | |
251 | NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) | | |
252 | NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) | | |
253 | NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) | | |
254 | NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) | | |
255 | NDTR0_tRP(ns2cycle(t->tRP, nand_clk)); | |
256 | ||
257 | ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | | |
258 | NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) | | |
259 | NDTR1_tAR(ns2cycle(t->tAR, nand_clk)); | |
260 | ||
18c81b18 LW |
261 | info->ndtr0cs0 = ndtr0; |
262 | info->ndtr1cs0 = ndtr1; | |
fe69af00 | 263 | nand_writel(info, NDTR0CS0, ndtr0); |
264 | nand_writel(info, NDTR1CS0, ndtr1); | |
265 | } | |
266 | ||
18c81b18 | 267 | static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info) |
fe69af00 | 268 | { |
9d8b1043 LW |
269 | int oob_enable = info->reg_ndcr & NDCR_SPARE_EN; |
270 | ||
271 | info->data_size = info->page_size; | |
272 | if (!oob_enable) { | |
273 | info->oob_size = 0; | |
274 | return; | |
275 | } | |
276 | ||
18c81b18 | 277 | switch (info->page_size) { |
fe69af00 | 278 | case 2048: |
9d8b1043 | 279 | info->oob_size = (info->use_ecc) ? 40 : 64; |
fe69af00 | 280 | break; |
281 | case 512: | |
9d8b1043 | 282 | info->oob_size = (info->use_ecc) ? 8 : 16; |
fe69af00 | 283 | break; |
fe69af00 | 284 | } |
18c81b18 LW |
285 | } |
286 | ||
f8155a40 LW |
287 | /** |
288 | * NOTE: it is a must to set ND_RUN firstly, then write | |
289 | * command buffer, otherwise, it does not work. | |
290 | * We enable all the interrupt at the same time, and | |
291 | * let pxa3xx_nand_irq to handle all logic. | |
292 | */ | |
293 | static void pxa3xx_nand_start(struct pxa3xx_nand_info *info) | |
294 | { | |
295 | uint32_t ndcr; | |
296 | ||
297 | ndcr = info->reg_ndcr; | |
298 | ndcr |= info->use_ecc ? NDCR_ECC_EN : 0; | |
299 | ndcr |= info->use_dma ? NDCR_DMA_EN : 0; | |
300 | ndcr |= NDCR_ND_RUN; | |
301 | ||
302 | /* clear status bits and run */ | |
303 | nand_writel(info, NDCR, 0); | |
304 | nand_writel(info, NDSR, NDSR_MASK); | |
305 | nand_writel(info, NDCR, ndcr); | |
306 | } | |
307 | ||
308 | static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info) | |
309 | { | |
310 | uint32_t ndcr; | |
311 | int timeout = NAND_STOP_DELAY; | |
312 | ||
313 | /* wait RUN bit in NDCR become 0 */ | |
314 | ndcr = nand_readl(info, NDCR); | |
315 | while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) { | |
316 | ndcr = nand_readl(info, NDCR); | |
317 | udelay(1); | |
318 | } | |
319 | ||
320 | if (timeout <= 0) { | |
321 | ndcr &= ~NDCR_ND_RUN; | |
322 | nand_writel(info, NDCR, ndcr); | |
323 | } | |
324 | /* clear status bits */ | |
325 | nand_writel(info, NDSR, NDSR_MASK); | |
326 | } | |
327 | ||
fe69af00 | 328 | static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) |
329 | { | |
330 | uint32_t ndcr; | |
331 | ||
332 | ndcr = nand_readl(info, NDCR); | |
333 | nand_writel(info, NDCR, ndcr & ~int_mask); | |
334 | } | |
335 | ||
336 | static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) | |
337 | { | |
338 | uint32_t ndcr; | |
339 | ||
340 | ndcr = nand_readl(info, NDCR); | |
341 | nand_writel(info, NDCR, ndcr | int_mask); | |
342 | } | |
343 | ||
f8155a40 | 344 | static void handle_data_pio(struct pxa3xx_nand_info *info) |
fe69af00 | 345 | { |
fe69af00 | 346 | switch (info->state) { |
347 | case STATE_PIO_WRITING: | |
348 | __raw_writesl(info->mmio_base + NDDB, info->data_buff, | |
a88bdbb5 | 349 | DIV_ROUND_UP(info->data_size, 4)); |
9d8b1043 LW |
350 | if (info->oob_size > 0) |
351 | __raw_writesl(info->mmio_base + NDDB, info->oob_buff, | |
352 | DIV_ROUND_UP(info->oob_size, 4)); | |
fe69af00 | 353 | break; |
354 | case STATE_PIO_READING: | |
355 | __raw_readsl(info->mmio_base + NDDB, info->data_buff, | |
a88bdbb5 | 356 | DIV_ROUND_UP(info->data_size, 4)); |
9d8b1043 LW |
357 | if (info->oob_size > 0) |
358 | __raw_readsl(info->mmio_base + NDDB, info->oob_buff, | |
359 | DIV_ROUND_UP(info->oob_size, 4)); | |
fe69af00 | 360 | break; |
361 | default: | |
a1c06ee1 | 362 | printk(KERN_ERR "%s: invalid state %d\n", __func__, |
fe69af00 | 363 | info->state); |
f8155a40 | 364 | BUG(); |
fe69af00 | 365 | } |
fe69af00 | 366 | } |
367 | ||
f8155a40 | 368 | static void start_data_dma(struct pxa3xx_nand_info *info) |
fe69af00 | 369 | { |
370 | struct pxa_dma_desc *desc = info->data_desc; | |
9d8b1043 | 371 | int dma_len = ALIGN(info->data_size + info->oob_size, 32); |
fe69af00 | 372 | |
373 | desc->ddadr = DDADR_STOP; | |
374 | desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len; | |
375 | ||
f8155a40 LW |
376 | switch (info->state) { |
377 | case STATE_DMA_WRITING: | |
fe69af00 | 378 | desc->dsadr = info->data_buff_phys; |
8638fac8 | 379 | desc->dtadr = info->mmio_phys + NDDB; |
fe69af00 | 380 | desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG; |
f8155a40 LW |
381 | break; |
382 | case STATE_DMA_READING: | |
fe69af00 | 383 | desc->dtadr = info->data_buff_phys; |
8638fac8 | 384 | desc->dsadr = info->mmio_phys + NDDB; |
fe69af00 | 385 | desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC; |
f8155a40 LW |
386 | break; |
387 | default: | |
388 | printk(KERN_ERR "%s: invalid state %d\n", __func__, | |
389 | info->state); | |
390 | BUG(); | |
fe69af00 | 391 | } |
392 | ||
393 | DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch; | |
394 | DDADR(info->data_dma_ch) = info->data_desc_addr; | |
395 | DCSR(info->data_dma_ch) |= DCSR_RUN; | |
396 | } | |
397 | ||
398 | static void pxa3xx_nand_data_dma_irq(int channel, void *data) | |
399 | { | |
400 | struct pxa3xx_nand_info *info = data; | |
401 | uint32_t dcsr; | |
402 | ||
403 | dcsr = DCSR(channel); | |
404 | DCSR(channel) = dcsr; | |
405 | ||
406 | if (dcsr & DCSR_BUSERR) { | |
407 | info->retcode = ERR_DMABUSERR; | |
fe69af00 | 408 | } |
409 | ||
f8155a40 LW |
410 | info->state = STATE_DMA_DONE; |
411 | enable_int(info, NDCR_INT_MASK); | |
412 | nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ); | |
fe69af00 | 413 | } |
414 | ||
415 | static irqreturn_t pxa3xx_nand_irq(int irq, void *devid) | |
416 | { | |
417 | struct pxa3xx_nand_info *info = devid; | |
f8155a40 | 418 | unsigned int status, is_completed = 0; |
fe69af00 | 419 | |
420 | status = nand_readl(info, NDSR); | |
421 | ||
f8155a40 LW |
422 | if (status & NDSR_DBERR) |
423 | info->retcode = ERR_DBERR; | |
424 | if (status & NDSR_SBERR) | |
425 | info->retcode = ERR_SBERR; | |
426 | if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) { | |
427 | /* whether use dma to transfer data */ | |
fe69af00 | 428 | if (info->use_dma) { |
f8155a40 LW |
429 | disable_int(info, NDCR_INT_MASK); |
430 | info->state = (status & NDSR_RDDREQ) ? | |
431 | STATE_DMA_READING : STATE_DMA_WRITING; | |
432 | start_data_dma(info); | |
433 | goto NORMAL_IRQ_EXIT; | |
fe69af00 | 434 | } else { |
f8155a40 LW |
435 | info->state = (status & NDSR_RDDREQ) ? |
436 | STATE_PIO_READING : STATE_PIO_WRITING; | |
437 | handle_data_pio(info); | |
fe69af00 | 438 | } |
fe69af00 | 439 | } |
f8155a40 LW |
440 | if (status & NDSR_CS0_CMDD) { |
441 | info->state = STATE_CMD_DONE; | |
442 | is_completed = 1; | |
fe69af00 | 443 | } |
401e67e2 LW |
444 | if (status & NDSR_FLASH_RDY) { |
445 | info->is_ready = 1; | |
f8155a40 | 446 | info->state = STATE_READY; |
401e67e2 | 447 | } |
fe69af00 | 448 | |
f8155a40 LW |
449 | if (status & NDSR_WRCMDREQ) { |
450 | nand_writel(info, NDSR, NDSR_WRCMDREQ); | |
451 | status &= ~NDSR_WRCMDREQ; | |
452 | info->state = STATE_CMD_HANDLE; | |
453 | nand_writel(info, NDCB0, info->ndcb0); | |
454 | nand_writel(info, NDCB0, info->ndcb1); | |
455 | nand_writel(info, NDCB0, info->ndcb2); | |
fe69af00 | 456 | } |
457 | ||
f8155a40 LW |
458 | /* clear NDSR to let the controller exit the IRQ */ |
459 | nand_writel(info, NDSR, status); | |
460 | if (is_completed) | |
461 | complete(&info->cmd_complete); | |
462 | NORMAL_IRQ_EXIT: | |
463 | return IRQ_HANDLED; | |
fe69af00 | 464 | } |
465 | ||
466 | static int pxa3xx_nand_dev_ready(struct mtd_info *mtd) | |
467 | { | |
468 | struct pxa3xx_nand_info *info = mtd->priv; | |
469 | return (nand_readl(info, NDSR) & NDSR_RDY) ? 1 : 0; | |
470 | } | |
471 | ||
472 | static inline int is_buf_blank(uint8_t *buf, size_t len) | |
473 | { | |
474 | for (; len > 0; len--) | |
475 | if (*buf++ != 0xff) | |
476 | return 0; | |
477 | return 1; | |
478 | } | |
479 | ||
4eb2da89 LW |
480 | static int prepare_command_pool(struct pxa3xx_nand_info *info, int command, |
481 | uint16_t column, int page_addr) | |
fe69af00 | 482 | { |
4eb2da89 LW |
483 | uint16_t cmd; |
484 | int addr_cycle, exec_cmd, ndcb0; | |
485 | struct mtd_info *mtd = info->mtd; | |
fe69af00 | 486 | |
4eb2da89 LW |
487 | ndcb0 = 0; |
488 | addr_cycle = 0; | |
489 | exec_cmd = 1; | |
490 | ||
491 | /* reset data and oob column point to handle data */ | |
401e67e2 LW |
492 | info->buf_start = 0; |
493 | info->buf_count = 0; | |
4eb2da89 LW |
494 | info->oob_size = 0; |
495 | info->use_ecc = 0; | |
401e67e2 | 496 | info->is_ready = 0; |
4eb2da89 | 497 | info->retcode = ERR_NONE; |
fe69af00 | 498 | |
499 | switch (command) { | |
4eb2da89 LW |
500 | case NAND_CMD_READ0: |
501 | case NAND_CMD_PAGEPROG: | |
502 | info->use_ecc = 1; | |
fe69af00 | 503 | case NAND_CMD_READOOB: |
4eb2da89 | 504 | pxa3xx_set_datasize(info); |
fe69af00 | 505 | break; |
4eb2da89 LW |
506 | case NAND_CMD_SEQIN: |
507 | exec_cmd = 0; | |
508 | break; | |
509 | default: | |
510 | info->ndcb1 = 0; | |
511 | info->ndcb2 = 0; | |
512 | break; | |
513 | } | |
514 | ||
515 | info->ndcb0 = ndcb0; | |
516 | addr_cycle = NDCB0_ADDR_CYC(info->row_addr_cycles | |
517 | + info->col_addr_cycles); | |
fe69af00 | 518 | |
4eb2da89 LW |
519 | switch (command) { |
520 | case NAND_CMD_READOOB: | |
fe69af00 | 521 | case NAND_CMD_READ0: |
4eb2da89 LW |
522 | cmd = info->cmdset->read1; |
523 | if (command == NAND_CMD_READOOB) | |
524 | info->buf_start = mtd->writesize + column; | |
525 | else | |
526 | info->buf_start = column; | |
527 | ||
528 | if (unlikely(info->page_size < PAGE_CHUNK_SIZE)) | |
529 | info->ndcb0 |= NDCB0_CMD_TYPE(0) | |
530 | | addr_cycle | |
531 | | (cmd & NDCB0_CMD1_MASK); | |
532 | else | |
533 | info->ndcb0 |= NDCB0_CMD_TYPE(0) | |
534 | | NDCB0_DBC | |
535 | | addr_cycle | |
536 | | cmd; | |
fe69af00 | 537 | |
fe69af00 | 538 | case NAND_CMD_SEQIN: |
4eb2da89 LW |
539 | /* small page addr setting */ |
540 | if (unlikely(info->page_size < PAGE_CHUNK_SIZE)) { | |
541 | info->ndcb1 = ((page_addr & 0xFFFFFF) << 8) | |
542 | | (column & 0xFF); | |
543 | ||
544 | info->ndcb2 = 0; | |
545 | } else { | |
546 | info->ndcb1 = ((page_addr & 0xFFFF) << 16) | |
547 | | (column & 0xFFFF); | |
548 | ||
549 | if (page_addr & 0xFF0000) | |
550 | info->ndcb2 = (page_addr & 0xFF0000) >> 16; | |
551 | else | |
552 | info->ndcb2 = 0; | |
553 | } | |
554 | ||
fe69af00 | 555 | info->buf_count = mtd->writesize + mtd->oobsize; |
4eb2da89 | 556 | memset(info->data_buff, 0xFF, info->buf_count); |
fe69af00 | 557 | |
fe69af00 | 558 | break; |
4eb2da89 | 559 | |
fe69af00 | 560 | case NAND_CMD_PAGEPROG: |
4eb2da89 LW |
561 | if (is_buf_blank(info->data_buff, |
562 | (mtd->writesize + mtd->oobsize))) { | |
563 | exec_cmd = 0; | |
564 | break; | |
565 | } | |
fe69af00 | 566 | |
4eb2da89 LW |
567 | cmd = info->cmdset->program; |
568 | info->ndcb0 |= NDCB0_CMD_TYPE(0x1) | |
569 | | NDCB0_AUTO_RS | |
570 | | NDCB0_ST_ROW_EN | |
571 | | NDCB0_DBC | |
572 | | cmd | |
573 | | addr_cycle; | |
fe69af00 | 574 | break; |
4eb2da89 | 575 | |
fe69af00 | 576 | case NAND_CMD_READID: |
4eb2da89 LW |
577 | cmd = info->cmdset->read_id; |
578 | info->buf_count = info->read_id_bytes; | |
579 | info->ndcb0 |= NDCB0_CMD_TYPE(3) | |
580 | | NDCB0_ADDR_CYC(1) | |
581 | | cmd; | |
582 | ||
583 | info->data_size = 8; | |
584 | break; | |
fe69af00 | 585 | case NAND_CMD_STATUS: |
4eb2da89 LW |
586 | cmd = info->cmdset->read_status; |
587 | info->buf_count = 1; | |
588 | info->ndcb0 |= NDCB0_CMD_TYPE(4) | |
589 | | NDCB0_ADDR_CYC(1) | |
590 | | cmd; | |
591 | ||
592 | info->data_size = 8; | |
593 | break; | |
594 | ||
595 | case NAND_CMD_ERASE1: | |
596 | cmd = info->cmdset->erase; | |
597 | info->ndcb0 |= NDCB0_CMD_TYPE(2) | |
598 | | NDCB0_AUTO_RS | |
599 | | NDCB0_ADDR_CYC(3) | |
600 | | NDCB0_DBC | |
601 | | cmd; | |
602 | info->ndcb1 = page_addr; | |
603 | info->ndcb2 = 0; | |
604 | ||
fe69af00 | 605 | break; |
606 | case NAND_CMD_RESET: | |
4eb2da89 LW |
607 | cmd = info->cmdset->reset; |
608 | info->ndcb0 |= NDCB0_CMD_TYPE(5) | |
609 | | cmd; | |
610 | ||
611 | break; | |
612 | ||
613 | case NAND_CMD_ERASE2: | |
614 | exec_cmd = 0; | |
fe69af00 | 615 | break; |
4eb2da89 | 616 | |
fe69af00 | 617 | default: |
4eb2da89 LW |
618 | exec_cmd = 0; |
619 | printk(KERN_ERR "pxa3xx-nand: non-supported" | |
620 | " command %x\n", command); | |
fe69af00 | 621 | break; |
622 | } | |
623 | ||
4eb2da89 LW |
624 | return exec_cmd; |
625 | } | |
626 | ||
627 | static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command, | |
628 | int column, int page_addr) | |
629 | { | |
630 | struct pxa3xx_nand_info *info = mtd->priv; | |
631 | int ret, exec_cmd; | |
632 | ||
633 | /* | |
634 | * if this is a x16 device ,then convert the input | |
635 | * "byte" address into a "word" address appropriate | |
636 | * for indexing a word-oriented device | |
637 | */ | |
638 | if (info->reg_ndcr & NDCR_DWIDTH_M) | |
639 | column /= 2; | |
640 | ||
641 | exec_cmd = prepare_command_pool(info, command, column, page_addr); | |
f8155a40 LW |
642 | if (exec_cmd) { |
643 | init_completion(&info->cmd_complete); | |
644 | pxa3xx_nand_start(info); | |
645 | ||
646 | ret = wait_for_completion_timeout(&info->cmd_complete, | |
647 | CHIP_DELAY_TIMEOUT); | |
648 | if (!ret) { | |
649 | printk(KERN_ERR "Wait time out!!!\n"); | |
650 | /* Stop State Machine for next command cycle */ | |
651 | pxa3xx_nand_stop(info); | |
652 | } | |
653 | info->state = STATE_IDLE; | |
654 | } | |
655 | } | |
656 | ||
657 | static void pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd, | |
658 | struct nand_chip *chip, const uint8_t *buf) | |
659 | { | |
660 | chip->write_buf(mtd, buf, mtd->writesize); | |
661 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
662 | } | |
663 | ||
664 | static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd, | |
665 | struct nand_chip *chip, uint8_t *buf, int page) | |
666 | { | |
667 | struct pxa3xx_nand_info *info = mtd->priv; | |
668 | ||
669 | chip->read_buf(mtd, buf, mtd->writesize); | |
670 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
671 | ||
672 | if (info->retcode == ERR_SBERR) { | |
673 | switch (info->use_ecc) { | |
674 | case 1: | |
675 | mtd->ecc_stats.corrected++; | |
676 | break; | |
677 | case 0: | |
678 | default: | |
679 | break; | |
680 | } | |
681 | } else if (info->retcode == ERR_DBERR) { | |
682 | /* | |
683 | * for blank page (all 0xff), HW will calculate its ECC as | |
684 | * 0, which is different from the ECC information within | |
685 | * OOB, ignore such double bit errors | |
686 | */ | |
687 | if (is_buf_blank(buf, mtd->writesize)) | |
688 | mtd->ecc_stats.failed++; | |
fe69af00 | 689 | } |
f8155a40 LW |
690 | |
691 | return 0; | |
fe69af00 | 692 | } |
693 | ||
694 | static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd) | |
695 | { | |
696 | struct pxa3xx_nand_info *info = mtd->priv; | |
697 | char retval = 0xFF; | |
698 | ||
699 | if (info->buf_start < info->buf_count) | |
700 | /* Has just send a new command? */ | |
701 | retval = info->data_buff[info->buf_start++]; | |
702 | ||
703 | return retval; | |
704 | } | |
705 | ||
706 | static u16 pxa3xx_nand_read_word(struct mtd_info *mtd) | |
707 | { | |
708 | struct pxa3xx_nand_info *info = mtd->priv; | |
709 | u16 retval = 0xFFFF; | |
710 | ||
711 | if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) { | |
712 | retval = *((u16 *)(info->data_buff+info->buf_start)); | |
713 | info->buf_start += 2; | |
714 | } | |
715 | return retval; | |
716 | } | |
717 | ||
718 | static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
719 | { | |
720 | struct pxa3xx_nand_info *info = mtd->priv; | |
721 | int real_len = min_t(size_t, len, info->buf_count - info->buf_start); | |
722 | ||
723 | memcpy(buf, info->data_buff + info->buf_start, real_len); | |
724 | info->buf_start += real_len; | |
725 | } | |
726 | ||
727 | static void pxa3xx_nand_write_buf(struct mtd_info *mtd, | |
728 | const uint8_t *buf, int len) | |
729 | { | |
730 | struct pxa3xx_nand_info *info = mtd->priv; | |
731 | int real_len = min_t(size_t, len, info->buf_count - info->buf_start); | |
732 | ||
733 | memcpy(info->data_buff + info->buf_start, buf, real_len); | |
734 | info->buf_start += real_len; | |
735 | } | |
736 | ||
737 | static int pxa3xx_nand_verify_buf(struct mtd_info *mtd, | |
738 | const uint8_t *buf, int len) | |
739 | { | |
740 | return 0; | |
741 | } | |
742 | ||
743 | static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip) | |
744 | { | |
745 | return; | |
746 | } | |
747 | ||
748 | static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this) | |
749 | { | |
750 | struct pxa3xx_nand_info *info = mtd->priv; | |
751 | ||
752 | /* pxa3xx_nand_send_command has waited for command complete */ | |
753 | if (this->state == FL_WRITING || this->state == FL_ERASING) { | |
754 | if (info->retcode == ERR_NONE) | |
755 | return 0; | |
756 | else { | |
757 | /* | |
758 | * any error make it return 0x01 which will tell | |
759 | * the caller the erase and write fail | |
760 | */ | |
761 | return 0x01; | |
762 | } | |
763 | } | |
764 | ||
765 | return 0; | |
766 | } | |
767 | ||
fe69af00 | 768 | static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, |
c8c17c88 | 769 | const struct pxa3xx_nand_flash *f) |
fe69af00 | 770 | { |
771 | struct platform_device *pdev = info->pdev; | |
772 | struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data; | |
f8155a40 | 773 | uint32_t ndcr = 0x0; /* enable all interrupts */ |
fe69af00 | 774 | |
775 | if (f->page_size != 2048 && f->page_size != 512) | |
776 | return -EINVAL; | |
777 | ||
778 | if (f->flash_width != 16 && f->flash_width != 8) | |
779 | return -EINVAL; | |
780 | ||
781 | /* calculate flash information */ | |
4332c116 | 782 | info->cmdset = &default_cmdset; |
18c81b18 | 783 | info->page_size = f->page_size; |
c8c17c88 | 784 | info->read_id_bytes = (f->page_size == 2048) ? 4 : 2; |
fe69af00 | 785 | |
786 | /* calculate addressing information */ | |
c8c17c88 | 787 | info->col_addr_cycles = (f->page_size == 2048) ? 2 : 1; |
fe69af00 | 788 | |
789 | if (f->num_blocks * f->page_per_block > 65536) | |
c8c17c88 | 790 | info->row_addr_cycles = 3; |
fe69af00 | 791 | else |
c8c17c88 | 792 | info->row_addr_cycles = 2; |
fe69af00 | 793 | |
794 | ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; | |
c8c17c88 | 795 | ndcr |= (info->col_addr_cycles == 2) ? NDCR_RA_START : 0; |
fe69af00 | 796 | ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0; |
797 | ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0; | |
798 | ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0; | |
799 | ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0; | |
800 | ||
c8c17c88 | 801 | ndcr |= NDCR_RD_ID_CNT(info->read_id_bytes); |
fe69af00 | 802 | ndcr |= NDCR_SPARE_EN; /* enable spare by default */ |
803 | ||
804 | info->reg_ndcr = ndcr; | |
805 | ||
806 | pxa3xx_nand_set_timing(info, f->timing); | |
fe69af00 | 807 | return 0; |
808 | } | |
809 | ||
f271049e MR |
810 | static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) |
811 | { | |
812 | uint32_t ndcr = nand_readl(info, NDCR); | |
18c81b18 | 813 | info->page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512; |
38caf7f6 | 814 | /* set info fields needed to read id */ |
18c81b18 | 815 | info->read_id_bytes = (info->page_size == 2048) ? 4 : 2; |
f271049e | 816 | info->reg_ndcr = ndcr; |
52d039fd | 817 | info->cmdset = &default_cmdset; |
f271049e | 818 | |
18c81b18 LW |
819 | info->ndtr0cs0 = nand_readl(info, NDTR0CS0); |
820 | info->ndtr1cs0 = nand_readl(info, NDTR1CS0); | |
f271049e MR |
821 | |
822 | return 0; | |
823 | } | |
824 | ||
fe69af00 | 825 | /* the maximum possible buffer size for large page with OOB data |
826 | * is: 2048 + 64 = 2112 bytes, allocate a page here for both the | |
827 | * data buffer and the DMA descriptor | |
828 | */ | |
829 | #define MAX_BUFF_SIZE PAGE_SIZE | |
830 | ||
831 | static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info) | |
832 | { | |
833 | struct platform_device *pdev = info->pdev; | |
834 | int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc); | |
835 | ||
836 | if (use_dma == 0) { | |
837 | info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL); | |
838 | if (info->data_buff == NULL) | |
839 | return -ENOMEM; | |
840 | return 0; | |
841 | } | |
842 | ||
843 | info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE, | |
844 | &info->data_buff_phys, GFP_KERNEL); | |
845 | if (info->data_buff == NULL) { | |
846 | dev_err(&pdev->dev, "failed to allocate dma buffer\n"); | |
847 | return -ENOMEM; | |
848 | } | |
849 | ||
850 | info->data_buff_size = MAX_BUFF_SIZE; | |
851 | info->data_desc = (void *)info->data_buff + data_desc_offset; | |
852 | info->data_desc_addr = info->data_buff_phys + data_desc_offset; | |
853 | ||
854 | info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW, | |
855 | pxa3xx_nand_data_dma_irq, info); | |
856 | if (info->data_dma_ch < 0) { | |
857 | dev_err(&pdev->dev, "failed to request data dma\n"); | |
858 | dma_free_coherent(&pdev->dev, info->data_buff_size, | |
859 | info->data_buff, info->data_buff_phys); | |
860 | return info->data_dma_ch; | |
861 | } | |
862 | ||
863 | return 0; | |
864 | } | |
865 | ||
401e67e2 LW |
866 | static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info) |
867 | { | |
868 | struct mtd_info *mtd = info->mtd; | |
869 | struct nand_chip *chip = mtd->priv; | |
fe69af00 | 870 | |
401e67e2 LW |
871 | /* use the common timing to make a try */ |
872 | pxa3xx_nand_config_flash(info, &builtin_flash_types[0]); | |
873 | chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0); | |
874 | if (info->is_ready) | |
875 | return 1; | |
876 | else | |
877 | return 0; | |
878 | } | |
fe69af00 | 879 | |
401e67e2 | 880 | static int pxa3xx_nand_scan(struct mtd_info *mtd) |
fe69af00 | 881 | { |
401e67e2 LW |
882 | struct pxa3xx_nand_info *info = mtd->priv; |
883 | struct platform_device *pdev = info->pdev; | |
884 | struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data; | |
4332c116 | 885 | struct nand_flash_dev pxa3xx_flash_ids[2] = { {NULL,}, {NULL,} }; |
401e67e2 LW |
886 | const struct pxa3xx_nand_flash *f = NULL; |
887 | struct nand_chip *chip = mtd->priv; | |
888 | uint32_t id = -1; | |
4332c116 | 889 | uint64_t chipsize; |
401e67e2 LW |
890 | int i, ret, num; |
891 | ||
892 | if (pdata->keep_config && !pxa3xx_nand_detect_config(info)) | |
4332c116 | 893 | goto KEEP_CONFIG; |
401e67e2 LW |
894 | |
895 | ret = pxa3xx_nand_sensing(info); | |
896 | if (!ret) { | |
897 | kfree(mtd); | |
898 | info->mtd = NULL; | |
899 | printk(KERN_INFO "There is no nand chip on cs 0!\n"); | |
900 | ||
901 | return -EINVAL; | |
902 | } | |
903 | ||
904 | chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0); | |
905 | id = *((uint16_t *)(info->data_buff)); | |
906 | if (id != 0) | |
907 | printk(KERN_INFO "Detect a flash id %x\n", id); | |
908 | else { | |
909 | kfree(mtd); | |
910 | info->mtd = NULL; | |
911 | printk(KERN_WARNING "Read out ID 0, potential timing set wrong!!\n"); | |
912 | ||
913 | return -EINVAL; | |
914 | } | |
915 | ||
916 | num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; | |
917 | for (i = 0; i < num; i++) { | |
918 | if (i < pdata->num_flash) | |
919 | f = pdata->flash + i; | |
920 | else | |
921 | f = &builtin_flash_types[i - pdata->num_flash + 1]; | |
922 | ||
923 | /* find the chip in default list */ | |
4332c116 | 924 | if (f->chip_id == id) |
401e67e2 | 925 | break; |
401e67e2 LW |
926 | } |
927 | ||
4332c116 | 928 | if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) { |
401e67e2 LW |
929 | kfree(mtd); |
930 | info->mtd = NULL; | |
931 | printk(KERN_ERR "ERROR!! flash not defined!!!\n"); | |
932 | ||
933 | return -EINVAL; | |
934 | } | |
935 | ||
4332c116 LW |
936 | pxa3xx_nand_config_flash(info, f); |
937 | pxa3xx_flash_ids[0].name = f->name; | |
938 | pxa3xx_flash_ids[0].id = (f->chip_id >> 8) & 0xffff; | |
939 | pxa3xx_flash_ids[0].pagesize = f->page_size; | |
940 | chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size; | |
941 | pxa3xx_flash_ids[0].chipsize = chipsize >> 20; | |
942 | pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block; | |
943 | if (f->flash_width == 16) | |
944 | pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16; | |
945 | KEEP_CONFIG: | |
946 | if (nand_scan_ident(mtd, 1, pxa3xx_flash_ids)) | |
947 | return -ENODEV; | |
948 | /* calculate addressing information */ | |
949 | info->col_addr_cycles = (mtd->writesize >= 2048) ? 2 : 1; | |
950 | info->oob_buff = info->data_buff + mtd->writesize; | |
951 | if ((mtd->size >> chip->page_shift) > 65536) | |
952 | info->row_addr_cycles = 3; | |
953 | else | |
954 | info->row_addr_cycles = 2; | |
955 | mtd->name = mtd_names[0]; | |
401e67e2 LW |
956 | chip->ecc.mode = NAND_ECC_HW; |
957 | chip->ecc.size = f->page_size; | |
401e67e2 LW |
958 | |
959 | chip->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16 : 0; | |
960 | chip->options |= NAND_NO_AUTOINCR; | |
961 | chip->options |= NAND_NO_READRDY; | |
fe69af00 | 962 | |
401e67e2 | 963 | return nand_scan_tail(mtd); |
fe69af00 | 964 | } |
965 | ||
e353a20a LW |
966 | static |
967 | struct pxa3xx_nand_info *alloc_nand_resource(struct platform_device *pdev) | |
fe69af00 | 968 | { |
fe69af00 | 969 | struct pxa3xx_nand_info *info; |
401e67e2 | 970 | struct nand_chip *chip; |
fe69af00 | 971 | struct mtd_info *mtd; |
972 | struct resource *r; | |
e353a20a | 973 | int ret, irq; |
fe69af00 | 974 | |
975 | mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct pxa3xx_nand_info), | |
976 | GFP_KERNEL); | |
a1c06ee1 | 977 | if (!mtd) { |
fe69af00 | 978 | dev_err(&pdev->dev, "failed to allocate memory\n"); |
e353a20a | 979 | return NULL; |
a1c06ee1 | 980 | } |
fe69af00 | 981 | |
982 | info = (struct pxa3xx_nand_info *)(&mtd[1]); | |
401e67e2 | 983 | chip = (struct nand_chip *)(&mtd[1]); |
fe69af00 | 984 | info->pdev = pdev; |
e353a20a | 985 | info->mtd = mtd; |
401e67e2 | 986 | mtd->priv = info; |
82a72d10 | 987 | mtd->owner = THIS_MODULE; |
fe69af00 | 988 | |
401e67e2 LW |
989 | chip->ecc.read_page = pxa3xx_nand_read_page_hwecc; |
990 | chip->ecc.write_page = pxa3xx_nand_write_page_hwecc; | |
991 | chip->controller = &info->controller; | |
992 | chip->waitfunc = pxa3xx_nand_waitfunc; | |
993 | chip->select_chip = pxa3xx_nand_select_chip; | |
994 | chip->dev_ready = pxa3xx_nand_dev_ready; | |
995 | chip->cmdfunc = pxa3xx_nand_cmdfunc; | |
996 | chip->read_word = pxa3xx_nand_read_word; | |
997 | chip->read_byte = pxa3xx_nand_read_byte; | |
998 | chip->read_buf = pxa3xx_nand_read_buf; | |
999 | chip->write_buf = pxa3xx_nand_write_buf; | |
1000 | chip->verify_buf = pxa3xx_nand_verify_buf; | |
1001 | ||
1002 | spin_lock_init(&chip->controller->lock); | |
1003 | init_waitqueue_head(&chip->controller->wq); | |
e0d8b13a | 1004 | info->clk = clk_get(&pdev->dev, NULL); |
fe69af00 | 1005 | if (IS_ERR(info->clk)) { |
1006 | dev_err(&pdev->dev, "failed to get nand clock\n"); | |
1007 | ret = PTR_ERR(info->clk); | |
1008 | goto fail_free_mtd; | |
1009 | } | |
1010 | clk_enable(info->clk); | |
1011 | ||
1012 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
1013 | if (r == NULL) { | |
1014 | dev_err(&pdev->dev, "no resource defined for data DMA\n"); | |
1015 | ret = -ENXIO; | |
1016 | goto fail_put_clk; | |
1017 | } | |
1018 | info->drcmr_dat = r->start; | |
1019 | ||
1020 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
1021 | if (r == NULL) { | |
1022 | dev_err(&pdev->dev, "no resource defined for command DMA\n"); | |
1023 | ret = -ENXIO; | |
1024 | goto fail_put_clk; | |
1025 | } | |
1026 | info->drcmr_cmd = r->start; | |
1027 | ||
1028 | irq = platform_get_irq(pdev, 0); | |
1029 | if (irq < 0) { | |
1030 | dev_err(&pdev->dev, "no IRQ resource defined\n"); | |
1031 | ret = -ENXIO; | |
1032 | goto fail_put_clk; | |
1033 | } | |
1034 | ||
1035 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1036 | if (r == NULL) { | |
1037 | dev_err(&pdev->dev, "no IO memory resource defined\n"); | |
1038 | ret = -ENODEV; | |
1039 | goto fail_put_clk; | |
1040 | } | |
1041 | ||
b2ed3680 | 1042 | r = request_mem_region(r->start, resource_size(r), pdev->name); |
fe69af00 | 1043 | if (r == NULL) { |
1044 | dev_err(&pdev->dev, "failed to request memory resource\n"); | |
1045 | ret = -EBUSY; | |
1046 | goto fail_put_clk; | |
1047 | } | |
1048 | ||
b2ed3680 | 1049 | info->mmio_base = ioremap(r->start, resource_size(r)); |
fe69af00 | 1050 | if (info->mmio_base == NULL) { |
1051 | dev_err(&pdev->dev, "ioremap() failed\n"); | |
1052 | ret = -ENODEV; | |
1053 | goto fail_free_res; | |
1054 | } | |
8638fac8 | 1055 | info->mmio_phys = r->start; |
fe69af00 | 1056 | |
1057 | ret = pxa3xx_nand_init_buff(info); | |
1058 | if (ret) | |
1059 | goto fail_free_io; | |
1060 | ||
346e1259 HZ |
1061 | /* initialize all interrupts to be disabled */ |
1062 | disable_int(info, NDSR_MASK); | |
1063 | ||
dbf5986a HZ |
1064 | ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED, |
1065 | pdev->name, info); | |
fe69af00 | 1066 | if (ret < 0) { |
1067 | dev_err(&pdev->dev, "failed to request IRQ\n"); | |
1068 | goto fail_free_buf; | |
1069 | } | |
1070 | ||
e353a20a | 1071 | platform_set_drvdata(pdev, info); |
fe69af00 | 1072 | |
e353a20a | 1073 | return info; |
fe69af00 | 1074 | |
fe69af00 | 1075 | fail_free_buf: |
401e67e2 | 1076 | free_irq(irq, info); |
fe69af00 | 1077 | if (use_dma) { |
1078 | pxa_free_dma(info->data_dma_ch); | |
1079 | dma_free_coherent(&pdev->dev, info->data_buff_size, | |
1080 | info->data_buff, info->data_buff_phys); | |
1081 | } else | |
1082 | kfree(info->data_buff); | |
1083 | fail_free_io: | |
1084 | iounmap(info->mmio_base); | |
1085 | fail_free_res: | |
b2ed3680 | 1086 | release_mem_region(r->start, resource_size(r)); |
fe69af00 | 1087 | fail_put_clk: |
1088 | clk_disable(info->clk); | |
1089 | clk_put(info->clk); | |
1090 | fail_free_mtd: | |
1091 | kfree(mtd); | |
e353a20a | 1092 | return NULL; |
fe69af00 | 1093 | } |
1094 | ||
1095 | static int pxa3xx_nand_remove(struct platform_device *pdev) | |
1096 | { | |
e353a20a LW |
1097 | struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); |
1098 | struct mtd_info *mtd = info->mtd; | |
82a72d10 | 1099 | struct resource *r; |
dbf5986a | 1100 | int irq; |
fe69af00 | 1101 | |
1102 | platform_set_drvdata(pdev, NULL); | |
1103 | ||
dbf5986a HZ |
1104 | irq = platform_get_irq(pdev, 0); |
1105 | if (irq >= 0) | |
1106 | free_irq(irq, info); | |
fe69af00 | 1107 | if (use_dma) { |
1108 | pxa_free_dma(info->data_dma_ch); | |
1109 | dma_free_writecombine(&pdev->dev, info->data_buff_size, | |
1110 | info->data_buff, info->data_buff_phys); | |
1111 | } else | |
1112 | kfree(info->data_buff); | |
82a72d10 MR |
1113 | |
1114 | iounmap(info->mmio_base); | |
1115 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1116 | release_mem_region(r->start, resource_size(r)); | |
1117 | ||
1118 | clk_disable(info->clk); | |
1119 | clk_put(info->clk); | |
1120 | ||
f8155a40 LW |
1121 | if (mtd) { |
1122 | del_mtd_device(mtd); | |
1123 | #ifdef CONFIG_MTD_PARTITIONS | |
1124 | del_mtd_partitions(mtd); | |
1125 | #endif | |
1126 | kfree(mtd); | |
1127 | } | |
fe69af00 | 1128 | return 0; |
1129 | } | |
1130 | ||
e353a20a LW |
1131 | static int pxa3xx_nand_probe(struct platform_device *pdev) |
1132 | { | |
1133 | struct pxa3xx_nand_platform_data *pdata; | |
1134 | struct pxa3xx_nand_info *info; | |
1135 | ||
1136 | pdata = pdev->dev.platform_data; | |
1137 | if (!pdata) { | |
1138 | dev_err(&pdev->dev, "no platform data defined\n"); | |
1139 | return -ENODEV; | |
1140 | } | |
1141 | ||
1142 | info = alloc_nand_resource(pdev); | |
1143 | if (info == NULL) | |
1144 | return -ENOMEM; | |
1145 | ||
401e67e2 | 1146 | if (pxa3xx_nand_scan(info->mtd)) { |
e353a20a LW |
1147 | dev_err(&pdev->dev, "failed to scan nand\n"); |
1148 | pxa3xx_nand_remove(pdev); | |
1149 | return -ENODEV; | |
1150 | } | |
1151 | ||
1152 | #ifdef CONFIG_MTD_PARTITIONS | |
1153 | if (mtd_has_cmdlinepart()) { | |
1154 | const char *probes[] = { "cmdlinepart", NULL }; | |
1155 | struct mtd_partition *parts; | |
1156 | int nr_parts; | |
1157 | ||
1158 | nr_parts = parse_mtd_partitions(info->mtd, probes, &parts, 0); | |
1159 | ||
1160 | if (nr_parts) | |
f8155a40 | 1161 | return add_mtd_partitions(info->mtd, parts, nr_parts); |
e353a20a LW |
1162 | } |
1163 | ||
f8155a40 | 1164 | return add_mtd_partitions(info->mtd, pdata->parts, pdata->nr_parts); |
e353a20a LW |
1165 | #else |
1166 | return 0; | |
1167 | #endif | |
1168 | } | |
1169 | ||
fe69af00 | 1170 | #ifdef CONFIG_PM |
1171 | static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state) | |
1172 | { | |
e353a20a LW |
1173 | struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); |
1174 | struct mtd_info *mtd = info->mtd; | |
fe69af00 | 1175 | |
f8155a40 | 1176 | if (info->state) { |
fe69af00 | 1177 | dev_err(&pdev->dev, "driver busy, state = %d\n", info->state); |
1178 | return -EAGAIN; | |
1179 | } | |
1180 | ||
1181 | return 0; | |
1182 | } | |
1183 | ||
1184 | static int pxa3xx_nand_resume(struct platform_device *pdev) | |
1185 | { | |
e353a20a LW |
1186 | struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); |
1187 | struct mtd_info *mtd = info->mtd; | |
fe69af00 | 1188 | |
18c81b18 LW |
1189 | nand_writel(info, NDTR0CS0, info->ndtr0cs0); |
1190 | nand_writel(info, NDTR1CS0, info->ndtr1cs0); | |
fe69af00 | 1191 | clk_enable(info->clk); |
1192 | ||
18c81b18 | 1193 | return 0; |
fe69af00 | 1194 | } |
1195 | #else | |
1196 | #define pxa3xx_nand_suspend NULL | |
1197 | #define pxa3xx_nand_resume NULL | |
1198 | #endif | |
1199 | ||
1200 | static struct platform_driver pxa3xx_nand_driver = { | |
1201 | .driver = { | |
1202 | .name = "pxa3xx-nand", | |
1203 | }, | |
1204 | .probe = pxa3xx_nand_probe, | |
1205 | .remove = pxa3xx_nand_remove, | |
1206 | .suspend = pxa3xx_nand_suspend, | |
1207 | .resume = pxa3xx_nand_resume, | |
1208 | }; | |
1209 | ||
1210 | static int __init pxa3xx_nand_init(void) | |
1211 | { | |
1212 | return platform_driver_register(&pxa3xx_nand_driver); | |
1213 | } | |
1214 | module_init(pxa3xx_nand_init); | |
1215 | ||
1216 | static void __exit pxa3xx_nand_exit(void) | |
1217 | { | |
1218 | platform_driver_unregister(&pxa3xx_nand_driver); | |
1219 | } | |
1220 | module_exit(pxa3xx_nand_exit); | |
1221 | ||
1222 | MODULE_LICENSE("GPL"); | |
1223 | MODULE_DESCRIPTION("PXA3xx NAND controller driver"); |