]>
Commit | Line | Data |
---|---|---|
fe69af00 | 1 | /* |
2 | * drivers/mtd/nand/pxa3xx_nand.c | |
3 | * | |
4 | * Copyright © 2005 Intel Corporation | |
5 | * Copyright © 2006 Marvell International Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
a88bdbb5 | 12 | #include <linux/kernel.h> |
fe69af00 | 13 | #include <linux/module.h> |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/mtd/mtd.h> | |
20 | #include <linux/mtd/nand.h> | |
21 | #include <linux/mtd/partitions.h> | |
a1c06ee1 DW |
22 | #include <linux/io.h> |
23 | #include <linux/irq.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
1e7ba630 DM |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
fe69af00 | 27 | |
f4db2e3a EG |
28 | #if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP) |
29 | #define ARCH_HAS_DMA | |
30 | #endif | |
31 | ||
32 | #ifdef ARCH_HAS_DMA | |
afb5b5c9 | 33 | #include <mach/dma.h> |
f4db2e3a EG |
34 | #endif |
35 | ||
293b2da1 | 36 | #include <linux/platform_data/mtd-nand-pxa3xx.h> |
fe69af00 | 37 | |
38 | #define CHIP_DELAY_TIMEOUT (2 * HZ/10) | |
f8155a40 | 39 | #define NAND_STOP_DELAY (2 * HZ/50) |
4eb2da89 | 40 | #define PAGE_CHUNK_SIZE (2048) |
fe69af00 | 41 | |
62e8b851 EG |
42 | /* |
43 | * Define a buffer size for the initial command that detects the flash device: | |
44 | * STATUS, READID and PARAM. The largest of these is the PARAM command, | |
45 | * needing 256 bytes. | |
46 | */ | |
47 | #define INIT_BUFFER_SIZE 256 | |
48 | ||
fe69af00 | 49 | /* registers and bit definitions */ |
50 | #define NDCR (0x00) /* Control register */ | |
51 | #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */ | |
52 | #define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */ | |
53 | #define NDSR (0x14) /* Status Register */ | |
54 | #define NDPCR (0x18) /* Page Count Register */ | |
55 | #define NDBDR0 (0x1C) /* Bad Block Register 0 */ | |
56 | #define NDBDR1 (0x20) /* Bad Block Register 1 */ | |
57 | #define NDDB (0x40) /* Data Buffer */ | |
58 | #define NDCB0 (0x48) /* Command Buffer0 */ | |
59 | #define NDCB1 (0x4C) /* Command Buffer1 */ | |
60 | #define NDCB2 (0x50) /* Command Buffer2 */ | |
61 | ||
62 | #define NDCR_SPARE_EN (0x1 << 31) | |
63 | #define NDCR_ECC_EN (0x1 << 30) | |
64 | #define NDCR_DMA_EN (0x1 << 29) | |
65 | #define NDCR_ND_RUN (0x1 << 28) | |
66 | #define NDCR_DWIDTH_C (0x1 << 27) | |
67 | #define NDCR_DWIDTH_M (0x1 << 26) | |
68 | #define NDCR_PAGE_SZ (0x1 << 24) | |
69 | #define NDCR_NCSX (0x1 << 23) | |
70 | #define NDCR_ND_MODE (0x3 << 21) | |
71 | #define NDCR_NAND_MODE (0x0) | |
72 | #define NDCR_CLR_PG_CNT (0x1 << 20) | |
f8155a40 | 73 | #define NDCR_STOP_ON_UNCOR (0x1 << 19) |
fe69af00 | 74 | #define NDCR_RD_ID_CNT_MASK (0x7 << 16) |
75 | #define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK) | |
76 | ||
77 | #define NDCR_RA_START (0x1 << 15) | |
78 | #define NDCR_PG_PER_BLK (0x1 << 14) | |
79 | #define NDCR_ND_ARB_EN (0x1 << 12) | |
f8155a40 | 80 | #define NDCR_INT_MASK (0xFFF) |
fe69af00 | 81 | |
82 | #define NDSR_MASK (0xfff) | |
f8155a40 LW |
83 | #define NDSR_RDY (0x1 << 12) |
84 | #define NDSR_FLASH_RDY (0x1 << 11) | |
fe69af00 | 85 | #define NDSR_CS0_PAGED (0x1 << 10) |
86 | #define NDSR_CS1_PAGED (0x1 << 9) | |
87 | #define NDSR_CS0_CMDD (0x1 << 8) | |
88 | #define NDSR_CS1_CMDD (0x1 << 7) | |
89 | #define NDSR_CS0_BBD (0x1 << 6) | |
90 | #define NDSR_CS1_BBD (0x1 << 5) | |
91 | #define NDSR_DBERR (0x1 << 4) | |
92 | #define NDSR_SBERR (0x1 << 3) | |
93 | #define NDSR_WRDREQ (0x1 << 2) | |
94 | #define NDSR_RDDREQ (0x1 << 1) | |
95 | #define NDSR_WRCMDREQ (0x1) | |
96 | ||
41a63430 | 97 | #define NDCB0_LEN_OVRD (0x1 << 28) |
4eb2da89 | 98 | #define NDCB0_ST_ROW_EN (0x1 << 26) |
fe69af00 | 99 | #define NDCB0_AUTO_RS (0x1 << 25) |
100 | #define NDCB0_CSEL (0x1 << 24) | |
101 | #define NDCB0_CMD_TYPE_MASK (0x7 << 21) | |
102 | #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK) | |
103 | #define NDCB0_NC (0x1 << 20) | |
104 | #define NDCB0_DBC (0x1 << 19) | |
105 | #define NDCB0_ADDR_CYC_MASK (0x7 << 16) | |
106 | #define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK) | |
107 | #define NDCB0_CMD2_MASK (0xff << 8) | |
108 | #define NDCB0_CMD1_MASK (0xff) | |
109 | #define NDCB0_ADDR_CYC_SHIFT (16) | |
110 | ||
fe69af00 | 111 | /* macros for registers read/write */ |
112 | #define nand_writel(info, off, val) \ | |
113 | __raw_writel((val), (info)->mmio_base + (off)) | |
114 | ||
115 | #define nand_readl(info, off) \ | |
116 | __raw_readl((info)->mmio_base + (off)) | |
117 | ||
118 | /* error code and state */ | |
119 | enum { | |
120 | ERR_NONE = 0, | |
121 | ERR_DMABUSERR = -1, | |
122 | ERR_SENDCMD = -2, | |
123 | ERR_DBERR = -3, | |
124 | ERR_BBERR = -4, | |
223cf6c3 | 125 | ERR_SBERR = -5, |
fe69af00 | 126 | }; |
127 | ||
128 | enum { | |
f8155a40 | 129 | STATE_IDLE = 0, |
d456882b | 130 | STATE_PREPARED, |
fe69af00 | 131 | STATE_CMD_HANDLE, |
132 | STATE_DMA_READING, | |
133 | STATE_DMA_WRITING, | |
134 | STATE_DMA_DONE, | |
135 | STATE_PIO_READING, | |
136 | STATE_PIO_WRITING, | |
f8155a40 LW |
137 | STATE_CMD_DONE, |
138 | STATE_READY, | |
fe69af00 | 139 | }; |
140 | ||
c0f3b864 EG |
141 | enum pxa3xx_nand_variant { |
142 | PXA3XX_NAND_VARIANT_PXA, | |
143 | PXA3XX_NAND_VARIANT_ARMADA370, | |
144 | }; | |
145 | ||
d456882b LW |
146 | struct pxa3xx_nand_host { |
147 | struct nand_chip chip; | |
d456882b LW |
148 | struct mtd_info *mtd; |
149 | void *info_data; | |
150 | ||
151 | /* page size of attached chip */ | |
152 | unsigned int page_size; | |
153 | int use_ecc; | |
f3c8cfc2 | 154 | int cs; |
fe69af00 | 155 | |
d456882b LW |
156 | /* calculated from pxa3xx_nand_flash data */ |
157 | unsigned int col_addr_cycles; | |
158 | unsigned int row_addr_cycles; | |
159 | size_t read_id_bytes; | |
160 | ||
d456882b LW |
161 | }; |
162 | ||
163 | struct pxa3xx_nand_info { | |
401e67e2 | 164 | struct nand_hw_control controller; |
fe69af00 | 165 | struct platform_device *pdev; |
fe69af00 | 166 | |
167 | struct clk *clk; | |
168 | void __iomem *mmio_base; | |
8638fac8 | 169 | unsigned long mmio_phys; |
d456882b | 170 | struct completion cmd_complete; |
fe69af00 | 171 | |
172 | unsigned int buf_start; | |
173 | unsigned int buf_count; | |
62e8b851 | 174 | unsigned int buf_size; |
fe69af00 | 175 | |
176 | /* DMA information */ | |
177 | int drcmr_dat; | |
178 | int drcmr_cmd; | |
179 | ||
180 | unsigned char *data_buff; | |
18c81b18 | 181 | unsigned char *oob_buff; |
fe69af00 | 182 | dma_addr_t data_buff_phys; |
fe69af00 | 183 | int data_dma_ch; |
184 | struct pxa_dma_desc *data_desc; | |
185 | dma_addr_t data_desc_addr; | |
186 | ||
f3c8cfc2 | 187 | struct pxa3xx_nand_host *host[NUM_CHIP_SELECT]; |
fe69af00 | 188 | unsigned int state; |
189 | ||
c0f3b864 EG |
190 | /* |
191 | * This driver supports NFCv1 (as found in PXA SoC) | |
192 | * and NFCv2 (as found in Armada 370/XP SoC). | |
193 | */ | |
194 | enum pxa3xx_nand_variant variant; | |
195 | ||
f3c8cfc2 | 196 | int cs; |
fe69af00 | 197 | int use_ecc; /* use HW ECC ? */ |
198 | int use_dma; /* use DMA ? */ | |
5bb653e8 | 199 | int use_spare; /* use spare ? */ |
401e67e2 | 200 | int is_ready; |
fe69af00 | 201 | |
18c81b18 LW |
202 | unsigned int page_size; /* page size of attached chip */ |
203 | unsigned int data_size; /* data size in FIFO */ | |
d456882b | 204 | unsigned int oob_size; |
fe69af00 | 205 | int retcode; |
fe69af00 | 206 | |
48cf7efa EG |
207 | /* cached register value */ |
208 | uint32_t reg_ndcr; | |
209 | uint32_t ndtr0cs0; | |
210 | uint32_t ndtr1cs0; | |
211 | ||
fe69af00 | 212 | /* generated NDCBx register values */ |
213 | uint32_t ndcb0; | |
214 | uint32_t ndcb1; | |
215 | uint32_t ndcb2; | |
3a1a344a | 216 | uint32_t ndcb3; |
fe69af00 | 217 | }; |
218 | ||
90ab5ee9 | 219 | static bool use_dma = 1; |
fe69af00 | 220 | module_param(use_dma, bool, 0444); |
25985edc | 221 | MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW"); |
fe69af00 | 222 | |
c1f82478 | 223 | static struct pxa3xx_nand_timing timing[] = { |
227a886c LW |
224 | { 40, 80, 60, 100, 80, 100, 90000, 400, 40, }, |
225 | { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, | |
226 | { 10, 25, 15, 25, 15, 30, 25000, 60, 10, }, | |
227 | { 10, 35, 15, 25, 15, 25, 25000, 60, 10, }, | |
d3490dfd HZ |
228 | }; |
229 | ||
c1f82478 | 230 | static struct pxa3xx_nand_flash builtin_flash_types[] = { |
4332c116 LW |
231 | { "DEFAULT FLASH", 0, 0, 2048, 8, 8, 0, &timing[0] }, |
232 | { "64MiB 16-bit", 0x46ec, 32, 512, 16, 16, 4096, &timing[1] }, | |
233 | { "256MiB 8-bit", 0xdaec, 64, 2048, 8, 8, 2048, &timing[1] }, | |
234 | { "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] }, | |
235 | { "128MiB 8-bit", 0xa12c, 64, 2048, 8, 8, 1024, &timing[2] }, | |
236 | { "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, 1024, &timing[2] }, | |
237 | { "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, 4096, &timing[2] }, | |
238 | { "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, 4096, &timing[2] }, | |
239 | { "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, &timing[3] }, | |
d3490dfd HZ |
240 | }; |
241 | ||
227a886c LW |
242 | /* Define a default flash type setting serve as flash detecting only */ |
243 | #define DEFAULT_FLASH_TYPE (&builtin_flash_types[0]) | |
244 | ||
fe69af00 | 245 | #define NDTR0_tCH(c) (min((c), 7) << 19) |
246 | #define NDTR0_tCS(c) (min((c), 7) << 16) | |
247 | #define NDTR0_tWH(c) (min((c), 7) << 11) | |
248 | #define NDTR0_tWP(c) (min((c), 7) << 8) | |
249 | #define NDTR0_tRH(c) (min((c), 7) << 3) | |
250 | #define NDTR0_tRP(c) (min((c), 7) << 0) | |
251 | ||
252 | #define NDTR1_tR(c) (min((c), 65535) << 16) | |
253 | #define NDTR1_tWHR(c) (min((c), 15) << 4) | |
254 | #define NDTR1_tAR(c) (min((c), 15) << 0) | |
255 | ||
256 | /* convert nano-seconds to nand flash controller clock cycles */ | |
93b352fc | 257 | #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000) |
fe69af00 | 258 | |
d456882b | 259 | static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host, |
7dad482e | 260 | const struct pxa3xx_nand_timing *t) |
fe69af00 | 261 | { |
d456882b | 262 | struct pxa3xx_nand_info *info = host->info_data; |
fe69af00 | 263 | unsigned long nand_clk = clk_get_rate(info->clk); |
264 | uint32_t ndtr0, ndtr1; | |
265 | ||
266 | ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) | | |
267 | NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) | | |
268 | NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) | | |
269 | NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) | | |
270 | NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) | | |
271 | NDTR0_tRP(ns2cycle(t->tRP, nand_clk)); | |
272 | ||
273 | ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | | |
274 | NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) | | |
275 | NDTR1_tAR(ns2cycle(t->tAR, nand_clk)); | |
276 | ||
48cf7efa EG |
277 | info->ndtr0cs0 = ndtr0; |
278 | info->ndtr1cs0 = ndtr1; | |
fe69af00 | 279 | nand_writel(info, NDTR0CS0, ndtr0); |
280 | nand_writel(info, NDTR1CS0, ndtr1); | |
281 | } | |
282 | ||
18c81b18 | 283 | static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info) |
fe69af00 | 284 | { |
f3c8cfc2 | 285 | struct pxa3xx_nand_host *host = info->host[info->cs]; |
48cf7efa | 286 | int oob_enable = info->reg_ndcr & NDCR_SPARE_EN; |
9d8b1043 | 287 | |
d456882b | 288 | info->data_size = host->page_size; |
9d8b1043 LW |
289 | if (!oob_enable) { |
290 | info->oob_size = 0; | |
291 | return; | |
292 | } | |
293 | ||
d456882b | 294 | switch (host->page_size) { |
fe69af00 | 295 | case 2048: |
9d8b1043 | 296 | info->oob_size = (info->use_ecc) ? 40 : 64; |
fe69af00 | 297 | break; |
298 | case 512: | |
9d8b1043 | 299 | info->oob_size = (info->use_ecc) ? 8 : 16; |
fe69af00 | 300 | break; |
fe69af00 | 301 | } |
18c81b18 LW |
302 | } |
303 | ||
f8155a40 LW |
304 | /** |
305 | * NOTE: it is a must to set ND_RUN firstly, then write | |
306 | * command buffer, otherwise, it does not work. | |
307 | * We enable all the interrupt at the same time, and | |
308 | * let pxa3xx_nand_irq to handle all logic. | |
309 | */ | |
310 | static void pxa3xx_nand_start(struct pxa3xx_nand_info *info) | |
311 | { | |
312 | uint32_t ndcr; | |
313 | ||
48cf7efa | 314 | ndcr = info->reg_ndcr; |
cd9d1182 EG |
315 | |
316 | if (info->use_ecc) | |
317 | ndcr |= NDCR_ECC_EN; | |
318 | else | |
319 | ndcr &= ~NDCR_ECC_EN; | |
320 | ||
321 | if (info->use_dma) | |
322 | ndcr |= NDCR_DMA_EN; | |
323 | else | |
324 | ndcr &= ~NDCR_DMA_EN; | |
325 | ||
5bb653e8 EG |
326 | if (info->use_spare) |
327 | ndcr |= NDCR_SPARE_EN; | |
328 | else | |
329 | ndcr &= ~NDCR_SPARE_EN; | |
330 | ||
f8155a40 LW |
331 | ndcr |= NDCR_ND_RUN; |
332 | ||
333 | /* clear status bits and run */ | |
334 | nand_writel(info, NDCR, 0); | |
335 | nand_writel(info, NDSR, NDSR_MASK); | |
336 | nand_writel(info, NDCR, ndcr); | |
337 | } | |
338 | ||
339 | static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info) | |
340 | { | |
341 | uint32_t ndcr; | |
342 | int timeout = NAND_STOP_DELAY; | |
343 | ||
344 | /* wait RUN bit in NDCR become 0 */ | |
345 | ndcr = nand_readl(info, NDCR); | |
346 | while ((ndcr & NDCR_ND_RUN) && (timeout-- > 0)) { | |
347 | ndcr = nand_readl(info, NDCR); | |
348 | udelay(1); | |
349 | } | |
350 | ||
351 | if (timeout <= 0) { | |
352 | ndcr &= ~NDCR_ND_RUN; | |
353 | nand_writel(info, NDCR, ndcr); | |
354 | } | |
355 | /* clear status bits */ | |
356 | nand_writel(info, NDSR, NDSR_MASK); | |
357 | } | |
358 | ||
57ff88f0 EG |
359 | static void __maybe_unused |
360 | enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) | |
fe69af00 | 361 | { |
362 | uint32_t ndcr; | |
363 | ||
364 | ndcr = nand_readl(info, NDCR); | |
365 | nand_writel(info, NDCR, ndcr & ~int_mask); | |
366 | } | |
367 | ||
368 | static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) | |
369 | { | |
370 | uint32_t ndcr; | |
371 | ||
372 | ndcr = nand_readl(info, NDCR); | |
373 | nand_writel(info, NDCR, ndcr | int_mask); | |
374 | } | |
375 | ||
f8155a40 | 376 | static void handle_data_pio(struct pxa3xx_nand_info *info) |
fe69af00 | 377 | { |
fe69af00 | 378 | switch (info->state) { |
379 | case STATE_PIO_WRITING: | |
380 | __raw_writesl(info->mmio_base + NDDB, info->data_buff, | |
a88bdbb5 | 381 | DIV_ROUND_UP(info->data_size, 4)); |
9d8b1043 LW |
382 | if (info->oob_size > 0) |
383 | __raw_writesl(info->mmio_base + NDDB, info->oob_buff, | |
384 | DIV_ROUND_UP(info->oob_size, 4)); | |
fe69af00 | 385 | break; |
386 | case STATE_PIO_READING: | |
387 | __raw_readsl(info->mmio_base + NDDB, info->data_buff, | |
a88bdbb5 | 388 | DIV_ROUND_UP(info->data_size, 4)); |
9d8b1043 LW |
389 | if (info->oob_size > 0) |
390 | __raw_readsl(info->mmio_base + NDDB, info->oob_buff, | |
391 | DIV_ROUND_UP(info->oob_size, 4)); | |
fe69af00 | 392 | break; |
393 | default: | |
da675b4e | 394 | dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, |
fe69af00 | 395 | info->state); |
f8155a40 | 396 | BUG(); |
fe69af00 | 397 | } |
fe69af00 | 398 | } |
399 | ||
f4db2e3a | 400 | #ifdef ARCH_HAS_DMA |
f8155a40 | 401 | static void start_data_dma(struct pxa3xx_nand_info *info) |
fe69af00 | 402 | { |
403 | struct pxa_dma_desc *desc = info->data_desc; | |
9d8b1043 | 404 | int dma_len = ALIGN(info->data_size + info->oob_size, 32); |
fe69af00 | 405 | |
406 | desc->ddadr = DDADR_STOP; | |
407 | desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len; | |
408 | ||
f8155a40 LW |
409 | switch (info->state) { |
410 | case STATE_DMA_WRITING: | |
fe69af00 | 411 | desc->dsadr = info->data_buff_phys; |
8638fac8 | 412 | desc->dtadr = info->mmio_phys + NDDB; |
fe69af00 | 413 | desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG; |
f8155a40 LW |
414 | break; |
415 | case STATE_DMA_READING: | |
fe69af00 | 416 | desc->dtadr = info->data_buff_phys; |
8638fac8 | 417 | desc->dsadr = info->mmio_phys + NDDB; |
fe69af00 | 418 | desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC; |
f8155a40 LW |
419 | break; |
420 | default: | |
da675b4e | 421 | dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, |
f8155a40 LW |
422 | info->state); |
423 | BUG(); | |
fe69af00 | 424 | } |
425 | ||
426 | DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch; | |
427 | DDADR(info->data_dma_ch) = info->data_desc_addr; | |
428 | DCSR(info->data_dma_ch) |= DCSR_RUN; | |
429 | } | |
430 | ||
431 | static void pxa3xx_nand_data_dma_irq(int channel, void *data) | |
432 | { | |
433 | struct pxa3xx_nand_info *info = data; | |
434 | uint32_t dcsr; | |
435 | ||
436 | dcsr = DCSR(channel); | |
437 | DCSR(channel) = dcsr; | |
438 | ||
439 | if (dcsr & DCSR_BUSERR) { | |
440 | info->retcode = ERR_DMABUSERR; | |
fe69af00 | 441 | } |
442 | ||
f8155a40 LW |
443 | info->state = STATE_DMA_DONE; |
444 | enable_int(info, NDCR_INT_MASK); | |
445 | nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ); | |
fe69af00 | 446 | } |
f4db2e3a EG |
447 | #else |
448 | static void start_data_dma(struct pxa3xx_nand_info *info) | |
449 | {} | |
450 | #endif | |
fe69af00 | 451 | |
452 | static irqreturn_t pxa3xx_nand_irq(int irq, void *devid) | |
453 | { | |
454 | struct pxa3xx_nand_info *info = devid; | |
f8155a40 | 455 | unsigned int status, is_completed = 0; |
f3c8cfc2 LW |
456 | unsigned int ready, cmd_done; |
457 | ||
458 | if (info->cs == 0) { | |
459 | ready = NDSR_FLASH_RDY; | |
460 | cmd_done = NDSR_CS0_CMDD; | |
461 | } else { | |
462 | ready = NDSR_RDY; | |
463 | cmd_done = NDSR_CS1_CMDD; | |
464 | } | |
fe69af00 | 465 | |
466 | status = nand_readl(info, NDSR); | |
467 | ||
f8155a40 LW |
468 | if (status & NDSR_DBERR) |
469 | info->retcode = ERR_DBERR; | |
470 | if (status & NDSR_SBERR) | |
471 | info->retcode = ERR_SBERR; | |
472 | if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) { | |
473 | /* whether use dma to transfer data */ | |
fe69af00 | 474 | if (info->use_dma) { |
f8155a40 LW |
475 | disable_int(info, NDCR_INT_MASK); |
476 | info->state = (status & NDSR_RDDREQ) ? | |
477 | STATE_DMA_READING : STATE_DMA_WRITING; | |
478 | start_data_dma(info); | |
479 | goto NORMAL_IRQ_EXIT; | |
fe69af00 | 480 | } else { |
f8155a40 LW |
481 | info->state = (status & NDSR_RDDREQ) ? |
482 | STATE_PIO_READING : STATE_PIO_WRITING; | |
483 | handle_data_pio(info); | |
fe69af00 | 484 | } |
fe69af00 | 485 | } |
f3c8cfc2 | 486 | if (status & cmd_done) { |
f8155a40 LW |
487 | info->state = STATE_CMD_DONE; |
488 | is_completed = 1; | |
fe69af00 | 489 | } |
f3c8cfc2 | 490 | if (status & ready) { |
401e67e2 | 491 | info->is_ready = 1; |
f8155a40 | 492 | info->state = STATE_READY; |
401e67e2 | 493 | } |
fe69af00 | 494 | |
f8155a40 LW |
495 | if (status & NDSR_WRCMDREQ) { |
496 | nand_writel(info, NDSR, NDSR_WRCMDREQ); | |
497 | status &= ~NDSR_WRCMDREQ; | |
498 | info->state = STATE_CMD_HANDLE; | |
3a1a344a EG |
499 | |
500 | /* | |
501 | * Command buffer registers NDCB{0-2} (and optionally NDCB3) | |
502 | * must be loaded by writing directly either 12 or 16 | |
503 | * bytes directly to NDCB0, four bytes at a time. | |
504 | * | |
505 | * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored | |
506 | * but each NDCBx register can be read. | |
507 | */ | |
f8155a40 LW |
508 | nand_writel(info, NDCB0, info->ndcb0); |
509 | nand_writel(info, NDCB0, info->ndcb1); | |
510 | nand_writel(info, NDCB0, info->ndcb2); | |
3a1a344a EG |
511 | |
512 | /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */ | |
513 | if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) | |
514 | nand_writel(info, NDCB0, info->ndcb3); | |
fe69af00 | 515 | } |
516 | ||
f8155a40 LW |
517 | /* clear NDSR to let the controller exit the IRQ */ |
518 | nand_writel(info, NDSR, status); | |
519 | if (is_completed) | |
520 | complete(&info->cmd_complete); | |
521 | NORMAL_IRQ_EXIT: | |
522 | return IRQ_HANDLED; | |
fe69af00 | 523 | } |
524 | ||
fe69af00 | 525 | static inline int is_buf_blank(uint8_t *buf, size_t len) |
526 | { | |
527 | for (; len > 0; len--) | |
528 | if (*buf++ != 0xff) | |
529 | return 0; | |
530 | return 1; | |
531 | } | |
532 | ||
4eb2da89 LW |
533 | static int prepare_command_pool(struct pxa3xx_nand_info *info, int command, |
534 | uint16_t column, int page_addr) | |
fe69af00 | 535 | { |
d456882b | 536 | int addr_cycle, exec_cmd; |
f3c8cfc2 LW |
537 | struct pxa3xx_nand_host *host; |
538 | struct mtd_info *mtd; | |
fe69af00 | 539 | |
f3c8cfc2 LW |
540 | host = info->host[info->cs]; |
541 | mtd = host->mtd; | |
4eb2da89 LW |
542 | addr_cycle = 0; |
543 | exec_cmd = 1; | |
544 | ||
545 | /* reset data and oob column point to handle data */ | |
401e67e2 LW |
546 | info->buf_start = 0; |
547 | info->buf_count = 0; | |
4eb2da89 LW |
548 | info->oob_size = 0; |
549 | info->use_ecc = 0; | |
5bb653e8 | 550 | info->use_spare = 1; |
401e67e2 | 551 | info->is_ready = 0; |
4eb2da89 | 552 | info->retcode = ERR_NONE; |
f3c8cfc2 LW |
553 | if (info->cs != 0) |
554 | info->ndcb0 = NDCB0_CSEL; | |
555 | else | |
556 | info->ndcb0 = 0; | |
fe69af00 | 557 | |
558 | switch (command) { | |
4eb2da89 LW |
559 | case NAND_CMD_READ0: |
560 | case NAND_CMD_PAGEPROG: | |
561 | info->use_ecc = 1; | |
fe69af00 | 562 | case NAND_CMD_READOOB: |
4eb2da89 | 563 | pxa3xx_set_datasize(info); |
fe69af00 | 564 | break; |
41a63430 EG |
565 | case NAND_CMD_PARAM: |
566 | info->use_spare = 0; | |
567 | break; | |
4eb2da89 LW |
568 | case NAND_CMD_SEQIN: |
569 | exec_cmd = 0; | |
570 | break; | |
571 | default: | |
572 | info->ndcb1 = 0; | |
573 | info->ndcb2 = 0; | |
3a1a344a | 574 | info->ndcb3 = 0; |
4eb2da89 LW |
575 | break; |
576 | } | |
577 | ||
d456882b LW |
578 | addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles |
579 | + host->col_addr_cycles); | |
fe69af00 | 580 | |
4eb2da89 LW |
581 | switch (command) { |
582 | case NAND_CMD_READOOB: | |
fe69af00 | 583 | case NAND_CMD_READ0: |
ec82135a EG |
584 | info->buf_start = column; |
585 | info->ndcb0 |= NDCB0_CMD_TYPE(0) | |
586 | | addr_cycle | |
587 | | NAND_CMD_READ0; | |
588 | ||
4eb2da89 | 589 | if (command == NAND_CMD_READOOB) |
ec82135a | 590 | info->buf_start += mtd->writesize; |
4eb2da89 | 591 | |
ec82135a EG |
592 | /* Second command setting for large pages */ |
593 | if (host->page_size >= PAGE_CHUNK_SIZE) | |
594 | info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8); | |
fe69af00 | 595 | |
fe69af00 | 596 | case NAND_CMD_SEQIN: |
4eb2da89 | 597 | /* small page addr setting */ |
d456882b | 598 | if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) { |
4eb2da89 LW |
599 | info->ndcb1 = ((page_addr & 0xFFFFFF) << 8) |
600 | | (column & 0xFF); | |
601 | ||
602 | info->ndcb2 = 0; | |
603 | } else { | |
604 | info->ndcb1 = ((page_addr & 0xFFFF) << 16) | |
605 | | (column & 0xFFFF); | |
606 | ||
607 | if (page_addr & 0xFF0000) | |
608 | info->ndcb2 = (page_addr & 0xFF0000) >> 16; | |
609 | else | |
610 | info->ndcb2 = 0; | |
611 | } | |
612 | ||
fe69af00 | 613 | info->buf_count = mtd->writesize + mtd->oobsize; |
4eb2da89 | 614 | memset(info->data_buff, 0xFF, info->buf_count); |
fe69af00 | 615 | |
fe69af00 | 616 | break; |
4eb2da89 | 617 | |
fe69af00 | 618 | case NAND_CMD_PAGEPROG: |
4eb2da89 LW |
619 | if (is_buf_blank(info->data_buff, |
620 | (mtd->writesize + mtd->oobsize))) { | |
621 | exec_cmd = 0; | |
622 | break; | |
623 | } | |
fe69af00 | 624 | |
4eb2da89 LW |
625 | info->ndcb0 |= NDCB0_CMD_TYPE(0x1) |
626 | | NDCB0_AUTO_RS | |
627 | | NDCB0_ST_ROW_EN | |
628 | | NDCB0_DBC | |
ec82135a EG |
629 | | (NAND_CMD_PAGEPROG << 8) |
630 | | NAND_CMD_SEQIN | |
4eb2da89 | 631 | | addr_cycle; |
fe69af00 | 632 | break; |
4eb2da89 | 633 | |
ce0268f6 | 634 | case NAND_CMD_PARAM: |
ce0268f6 EG |
635 | info->buf_count = 256; |
636 | info->ndcb0 |= NDCB0_CMD_TYPE(0) | |
637 | | NDCB0_ADDR_CYC(1) | |
41a63430 | 638 | | NDCB0_LEN_OVRD |
ec82135a | 639 | | command; |
ce0268f6 | 640 | info->ndcb1 = (column & 0xFF); |
41a63430 | 641 | info->ndcb3 = 256; |
ce0268f6 EG |
642 | info->data_size = 256; |
643 | break; | |
644 | ||
fe69af00 | 645 | case NAND_CMD_READID: |
d456882b | 646 | info->buf_count = host->read_id_bytes; |
4eb2da89 LW |
647 | info->ndcb0 |= NDCB0_CMD_TYPE(3) |
648 | | NDCB0_ADDR_CYC(1) | |
ec82135a | 649 | | command; |
d14231f1 | 650 | info->ndcb1 = (column & 0xFF); |
4eb2da89 LW |
651 | |
652 | info->data_size = 8; | |
653 | break; | |
fe69af00 | 654 | case NAND_CMD_STATUS: |
4eb2da89 LW |
655 | info->buf_count = 1; |
656 | info->ndcb0 |= NDCB0_CMD_TYPE(4) | |
657 | | NDCB0_ADDR_CYC(1) | |
ec82135a | 658 | | command; |
4eb2da89 LW |
659 | |
660 | info->data_size = 8; | |
661 | break; | |
662 | ||
663 | case NAND_CMD_ERASE1: | |
4eb2da89 LW |
664 | info->ndcb0 |= NDCB0_CMD_TYPE(2) |
665 | | NDCB0_AUTO_RS | |
666 | | NDCB0_ADDR_CYC(3) | |
667 | | NDCB0_DBC | |
ec82135a EG |
668 | | (NAND_CMD_ERASE2 << 8) |
669 | | NAND_CMD_ERASE1; | |
4eb2da89 LW |
670 | info->ndcb1 = page_addr; |
671 | info->ndcb2 = 0; | |
672 | ||
fe69af00 | 673 | break; |
674 | case NAND_CMD_RESET: | |
4eb2da89 | 675 | info->ndcb0 |= NDCB0_CMD_TYPE(5) |
ec82135a | 676 | | command; |
4eb2da89 LW |
677 | |
678 | break; | |
679 | ||
680 | case NAND_CMD_ERASE2: | |
681 | exec_cmd = 0; | |
fe69af00 | 682 | break; |
4eb2da89 | 683 | |
fe69af00 | 684 | default: |
4eb2da89 | 685 | exec_cmd = 0; |
da675b4e LW |
686 | dev_err(&info->pdev->dev, "non-supported command %x\n", |
687 | command); | |
fe69af00 | 688 | break; |
689 | } | |
690 | ||
4eb2da89 LW |
691 | return exec_cmd; |
692 | } | |
693 | ||
694 | static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command, | |
695 | int column, int page_addr) | |
696 | { | |
d456882b LW |
697 | struct pxa3xx_nand_host *host = mtd->priv; |
698 | struct pxa3xx_nand_info *info = host->info_data; | |
4eb2da89 LW |
699 | int ret, exec_cmd; |
700 | ||
701 | /* | |
702 | * if this is a x16 device ,then convert the input | |
703 | * "byte" address into a "word" address appropriate | |
704 | * for indexing a word-oriented device | |
705 | */ | |
48cf7efa | 706 | if (info->reg_ndcr & NDCR_DWIDTH_M) |
4eb2da89 LW |
707 | column /= 2; |
708 | ||
f3c8cfc2 LW |
709 | /* |
710 | * There may be different NAND chip hooked to | |
711 | * different chip select, so check whether | |
712 | * chip select has been changed, if yes, reset the timing | |
713 | */ | |
714 | if (info->cs != host->cs) { | |
715 | info->cs = host->cs; | |
48cf7efa EG |
716 | nand_writel(info, NDTR0CS0, info->ndtr0cs0); |
717 | nand_writel(info, NDTR1CS0, info->ndtr1cs0); | |
f3c8cfc2 LW |
718 | } |
719 | ||
d456882b | 720 | info->state = STATE_PREPARED; |
4eb2da89 | 721 | exec_cmd = prepare_command_pool(info, command, column, page_addr); |
f8155a40 LW |
722 | if (exec_cmd) { |
723 | init_completion(&info->cmd_complete); | |
724 | pxa3xx_nand_start(info); | |
725 | ||
726 | ret = wait_for_completion_timeout(&info->cmd_complete, | |
727 | CHIP_DELAY_TIMEOUT); | |
728 | if (!ret) { | |
da675b4e | 729 | dev_err(&info->pdev->dev, "Wait time out!!!\n"); |
f8155a40 LW |
730 | /* Stop State Machine for next command cycle */ |
731 | pxa3xx_nand_stop(info); | |
732 | } | |
f8155a40 | 733 | } |
d456882b | 734 | info->state = STATE_IDLE; |
f8155a40 LW |
735 | } |
736 | ||
fdbad98d | 737 | static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd, |
1fbb938d | 738 | struct nand_chip *chip, const uint8_t *buf, int oob_required) |
f8155a40 LW |
739 | { |
740 | chip->write_buf(mtd, buf, mtd->writesize); | |
741 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
fdbad98d JW |
742 | |
743 | return 0; | |
f8155a40 LW |
744 | } |
745 | ||
746 | static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd, | |
1fbb938d BN |
747 | struct nand_chip *chip, uint8_t *buf, int oob_required, |
748 | int page) | |
f8155a40 | 749 | { |
d456882b LW |
750 | struct pxa3xx_nand_host *host = mtd->priv; |
751 | struct pxa3xx_nand_info *info = host->info_data; | |
f8155a40 LW |
752 | |
753 | chip->read_buf(mtd, buf, mtd->writesize); | |
754 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
755 | ||
756 | if (info->retcode == ERR_SBERR) { | |
757 | switch (info->use_ecc) { | |
758 | case 1: | |
759 | mtd->ecc_stats.corrected++; | |
760 | break; | |
761 | case 0: | |
762 | default: | |
763 | break; | |
764 | } | |
765 | } else if (info->retcode == ERR_DBERR) { | |
766 | /* | |
767 | * for blank page (all 0xff), HW will calculate its ECC as | |
768 | * 0, which is different from the ECC information within | |
769 | * OOB, ignore such double bit errors | |
770 | */ | |
771 | if (is_buf_blank(buf, mtd->writesize)) | |
543e32d5 DM |
772 | info->retcode = ERR_NONE; |
773 | else | |
f8155a40 | 774 | mtd->ecc_stats.failed++; |
fe69af00 | 775 | } |
f8155a40 LW |
776 | |
777 | return 0; | |
fe69af00 | 778 | } |
779 | ||
780 | static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd) | |
781 | { | |
d456882b LW |
782 | struct pxa3xx_nand_host *host = mtd->priv; |
783 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 784 | char retval = 0xFF; |
785 | ||
786 | if (info->buf_start < info->buf_count) | |
787 | /* Has just send a new command? */ | |
788 | retval = info->data_buff[info->buf_start++]; | |
789 | ||
790 | return retval; | |
791 | } | |
792 | ||
793 | static u16 pxa3xx_nand_read_word(struct mtd_info *mtd) | |
794 | { | |
d456882b LW |
795 | struct pxa3xx_nand_host *host = mtd->priv; |
796 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 797 | u16 retval = 0xFFFF; |
798 | ||
799 | if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) { | |
800 | retval = *((u16 *)(info->data_buff+info->buf_start)); | |
801 | info->buf_start += 2; | |
802 | } | |
803 | return retval; | |
804 | } | |
805 | ||
806 | static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
807 | { | |
d456882b LW |
808 | struct pxa3xx_nand_host *host = mtd->priv; |
809 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 810 | int real_len = min_t(size_t, len, info->buf_count - info->buf_start); |
811 | ||
812 | memcpy(buf, info->data_buff + info->buf_start, real_len); | |
813 | info->buf_start += real_len; | |
814 | } | |
815 | ||
816 | static void pxa3xx_nand_write_buf(struct mtd_info *mtd, | |
817 | const uint8_t *buf, int len) | |
818 | { | |
d456882b LW |
819 | struct pxa3xx_nand_host *host = mtd->priv; |
820 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 821 | int real_len = min_t(size_t, len, info->buf_count - info->buf_start); |
822 | ||
823 | memcpy(info->data_buff + info->buf_start, buf, real_len); | |
824 | info->buf_start += real_len; | |
825 | } | |
826 | ||
fe69af00 | 827 | static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip) |
828 | { | |
829 | return; | |
830 | } | |
831 | ||
832 | static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this) | |
833 | { | |
d456882b LW |
834 | struct pxa3xx_nand_host *host = mtd->priv; |
835 | struct pxa3xx_nand_info *info = host->info_data; | |
fe69af00 | 836 | |
837 | /* pxa3xx_nand_send_command has waited for command complete */ | |
838 | if (this->state == FL_WRITING || this->state == FL_ERASING) { | |
839 | if (info->retcode == ERR_NONE) | |
840 | return 0; | |
841 | else { | |
842 | /* | |
843 | * any error make it return 0x01 which will tell | |
844 | * the caller the erase and write fail | |
845 | */ | |
846 | return 0x01; | |
847 | } | |
848 | } | |
849 | ||
850 | return 0; | |
851 | } | |
852 | ||
fe69af00 | 853 | static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, |
c8c17c88 | 854 | const struct pxa3xx_nand_flash *f) |
fe69af00 | 855 | { |
856 | struct platform_device *pdev = info->pdev; | |
453810b7 | 857 | struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev); |
f3c8cfc2 | 858 | struct pxa3xx_nand_host *host = info->host[info->cs]; |
f8155a40 | 859 | uint32_t ndcr = 0x0; /* enable all interrupts */ |
fe69af00 | 860 | |
da675b4e LW |
861 | if (f->page_size != 2048 && f->page_size != 512) { |
862 | dev_err(&pdev->dev, "Current only support 2048 and 512 size\n"); | |
fe69af00 | 863 | return -EINVAL; |
da675b4e | 864 | } |
fe69af00 | 865 | |
da675b4e LW |
866 | if (f->flash_width != 16 && f->flash_width != 8) { |
867 | dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n"); | |
fe69af00 | 868 | return -EINVAL; |
da675b4e | 869 | } |
fe69af00 | 870 | |
871 | /* calculate flash information */ | |
d456882b LW |
872 | host->page_size = f->page_size; |
873 | host->read_id_bytes = (f->page_size == 2048) ? 4 : 2; | |
fe69af00 | 874 | |
875 | /* calculate addressing information */ | |
d456882b | 876 | host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1; |
fe69af00 | 877 | |
878 | if (f->num_blocks * f->page_per_block > 65536) | |
d456882b | 879 | host->row_addr_cycles = 3; |
fe69af00 | 880 | else |
d456882b | 881 | host->row_addr_cycles = 2; |
fe69af00 | 882 | |
883 | ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; | |
d456882b | 884 | ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0; |
fe69af00 | 885 | ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0; |
886 | ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0; | |
887 | ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0; | |
888 | ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0; | |
889 | ||
d456882b | 890 | ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes); |
fe69af00 | 891 | ndcr |= NDCR_SPARE_EN; /* enable spare by default */ |
892 | ||
48cf7efa | 893 | info->reg_ndcr = ndcr; |
fe69af00 | 894 | |
d456882b | 895 | pxa3xx_nand_set_timing(host, f->timing); |
fe69af00 | 896 | return 0; |
897 | } | |
898 | ||
f271049e MR |
899 | static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) |
900 | { | |
f3c8cfc2 LW |
901 | /* |
902 | * We set 0 by hard coding here, for we don't support keep_config | |
903 | * when there is more than one chip attached to the controller | |
904 | */ | |
905 | struct pxa3xx_nand_host *host = info->host[0]; | |
f271049e | 906 | uint32_t ndcr = nand_readl(info, NDCR); |
f271049e | 907 | |
d456882b LW |
908 | if (ndcr & NDCR_PAGE_SZ) { |
909 | host->page_size = 2048; | |
910 | host->read_id_bytes = 4; | |
911 | } else { | |
912 | host->page_size = 512; | |
913 | host->read_id_bytes = 2; | |
914 | } | |
915 | ||
48cf7efa EG |
916 | info->reg_ndcr = ndcr & ~NDCR_INT_MASK; |
917 | info->ndtr0cs0 = nand_readl(info, NDTR0CS0); | |
918 | info->ndtr1cs0 = nand_readl(info, NDTR1CS0); | |
f271049e MR |
919 | return 0; |
920 | } | |
921 | ||
f4db2e3a | 922 | #ifdef ARCH_HAS_DMA |
fe69af00 | 923 | static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info) |
924 | { | |
925 | struct platform_device *pdev = info->pdev; | |
62e8b851 | 926 | int data_desc_offset = info->buf_size - sizeof(struct pxa_dma_desc); |
fe69af00 | 927 | |
928 | if (use_dma == 0) { | |
62e8b851 | 929 | info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); |
fe69af00 | 930 | if (info->data_buff == NULL) |
931 | return -ENOMEM; | |
932 | return 0; | |
933 | } | |
934 | ||
62e8b851 | 935 | info->data_buff = dma_alloc_coherent(&pdev->dev, info->buf_size, |
fe69af00 | 936 | &info->data_buff_phys, GFP_KERNEL); |
937 | if (info->data_buff == NULL) { | |
938 | dev_err(&pdev->dev, "failed to allocate dma buffer\n"); | |
939 | return -ENOMEM; | |
940 | } | |
941 | ||
fe69af00 | 942 | info->data_desc = (void *)info->data_buff + data_desc_offset; |
943 | info->data_desc_addr = info->data_buff_phys + data_desc_offset; | |
944 | ||
945 | info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW, | |
946 | pxa3xx_nand_data_dma_irq, info); | |
947 | if (info->data_dma_ch < 0) { | |
948 | dev_err(&pdev->dev, "failed to request data dma\n"); | |
62e8b851 | 949 | dma_free_coherent(&pdev->dev, info->buf_size, |
fe69af00 | 950 | info->data_buff, info->data_buff_phys); |
951 | return info->data_dma_ch; | |
952 | } | |
953 | ||
95b26563 EG |
954 | /* |
955 | * Now that DMA buffers are allocated we turn on | |
956 | * DMA proper for I/O operations. | |
957 | */ | |
958 | info->use_dma = 1; | |
fe69af00 | 959 | return 0; |
960 | } | |
961 | ||
498b6145 EG |
962 | static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info) |
963 | { | |
964 | struct platform_device *pdev = info->pdev; | |
965 | if (use_dma) { | |
966 | pxa_free_dma(info->data_dma_ch); | |
62e8b851 | 967 | dma_free_coherent(&pdev->dev, info->buf_size, |
498b6145 EG |
968 | info->data_buff, info->data_buff_phys); |
969 | } else { | |
970 | kfree(info->data_buff); | |
971 | } | |
972 | } | |
f4db2e3a EG |
973 | #else |
974 | static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info) | |
975 | { | |
62e8b851 | 976 | info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); |
f4db2e3a EG |
977 | if (info->data_buff == NULL) |
978 | return -ENOMEM; | |
979 | return 0; | |
980 | } | |
981 | ||
982 | static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info) | |
983 | { | |
984 | kfree(info->data_buff); | |
985 | } | |
986 | #endif | |
498b6145 | 987 | |
401e67e2 LW |
988 | static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info) |
989 | { | |
f3c8cfc2 | 990 | struct mtd_info *mtd; |
d456882b | 991 | int ret; |
f3c8cfc2 | 992 | mtd = info->host[info->cs]->mtd; |
401e67e2 | 993 | /* use the common timing to make a try */ |
d456882b LW |
994 | ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]); |
995 | if (ret) | |
996 | return ret; | |
997 | ||
998 | pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RESET, 0, 0); | |
401e67e2 | 999 | if (info->is_ready) |
401e67e2 | 1000 | return 0; |
d456882b LW |
1001 | |
1002 | return -ENODEV; | |
401e67e2 | 1003 | } |
fe69af00 | 1004 | |
401e67e2 | 1005 | static int pxa3xx_nand_scan(struct mtd_info *mtd) |
fe69af00 | 1006 | { |
d456882b LW |
1007 | struct pxa3xx_nand_host *host = mtd->priv; |
1008 | struct pxa3xx_nand_info *info = host->info_data; | |
401e67e2 | 1009 | struct platform_device *pdev = info->pdev; |
453810b7 | 1010 | struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev); |
0fab028b | 1011 | struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL; |
401e67e2 LW |
1012 | const struct pxa3xx_nand_flash *f = NULL; |
1013 | struct nand_chip *chip = mtd->priv; | |
1014 | uint32_t id = -1; | |
4332c116 | 1015 | uint64_t chipsize; |
401e67e2 LW |
1016 | int i, ret, num; |
1017 | ||
1018 | if (pdata->keep_config && !pxa3xx_nand_detect_config(info)) | |
4332c116 | 1019 | goto KEEP_CONFIG; |
401e67e2 LW |
1020 | |
1021 | ret = pxa3xx_nand_sensing(info); | |
d456882b | 1022 | if (ret) { |
f3c8cfc2 LW |
1023 | dev_info(&info->pdev->dev, "There is no chip on cs %d!\n", |
1024 | info->cs); | |
401e67e2 | 1025 | |
d456882b | 1026 | return ret; |
401e67e2 LW |
1027 | } |
1028 | ||
1029 | chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0); | |
1030 | id = *((uint16_t *)(info->data_buff)); | |
1031 | if (id != 0) | |
da675b4e | 1032 | dev_info(&info->pdev->dev, "Detect a flash id %x\n", id); |
401e67e2 | 1033 | else { |
da675b4e LW |
1034 | dev_warn(&info->pdev->dev, |
1035 | "Read out ID 0, potential timing set wrong!!\n"); | |
401e67e2 LW |
1036 | |
1037 | return -EINVAL; | |
1038 | } | |
1039 | ||
1040 | num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; | |
1041 | for (i = 0; i < num; i++) { | |
1042 | if (i < pdata->num_flash) | |
1043 | f = pdata->flash + i; | |
1044 | else | |
1045 | f = &builtin_flash_types[i - pdata->num_flash + 1]; | |
1046 | ||
1047 | /* find the chip in default list */ | |
4332c116 | 1048 | if (f->chip_id == id) |
401e67e2 | 1049 | break; |
401e67e2 LW |
1050 | } |
1051 | ||
4332c116 | 1052 | if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) { |
da675b4e | 1053 | dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n"); |
401e67e2 LW |
1054 | |
1055 | return -EINVAL; | |
1056 | } | |
1057 | ||
d456882b LW |
1058 | ret = pxa3xx_nand_config_flash(info, f); |
1059 | if (ret) { | |
1060 | dev_err(&info->pdev->dev, "ERROR! Configure failed\n"); | |
1061 | return ret; | |
1062 | } | |
1063 | ||
4332c116 | 1064 | pxa3xx_flash_ids[0].name = f->name; |
68aa352d | 1065 | pxa3xx_flash_ids[0].dev_id = (f->chip_id >> 8) & 0xffff; |
4332c116 LW |
1066 | pxa3xx_flash_ids[0].pagesize = f->page_size; |
1067 | chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size; | |
1068 | pxa3xx_flash_ids[0].chipsize = chipsize >> 20; | |
1069 | pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block; | |
1070 | if (f->flash_width == 16) | |
1071 | pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16; | |
0fab028b LW |
1072 | pxa3xx_flash_ids[1].name = NULL; |
1073 | def = pxa3xx_flash_ids; | |
4332c116 | 1074 | KEEP_CONFIG: |
d456882b LW |
1075 | chip->ecc.mode = NAND_ECC_HW; |
1076 | chip->ecc.size = host->page_size; | |
6a918bad | 1077 | chip->ecc.strength = 1; |
d456882b | 1078 | |
48cf7efa | 1079 | if (info->reg_ndcr & NDCR_DWIDTH_M) |
d456882b LW |
1080 | chip->options |= NAND_BUSWIDTH_16; |
1081 | ||
0fab028b | 1082 | if (nand_scan_ident(mtd, 1, def)) |
4332c116 LW |
1083 | return -ENODEV; |
1084 | /* calculate addressing information */ | |
d456882b LW |
1085 | if (mtd->writesize >= 2048) |
1086 | host->col_addr_cycles = 2; | |
1087 | else | |
1088 | host->col_addr_cycles = 1; | |
1089 | ||
62e8b851 EG |
1090 | /* release the initial buffer */ |
1091 | kfree(info->data_buff); | |
1092 | ||
1093 | /* allocate the real data + oob buffer */ | |
1094 | info->buf_size = mtd->writesize + mtd->oobsize; | |
1095 | ret = pxa3xx_nand_init_buff(info); | |
1096 | if (ret) | |
1097 | return ret; | |
4332c116 | 1098 | info->oob_buff = info->data_buff + mtd->writesize; |
62e8b851 | 1099 | |
4332c116 | 1100 | if ((mtd->size >> chip->page_shift) > 65536) |
d456882b | 1101 | host->row_addr_cycles = 3; |
4332c116 | 1102 | else |
d456882b | 1103 | host->row_addr_cycles = 2; |
401e67e2 | 1104 | return nand_scan_tail(mtd); |
fe69af00 | 1105 | } |
1106 | ||
d456882b | 1107 | static int alloc_nand_resource(struct platform_device *pdev) |
fe69af00 | 1108 | { |
f3c8cfc2 | 1109 | struct pxa3xx_nand_platform_data *pdata; |
fe69af00 | 1110 | struct pxa3xx_nand_info *info; |
d456882b | 1111 | struct pxa3xx_nand_host *host; |
6e308f87 | 1112 | struct nand_chip *chip = NULL; |
fe69af00 | 1113 | struct mtd_info *mtd; |
1114 | struct resource *r; | |
f3c8cfc2 | 1115 | int ret, irq, cs; |
fe69af00 | 1116 | |
453810b7 | 1117 | pdata = dev_get_platdata(&pdev->dev); |
4c073cd2 EG |
1118 | info = devm_kzalloc(&pdev->dev, sizeof(*info) + (sizeof(*mtd) + |
1119 | sizeof(*host)) * pdata->num_cs, GFP_KERNEL); | |
1120 | if (!info) | |
d456882b | 1121 | return -ENOMEM; |
fe69af00 | 1122 | |
fe69af00 | 1123 | info->pdev = pdev; |
f3c8cfc2 LW |
1124 | for (cs = 0; cs < pdata->num_cs; cs++) { |
1125 | mtd = (struct mtd_info *)((unsigned int)&info[1] + | |
1126 | (sizeof(*mtd) + sizeof(*host)) * cs); | |
1127 | chip = (struct nand_chip *)(&mtd[1]); | |
1128 | host = (struct pxa3xx_nand_host *)chip; | |
1129 | info->host[cs] = host; | |
1130 | host->mtd = mtd; | |
1131 | host->cs = cs; | |
1132 | host->info_data = info; | |
1133 | mtd->priv = host; | |
1134 | mtd->owner = THIS_MODULE; | |
1135 | ||
1136 | chip->ecc.read_page = pxa3xx_nand_read_page_hwecc; | |
1137 | chip->ecc.write_page = pxa3xx_nand_write_page_hwecc; | |
1138 | chip->controller = &info->controller; | |
1139 | chip->waitfunc = pxa3xx_nand_waitfunc; | |
1140 | chip->select_chip = pxa3xx_nand_select_chip; | |
1141 | chip->cmdfunc = pxa3xx_nand_cmdfunc; | |
1142 | chip->read_word = pxa3xx_nand_read_word; | |
1143 | chip->read_byte = pxa3xx_nand_read_byte; | |
1144 | chip->read_buf = pxa3xx_nand_read_buf; | |
1145 | chip->write_buf = pxa3xx_nand_write_buf; | |
f3c8cfc2 | 1146 | } |
401e67e2 LW |
1147 | |
1148 | spin_lock_init(&chip->controller->lock); | |
1149 | init_waitqueue_head(&chip->controller->wq); | |
9ca7944d | 1150 | info->clk = devm_clk_get(&pdev->dev, NULL); |
fe69af00 | 1151 | if (IS_ERR(info->clk)) { |
1152 | dev_err(&pdev->dev, "failed to get nand clock\n"); | |
4c073cd2 | 1153 | return PTR_ERR(info->clk); |
fe69af00 | 1154 | } |
1f8eaff2 EG |
1155 | ret = clk_prepare_enable(info->clk); |
1156 | if (ret < 0) | |
1157 | return ret; | |
fe69af00 | 1158 | |
6b45c1ee EG |
1159 | if (use_dma) { |
1160 | /* | |
1161 | * This is a dirty hack to make this driver work from | |
1162 | * devicetree bindings. It can be removed once we have | |
1163 | * a prober DMA controller framework for DT. | |
1164 | */ | |
1165 | if (pdev->dev.of_node && | |
1166 | of_machine_is_compatible("marvell,pxa3xx")) { | |
1167 | info->drcmr_dat = 97; | |
1168 | info->drcmr_cmd = 99; | |
1169 | } else { | |
1170 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
1171 | if (r == NULL) { | |
1172 | dev_err(&pdev->dev, | |
1173 | "no resource defined for data DMA\n"); | |
1174 | ret = -ENXIO; | |
1175 | goto fail_disable_clk; | |
1176 | } | |
1177 | info->drcmr_dat = r->start; | |
1178 | ||
1179 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
1180 | if (r == NULL) { | |
1181 | dev_err(&pdev->dev, | |
1182 | "no resource defined for cmd DMA\n"); | |
1183 | ret = -ENXIO; | |
1184 | goto fail_disable_clk; | |
1185 | } | |
1186 | info->drcmr_cmd = r->start; | |
1e7ba630 | 1187 | } |
fe69af00 | 1188 | } |
fe69af00 | 1189 | |
1190 | irq = platform_get_irq(pdev, 0); | |
1191 | if (irq < 0) { | |
1192 | dev_err(&pdev->dev, "no IRQ resource defined\n"); | |
1193 | ret = -ENXIO; | |
9ca7944d | 1194 | goto fail_disable_clk; |
fe69af00 | 1195 | } |
1196 | ||
1197 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
0ddd846f EG |
1198 | info->mmio_base = devm_ioremap_resource(&pdev->dev, r); |
1199 | if (IS_ERR(info->mmio_base)) { | |
1200 | ret = PTR_ERR(info->mmio_base); | |
9ca7944d | 1201 | goto fail_disable_clk; |
fe69af00 | 1202 | } |
8638fac8 | 1203 | info->mmio_phys = r->start; |
fe69af00 | 1204 | |
62e8b851 EG |
1205 | /* Allocate a buffer to allow flash detection */ |
1206 | info->buf_size = INIT_BUFFER_SIZE; | |
1207 | info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); | |
1208 | if (info->data_buff == NULL) { | |
1209 | ret = -ENOMEM; | |
9ca7944d | 1210 | goto fail_disable_clk; |
62e8b851 | 1211 | } |
fe69af00 | 1212 | |
346e1259 HZ |
1213 | /* initialize all interrupts to be disabled */ |
1214 | disable_int(info, NDSR_MASK); | |
1215 | ||
dbf5986a HZ |
1216 | ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED, |
1217 | pdev->name, info); | |
fe69af00 | 1218 | if (ret < 0) { |
1219 | dev_err(&pdev->dev, "failed to request IRQ\n"); | |
1220 | goto fail_free_buf; | |
1221 | } | |
1222 | ||
e353a20a | 1223 | platform_set_drvdata(pdev, info); |
fe69af00 | 1224 | |
d456882b | 1225 | return 0; |
fe69af00 | 1226 | |
fe69af00 | 1227 | fail_free_buf: |
401e67e2 | 1228 | free_irq(irq, info); |
62e8b851 | 1229 | kfree(info->data_buff); |
9ca7944d | 1230 | fail_disable_clk: |
fb32061f | 1231 | clk_disable_unprepare(info->clk); |
d456882b | 1232 | return ret; |
fe69af00 | 1233 | } |
1234 | ||
1235 | static int pxa3xx_nand_remove(struct platform_device *pdev) | |
1236 | { | |
e353a20a | 1237 | struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); |
f3c8cfc2 | 1238 | struct pxa3xx_nand_platform_data *pdata; |
f3c8cfc2 | 1239 | int irq, cs; |
fe69af00 | 1240 | |
d456882b LW |
1241 | if (!info) |
1242 | return 0; | |
1243 | ||
453810b7 | 1244 | pdata = dev_get_platdata(&pdev->dev); |
fe69af00 | 1245 | |
dbf5986a HZ |
1246 | irq = platform_get_irq(pdev, 0); |
1247 | if (irq >= 0) | |
1248 | free_irq(irq, info); | |
498b6145 | 1249 | pxa3xx_nand_free_buff(info); |
82a72d10 | 1250 | |
fb32061f | 1251 | clk_disable_unprepare(info->clk); |
82a72d10 | 1252 | |
f3c8cfc2 LW |
1253 | for (cs = 0; cs < pdata->num_cs; cs++) |
1254 | nand_release(info->host[cs]->mtd); | |
fe69af00 | 1255 | return 0; |
1256 | } | |
1257 | ||
1e7ba630 | 1258 | static struct of_device_id pxa3xx_nand_dt_ids[] = { |
c0f3b864 EG |
1259 | { |
1260 | .compatible = "marvell,pxa3xx-nand", | |
1261 | .data = (void *)PXA3XX_NAND_VARIANT_PXA, | |
1262 | }, | |
1263 | { | |
1264 | .compatible = "marvell,armada370-nand", | |
1265 | .data = (void *)PXA3XX_NAND_VARIANT_ARMADA370, | |
1266 | }, | |
1e7ba630 DM |
1267 | {} |
1268 | }; | |
f3958984 | 1269 | MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids); |
1e7ba630 | 1270 | |
c0f3b864 EG |
1271 | static enum pxa3xx_nand_variant |
1272 | pxa3xx_nand_get_variant(struct platform_device *pdev) | |
1273 | { | |
1274 | const struct of_device_id *of_id = | |
1275 | of_match_device(pxa3xx_nand_dt_ids, &pdev->dev); | |
1276 | if (!of_id) | |
1277 | return PXA3XX_NAND_VARIANT_PXA; | |
1278 | return (enum pxa3xx_nand_variant)of_id->data; | |
1279 | } | |
1280 | ||
1e7ba630 DM |
1281 | static int pxa3xx_nand_probe_dt(struct platform_device *pdev) |
1282 | { | |
1283 | struct pxa3xx_nand_platform_data *pdata; | |
1284 | struct device_node *np = pdev->dev.of_node; | |
1285 | const struct of_device_id *of_id = | |
1286 | of_match_device(pxa3xx_nand_dt_ids, &pdev->dev); | |
1287 | ||
1288 | if (!of_id) | |
1289 | return 0; | |
1290 | ||
1291 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1292 | if (!pdata) | |
1293 | return -ENOMEM; | |
1294 | ||
1295 | if (of_get_property(np, "marvell,nand-enable-arbiter", NULL)) | |
1296 | pdata->enable_arbiter = 1; | |
1297 | if (of_get_property(np, "marvell,nand-keep-config", NULL)) | |
1298 | pdata->keep_config = 1; | |
1299 | of_property_read_u32(np, "num-cs", &pdata->num_cs); | |
1300 | ||
1301 | pdev->dev.platform_data = pdata; | |
1302 | ||
1303 | return 0; | |
1304 | } | |
1e7ba630 | 1305 | |
e353a20a LW |
1306 | static int pxa3xx_nand_probe(struct platform_device *pdev) |
1307 | { | |
1308 | struct pxa3xx_nand_platform_data *pdata; | |
1e7ba630 | 1309 | struct mtd_part_parser_data ppdata = {}; |
e353a20a | 1310 | struct pxa3xx_nand_info *info; |
f3c8cfc2 | 1311 | int ret, cs, probe_success; |
e353a20a | 1312 | |
f4db2e3a EG |
1313 | #ifndef ARCH_HAS_DMA |
1314 | if (use_dma) { | |
1315 | use_dma = 0; | |
1316 | dev_warn(&pdev->dev, | |
1317 | "This platform can't do DMA on this device\n"); | |
1318 | } | |
1319 | #endif | |
1e7ba630 DM |
1320 | ret = pxa3xx_nand_probe_dt(pdev); |
1321 | if (ret) | |
1322 | return ret; | |
1323 | ||
453810b7 | 1324 | pdata = dev_get_platdata(&pdev->dev); |
e353a20a LW |
1325 | if (!pdata) { |
1326 | dev_err(&pdev->dev, "no platform data defined\n"); | |
1327 | return -ENODEV; | |
1328 | } | |
1329 | ||
d456882b LW |
1330 | ret = alloc_nand_resource(pdev); |
1331 | if (ret) { | |
1332 | dev_err(&pdev->dev, "alloc nand resource failed\n"); | |
1333 | return ret; | |
1334 | } | |
e353a20a | 1335 | |
d456882b | 1336 | info = platform_get_drvdata(pdev); |
c0f3b864 | 1337 | info->variant = pxa3xx_nand_get_variant(pdev); |
f3c8cfc2 LW |
1338 | probe_success = 0; |
1339 | for (cs = 0; cs < pdata->num_cs; cs++) { | |
b7655bcb | 1340 | struct mtd_info *mtd = info->host[cs]->mtd; |
f455578d | 1341 | |
18a84e93 EG |
1342 | /* |
1343 | * The mtd name matches the one used in 'mtdparts' kernel | |
1344 | * parameter. This name cannot be changed or otherwise | |
1345 | * user's mtd partitions configuration would get broken. | |
1346 | */ | |
1347 | mtd->name = "pxa3xx_nand-0"; | |
f3c8cfc2 | 1348 | info->cs = cs; |
b7655bcb | 1349 | ret = pxa3xx_nand_scan(mtd); |
f3c8cfc2 LW |
1350 | if (ret) { |
1351 | dev_warn(&pdev->dev, "failed to scan nand at cs %d\n", | |
1352 | cs); | |
1353 | continue; | |
1354 | } | |
1355 | ||
1e7ba630 | 1356 | ppdata.of_node = pdev->dev.of_node; |
b7655bcb | 1357 | ret = mtd_device_parse_register(mtd, NULL, |
1e7ba630 | 1358 | &ppdata, pdata->parts[cs], |
42d7fbe2 | 1359 | pdata->nr_parts[cs]); |
f3c8cfc2 LW |
1360 | if (!ret) |
1361 | probe_success = 1; | |
1362 | } | |
1363 | ||
1364 | if (!probe_success) { | |
e353a20a LW |
1365 | pxa3xx_nand_remove(pdev); |
1366 | return -ENODEV; | |
1367 | } | |
1368 | ||
f3c8cfc2 | 1369 | return 0; |
e353a20a LW |
1370 | } |
1371 | ||
fe69af00 | 1372 | #ifdef CONFIG_PM |
1373 | static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state) | |
1374 | { | |
e353a20a | 1375 | struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); |
f3c8cfc2 LW |
1376 | struct pxa3xx_nand_platform_data *pdata; |
1377 | struct mtd_info *mtd; | |
1378 | int cs; | |
fe69af00 | 1379 | |
453810b7 | 1380 | pdata = dev_get_platdata(&pdev->dev); |
f8155a40 | 1381 | if (info->state) { |
fe69af00 | 1382 | dev_err(&pdev->dev, "driver busy, state = %d\n", info->state); |
1383 | return -EAGAIN; | |
1384 | } | |
1385 | ||
f3c8cfc2 LW |
1386 | for (cs = 0; cs < pdata->num_cs; cs++) { |
1387 | mtd = info->host[cs]->mtd; | |
3fe4bae8 | 1388 | mtd_suspend(mtd); |
f3c8cfc2 LW |
1389 | } |
1390 | ||
fe69af00 | 1391 | return 0; |
1392 | } | |
1393 | ||
1394 | static int pxa3xx_nand_resume(struct platform_device *pdev) | |
1395 | { | |
e353a20a | 1396 | struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); |
f3c8cfc2 LW |
1397 | struct pxa3xx_nand_platform_data *pdata; |
1398 | struct mtd_info *mtd; | |
1399 | int cs; | |
051fc41c | 1400 | |
453810b7 | 1401 | pdata = dev_get_platdata(&pdev->dev); |
051fc41c LW |
1402 | /* We don't want to handle interrupt without calling mtd routine */ |
1403 | disable_int(info, NDCR_INT_MASK); | |
fe69af00 | 1404 | |
f3c8cfc2 LW |
1405 | /* |
1406 | * Directly set the chip select to a invalid value, | |
1407 | * then the driver would reset the timing according | |
1408 | * to current chip select at the beginning of cmdfunc | |
1409 | */ | |
1410 | info->cs = 0xff; | |
fe69af00 | 1411 | |
051fc41c LW |
1412 | /* |
1413 | * As the spec says, the NDSR would be updated to 0x1800 when | |
1414 | * doing the nand_clk disable/enable. | |
1415 | * To prevent it damaging state machine of the driver, clear | |
1416 | * all status before resume | |
1417 | */ | |
1418 | nand_writel(info, NDSR, NDSR_MASK); | |
f3c8cfc2 LW |
1419 | for (cs = 0; cs < pdata->num_cs; cs++) { |
1420 | mtd = info->host[cs]->mtd; | |
ead995f8 | 1421 | mtd_resume(mtd); |
f3c8cfc2 LW |
1422 | } |
1423 | ||
18c81b18 | 1424 | return 0; |
fe69af00 | 1425 | } |
1426 | #else | |
1427 | #define pxa3xx_nand_suspend NULL | |
1428 | #define pxa3xx_nand_resume NULL | |
1429 | #endif | |
1430 | ||
1431 | static struct platform_driver pxa3xx_nand_driver = { | |
1432 | .driver = { | |
1433 | .name = "pxa3xx-nand", | |
5576bc7b | 1434 | .of_match_table = pxa3xx_nand_dt_ids, |
fe69af00 | 1435 | }, |
1436 | .probe = pxa3xx_nand_probe, | |
1437 | .remove = pxa3xx_nand_remove, | |
1438 | .suspend = pxa3xx_nand_suspend, | |
1439 | .resume = pxa3xx_nand_resume, | |
1440 | }; | |
1441 | ||
f99640de | 1442 | module_platform_driver(pxa3xx_nand_driver); |
fe69af00 | 1443 | |
1444 | MODULE_LICENSE("GPL"); | |
1445 | MODULE_DESCRIPTION("PXA3xx NAND controller driver"); |