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pxa3xx_nand: fix memory out of bound
[mirror_ubuntu-jammy-kernel.git] / drivers / mtd / nand / pxa3xx_nand.c
CommitLineData
fe69af00 1/*
2 * drivers/mtd/nand/pxa3xx_nand.c
3 *
4 * Copyright © 2005 Intel Corporation
5 * Copyright © 2006 Marvell International Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
a88bdbb5 12#include <linux/kernel.h>
fe69af00 13#include <linux/module.h>
14#include <linux/interrupt.h>
15#include <linux/platform_device.h>
16#include <linux/dma-mapping.h>
17#include <linux/delay.h>
18#include <linux/clk.h>
19#include <linux/mtd/mtd.h>
20#include <linux/mtd/nand.h>
21#include <linux/mtd/partitions.h>
a1c06ee1
DW		 22#include <linux/io.h>
23#include <linux/irq.h>
fe69af00 24
afb5b5c9 25#include <mach/dma.h>
a09e64fb 26#include <mach/pxa3xx_nand.h>
fe69af00 27
28#define CHIP_DELAY_TIMEOUT (2 * HZ/10)
29
30/* registers and bit definitions */
31#define NDCR (0x00) /* Control register */
32#define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
33#define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
34#define NDSR (0x14) /* Status Register */
35#define NDPCR (0x18) /* Page Count Register */
36#define NDBDR0 (0x1C) /* Bad Block Register 0 */
37#define NDBDR1 (0x20) /* Bad Block Register 1 */
38#define NDDB (0x40) /* Data Buffer */
39#define NDCB0 (0x48) /* Command Buffer0 */
40#define NDCB1 (0x4C) /* Command Buffer1 */
41#define NDCB2 (0x50) /* Command Buffer2 */
42
43#define NDCR_SPARE_EN (0x1 << 31)
44#define NDCR_ECC_EN (0x1 << 30)
45#define NDCR_DMA_EN (0x1 << 29)
46#define NDCR_ND_RUN (0x1 << 28)
47#define NDCR_DWIDTH_C (0x1 << 27)
48#define NDCR_DWIDTH_M (0x1 << 26)
49#define NDCR_PAGE_SZ (0x1 << 24)
50#define NDCR_NCSX (0x1 << 23)
51#define NDCR_ND_MODE (0x3 << 21)
52#define NDCR_NAND_MODE (0x0)
53#define NDCR_CLR_PG_CNT (0x1 << 20)
54#define NDCR_CLR_ECC (0x1 << 19)
55#define NDCR_RD_ID_CNT_MASK (0x7 << 16)
56#define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
57
58#define NDCR_RA_START (0x1 << 15)
59#define NDCR_PG_PER_BLK (0x1 << 14)
60#define NDCR_ND_ARB_EN (0x1 << 12)
61
62#define NDSR_MASK (0xfff)
63#define NDSR_RDY (0x1 << 11)
64#define NDSR_CS0_PAGED (0x1 << 10)
65#define NDSR_CS1_PAGED (0x1 << 9)
66#define NDSR_CS0_CMDD (0x1 << 8)
67#define NDSR_CS1_CMDD (0x1 << 7)
68#define NDSR_CS0_BBD (0x1 << 6)
69#define NDSR_CS1_BBD (0x1 << 5)
70#define NDSR_DBERR (0x1 << 4)
71#define NDSR_SBERR (0x1 << 3)
72#define NDSR_WRDREQ (0x1 << 2)
73#define NDSR_RDDREQ (0x1 << 1)
74#define NDSR_WRCMDREQ (0x1)
75
76#define NDCB0_AUTO_RS (0x1 << 25)
77#define NDCB0_CSEL (0x1 << 24)
78#define NDCB0_CMD_TYPE_MASK (0x7 << 21)
79#define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
80#define NDCB0_NC (0x1 << 20)
81#define NDCB0_DBC (0x1 << 19)
82#define NDCB0_ADDR_CYC_MASK (0x7 << 16)
83#define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
84#define NDCB0_CMD2_MASK (0xff << 8)
85#define NDCB0_CMD1_MASK (0xff)
86#define NDCB0_ADDR_CYC_SHIFT (16)
87
88/* dma-able I/O address for the NAND data and commands */
89#define NDCB0_DMA_ADDR (0x43100048)
90#define NDDB_DMA_ADDR (0x43100040)
91
92/* macros for registers read/write */
93#define nand_writel(info, off, val) \
94 __raw_writel((val), (info)->mmio_base + (off))
95
96#define nand_readl(info, off) \
97 __raw_readl((info)->mmio_base + (off))
98
99/* error code and state */
100enum {
101 ERR_NONE = 0,
102 ERR_DMABUSERR = -1,
103 ERR_SENDCMD = -2,
104 ERR_DBERR = -3,
105 ERR_BBERR = -4,
223cf6c3 106 ERR_SBERR = -5,
fe69af00 107};
108
109enum {
110 STATE_READY = 0,
111 STATE_CMD_HANDLE,
112 STATE_DMA_READING,
113 STATE_DMA_WRITING,
114 STATE_DMA_DONE,
115 STATE_PIO_READING,
116 STATE_PIO_WRITING,
117};
118
fe69af00 119struct pxa3xx_nand_info {
120 struct nand_chip nand_chip;
121
122 struct platform_device *pdev;
c8c17c88 123 const struct pxa3xx_nand_flash *flash_info;
fe69af00 124
125 struct clk *clk;
126 void __iomem *mmio_base;
127
128 unsigned int buf_start;
129 unsigned int buf_count;
130
131 /* DMA information */
132 int drcmr_dat;
133 int drcmr_cmd;
134
135 unsigned char *data_buff;
136 dma_addr_t data_buff_phys;
137 size_t data_buff_size;
138 int data_dma_ch;
139 struct pxa_dma_desc *data_desc;
140 dma_addr_t data_desc_addr;
141
142 uint32_t reg_ndcr;
143
144 /* saved column/page_addr during CMD_SEQIN */
145 int seqin_column;
146 int seqin_page_addr;
147
148 /* relate to the command */
149 unsigned int state;
150
151 int use_ecc; /* use HW ECC ? */
152 int use_dma; /* use DMA ? */
153
154 size_t data_size; /* data size in FIFO */
155 int retcode;
156 struct completion cmd_complete;
157
158 /* generated NDCBx register values */
159 uint32_t ndcb0;
160 uint32_t ndcb1;
161 uint32_t ndcb2;
c8c17c88
ES		 162
163 /* calculated from pxa3xx_nand_flash data */
164 size_t oob_size;
165 size_t read_id_bytes;
166
167 unsigned int col_addr_cycles;
168 unsigned int row_addr_cycles;
fe69af00 169};
170
171static int use_dma = 1;
172module_param(use_dma, bool, 0444);
173MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW");
174
f271049e
MR		 175/*
176 * Default NAND flash controller configuration setup by the
177 * bootloader. This configuration is used only when pdata->keep_config is set
178 */
179static struct pxa3xx_nand_timing default_timing;
180static struct pxa3xx_nand_flash default_flash;
181
fe69af00 182static struct pxa3xx_nand_cmdset smallpage_cmdset = {
183 .read1 = 0x0000,
184 .read2 = 0x0050,
185 .program = 0x1080,
186 .read_status = 0x0070,
187 .read_id = 0x0090,
188 .erase = 0xD060,
189 .reset = 0x00FF,
190 .lock = 0x002A,
191 .unlock = 0x2423,
192 .lock_status = 0x007A,
193};
194
195static struct pxa3xx_nand_cmdset largepage_cmdset = {
196 .read1 = 0x3000,
197 .read2 = 0x0050,
198 .program = 0x1080,
199 .read_status = 0x0070,
200 .read_id = 0x0090,
201 .erase = 0xD060,
202 .reset = 0x00FF,
203 .lock = 0x002A,
204 .unlock = 0x2423,
205 .lock_status = 0x007A,
206};
207
f271049e 208#ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
fe69af00 209static struct pxa3xx_nand_timing samsung512MbX16_timing = {
210 .tCH = 10,
211 .tCS = 0,
212 .tWH = 20,
213 .tWP = 40,
214 .tRH = 30,
215 .tRP = 40,
216 .tR = 11123,
217 .tWHR = 110,
218 .tAR = 10,
219};
220
221static struct pxa3xx_nand_flash samsung512MbX16 = {
222 .timing = &samsung512MbX16_timing,
223 .cmdset = &smallpage_cmdset,
224 .page_per_block = 32,
225 .page_size = 512,
226 .flash_width = 16,
227 .dfc_width = 16,
228 .num_blocks = 4096,
229 .chip_id = 0x46ec,
230};
231
232static struct pxa3xx_nand_timing micron_timing = {
233 .tCH = 10,
234 .tCS = 25,
235 .tWH = 15,
236 .tWP = 25,
237 .tRH = 15,
238 .tRP = 25,
239 .tR = 25000,
240 .tWHR = 60,
241 .tAR = 10,
242};
243
244static struct pxa3xx_nand_flash micron1GbX8 = {
245 .timing = &micron_timing,
246 .cmdset = &largepage_cmdset,
247 .page_per_block = 64,
248 .page_size = 2048,
249 .flash_width = 8,
250 .dfc_width = 8,
251 .num_blocks = 1024,
252 .chip_id = 0xa12c,
253};
254
255static struct pxa3xx_nand_flash micron1GbX16 = {
256 .timing = &micron_timing,
257 .cmdset = &largepage_cmdset,
258 .page_per_block = 64,
259 .page_size = 2048,
260 .flash_width = 16,
261 .dfc_width = 16,
262 .num_blocks = 1024,
263 .chip_id = 0xb12c,
264};
265
4262bd29
SL		 266static struct pxa3xx_nand_timing stm2GbX16_timing = {
267 .tCH = 10,
268 .tCS = 35,
269 .tWH = 15,
270 .tWP = 25,
271 .tRH = 15,
272 .tRP = 25,
273 .tR = 25000,
274 .tWHR = 60,
275 .tAR = 10,
276};
277
278static struct pxa3xx_nand_flash stm2GbX16 = {
279 .timing = &stm2GbX16_timing,
e93f1be5 280 .cmdset = &largepage_cmdset,
4262bd29
SL		 281 .page_per_block = 64,
282 .page_size = 2048,
283 .flash_width = 16,
284 .dfc_width = 16,
285 .num_blocks = 2048,
286 .chip_id = 0xba20,
287};
288
fe69af00 289static struct pxa3xx_nand_flash *builtin_flash_types[] = {
290 &samsung512MbX16,
291 &micron1GbX8,
292 &micron1GbX16,
4262bd29 293 &stm2GbX16,
fe69af00 294};
80ebf20f 295#endif /* CONFIG_MTD_NAND_PXA3xx_BUILTIN */
fe69af00 296
297#define NDTR0_tCH(c) (min((c), 7) << 19)
298#define NDTR0_tCS(c) (min((c), 7) << 16)
299#define NDTR0_tWH(c) (min((c), 7) << 11)
300#define NDTR0_tWP(c) (min((c), 7) << 8)
301#define NDTR0_tRH(c) (min((c), 7) << 3)
302#define NDTR0_tRP(c) (min((c), 7) << 0)
303
304#define NDTR1_tR(c) (min((c), 65535) << 16)
305#define NDTR1_tWHR(c) (min((c), 15) << 4)
306#define NDTR1_tAR(c) (min((c), 15) << 0)
307
f271049e
MR		 308#define tCH_NDTR0(r) (((r) >> 19) & 0x7)
309#define tCS_NDTR0(r) (((r) >> 16) & 0x7)
310#define tWH_NDTR0(r) (((r) >> 11) & 0x7)
311#define tWP_NDTR0(r) (((r) >> 8) & 0x7)
312#define tRH_NDTR0(r) (((r) >> 3) & 0x7)
313#define tRP_NDTR0(r) (((r) >> 0) & 0x7)
314
315#define tR_NDTR1(r) (((r) >> 16) & 0xffff)
316#define tWHR_NDTR1(r) (((r) >> 4) & 0xf)
317#define tAR_NDTR1(r) (((r) >> 0) & 0xf)
318
fe69af00 319/* convert nano-seconds to nand flash controller clock cycles */
5b0d4d7c 320#define ns2cycle(ns, clk) (int)(((ns) * (clk / 1000000) / 1000) - 1)
fe69af00 321
f271049e
MR		 322/* convert nand flash controller clock cycles to nano-seconds */
323#define cycle2ns(c, clk) ((((c) + 1) * 1000000 + clk / 500) / (clk / 1000))
324
fe69af00 325static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
7dad482e 326 const struct pxa3xx_nand_timing *t)
fe69af00 327{
328 unsigned long nand_clk = clk_get_rate(info->clk);
329 uint32_t ndtr0, ndtr1;
330
331 ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
332 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
333 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
334 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
335 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
336 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
337
338 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
339 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
340 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
341
342 nand_writel(info, NDTR0CS0, ndtr0);
343 nand_writel(info, NDTR1CS0, ndtr1);
344}
345
346#define WAIT_EVENT_TIMEOUT 10
347
348static int wait_for_event(struct pxa3xx_nand_info *info, uint32_t event)
349{
350 int timeout = WAIT_EVENT_TIMEOUT;
351 uint32_t ndsr;
352
353 while (timeout--) {
354 ndsr = nand_readl(info, NDSR) & NDSR_MASK;
355 if (ndsr & event) {
356 nand_writel(info, NDSR, ndsr);
357 return 0;
358 }
359 udelay(10);
360 }
361
362 return -ETIMEDOUT;
363}
364
365static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
366 uint16_t cmd, int column, int page_addr)
367{
c8c17c88 368 const struct pxa3xx_nand_flash *f = info->flash_info;
7dad482e 369 const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
fe69af00 370
371 /* calculate data size */
372 switch (f->page_size) {
373 case 2048:
374 info->data_size = (info->use_ecc) ? 2088 : 2112;
375 break;
376 case 512:
377 info->data_size = (info->use_ecc) ? 520 : 528;
378 break;
379 default:
380 return -EINVAL;
381 }
382
383 /* generate values for NDCBx registers */
384 info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
385 info->ndcb1 = 0;
386 info->ndcb2 = 0;
c8c17c88 387 info->ndcb0 |= NDCB0_ADDR_CYC(info->row_addr_cycles + info->col_addr_cycles);
fe69af00 388
c8c17c88 389 if (info->col_addr_cycles == 2) {
fe69af00 390 /* large block, 2 cycles for column address
391 * row address starts from 3rd cycle
392 */
7f9938d0 393 info->ndcb1 |= page_addr << 16;
c8c17c88 394 if (info->row_addr_cycles == 3)
fe69af00 395 info->ndcb2 = (page_addr >> 16) & 0xff;
396 } else
397 /* small block, 1 cycles for column address
398 * row address starts from 2nd cycle
399 */
7f9938d0 400 info->ndcb1 = page_addr << 8;
fe69af00 401
402 if (cmd == cmdset->program)
403 info->ndcb0 |= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS;
404
405 return 0;
406}
407
408static int prepare_erase_cmd(struct pxa3xx_nand_info *info,
409 uint16_t cmd, int page_addr)
410{
411 info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
412 info->ndcb0 |= NDCB0_CMD_TYPE(2) | NDCB0_AUTO_RS | NDCB0_ADDR_CYC(3);
413 info->ndcb1 = page_addr;
414 info->ndcb2 = 0;
415 return 0;
416}
417
418static int prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
419{
7dad482e 420 const struct pxa3xx_nand_cmdset *cmdset = info->flash_info->cmdset;
fe69af00 421
422 info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
423 info->ndcb1 = 0;
424 info->ndcb2 = 0;
425
426 if (cmd == cmdset->read_id) {
427 info->ndcb0 |= NDCB0_CMD_TYPE(3);
428 info->data_size = 8;
429 } else if (cmd == cmdset->read_status) {
430 info->ndcb0 |= NDCB0_CMD_TYPE(4);
431 info->data_size = 8;
432 } else if (cmd == cmdset->reset || cmd == cmdset->lock ||
433 cmd == cmdset->unlock) {
434 info->ndcb0 |= NDCB0_CMD_TYPE(5);
435 } else
436 return -EINVAL;
437
438 return 0;
439}
440
441static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
442{
443 uint32_t ndcr;
444
445 ndcr = nand_readl(info, NDCR);
446 nand_writel(info, NDCR, ndcr & ~int_mask);
447}
448
449static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
450{
451 uint32_t ndcr;
452
453 ndcr = nand_readl(info, NDCR);
454 nand_writel(info, NDCR, ndcr | int_mask);
455}
456
457/* NOTE: it is a must to set ND_RUN firstly, then write command buffer
458 * otherwise, it does not work
459 */
460static int write_cmd(struct pxa3xx_nand_info *info)
461{
462 uint32_t ndcr;
463
464 /* clear status bits and run */
465 nand_writel(info, NDSR, NDSR_MASK);
466
467 ndcr = info->reg_ndcr;
468
469 ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
470 ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
471 ndcr |= NDCR_ND_RUN;
472
473 nand_writel(info, NDCR, ndcr);
474
475 if (wait_for_event(info, NDSR_WRCMDREQ)) {
476 printk(KERN_ERR "timed out writing command\n");
477 return -ETIMEDOUT;
478 }
479
480 nand_writel(info, NDCB0, info->ndcb0);
481 nand_writel(info, NDCB0, info->ndcb1);
482 nand_writel(info, NDCB0, info->ndcb2);
483 return 0;
484}
485
486static int handle_data_pio(struct pxa3xx_nand_info *info)
487{
488 int ret, timeout = CHIP_DELAY_TIMEOUT;
489
490 switch (info->state) {
491 case STATE_PIO_WRITING:
492 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
a88bdbb5 493 DIV_ROUND_UP(info->data_size, 4));
fe69af00 494
495 enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
496
497 ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
498 if (!ret) {
499 printk(KERN_ERR "program command time out\n");
500 return -1;
501 }
502 break;
503 case STATE_PIO_READING:
504 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
a88bdbb5 505 DIV_ROUND_UP(info->data_size, 4));
fe69af00 506 break;
507 default:
a1c06ee1 508 printk(KERN_ERR "%s: invalid state %d\n", __func__,
fe69af00 509 info->state);
510 return -EINVAL;
511 }
512
513 info->state = STATE_READY;
514 return 0;
515}
516
517static void start_data_dma(struct pxa3xx_nand_info *info, int dir_out)
518{
519 struct pxa_dma_desc *desc = info->data_desc;
520 int dma_len = ALIGN(info->data_size, 32);
521
522 desc->ddadr = DDADR_STOP;
523 desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
524
525 if (dir_out) {
526 desc->dsadr = info->data_buff_phys;
527 desc->dtadr = NDDB_DMA_ADDR;
528 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
529 } else {
530 desc->dtadr = info->data_buff_phys;
531 desc->dsadr = NDDB_DMA_ADDR;
532 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
533 }
534
535 DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
536 DDADR(info->data_dma_ch) = info->data_desc_addr;
537 DCSR(info->data_dma_ch) |= DCSR_RUN;
538}
539
540static void pxa3xx_nand_data_dma_irq(int channel, void *data)
541{
542 struct pxa3xx_nand_info *info = data;
543 uint32_t dcsr;
544
545 dcsr = DCSR(channel);
546 DCSR(channel) = dcsr;
547
548 if (dcsr & DCSR_BUSERR) {
549 info->retcode = ERR_DMABUSERR;
550 complete(&info->cmd_complete);
551 }
552
553 if (info->state == STATE_DMA_WRITING) {
554 info->state = STATE_DMA_DONE;
555 enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
556 } else {
557 info->state = STATE_READY;
558 complete(&info->cmd_complete);
559 }
560}
561
562static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
563{
564 struct pxa3xx_nand_info *info = devid;
565 unsigned int status;
566
567 status = nand_readl(info, NDSR);
568
223cf6c3 569 if (status & (NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR)) {
fe69af00 570 if (status & NDSR_DBERR)
571 info->retcode = ERR_DBERR;
223cf6c3
YP		 572 else if (status & NDSR_SBERR)
573 info->retcode = ERR_SBERR;
fe69af00 574
223cf6c3 575 disable_int(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
fe69af00 576
577 if (info->use_dma) {
578 info->state = STATE_DMA_READING;
579 start_data_dma(info, 0);
580 } else {
581 info->state = STATE_PIO_READING;
582 complete(&info->cmd_complete);
583 }
584 } else if (status & NDSR_WRDREQ) {
585 disable_int(info, NDSR_WRDREQ);
586 if (info->use_dma) {
587 info->state = STATE_DMA_WRITING;
588 start_data_dma(info, 1);
589 } else {
590 info->state = STATE_PIO_WRITING;
591 complete(&info->cmd_complete);
592 }
593 } else if (status & (NDSR_CS0_BBD | NDSR_CS0_CMDD)) {
594 if (status & NDSR_CS0_BBD)
595 info->retcode = ERR_BBERR;
596
597 disable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
598 info->state = STATE_READY;
599 complete(&info->cmd_complete);
600 }
601 nand_writel(info, NDSR, status);
602 return IRQ_HANDLED;
603}
604
605static int pxa3xx_nand_do_cmd(struct pxa3xx_nand_info *info, uint32_t event)
606{
607 uint32_t ndcr;
608 int ret, timeout = CHIP_DELAY_TIMEOUT;
609
610 if (write_cmd(info)) {
611 info->retcode = ERR_SENDCMD;
612 goto fail_stop;
613 }
614
615 info->state = STATE_CMD_HANDLE;
616
617 enable_int(info, event);
618
619 ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
620 if (!ret) {
621 printk(KERN_ERR "command execution timed out\n");
622 info->retcode = ERR_SENDCMD;
623 goto fail_stop;
624 }
625
626 if (info->use_dma == 0 && info->data_size > 0)
627 if (handle_data_pio(info))
628 goto fail_stop;
629
630 return 0;
631
632fail_stop:
633 ndcr = nand_readl(info, NDCR);
634 nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
635 udelay(10);
636 return -ETIMEDOUT;
637}
638
639static int pxa3xx_nand_dev_ready(struct mtd_info *mtd)
640{
641 struct pxa3xx_nand_info *info = mtd->priv;
642 return (nand_readl(info, NDSR) & NDSR_RDY) ? 1 : 0;
643}
644
645static inline int is_buf_blank(uint8_t *buf, size_t len)
646{
647 for (; len > 0; len--)
648 if (*buf++ != 0xff)
649 return 0;
650 return 1;
651}
652
653static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
a1c06ee1 654 int column, int page_addr)
fe69af00 655{
656 struct pxa3xx_nand_info *info = mtd->priv;
c8c17c88 657 const struct pxa3xx_nand_flash *flash_info = info->flash_info;
7dad482e 658 const struct pxa3xx_nand_cmdset *cmdset = flash_info->cmdset;
fe69af00 659 int ret;
660
661 info->use_dma = (use_dma) ? 1 : 0;
662 info->use_ecc = 0;
663 info->data_size = 0;
664 info->state = STATE_READY;
665
666 init_completion(&info->cmd_complete);
667
668 switch (command) {
669 case NAND_CMD_READOOB:
670 /* disable HW ECC to get all the OOB data */
671 info->buf_count = mtd->writesize + mtd->oobsize;
672 info->buf_start = mtd->writesize + column;
673
674 if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr))
675 break;
676
223cf6c3 677 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
fe69af00 678
679 /* We only are OOB, so if the data has error, does not matter */
680 if (info->retcode == ERR_DBERR)
681 info->retcode = ERR_NONE;
682 break;
683
684 case NAND_CMD_READ0:
685 info->use_ecc = 1;
686 info->retcode = ERR_NONE;
687 info->buf_start = column;
688 info->buf_count = mtd->writesize + mtd->oobsize;
689 memset(info->data_buff, 0xFF, info->buf_count);
690
691 if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr))
692 break;
693
223cf6c3 694 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
fe69af00 695
696 if (info->retcode == ERR_DBERR) {
697 /* for blank page (all 0xff), HW will calculate its ECC as
698 * 0, which is different from the ECC information within
699 * OOB, ignore such double bit errors
700 */
701 if (is_buf_blank(info->data_buff, mtd->writesize))
702 info->retcode = ERR_NONE;
703 }
704 break;
705 case NAND_CMD_SEQIN:
706 info->buf_start = column;
707 info->buf_count = mtd->writesize + mtd->oobsize;
708 memset(info->data_buff, 0xff, info->buf_count);
709
710 /* save column/page_addr for next CMD_PAGEPROG */
711 info->seqin_column = column;
712 info->seqin_page_addr = page_addr;
713 break;
714 case NAND_CMD_PAGEPROG:
715 info->use_ecc = (info->seqin_column >= mtd->writesize) ? 0 : 1;
716
717 if (prepare_read_prog_cmd(info, cmdset->program,
718 info->seqin_column, info->seqin_page_addr))
719 break;
720
721 pxa3xx_nand_do_cmd(info, NDSR_WRDREQ);
722 break;
723 case NAND_CMD_ERASE1:
724 if (prepare_erase_cmd(info, cmdset->erase, page_addr))
725 break;
726
727 pxa3xx_nand_do_cmd(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
728 break;
729 case NAND_CMD_ERASE2:
730 break;
731 case NAND_CMD_READID:
732 case NAND_CMD_STATUS:
733 info->use_dma = 0; /* force PIO read */
734 info->buf_start = 0;
735 info->buf_count = (command == NAND_CMD_READID) ?
c8c17c88 736 info->read_id_bytes : 1;
fe69af00 737
738 if (prepare_other_cmd(info, (command == NAND_CMD_READID) ?
739 cmdset->read_id : cmdset->read_status))
740 break;
741
742 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ);
743 break;
744 case NAND_CMD_RESET:
745 if (prepare_other_cmd(info, cmdset->reset))
746 break;
747
748 ret = pxa3xx_nand_do_cmd(info, NDSR_CS0_CMDD);
749 if (ret == 0) {
750 int timeout = 2;
751 uint32_t ndcr;
752
753 while (timeout--) {
754 if (nand_readl(info, NDSR) & NDSR_RDY)
755 break;
756 msleep(10);
757 }
758
759 ndcr = nand_readl(info, NDCR);
760 nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
761 }
762 break;
763 default:
764 printk(KERN_ERR "non-supported command.\n");
765 break;
766 }
767
768 if (info->retcode == ERR_DBERR) {
769 printk(KERN_ERR "double bit error @ page %08x\n", page_addr);
770 info->retcode = ERR_NONE;
771 }
772}
773
774static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
775{
776 struct pxa3xx_nand_info *info = mtd->priv;
777 char retval = 0xFF;
778
779 if (info->buf_start < info->buf_count)
780 /* Has just send a new command? */
781 retval = info->data_buff[info->buf_start++];
782
783 return retval;
784}
785
786static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
787{
788 struct pxa3xx_nand_info *info = mtd->priv;
789 u16 retval = 0xFFFF;
790
791 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
792 retval = *((u16 *)(info->data_buff+info->buf_start));
793 info->buf_start += 2;
794 }
795 return retval;
796}
797
798static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
799{
800 struct pxa3xx_nand_info *info = mtd->priv;
801 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
802
803 memcpy(buf, info->data_buff + info->buf_start, real_len);
804 info->buf_start += real_len;
805}
806
807static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
808 const uint8_t *buf, int len)
809{
810 struct pxa3xx_nand_info *info = mtd->priv;
811 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
812
813 memcpy(info->data_buff + info->buf_start, buf, real_len);
814 info->buf_start += real_len;
815}
816
817static int pxa3xx_nand_verify_buf(struct mtd_info *mtd,
818 const uint8_t *buf, int len)
819{
820 return 0;
821}
822
823static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
824{
825 return;
826}
827
828static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
829{
830 struct pxa3xx_nand_info *info = mtd->priv;
831
832 /* pxa3xx_nand_send_command has waited for command complete */
833 if (this->state == FL_WRITING || this->state == FL_ERASING) {
834 if (info->retcode == ERR_NONE)
835 return 0;
836 else {
837 /*
838 * any error make it return 0x01 which will tell
839 * the caller the erase and write fail
840 */
841 return 0x01;
842 }
843 }
844
845 return 0;
846}
847
848static void pxa3xx_nand_ecc_hwctl(struct mtd_info *mtd, int mode)
849{
850 return;
851}
852
853static int pxa3xx_nand_ecc_calculate(struct mtd_info *mtd,
854 const uint8_t *dat, uint8_t *ecc_code)
855{
856 return 0;
857}
858
859static int pxa3xx_nand_ecc_correct(struct mtd_info *mtd,
860 uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc)
861{
862 struct pxa3xx_nand_info *info = mtd->priv;
863 /*
864 * Any error include ERR_SEND_CMD, ERR_DBERR, ERR_BUSERR, we
865 * consider it as a ecc error which will tell the caller the
866 * read fail We have distinguish all the errors, but the
867 * nand_read_ecc only check this function return value
223cf6c3
YP		 868 *
869 * Corrected (single-bit) errors must also be noted.
fe69af00 870 */
223cf6c3
YP		 871 if (info->retcode == ERR_SBERR)
872 return 1;
873 else if (info->retcode != ERR_NONE)
fe69af00 874 return -1;
875
876 return 0;
877}
878
879static int __readid(struct pxa3xx_nand_info *info, uint32_t *id)
880{
c8c17c88 881 const struct pxa3xx_nand_flash *f = info->flash_info;
7dad482e 882 const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
fe69af00 883 uint32_t ndcr;
884 uint8_t id_buff[8];
885
886 if (prepare_other_cmd(info, cmdset->read_id)) {
887 printk(KERN_ERR "failed to prepare command\n");
888 return -EINVAL;
889 }
890
891 /* Send command */
892 if (write_cmd(info))
893 goto fail_timeout;
894
895 /* Wait for CMDDM(command done successfully) */
896 if (wait_for_event(info, NDSR_RDDREQ))
897 goto fail_timeout;
898
899 __raw_readsl(info->mmio_base + NDDB, id_buff, 2);
900 *id = id_buff[0] | (id_buff[1] << 8);
901 return 0;
902
903fail_timeout:
904 ndcr = nand_readl(info, NDCR);
905 nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
906 udelay(10);
907 return -ETIMEDOUT;
908}
909
910static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
c8c17c88 911 const struct pxa3xx_nand_flash *f)
fe69af00 912{
913 struct platform_device *pdev = info->pdev;
914 struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
915 uint32_t ndcr = 0x00000FFF; /* disable all interrupts */
916
917 if (f->page_size != 2048 && f->page_size != 512)
918 return -EINVAL;
919
920 if (f->flash_width != 16 && f->flash_width != 8)
921 return -EINVAL;
922
923 /* calculate flash information */
c8c17c88
ES		 924 info->oob_size = (f->page_size == 2048) ? 64 : 16;
925 info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
fe69af00 926
927 /* calculate addressing information */
c8c17c88 928 info->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
fe69af00 929
930 if (f->num_blocks * f->page_per_block > 65536)
c8c17c88 931 info->row_addr_cycles = 3;
fe69af00 932 else
c8c17c88 933 info->row_addr_cycles = 2;
fe69af00 934
935 ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
c8c17c88 936 ndcr |= (info->col_addr_cycles == 2) ? NDCR_RA_START : 0;
fe69af00 937 ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
938 ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
939 ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
940 ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
941
c8c17c88 942 ndcr |= NDCR_RD_ID_CNT(info->read_id_bytes);
fe69af00 943 ndcr |= NDCR_SPARE_EN; /* enable spare by default */
944
945 info->reg_ndcr = ndcr;
946
947 pxa3xx_nand_set_timing(info, f->timing);
948 info->flash_info = f;
949 return 0;
950}
951
f271049e
MR		 952static void pxa3xx_nand_detect_timing(struct pxa3xx_nand_info *info,
953 struct pxa3xx_nand_timing *t)
954{
955 unsigned long nand_clk = clk_get_rate(info->clk);
956 uint32_t ndtr0 = nand_readl(info, NDTR0CS0);
957 uint32_t ndtr1 = nand_readl(info, NDTR1CS0);
958
959 t->tCH = cycle2ns(tCH_NDTR0(ndtr0), nand_clk);
960 t->tCS = cycle2ns(tCS_NDTR0(ndtr0), nand_clk);
961 t->tWH = cycle2ns(tWH_NDTR0(ndtr0), nand_clk);
962 t->tWP = cycle2ns(tWP_NDTR0(ndtr0), nand_clk);
963 t->tRH = cycle2ns(tRH_NDTR0(ndtr0), nand_clk);
964 t->tRP = cycle2ns(tRP_NDTR0(ndtr0), nand_clk);
965
966 t->tR = cycle2ns(tR_NDTR1(ndtr1), nand_clk);
967 t->tWHR = cycle2ns(tWHR_NDTR1(ndtr1), nand_clk);
968 t->tAR = cycle2ns(tAR_NDTR1(ndtr1), nand_clk);
969}
970
971static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
972{
973 uint32_t ndcr = nand_readl(info, NDCR);
974 struct nand_flash_dev *type = NULL;
975 uint32_t id = -1;
976 int i;
977
978 default_flash.page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32;
979 default_flash.page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
980 default_flash.flash_width = ndcr & NDCR_DWIDTH_M ? 16 : 8;
981 default_flash.dfc_width = ndcr & NDCR_DWIDTH_C ? 16 : 8;
982
983 if (default_flash.page_size == 2048)
984 default_flash.cmdset = &largepage_cmdset;
985 else
986 default_flash.cmdset = &smallpage_cmdset;
987
988 /* set info fields needed to __readid */
989 info->flash_info = &default_flash;
990 info->read_id_bytes = (default_flash.page_size == 2048) ? 4 : 2;
991 info->reg_ndcr = ndcr;
992
993 if (__readid(info, &id))
994 return -ENODEV;
995
996 /* Lookup the flash id */
997 id = (id >> 8) & 0xff; /* device id is byte 2 */
998 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
999 if (id == nand_flash_ids[i].id) {
1000 type = &nand_flash_ids[i];
1001 break;
1002 }
1003 }
1004
1005 if (!type)
1006 return -ENODEV;
1007
1008 /* fill the missing flash information */
1009 i = __ffs(default_flash.page_per_block * default_flash.page_size);
1010 default_flash.num_blocks = type->chipsize << (20 - i);
1011
1012 info->oob_size = (default_flash.page_size == 2048) ? 64 : 16;
1013
1014 /* calculate addressing information */
1015 info->col_addr_cycles = (default_flash.page_size == 2048) ? 2 : 1;
1016
1017 if (default_flash.num_blocks * default_flash.page_per_block > 65536)
1018 info->row_addr_cycles = 3;
1019 else
1020 info->row_addr_cycles = 2;
1021
1022 pxa3xx_nand_detect_timing(info, &default_timing);
1023 default_flash.timing = &default_timing;
1024
1025 return 0;
1026}
1027
c8ac3f81
ES		 1028static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info,
1029 const struct pxa3xx_nand_platform_data *pdata)
fe69af00 1030{
c8c17c88 1031 const struct pxa3xx_nand_flash *f;
2675e944 1032 uint32_t id = -1;
fe69af00 1033 int i;
1034
f271049e
MR		 1035 if (pdata->keep_config)
1036 if (pxa3xx_nand_detect_config(info) == 0)
1037 return 0;
1038
c8ac3f81
ES		 1039 for (i = 0; i<pdata->num_flash; ++i) {
1040 f = pdata->flash + i;
1041
1042 if (pxa3xx_nand_config_flash(info, f))
1043 continue;
1044
1045 if (__readid(info, &id))
1046 continue;
1047
1048 if (id == f->chip_id)
1049 return 0;
1050 }
1051
80ebf20f 1052#ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
fe69af00 1053 for (i = 0; i < ARRAY_SIZE(builtin_flash_types); i++) {
1054
1055 f = builtin_flash_types[i];
1056
1057 if (pxa3xx_nand_config_flash(info, f))
1058 continue;
1059
1060 if (__readid(info, &id))
1061 continue;
1062
1063 if (id == f->chip_id)
1064 return 0;
1065 }
80ebf20f 1066#endif
fe69af00 1067
2675e944
ES		 1068 dev_warn(&info->pdev->dev,
1069 "failed to detect configured nand flash; found %04x instead of\n",
1070 id);
fe69af00 1071 return -ENODEV;
1072}
1073
1074/* the maximum possible buffer size for large page with OOB data
1075 * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
1076 * data buffer and the DMA descriptor
1077 */
1078#define MAX_BUFF_SIZE PAGE_SIZE
1079
1080static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
1081{
1082 struct platform_device *pdev = info->pdev;
1083 int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
1084
1085 if (use_dma == 0) {
1086 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
1087 if (info->data_buff == NULL)
1088 return -ENOMEM;
1089 return 0;
1090 }
1091
1092 info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
1093 &info->data_buff_phys, GFP_KERNEL);
1094 if (info->data_buff == NULL) {
1095 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
1096 return -ENOMEM;
1097 }
1098
1099 info->data_buff_size = MAX_BUFF_SIZE;
1100 info->data_desc = (void *)info->data_buff + data_desc_offset;
1101 info->data_desc_addr = info->data_buff_phys + data_desc_offset;
1102
1103 info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
1104 pxa3xx_nand_data_dma_irq, info);
1105 if (info->data_dma_ch < 0) {
1106 dev_err(&pdev->dev, "failed to request data dma\n");
1107 dma_free_coherent(&pdev->dev, info->data_buff_size,
1108 info->data_buff, info->data_buff_phys);
1109 return info->data_dma_ch;
1110 }
1111
1112 return 0;
1113}
1114
1115static struct nand_ecclayout hw_smallpage_ecclayout = {
1116 .eccbytes = 6,
1117 .eccpos = {8, 9, 10, 11, 12, 13 },
1118 .oobfree = { {2, 6} }
1119};
1120
1121static struct nand_ecclayout hw_largepage_ecclayout = {
1122 .eccbytes = 24,
1123 .eccpos = {
1124 40, 41, 42, 43, 44, 45, 46, 47,
1125 48, 49, 50, 51, 52, 53, 54, 55,
1126 56, 57, 58, 59, 60, 61, 62, 63},
1127 .oobfree = { {2, 38} }
1128};
1129
1130static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
1131 struct pxa3xx_nand_info *info)
1132{
c8c17c88 1133 const struct pxa3xx_nand_flash *f = info->flash_info;
fe69af00 1134 struct nand_chip *this = &info->nand_chip;
1135
1136 this->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0;
1137
1138 this->waitfunc = pxa3xx_nand_waitfunc;
1139 this->select_chip = pxa3xx_nand_select_chip;
1140 this->dev_ready = pxa3xx_nand_dev_ready;
1141 this->cmdfunc = pxa3xx_nand_cmdfunc;
1142 this->read_word = pxa3xx_nand_read_word;
1143 this->read_byte = pxa3xx_nand_read_byte;
1144 this->read_buf = pxa3xx_nand_read_buf;
1145 this->write_buf = pxa3xx_nand_write_buf;
1146 this->verify_buf = pxa3xx_nand_verify_buf;
1147
1148 this->ecc.mode = NAND_ECC_HW;
1149 this->ecc.hwctl = pxa3xx_nand_ecc_hwctl;
1150 this->ecc.calculate = pxa3xx_nand_ecc_calculate;
1151 this->ecc.correct = pxa3xx_nand_ecc_correct;
1152 this->ecc.size = f->page_size;
1153
1154 if (f->page_size == 2048)
1155 this->ecc.layout = &hw_largepage_ecclayout;
1156 else
1157 this->ecc.layout = &hw_smallpage_ecclayout;
1158
a1c06ee1 1159 this->chip_delay = 25;
fe69af00 1160}
1161
1162static int pxa3xx_nand_probe(struct platform_device *pdev)
1163{
1164 struct pxa3xx_nand_platform_data *pdata;
1165 struct pxa3xx_nand_info *info;
1166 struct nand_chip *this;
1167 struct mtd_info *mtd;
1168 struct resource *r;
1169 int ret = 0, irq;
1170
1171 pdata = pdev->dev.platform_data;
1172
a1c06ee1 1173 if (!pdata) {
fe69af00 1174 dev_err(&pdev->dev, "no platform data defined\n");
1175 return -ENODEV;
1176 }
1177
1178 mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct pxa3xx_nand_info),
1179 GFP_KERNEL);
a1c06ee1 1180 if (!mtd) {
fe69af00 1181 dev_err(&pdev->dev, "failed to allocate memory\n");
1182 return -ENOMEM;
a1c06ee1 1183 }
fe69af00 1184
1185 info = (struct pxa3xx_nand_info *)(&mtd[1]);
1186 info->pdev = pdev;
1187
1188 this = &info->nand_chip;
1189 mtd->priv = info;
82a72d10 1190 mtd->owner = THIS_MODULE;
fe69af00 1191
e0d8b13a 1192 info->clk = clk_get(&pdev->dev, NULL);
fe69af00 1193 if (IS_ERR(info->clk)) {
1194 dev_err(&pdev->dev, "failed to get nand clock\n");
1195 ret = PTR_ERR(info->clk);
1196 goto fail_free_mtd;
1197 }
1198 clk_enable(info->clk);
1199
1200 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1201 if (r == NULL) {
1202 dev_err(&pdev->dev, "no resource defined for data DMA\n");
1203 ret = -ENXIO;
1204 goto fail_put_clk;
1205 }
1206 info->drcmr_dat = r->start;
1207
1208 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1209 if (r == NULL) {
1210 dev_err(&pdev->dev, "no resource defined for command DMA\n");
1211 ret = -ENXIO;
1212 goto fail_put_clk;
1213 }
1214 info->drcmr_cmd = r->start;
1215
1216 irq = platform_get_irq(pdev, 0);
1217 if (irq < 0) {
1218 dev_err(&pdev->dev, "no IRQ resource defined\n");
1219 ret = -ENXIO;
1220 goto fail_put_clk;
1221 }
1222
1223 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1224 if (r == NULL) {
1225 dev_err(&pdev->dev, "no IO memory resource defined\n");
1226 ret = -ENODEV;
1227 goto fail_put_clk;
1228 }
1229
b2ed3680 1230 r = request_mem_region(r->start, resource_size(r), pdev->name);
fe69af00 1231 if (r == NULL) {
1232 dev_err(&pdev->dev, "failed to request memory resource\n");
1233 ret = -EBUSY;
1234 goto fail_put_clk;
1235 }
1236
b2ed3680 1237 info->mmio_base = ioremap(r->start, resource_size(r));
fe69af00 1238 if (info->mmio_base == NULL) {
1239 dev_err(&pdev->dev, "ioremap() failed\n");
1240 ret = -ENODEV;
1241 goto fail_free_res;
1242 }
1243
1244 ret = pxa3xx_nand_init_buff(info);
1245 if (ret)
1246 goto fail_free_io;
1247
1248 ret = request_irq(IRQ_NAND, pxa3xx_nand_irq, IRQF_DISABLED,
1249 pdev->name, info);
1250 if (ret < 0) {
1251 dev_err(&pdev->dev, "failed to request IRQ\n");
1252 goto fail_free_buf;
1253 }
1254
c8ac3f81 1255 ret = pxa3xx_nand_detect_flash(info, pdata);
fe69af00 1256 if (ret) {
1257 dev_err(&pdev->dev, "failed to detect flash\n");
1258 ret = -ENODEV;
1259 goto fail_free_irq;
1260 }
1261
1262 pxa3xx_nand_init_mtd(mtd, info);
1263
1264 platform_set_drvdata(pdev, mtd);
1265
1266 if (nand_scan(mtd, 1)) {
1267 dev_err(&pdev->dev, "failed to scan nand\n");
1268 ret = -ENXIO;
1269 goto fail_free_irq;
1270 }
1271
1272 return add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts);
1273
1274fail_free_irq:
1275 free_irq(IRQ_NAND, info);
1276fail_free_buf:
1277 if (use_dma) {
1278 pxa_free_dma(info->data_dma_ch);
1279 dma_free_coherent(&pdev->dev, info->data_buff_size,
1280 info->data_buff, info->data_buff_phys);
1281 } else
1282 kfree(info->data_buff);
1283fail_free_io:
1284 iounmap(info->mmio_base);
1285fail_free_res:
b2ed3680 1286 release_mem_region(r->start, resource_size(r));
fe69af00 1287fail_put_clk:
1288 clk_disable(info->clk);
1289 clk_put(info->clk);
1290fail_free_mtd:
1291 kfree(mtd);
1292 return ret;
1293}
1294
1295static int pxa3xx_nand_remove(struct platform_device *pdev)
1296{
1297 struct mtd_info *mtd = platform_get_drvdata(pdev);
1298 struct pxa3xx_nand_info *info = mtd->priv;
82a72d10 1299 struct resource *r;
fe69af00 1300
1301 platform_set_drvdata(pdev, NULL);
1302
1303 del_mtd_device(mtd);
1304 del_mtd_partitions(mtd);
1305 free_irq(IRQ_NAND, info);
1306 if (use_dma) {
1307 pxa_free_dma(info->data_dma_ch);
1308 dma_free_writecombine(&pdev->dev, info->data_buff_size,
1309 info->data_buff, info->data_buff_phys);
1310 } else
1311 kfree(info->data_buff);
82a72d10
MR		 1312
1313 iounmap(info->mmio_base);
1314 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1315 release_mem_region(r->start, resource_size(r));
1316
1317 clk_disable(info->clk);
1318 clk_put(info->clk);
1319
fe69af00 1320 kfree(mtd);
1321 return 0;
1322}
1323
1324#ifdef CONFIG_PM
1325static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1326{
1327 struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
1328 struct pxa3xx_nand_info *info = mtd->priv;
1329
1330 if (info->state != STATE_READY) {
1331 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1332 return -EAGAIN;
1333 }
1334
1335 return 0;
1336}
1337
1338static int pxa3xx_nand_resume(struct platform_device *pdev)
1339{
1340 struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
1341 struct pxa3xx_nand_info *info = mtd->priv;
1342
1343 clk_enable(info->clk);
1344
9b62d864 1345 return pxa3xx_nand_config_flash(info, info->flash_info);
fe69af00 1346}
1347#else
1348#define pxa3xx_nand_suspend NULL
1349#define pxa3xx_nand_resume NULL
1350#endif
1351
1352static struct platform_driver pxa3xx_nand_driver = {
1353 .driver = {
1354 .name = "pxa3xx-nand",
1355 },
1356 .probe = pxa3xx_nand_probe,
1357 .remove = pxa3xx_nand_remove,
1358 .suspend = pxa3xx_nand_suspend,
1359 .resume = pxa3xx_nand_resume,
1360};
1361
1362static int __init pxa3xx_nand_init(void)
1363{
1364 return platform_driver_register(&pxa3xx_nand_driver);
1365}
1366module_init(pxa3xx_nand_init);
1367
1368static void __exit pxa3xx_nand_exit(void)
1369{
1370 platform_driver_unregister(&pxa3xx_nand_driver);
1371}
1372module_exit(pxa3xx_nand_exit);
1373
1374MODULE_LICENSE("GPL");
1375MODULE_DESCRIPTION("PXA3xx NAND controller driver");
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