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pxa3xx_nand: remove hardcode irq number
[mirror_ubuntu-jammy-kernel.git] / drivers / mtd / nand / pxa3xx_nand.c
CommitLineData
fe69af00 1/*
2 * drivers/mtd/nand/pxa3xx_nand.c
3 *
4 * Copyright © 2005 Intel Corporation
5 * Copyright © 2006 Marvell International Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
a88bdbb5 12#include <linux/kernel.h>
fe69af00 13#include <linux/module.h>
14#include <linux/interrupt.h>
15#include <linux/platform_device.h>
16#include <linux/dma-mapping.h>
17#include <linux/delay.h>
18#include <linux/clk.h>
19#include <linux/mtd/mtd.h>
20#include <linux/mtd/nand.h>
21#include <linux/mtd/partitions.h>
a1c06ee1
DW		 22#include <linux/io.h>
23#include <linux/irq.h>
fe69af00 24
afb5b5c9 25#include <mach/dma.h>
a09e64fb 26#include <mach/pxa3xx_nand.h>
fe69af00 27
28#define CHIP_DELAY_TIMEOUT (2 * HZ/10)
29
30/* registers and bit definitions */
31#define NDCR (0x00) /* Control register */
32#define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
33#define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
34#define NDSR (0x14) /* Status Register */
35#define NDPCR (0x18) /* Page Count Register */
36#define NDBDR0 (0x1C) /* Bad Block Register 0 */
37#define NDBDR1 (0x20) /* Bad Block Register 1 */
38#define NDDB (0x40) /* Data Buffer */
39#define NDCB0 (0x48) /* Command Buffer0 */
40#define NDCB1 (0x4C) /* Command Buffer1 */
41#define NDCB2 (0x50) /* Command Buffer2 */
42
43#define NDCR_SPARE_EN (0x1 << 31)
44#define NDCR_ECC_EN (0x1 << 30)
45#define NDCR_DMA_EN (0x1 << 29)
46#define NDCR_ND_RUN (0x1 << 28)
47#define NDCR_DWIDTH_C (0x1 << 27)
48#define NDCR_DWIDTH_M (0x1 << 26)
49#define NDCR_PAGE_SZ (0x1 << 24)
50#define NDCR_NCSX (0x1 << 23)
51#define NDCR_ND_MODE (0x3 << 21)
52#define NDCR_NAND_MODE (0x0)
53#define NDCR_CLR_PG_CNT (0x1 << 20)
54#define NDCR_CLR_ECC (0x1 << 19)
55#define NDCR_RD_ID_CNT_MASK (0x7 << 16)
56#define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
57
58#define NDCR_RA_START (0x1 << 15)
59#define NDCR_PG_PER_BLK (0x1 << 14)
60#define NDCR_ND_ARB_EN (0x1 << 12)
61
62#define NDSR_MASK (0xfff)
63#define NDSR_RDY (0x1 << 11)
64#define NDSR_CS0_PAGED (0x1 << 10)
65#define NDSR_CS1_PAGED (0x1 << 9)
66#define NDSR_CS0_CMDD (0x1 << 8)
67#define NDSR_CS1_CMDD (0x1 << 7)
68#define NDSR_CS0_BBD (0x1 << 6)
69#define NDSR_CS1_BBD (0x1 << 5)
70#define NDSR_DBERR (0x1 << 4)
71#define NDSR_SBERR (0x1 << 3)
72#define NDSR_WRDREQ (0x1 << 2)
73#define NDSR_RDDREQ (0x1 << 1)
74#define NDSR_WRCMDREQ (0x1)
75
76#define NDCB0_AUTO_RS (0x1 << 25)
77#define NDCB0_CSEL (0x1 << 24)
78#define NDCB0_CMD_TYPE_MASK (0x7 << 21)
79#define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
80#define NDCB0_NC (0x1 << 20)
81#define NDCB0_DBC (0x1 << 19)
82#define NDCB0_ADDR_CYC_MASK (0x7 << 16)
83#define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
84#define NDCB0_CMD2_MASK (0xff << 8)
85#define NDCB0_CMD1_MASK (0xff)
86#define NDCB0_ADDR_CYC_SHIFT (16)
87
fe69af00 88/* macros for registers read/write */
89#define nand_writel(info, off, val) \
90 __raw_writel((val), (info)->mmio_base + (off))
91
92#define nand_readl(info, off) \
93 __raw_readl((info)->mmio_base + (off))
94
95/* error code and state */
96enum {
97 ERR_NONE = 0,
98 ERR_DMABUSERR = -1,
99 ERR_SENDCMD = -2,
100 ERR_DBERR = -3,
101 ERR_BBERR = -4,
223cf6c3 102 ERR_SBERR = -5,
fe69af00 103};
104
105enum {
106 STATE_READY = 0,
107 STATE_CMD_HANDLE,
108 STATE_DMA_READING,
109 STATE_DMA_WRITING,
110 STATE_DMA_DONE,
111 STATE_PIO_READING,
112 STATE_PIO_WRITING,
113};
114
fe69af00 115struct pxa3xx_nand_info {
116 struct nand_chip nand_chip;
117
118 struct platform_device *pdev;
c8c17c88 119 const struct pxa3xx_nand_flash *flash_info;
fe69af00 120
121 struct clk *clk;
122 void __iomem *mmio_base;
8638fac8 123 unsigned long mmio_phys;
fe69af00 124
125 unsigned int buf_start;
126 unsigned int buf_count;
127
128 /* DMA information */
129 int drcmr_dat;
130 int drcmr_cmd;
131
132 unsigned char *data_buff;
133 dma_addr_t data_buff_phys;
134 size_t data_buff_size;
135 int data_dma_ch;
136 struct pxa_dma_desc *data_desc;
137 dma_addr_t data_desc_addr;
138
139 uint32_t reg_ndcr;
140
141 /* saved column/page_addr during CMD_SEQIN */
142 int seqin_column;
143 int seqin_page_addr;
144
145 /* relate to the command */
146 unsigned int state;
147
148 int use_ecc; /* use HW ECC ? */
149 int use_dma; /* use DMA ? */
150
151 size_t data_size; /* data size in FIFO */
152 int retcode;
153 struct completion cmd_complete;
154
155 /* generated NDCBx register values */
156 uint32_t ndcb0;
157 uint32_t ndcb1;
158 uint32_t ndcb2;
c8c17c88
ES		 159
160 /* calculated from pxa3xx_nand_flash data */
161 size_t oob_size;
162 size_t read_id_bytes;
163
164 unsigned int col_addr_cycles;
165 unsigned int row_addr_cycles;
fe69af00 166};
167
168static int use_dma = 1;
169module_param(use_dma, bool, 0444);
170MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW");
171
f271049e
MR		 172/*
173 * Default NAND flash controller configuration setup by the
174 * bootloader. This configuration is used only when pdata->keep_config is set
175 */
176static struct pxa3xx_nand_timing default_timing;
177static struct pxa3xx_nand_flash default_flash;
178
fe69af00 179static struct pxa3xx_nand_cmdset smallpage_cmdset = {
180 .read1 = 0x0000,
181 .read2 = 0x0050,
182 .program = 0x1080,
183 .read_status = 0x0070,
184 .read_id = 0x0090,
185 .erase = 0xD060,
186 .reset = 0x00FF,
187 .lock = 0x002A,
188 .unlock = 0x2423,
189 .lock_status = 0x007A,
190};
191
192static struct pxa3xx_nand_cmdset largepage_cmdset = {
193 .read1 = 0x3000,
194 .read2 = 0x0050,
195 .program = 0x1080,
196 .read_status = 0x0070,
197 .read_id = 0x0090,
198 .erase = 0xD060,
199 .reset = 0x00FF,
200 .lock = 0x002A,
201 .unlock = 0x2423,
202 .lock_status = 0x007A,
203};
204
f271049e 205#ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
fe69af00 206static struct pxa3xx_nand_timing samsung512MbX16_timing = {
207 .tCH = 10,
208 .tCS = 0,
209 .tWH = 20,
210 .tWP = 40,
211 .tRH = 30,
212 .tRP = 40,
213 .tR = 11123,
214 .tWHR = 110,
215 .tAR = 10,
216};
217
218static struct pxa3xx_nand_flash samsung512MbX16 = {
219 .timing = &samsung512MbX16_timing,
220 .cmdset = &smallpage_cmdset,
221 .page_per_block = 32,
222 .page_size = 512,
223 .flash_width = 16,
224 .dfc_width = 16,
225 .num_blocks = 4096,
226 .chip_id = 0x46ec,
227};
228
229static struct pxa3xx_nand_timing micron_timing = {
230 .tCH = 10,
231 .tCS = 25,
232 .tWH = 15,
233 .tWP = 25,
234 .tRH = 15,
726de6e1 235 .tRP = 30,
fe69af00 236 .tR = 25000,
237 .tWHR = 60,
238 .tAR = 10,
239};
240
241static struct pxa3xx_nand_flash micron1GbX8 = {
242 .timing = &micron_timing,
243 .cmdset = &largepage_cmdset,
244 .page_per_block = 64,
245 .page_size = 2048,
246 .flash_width = 8,
247 .dfc_width = 8,
248 .num_blocks = 1024,
249 .chip_id = 0xa12c,
250};
251
252static struct pxa3xx_nand_flash micron1GbX16 = {
253 .timing = &micron_timing,
254 .cmdset = &largepage_cmdset,
255 .page_per_block = 64,
256 .page_size = 2048,
257 .flash_width = 16,
258 .dfc_width = 16,
259 .num_blocks = 1024,
260 .chip_id = 0xb12c,
261};
262
4262bd29
SL		 263static struct pxa3xx_nand_timing stm2GbX16_timing = {
264 .tCH = 10,
265 .tCS = 35,
266 .tWH = 15,
267 .tWP = 25,
268 .tRH = 15,
269 .tRP = 25,
270 .tR = 25000,
271 .tWHR = 60,
272 .tAR = 10,
273};
274
275static struct pxa3xx_nand_flash stm2GbX16 = {
276 .timing = &stm2GbX16_timing,
e93f1be5 277 .cmdset = &largepage_cmdset,
4262bd29
SL		 278 .page_per_block = 64,
279 .page_size = 2048,
280 .flash_width = 16,
281 .dfc_width = 16,
282 .num_blocks = 2048,
283 .chip_id = 0xba20,
284};
285
fe69af00 286static struct pxa3xx_nand_flash *builtin_flash_types[] = {
287 &samsung512MbX16,
288 &micron1GbX8,
289 &micron1GbX16,
4262bd29 290 &stm2GbX16,
fe69af00 291};
80ebf20f 292#endif /* CONFIG_MTD_NAND_PXA3xx_BUILTIN */
fe69af00 293
294#define NDTR0_tCH(c) (min((c), 7) << 19)
295#define NDTR0_tCS(c) (min((c), 7) << 16)
296#define NDTR0_tWH(c) (min((c), 7) << 11)
297#define NDTR0_tWP(c) (min((c), 7) << 8)
298#define NDTR0_tRH(c) (min((c), 7) << 3)
299#define NDTR0_tRP(c) (min((c), 7) << 0)
300
301#define NDTR1_tR(c) (min((c), 65535) << 16)
302#define NDTR1_tWHR(c) (min((c), 15) << 4)
303#define NDTR1_tAR(c) (min((c), 15) << 0)
304
f271049e
MR		 305#define tCH_NDTR0(r) (((r) >> 19) & 0x7)
306#define tCS_NDTR0(r) (((r) >> 16) & 0x7)
307#define tWH_NDTR0(r) (((r) >> 11) & 0x7)
308#define tWP_NDTR0(r) (((r) >> 8) & 0x7)
309#define tRH_NDTR0(r) (((r) >> 3) & 0x7)
310#define tRP_NDTR0(r) (((r) >> 0) & 0x7)
311
312#define tR_NDTR1(r) (((r) >> 16) & 0xffff)
313#define tWHR_NDTR1(r) (((r) >> 4) & 0xf)
314#define tAR_NDTR1(r) (((r) >> 0) & 0xf)
315
fe69af00 316/* convert nano-seconds to nand flash controller clock cycles */
5b0d4d7c 317#define ns2cycle(ns, clk) (int)(((ns) * (clk / 1000000) / 1000) - 1)
fe69af00 318
f271049e
MR		 319/* convert nand flash controller clock cycles to nano-seconds */
320#define cycle2ns(c, clk) ((((c) + 1) * 1000000 + clk / 500) / (clk / 1000))
321
fe69af00 322static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
7dad482e 323 const struct pxa3xx_nand_timing *t)
fe69af00 324{
325 unsigned long nand_clk = clk_get_rate(info->clk);
326 uint32_t ndtr0, ndtr1;
327
328 ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
329 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
330 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
331 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
332 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
333 NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
334
335 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
336 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
337 NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
338
339 nand_writel(info, NDTR0CS0, ndtr0);
340 nand_writel(info, NDTR1CS0, ndtr1);
341}
342
343#define WAIT_EVENT_TIMEOUT 10
344
345static int wait_for_event(struct pxa3xx_nand_info *info, uint32_t event)
346{
347 int timeout = WAIT_EVENT_TIMEOUT;
348 uint32_t ndsr;
349
350 while (timeout--) {
351 ndsr = nand_readl(info, NDSR) & NDSR_MASK;
352 if (ndsr & event) {
353 nand_writel(info, NDSR, ndsr);
354 return 0;
355 }
356 udelay(10);
357 }
358
359 return -ETIMEDOUT;
360}
361
362static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
363 uint16_t cmd, int column, int page_addr)
364{
c8c17c88 365 const struct pxa3xx_nand_flash *f = info->flash_info;
7dad482e 366 const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
fe69af00 367
368 /* calculate data size */
369 switch (f->page_size) {
370 case 2048:
371 info->data_size = (info->use_ecc) ? 2088 : 2112;
372 break;
373 case 512:
374 info->data_size = (info->use_ecc) ? 520 : 528;
375 break;
376 default:
377 return -EINVAL;
378 }
379
380 /* generate values for NDCBx registers */
381 info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
382 info->ndcb1 = 0;
383 info->ndcb2 = 0;
c8c17c88 384 info->ndcb0 |= NDCB0_ADDR_CYC(info->row_addr_cycles + info->col_addr_cycles);
fe69af00 385
c8c17c88 386 if (info->col_addr_cycles == 2) {
fe69af00 387 /* large block, 2 cycles for column address
388 * row address starts from 3rd cycle
389 */
7f9938d0 390 info->ndcb1 |= page_addr << 16;
c8c17c88 391 if (info->row_addr_cycles == 3)
fe69af00 392 info->ndcb2 = (page_addr >> 16) & 0xff;
393 } else
394 /* small block, 1 cycles for column address
395 * row address starts from 2nd cycle
396 */
7f9938d0 397 info->ndcb1 = page_addr << 8;
fe69af00 398
399 if (cmd == cmdset->program)
400 info->ndcb0 |= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS;
401
402 return 0;
403}
404
405static int prepare_erase_cmd(struct pxa3xx_nand_info *info,
406 uint16_t cmd, int page_addr)
407{
408 info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
409 info->ndcb0 |= NDCB0_CMD_TYPE(2) | NDCB0_AUTO_RS | NDCB0_ADDR_CYC(3);
410 info->ndcb1 = page_addr;
411 info->ndcb2 = 0;
412 return 0;
413}
414
415static int prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
416{
7dad482e 417 const struct pxa3xx_nand_cmdset *cmdset = info->flash_info->cmdset;
fe69af00 418
419 info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
420 info->ndcb1 = 0;
421 info->ndcb2 = 0;
422
423 if (cmd == cmdset->read_id) {
424 info->ndcb0 |= NDCB0_CMD_TYPE(3);
425 info->data_size = 8;
426 } else if (cmd == cmdset->read_status) {
427 info->ndcb0 |= NDCB0_CMD_TYPE(4);
428 info->data_size = 8;
429 } else if (cmd == cmdset->reset || cmd == cmdset->lock ||
430 cmd == cmdset->unlock) {
431 info->ndcb0 |= NDCB0_CMD_TYPE(5);
432 } else
433 return -EINVAL;
434
435 return 0;
436}
437
438static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
439{
440 uint32_t ndcr;
441
442 ndcr = nand_readl(info, NDCR);
443 nand_writel(info, NDCR, ndcr & ~int_mask);
444}
445
446static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
447{
448 uint32_t ndcr;
449
450 ndcr = nand_readl(info, NDCR);
451 nand_writel(info, NDCR, ndcr | int_mask);
452}
453
454/* NOTE: it is a must to set ND_RUN firstly, then write command buffer
455 * otherwise, it does not work
456 */
457static int write_cmd(struct pxa3xx_nand_info *info)
458{
459 uint32_t ndcr;
460
461 /* clear status bits and run */
462 nand_writel(info, NDSR, NDSR_MASK);
463
464 ndcr = info->reg_ndcr;
465
466 ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
467 ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
468 ndcr |= NDCR_ND_RUN;
469
470 nand_writel(info, NDCR, ndcr);
471
472 if (wait_for_event(info, NDSR_WRCMDREQ)) {
473 printk(KERN_ERR "timed out writing command\n");
474 return -ETIMEDOUT;
475 }
476
477 nand_writel(info, NDCB0, info->ndcb0);
478 nand_writel(info, NDCB0, info->ndcb1);
479 nand_writel(info, NDCB0, info->ndcb2);
480 return 0;
481}
482
483static int handle_data_pio(struct pxa3xx_nand_info *info)
484{
485 int ret, timeout = CHIP_DELAY_TIMEOUT;
486
487 switch (info->state) {
488 case STATE_PIO_WRITING:
489 __raw_writesl(info->mmio_base + NDDB, info->data_buff,
a88bdbb5 490 DIV_ROUND_UP(info->data_size, 4));
fe69af00 491
492 enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
493
494 ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
495 if (!ret) {
496 printk(KERN_ERR "program command time out\n");
497 return -1;
498 }
499 break;
500 case STATE_PIO_READING:
501 __raw_readsl(info->mmio_base + NDDB, info->data_buff,
a88bdbb5 502 DIV_ROUND_UP(info->data_size, 4));
fe69af00 503 break;
504 default:
a1c06ee1 505 printk(KERN_ERR "%s: invalid state %d\n", __func__,
fe69af00 506 info->state);
507 return -EINVAL;
508 }
509
510 info->state = STATE_READY;
511 return 0;
512}
513
514static void start_data_dma(struct pxa3xx_nand_info *info, int dir_out)
515{
516 struct pxa_dma_desc *desc = info->data_desc;
517 int dma_len = ALIGN(info->data_size, 32);
518
519 desc->ddadr = DDADR_STOP;
520 desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
521
522 if (dir_out) {
523 desc->dsadr = info->data_buff_phys;
8638fac8 524 desc->dtadr = info->mmio_phys + NDDB;
fe69af00 525 desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
526 } else {
527 desc->dtadr = info->data_buff_phys;
8638fac8 528 desc->dsadr = info->mmio_phys + NDDB;
fe69af00 529 desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
530 }
531
532 DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
533 DDADR(info->data_dma_ch) = info->data_desc_addr;
534 DCSR(info->data_dma_ch) |= DCSR_RUN;
535}
536
537static void pxa3xx_nand_data_dma_irq(int channel, void *data)
538{
539 struct pxa3xx_nand_info *info = data;
540 uint32_t dcsr;
541
542 dcsr = DCSR(channel);
543 DCSR(channel) = dcsr;
544
545 if (dcsr & DCSR_BUSERR) {
546 info->retcode = ERR_DMABUSERR;
547 complete(&info->cmd_complete);
548 }
549
550 if (info->state == STATE_DMA_WRITING) {
551 info->state = STATE_DMA_DONE;
552 enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
553 } else {
554 info->state = STATE_READY;
555 complete(&info->cmd_complete);
556 }
557}
558
559static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
560{
561 struct pxa3xx_nand_info *info = devid;
562 unsigned int status;
563
564 status = nand_readl(info, NDSR);
565
223cf6c3 566 if (status & (NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR)) {
fe69af00 567 if (status & NDSR_DBERR)
568 info->retcode = ERR_DBERR;
223cf6c3
YP		 569 else if (status & NDSR_SBERR)
570 info->retcode = ERR_SBERR;
fe69af00 571
223cf6c3 572 disable_int(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
fe69af00 573
574 if (info->use_dma) {
575 info->state = STATE_DMA_READING;
576 start_data_dma(info, 0);
577 } else {
578 info->state = STATE_PIO_READING;
579 complete(&info->cmd_complete);
580 }
581 } else if (status & NDSR_WRDREQ) {
582 disable_int(info, NDSR_WRDREQ);
583 if (info->use_dma) {
584 info->state = STATE_DMA_WRITING;
585 start_data_dma(info, 1);
586 } else {
587 info->state = STATE_PIO_WRITING;
588 complete(&info->cmd_complete);
589 }
590 } else if (status & (NDSR_CS0_BBD | NDSR_CS0_CMDD)) {
591 if (status & NDSR_CS0_BBD)
592 info->retcode = ERR_BBERR;
593
594 disable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
595 info->state = STATE_READY;
596 complete(&info->cmd_complete);
597 }
598 nand_writel(info, NDSR, status);
599 return IRQ_HANDLED;
600}
601
602static int pxa3xx_nand_do_cmd(struct pxa3xx_nand_info *info, uint32_t event)
603{
604 uint32_t ndcr;
605 int ret, timeout = CHIP_DELAY_TIMEOUT;
606
607 if (write_cmd(info)) {
608 info->retcode = ERR_SENDCMD;
609 goto fail_stop;
610 }
611
612 info->state = STATE_CMD_HANDLE;
613
614 enable_int(info, event);
615
616 ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
617 if (!ret) {
618 printk(KERN_ERR "command execution timed out\n");
619 info->retcode = ERR_SENDCMD;
620 goto fail_stop;
621 }
622
623 if (info->use_dma == 0 && info->data_size > 0)
624 if (handle_data_pio(info))
625 goto fail_stop;
626
627 return 0;
628
629fail_stop:
630 ndcr = nand_readl(info, NDCR);
631 nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
632 udelay(10);
633 return -ETIMEDOUT;
634}
635
636static int pxa3xx_nand_dev_ready(struct mtd_info *mtd)
637{
638 struct pxa3xx_nand_info *info = mtd->priv;
639 return (nand_readl(info, NDSR) & NDSR_RDY) ? 1 : 0;
640}
641
642static inline int is_buf_blank(uint8_t *buf, size_t len)
643{
644 for (; len > 0; len--)
645 if (*buf++ != 0xff)
646 return 0;
647 return 1;
648}
649
650static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
a1c06ee1 651 int column, int page_addr)
fe69af00 652{
653 struct pxa3xx_nand_info *info = mtd->priv;
c8c17c88 654 const struct pxa3xx_nand_flash *flash_info = info->flash_info;
7dad482e 655 const struct pxa3xx_nand_cmdset *cmdset = flash_info->cmdset;
fe69af00 656 int ret;
657
658 info->use_dma = (use_dma) ? 1 : 0;
659 info->use_ecc = 0;
660 info->data_size = 0;
661 info->state = STATE_READY;
662
663 init_completion(&info->cmd_complete);
664
665 switch (command) {
666 case NAND_CMD_READOOB:
667 /* disable HW ECC to get all the OOB data */
668 info->buf_count = mtd->writesize + mtd->oobsize;
669 info->buf_start = mtd->writesize + column;
7ce33aff 670 memset(info->data_buff, 0xFF, info->buf_count);
fe69af00 671
672 if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr))
673 break;
674
223cf6c3 675 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
fe69af00 676
677 /* We only are OOB, so if the data has error, does not matter */
678 if (info->retcode == ERR_DBERR)
679 info->retcode = ERR_NONE;
680 break;
681
682 case NAND_CMD_READ0:
683 info->use_ecc = 1;
684 info->retcode = ERR_NONE;
685 info->buf_start = column;
686 info->buf_count = mtd->writesize + mtd->oobsize;
687 memset(info->data_buff, 0xFF, info->buf_count);
688
689 if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr))
690 break;
691
223cf6c3 692 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
fe69af00 693
694 if (info->retcode == ERR_DBERR) {
695 /* for blank page (all 0xff), HW will calculate its ECC as
696 * 0, which is different from the ECC information within
697 * OOB, ignore such double bit errors
698 */
699 if (is_buf_blank(info->data_buff, mtd->writesize))
700 info->retcode = ERR_NONE;
701 }
702 break;
703 case NAND_CMD_SEQIN:
704 info->buf_start = column;
705 info->buf_count = mtd->writesize + mtd->oobsize;
706 memset(info->data_buff, 0xff, info->buf_count);
707
708 /* save column/page_addr for next CMD_PAGEPROG */
709 info->seqin_column = column;
710 info->seqin_page_addr = page_addr;
711 break;
712 case NAND_CMD_PAGEPROG:
713 info->use_ecc = (info->seqin_column >= mtd->writesize) ? 0 : 1;
714
715 if (prepare_read_prog_cmd(info, cmdset->program,
716 info->seqin_column, info->seqin_page_addr))
717 break;
718
719 pxa3xx_nand_do_cmd(info, NDSR_WRDREQ);
720 break;
721 case NAND_CMD_ERASE1:
722 if (prepare_erase_cmd(info, cmdset->erase, page_addr))
723 break;
724
725 pxa3xx_nand_do_cmd(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
726 break;
727 case NAND_CMD_ERASE2:
728 break;
729 case NAND_CMD_READID:
730 case NAND_CMD_STATUS:
731 info->use_dma = 0; /* force PIO read */
732 info->buf_start = 0;
733 info->buf_count = (command == NAND_CMD_READID) ?
c8c17c88 734 info->read_id_bytes : 1;
fe69af00 735
736 if (prepare_other_cmd(info, (command == NAND_CMD_READID) ?
737 cmdset->read_id : cmdset->read_status))
738 break;
739
740 pxa3xx_nand_do_cmd(info, NDSR_RDDREQ);
741 break;
742 case NAND_CMD_RESET:
743 if (prepare_other_cmd(info, cmdset->reset))
744 break;
745
746 ret = pxa3xx_nand_do_cmd(info, NDSR_CS0_CMDD);
747 if (ret == 0) {
748 int timeout = 2;
749 uint32_t ndcr;
750
751 while (timeout--) {
752 if (nand_readl(info, NDSR) & NDSR_RDY)
753 break;
754 msleep(10);
755 }
756
757 ndcr = nand_readl(info, NDCR);
758 nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
759 }
760 break;
761 default:
762 printk(KERN_ERR "non-supported command.\n");
763 break;
764 }
765
766 if (info->retcode == ERR_DBERR) {
767 printk(KERN_ERR "double bit error @ page %08x\n", page_addr);
768 info->retcode = ERR_NONE;
769 }
770}
771
772static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
773{
774 struct pxa3xx_nand_info *info = mtd->priv;
775 char retval = 0xFF;
776
777 if (info->buf_start < info->buf_count)
778 /* Has just send a new command? */
779 retval = info->data_buff[info->buf_start++];
780
781 return retval;
782}
783
784static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
785{
786 struct pxa3xx_nand_info *info = mtd->priv;
787 u16 retval = 0xFFFF;
788
789 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
790 retval = *((u16 *)(info->data_buff+info->buf_start));
791 info->buf_start += 2;
792 }
793 return retval;
794}
795
796static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
797{
798 struct pxa3xx_nand_info *info = mtd->priv;
799 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
800
801 memcpy(buf, info->data_buff + info->buf_start, real_len);
802 info->buf_start += real_len;
803}
804
805static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
806 const uint8_t *buf, int len)
807{
808 struct pxa3xx_nand_info *info = mtd->priv;
809 int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
810
811 memcpy(info->data_buff + info->buf_start, buf, real_len);
812 info->buf_start += real_len;
813}
814
815static int pxa3xx_nand_verify_buf(struct mtd_info *mtd,
816 const uint8_t *buf, int len)
817{
818 return 0;
819}
820
821static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
822{
823 return;
824}
825
826static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
827{
828 struct pxa3xx_nand_info *info = mtd->priv;
829
830 /* pxa3xx_nand_send_command has waited for command complete */
831 if (this->state == FL_WRITING || this->state == FL_ERASING) {
832 if (info->retcode == ERR_NONE)
833 return 0;
834 else {
835 /*
836 * any error make it return 0x01 which will tell
837 * the caller the erase and write fail
838 */
839 return 0x01;
840 }
841 }
842
843 return 0;
844}
845
846static void pxa3xx_nand_ecc_hwctl(struct mtd_info *mtd, int mode)
847{
848 return;
849}
850
851static int pxa3xx_nand_ecc_calculate(struct mtd_info *mtd,
852 const uint8_t *dat, uint8_t *ecc_code)
853{
854 return 0;
855}
856
857static int pxa3xx_nand_ecc_correct(struct mtd_info *mtd,
858 uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc)
859{
860 struct pxa3xx_nand_info *info = mtd->priv;
861 /*
862 * Any error include ERR_SEND_CMD, ERR_DBERR, ERR_BUSERR, we
863 * consider it as a ecc error which will tell the caller the
864 * read fail We have distinguish all the errors, but the
865 * nand_read_ecc only check this function return value
223cf6c3
YP		 866 *
867 * Corrected (single-bit) errors must also be noted.
fe69af00 868 */
223cf6c3
YP		 869 if (info->retcode == ERR_SBERR)
870 return 1;
871 else if (info->retcode != ERR_NONE)
fe69af00 872 return -1;
873
874 return 0;
875}
876
877static int __readid(struct pxa3xx_nand_info *info, uint32_t *id)
878{
c8c17c88 879 const struct pxa3xx_nand_flash *f = info->flash_info;
7dad482e 880 const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
fe69af00 881 uint32_t ndcr;
882 uint8_t id_buff[8];
883
884 if (prepare_other_cmd(info, cmdset->read_id)) {
885 printk(KERN_ERR "failed to prepare command\n");
886 return -EINVAL;
887 }
888
889 /* Send command */
890 if (write_cmd(info))
891 goto fail_timeout;
892
893 /* Wait for CMDDM(command done successfully) */
894 if (wait_for_event(info, NDSR_RDDREQ))
895 goto fail_timeout;
896
897 __raw_readsl(info->mmio_base + NDDB, id_buff, 2);
898 *id = id_buff[0] | (id_buff[1] << 8);
899 return 0;
900
901fail_timeout:
902 ndcr = nand_readl(info, NDCR);
903 nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
904 udelay(10);
905 return -ETIMEDOUT;
906}
907
908static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
c8c17c88 909 const struct pxa3xx_nand_flash *f)
fe69af00 910{
911 struct platform_device *pdev = info->pdev;
912 struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
913 uint32_t ndcr = 0x00000FFF; /* disable all interrupts */
914
915 if (f->page_size != 2048 && f->page_size != 512)
916 return -EINVAL;
917
918 if (f->flash_width != 16 && f->flash_width != 8)
919 return -EINVAL;
920
921 /* calculate flash information */
c8c17c88
ES		 922 info->oob_size = (f->page_size == 2048) ? 64 : 16;
923 info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
fe69af00 924
925 /* calculate addressing information */
c8c17c88 926 info->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
fe69af00 927
928 if (f->num_blocks * f->page_per_block > 65536)
c8c17c88 929 info->row_addr_cycles = 3;
fe69af00 930 else
c8c17c88 931 info->row_addr_cycles = 2;
fe69af00 932
933 ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
c8c17c88 934 ndcr |= (info->col_addr_cycles == 2) ? NDCR_RA_START : 0;
fe69af00 935 ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
936 ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
937 ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
938 ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
939
c8c17c88 940 ndcr |= NDCR_RD_ID_CNT(info->read_id_bytes);
fe69af00 941 ndcr |= NDCR_SPARE_EN; /* enable spare by default */
942
943 info->reg_ndcr = ndcr;
944
945 pxa3xx_nand_set_timing(info, f->timing);
946 info->flash_info = f;
947 return 0;
948}
949
f271049e
MR		 950static void pxa3xx_nand_detect_timing(struct pxa3xx_nand_info *info,
951 struct pxa3xx_nand_timing *t)
952{
953 unsigned long nand_clk = clk_get_rate(info->clk);
954 uint32_t ndtr0 = nand_readl(info, NDTR0CS0);
955 uint32_t ndtr1 = nand_readl(info, NDTR1CS0);
956
957 t->tCH = cycle2ns(tCH_NDTR0(ndtr0), nand_clk);
958 t->tCS = cycle2ns(tCS_NDTR0(ndtr0), nand_clk);
959 t->tWH = cycle2ns(tWH_NDTR0(ndtr0), nand_clk);
960 t->tWP = cycle2ns(tWP_NDTR0(ndtr0), nand_clk);
961 t->tRH = cycle2ns(tRH_NDTR0(ndtr0), nand_clk);
962 t->tRP = cycle2ns(tRP_NDTR0(ndtr0), nand_clk);
963
964 t->tR = cycle2ns(tR_NDTR1(ndtr1), nand_clk);
965 t->tWHR = cycle2ns(tWHR_NDTR1(ndtr1), nand_clk);
966 t->tAR = cycle2ns(tAR_NDTR1(ndtr1), nand_clk);
967}
968
969static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
970{
971 uint32_t ndcr = nand_readl(info, NDCR);
972 struct nand_flash_dev *type = NULL;
973 uint32_t id = -1;
974 int i;
975
976 default_flash.page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32;
977 default_flash.page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
978 default_flash.flash_width = ndcr & NDCR_DWIDTH_M ? 16 : 8;
979 default_flash.dfc_width = ndcr & NDCR_DWIDTH_C ? 16 : 8;
980
981 if (default_flash.page_size == 2048)
982 default_flash.cmdset = &largepage_cmdset;
983 else
984 default_flash.cmdset = &smallpage_cmdset;
985
986 /* set info fields needed to __readid */
987 info->flash_info = &default_flash;
988 info->read_id_bytes = (default_flash.page_size == 2048) ? 4 : 2;
989 info->reg_ndcr = ndcr;
990
991 if (__readid(info, &id))
992 return -ENODEV;
993
994 /* Lookup the flash id */
995 id = (id >> 8) & 0xff; /* device id is byte 2 */
996 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
997 if (id == nand_flash_ids[i].id) {
998 type = &nand_flash_ids[i];
999 break;
1000 }
1001 }
1002
1003 if (!type)
1004 return -ENODEV;
1005
1006 /* fill the missing flash information */
1007 i = __ffs(default_flash.page_per_block * default_flash.page_size);
1008 default_flash.num_blocks = type->chipsize << (20 - i);
1009
1010 info->oob_size = (default_flash.page_size == 2048) ? 64 : 16;
1011
1012 /* calculate addressing information */
1013 info->col_addr_cycles = (default_flash.page_size == 2048) ? 2 : 1;
1014
1015 if (default_flash.num_blocks * default_flash.page_per_block > 65536)
1016 info->row_addr_cycles = 3;
1017 else
1018 info->row_addr_cycles = 2;
1019
1020 pxa3xx_nand_detect_timing(info, &default_timing);
1021 default_flash.timing = &default_timing;
1022
1023 return 0;
1024}
1025
c8ac3f81
ES		 1026static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info,
1027 const struct pxa3xx_nand_platform_data *pdata)
fe69af00 1028{
c8c17c88 1029 const struct pxa3xx_nand_flash *f;
2675e944 1030 uint32_t id = -1;
fe69af00 1031 int i;
1032
f271049e
MR		 1033 if (pdata->keep_config)
1034 if (pxa3xx_nand_detect_config(info) == 0)
1035 return 0;
1036
c8ac3f81
ES		 1037 for (i = 0; i<pdata->num_flash; ++i) {
1038 f = pdata->flash + i;
1039
1040 if (pxa3xx_nand_config_flash(info, f))
1041 continue;
1042
1043 if (__readid(info, &id))
1044 continue;
1045
1046 if (id == f->chip_id)
1047 return 0;
1048 }
1049
80ebf20f 1050#ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
fe69af00 1051 for (i = 0; i < ARRAY_SIZE(builtin_flash_types); i++) {
1052
1053 f = builtin_flash_types[i];
1054
1055 if (pxa3xx_nand_config_flash(info, f))
1056 continue;
1057
1058 if (__readid(info, &id))
1059 continue;
1060
1061 if (id == f->chip_id)
1062 return 0;
1063 }
80ebf20f 1064#endif
fe69af00 1065
2675e944
ES		 1066 dev_warn(&info->pdev->dev,
1067 "failed to detect configured nand flash; found %04x instead of\n",
1068 id);
fe69af00 1069 return -ENODEV;
1070}
1071
1072/* the maximum possible buffer size for large page with OOB data
1073 * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
1074 * data buffer and the DMA descriptor
1075 */
1076#define MAX_BUFF_SIZE PAGE_SIZE
1077
1078static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
1079{
1080 struct platform_device *pdev = info->pdev;
1081 int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
1082
1083 if (use_dma == 0) {
1084 info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
1085 if (info->data_buff == NULL)
1086 return -ENOMEM;
1087 return 0;
1088 }
1089
1090 info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
1091 &info->data_buff_phys, GFP_KERNEL);
1092 if (info->data_buff == NULL) {
1093 dev_err(&pdev->dev, "failed to allocate dma buffer\n");
1094 return -ENOMEM;
1095 }
1096
1097 info->data_buff_size = MAX_BUFF_SIZE;
1098 info->data_desc = (void *)info->data_buff + data_desc_offset;
1099 info->data_desc_addr = info->data_buff_phys + data_desc_offset;
1100
1101 info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
1102 pxa3xx_nand_data_dma_irq, info);
1103 if (info->data_dma_ch < 0) {
1104 dev_err(&pdev->dev, "failed to request data dma\n");
1105 dma_free_coherent(&pdev->dev, info->data_buff_size,
1106 info->data_buff, info->data_buff_phys);
1107 return info->data_dma_ch;
1108 }
1109
1110 return 0;
1111}
1112
1113static struct nand_ecclayout hw_smallpage_ecclayout = {
1114 .eccbytes = 6,
1115 .eccpos = {8, 9, 10, 11, 12, 13 },
1116 .oobfree = { {2, 6} }
1117};
1118
1119static struct nand_ecclayout hw_largepage_ecclayout = {
1120 .eccbytes = 24,
1121 .eccpos = {
1122 40, 41, 42, 43, 44, 45, 46, 47,
1123 48, 49, 50, 51, 52, 53, 54, 55,
1124 56, 57, 58, 59, 60, 61, 62, 63},
1125 .oobfree = { {2, 38} }
1126};
1127
1128static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
1129 struct pxa3xx_nand_info *info)
1130{
c8c17c88 1131 const struct pxa3xx_nand_flash *f = info->flash_info;
fe69af00 1132 struct nand_chip *this = &info->nand_chip;
1133
1134 this->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0;
1135
1136 this->waitfunc = pxa3xx_nand_waitfunc;
1137 this->select_chip = pxa3xx_nand_select_chip;
1138 this->dev_ready = pxa3xx_nand_dev_ready;
1139 this->cmdfunc = pxa3xx_nand_cmdfunc;
1140 this->read_word = pxa3xx_nand_read_word;
1141 this->read_byte = pxa3xx_nand_read_byte;
1142 this->read_buf = pxa3xx_nand_read_buf;
1143 this->write_buf = pxa3xx_nand_write_buf;
1144 this->verify_buf = pxa3xx_nand_verify_buf;
1145
1146 this->ecc.mode = NAND_ECC_HW;
1147 this->ecc.hwctl = pxa3xx_nand_ecc_hwctl;
1148 this->ecc.calculate = pxa3xx_nand_ecc_calculate;
1149 this->ecc.correct = pxa3xx_nand_ecc_correct;
1150 this->ecc.size = f->page_size;
1151
1152 if (f->page_size == 2048)
1153 this->ecc.layout = &hw_largepage_ecclayout;
1154 else
1155 this->ecc.layout = &hw_smallpage_ecclayout;
1156
a1c06ee1 1157 this->chip_delay = 25;
fe69af00 1158}
1159
1160static int pxa3xx_nand_probe(struct platform_device *pdev)
1161{
1162 struct pxa3xx_nand_platform_data *pdata;
1163 struct pxa3xx_nand_info *info;
1164 struct nand_chip *this;
1165 struct mtd_info *mtd;
1166 struct resource *r;
1167 int ret = 0, irq;
1168
1169 pdata = pdev->dev.platform_data;
1170
a1c06ee1 1171 if (!pdata) {
fe69af00 1172 dev_err(&pdev->dev, "no platform data defined\n");
1173 return -ENODEV;
1174 }
1175
1176 mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct pxa3xx_nand_info),
1177 GFP_KERNEL);
a1c06ee1 1178 if (!mtd) {
fe69af00 1179 dev_err(&pdev->dev, "failed to allocate memory\n");
1180 return -ENOMEM;
a1c06ee1 1181 }
fe69af00 1182
1183 info = (struct pxa3xx_nand_info *)(&mtd[1]);
1184 info->pdev = pdev;
1185
1186 this = &info->nand_chip;
1187 mtd->priv = info;
82a72d10 1188 mtd->owner = THIS_MODULE;
fe69af00 1189
e0d8b13a 1190 info->clk = clk_get(&pdev->dev, NULL);
fe69af00 1191 if (IS_ERR(info->clk)) {
1192 dev_err(&pdev->dev, "failed to get nand clock\n");
1193 ret = PTR_ERR(info->clk);
1194 goto fail_free_mtd;
1195 }
1196 clk_enable(info->clk);
1197
1198 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1199 if (r == NULL) {
1200 dev_err(&pdev->dev, "no resource defined for data DMA\n");
1201 ret = -ENXIO;
1202 goto fail_put_clk;
1203 }
1204 info->drcmr_dat = r->start;
1205
1206 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1207 if (r == NULL) {
1208 dev_err(&pdev->dev, "no resource defined for command DMA\n");
1209 ret = -ENXIO;
1210 goto fail_put_clk;
1211 }
1212 info->drcmr_cmd = r->start;
1213
1214 irq = platform_get_irq(pdev, 0);
1215 if (irq < 0) {
1216 dev_err(&pdev->dev, "no IRQ resource defined\n");
1217 ret = -ENXIO;
1218 goto fail_put_clk;
1219 }
1220
1221 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1222 if (r == NULL) {
1223 dev_err(&pdev->dev, "no IO memory resource defined\n");
1224 ret = -ENODEV;
1225 goto fail_put_clk;
1226 }
1227
b2ed3680 1228 r = request_mem_region(r->start, resource_size(r), pdev->name);
fe69af00 1229 if (r == NULL) {
1230 dev_err(&pdev->dev, "failed to request memory resource\n");
1231 ret = -EBUSY;
1232 goto fail_put_clk;
1233 }
1234
b2ed3680 1235 info->mmio_base = ioremap(r->start, resource_size(r));
fe69af00 1236 if (info->mmio_base == NULL) {
1237 dev_err(&pdev->dev, "ioremap() failed\n");
1238 ret = -ENODEV;
1239 goto fail_free_res;
1240 }
8638fac8 1241 info->mmio_phys = r->start;
fe69af00 1242
1243 ret = pxa3xx_nand_init_buff(info);
1244 if (ret)
1245 goto fail_free_io;
1246
dbf5986a
HZ		 1247 ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED,
1248 pdev->name, info);
fe69af00 1249 if (ret < 0) {
1250 dev_err(&pdev->dev, "failed to request IRQ\n");
1251 goto fail_free_buf;
1252 }
1253
c8ac3f81 1254 ret = pxa3xx_nand_detect_flash(info, pdata);
fe69af00 1255 if (ret) {
1256 dev_err(&pdev->dev, "failed to detect flash\n");
1257 ret = -ENODEV;
1258 goto fail_free_irq;
1259 }
1260
1261 pxa3xx_nand_init_mtd(mtd, info);
1262
1263 platform_set_drvdata(pdev, mtd);
1264
1265 if (nand_scan(mtd, 1)) {
1266 dev_err(&pdev->dev, "failed to scan nand\n");
1267 ret = -ENXIO;
1268 goto fail_free_irq;
1269 }
1270
1271 return add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts);
1272
1273fail_free_irq:
dbf5986a 1274 free_irq(irq, info);
fe69af00 1275fail_free_buf:
1276 if (use_dma) {
1277 pxa_free_dma(info->data_dma_ch);
1278 dma_free_coherent(&pdev->dev, info->data_buff_size,
1279 info->data_buff, info->data_buff_phys);
1280 } else
1281 kfree(info->data_buff);
1282fail_free_io:
1283 iounmap(info->mmio_base);
1284fail_free_res:
b2ed3680 1285 release_mem_region(r->start, resource_size(r));
fe69af00 1286fail_put_clk:
1287 clk_disable(info->clk);
1288 clk_put(info->clk);
1289fail_free_mtd:
1290 kfree(mtd);
1291 return ret;
1292}
1293
1294static int pxa3xx_nand_remove(struct platform_device *pdev)
1295{
1296 struct mtd_info *mtd = platform_get_drvdata(pdev);
1297 struct pxa3xx_nand_info *info = mtd->priv;
82a72d10 1298 struct resource *r;
dbf5986a 1299 int irq;
fe69af00 1300
1301 platform_set_drvdata(pdev, NULL);
1302
1303 del_mtd_device(mtd);
1304 del_mtd_partitions(mtd);
dbf5986a
HZ		 1305 irq = platform_get_irq(pdev, 0);
1306 if (irq >= 0)
1307 free_irq(irq, info);
fe69af00 1308 if (use_dma) {
1309 pxa_free_dma(info->data_dma_ch);
1310 dma_free_writecombine(&pdev->dev, info->data_buff_size,
1311 info->data_buff, info->data_buff_phys);
1312 } else
1313 kfree(info->data_buff);
82a72d10
MR		 1314
1315 iounmap(info->mmio_base);
1316 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1317 release_mem_region(r->start, resource_size(r));
1318
1319 clk_disable(info->clk);
1320 clk_put(info->clk);
1321
fe69af00 1322 kfree(mtd);
1323 return 0;
1324}
1325
1326#ifdef CONFIG_PM
1327static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state)
1328{
1329 struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
1330 struct pxa3xx_nand_info *info = mtd->priv;
1331
1332 if (info->state != STATE_READY) {
1333 dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
1334 return -EAGAIN;
1335 }
1336
1337 return 0;
1338}
1339
1340static int pxa3xx_nand_resume(struct platform_device *pdev)
1341{
1342 struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
1343 struct pxa3xx_nand_info *info = mtd->priv;
1344
1345 clk_enable(info->clk);
1346
9b62d864 1347 return pxa3xx_nand_config_flash(info, info->flash_info);
fe69af00 1348}
1349#else
1350#define pxa3xx_nand_suspend NULL
1351#define pxa3xx_nand_resume NULL
1352#endif
1353
1354static struct platform_driver pxa3xx_nand_driver = {
1355 .driver = {
1356 .name = "pxa3xx-nand",
1357 },
1358 .probe = pxa3xx_nand_probe,
1359 .remove = pxa3xx_nand_remove,
1360 .suspend = pxa3xx_nand_suspend,
1361 .resume = pxa3xx_nand_resume,
1362};
1363
1364static int __init pxa3xx_nand_init(void)
1365{
1366 return platform_driver_register(&pxa3xx_nand_driver);
1367}
1368module_init(pxa3xx_nand_init);
1369
1370static void __exit pxa3xx_nand_exit(void)
1371{
1372 platform_driver_unregister(&pxa3xx_nand_driver);
1373}
1374module_exit(pxa3xx_nand_exit);
1375
1376MODULE_LICENSE("GPL");
1377MODULE_DESCRIPTION("PXA3xx NAND controller driver");
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