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Commit | Line | Data |
---|---|---|
c9ac5977 | 1 | /* |
fbad5696 | 2 | * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01 |
5467fb02 | 3 | * |
514fca43 | 4 | * The data sheet for this device can be found at: |
631dd1a8 | 5 | * http://wiki.laptop.org/go/Datasheets |
514fca43 | 6 | * |
5467fb02 DW |
7 | * Copyright © 2006 Red Hat, Inc. |
8 | * Copyright © 2006 David Woodhouse <dwmw2@infradead.org> | |
9 | */ | |
10 | ||
8dd851de | 11 | #define DEBUG |
5467fb02 DW |
12 | |
13 | #include <linux/device.h> | |
14 | #undef DEBUG | |
15 | #include <linux/mtd/mtd.h> | |
d4092d76 | 16 | #include <linux/mtd/rawnand.h> |
9c37f332 | 17 | #include <linux/mtd/partitions.h> |
8c61b7a7 | 18 | #include <linux/rslib.h> |
5467fb02 DW |
19 | #include <linux/pci.h> |
20 | #include <linux/delay.h> | |
21 | #include <linux/interrupt.h> | |
a1274302 | 22 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
a0e5cc58 | 24 | #include <linux/module.h> |
5467fb02 DW |
25 | #include <asm/io.h> |
26 | ||
27 | #define CAFE_NAND_CTRL1 0x00 | |
28 | #define CAFE_NAND_CTRL2 0x04 | |
29 | #define CAFE_NAND_CTRL3 0x08 | |
30 | #define CAFE_NAND_STATUS 0x0c | |
31 | #define CAFE_NAND_IRQ 0x10 | |
32 | #define CAFE_NAND_IRQ_MASK 0x14 | |
33 | #define CAFE_NAND_DATA_LEN 0x18 | |
34 | #define CAFE_NAND_ADDR1 0x1c | |
35 | #define CAFE_NAND_ADDR2 0x20 | |
36 | #define CAFE_NAND_TIMING1 0x24 | |
37 | #define CAFE_NAND_TIMING2 0x28 | |
38 | #define CAFE_NAND_TIMING3 0x2c | |
39 | #define CAFE_NAND_NONMEM 0x30 | |
04459d7c | 40 | #define CAFE_NAND_ECC_RESULT 0x3C |
fbad5696 DW |
41 | #define CAFE_NAND_DMA_CTRL 0x40 |
42 | #define CAFE_NAND_DMA_ADDR0 0x44 | |
43 | #define CAFE_NAND_DMA_ADDR1 0x48 | |
04459d7c DW |
44 | #define CAFE_NAND_ECC_SYN01 0x50 |
45 | #define CAFE_NAND_ECC_SYN23 0x54 | |
46 | #define CAFE_NAND_ECC_SYN45 0x58 | |
47 | #define CAFE_NAND_ECC_SYN67 0x5c | |
5467fb02 DW |
48 | #define CAFE_NAND_READ_DATA 0x1000 |
49 | #define CAFE_NAND_WRITE_DATA 0x2000 | |
50 | ||
195a253b DW |
51 | #define CAFE_GLOBAL_CTRL 0x3004 |
52 | #define CAFE_GLOBAL_IRQ 0x3008 | |
53 | #define CAFE_GLOBAL_IRQ_MASK 0x300c | |
54 | #define CAFE_NAND_RESET 0x3034 | |
55 | ||
048c37b4 DW |
56 | /* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */ |
57 | #define CTRL1_CHIPSELECT (1<<19) | |
58 | ||
5467fb02 DW |
59 | struct cafe_priv { |
60 | struct nand_chip nand; | |
61 | struct pci_dev *pdev; | |
62 | void __iomem *mmio; | |
8c61b7a7 | 63 | struct rs_control *rs; |
5467fb02 DW |
64 | uint32_t ctl1; |
65 | uint32_t ctl2; | |
66 | int datalen; | |
67 | int nr_data; | |
68 | int data_pos; | |
69 | int page_addr; | |
73a27db8 | 70 | bool usedma; |
5467fb02 DW |
71 | dma_addr_t dmaaddr; |
72 | unsigned char *dmabuf; | |
5467fb02 DW |
73 | }; |
74 | ||
b478c775 | 75 | static int usedma = 1; |
5467fb02 DW |
76 | module_param(usedma, int, 0644); |
77 | ||
8dd851de DW |
78 | static int skipbbt = 0; |
79 | module_param(skipbbt, int, 0644); | |
80 | ||
81 | static int debug = 0; | |
82 | module_param(debug, int, 0644); | |
83 | ||
be8444bd DW |
84 | static int regdebug = 0; |
85 | module_param(regdebug, int, 0644); | |
86 | ||
b478c775 | 87 | static int checkecc = 1; |
470b0a90 DW |
88 | module_param(checkecc, int, 0644); |
89 | ||
64a6f950 | 90 | static unsigned int numtimings; |
527a4f45 DW |
91 | static int timing[3]; |
92 | module_param_array(timing, int, &numtimings, 0644); | |
b478c775 | 93 | |
68874414 | 94 | static const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL }; |
9c37f332 | 95 | |
04459d7c | 96 | /* Hrm. Why isn't this already conditional on something in the struct device? */ |
8dd851de DW |
97 | #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0) |
98 | ||
195a253b DW |
99 | /* Make it easier to switch to PIO if we need to */ |
100 | #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr) | |
101 | #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr) | |
8dd851de | 102 | |
50a487e7 | 103 | static int cafe_device_ready(struct nand_chip *chip) |
5467fb02 | 104 | { |
d699ed25 | 105 | struct cafe_priv *cafe = nand_get_controller_data(chip); |
48f8b641 | 106 | int result = !!(cafe_readl(cafe, NAND_STATUS) & 0x40000000); |
195a253b | 107 | uint32_t irqs = cafe_readl(cafe, NAND_IRQ); |
fbad5696 | 108 | |
195a253b | 109 | cafe_writel(cafe, irqs, NAND_IRQ); |
fbad5696 | 110 | |
8dd851de | 111 | cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n", |
195a253b DW |
112 | result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ), |
113 | cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK)); | |
fbad5696 | 114 | |
5467fb02 DW |
115 | return result; |
116 | } | |
117 | ||
118 | ||
c0739d85 | 119 | static void cafe_write_buf(struct nand_chip *chip, const uint8_t *buf, int len) |
5467fb02 | 120 | { |
d699ed25 | 121 | struct cafe_priv *cafe = nand_get_controller_data(chip); |
5467fb02 | 122 | |
73a27db8 | 123 | if (cafe->usedma) |
5467fb02 DW |
124 | memcpy(cafe->dmabuf + cafe->datalen, buf, len); |
125 | else | |
126 | memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len); | |
fbad5696 | 127 | |
5467fb02 DW |
128 | cafe->datalen += len; |
129 | ||
8dd851de | 130 | cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n", |
5467fb02 DW |
131 | len, cafe->datalen); |
132 | } | |
133 | ||
7e534323 | 134 | static void cafe_read_buf(struct nand_chip *chip, uint8_t *buf, int len) |
5467fb02 | 135 | { |
d699ed25 | 136 | struct cafe_priv *cafe = nand_get_controller_data(chip); |
5467fb02 | 137 | |
73a27db8 | 138 | if (cafe->usedma) |
5467fb02 DW |
139 | memcpy(buf, cafe->dmabuf + cafe->datalen, len); |
140 | else | |
141 | memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len); | |
142 | ||
8dd851de | 143 | cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n", |
5467fb02 DW |
144 | len, cafe->datalen); |
145 | cafe->datalen += len; | |
146 | } | |
147 | ||
7e534323 | 148 | static uint8_t cafe_read_byte(struct nand_chip *chip) |
5467fb02 | 149 | { |
d699ed25 | 150 | struct cafe_priv *cafe = nand_get_controller_data(chip); |
5467fb02 DW |
151 | uint8_t d; |
152 | ||
7e534323 | 153 | cafe_read_buf(chip, &d, 1); |
8dd851de | 154 | cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d); |
5467fb02 DW |
155 | |
156 | return d; | |
157 | } | |
158 | ||
5295cf2e | 159 | static void cafe_nand_cmdfunc(struct nand_chip *chip, unsigned command, |
5467fb02 DW |
160 | int column, int page_addr) |
161 | { | |
5295cf2e | 162 | struct mtd_info *mtd = nand_to_mtd(chip); |
d699ed25 | 163 | struct cafe_priv *cafe = nand_get_controller_data(chip); |
5467fb02 DW |
164 | int adrbytes = 0; |
165 | uint32_t ctl1; | |
166 | uint32_t doneint = 0x80000000; | |
5467fb02 | 167 | |
8dd851de | 168 | cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n", |
5467fb02 DW |
169 | command, column, page_addr); |
170 | ||
171 | if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) { | |
172 | /* Second half of a command we already calculated */ | |
195a253b | 173 | cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2); |
5467fb02 | 174 | ctl1 = cafe->ctl1; |
cad40654 | 175 | cafe->ctl2 &= ~(1<<30); |
8dd851de | 176 | cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n", |
5467fb02 DW |
177 | cafe->ctl1, cafe->nr_data); |
178 | goto do_command; | |
179 | } | |
180 | /* Reset ECC engine */ | |
195a253b | 181 | cafe_writel(cafe, 0, NAND_CTRL2); |
5467fb02 DW |
182 | |
183 | /* Emulate NAND_CMD_READOOB on large-page chips */ | |
184 | if (mtd->writesize > 512 && | |
185 | command == NAND_CMD_READOOB) { | |
186 | column += mtd->writesize; | |
187 | command = NAND_CMD_READ0; | |
188 | } | |
189 | ||
190 | /* FIXME: Do we need to send read command before sending data | |
191 | for small-page chips, to position the buffer correctly? */ | |
192 | ||
193 | if (column != -1) { | |
195a253b | 194 | cafe_writel(cafe, column, NAND_ADDR1); |
5467fb02 DW |
195 | adrbytes = 2; |
196 | if (page_addr != -1) | |
197 | goto write_adr2; | |
198 | } else if (page_addr != -1) { | |
195a253b | 199 | cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1); |
5467fb02 DW |
200 | page_addr >>= 16; |
201 | write_adr2: | |
195a253b | 202 | cafe_writel(cafe, page_addr, NAND_ADDR2); |
5467fb02 DW |
203 | adrbytes += 2; |
204 | if (mtd->size > mtd->writesize << 16) | |
205 | adrbytes++; | |
206 | } | |
207 | ||
208 | cafe->data_pos = cafe->datalen = 0; | |
209 | ||
048c37b4 DW |
210 | /* Set command valid bit, mask in the chip select bit */ |
211 | ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT); | |
5467fb02 DW |
212 | |
213 | /* Set RD or WR bits as appropriate */ | |
214 | if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) { | |
215 | ctl1 |= (1<<26); /* rd */ | |
216 | /* Always 5 bytes, for now */ | |
8dd851de | 217 | cafe->datalen = 4; |
5467fb02 DW |
218 | /* And one address cycle -- even for STATUS, since the controller doesn't work without */ |
219 | adrbytes = 1; | |
220 | } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 || | |
221 | command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) { | |
222 | ctl1 |= 1<<26; /* rd */ | |
223 | /* For now, assume just read to end of page */ | |
224 | cafe->datalen = mtd->writesize + mtd->oobsize - column; | |
225 | } else if (command == NAND_CMD_SEQIN) | |
226 | ctl1 |= 1<<25; /* wr */ | |
227 | ||
228 | /* Set number of address bytes */ | |
229 | if (adrbytes) | |
230 | ctl1 |= ((adrbytes-1)|8) << 27; | |
231 | ||
232 | if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) { | |
c9ac5977 | 233 | /* Ignore the first command of a pair; the hardware |
5467fb02 DW |
234 | deals with them both at once, later */ |
235 | cafe->ctl1 = ctl1; | |
8dd851de | 236 | cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n", |
5467fb02 DW |
237 | cafe->ctl1, cafe->datalen); |
238 | return; | |
239 | } | |
240 | /* RNDOUT and READ0 commands need a following byte */ | |
241 | if (command == NAND_CMD_RNDOUT) | |
195a253b | 242 | cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2); |
5467fb02 | 243 | else if (command == NAND_CMD_READ0 && mtd->writesize > 512) |
195a253b | 244 | cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2); |
5467fb02 DW |
245 | |
246 | do_command: | |
c9ac5977 | 247 | cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n", |
195a253b | 248 | cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2)); |
fbad5696 | 249 | |
5467fb02 | 250 | /* NB: The datasheet lies -- we really should be subtracting 1 here */ |
195a253b DW |
251 | cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN); |
252 | cafe_writel(cafe, 0x90000000, NAND_IRQ); | |
73a27db8 | 253 | if (cafe->usedma && (ctl1 & (3<<25))) { |
5467fb02 DW |
254 | uint32_t dmactl = 0xc0000000 + cafe->datalen; |
255 | /* If WR or RD bits set, set up DMA */ | |
256 | if (ctl1 & (1<<26)) { | |
257 | /* It's a read */ | |
258 | dmactl |= (1<<29); | |
259 | /* ... so it's done when the DMA is done, not just | |
260 | the command. */ | |
261 | doneint = 0x10000000; | |
262 | } | |
195a253b | 263 | cafe_writel(cafe, dmactl, NAND_DMA_CTRL); |
5467fb02 | 264 | } |
5467fb02 DW |
265 | cafe->datalen = 0; |
266 | ||
be8444bd DW |
267 | if (unlikely(regdebug)) { |
268 | int i; | |
269 | printk("About to write command %08x to register 0\n", ctl1); | |
270 | for (i=4; i< 0x5c; i+=4) | |
271 | printk("Register %x: %08x\n", i, readl(cafe->mmio + i)); | |
fbad5696 | 272 | } |
be8444bd | 273 | |
195a253b | 274 | cafe_writel(cafe, ctl1, NAND_CTRL1); |
5467fb02 DW |
275 | /* Apply this short delay always to ensure that we do wait tWB in |
276 | * any case on any machine. */ | |
277 | ndelay(100); | |
278 | ||
279 | if (1) { | |
2a7295b2 | 280 | int c; |
5467fb02 DW |
281 | uint32_t irqs; |
282 | ||
2a7295b2 | 283 | for (c = 500000; c != 0; c--) { |
195a253b | 284 | irqs = cafe_readl(cafe, NAND_IRQ); |
5467fb02 DW |
285 | if (irqs & doneint) |
286 | break; | |
287 | udelay(1); | |
8dd851de DW |
288 | if (!(c % 100000)) |
289 | cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs); | |
5467fb02 DW |
290 | cpu_relax(); |
291 | } | |
195a253b | 292 | cafe_writel(cafe, doneint, NAND_IRQ); |
a020727b | 293 | cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n", |
195a253b | 294 | command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ)); |
5467fb02 DW |
295 | } |
296 | ||
cad40654 | 297 | WARN_ON(cafe->ctl2 & (1<<30)); |
5467fb02 DW |
298 | |
299 | switch (command) { | |
300 | ||
301 | case NAND_CMD_CACHEDPROG: | |
302 | case NAND_CMD_PAGEPROG: | |
303 | case NAND_CMD_ERASE1: | |
304 | case NAND_CMD_ERASE2: | |
305 | case NAND_CMD_SEQIN: | |
306 | case NAND_CMD_RNDIN: | |
307 | case NAND_CMD_STATUS: | |
5467fb02 | 308 | case NAND_CMD_RNDOUT: |
195a253b | 309 | cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); |
5467fb02 DW |
310 | return; |
311 | } | |
2b356ab4 | 312 | nand_wait_ready(chip); |
195a253b | 313 | cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); |
5467fb02 DW |
314 | } |
315 | ||
758b56f5 | 316 | static void cafe_select_chip(struct nand_chip *chip, int chipnr) |
5467fb02 | 317 | { |
d699ed25 | 318 | struct cafe_priv *cafe = nand_get_controller_data(chip); |
048c37b4 DW |
319 | |
320 | cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr); | |
321 | ||
322 | /* Mask the appropriate bit into the stored value of ctl1 | |
323 | which will be used by cafe_nand_cmdfunc() */ | |
324 | if (chipnr) | |
325 | cafe->ctl1 |= CTRL1_CHIPSELECT; | |
326 | else | |
327 | cafe->ctl1 &= ~CTRL1_CHIPSELECT; | |
5467fb02 | 328 | } |
fbad5696 | 329 | |
67cd724f | 330 | static irqreturn_t cafe_nand_interrupt(int irq, void *id) |
5467fb02 DW |
331 | { |
332 | struct mtd_info *mtd = id; | |
4bd4ebcc | 333 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 334 | struct cafe_priv *cafe = nand_get_controller_data(chip); |
195a253b DW |
335 | uint32_t irqs = cafe_readl(cafe, NAND_IRQ); |
336 | cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ); | |
5467fb02 DW |
337 | if (!irqs) |
338 | return IRQ_NONE; | |
339 | ||
195a253b | 340 | cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ)); |
5467fb02 DW |
341 | return IRQ_HANDLED; |
342 | } | |
343 | ||
767eb6fb | 344 | static int cafe_nand_write_oob(struct nand_chip *chip, int page) |
5467fb02 | 345 | { |
767eb6fb BB |
346 | struct mtd_info *mtd = nand_to_mtd(chip); |
347 | ||
97d90da8 BB |
348 | return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi, |
349 | mtd->oobsize); | |
5467fb02 DW |
350 | } |
351 | ||
352 | /* Don't use -- use nand_read_oob_std for now */ | |
b9761687 | 353 | static int cafe_nand_read_oob(struct nand_chip *chip, int page) |
5467fb02 | 354 | { |
b9761687 BB |
355 | struct mtd_info *mtd = nand_to_mtd(chip); |
356 | ||
97d90da8 | 357 | return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); |
5467fb02 DW |
358 | } |
359 | /** | |
7854d3f7 | 360 | * cafe_nand_read_page_syndrome - [REPLACEABLE] hardware ecc syndrome based page read |
5467fb02 DW |
361 | * @mtd: mtd info structure |
362 | * @chip: nand chip info structure | |
363 | * @buf: buffer to store read data | |
1fbb938d | 364 | * @oob_required: caller expects OOB data read to chip->oob_poi |
5467fb02 | 365 | * |
b9bc815c | 366 | * The hw generator calculates the error syndrome automatically. Therefore |
5467fb02 DW |
367 | * we need a special oob layout and handling. |
368 | */ | |
b9761687 BB |
369 | static int cafe_nand_read_page(struct nand_chip *chip, uint8_t *buf, |
370 | int oob_required, int page) | |
5467fb02 | 371 | { |
b9761687 | 372 | struct mtd_info *mtd = nand_to_mtd(chip); |
d699ed25 | 373 | struct cafe_priv *cafe = nand_get_controller_data(chip); |
3f91e94f | 374 | unsigned int max_bitflips = 0; |
5467fb02 | 375 | |
fbad5696 | 376 | cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n", |
195a253b DW |
377 | cafe_readl(cafe, NAND_ECC_RESULT), |
378 | cafe_readl(cafe, NAND_ECC_SYN01)); | |
5467fb02 | 379 | |
25f815f6 | 380 | nand_read_page_op(chip, page, 0, buf, mtd->writesize); |
716bbbab | 381 | chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize); |
5467fb02 | 382 | |
195a253b | 383 | if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) { |
8c61b7a7 SB |
384 | unsigned short syn[8], pat[4]; |
385 | int pos[4]; | |
386 | u8 *oob = chip->oob_poi; | |
387 | int i, n; | |
04459d7c DW |
388 | |
389 | for (i=0; i<8; i+=2) { | |
195a253b | 390 | uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2)); |
21633981 TG |
391 | |
392 | syn[i] = cafe->rs->codec->index_of[tmp & 0xfff]; | |
393 | syn[i+1] = cafe->rs->codec->index_of[(tmp >> 16) & 0xfff]; | |
8c61b7a7 SB |
394 | } |
395 | ||
396 | n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0, | |
21633981 | 397 | pat); |
8c61b7a7 SB |
398 | |
399 | for (i = 0; i < n; i++) { | |
400 | int p = pos[i]; | |
401 | ||
402 | /* The 12-bit symbols are mapped to bytes here */ | |
403 | ||
404 | if (p > 1374) { | |
405 | /* out of range */ | |
406 | n = -1374; | |
407 | } else if (p == 0) { | |
408 | /* high four bits do not correspond to data */ | |
409 | if (pat[i] > 0xff) | |
410 | n = -2048; | |
411 | else | |
412 | buf[0] ^= pat[i]; | |
413 | } else if (p == 1365) { | |
414 | buf[2047] ^= pat[i] >> 4; | |
415 | oob[0] ^= pat[i] << 4; | |
416 | } else if (p > 1365) { | |
417 | if ((p & 1) == 1) { | |
418 | oob[3*p/2 - 2048] ^= pat[i] >> 4; | |
419 | oob[3*p/2 - 2047] ^= pat[i] << 4; | |
420 | } else { | |
421 | oob[3*p/2 - 2049] ^= pat[i] >> 8; | |
422 | oob[3*p/2 - 2048] ^= pat[i]; | |
423 | } | |
424 | } else if ((p & 1) == 1) { | |
425 | buf[3*p/2] ^= pat[i] >> 4; | |
426 | buf[3*p/2 + 1] ^= pat[i] << 4; | |
427 | } else { | |
428 | buf[3*p/2 - 1] ^= pat[i] >> 8; | |
429 | buf[3*p/2] ^= pat[i]; | |
430 | } | |
c9ac5977 | 431 | } |
04459d7c | 432 | |
8c61b7a7 | 433 | if (n < 0) { |
be8444bd DW |
434 | dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n", |
435 | cafe_readl(cafe, NAND_ADDR2) * 2048); | |
8c61b7a7 | 436 | for (i = 0; i < 0x5c; i += 4) |
be8444bd | 437 | printk("Register %x: %08x\n", i, readl(cafe->mmio + i)); |
04459d7c DW |
438 | mtd->ecc_stats.failed++; |
439 | } else { | |
8c61b7a7 SB |
440 | dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n); |
441 | mtd->ecc_stats.corrected += n; | |
3f91e94f | 442 | max_bitflips = max_t(unsigned int, max_bitflips, n); |
04459d7c DW |
443 | } |
444 | } | |
445 | ||
3f91e94f | 446 | return max_bitflips; |
5467fb02 DW |
447 | } |
448 | ||
a8ed6e66 BB |
449 | static int cafe_ooblayout_ecc(struct mtd_info *mtd, int section, |
450 | struct mtd_oob_region *oobregion) | |
451 | { | |
452 | struct nand_chip *chip = mtd_to_nand(mtd); | |
453 | ||
454 | if (section) | |
455 | return -ERANGE; | |
456 | ||
457 | oobregion->offset = 0; | |
458 | oobregion->length = chip->ecc.total; | |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
463 | static int cafe_ooblayout_free(struct mtd_info *mtd, int section, | |
464 | struct mtd_oob_region *oobregion) | |
465 | { | |
466 | struct nand_chip *chip = mtd_to_nand(mtd); | |
467 | ||
468 | if (section) | |
469 | return -ERANGE; | |
470 | ||
471 | oobregion->offset = chip->ecc.total; | |
472 | oobregion->length = mtd->oobsize - chip->ecc.total; | |
473 | ||
474 | return 0; | |
475 | } | |
476 | ||
477 | static const struct mtd_ooblayout_ops cafe_ooblayout_ops = { | |
478 | .ecc = cafe_ooblayout_ecc, | |
479 | .free = cafe_ooblayout_free, | |
8dd851de DW |
480 | }; |
481 | ||
c9ac5977 | 482 | /* Ick. The BBT code really ought to be able to work this bit out |
fbad5696 DW |
483 | for itself from the above, at least for the 2KiB case */ |
484 | static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' }; | |
485 | static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' }; | |
486 | ||
487 | static uint8_t cafe_bbt_pattern_512[] = { 0xBB }; | |
488 | static uint8_t cafe_mirror_pattern_512[] = { 0xBC }; | |
489 | ||
8dd851de DW |
490 | |
491 | static struct nand_bbt_descr cafe_bbt_main_descr_2048 = { | |
492 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
048c37b4 | 493 | | NAND_BBT_2BIT | NAND_BBT_VERSION, |
8dd851de DW |
494 | .offs = 14, |
495 | .len = 4, | |
496 | .veroffs = 18, | |
497 | .maxblocks = 4, | |
fbad5696 | 498 | .pattern = cafe_bbt_pattern_2048 |
8dd851de DW |
499 | }; |
500 | ||
501 | static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = { | |
502 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
048c37b4 | 503 | | NAND_BBT_2BIT | NAND_BBT_VERSION, |
8dd851de DW |
504 | .offs = 14, |
505 | .len = 4, | |
506 | .veroffs = 18, | |
507 | .maxblocks = 4, | |
fbad5696 | 508 | .pattern = cafe_mirror_pattern_2048 |
8dd851de DW |
509 | }; |
510 | ||
fbad5696 DW |
511 | static struct nand_bbt_descr cafe_bbt_main_descr_512 = { |
512 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
048c37b4 | 513 | | NAND_BBT_2BIT | NAND_BBT_VERSION, |
fbad5696 DW |
514 | .offs = 14, |
515 | .len = 1, | |
516 | .veroffs = 15, | |
517 | .maxblocks = 4, | |
518 | .pattern = cafe_bbt_pattern_512 | |
519 | }; | |
520 | ||
521 | static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = { | |
522 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
048c37b4 | 523 | | NAND_BBT_2BIT | NAND_BBT_VERSION, |
fbad5696 DW |
524 | .offs = 14, |
525 | .len = 1, | |
526 | .veroffs = 15, | |
527 | .maxblocks = 4, | |
528 | .pattern = cafe_mirror_pattern_512 | |
529 | }; | |
530 | ||
531 | ||
767eb6fb BB |
532 | static int cafe_nand_write_page_lowlevel(struct nand_chip *chip, |
533 | const uint8_t *buf, int oob_required, | |
534 | int page) | |
5467fb02 | 535 | { |
767eb6fb | 536 | struct mtd_info *mtd = nand_to_mtd(chip); |
d699ed25 | 537 | struct cafe_priv *cafe = nand_get_controller_data(chip); |
5467fb02 | 538 | |
25f815f6 | 539 | nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize); |
716bbbab | 540 | chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize); |
5467fb02 DW |
541 | |
542 | /* Set up ECC autogeneration */ | |
cad40654 | 543 | cafe->ctl2 |= (1<<30); |
fdbad98d | 544 | |
25f815f6 | 545 | return nand_prog_page_end_op(chip); |
5467fb02 DW |
546 | } |
547 | ||
c17556f5 | 548 | static int cafe_nand_block_bad(struct nand_chip *chip, loff_t ofs) |
8dd851de DW |
549 | { |
550 | return 0; | |
551 | } | |
5467fb02 | 552 | |
8c61b7a7 | 553 | /* F_2[X]/(X**6+X+1) */ |
06f25510 | 554 | static unsigned short gf64_mul(u8 a, u8 b) |
8c61b7a7 SB |
555 | { |
556 | u8 c; | |
557 | unsigned int i; | |
558 | ||
559 | c = 0; | |
560 | for (i = 0; i < 6; i++) { | |
561 | if (a & 1) | |
562 | c ^= b; | |
563 | a >>= 1; | |
564 | b <<= 1; | |
565 | if ((b & 0x40) != 0) | |
566 | b ^= 0x43; | |
567 | } | |
568 | ||
569 | return c; | |
570 | } | |
571 | ||
572 | /* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X] */ | |
06f25510 | 573 | static u16 gf4096_mul(u16 a, u16 b) |
8c61b7a7 SB |
574 | { |
575 | u8 ah, al, bh, bl, ch, cl; | |
576 | ||
577 | ah = a >> 6; | |
578 | al = a & 0x3f; | |
579 | bh = b >> 6; | |
580 | bl = b & 0x3f; | |
581 | ||
582 | ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl); | |
583 | cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl); | |
584 | ||
585 | return (ch << 6) ^ cl; | |
586 | } | |
587 | ||
06f25510 | 588 | static int cafe_mul(int x) |
8c61b7a7 SB |
589 | { |
590 | if (x == 0) | |
591 | return 1; | |
592 | return gf4096_mul(x, 0xe01); | |
593 | } | |
594 | ||
73a27db8 MR |
595 | static int cafe_nand_attach_chip(struct nand_chip *chip) |
596 | { | |
597 | struct mtd_info *mtd = nand_to_mtd(chip); | |
598 | struct cafe_priv *cafe = nand_get_controller_data(chip); | |
599 | int err = 0; | |
600 | ||
601 | cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112, | |
602 | &cafe->dmaaddr, GFP_KERNEL); | |
603 | if (!cafe->dmabuf) | |
604 | return -ENOMEM; | |
605 | ||
606 | /* Set up DMA address */ | |
607 | cafe_writel(cafe, lower_32_bits(cafe->dmaaddr), NAND_DMA_ADDR0); | |
608 | cafe_writel(cafe, upper_32_bits(cafe->dmaaddr), NAND_DMA_ADDR1); | |
609 | ||
610 | cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n", | |
611 | cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf); | |
612 | ||
613 | /* Restore the DMA flag */ | |
614 | cafe->usedma = usedma; | |
615 | ||
616 | cafe->ctl2 = BIT(27); /* Reed-Solomon ECC */ | |
617 | if (mtd->writesize == 2048) | |
618 | cafe->ctl2 |= BIT(29); /* 2KiB page size */ | |
619 | ||
620 | /* Set up ECC according to the type of chip we found */ | |
621 | mtd_set_ooblayout(mtd, &cafe_ooblayout_ops); | |
622 | if (mtd->writesize == 2048) { | |
623 | cafe->nand.bbt_td = &cafe_bbt_main_descr_2048; | |
624 | cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048; | |
625 | } else if (mtd->writesize == 512) { | |
626 | cafe->nand.bbt_td = &cafe_bbt_main_descr_512; | |
627 | cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512; | |
628 | } else { | |
629 | dev_warn(&cafe->pdev->dev, | |
630 | "Unexpected NAND flash writesize %d. Aborting\n", | |
631 | mtd->writesize); | |
632 | err = -ENOTSUPP; | |
633 | goto out_free_dma; | |
634 | } | |
635 | ||
636 | cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME; | |
637 | cafe->nand.ecc.size = mtd->writesize; | |
638 | cafe->nand.ecc.bytes = 14; | |
639 | cafe->nand.ecc.strength = 4; | |
640 | cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel; | |
641 | cafe->nand.ecc.write_oob = cafe_nand_write_oob; | |
642 | cafe->nand.ecc.read_page = cafe_nand_read_page; | |
643 | cafe->nand.ecc.read_oob = cafe_nand_read_oob; | |
644 | ||
645 | return 0; | |
646 | ||
647 | out_free_dma: | |
648 | dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr); | |
649 | ||
650 | return err; | |
651 | } | |
652 | ||
653 | static void cafe_nand_detach_chip(struct nand_chip *chip) | |
654 | { | |
655 | struct cafe_priv *cafe = nand_get_controller_data(chip); | |
656 | ||
657 | dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr); | |
658 | } | |
659 | ||
660 | static const struct nand_controller_ops cafe_nand_controller_ops = { | |
661 | .attach_chip = cafe_nand_attach_chip, | |
662 | .detach_chip = cafe_nand_detach_chip, | |
663 | }; | |
664 | ||
06f25510 | 665 | static int cafe_nand_probe(struct pci_dev *pdev, |
5467fb02 DW |
666 | const struct pci_device_id *ent) |
667 | { | |
668 | struct mtd_info *mtd; | |
669 | struct cafe_priv *cafe; | |
670 | uint32_t ctrl; | |
671 | int err = 0; | |
672 | ||
06ed24e5 DW |
673 | /* Very old versions shared the same PCI ident for all three |
674 | functions on the chip. Verify the class too... */ | |
675 | if ((pdev->class >> 8) != PCI_CLASS_MEMORY_FLASH) | |
676 | return -ENODEV; | |
677 | ||
5467fb02 DW |
678 | err = pci_enable_device(pdev); |
679 | if (err) | |
680 | return err; | |
681 | ||
682 | pci_set_master(pdev); | |
683 | ||
e787dfd1 BB |
684 | cafe = kzalloc(sizeof(*cafe), GFP_KERNEL); |
685 | if (!cafe) | |
5467fb02 | 686 | return -ENOMEM; |
5467fb02 | 687 | |
e787dfd1 | 688 | mtd = nand_to_mtd(&cafe->nand); |
c451c7c4 | 689 | mtd->dev.parent = &pdev->dev; |
d699ed25 | 690 | nand_set_controller_data(&cafe->nand, cafe); |
5467fb02 DW |
691 | |
692 | cafe->pdev = pdev; | |
693 | cafe->mmio = pci_iomap(pdev, 0, 0); | |
694 | if (!cafe->mmio) { | |
695 | dev_warn(&pdev->dev, "failed to iomap\n"); | |
696 | err = -ENOMEM; | |
697 | goto out_free_mtd; | |
698 | } | |
5467fb02 | 699 | |
8c61b7a7 SB |
700 | cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8); |
701 | if (!cafe->rs) { | |
702 | err = -ENOMEM; | |
703 | goto out_ior; | |
704 | } | |
705 | ||
bf6065c6 | 706 | cafe->nand.legacy.cmdfunc = cafe_nand_cmdfunc; |
8395b753 | 707 | cafe->nand.legacy.dev_ready = cafe_device_ready; |
716bbbab BB |
708 | cafe->nand.legacy.read_byte = cafe_read_byte; |
709 | cafe->nand.legacy.read_buf = cafe_read_buf; | |
710 | cafe->nand.legacy.write_buf = cafe_write_buf; | |
7d6c37e9 | 711 | cafe->nand.legacy.select_chip = cafe_select_chip; |
45240367 BB |
712 | cafe->nand.legacy.set_features = nand_get_set_features_notsupp; |
713 | cafe->nand.legacy.get_features = nand_get_set_features_notsupp; | |
5467fb02 | 714 | |
3cece3ab | 715 | cafe->nand.legacy.chip_delay = 0; |
5467fb02 DW |
716 | |
717 | /* Enable the following for a flash based bad block table */ | |
bb9ebd4e | 718 | cafe->nand.bbt_options = NAND_BBT_USE_FLASH; |
8dd851de DW |
719 | |
720 | if (skipbbt) { | |
721 | cafe->nand.options |= NAND_SKIP_BBTSCAN; | |
cdc784c7 | 722 | cafe->nand.legacy.block_bad = cafe_nand_block_bad; |
8dd851de | 723 | } |
c9ac5977 | 724 | |
527a4f45 DW |
725 | if (numtimings && numtimings != 3) { |
726 | dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings); | |
727 | } | |
728 | ||
729 | if (numtimings == 3) { | |
527a4f45 | 730 | cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n", |
8e5368a1 | 731 | timing[0], timing[1], timing[2]); |
527a4f45 | 732 | } else { |
8e5368a1 DW |
733 | timing[0] = cafe_readl(cafe, NAND_TIMING1); |
734 | timing[1] = cafe_readl(cafe, NAND_TIMING2); | |
735 | timing[2] = cafe_readl(cafe, NAND_TIMING3); | |
527a4f45 | 736 | |
8e5368a1 DW |
737 | if (timing[0] | timing[1] | timing[2]) { |
738 | cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n", | |
739 | timing[0], timing[1], timing[2]); | |
527a4f45 DW |
740 | } else { |
741 | dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n"); | |
8e5368a1 | 742 | timing[0] = timing[1] = timing[2] = 0xffffffff; |
527a4f45 DW |
743 | } |
744 | } | |
745 | ||
dcc41bc8 | 746 | /* Start off by resetting the NAND controller completely */ |
195a253b DW |
747 | cafe_writel(cafe, 1, NAND_RESET); |
748 | cafe_writel(cafe, 0, NAND_RESET); | |
dcc41bc8 | 749 | |
8e5368a1 DW |
750 | cafe_writel(cafe, timing[0], NAND_TIMING1); |
751 | cafe_writel(cafe, timing[1], NAND_TIMING2); | |
752 | cafe_writel(cafe, timing[2], NAND_TIMING3); | |
b478c775 | 753 | |
195a253b | 754 | cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK); |
2db6346f TG |
755 | err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED, |
756 | "CAFE NAND", mtd); | |
5467fb02 DW |
757 | if (err) { |
758 | dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq); | |
f02ea4e6 | 759 | goto out_ior; |
5467fb02 | 760 | } |
f7c37d7b | 761 | |
5467fb02 | 762 | /* Disable master reset, enable NAND clock */ |
195a253b | 763 | ctrl = cafe_readl(cafe, GLOBAL_CTRL); |
5467fb02 DW |
764 | ctrl &= 0xffffeff0; |
765 | ctrl |= 0x00007000; | |
195a253b DW |
766 | cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL); |
767 | cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL); | |
768 | cafe_writel(cafe, 0, NAND_DMA_CTRL); | |
5467fb02 | 769 | |
195a253b DW |
770 | cafe_writel(cafe, 0x7006, GLOBAL_CTRL); |
771 | cafe_writel(cafe, 0x700a, GLOBAL_CTRL); | |
5467fb02 | 772 | |
f02ea4e6 HS |
773 | /* Enable NAND IRQ in global IRQ mask register */ |
774 | cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK); | |
775 | cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n", | |
776 | cafe_readl(cafe, GLOBAL_CTRL), | |
777 | cafe_readl(cafe, GLOBAL_IRQ_MASK)); | |
778 | ||
73a27db8 MR |
779 | /* Do not use the DMA during the NAND identification */ |
780 | cafe->usedma = 0; | |
f02ea4e6 HS |
781 | |
782 | /* Scan to find existence of the device */ | |
7b6a9b28 | 783 | cafe->nand.legacy.dummy_controller.ops = &cafe_nand_controller_ops; |
00ad378f | 784 | err = nand_scan(&cafe->nand, 2); |
72480e4e | 785 | if (err) |
f02ea4e6 | 786 | goto out_irq; |
f02ea4e6 | 787 | |
5467fb02 | 788 | pci_set_drvdata(pdev, mtd); |
9c37f332 | 789 | |
68874414 | 790 | mtd->name = "cafe_nand"; |
a446c998 MR |
791 | err = mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0); |
792 | if (err) | |
793 | goto out_cleanup_nand; | |
4d32de81 | 794 | |
5467fb02 DW |
795 | goto out; |
796 | ||
a446c998 MR |
797 | out_cleanup_nand: |
798 | nand_cleanup(&cafe->nand); | |
5467fb02 DW |
799 | out_irq: |
800 | /* Disable NAND IRQ in global IRQ mask register */ | |
195a253b | 801 | cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK); |
5467fb02 | 802 | free_irq(pdev->irq, mtd); |
5467fb02 DW |
803 | out_ior: |
804 | pci_iounmap(pdev, cafe->mmio); | |
805 | out_free_mtd: | |
e787dfd1 | 806 | kfree(cafe); |
5467fb02 DW |
807 | out: |
808 | return err; | |
809 | } | |
810 | ||
810b7e06 | 811 | static void cafe_nand_remove(struct pci_dev *pdev) |
5467fb02 DW |
812 | { |
813 | struct mtd_info *mtd = pci_get_drvdata(pdev); | |
4bd4ebcc | 814 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 815 | struct cafe_priv *cafe = nand_get_controller_data(chip); |
5467fb02 | 816 | |
5467fb02 | 817 | /* Disable NAND IRQ in global IRQ mask register */ |
195a253b | 818 | cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK); |
5467fb02 | 819 | free_irq(pdev->irq, mtd); |
59ac276f | 820 | nand_release(chip); |
8c61b7a7 | 821 | free_rs(cafe->rs); |
5467fb02 | 822 | pci_iounmap(pdev, cafe->mmio); |
f880b07b | 823 | dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr); |
e787dfd1 | 824 | kfree(cafe); |
5467fb02 DW |
825 | } |
826 | ||
377ace08 | 827 | static const struct pci_device_id cafe_nand_tbl[] = { |
514fca43 DW |
828 | { PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_88ALP01_NAND, |
829 | PCI_ANY_ID, PCI_ANY_ID }, | |
06ed24e5 | 830 | { } |
5467fb02 DW |
831 | }; |
832 | ||
833 | MODULE_DEVICE_TABLE(pci, cafe_nand_tbl); | |
834 | ||
1fcf8ce5 DW |
835 | static int cafe_nand_resume(struct pci_dev *pdev) |
836 | { | |
837 | uint32_t ctrl; | |
838 | struct mtd_info *mtd = pci_get_drvdata(pdev); | |
4bd4ebcc | 839 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 840 | struct cafe_priv *cafe = nand_get_controller_data(chip); |
1fcf8ce5 DW |
841 | |
842 | /* Start off by resetting the NAND controller completely */ | |
843 | cafe_writel(cafe, 1, NAND_RESET); | |
844 | cafe_writel(cafe, 0, NAND_RESET); | |
845 | cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK); | |
846 | ||
847 | /* Restore timing configuration */ | |
848 | cafe_writel(cafe, timing[0], NAND_TIMING1); | |
849 | cafe_writel(cafe, timing[1], NAND_TIMING2); | |
850 | cafe_writel(cafe, timing[2], NAND_TIMING3); | |
851 | ||
852 | /* Disable master reset, enable NAND clock */ | |
853 | ctrl = cafe_readl(cafe, GLOBAL_CTRL); | |
854 | ctrl &= 0xffffeff0; | |
855 | ctrl |= 0x00007000; | |
856 | cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL); | |
857 | cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL); | |
858 | cafe_writel(cafe, 0, NAND_DMA_CTRL); | |
859 | cafe_writel(cafe, 0x7006, GLOBAL_CTRL); | |
860 | cafe_writel(cafe, 0x700a, GLOBAL_CTRL); | |
861 | ||
862 | /* Set up DMA address */ | |
863 | cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0); | |
864 | if (sizeof(cafe->dmaaddr) > 4) | |
865 | /* Shift in two parts to shut the compiler up */ | |
866 | cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1); | |
867 | else | |
868 | cafe_writel(cafe, 0, NAND_DMA_ADDR1); | |
869 | ||
870 | /* Enable NAND IRQ in global IRQ mask register */ | |
871 | cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK); | |
872 | return 0; | |
873 | } | |
874 | ||
5467fb02 DW |
875 | static struct pci_driver cafe_nand_pci_driver = { |
876 | .name = "CAFÉ NAND", | |
877 | .id_table = cafe_nand_tbl, | |
878 | .probe = cafe_nand_probe, | |
5153b88c | 879 | .remove = cafe_nand_remove, |
5467fb02 | 880 | .resume = cafe_nand_resume, |
5467fb02 DW |
881 | }; |
882 | ||
4d16cd65 | 883 | module_pci_driver(cafe_nand_pci_driver); |
5467fb02 DW |
884 | |
885 | MODULE_LICENSE("GPL"); | |
886 | MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>"); | |
f7c37d7b | 887 | MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip"); |