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1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
82771882 PK |
2 | /* |
3 | * Freescale Integrated Flash Controller NAND driver | |
4 | * | |
5 | * Copyright 2011-2012 Freescale Semiconductor, Inc | |
6 | * | |
7 | * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com> | |
82771882 PK |
8 | */ |
9 | ||
10 | #include <linux/module.h> | |
11 | #include <linux/types.h> | |
82771882 | 12 | #include <linux/kernel.h> |
5af50730 | 13 | #include <linux/of_address.h> |
82771882 PK |
14 | #include <linux/slab.h> |
15 | #include <linux/mtd/mtd.h> | |
d4092d76 | 16 | #include <linux/mtd/rawnand.h> |
82771882 PK |
17 | #include <linux/mtd/partitions.h> |
18 | #include <linux/mtd/nand_ecc.h> | |
d2ae2e20 | 19 | #include <linux/fsl_ifc.h> |
ff8648f2 | 20 | #include <linux/iopoll.h> |
82771882 PK |
21 | |
22 | #define ERR_BYTE 0xFF /* Value returned for read | |
23 | bytes when read failed */ | |
24 | #define IFC_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait | |
25 | for IFC NAND Machine */ | |
26 | ||
27 | struct fsl_ifc_ctrl; | |
28 | ||
29 | /* mtd information per set */ | |
30 | struct fsl_ifc_mtd { | |
82771882 PK |
31 | struct nand_chip chip; |
32 | struct fsl_ifc_ctrl *ctrl; | |
33 | ||
34 | struct device *dev; | |
35 | int bank; /* Chip select bank number */ | |
36 | unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */ | |
37 | u8 __iomem *vbase; /* Chip select base virtual address */ | |
38 | }; | |
39 | ||
40 | /* overview of the fsl ifc controller */ | |
41 | struct fsl_ifc_nand_ctrl { | |
7da45139 | 42 | struct nand_controller controller; |
82771882 PK |
43 | struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT]; |
44 | ||
4454406e | 45 | void __iomem *addr; /* Address of assigned IFC buffer */ |
82771882 PK |
46 | unsigned int page; /* Last page written to / read from */ |
47 | unsigned int read_bytes;/* Number of bytes read during command */ | |
48 | unsigned int column; /* Saved column from SEQIN */ | |
49 | unsigned int index; /* Pointer to next byte to 'read' */ | |
50 | unsigned int oob; /* Non zero if operating on OOB data */ | |
51 | unsigned int eccread; /* Non zero for a full-page ECC read */ | |
52 | unsigned int counter; /* counter for the initializations */ | |
3f91e94f | 53 | unsigned int max_bitflips; /* Saved during READ0 cmd */ |
82771882 PK |
54 | }; |
55 | ||
56 | static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl; | |
57 | ||
82771882 PK |
58 | /* |
59 | * Generic flash bbt descriptors | |
60 | */ | |
61 | static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; | |
62 | static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; | |
63 | ||
64 | static struct nand_bbt_descr bbt_main_descr = { | |
65 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | |
66 | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
67 | .offs = 2, /* 0 on 8-bit small page */ | |
68 | .len = 4, | |
69 | .veroffs = 6, | |
70 | .maxblocks = 4, | |
71 | .pattern = bbt_pattern, | |
72 | }; | |
73 | ||
74 | static struct nand_bbt_descr bbt_mirror_descr = { | |
75 | .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | | |
76 | NAND_BBT_2BIT | NAND_BBT_VERSION, | |
77 | .offs = 2, /* 0 on 8-bit small page */ | |
78 | .len = 4, | |
79 | .veroffs = 6, | |
80 | .maxblocks = 4, | |
81 | .pattern = mirror_pattern, | |
82 | }; | |
83 | ||
caf5129e BB |
84 | static int fsl_ifc_ooblayout_ecc(struct mtd_info *mtd, int section, |
85 | struct mtd_oob_region *oobregion) | |
86 | { | |
87 | struct nand_chip *chip = mtd_to_nand(mtd); | |
88 | ||
89 | if (section) | |
90 | return -ERANGE; | |
91 | ||
92 | oobregion->offset = 8; | |
93 | oobregion->length = chip->ecc.total; | |
94 | ||
95 | return 0; | |
96 | } | |
97 | ||
98 | static int fsl_ifc_ooblayout_free(struct mtd_info *mtd, int section, | |
99 | struct mtd_oob_region *oobregion) | |
100 | { | |
101 | struct nand_chip *chip = mtd_to_nand(mtd); | |
102 | ||
103 | if (section > 1) | |
104 | return -ERANGE; | |
105 | ||
106 | if (mtd->writesize == 512 && | |
107 | !(chip->options & NAND_BUSWIDTH_16)) { | |
108 | if (!section) { | |
109 | oobregion->offset = 0; | |
110 | oobregion->length = 5; | |
111 | } else { | |
112 | oobregion->offset = 6; | |
113 | oobregion->length = 2; | |
114 | } | |
115 | ||
116 | return 0; | |
117 | } | |
118 | ||
119 | if (!section) { | |
120 | oobregion->offset = 2; | |
121 | oobregion->length = 6; | |
122 | } else { | |
123 | oobregion->offset = chip->ecc.total + 8; | |
124 | oobregion->length = mtd->oobsize - oobregion->offset; | |
125 | } | |
126 | ||
127 | return 0; | |
128 | } | |
129 | ||
130 | static const struct mtd_ooblayout_ops fsl_ifc_ooblayout_ops = { | |
131 | .ecc = fsl_ifc_ooblayout_ecc, | |
132 | .free = fsl_ifc_ooblayout_free, | |
133 | }; | |
134 | ||
82771882 PK |
135 | /* |
136 | * Set up the IFC hardware block and page address fields, and the ifc nand | |
137 | * structure addr field to point to the correct IFC buffer in memory | |
138 | */ | |
139 | static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) | |
140 | { | |
4bd4ebcc | 141 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 142 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 | 143 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; |
7a654172 | 144 | struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; |
82771882 PK |
145 | int buf_num; |
146 | ||
147 | ifc_nand_ctrl->page = page_addr; | |
148 | /* Program ROW0/COL0 */ | |
cf184dc2 JS |
149 | ifc_out32(page_addr, &ifc->ifc_nand.row0); |
150 | ifc_out32((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0); | |
82771882 PK |
151 | |
152 | buf_num = page_addr & priv->bufnum_mask; | |
153 | ||
154 | ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2); | |
155 | ifc_nand_ctrl->index = column; | |
156 | ||
157 | /* for OOB data point to the second half of the buffer */ | |
158 | if (oob) | |
159 | ifc_nand_ctrl->index += mtd->writesize; | |
160 | } | |
161 | ||
82771882 PK |
162 | /* returns nonzero if entire page is blank */ |
163 | static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl, | |
843c3a59 | 164 | u32 eccstat, unsigned int bufnum) |
82771882 | 165 | { |
843c3a59 | 166 | return (eccstat >> ((3 - bufnum % 4) * 8)) & 15; |
82771882 PK |
167 | } |
168 | ||
169 | /* | |
170 | * execute IFC NAND command and wait for it to complete | |
171 | */ | |
172 | static void fsl_ifc_run_command(struct mtd_info *mtd) | |
173 | { | |
4bd4ebcc | 174 | struct nand_chip *chip = mtd_to_nand(mtd); |
d699ed25 | 175 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 PK |
176 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; |
177 | struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl; | |
7a654172 | 178 | struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; |
843c3a59 | 179 | u32 eccstat; |
82771882 PK |
180 | int i; |
181 | ||
182 | /* set the chip select for NAND Transaction */ | |
cf184dc2 JS |
183 | ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT, |
184 | &ifc->ifc_nand.nand_csel); | |
82771882 PK |
185 | |
186 | dev_vdbg(priv->dev, | |
187 | "%s: fir0=%08x fcr0=%08x\n", | |
188 | __func__, | |
cf184dc2 JS |
189 | ifc_in32(&ifc->ifc_nand.nand_fir0), |
190 | ifc_in32(&ifc->ifc_nand.nand_fcr0)); | |
82771882 PK |
191 | |
192 | ctrl->nand_stat = 0; | |
193 | ||
194 | /* start read/write seq */ | |
cf184dc2 | 195 | ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt); |
82771882 PK |
196 | |
197 | /* wait for command complete flag or timeout */ | |
198 | wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat, | |
95d70665 | 199 | msecs_to_jiffies(IFC_TIMEOUT_MSECS)); |
82771882 PK |
200 | |
201 | /* ctrl->nand_stat will be updated from IRQ context */ | |
202 | if (!ctrl->nand_stat) | |
203 | dev_err(priv->dev, "Controller is not responding\n"); | |
204 | if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER) | |
205 | dev_err(priv->dev, "NAND Flash Timeout Error\n"); | |
206 | if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER) | |
207 | dev_err(priv->dev, "NAND Flash Write Protect Error\n"); | |
208 | ||
3f91e94f MD |
209 | nctrl->max_bitflips = 0; |
210 | ||
82771882 PK |
211 | if (nctrl->eccread) { |
212 | int errors; | |
213 | int bufnum = nctrl->page & priv->bufnum_mask; | |
843c3a59 JG |
214 | int sector_start = bufnum * chip->ecc.steps; |
215 | int sector_end = sector_start + chip->ecc.steps - 1; | |
62a31608 | 216 | __be32 __iomem *eccstat_regs; |
65644147 | 217 | |
6b00c351 | 218 | eccstat_regs = ifc->ifc_nand.nand_eccstat; |
843c3a59 JG |
219 | eccstat = ifc_in32(&eccstat_regs[sector_start / 4]); |
220 | ||
221 | for (i = sector_start; i <= sector_end; i++) { | |
222 | if (i != sector_start && !(i % 4)) | |
223 | eccstat = ifc_in32(&eccstat_regs[i / 4]); | |
82771882 | 224 | |
82771882 PK |
225 | errors = check_read_ecc(mtd, ctrl, eccstat, i); |
226 | ||
227 | if (errors == 15) { | |
228 | /* | |
229 | * Uncorrectable error. | |
d45e5316 | 230 | * We'll check for blank pages later. |
82771882 PK |
231 | * |
232 | * We disable ECCER reporting due to... | |
233 | * erratum IFC-A002770 -- so report it now if we | |
234 | * see an uncorrectable error in ECCSTAT. | |
235 | */ | |
d45e5316 BB |
236 | ctrl->nand_stat |= IFC_NAND_EVTER_STAT_ECCER; |
237 | continue; | |
82771882 PK |
238 | } |
239 | ||
240 | mtd->ecc_stats.corrected += errors; | |
3f91e94f MD |
241 | nctrl->max_bitflips = max_t(unsigned int, |
242 | nctrl->max_bitflips, | |
243 | errors); | |
82771882 PK |
244 | } |
245 | ||
246 | nctrl->eccread = 0; | |
247 | } | |
248 | } | |
249 | ||
250 | static void fsl_ifc_do_read(struct nand_chip *chip, | |
251 | int oob, | |
252 | struct mtd_info *mtd) | |
253 | { | |
d699ed25 | 254 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 | 255 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; |
7a654172 | 256 | struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; |
82771882 PK |
257 | |
258 | /* Program FIR/IFC_NAND_FCR0 for Small/Large page */ | |
259 | if (mtd->writesize > 512) { | |
cf184dc2 JS |
260 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
261 | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | | |
262 | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | | |
263 | (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | | |
264 | (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT), | |
265 | &ifc->ifc_nand.nand_fir0); | |
266 | ifc_out32(0x0, &ifc->ifc_nand.nand_fir1); | |
267 | ||
268 | ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | | |
269 | (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT), | |
270 | &ifc->ifc_nand.nand_fcr0); | |
82771882 | 271 | } else { |
cf184dc2 JS |
272 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
273 | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | | |
274 | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | | |
275 | (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT), | |
276 | &ifc->ifc_nand.nand_fir0); | |
277 | ifc_out32(0x0, &ifc->ifc_nand.nand_fir1); | |
82771882 PK |
278 | |
279 | if (oob) | |
cf184dc2 JS |
280 | ifc_out32(NAND_CMD_READOOB << |
281 | IFC_NAND_FCR0_CMD0_SHIFT, | |
282 | &ifc->ifc_nand.nand_fcr0); | |
82771882 | 283 | else |
cf184dc2 JS |
284 | ifc_out32(NAND_CMD_READ0 << |
285 | IFC_NAND_FCR0_CMD0_SHIFT, | |
286 | &ifc->ifc_nand.nand_fcr0); | |
82771882 PK |
287 | } |
288 | } | |
289 | ||
290 | /* cmdfunc send commands to the IFC NAND Machine */ | |
5295cf2e BB |
291 | static void fsl_ifc_cmdfunc(struct nand_chip *chip, unsigned int command, |
292 | int column, int page_addr) { | |
293 | struct mtd_info *mtd = nand_to_mtd(chip); | |
d699ed25 | 294 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 | 295 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; |
7a654172 | 296 | struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; |
82771882 PK |
297 | |
298 | /* clear the read buffer */ | |
299 | ifc_nand_ctrl->read_bytes = 0; | |
300 | if (command != NAND_CMD_PAGEPROG) | |
301 | ifc_nand_ctrl->index = 0; | |
302 | ||
303 | switch (command) { | |
304 | /* READ0 read the entire buffer to use hardware ECC. */ | |
305 | case NAND_CMD_READ0: | |
cf184dc2 | 306 | ifc_out32(0, &ifc->ifc_nand.nand_fbcr); |
82771882 PK |
307 | set_addr(mtd, 0, page_addr, 0); |
308 | ||
309 | ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize; | |
310 | ifc_nand_ctrl->index += column; | |
311 | ||
312 | if (chip->ecc.mode == NAND_ECC_HW) | |
313 | ifc_nand_ctrl->eccread = 1; | |
314 | ||
315 | fsl_ifc_do_read(chip, 0, mtd); | |
316 | fsl_ifc_run_command(mtd); | |
317 | return; | |
318 | ||
319 | /* READOOB reads only the OOB because no ECC is performed. */ | |
320 | case NAND_CMD_READOOB: | |
cf184dc2 | 321 | ifc_out32(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr); |
82771882 PK |
322 | set_addr(mtd, column, page_addr, 1); |
323 | ||
324 | ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize; | |
325 | ||
326 | fsl_ifc_do_read(chip, 1, mtd); | |
327 | fsl_ifc_run_command(mtd); | |
328 | ||
329 | return; | |
330 | ||
82771882 | 331 | case NAND_CMD_READID: |
59fdd5b9 | 332 | case NAND_CMD_PARAM: { |
a75bbe71 JW |
333 | /* |
334 | * For READID, read 8 bytes that are currently used. | |
335 | * For PARAM, read all 3 copies of 256-bytes pages. | |
336 | */ | |
337 | int len = 8; | |
59fdd5b9 | 338 | int timing = IFC_FIR_OP_RB; |
a75bbe71 | 339 | if (command == NAND_CMD_PARAM) { |
59fdd5b9 | 340 | timing = IFC_FIR_OP_RBCD; |
a75bbe71 JW |
341 | len = 256 * 3; |
342 | } | |
59fdd5b9 | 343 | |
cf184dc2 JS |
344 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
345 | (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | | |
346 | (timing << IFC_NAND_FIR0_OP2_SHIFT), | |
347 | &ifc->ifc_nand.nand_fir0); | |
348 | ifc_out32(command << IFC_NAND_FCR0_CMD0_SHIFT, | |
349 | &ifc->ifc_nand.nand_fcr0); | |
350 | ifc_out32(column, &ifc->ifc_nand.row3); | |
59fdd5b9 | 351 | |
a75bbe71 JW |
352 | ifc_out32(len, &ifc->ifc_nand.nand_fbcr); |
353 | ifc_nand_ctrl->read_bytes = len; | |
82771882 PK |
354 | |
355 | set_addr(mtd, 0, 0, 0); | |
356 | fsl_ifc_run_command(mtd); | |
357 | return; | |
59fdd5b9 | 358 | } |
82771882 PK |
359 | |
360 | /* ERASE1 stores the block and page address */ | |
361 | case NAND_CMD_ERASE1: | |
362 | set_addr(mtd, 0, page_addr, 0); | |
363 | return; | |
364 | ||
365 | /* ERASE2 uses the block and page address from ERASE1 */ | |
366 | case NAND_CMD_ERASE2: | |
cf184dc2 JS |
367 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
368 | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | | |
369 | (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT), | |
370 | &ifc->ifc_nand.nand_fir0); | |
82771882 | 371 | |
cf184dc2 JS |
372 | ifc_out32((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | |
373 | (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT), | |
374 | &ifc->ifc_nand.nand_fcr0); | |
82771882 | 375 | |
cf184dc2 | 376 | ifc_out32(0, &ifc->ifc_nand.nand_fbcr); |
82771882 PK |
377 | ifc_nand_ctrl->read_bytes = 0; |
378 | fsl_ifc_run_command(mtd); | |
379 | return; | |
380 | ||
381 | /* SEQIN sets up the addr buffer and all registers except the length */ | |
382 | case NAND_CMD_SEQIN: { | |
383 | u32 nand_fcr0; | |
384 | ifc_nand_ctrl->column = column; | |
385 | ifc_nand_ctrl->oob = 0; | |
386 | ||
387 | if (mtd->writesize > 512) { | |
388 | nand_fcr0 = | |
389 | (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) | | |
4af98749 PK |
390 | (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) | |
391 | (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT); | |
82771882 | 392 | |
cf184dc2 JS |
393 | ifc_out32( |
394 | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | | |
395 | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | | |
396 | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | | |
397 | (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) | | |
398 | (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT), | |
399 | &ifc->ifc_nand.nand_fir0); | |
400 | ifc_out32( | |
401 | (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) | | |
402 | (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) | | |
403 | (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT), | |
404 | &ifc->ifc_nand.nand_fir1); | |
82771882 PK |
405 | } else { |
406 | nand_fcr0 = ((NAND_CMD_PAGEPROG << | |
407 | IFC_NAND_FCR0_CMD1_SHIFT) | | |
408 | (NAND_CMD_SEQIN << | |
4af98749 PK |
409 | IFC_NAND_FCR0_CMD2_SHIFT) | |
410 | (NAND_CMD_STATUS << | |
411 | IFC_NAND_FCR0_CMD3_SHIFT)); | |
82771882 | 412 | |
cf184dc2 | 413 | ifc_out32( |
0c69fb03 KP |
414 | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
415 | (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) | | |
416 | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) | | |
417 | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | | |
418 | (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT), | |
419 | &ifc->ifc_nand.nand_fir0); | |
cf184dc2 JS |
420 | ifc_out32( |
421 | (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) | | |
422 | (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) | | |
423 | (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) | | |
424 | (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT), | |
425 | &ifc->ifc_nand.nand_fir1); | |
82771882 PK |
426 | |
427 | if (column >= mtd->writesize) | |
428 | nand_fcr0 |= | |
429 | NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT; | |
430 | else | |
431 | nand_fcr0 |= | |
432 | NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT; | |
433 | } | |
434 | ||
435 | if (column >= mtd->writesize) { | |
436 | /* OOB area --> READOOB */ | |
437 | column -= mtd->writesize; | |
438 | ifc_nand_ctrl->oob = 1; | |
439 | } | |
cf184dc2 | 440 | ifc_out32(nand_fcr0, &ifc->ifc_nand.nand_fcr0); |
82771882 PK |
441 | set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob); |
442 | return; | |
443 | } | |
444 | ||
445 | /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ | |
446 | case NAND_CMD_PAGEPROG: { | |
447 | if (ifc_nand_ctrl->oob) { | |
cf184dc2 JS |
448 | ifc_out32(ifc_nand_ctrl->index - |
449 | ifc_nand_ctrl->column, | |
450 | &ifc->ifc_nand.nand_fbcr); | |
82771882 | 451 | } else { |
cf184dc2 | 452 | ifc_out32(0, &ifc->ifc_nand.nand_fbcr); |
82771882 PK |
453 | } |
454 | ||
455 | fsl_ifc_run_command(mtd); | |
456 | return; | |
457 | } | |
458 | ||
cf184dc2 JS |
459 | case NAND_CMD_STATUS: { |
460 | void __iomem *addr; | |
461 | ||
462 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | | |
463 | (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT), | |
464 | &ifc->ifc_nand.nand_fir0); | |
465 | ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT, | |
466 | &ifc->ifc_nand.nand_fcr0); | |
467 | ifc_out32(1, &ifc->ifc_nand.nand_fbcr); | |
82771882 PK |
468 | set_addr(mtd, 0, 0, 0); |
469 | ifc_nand_ctrl->read_bytes = 1; | |
470 | ||
471 | fsl_ifc_run_command(mtd); | |
472 | ||
473 | /* | |
474 | * The chip always seems to report that it is | |
475 | * write-protected, even when it is not. | |
476 | */ | |
cf184dc2 | 477 | addr = ifc_nand_ctrl->addr; |
21704804 | 478 | if (chip->options & NAND_BUSWIDTH_16) |
cf184dc2 | 479 | ifc_out16(ifc_in16(addr) | (NAND_STATUS_WP), addr); |
21704804 | 480 | else |
cf184dc2 | 481 | ifc_out8(ifc_in8(addr) | (NAND_STATUS_WP), addr); |
82771882 | 482 | return; |
cf184dc2 | 483 | } |
82771882 PK |
484 | |
485 | case NAND_CMD_RESET: | |
cf184dc2 JS |
486 | ifc_out32(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT, |
487 | &ifc->ifc_nand.nand_fir0); | |
488 | ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT, | |
489 | &ifc->ifc_nand.nand_fcr0); | |
82771882 PK |
490 | fsl_ifc_run_command(mtd); |
491 | return; | |
492 | ||
493 | default: | |
494 | dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n", | |
495 | __func__, command); | |
496 | } | |
497 | } | |
498 | ||
758b56f5 | 499 | static void fsl_ifc_select_chip(struct nand_chip *chip, int cs) |
82771882 PK |
500 | { |
501 | /* The hardware does not seem to support multiple | |
502 | * chips per bank. | |
503 | */ | |
504 | } | |
505 | ||
506 | /* | |
507 | * Write buf to the IFC NAND Controller Data Buffer | |
508 | */ | |
c0739d85 | 509 | static void fsl_ifc_write_buf(struct nand_chip *chip, const u8 *buf, int len) |
82771882 | 510 | { |
c0739d85 | 511 | struct mtd_info *mtd = nand_to_mtd(chip); |
d699ed25 | 512 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 PK |
513 | unsigned int bufsize = mtd->writesize + mtd->oobsize; |
514 | ||
515 | if (len <= 0) { | |
516 | dev_err(priv->dev, "%s: len %d bytes", __func__, len); | |
517 | return; | |
518 | } | |
519 | ||
520 | if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) { | |
521 | dev_err(priv->dev, | |
522 | "%s: beyond end of buffer (%d requested, %u available)\n", | |
523 | __func__, len, bufsize - ifc_nand_ctrl->index); | |
524 | len = bufsize - ifc_nand_ctrl->index; | |
525 | } | |
526 | ||
4454406e | 527 | memcpy_toio(ifc_nand_ctrl->addr + ifc_nand_ctrl->index, buf, len); |
82771882 PK |
528 | ifc_nand_ctrl->index += len; |
529 | } | |
530 | ||
531 | /* | |
532 | * Read a byte from either the IFC hardware buffer | |
533 | * read function for 8-bit buswidth | |
534 | */ | |
7e534323 | 535 | static uint8_t fsl_ifc_read_byte(struct nand_chip *chip) |
82771882 | 536 | { |
d699ed25 | 537 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
4454406e | 538 | unsigned int offset; |
82771882 PK |
539 | |
540 | /* | |
541 | * If there are still bytes in the IFC buffer, then use the | |
542 | * next byte. | |
543 | */ | |
4454406e AS |
544 | if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) { |
545 | offset = ifc_nand_ctrl->index++; | |
cf184dc2 | 546 | return ifc_in8(ifc_nand_ctrl->addr + offset); |
4454406e | 547 | } |
82771882 PK |
548 | |
549 | dev_err(priv->dev, "%s: beyond end of buffer\n", __func__); | |
550 | return ERR_BYTE; | |
551 | } | |
552 | ||
553 | /* | |
554 | * Read two bytes from the IFC hardware buffer | |
555 | * read function for 16-bit buswith | |
556 | */ | |
7e534323 | 557 | static uint8_t fsl_ifc_read_byte16(struct nand_chip *chip) |
82771882 | 558 | { |
d699ed25 | 559 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 PK |
560 | uint16_t data; |
561 | ||
562 | /* | |
563 | * If there are still bytes in the IFC buffer, then use the | |
564 | * next byte. | |
565 | */ | |
566 | if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) { | |
cf184dc2 | 567 | data = ifc_in16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index); |
82771882 PK |
568 | ifc_nand_ctrl->index += 2; |
569 | return (uint8_t) data; | |
570 | } | |
571 | ||
572 | dev_err(priv->dev, "%s: beyond end of buffer\n", __func__); | |
573 | return ERR_BYTE; | |
574 | } | |
575 | ||
576 | /* | |
577 | * Read from the IFC Controller Data Buffer | |
578 | */ | |
7e534323 | 579 | static void fsl_ifc_read_buf(struct nand_chip *chip, u8 *buf, int len) |
82771882 | 580 | { |
d699ed25 | 581 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 PK |
582 | int avail; |
583 | ||
584 | if (len < 0) { | |
585 | dev_err(priv->dev, "%s: len %d bytes", __func__, len); | |
586 | return; | |
587 | } | |
588 | ||
589 | avail = min((unsigned int)len, | |
590 | ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index); | |
4454406e | 591 | memcpy_fromio(buf, ifc_nand_ctrl->addr + ifc_nand_ctrl->index, avail); |
82771882 PK |
592 | ifc_nand_ctrl->index += avail; |
593 | ||
594 | if (len > avail) | |
595 | dev_err(priv->dev, | |
596 | "%s: beyond end of buffer (%d requested, %d available)\n", | |
597 | __func__, len, avail); | |
598 | } | |
599 | ||
82771882 PK |
600 | /* |
601 | * This function is called after Program and Erase Operations to | |
602 | * check for success or failure. | |
603 | */ | |
f1d46942 | 604 | static int fsl_ifc_wait(struct nand_chip *chip) |
82771882 | 605 | { |
f1d46942 | 606 | struct mtd_info *mtd = nand_to_mtd(chip); |
d699ed25 | 607 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 | 608 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; |
7a654172 | 609 | struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs; |
82771882 | 610 | u32 nand_fsr; |
fa8e6d58 | 611 | int status; |
82771882 PK |
612 | |
613 | /* Use READ_STATUS command, but wait for the device to be ready */ | |
cf184dc2 JS |
614 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
615 | (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT), | |
616 | &ifc->ifc_nand.nand_fir0); | |
617 | ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT, | |
618 | &ifc->ifc_nand.nand_fcr0); | |
619 | ifc_out32(1, &ifc->ifc_nand.nand_fbcr); | |
82771882 PK |
620 | set_addr(mtd, 0, 0, 0); |
621 | ifc_nand_ctrl->read_bytes = 1; | |
622 | ||
623 | fsl_ifc_run_command(mtd); | |
624 | ||
cf184dc2 | 625 | nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr); |
fa8e6d58 | 626 | status = nand_fsr >> 24; |
82771882 PK |
627 | /* |
628 | * The chip always seems to report that it is | |
629 | * write-protected, even when it is not. | |
630 | */ | |
fa8e6d58 | 631 | return status | NAND_STATUS_WP; |
82771882 PK |
632 | } |
633 | ||
d45e5316 BB |
634 | /* |
635 | * The controller does not check for bitflips in erased pages, | |
636 | * therefore software must check instead. | |
637 | */ | |
638 | static int check_erased_page(struct nand_chip *chip, u8 *buf) | |
639 | { | |
640 | struct mtd_info *mtd = nand_to_mtd(chip); | |
641 | u8 *ecc = chip->oob_poi; | |
642 | const int ecc_size = chip->ecc.bytes; | |
643 | const int pkt_size = chip->ecc.size; | |
644 | int i, res, bitflips = 0; | |
645 | struct mtd_oob_region oobregion = { }; | |
646 | ||
647 | mtd_ooblayout_ecc(mtd, 0, &oobregion); | |
648 | ecc += oobregion.offset; | |
649 | ||
650 | for (i = 0; i < chip->ecc.steps; ++i) { | |
651 | res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size, | |
652 | NULL, 0, | |
653 | chip->ecc.strength); | |
654 | if (res < 0) | |
655 | mtd->ecc_stats.failed++; | |
656 | else | |
657 | mtd->ecc_stats.corrected += res; | |
658 | ||
659 | bitflips = max(res, bitflips); | |
660 | buf += pkt_size; | |
661 | ecc += ecc_size; | |
662 | } | |
663 | ||
664 | return bitflips; | |
665 | } | |
666 | ||
b9761687 BB |
667 | static int fsl_ifc_read_page(struct nand_chip *chip, uint8_t *buf, |
668 | int oob_required, int page) | |
82771882 | 669 | { |
b9761687 | 670 | struct mtd_info *mtd = nand_to_mtd(chip); |
d699ed25 | 671 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 | 672 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; |
3f91e94f | 673 | struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl; |
82771882 | 674 | |
25f815f6 | 675 | nand_read_page_op(chip, page, 0, buf, mtd->writesize); |
a6976cdf | 676 | if (oob_required) |
7e534323 | 677 | fsl_ifc_read_buf(chip, chip->oob_poi, mtd->oobsize); |
82771882 | 678 | |
d45e5316 BB |
679 | if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER) { |
680 | if (!oob_required) | |
7e534323 | 681 | fsl_ifc_read_buf(chip, chip->oob_poi, mtd->oobsize); |
d45e5316 BB |
682 | |
683 | return check_erased_page(chip, buf); | |
684 | } | |
82771882 PK |
685 | |
686 | if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC) | |
687 | mtd->ecc_stats.failed++; | |
688 | ||
3f91e94f | 689 | return nctrl->max_bitflips; |
82771882 PK |
690 | } |
691 | ||
692 | /* ECC will be calculated automatically, and errors will be detected in | |
693 | * waitfunc. | |
694 | */ | |
767eb6fb BB |
695 | static int fsl_ifc_write_page(struct nand_chip *chip, const uint8_t *buf, |
696 | int oob_required, int page) | |
82771882 | 697 | { |
767eb6fb BB |
698 | struct mtd_info *mtd = nand_to_mtd(chip); |
699 | ||
25f815f6 | 700 | nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize); |
c0739d85 | 701 | fsl_ifc_write_buf(chip, chip->oob_poi, mtd->oobsize); |
fdbad98d | 702 | |
25f815f6 | 703 | return nand_prog_page_end_op(chip); |
82771882 PK |
704 | } |
705 | ||
37b0375d | 706 | static int fsl_ifc_attach_chip(struct nand_chip *chip) |
82771882 | 707 | { |
37b0375d | 708 | struct mtd_info *mtd = nand_to_mtd(chip); |
d699ed25 | 709 | struct fsl_ifc_mtd *priv = nand_get_controller_data(chip); |
82771882 PK |
710 | |
711 | dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__, | |
32813e28 | 712 | nanddev_ntargets(&chip->base)); |
82771882 | 713 | dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__, |
6c836d51 | 714 | nanddev_target_size(&chip->base)); |
82771882 PK |
715 | dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__, |
716 | chip->pagemask); | |
3cece3ab BB |
717 | dev_dbg(priv->dev, "%s: nand->legacy.chip_delay = %d\n", __func__, |
718 | chip->legacy.chip_delay); | |
82771882 PK |
719 | dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__, |
720 | chip->badblockpos); | |
721 | dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__, | |
722 | chip->chip_shift); | |
723 | dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__, | |
724 | chip->page_shift); | |
725 | dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__, | |
726 | chip->phys_erase_shift); | |
82771882 PK |
727 | dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__, |
728 | chip->ecc.mode); | |
729 | dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__, | |
730 | chip->ecc.steps); | |
731 | dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__, | |
732 | chip->ecc.bytes); | |
733 | dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__, | |
734 | chip->ecc.total); | |
caf5129e BB |
735 | dev_dbg(priv->dev, "%s: mtd->ooblayout = %p\n", __func__, |
736 | mtd->ooblayout); | |
82771882 PK |
737 | dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags); |
738 | dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size); | |
739 | dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__, | |
740 | mtd->erasesize); | |
741 | dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__, | |
742 | mtd->writesize); | |
743 | dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__, | |
744 | mtd->oobsize); | |
745 | ||
746 | return 0; | |
747 | } | |
748 | ||
37b0375d MR |
749 | static const struct nand_controller_ops fsl_ifc_controller_ops = { |
750 | .attach_chip = fsl_ifc_attach_chip, | |
751 | }; | |
752 | ||
434655af | 753 | static int fsl_ifc_sram_init(struct fsl_ifc_mtd *priv) |
10bfa766 PK |
754 | { |
755 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; | |
7a654172 RD |
756 | struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs; |
757 | struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs; | |
10bfa766 PK |
758 | uint32_t csor = 0, csor_8k = 0, csor_ext = 0; |
759 | uint32_t cs = priv->bank; | |
760 | ||
ff8648f2 KK |
761 | if (ctrl->version < FSL_IFC_VERSION_1_1_0) |
762 | return 0; | |
763 | ||
764 | if (ctrl->version > FSL_IFC_VERSION_1_1_0) { | |
765 | u32 ncfgr, status; | |
766 | int ret; | |
767 | ||
768 | /* Trigger auto initialization */ | |
769 | ncfgr = ifc_in32(&ifc_runtime->ifc_nand.ncfgr); | |
770 | ifc_out32(ncfgr | IFC_NAND_NCFGR_SRAM_INIT_EN, &ifc_runtime->ifc_nand.ncfgr); | |
771 | ||
772 | /* Wait until done */ | |
773 | ret = readx_poll_timeout(ifc_in32, &ifc_runtime->ifc_nand.ncfgr, | |
774 | status, !(status & IFC_NAND_NCFGR_SRAM_INIT_EN), | |
775 | 10, IFC_TIMEOUT_MSECS * 1000); | |
776 | if (ret) | |
777 | dev_err(priv->dev, "Failed to initialize SRAM!\n"); | |
778 | ||
779 | return ret; | |
780 | } | |
781 | ||
10bfa766 | 782 | /* Save CSOR and CSOR_ext */ |
7a654172 RD |
783 | csor = ifc_in32(&ifc_global->csor_cs[cs].csor); |
784 | csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext); | |
10bfa766 PK |
785 | |
786 | /* chage PageSize 8K and SpareSize 1K*/ | |
787 | csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000; | |
7a654172 RD |
788 | ifc_out32(csor_8k, &ifc_global->csor_cs[cs].csor); |
789 | ifc_out32(0x0000400, &ifc_global->csor_cs[cs].csor_ext); | |
10bfa766 PK |
790 | |
791 | /* READID */ | |
cf184dc2 | 792 | ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | |
7a654172 RD |
793 | (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | |
794 | (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT), | |
795 | &ifc_runtime->ifc_nand.nand_fir0); | |
cf184dc2 | 796 | ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT, |
7a654172 RD |
797 | &ifc_runtime->ifc_nand.nand_fcr0); |
798 | ifc_out32(0x0, &ifc_runtime->ifc_nand.row3); | |
10bfa766 | 799 | |
7a654172 | 800 | ifc_out32(0x0, &ifc_runtime->ifc_nand.nand_fbcr); |
10bfa766 PK |
801 | |
802 | /* Program ROW0/COL0 */ | |
7a654172 RD |
803 | ifc_out32(0x0, &ifc_runtime->ifc_nand.row0); |
804 | ifc_out32(0x0, &ifc_runtime->ifc_nand.col0); | |
10bfa766 PK |
805 | |
806 | /* set the chip select for NAND Transaction */ | |
7a654172 RD |
807 | ifc_out32(cs << IFC_NAND_CSEL_SHIFT, |
808 | &ifc_runtime->ifc_nand.nand_csel); | |
10bfa766 PK |
809 | |
810 | /* start read seq */ | |
7a654172 RD |
811 | ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, |
812 | &ifc_runtime->ifc_nand.nandseq_strt); | |
10bfa766 PK |
813 | |
814 | /* wait for command complete flag or timeout */ | |
815 | wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat, | |
95d70665 | 816 | msecs_to_jiffies(IFC_TIMEOUT_MSECS)); |
10bfa766 | 817 | |
434655af | 818 | if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC) { |
63fa37f0 | 819 | pr_err("fsl-ifc: Failed to Initialise SRAM\n"); |
434655af KK |
820 | return -ETIMEDOUT; |
821 | } | |
10bfa766 PK |
822 | |
823 | /* Restore CSOR and CSOR_ext */ | |
7a654172 RD |
824 | ifc_out32(csor, &ifc_global->csor_cs[cs].csor); |
825 | ifc_out32(csor_ext, &ifc_global->csor_cs[cs].csor_ext); | |
434655af KK |
826 | |
827 | return 0; | |
10bfa766 PK |
828 | } |
829 | ||
82771882 PK |
830 | static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) |
831 | { | |
832 | struct fsl_ifc_ctrl *ctrl = priv->ctrl; | |
7a654172 RD |
833 | struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs; |
834 | struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs; | |
82771882 | 835 | struct nand_chip *chip = &priv->chip; |
5e9fb93d | 836 | struct mtd_info *mtd = nand_to_mtd(&priv->chip); |
09691661 | 837 | u32 csor; |
ff8648f2 | 838 | int ret; |
82771882 PK |
839 | |
840 | /* Fill in fsl_ifc_mtd structure */ | |
5e9fb93d | 841 | mtd->dev.parent = priv->dev; |
a61ae81a | 842 | nand_set_flash_node(chip, priv->dev->of_node); |
82771882 PK |
843 | |
844 | /* fill in nand_chip structure */ | |
845 | /* set up function call table */ | |
7a654172 RD |
846 | if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)) |
847 | & CSPR_PORT_SIZE_16) | |
716bbbab | 848 | chip->legacy.read_byte = fsl_ifc_read_byte16; |
82771882 | 849 | else |
716bbbab | 850 | chip->legacy.read_byte = fsl_ifc_read_byte; |
82771882 | 851 | |
716bbbab BB |
852 | chip->legacy.write_buf = fsl_ifc_write_buf; |
853 | chip->legacy.read_buf = fsl_ifc_read_buf; | |
7d6c37e9 | 854 | chip->legacy.select_chip = fsl_ifc_select_chip; |
bf6065c6 | 855 | chip->legacy.cmdfunc = fsl_ifc_cmdfunc; |
8395b753 | 856 | chip->legacy.waitfunc = fsl_ifc_wait; |
45240367 BB |
857 | chip->legacy.set_features = nand_get_set_features_notsupp; |
858 | chip->legacy.get_features = nand_get_set_features_notsupp; | |
82771882 PK |
859 | |
860 | chip->bbt_td = &bbt_main_descr; | |
861 | chip->bbt_md = &bbt_mirror_descr; | |
862 | ||
7a654172 | 863 | ifc_out32(0x0, &ifc_runtime->ifc_nand.ncfgr); |
82771882 PK |
864 | |
865 | /* set up nand options */ | |
82771882 | 866 | chip->bbt_options = NAND_BBT_USE_FLASH; |
20cd0008 | 867 | chip->options = NAND_NO_SUBPAGE_WRITE; |
82771882 | 868 | |
7a654172 RD |
869 | if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr) |
870 | & CSPR_PORT_SIZE_16) { | |
716bbbab | 871 | chip->legacy.read_byte = fsl_ifc_read_byte16; |
82771882 PK |
872 | chip->options |= NAND_BUSWIDTH_16; |
873 | } else { | |
716bbbab | 874 | chip->legacy.read_byte = fsl_ifc_read_byte; |
82771882 PK |
875 | } |
876 | ||
877 | chip->controller = &ifc_nand_ctrl->controller; | |
d699ed25 | 878 | nand_set_controller_data(chip, priv); |
82771882 PK |
879 | |
880 | chip->ecc.read_page = fsl_ifc_read_page; | |
881 | chip->ecc.write_page = fsl_ifc_write_page; | |
882 | ||
7a654172 | 883 | csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor); |
82771882 | 884 | |
82771882 PK |
885 | switch (csor & CSOR_NAND_PGS_MASK) { |
886 | case CSOR_NAND_PGS_512: | |
caf5129e | 887 | if (!(chip->options & NAND_BUSWIDTH_16)) { |
82771882 PK |
888 | /* Avoid conflict with bad block marker */ |
889 | bbt_main_descr.offs = 0; | |
890 | bbt_mirror_descr.offs = 0; | |
891 | } | |
892 | ||
893 | priv->bufnum_mask = 15; | |
894 | break; | |
895 | ||
896 | case CSOR_NAND_PGS_2K: | |
82771882 PK |
897 | priv->bufnum_mask = 3; |
898 | break; | |
899 | ||
900 | case CSOR_NAND_PGS_4K: | |
82771882 PK |
901 | priv->bufnum_mask = 1; |
902 | break; | |
903 | ||
ebff90b2 | 904 | case CSOR_NAND_PGS_8K: |
ebff90b2 | 905 | priv->bufnum_mask = 0; |
caf5129e | 906 | break; |
ebff90b2 | 907 | |
82771882 PK |
908 | default: |
909 | dev_err(priv->dev, "bad csor %#x: bad page size\n", csor); | |
910 | return -ENODEV; | |
911 | } | |
912 | ||
913 | /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */ | |
914 | if (csor & CSOR_NAND_ECC_DEC_EN) { | |
915 | chip->ecc.mode = NAND_ECC_HW; | |
caf5129e BB |
916 | mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops); |
917 | ||
918 | /* Hardware generates ECC per 512 Bytes */ | |
919 | chip->ecc.size = 512; | |
920 | if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) { | |
921 | chip->ecc.bytes = 8; | |
922 | chip->ecc.strength = 4; | |
923 | } else { | |
924 | chip->ecc.bytes = 16; | |
925 | chip->ecc.strength = 8; | |
926 | } | |
82771882 PK |
927 | } else { |
928 | chip->ecc.mode = NAND_ECC_SOFT; | |
ff1ef350 | 929 | chip->ecc.algo = NAND_ECC_HAMMING; |
82771882 PK |
930 | } |
931 | ||
ff8648f2 KK |
932 | ret = fsl_ifc_sram_init(priv); |
933 | if (ret) | |
934 | return ret; | |
10bfa766 | 935 | |
bccb06c3 JG |
936 | /* |
937 | * As IFC version 2.0.0 has 16KB of internal SRAM as compared to older | |
938 | * versions which had 8KB. Hence bufnum mask needs to be updated. | |
939 | */ | |
940 | if (ctrl->version >= FSL_IFC_VERSION_2_0_0) | |
941 | priv->bufnum_mask = (priv->bufnum_mask * 2) + 1; | |
942 | ||
82771882 PK |
943 | return 0; |
944 | } | |
945 | ||
946 | static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv) | |
947 | { | |
5e9fb93d | 948 | struct mtd_info *mtd = nand_to_mtd(&priv->chip); |
82771882 | 949 | |
5e9fb93d | 950 | kfree(mtd->name); |
82771882 PK |
951 | |
952 | if (priv->vbase) | |
953 | iounmap(priv->vbase); | |
954 | ||
955 | ifc_nand_ctrl->chips[priv->bank] = NULL; | |
82771882 PK |
956 | |
957 | return 0; | |
958 | } | |
959 | ||
7a654172 | 960 | static int match_bank(struct fsl_ifc_global __iomem *ifc_global, int bank, |
82771882 PK |
961 | phys_addr_t addr) |
962 | { | |
7a654172 | 963 | u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr); |
82771882 PK |
964 | |
965 | if (!(cspr & CSPR_V)) | |
966 | return 0; | |
967 | if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND) | |
968 | return 0; | |
969 | ||
970 | return (cspr & CSPR_BA) == convert_ifc_address(addr); | |
971 | } | |
972 | ||
973 | static DEFINE_MUTEX(fsl_ifc_nand_mutex); | |
974 | ||
06f25510 | 975 | static int fsl_ifc_nand_probe(struct platform_device *dev) |
82771882 | 976 | { |
7a654172 | 977 | struct fsl_ifc_runtime __iomem *ifc; |
82771882 PK |
978 | struct fsl_ifc_mtd *priv; |
979 | struct resource res; | |
980 | static const char *part_probe_types[] | |
981 | = { "cmdlinepart", "RedBoot", "ofpart", NULL }; | |
982 | int ret; | |
983 | int bank; | |
984 | struct device_node *node = dev->dev.of_node; | |
5e9fb93d | 985 | struct mtd_info *mtd; |
82771882 | 986 | |
7a654172 | 987 | if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->rregs) |
82771882 | 988 | return -ENODEV; |
7a654172 | 989 | ifc = fsl_ifc_ctrl_dev->rregs; |
82771882 PK |
990 | |
991 | /* get, allocate and map the memory resource */ | |
992 | ret = of_address_to_resource(node, 0, &res); | |
993 | if (ret) { | |
994 | dev_err(&dev->dev, "%s: failed to get resource\n", __func__); | |
995 | return ret; | |
996 | } | |
997 | ||
998 | /* find which chip select it is connected to */ | |
09691661 | 999 | for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) { |
7a654172 | 1000 | if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start)) |
82771882 PK |
1001 | break; |
1002 | } | |
1003 | ||
09691661 | 1004 | if (bank >= fsl_ifc_ctrl_dev->banks) { |
82771882 PK |
1005 | dev_err(&dev->dev, "%s: address did not match any chip selects\n", |
1006 | __func__); | |
1007 | return -ENODEV; | |
1008 | } | |
1009 | ||
1010 | priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); | |
1011 | if (!priv) | |
1012 | return -ENOMEM; | |
1013 | ||
1014 | mutex_lock(&fsl_ifc_nand_mutex); | |
1015 | if (!fsl_ifc_ctrl_dev->nand) { | |
1016 | ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL); | |
1017 | if (!ifc_nand_ctrl) { | |
82771882 PK |
1018 | mutex_unlock(&fsl_ifc_nand_mutex); |
1019 | return -ENOMEM; | |
1020 | } | |
1021 | ||
1022 | ifc_nand_ctrl->read_bytes = 0; | |
1023 | ifc_nand_ctrl->index = 0; | |
1024 | ifc_nand_ctrl->addr = NULL; | |
1025 | fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl; | |
1026 | ||
7da45139 | 1027 | nand_controller_init(&ifc_nand_ctrl->controller); |
82771882 PK |
1028 | } else { |
1029 | ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand; | |
1030 | } | |
1031 | mutex_unlock(&fsl_ifc_nand_mutex); | |
1032 | ||
1033 | ifc_nand_ctrl->chips[bank] = priv; | |
1034 | priv->bank = bank; | |
1035 | priv->ctrl = fsl_ifc_ctrl_dev; | |
1036 | priv->dev = &dev->dev; | |
1037 | ||
1038 | priv->vbase = ioremap(res.start, resource_size(&res)); | |
1039 | if (!priv->vbase) { | |
1040 | dev_err(priv->dev, "%s: failed to map chip region\n", __func__); | |
1041 | ret = -ENOMEM; | |
1042 | goto err; | |
1043 | } | |
1044 | ||
1045 | dev_set_drvdata(priv->dev, priv); | |
1046 | ||
cf184dc2 JS |
1047 | ifc_out32(IFC_NAND_EVTER_EN_OPC_EN | |
1048 | IFC_NAND_EVTER_EN_FTOER_EN | | |
1049 | IFC_NAND_EVTER_EN_WPER_EN, | |
1050 | &ifc->ifc_nand.nand_evter_en); | |
82771882 PK |
1051 | |
1052 | /* enable NAND Machine Interrupts */ | |
cf184dc2 JS |
1053 | ifc_out32(IFC_NAND_EVTER_INTR_OPCIR_EN | |
1054 | IFC_NAND_EVTER_INTR_FTOERIR_EN | | |
1055 | IFC_NAND_EVTER_INTR_WPERIR_EN, | |
1056 | &ifc->ifc_nand.nand_evter_intr_en); | |
5e9fb93d BB |
1057 | |
1058 | mtd = nand_to_mtd(&priv->chip); | |
1059 | mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start); | |
1060 | if (!mtd->name) { | |
82771882 PK |
1061 | ret = -ENOMEM; |
1062 | goto err; | |
1063 | } | |
1064 | ||
1065 | ret = fsl_ifc_chip_init(priv); | |
1066 | if (ret) | |
1067 | goto err; | |
1068 | ||
37b0375d | 1069 | priv->chip.controller->ops = &fsl_ifc_controller_ops; |
00ad378f | 1070 | ret = nand_scan(&priv->chip, 1); |
82771882 PK |
1071 | if (ret) |
1072 | goto err; | |
1073 | ||
1074 | /* First look for RedBoot table or partitions on the command | |
1075 | * line, these take precedence over device tree information */ | |
acfc3309 MR |
1076 | ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0); |
1077 | if (ret) | |
1078 | goto cleanup_nand; | |
82771882 PK |
1079 | |
1080 | dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n", | |
1081 | (unsigned long long)res.start, priv->bank); | |
acfc3309 | 1082 | |
82771882 PK |
1083 | return 0; |
1084 | ||
acfc3309 MR |
1085 | cleanup_nand: |
1086 | nand_cleanup(&priv->chip); | |
82771882 PK |
1087 | err: |
1088 | fsl_ifc_chip_remove(priv); | |
acfc3309 | 1089 | |
82771882 PK |
1090 | return ret; |
1091 | } | |
1092 | ||
1093 | static int fsl_ifc_nand_remove(struct platform_device *dev) | |
1094 | { | |
1095 | struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev); | |
1096 | ||
59ac276f | 1097 | nand_release(&priv->chip); |
82771882 PK |
1098 | fsl_ifc_chip_remove(priv); |
1099 | ||
1100 | mutex_lock(&fsl_ifc_nand_mutex); | |
1101 | ifc_nand_ctrl->counter--; | |
1102 | if (!ifc_nand_ctrl->counter) { | |
1103 | fsl_ifc_ctrl_dev->nand = NULL; | |
1104 | kfree(ifc_nand_ctrl); | |
1105 | } | |
1106 | mutex_unlock(&fsl_ifc_nand_mutex); | |
1107 | ||
1108 | return 0; | |
1109 | } | |
1110 | ||
1111 | static const struct of_device_id fsl_ifc_nand_match[] = { | |
1112 | { | |
1113 | .compatible = "fsl,ifc-nand", | |
1114 | }, | |
1115 | {} | |
1116 | }; | |
3f7f7a5f | 1117 | MODULE_DEVICE_TABLE(of, fsl_ifc_nand_match); |
82771882 PK |
1118 | |
1119 | static struct platform_driver fsl_ifc_nand_driver = { | |
1120 | .driver = { | |
1121 | .name = "fsl,ifc-nand", | |
82771882 PK |
1122 | .of_match_table = fsl_ifc_nand_match, |
1123 | }, | |
1124 | .probe = fsl_ifc_nand_probe, | |
1125 | .remove = fsl_ifc_nand_remove, | |
1126 | }; | |
1127 | ||
c69ad0ef | 1128 | module_platform_driver(fsl_ifc_nand_driver); |
82771882 PK |
1129 | |
1130 | MODULE_LICENSE("GPL"); | |
1131 | MODULE_AUTHOR("Freescale"); | |
1132 | MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver"); |