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bb696344 | 1 | // SPDX-License-Identifier: GPL-2.0 |
6c009ab8 | 2 | /* |
6c009ab8 LW |
3 | * ST Microelectronics |
4 | * Flexible Static Memory Controller (FSMC) | |
5 | * Driver for NAND portions | |
6 | * | |
7 | * Copyright © 2010 ST Microelectronics | |
8 | * Vipin Kumar <vipin.kumar@st.com> | |
9 | * Ashish Priyadarshi | |
10 | * | |
187c5448 | 11 | * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8) |
7b6afee7 BB |
12 | * Copyright © 2007 STMicroelectronics Pvt. Ltd. |
13 | * Copyright © 2009 Alessandro Rubini | |
6c009ab8 LW |
14 | */ |
15 | ||
16 | #include <linux/clk.h> | |
4774fb0a VK |
17 | #include <linux/completion.h> |
18 | #include <linux/dmaengine.h> | |
19 | #include <linux/dma-direction.h> | |
20 | #include <linux/dma-mapping.h> | |
6c009ab8 LW |
21 | #include <linux/err.h> |
22 | #include <linux/init.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/resource.h> | |
25 | #include <linux/sched.h> | |
26 | #include <linux/types.h> | |
27 | #include <linux/mtd/mtd.h> | |
d4092d76 | 28 | #include <linux/mtd/rawnand.h> |
6c009ab8 LW |
29 | #include <linux/mtd/nand_ecc.h> |
30 | #include <linux/platform_device.h> | |
eea62819 | 31 | #include <linux/of.h> |
6c009ab8 LW |
32 | #include <linux/mtd/partitions.h> |
33 | #include <linux/io.h> | |
34 | #include <linux/slab.h> | |
593cd871 | 35 | #include <linux/amba/bus.h> |
6c009ab8 LW |
36 | #include <mtd/mtd-abi.h> |
37 | ||
4404d7d8 LW |
38 | /* fsmc controller registers for NOR flash */ |
39 | #define CTRL 0x0 | |
40 | /* ctrl register definitions */ | |
fc43f45e BB |
41 | #define BANK_ENABLE BIT(0) |
42 | #define MUXED BIT(1) | |
4404d7d8 | 43 | #define NOR_DEV (2 << 2) |
fc43f45e BB |
44 | #define WIDTH_16 BIT(4) |
45 | #define RSTPWRDWN BIT(6) | |
46 | #define WPROT BIT(7) | |
47 | #define WRT_ENABLE BIT(12) | |
48 | #define WAIT_ENB BIT(13) | |
4404d7d8 LW |
49 | |
50 | #define CTRL_TIM 0x4 | |
51 | /* ctrl_tim register definitions */ | |
52 | ||
53 | #define FSMC_NOR_BANK_SZ 0x8 | |
54 | #define FSMC_NOR_REG_SIZE 0x40 | |
55 | ||
fc43f45e BB |
56 | #define FSMC_NOR_REG(base, bank, reg) ((base) + \ |
57 | (FSMC_NOR_BANK_SZ * (bank)) + \ | |
58 | (reg)) | |
4404d7d8 LW |
59 | |
60 | /* fsmc controller registers for NAND flash */ | |
8f3931ed | 61 | #define FSMC_PC 0x00 |
4404d7d8 | 62 | /* pc register definitions */ |
fc43f45e BB |
63 | #define FSMC_RESET BIT(0) |
64 | #define FSMC_WAITON BIT(1) | |
65 | #define FSMC_ENABLE BIT(2) | |
66 | #define FSMC_DEVTYPE_NAND BIT(3) | |
67 | #define FSMC_DEVWID_16 BIT(4) | |
68 | #define FSMC_ECCEN BIT(6) | |
69 | #define FSMC_ECCPLEN_256 BIT(7) | |
4404d7d8 LW |
70 | #define FSMC_TCLR_SHIFT (9) |
71 | #define FSMC_TCLR_MASK (0xF) | |
4404d7d8 LW |
72 | #define FSMC_TAR_SHIFT (13) |
73 | #define FSMC_TAR_MASK (0xF) | |
74 | #define STS 0x04 | |
75 | /* sts register definitions */ | |
fc43f45e | 76 | #define FSMC_CODE_RDY BIT(15) |
4404d7d8 LW |
77 | #define COMM 0x08 |
78 | /* comm register definitions */ | |
4404d7d8 LW |
79 | #define FSMC_TSET_SHIFT 0 |
80 | #define FSMC_TSET_MASK 0xFF | |
4404d7d8 LW |
81 | #define FSMC_TWAIT_SHIFT 8 |
82 | #define FSMC_TWAIT_MASK 0xFF | |
4404d7d8 LW |
83 | #define FSMC_THOLD_SHIFT 16 |
84 | #define FSMC_THOLD_MASK 0xFF | |
4404d7d8 LW |
85 | #define FSMC_THIZ_SHIFT 24 |
86 | #define FSMC_THIZ_MASK 0xFF | |
87 | #define ATTRIB 0x0C | |
88 | #define IOATA 0x10 | |
89 | #define ECC1 0x14 | |
90 | #define ECC2 0x18 | |
91 | #define ECC3 0x1C | |
92 | #define FSMC_NAND_BANK_SZ 0x20 | |
93 | ||
4404d7d8 LW |
94 | #define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ) |
95 | ||
96 | struct fsmc_nand_timings { | |
fc43f45e BB |
97 | u8 tclr; |
98 | u8 tar; | |
99 | u8 thiz; | |
100 | u8 thold; | |
101 | u8 twait; | |
102 | u8 tset; | |
4404d7d8 LW |
103 | }; |
104 | ||
105 | enum access_mode { | |
106 | USE_DMA_ACCESS = 1, | |
107 | USE_WORD_ACCESS, | |
108 | }; | |
109 | ||
e7cda017 TP |
110 | /** |
111 | * struct fsmc_nand_data - structure for FSMC NAND device state | |
112 | * | |
ad71148c | 113 | * @base: Inherit from the nand_controller struct |
e7cda017 | 114 | * @pid: Part ID on the AMBA PrimeCell format |
e7cda017 | 115 | * @nand: Chip related info for a NAND flash. |
e7cda017 TP |
116 | * |
117 | * @bank: Bank number for probed device. | |
5b47f407 BB |
118 | * @dev: Parent device |
119 | * @mode: Access mode | |
e7cda017 TP |
120 | * @clk: Clock structure for FSMC. |
121 | * | |
122 | * @read_dma_chan: DMA channel for read access | |
123 | * @write_dma_chan: DMA channel for write access to NAND | |
124 | * @dma_access_complete: Completion structure | |
125 | * | |
5b47f407 BB |
126 | * @dev_timings: NAND timings |
127 | * | |
e7cda017 TP |
128 | * @data_pa: NAND Physical port for Data. |
129 | * @data_va: NAND port for Data. | |
130 | * @cmd_va: NAND port for Command. | |
131 | * @addr_va: NAND port for Address. | |
4df6ed4f | 132 | * @regs_va: Registers base address for a given bank. |
e7cda017 TP |
133 | */ |
134 | struct fsmc_nand_data { | |
ad71148c | 135 | struct nand_controller base; |
e7cda017 TP |
136 | u32 pid; |
137 | struct nand_chip nand; | |
e7cda017 TP |
138 | |
139 | unsigned int bank; | |
140 | struct device *dev; | |
141 | enum access_mode mode; | |
142 | struct clk *clk; | |
143 | ||
144 | /* DMA related objects */ | |
145 | struct dma_chan *read_dma_chan; | |
146 | struct dma_chan *write_dma_chan; | |
147 | struct completion dma_access_complete; | |
148 | ||
149 | struct fsmc_nand_timings *dev_timings; | |
150 | ||
151 | dma_addr_t data_pa; | |
152 | void __iomem *data_va; | |
153 | void __iomem *cmd_va; | |
154 | void __iomem *addr_va; | |
155 | void __iomem *regs_va; | |
e7cda017 TP |
156 | }; |
157 | ||
22b46957 BB |
158 | static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section, |
159 | struct mtd_oob_region *oobregion) | |
160 | { | |
161 | struct nand_chip *chip = mtd_to_nand(mtd); | |
162 | ||
163 | if (section >= chip->ecc.steps) | |
164 | return -ERANGE; | |
165 | ||
166 | oobregion->offset = (section * 16) + 2; | |
167 | oobregion->length = 3; | |
168 | ||
169 | return 0; | |
170 | } | |
171 | ||
172 | static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section, | |
173 | struct mtd_oob_region *oobregion) | |
174 | { | |
175 | struct nand_chip *chip = mtd_to_nand(mtd); | |
176 | ||
177 | if (section >= chip->ecc.steps) | |
178 | return -ERANGE; | |
179 | ||
180 | oobregion->offset = (section * 16) + 8; | |
181 | ||
182 | if (section < chip->ecc.steps - 1) | |
183 | oobregion->length = 8; | |
184 | else | |
185 | oobregion->length = mtd->oobsize - oobregion->offset; | |
186 | ||
187 | return 0; | |
188 | } | |
189 | ||
190 | static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = { | |
191 | .ecc = fsmc_ecc1_ooblayout_ecc, | |
192 | .free = fsmc_ecc1_ooblayout_free, | |
193 | }; | |
194 | ||
04a123a9 BB |
195 | /* |
196 | * ECC placement definitions in oobfree type format. | |
197 | * There are 13 bytes of ecc for every 512 byte block and it has to be read | |
198 | * consecutively and immediately after the 512 byte data block for hardware to | |
199 | * generate the error bit offsets in 512 byte data. | |
200 | */ | |
22b46957 BB |
201 | static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section, |
202 | struct mtd_oob_region *oobregion) | |
203 | { | |
204 | struct nand_chip *chip = mtd_to_nand(mtd); | |
205 | ||
206 | if (section >= chip->ecc.steps) | |
207 | return -ERANGE; | |
208 | ||
209 | oobregion->length = chip->ecc.bytes; | |
210 | ||
211 | if (!section && mtd->writesize <= 512) | |
212 | oobregion->offset = 0; | |
213 | else | |
214 | oobregion->offset = (section * 16) + 2; | |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
219 | static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section, | |
220 | struct mtd_oob_region *oobregion) | |
221 | { | |
222 | struct nand_chip *chip = mtd_to_nand(mtd); | |
223 | ||
224 | if (section >= chip->ecc.steps) | |
225 | return -ERANGE; | |
226 | ||
227 | oobregion->offset = (section * 16) + 15; | |
228 | ||
229 | if (section < chip->ecc.steps - 1) | |
230 | oobregion->length = 3; | |
231 | else | |
232 | oobregion->length = mtd->oobsize - oobregion->offset; | |
233 | ||
234 | return 0; | |
235 | } | |
236 | ||
237 | static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = { | |
238 | .ecc = fsmc_ecc4_ooblayout_ecc, | |
239 | .free = fsmc_ecc4_ooblayout_free, | |
240 | }; | |
241 | ||
bfc535f4 | 242 | static inline struct fsmc_nand_data *nand_to_fsmc(struct nand_chip *chip) |
277af429 | 243 | { |
bfc535f4 | 244 | return container_of(chip, struct fsmc_nand_data, nand); |
277af429 BB |
245 | } |
246 | ||
6c009ab8 LW |
247 | /* |
248 | * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine | |
249 | * | |
250 | * This routine initializes timing parameters related to NAND memory access in | |
251 | * FSMC registers | |
252 | */ | |
6335b509 | 253 | static void fsmc_nand_setup(struct fsmc_nand_data *host, |
1debdb96 | 254 | struct fsmc_nand_timings *tims) |
6c009ab8 | 255 | { |
fc43f45e BB |
256 | u32 value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON; |
257 | u32 tclr, tar, thiz, thold, twait, tset; | |
e2f6bce8 VK |
258 | |
259 | tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT; | |
260 | tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT; | |
261 | thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT; | |
262 | thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT; | |
263 | twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT; | |
264 | tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT; | |
6c009ab8 | 265 | |
6335b509 | 266 | if (host->nand.options & NAND_BUSWIDTH_16) |
fc43f45e | 267 | value |= FSMC_DEVWID_16; |
4df6ed4f | 268 | |
fc43f45e | 269 | writel_relaxed(value | tclr | tar, host->regs_va + FSMC_PC); |
4df6ed4f MR |
270 | writel_relaxed(thiz | thold | twait | tset, host->regs_va + COMM); |
271 | writel_relaxed(thiz | thold | twait | tset, host->regs_va + ATTRIB); | |
6c009ab8 LW |
272 | } |
273 | ||
d9fb0795 TP |
274 | static int fsmc_calc_timings(struct fsmc_nand_data *host, |
275 | const struct nand_sdr_timings *sdrt, | |
276 | struct fsmc_nand_timings *tims) | |
277 | { | |
278 | unsigned long hclk = clk_get_rate(host->clk); | |
279 | unsigned long hclkn = NSEC_PER_SEC / hclk; | |
fc43f45e | 280 | u32 thiz, thold, twait, tset; |
d9fb0795 TP |
281 | |
282 | if (sdrt->tRC_min < 30000) | |
283 | return -EOPNOTSUPP; | |
284 | ||
285 | tims->tar = DIV_ROUND_UP(sdrt->tAR_min / 1000, hclkn) - 1; | |
286 | if (tims->tar > FSMC_TAR_MASK) | |
287 | tims->tar = FSMC_TAR_MASK; | |
288 | tims->tclr = DIV_ROUND_UP(sdrt->tCLR_min / 1000, hclkn) - 1; | |
289 | if (tims->tclr > FSMC_TCLR_MASK) | |
290 | tims->tclr = FSMC_TCLR_MASK; | |
291 | ||
292 | thiz = sdrt->tCS_min - sdrt->tWP_min; | |
293 | tims->thiz = DIV_ROUND_UP(thiz / 1000, hclkn); | |
294 | ||
295 | thold = sdrt->tDH_min; | |
296 | if (thold < sdrt->tCH_min) | |
297 | thold = sdrt->tCH_min; | |
298 | if (thold < sdrt->tCLH_min) | |
299 | thold = sdrt->tCLH_min; | |
300 | if (thold < sdrt->tWH_min) | |
301 | thold = sdrt->tWH_min; | |
302 | if (thold < sdrt->tALH_min) | |
303 | thold = sdrt->tALH_min; | |
304 | if (thold < sdrt->tREH_min) | |
305 | thold = sdrt->tREH_min; | |
306 | tims->thold = DIV_ROUND_UP(thold / 1000, hclkn); | |
307 | if (tims->thold == 0) | |
308 | tims->thold = 1; | |
309 | else if (tims->thold > FSMC_THOLD_MASK) | |
310 | tims->thold = FSMC_THOLD_MASK; | |
311 | ||
312 | twait = max(sdrt->tRP_min, sdrt->tWP_min); | |
313 | tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1; | |
314 | if (tims->twait == 0) | |
315 | tims->twait = 1; | |
316 | else if (tims->twait > FSMC_TWAIT_MASK) | |
317 | tims->twait = FSMC_TWAIT_MASK; | |
318 | ||
319 | tset = max(sdrt->tCS_min - sdrt->tWP_min, | |
320 | sdrt->tCEA_max - sdrt->tREA_max); | |
321 | tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1; | |
322 | if (tims->tset == 0) | |
323 | tims->tset = 1; | |
324 | else if (tims->tset > FSMC_TSET_MASK) | |
325 | tims->tset = FSMC_TSET_MASK; | |
326 | ||
327 | return 0; | |
328 | } | |
329 | ||
858838b8 | 330 | static int fsmc_setup_data_interface(struct nand_chip *nand, int csline, |
104e442a | 331 | const struct nand_data_interface *conf) |
d9fb0795 | 332 | { |
1e809f7e | 333 | struct fsmc_nand_data *host = nand_to_fsmc(nand); |
d9fb0795 TP |
334 | struct fsmc_nand_timings tims; |
335 | const struct nand_sdr_timings *sdrt; | |
336 | int ret; | |
337 | ||
338 | sdrt = nand_get_sdr_timings(conf); | |
339 | if (IS_ERR(sdrt)) | |
340 | return PTR_ERR(sdrt); | |
341 | ||
342 | ret = fsmc_calc_timings(host, sdrt, &tims); | |
343 | if (ret) | |
344 | return ret; | |
345 | ||
104e442a | 346 | if (csline == NAND_DATA_IFACE_CHECK_ONLY) |
d9fb0795 TP |
347 | return 0; |
348 | ||
349 | fsmc_nand_setup(host, &tims); | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
6c009ab8 LW |
354 | /* |
355 | * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers | |
356 | */ | |
ec47636c | 357 | static void fsmc_enable_hwecc(struct nand_chip *chip, int mode) |
6c009ab8 | 358 | { |
bfc535f4 | 359 | struct fsmc_nand_data *host = nand_to_fsmc(chip); |
4df6ed4f | 360 | |
8f3931ed BB |
361 | writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCPLEN_256, |
362 | host->regs_va + FSMC_PC); | |
363 | writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCEN, | |
364 | host->regs_va + FSMC_PC); | |
365 | writel_relaxed(readl(host->regs_va + FSMC_PC) | FSMC_ECCEN, | |
366 | host->regs_va + FSMC_PC); | |
6c009ab8 LW |
367 | } |
368 | ||
369 | /* | |
370 | * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by | |
25985edc | 371 | * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to |
6c009ab8 LW |
372 | * max of 8-bits) |
373 | */ | |
fc43f45e BB |
374 | static int fsmc_read_hwecc_ecc4(struct nand_chip *chip, const u8 *data, |
375 | u8 *ecc) | |
6c009ab8 | 376 | { |
bfc535f4 | 377 | struct fsmc_nand_data *host = nand_to_fsmc(chip); |
fc43f45e | 378 | u32 ecc_tmp; |
6c009ab8 LW |
379 | unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT; |
380 | ||
381 | do { | |
4df6ed4f | 382 | if (readl_relaxed(host->regs_va + STS) & FSMC_CODE_RDY) |
6c009ab8 | 383 | break; |
fc43f45e BB |
384 | |
385 | cond_resched(); | |
6c009ab8 LW |
386 | } while (!time_after_eq(jiffies, deadline)); |
387 | ||
712c4add VK |
388 | if (time_after_eq(jiffies, deadline)) { |
389 | dev_err(host->dev, "calculate ecc timed out\n"); | |
390 | return -ETIMEDOUT; | |
391 | } | |
392 | ||
4df6ed4f | 393 | ecc_tmp = readl_relaxed(host->regs_va + ECC1); |
fc43f45e BB |
394 | ecc[0] = ecc_tmp; |
395 | ecc[1] = ecc_tmp >> 8; | |
396 | ecc[2] = ecc_tmp >> 16; | |
397 | ecc[3] = ecc_tmp >> 24; | |
6c009ab8 | 398 | |
4df6ed4f | 399 | ecc_tmp = readl_relaxed(host->regs_va + ECC2); |
fc43f45e BB |
400 | ecc[4] = ecc_tmp; |
401 | ecc[5] = ecc_tmp >> 8; | |
402 | ecc[6] = ecc_tmp >> 16; | |
403 | ecc[7] = ecc_tmp >> 24; | |
6c009ab8 | 404 | |
4df6ed4f | 405 | ecc_tmp = readl_relaxed(host->regs_va + ECC3); |
fc43f45e BB |
406 | ecc[8] = ecc_tmp; |
407 | ecc[9] = ecc_tmp >> 8; | |
408 | ecc[10] = ecc_tmp >> 16; | |
409 | ecc[11] = ecc_tmp >> 24; | |
6c009ab8 | 410 | |
4df6ed4f | 411 | ecc_tmp = readl_relaxed(host->regs_va + STS); |
fc43f45e | 412 | ecc[12] = ecc_tmp >> 16; |
6c009ab8 LW |
413 | |
414 | return 0; | |
415 | } | |
416 | ||
417 | /* | |
418 | * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by | |
25985edc | 419 | * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to |
6c009ab8 LW |
420 | * max of 1-bit) |
421 | */ | |
fc43f45e BB |
422 | static int fsmc_read_hwecc_ecc1(struct nand_chip *chip, const u8 *data, |
423 | u8 *ecc) | |
6c009ab8 | 424 | { |
bfc535f4 | 425 | struct fsmc_nand_data *host = nand_to_fsmc(chip); |
fc43f45e | 426 | u32 ecc_tmp; |
6c009ab8 | 427 | |
4df6ed4f | 428 | ecc_tmp = readl_relaxed(host->regs_va + ECC1); |
fc43f45e BB |
429 | ecc[0] = ecc_tmp; |
430 | ecc[1] = ecc_tmp >> 8; | |
431 | ecc[2] = ecc_tmp >> 16; | |
6c009ab8 LW |
432 | |
433 | return 0; | |
434 | } | |
435 | ||
519300cf | 436 | /* Count the number of 0's in buff upto a max of max_bits */ |
fc43f45e | 437 | static int count_written_bits(u8 *buff, int size, int max_bits) |
519300cf VK |
438 | { |
439 | int k, written_bits = 0; | |
440 | ||
441 | for (k = 0; k < size; k++) { | |
442 | written_bits += hweight8(~buff[k]); | |
443 | if (written_bits > max_bits) | |
444 | break; | |
445 | } | |
446 | ||
447 | return written_bits; | |
448 | } | |
449 | ||
4774fb0a VK |
450 | static void dma_complete(void *param) |
451 | { | |
452 | struct fsmc_nand_data *host = param; | |
453 | ||
454 | complete(&host->dma_access_complete); | |
455 | } | |
456 | ||
457 | static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len, | |
fc43f45e | 458 | enum dma_data_direction direction) |
4774fb0a VK |
459 | { |
460 | struct dma_chan *chan; | |
461 | struct dma_device *dma_dev; | |
462 | struct dma_async_tx_descriptor *tx; | |
463 | dma_addr_t dma_dst, dma_src, dma_addr; | |
464 | dma_cookie_t cookie; | |
465 | unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; | |
466 | int ret; | |
818a45b1 | 467 | unsigned long time_left; |
4774fb0a VK |
468 | |
469 | if (direction == DMA_TO_DEVICE) | |
470 | chan = host->write_dma_chan; | |
471 | else if (direction == DMA_FROM_DEVICE) | |
472 | chan = host->read_dma_chan; | |
473 | else | |
474 | return -EINVAL; | |
475 | ||
476 | dma_dev = chan->device; | |
477 | dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction); | |
478 | ||
479 | if (direction == DMA_TO_DEVICE) { | |
480 | dma_src = dma_addr; | |
481 | dma_dst = host->data_pa; | |
4774fb0a VK |
482 | } else { |
483 | dma_src = host->data_pa; | |
484 | dma_dst = dma_addr; | |
4774fb0a VK |
485 | } |
486 | ||
487 | tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src, | |
488 | len, flags); | |
4774fb0a VK |
489 | if (!tx) { |
490 | dev_err(host->dev, "device_prep_dma_memcpy error\n"); | |
d1806a5c BZ |
491 | ret = -EIO; |
492 | goto unmap_dma; | |
4774fb0a VK |
493 | } |
494 | ||
495 | tx->callback = dma_complete; | |
496 | tx->callback_param = host; | |
497 | cookie = tx->tx_submit(tx); | |
498 | ||
499 | ret = dma_submit_error(cookie); | |
500 | if (ret) { | |
501 | dev_err(host->dev, "dma_submit_error %d\n", cookie); | |
d1806a5c | 502 | goto unmap_dma; |
4774fb0a VK |
503 | } |
504 | ||
505 | dma_async_issue_pending(chan); | |
506 | ||
818a45b1 | 507 | time_left = |
928aa2ae | 508 | wait_for_completion_timeout(&host->dma_access_complete, |
fc43f45e | 509 | msecs_to_jiffies(3000)); |
818a45b1 | 510 | if (time_left == 0) { |
b177ea34 | 511 | dmaengine_terminate_all(chan); |
4774fb0a | 512 | dev_err(host->dev, "wait_for_completion_timeout\n"); |
0bda3e19 | 513 | ret = -ETIMEDOUT; |
d1806a5c | 514 | goto unmap_dma; |
4774fb0a VK |
515 | } |
516 | ||
d1806a5c BZ |
517 | ret = 0; |
518 | ||
519 | unmap_dma: | |
520 | dma_unmap_single(dma_dev->dev, dma_addr, len, direction); | |
521 | ||
522 | return ret; | |
4774fb0a VK |
523 | } |
524 | ||
604e7544 VK |
525 | /* |
526 | * fsmc_write_buf - write buffer to chip | |
bfc535f4 | 527 | * @host: FSMC NAND controller |
604e7544 VK |
528 | * @buf: data buffer |
529 | * @len: number of bytes to write | |
530 | */ | |
fc43f45e | 531 | static void fsmc_write_buf(struct fsmc_nand_data *host, const u8 *buf, |
bfc535f4 | 532 | int len) |
604e7544 VK |
533 | { |
534 | int i; | |
604e7544 | 535 | |
fc43f45e BB |
536 | if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) && |
537 | IS_ALIGNED(len, sizeof(u32))) { | |
538 | u32 *p = (u32 *)buf; | |
539 | ||
604e7544 VK |
540 | len = len >> 2; |
541 | for (i = 0; i < len; i++) | |
4df6ed4f | 542 | writel_relaxed(p[i], host->data_va); |
604e7544 VK |
543 | } else { |
544 | for (i = 0; i < len; i++) | |
4df6ed4f | 545 | writeb_relaxed(buf[i], host->data_va); |
604e7544 VK |
546 | } |
547 | } | |
548 | ||
549 | /* | |
550 | * fsmc_read_buf - read chip data into buffer | |
bfc535f4 | 551 | * @host: FSMC NAND controller |
604e7544 VK |
552 | * @buf: buffer to store date |
553 | * @len: number of bytes to read | |
554 | */ | |
fc43f45e | 555 | static void fsmc_read_buf(struct fsmc_nand_data *host, u8 *buf, int len) |
604e7544 VK |
556 | { |
557 | int i; | |
604e7544 | 558 | |
fc43f45e BB |
559 | if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) && |
560 | IS_ALIGNED(len, sizeof(u32))) { | |
561 | u32 *p = (u32 *)buf; | |
562 | ||
604e7544 VK |
563 | len = len >> 2; |
564 | for (i = 0; i < len; i++) | |
4df6ed4f | 565 | p[i] = readl_relaxed(host->data_va); |
604e7544 VK |
566 | } else { |
567 | for (i = 0; i < len; i++) | |
4df6ed4f | 568 | buf[i] = readb_relaxed(host->data_va); |
604e7544 VK |
569 | } |
570 | } | |
571 | ||
4774fb0a VK |
572 | /* |
573 | * fsmc_read_buf_dma - read chip data into buffer | |
bfc535f4 | 574 | * @host: FSMC NAND controller |
4774fb0a VK |
575 | * @buf: buffer to store date |
576 | * @len: number of bytes to read | |
577 | */ | |
fc43f45e | 578 | static void fsmc_read_buf_dma(struct fsmc_nand_data *host, u8 *buf, |
bfc535f4 | 579 | int len) |
4774fb0a | 580 | { |
4774fb0a VK |
581 | dma_xfer(host, buf, len, DMA_FROM_DEVICE); |
582 | } | |
583 | ||
584 | /* | |
585 | * fsmc_write_buf_dma - write buffer to chip | |
bfc535f4 | 586 | * @host: FSMC NAND controller |
4774fb0a VK |
587 | * @buf: data buffer |
588 | * @len: number of bytes to write | |
589 | */ | |
fc43f45e | 590 | static void fsmc_write_buf_dma(struct fsmc_nand_data *host, const u8 *buf, |
bfc535f4 | 591 | int len) |
4774fb0a | 592 | { |
4774fb0a VK |
593 | dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE); |
594 | } | |
595 | ||
4da712e7 MR |
596 | /* |
597 | * fsmc_exec_op - hook called by the core to execute NAND operations | |
598 | * | |
599 | * This controller is simple enough and thus does not need to use the parser | |
600 | * provided by the core, instead, handle every situation here. | |
601 | */ | |
602 | static int fsmc_exec_op(struct nand_chip *chip, const struct nand_operation *op, | |
603 | bool check_only) | |
604 | { | |
bfc535f4 | 605 | struct fsmc_nand_data *host = nand_to_fsmc(chip); |
4da712e7 MR |
606 | const struct nand_op_instr *instr = NULL; |
607 | int ret = 0; | |
608 | unsigned int op_id; | |
609 | int i; | |
610 | ||
611 | pr_debug("Executing operation [%d instructions]:\n", op->ninstrs); | |
550b9fc4 | 612 | |
4da712e7 MR |
613 | for (op_id = 0; op_id < op->ninstrs; op_id++) { |
614 | instr = &op->instrs[op_id]; | |
615 | ||
616 | switch (instr->type) { | |
617 | case NAND_OP_CMD_INSTR: | |
618 | pr_debug(" ->CMD [0x%02x]\n", | |
619 | instr->ctx.cmd.opcode); | |
620 | ||
621 | writeb_relaxed(instr->ctx.cmd.opcode, host->cmd_va); | |
622 | break; | |
623 | ||
624 | case NAND_OP_ADDR_INSTR: | |
625 | pr_debug(" ->ADDR [%d cyc]", | |
626 | instr->ctx.addr.naddrs); | |
627 | ||
628 | for (i = 0; i < instr->ctx.addr.naddrs; i++) | |
629 | writeb_relaxed(instr->ctx.addr.addrs[i], | |
630 | host->addr_va); | |
631 | break; | |
632 | ||
633 | case NAND_OP_DATA_IN_INSTR: | |
634 | pr_debug(" ->DATA_IN [%d B%s]\n", instr->ctx.data.len, | |
635 | instr->ctx.data.force_8bit ? | |
636 | ", force 8-bit" : ""); | |
637 | ||
638 | if (host->mode == USE_DMA_ACCESS) | |
bfc535f4 | 639 | fsmc_read_buf_dma(host, instr->ctx.data.buf.in, |
4da712e7 MR |
640 | instr->ctx.data.len); |
641 | else | |
bfc535f4 | 642 | fsmc_read_buf(host, instr->ctx.data.buf.in, |
4da712e7 MR |
643 | instr->ctx.data.len); |
644 | break; | |
645 | ||
646 | case NAND_OP_DATA_OUT_INSTR: | |
647 | pr_debug(" ->DATA_OUT [%d B%s]\n", instr->ctx.data.len, | |
648 | instr->ctx.data.force_8bit ? | |
649 | ", force 8-bit" : ""); | |
650 | ||
651 | if (host->mode == USE_DMA_ACCESS) | |
fc43f45e BB |
652 | fsmc_write_buf_dma(host, |
653 | instr->ctx.data.buf.out, | |
4da712e7 MR |
654 | instr->ctx.data.len); |
655 | else | |
bfc535f4 | 656 | fsmc_write_buf(host, instr->ctx.data.buf.out, |
4da712e7 MR |
657 | instr->ctx.data.len); |
658 | break; | |
659 | ||
660 | case NAND_OP_WAITRDY_INSTR: | |
661 | pr_debug(" ->WAITRDY [max %d ms]\n", | |
662 | instr->ctx.waitrdy.timeout_ms); | |
663 | ||
664 | ret = nand_soft_waitrdy(chip, | |
665 | instr->ctx.waitrdy.timeout_ms); | |
666 | break; | |
667 | } | |
668 | } | |
669 | ||
670 | return ret; | |
671 | } | |
672 | ||
6c009ab8 LW |
673 | /* |
674 | * fsmc_read_page_hwecc | |
6c009ab8 LW |
675 | * @chip: nand chip info structure |
676 | * @buf: buffer to store read data | |
1fbb938d | 677 | * @oob_required: caller expects OOB data read to chip->oob_poi |
6c009ab8 LW |
678 | * @page: page number to read |
679 | * | |
25985edc | 680 | * This routine is needed for fsmc version 8 as reading from NAND chip has to be |
6c009ab8 LW |
681 | * performed in a strict sequence as follows: |
682 | * data(512 byte) -> ecc(13 byte) | |
25985edc | 683 | * After this read, fsmc hardware generates and reports error data bits(up to a |
6c009ab8 LW |
684 | * max of 8 bits) |
685 | */ | |
fc43f45e | 686 | static int fsmc_read_page_hwecc(struct nand_chip *chip, u8 *buf, |
b9761687 | 687 | int oob_required, int page) |
6c009ab8 | 688 | { |
b9761687 | 689 | struct mtd_info *mtd = nand_to_mtd(chip); |
6c009ab8 LW |
690 | int i, j, s, stat, eccsize = chip->ecc.size; |
691 | int eccbytes = chip->ecc.bytes; | |
692 | int eccsteps = chip->ecc.steps; | |
fc43f45e BB |
693 | u8 *p = buf; |
694 | u8 *ecc_calc = chip->ecc.calc_buf; | |
695 | u8 *ecc_code = chip->ecc.code_buf; | |
41d6f0d0 | 696 | int off, len, ret, group = 0; |
6c009ab8 | 697 | /* |
fc43f45e | 698 | * ecc_oob is intentionally taken as u16. In 16bit devices, we |
6c009ab8 LW |
699 | * end up reading 14 bytes (7 words) from oob. The local array is |
700 | * to maintain word alignment | |
701 | */ | |
fc43f45e BB |
702 | u16 ecc_oob[7]; |
703 | u8 *oob = (u8 *)&ecc_oob[0]; | |
3f91e94f | 704 | unsigned int max_bitflips = 0; |
6c009ab8 LW |
705 | |
706 | for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) { | |
97d90da8 | 707 | nand_read_page_op(chip, page, s * eccsize, NULL, 0); |
ec47636c | 708 | chip->ecc.hwctl(chip, NAND_ECC_READ); |
41d6f0d0 GS |
709 | ret = nand_read_data_op(chip, p, eccsize, false); |
710 | if (ret) | |
711 | return ret; | |
6c009ab8 LW |
712 | |
713 | for (j = 0; j < eccbytes;) { | |
04a123a9 | 714 | struct mtd_oob_region oobregion; |
04a123a9 BB |
715 | |
716 | ret = mtd_ooblayout_ecc(mtd, group++, &oobregion); | |
717 | if (ret) | |
718 | return ret; | |
719 | ||
720 | off = oobregion.offset; | |
721 | len = oobregion.length; | |
6c009ab8 LW |
722 | |
723 | /* | |
4cbe1bf0 VK |
724 | * length is intentionally kept a higher multiple of 2 |
725 | * to read at least 13 bytes even in case of 16 bit NAND | |
726 | * devices | |
727 | */ | |
aea686b4 VK |
728 | if (chip->options & NAND_BUSWIDTH_16) |
729 | len = roundup(len, 2); | |
730 | ||
97d90da8 | 731 | nand_read_oob_op(chip, page, off, oob + j, len); |
6c009ab8 LW |
732 | j += len; |
733 | } | |
734 | ||
519300cf | 735 | memcpy(&ecc_code[i], oob, chip->ecc.bytes); |
af37d2c3 | 736 | chip->ecc.calculate(chip, p, &ecc_calc[i]); |
6c009ab8 | 737 | |
00da2ea9 | 738 | stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]); |
3f91e94f | 739 | if (stat < 0) { |
6c009ab8 | 740 | mtd->ecc_stats.failed++; |
3f91e94f | 741 | } else { |
6c009ab8 | 742 | mtd->ecc_stats.corrected += stat; |
3f91e94f MD |
743 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
744 | } | |
6c009ab8 LW |
745 | } |
746 | ||
3f91e94f | 747 | return max_bitflips; |
6c009ab8 LW |
748 | } |
749 | ||
750 | /* | |
753e0139 | 751 | * fsmc_bch8_correct_data |
6c009ab8 LW |
752 | * @mtd: mtd info structure |
753 | * @dat: buffer of read data | |
754 | * @read_ecc: ecc read from device spare area | |
755 | * @calc_ecc: ecc calculated from read data | |
756 | * | |
757 | * calc_ecc is a 104 bit information containing maximum of 8 error | |
fc43f45e | 758 | * offset information of 13 bits each in 512 bytes of read data. |
6c009ab8 | 759 | */ |
fc43f45e BB |
760 | static int fsmc_bch8_correct_data(struct nand_chip *chip, u8 *dat, |
761 | u8 *read_ecc, u8 *calc_ecc) | |
6c009ab8 | 762 | { |
bfc535f4 | 763 | struct fsmc_nand_data *host = nand_to_fsmc(chip); |
fc43f45e BB |
764 | u32 err_idx[8]; |
765 | u32 num_err, i; | |
766 | u32 ecc1, ecc2, ecc3, ecc4; | |
6c009ab8 | 767 | |
4df6ed4f | 768 | num_err = (readl_relaxed(host->regs_va + STS) >> 10) & 0xF; |
519300cf VK |
769 | |
770 | /* no bit flipping */ | |
771 | if (likely(num_err == 0)) | |
772 | return 0; | |
773 | ||
774 | /* too many errors */ | |
775 | if (unlikely(num_err > 8)) { | |
776 | /* | |
777 | * This is a temporary erase check. A newly erased page read | |
778 | * would result in an ecc error because the oob data is also | |
779 | * erased to FF and the calculated ecc for an FF data is not | |
780 | * FF..FF. | |
781 | * This is a workaround to skip performing correction in case | |
782 | * data is FF..FF | |
783 | * | |
784 | * Logic: | |
785 | * For every page, each bit written as 0 is counted until these | |
786 | * number of bits are greater than 8 (the maximum correction | |
787 | * capability of FSMC for each 512 + 13 bytes) | |
788 | */ | |
789 | ||
790 | int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8); | |
791 | int bits_data = count_written_bits(dat, chip->ecc.size, 8); | |
792 | ||
793 | if ((bits_ecc + bits_data) <= 8) { | |
794 | if (bits_data) | |
795 | memset(dat, 0xff, chip->ecc.size); | |
796 | return bits_data; | |
797 | } | |
798 | ||
799 | return -EBADMSG; | |
800 | } | |
801 | ||
6c009ab8 LW |
802 | /* |
803 | * ------------------- calc_ecc[] bit wise -----------|--13 bits--| | |
804 | * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--| | |
805 | * | |
806 | * calc_ecc is a 104 bit information containing maximum of 8 error | |
fc43f45e BB |
807 | * offset information of 13 bits each. calc_ecc is copied into a |
808 | * u64 array and error offset indexes are populated in err_idx | |
6c009ab8 LW |
809 | * array |
810 | */ | |
4df6ed4f MR |
811 | ecc1 = readl_relaxed(host->regs_va + ECC1); |
812 | ecc2 = readl_relaxed(host->regs_va + ECC2); | |
813 | ecc3 = readl_relaxed(host->regs_va + ECC3); | |
814 | ecc4 = readl_relaxed(host->regs_va + STS); | |
753e0139 AV |
815 | |
816 | err_idx[0] = (ecc1 >> 0) & 0x1FFF; | |
817 | err_idx[1] = (ecc1 >> 13) & 0x1FFF; | |
818 | err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F); | |
819 | err_idx[3] = (ecc2 >> 7) & 0x1FFF; | |
820 | err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF); | |
821 | err_idx[5] = (ecc3 >> 1) & 0x1FFF; | |
822 | err_idx[6] = (ecc3 >> 14) & 0x1FFF; | |
823 | err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F); | |
6c009ab8 LW |
824 | |
825 | i = 0; | |
826 | while (num_err--) { | |
827 | change_bit(0, (unsigned long *)&err_idx[i]); | |
828 | change_bit(1, (unsigned long *)&err_idx[i]); | |
829 | ||
b533f8d8 | 830 | if (err_idx[i] < chip->ecc.size * 8) { |
6c009ab8 LW |
831 | change_bit(err_idx[i], (unsigned long *)dat); |
832 | i++; | |
833 | } | |
834 | } | |
835 | return i; | |
836 | } | |
837 | ||
4774fb0a VK |
838 | static bool filter(struct dma_chan *chan, void *slave) |
839 | { | |
840 | chan->private = slave; | |
841 | return true; | |
842 | } | |
843 | ||
06f25510 | 844 | static int fsmc_nand_probe_config_dt(struct platform_device *pdev, |
a1b1e1d5 TP |
845 | struct fsmc_nand_data *host, |
846 | struct nand_chip *nand) | |
eea62819 | 847 | { |
a1b1e1d5 | 848 | struct device_node *np = pdev->dev.of_node; |
eea62819 | 849 | u32 val; |
62b57f4c | 850 | int ret; |
eea62819 | 851 | |
a1b1e1d5 | 852 | nand->options = 0; |
ee56874f | 853 | |
eea62819 SR |
854 | if (!of_property_read_u32(np, "bank-width", &val)) { |
855 | if (val == 2) { | |
a1b1e1d5 | 856 | nand->options |= NAND_BUSWIDTH_16; |
eea62819 SR |
857 | } else if (val != 1) { |
858 | dev_err(&pdev->dev, "invalid bank-width %u\n", val); | |
859 | return -EINVAL; | |
860 | } | |
861 | } | |
ee56874f | 862 | |
eea62819 | 863 | if (of_get_property(np, "nand-skip-bbtscan", NULL)) |
a1b1e1d5 | 864 | nand->options |= NAND_SKIP_BBTSCAN; |
eea62819 | 865 | |
a1b1e1d5 | 866 | host->dev_timings = devm_kzalloc(&pdev->dev, |
fc43f45e BB |
867 | sizeof(*host->dev_timings), |
868 | GFP_KERNEL); | |
a1b1e1d5 | 869 | if (!host->dev_timings) |
64ddba4d | 870 | return -ENOMEM; |
fc43f45e | 871 | |
a1b1e1d5 | 872 | ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings, |
fc43f45e | 873 | sizeof(*host->dev_timings)); |
d9fb0795 | 874 | if (ret) |
a1b1e1d5 | 875 | host->dev_timings = NULL; |
64ddba4d MYK |
876 | |
877 | /* Set default NAND bank to 0 */ | |
a1b1e1d5 | 878 | host->bank = 0; |
64ddba4d MYK |
879 | if (!of_property_read_u32(np, "bank", &val)) { |
880 | if (val > 3) { | |
881 | dev_err(&pdev->dev, "invalid bank %u\n", val); | |
882 | return -EINVAL; | |
883 | } | |
a1b1e1d5 | 884 | host->bank = val; |
64ddba4d | 885 | } |
eea62819 SR |
886 | return 0; |
887 | } | |
eea62819 | 888 | |
3bbddfa3 MR |
889 | static int fsmc_nand_attach_chip(struct nand_chip *nand) |
890 | { | |
891 | struct mtd_info *mtd = nand_to_mtd(nand); | |
bfc535f4 | 892 | struct fsmc_nand_data *host = nand_to_fsmc(nand); |
3bbddfa3 MR |
893 | |
894 | if (AMBA_REV_BITS(host->pid) >= 8) { | |
895 | switch (mtd->oobsize) { | |
896 | case 16: | |
897 | case 64: | |
898 | case 128: | |
899 | case 224: | |
900 | case 256: | |
901 | break; | |
902 | default: | |
903 | dev_warn(host->dev, | |
904 | "No oob scheme defined for oobsize %d\n", | |
905 | mtd->oobsize); | |
906 | return -EINVAL; | |
907 | } | |
908 | ||
909 | mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops); | |
910 | ||
911 | return 0; | |
912 | } | |
913 | ||
914 | switch (nand->ecc.mode) { | |
915 | case NAND_ECC_HW: | |
916 | dev_info(host->dev, "Using 1-bit HW ECC scheme\n"); | |
917 | nand->ecc.calculate = fsmc_read_hwecc_ecc1; | |
918 | nand->ecc.correct = nand_correct_data; | |
919 | nand->ecc.bytes = 3; | |
920 | nand->ecc.strength = 1; | |
309600c1 | 921 | nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER; |
3bbddfa3 MR |
922 | break; |
923 | ||
924 | case NAND_ECC_SOFT: | |
925 | if (nand->ecc.algo == NAND_ECC_BCH) { | |
926 | dev_info(host->dev, | |
927 | "Using 4-bit SW BCH ECC scheme\n"); | |
928 | break; | |
929 | } | |
930 | ||
931 | case NAND_ECC_ON_DIE: | |
932 | break; | |
933 | ||
934 | default: | |
935 | dev_err(host->dev, "Unsupported ECC mode!\n"); | |
936 | return -ENOTSUPP; | |
937 | } | |
938 | ||
939 | /* | |
940 | * Don't set layout for BCH4 SW ECC. This will be | |
941 | * generated later in nand_bch_init() later. | |
942 | */ | |
943 | if (nand->ecc.mode == NAND_ECC_HW) { | |
944 | switch (mtd->oobsize) { | |
945 | case 16: | |
946 | case 64: | |
947 | case 128: | |
948 | mtd_set_ooblayout(mtd, | |
949 | &fsmc_ecc1_ooblayout_ops); | |
950 | break; | |
951 | default: | |
952 | dev_warn(host->dev, | |
953 | "No oob scheme defined for oobsize %d\n", | |
954 | mtd->oobsize); | |
955 | return -EINVAL; | |
956 | } | |
957 | } | |
958 | ||
959 | return 0; | |
960 | } | |
961 | ||
962 | static const struct nand_controller_ops fsmc_nand_controller_ops = { | |
963 | .attach_chip = fsmc_nand_attach_chip, | |
f2abfeb2 | 964 | .exec_op = fsmc_exec_op, |
7a08dbae | 965 | .setup_data_interface = fsmc_setup_data_interface, |
3bbddfa3 MR |
966 | }; |
967 | ||
6c009ab8 LW |
968 | /* |
969 | * fsmc_nand_probe - Probe function | |
970 | * @pdev: platform device structure | |
971 | */ | |
972 | static int __init fsmc_nand_probe(struct platform_device *pdev) | |
973 | { | |
6c009ab8 LW |
974 | struct fsmc_nand_data *host; |
975 | struct mtd_info *mtd; | |
976 | struct nand_chip *nand; | |
6c009ab8 | 977 | struct resource *res; |
4df6ed4f | 978 | void __iomem *base; |
4774fb0a | 979 | dma_cap_mask_t mask; |
4ad916bc | 980 | int ret = 0; |
593cd871 LW |
981 | u32 pid; |
982 | int i; | |
6c009ab8 | 983 | |
6c009ab8 | 984 | /* Allocate memory for the device structure (and zero it) */ |
82b9dbe2 | 985 | host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); |
d9a21ae8 | 986 | if (!host) |
6c009ab8 | 987 | return -ENOMEM; |
6c009ab8 | 988 | |
a1b1e1d5 TP |
989 | nand = &host->nand; |
990 | ||
991 | ret = fsmc_nand_probe_config_dt(pdev, host, nand); | |
992 | if (ret) | |
993 | return ret; | |
994 | ||
6c009ab8 | 995 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data"); |
b0de774c TR |
996 | host->data_va = devm_ioremap_resource(&pdev->dev, res); |
997 | if (IS_ERR(host->data_va)) | |
998 | return PTR_ERR(host->data_va); | |
cbf29b83 | 999 | |
6d7b42a4 | 1000 | host->data_pa = (dma_addr_t)res->start; |
6c009ab8 | 1001 | |
6d7b42a4 | 1002 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr"); |
b0de774c TR |
1003 | host->addr_va = devm_ioremap_resource(&pdev->dev, res); |
1004 | if (IS_ERR(host->addr_va)) | |
1005 | return PTR_ERR(host->addr_va); | |
6c009ab8 | 1006 | |
6d7b42a4 | 1007 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd"); |
b0de774c TR |
1008 | host->cmd_va = devm_ioremap_resource(&pdev->dev, res); |
1009 | if (IS_ERR(host->cmd_va)) | |
1010 | return PTR_ERR(host->cmd_va); | |
6c009ab8 LW |
1011 | |
1012 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs"); | |
4df6ed4f MR |
1013 | base = devm_ioremap_resource(&pdev->dev, res); |
1014 | if (IS_ERR(base)) | |
1015 | return PTR_ERR(base); | |
1016 | ||
1017 | host->regs_va = base + FSMC_NOR_REG_SIZE + | |
1018 | (host->bank * FSMC_NAND_BANK_SZ); | |
6c009ab8 | 1019 | |
fb8ed2ca | 1020 | host->clk = devm_clk_get(&pdev->dev, NULL); |
6c009ab8 LW |
1021 | if (IS_ERR(host->clk)) { |
1022 | dev_err(&pdev->dev, "failed to fetch block clock\n"); | |
82b9dbe2 | 1023 | return PTR_ERR(host->clk); |
6c009ab8 LW |
1024 | } |
1025 | ||
e25da1c0 | 1026 | ret = clk_prepare_enable(host->clk); |
6c009ab8 | 1027 | if (ret) |
fb8ed2ca | 1028 | return ret; |
6c009ab8 | 1029 | |
593cd871 LW |
1030 | /* |
1031 | * This device ID is actually a common AMBA ID as used on the | |
1032 | * AMBA PrimeCell bus. However it is not a PrimeCell. | |
1033 | */ | |
1034 | for (pid = 0, i = 0; i < 4; i++) | |
fc43f45e BB |
1035 | pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) & |
1036 | 255) << (i * 8); | |
1037 | ||
593cd871 | 1038 | host->pid = pid; |
fc43f45e BB |
1039 | |
1040 | dev_info(&pdev->dev, | |
1041 | "FSMC device partno %03x, manufacturer %02x, revision %02x, config %02x\n", | |
593cd871 LW |
1042 | AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid), |
1043 | AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid)); | |
1044 | ||
712c4add | 1045 | host->dev = &pdev->dev; |
4774fb0a VK |
1046 | |
1047 | if (host->mode == USE_DMA_ACCESS) | |
1048 | init_completion(&host->dma_access_complete); | |
1049 | ||
6c009ab8 | 1050 | /* Link all private pointers */ |
bdf3a555 | 1051 | mtd = nand_to_mtd(&host->nand); |
a1b1e1d5 | 1052 | nand_set_flash_node(nand, pdev->dev.of_node); |
6c009ab8 | 1053 | |
bdf3a555 | 1054 | mtd->dev.parent = &pdev->dev; |
6c009ab8 | 1055 | |
e278fc71 SR |
1056 | /* |
1057 | * Setup default ECC mode. nand_dt_init() called from nand_scan_ident() | |
1058 | * can overwrite this value if the DT provides a different value. | |
1059 | */ | |
6c009ab8 LW |
1060 | nand->ecc.mode = NAND_ECC_HW; |
1061 | nand->ecc.hwctl = fsmc_enable_hwecc; | |
1062 | nand->ecc.size = 512; | |
467e6e7b | 1063 | nand->badblockbits = 7; |
6c009ab8 | 1064 | |
4da712e7 | 1065 | if (host->mode == USE_DMA_ACCESS) { |
4774fb0a VK |
1066 | dma_cap_zero(mask); |
1067 | dma_cap_set(DMA_MEMCPY, mask); | |
feb1e57e | 1068 | host->read_dma_chan = dma_request_channel(mask, filter, NULL); |
4774fb0a VK |
1069 | if (!host->read_dma_chan) { |
1070 | dev_err(&pdev->dev, "Unable to get read dma channel\n"); | |
43fab011 | 1071 | goto disable_clk; |
4774fb0a | 1072 | } |
feb1e57e | 1073 | host->write_dma_chan = dma_request_channel(mask, filter, NULL); |
4774fb0a VK |
1074 | if (!host->write_dma_chan) { |
1075 | dev_err(&pdev->dev, "Unable to get write dma channel\n"); | |
43fab011 | 1076 | goto release_dma_read_chan; |
4774fb0a | 1077 | } |
604e7544 VK |
1078 | } |
1079 | ||
7a08dbae | 1080 | if (host->dev_timings) { |
d9fb0795 | 1081 | fsmc_nand_setup(host, host->dev_timings); |
7a08dbae BB |
1082 | nand->options |= NAND_KEEP_TIMINGS; |
1083 | } | |
6c009ab8 | 1084 | |
593cd871 | 1085 | if (AMBA_REV_BITS(host->pid) >= 8) { |
6c009ab8 LW |
1086 | nand->ecc.read_page = fsmc_read_page_hwecc; |
1087 | nand->ecc.calculate = fsmc_read_hwecc_ecc4; | |
753e0139 | 1088 | nand->ecc.correct = fsmc_bch8_correct_data; |
6c009ab8 | 1089 | nand->ecc.bytes = 13; |
6a918bad | 1090 | nand->ecc.strength = 8; |
6c009ab8 LW |
1091 | } |
1092 | ||
ad71148c BB |
1093 | nand_controller_init(&host->base); |
1094 | host->base.ops = &fsmc_nand_controller_ops; | |
1095 | nand->controller = &host->base; | |
1096 | ||
6c009ab8 | 1097 | /* |
25985edc | 1098 | * Scan to find existence of the device |
6c009ab8 | 1099 | */ |
00ad378f | 1100 | ret = nand_scan(nand, 1); |
ad5678ec | 1101 | if (ret) |
43fab011 | 1102 | goto release_dma_write_chan; |
6c009ab8 | 1103 | |
bdf3a555 | 1104 | mtd->name = "nand"; |
ede29a02 | 1105 | ret = mtd_device_register(mtd, NULL, 0); |
99335d00 | 1106 | if (ret) |
682cae27 | 1107 | goto cleanup_nand; |
6c009ab8 LW |
1108 | |
1109 | platform_set_drvdata(pdev, host); | |
1110 | dev_info(&pdev->dev, "FSMC NAND driver registration successful\n"); | |
43fab011 | 1111 | |
6c009ab8 LW |
1112 | return 0; |
1113 | ||
682cae27 MR |
1114 | cleanup_nand: |
1115 | nand_cleanup(nand); | |
43fab011 | 1116 | release_dma_write_chan: |
4774fb0a VK |
1117 | if (host->mode == USE_DMA_ACCESS) |
1118 | dma_release_channel(host->write_dma_chan); | |
43fab011 | 1119 | release_dma_read_chan: |
4774fb0a VK |
1120 | if (host->mode == USE_DMA_ACCESS) |
1121 | dma_release_channel(host->read_dma_chan); | |
43fab011 | 1122 | disable_clk: |
e25da1c0 | 1123 | clk_disable_unprepare(host->clk); |
43fab011 | 1124 | |
6c009ab8 LW |
1125 | return ret; |
1126 | } | |
1127 | ||
1128 | /* | |
1129 | * Clean up routine | |
1130 | */ | |
1131 | static int fsmc_nand_remove(struct platform_device *pdev) | |
1132 | { | |
1133 | struct fsmc_nand_data *host = platform_get_drvdata(pdev); | |
1134 | ||
6c009ab8 | 1135 | if (host) { |
59ac276f | 1136 | nand_release(&host->nand); |
4774fb0a VK |
1137 | |
1138 | if (host->mode == USE_DMA_ACCESS) { | |
1139 | dma_release_channel(host->write_dma_chan); | |
1140 | dma_release_channel(host->read_dma_chan); | |
1141 | } | |
e25da1c0 | 1142 | clk_disable_unprepare(host->clk); |
6c009ab8 | 1143 | } |
82b9dbe2 | 1144 | |
6c009ab8 LW |
1145 | return 0; |
1146 | } | |
1147 | ||
80ce4dde | 1148 | #ifdef CONFIG_PM_SLEEP |
6c009ab8 LW |
1149 | static int fsmc_nand_suspend(struct device *dev) |
1150 | { | |
1151 | struct fsmc_nand_data *host = dev_get_drvdata(dev); | |
fc43f45e | 1152 | |
6c009ab8 | 1153 | if (host) |
e25da1c0 | 1154 | clk_disable_unprepare(host->clk); |
fc43f45e | 1155 | |
6c009ab8 LW |
1156 | return 0; |
1157 | } | |
1158 | ||
1159 | static int fsmc_nand_resume(struct device *dev) | |
1160 | { | |
1161 | struct fsmc_nand_data *host = dev_get_drvdata(dev); | |
fc43f45e | 1162 | |
f63acb75 | 1163 | if (host) { |
e25da1c0 | 1164 | clk_prepare_enable(host->clk); |
d9fb0795 TP |
1165 | if (host->dev_timings) |
1166 | fsmc_nand_setup(host, host->dev_timings); | |
f63acb75 | 1167 | } |
fc43f45e | 1168 | |
6c009ab8 LW |
1169 | return 0; |
1170 | } | |
80ce4dde | 1171 | #endif |
6c009ab8 | 1172 | |
f63acb75 | 1173 | static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume); |
6c009ab8 | 1174 | |
eea62819 SR |
1175 | static const struct of_device_id fsmc_nand_id_table[] = { |
1176 | { .compatible = "st,spear600-fsmc-nand" }, | |
ba785205 | 1177 | { .compatible = "stericsson,fsmc-nand" }, |
eea62819 SR |
1178 | {} |
1179 | }; | |
1180 | MODULE_DEVICE_TABLE(of, fsmc_nand_id_table); | |
eea62819 | 1181 | |
6c009ab8 LW |
1182 | static struct platform_driver fsmc_nand_driver = { |
1183 | .remove = fsmc_nand_remove, | |
1184 | .driver = { | |
6c009ab8 | 1185 | .name = "fsmc-nand", |
33575b25 | 1186 | .of_match_table = fsmc_nand_id_table, |
6c009ab8 | 1187 | .pm = &fsmc_nand_pm_ops, |
6c009ab8 LW |
1188 | }, |
1189 | }; | |
1190 | ||
307d2a51 | 1191 | module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe); |
6c009ab8 | 1192 | |
bb696344 | 1193 | MODULE_LICENSE("GPL v2"); |
6c009ab8 LW |
1194 | MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi"); |
1195 | MODULE_DESCRIPTION("NAND driver for SPEAr Platforms"); |