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b04a3fe3 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
45dfc1a0 HS |
2 | /* |
3 | * Freescale GPMI NAND Flash Driver | |
4 | * | |
5 | * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. | |
6 | * Copyright (C) 2008 Embedded Alley Solutions, Inc. | |
45dfc1a0 | 7 | */ |
45dfc1a0 HS |
8 | #include <linux/delay.h> |
9 | #include <linux/clk.h> | |
df877fb3 | 10 | #include <linux/slab.h> |
45dfc1a0 HS |
11 | |
12 | #include "gpmi-nand.h" | |
13 | #include "gpmi-regs.h" | |
14 | #include "bch-regs.h" | |
15 | ||
b1206122 MR |
16 | /* Converts time to clock cycles */ |
17 | #define TO_CYCLES(duration, period) DIV_ROUND_UP_ULL(duration, period) | |
45dfc1a0 | 18 | |
4aa6ae3e HS |
19 | #define MXS_SET_ADDR 0x4 |
20 | #define MXS_CLR_ADDR 0x8 | |
45dfc1a0 HS |
21 | /* |
22 | * Clear the bit and poll it cleared. This is usually called with | |
23 | * a reset address and mask being either SFTRST(bit 31) or CLKGATE | |
24 | * (bit 30). | |
25 | */ | |
26 | static int clear_poll_bit(void __iomem *addr, u32 mask) | |
27 | { | |
28 | int timeout = 0x400; | |
29 | ||
30 | /* clear the bit */ | |
4aa6ae3e | 31 | writel(mask, addr + MXS_CLR_ADDR); |
45dfc1a0 HS |
32 | |
33 | /* | |
34 | * SFTRST needs 3 GPMI clocks to settle, the reference manual | |
35 | * recommends to wait 1us. | |
36 | */ | |
37 | udelay(1); | |
38 | ||
39 | /* poll the bit becoming clear */ | |
40 | while ((readl(addr) & mask) && --timeout) | |
41 | /* nothing */; | |
42 | ||
43 | return !timeout; | |
44 | } | |
45 | ||
46 | #define MODULE_CLKGATE (1 << 30) | |
47 | #define MODULE_SFTRST (1 << 31) | |
48 | /* | |
49 | * The current mxs_reset_block() will do two things: | |
50 | * [1] enable the module. | |
51 | * [2] reset the module. | |
52 | * | |
9398d1ce HS |
53 | * In most of the cases, it's ok. |
54 | * But in MX23, there is a hardware bug in the BCH block (see erratum #2847). | |
45dfc1a0 HS |
55 | * If you try to soft reset the BCH block, it becomes unusable until |
56 | * the next hard reset. This case occurs in the NAND boot mode. When the board | |
57 | * boots by NAND, the ROM of the chip will initialize the BCH blocks itself. | |
58 | * So If the driver tries to reset the BCH again, the BCH will not work anymore. | |
9398d1ce HS |
59 | * You will see a DMA timeout in this case. The bug has been fixed |
60 | * in the following chips, such as MX28. | |
45dfc1a0 HS |
61 | * |
62 | * To avoid this bug, just add a new parameter `just_enable` for | |
63 | * the mxs_reset_block(), and rewrite it here. | |
64 | */ | |
9398d1ce | 65 | static int gpmi_reset_block(void __iomem *reset_addr, bool just_enable) |
45dfc1a0 HS |
66 | { |
67 | int ret; | |
68 | int timeout = 0x400; | |
69 | ||
70 | /* clear and poll SFTRST */ | |
71 | ret = clear_poll_bit(reset_addr, MODULE_SFTRST); | |
72 | if (unlikely(ret)) | |
73 | goto error; | |
74 | ||
75 | /* clear CLKGATE */ | |
4aa6ae3e | 76 | writel(MODULE_CLKGATE, reset_addr + MXS_CLR_ADDR); |
45dfc1a0 HS |
77 | |
78 | if (!just_enable) { | |
79 | /* set SFTRST to reset the block */ | |
4aa6ae3e | 80 | writel(MODULE_SFTRST, reset_addr + MXS_SET_ADDR); |
45dfc1a0 HS |
81 | udelay(1); |
82 | ||
83 | /* poll CLKGATE becoming set */ | |
84 | while ((!(readl(reset_addr) & MODULE_CLKGATE)) && --timeout) | |
85 | /* nothing */; | |
86 | if (unlikely(!timeout)) | |
87 | goto error; | |
88 | } | |
89 | ||
90 | /* clear and poll SFTRST */ | |
91 | ret = clear_poll_bit(reset_addr, MODULE_SFTRST); | |
92 | if (unlikely(ret)) | |
93 | goto error; | |
94 | ||
95 | /* clear and poll CLKGATE */ | |
96 | ret = clear_poll_bit(reset_addr, MODULE_CLKGATE); | |
97 | if (unlikely(ret)) | |
98 | goto error; | |
99 | ||
100 | return 0; | |
101 | ||
102 | error: | |
103 | pr_err("%s(%p): module reset timeout\n", __func__, reset_addr); | |
104 | return -ETIMEDOUT; | |
105 | } | |
106 | ||
ff506172 HS |
107 | static int __gpmi_enable_clk(struct gpmi_nand_data *this, bool v) |
108 | { | |
109 | struct clk *clk; | |
110 | int ret; | |
111 | int i; | |
112 | ||
113 | for (i = 0; i < GPMI_CLK_MAX; i++) { | |
114 | clk = this->resources.clock[i]; | |
115 | if (!clk) | |
116 | break; | |
117 | ||
118 | if (v) { | |
119 | ret = clk_prepare_enable(clk); | |
120 | if (ret) | |
121 | goto err_clk; | |
122 | } else { | |
123 | clk_disable_unprepare(clk); | |
124 | } | |
125 | } | |
126 | return 0; | |
127 | ||
128 | err_clk: | |
129 | for (; i > 0; i--) | |
130 | clk_disable_unprepare(this->resources.clock[i - 1]); | |
131 | return ret; | |
132 | } | |
133 | ||
76e1a008 MR |
134 | int gpmi_enable_clk(struct gpmi_nand_data *this) |
135 | { | |
136 | return __gpmi_enable_clk(this, true); | |
137 | } | |
138 | ||
139 | int gpmi_disable_clk(struct gpmi_nand_data *this) | |
140 | { | |
141 | return __gpmi_enable_clk(this, false); | |
142 | } | |
ff506172 | 143 | |
45dfc1a0 HS |
144 | int gpmi_init(struct gpmi_nand_data *this) |
145 | { | |
146 | struct resources *r = &this->resources; | |
147 | int ret; | |
148 | ||
ff506172 | 149 | ret = gpmi_enable_clk(this); |
45dfc1a0 | 150 | if (ret) |
ce93bedb | 151 | return ret; |
45dfc1a0 HS |
152 | ret = gpmi_reset_block(r->gpmi_regs, false); |
153 | if (ret) | |
154 | goto err_out; | |
155 | ||
6f2a6a52 WS |
156 | /* |
157 | * Reset BCH here, too. We got failures otherwise :( | |
d5d27fd9 | 158 | * See later BCH reset for explanation of MX23 and MX28 handling |
6f2a6a52 | 159 | */ |
f67ed146 | 160 | ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MXS(this)); |
6f2a6a52 WS |
161 | if (ret) |
162 | goto err_out; | |
163 | ||
45dfc1a0 HS |
164 | /* Choose NAND mode. */ |
165 | writel(BM_GPMI_CTRL1_GPMI_MODE, r->gpmi_regs + HW_GPMI_CTRL1_CLR); | |
166 | ||
167 | /* Set the IRQ polarity. */ | |
168 | writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY, | |
169 | r->gpmi_regs + HW_GPMI_CTRL1_SET); | |
170 | ||
171 | /* Disable Write-Protection. */ | |
172 | writel(BM_GPMI_CTRL1_DEV_RESET, r->gpmi_regs + HW_GPMI_CTRL1_SET); | |
173 | ||
174 | /* Select BCH ECC. */ | |
175 | writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET); | |
176 | ||
d159d8b7 HS |
177 | /* |
178 | * Decouple the chip select from dma channel. We use dma0 for all | |
179 | * the chips. | |
180 | */ | |
181 | writel(BM_GPMI_CTRL1_DECOUPLE_CS, r->gpmi_regs + HW_GPMI_CTRL1_SET); | |
182 | ||
ff506172 | 183 | gpmi_disable_clk(this); |
45dfc1a0 HS |
184 | return 0; |
185 | err_out: | |
ce93bedb | 186 | gpmi_disable_clk(this); |
45dfc1a0 HS |
187 | return ret; |
188 | } | |
189 | ||
190 | /* This function is very useful. It is called only when the bug occur. */ | |
191 | void gpmi_dump_info(struct gpmi_nand_data *this) | |
192 | { | |
193 | struct resources *r = &this->resources; | |
194 | struct bch_geometry *geo = &this->bch_geometry; | |
195 | u32 reg; | |
196 | int i; | |
197 | ||
da40c16a | 198 | dev_err(this->dev, "Show GPMI registers :\n"); |
45dfc1a0 HS |
199 | for (i = 0; i <= HW_GPMI_DEBUG / 0x10 + 1; i++) { |
200 | reg = readl(r->gpmi_regs + i * 0x10); | |
da40c16a | 201 | dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg); |
45dfc1a0 HS |
202 | } |
203 | ||
204 | /* start to print out the BCH info */ | |
da40c16a | 205 | dev_err(this->dev, "Show BCH registers :\n"); |
f7226893 HS |
206 | for (i = 0; i <= HW_BCH_VERSION / 0x10 + 1; i++) { |
207 | reg = readl(r->bch_regs + i * 0x10); | |
da40c16a | 208 | dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg); |
f7226893 | 209 | } |
da40c16a HS |
210 | dev_err(this->dev, "BCH Geometry :\n" |
211 | "GF length : %u\n" | |
212 | "ECC Strength : %u\n" | |
213 | "Page Size in Bytes : %u\n" | |
214 | "Metadata Size in Bytes : %u\n" | |
215 | "ECC Chunk Size in Bytes: %u\n" | |
216 | "ECC Chunk Count : %u\n" | |
217 | "Payload Size in Bytes : %u\n" | |
218 | "Auxiliary Size in Bytes: %u\n" | |
219 | "Auxiliary Status Offset: %u\n" | |
220 | "Block Mark Byte Offset : %u\n" | |
221 | "Block Mark Bit Offset : %u\n", | |
222 | geo->gf_len, | |
223 | geo->ecc_strength, | |
224 | geo->page_size, | |
225 | geo->metadata_size, | |
226 | geo->ecc_chunk_size, | |
227 | geo->ecc_chunk_count, | |
228 | geo->payload_size, | |
229 | geo->auxiliary_size, | |
230 | geo->auxiliary_status_offset, | |
231 | geo->block_mark_byte_offset, | |
232 | geo->block_mark_bit_offset); | |
45dfc1a0 HS |
233 | } |
234 | ||
235 | /* Configures the geometry for BCH. */ | |
236 | int bch_set_geometry(struct gpmi_nand_data *this) | |
237 | { | |
238 | struct resources *r = &this->resources; | |
239 | struct bch_geometry *bch_geo = &this->bch_geometry; | |
240 | unsigned int block_count; | |
241 | unsigned int block_size; | |
242 | unsigned int metadata_size; | |
243 | unsigned int ecc_strength; | |
244 | unsigned int page_size; | |
9ff16f08 | 245 | unsigned int gf_len; |
45dfc1a0 HS |
246 | int ret; |
247 | ||
e637f5fe SH |
248 | ret = common_nfc_set_geometry(this); |
249 | if (ret) | |
250 | return ret; | |
45dfc1a0 HS |
251 | |
252 | block_count = bch_geo->ecc_chunk_count - 1; | |
253 | block_size = bch_geo->ecc_chunk_size; | |
254 | metadata_size = bch_geo->metadata_size; | |
255 | ecc_strength = bch_geo->ecc_strength >> 1; | |
256 | page_size = bch_geo->page_size; | |
9ff16f08 | 257 | gf_len = bch_geo->gf_len; |
45dfc1a0 | 258 | |
ff506172 | 259 | ret = gpmi_enable_clk(this); |
45dfc1a0 | 260 | if (ret) |
ce93bedb | 261 | return ret; |
45dfc1a0 | 262 | |
9398d1ce HS |
263 | /* |
264 | * Due to erratum #2847 of the MX23, the BCH cannot be soft reset on this | |
265 | * chip, otherwise it will lock up. So we skip resetting BCH on the MX23. | |
d5d27fd9 | 266 | * and MX28. |
9398d1ce | 267 | */ |
f67ed146 | 268 | ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MXS(this)); |
45dfc1a0 HS |
269 | if (ret) |
270 | goto err_out; | |
271 | ||
272 | /* Configure layout 0. */ | |
273 | writel(BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count) | |
274 | | BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size) | |
9013bb40 | 275 | | BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength, this) |
9ff16f08 | 276 | | BF_BCH_FLASH0LAYOUT0_GF(gf_len, this) |
9013bb40 | 277 | | BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size, this), |
45dfc1a0 HS |
278 | r->bch_regs + HW_BCH_FLASH0LAYOUT0); |
279 | ||
280 | writel(BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size) | |
9013bb40 | 281 | | BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength, this) |
9ff16f08 | 282 | | BF_BCH_FLASH0LAYOUT1_GF(gf_len, this) |
9013bb40 | 283 | | BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size, this), |
45dfc1a0 HS |
284 | r->bch_regs + HW_BCH_FLASH0LAYOUT1); |
285 | ||
286 | /* Set *all* chip selects to use layout 0. */ | |
287 | writel(0, r->bch_regs + HW_BCH_LAYOUTSELECT); | |
288 | ||
289 | /* Enable interrupts. */ | |
290 | writel(BM_BCH_CTRL_COMPLETE_IRQ_EN, | |
291 | r->bch_regs + HW_BCH_CTRL_SET); | |
292 | ||
ff506172 | 293 | gpmi_disable_clk(this); |
45dfc1a0 HS |
294 | return 0; |
295 | err_out: | |
ce93bedb | 296 | gpmi_disable_clk(this); |
45dfc1a0 HS |
297 | return ret; |
298 | } | |
299 | ||
995fbbf5 HS |
300 | /* |
301 | * <1> Firstly, we should know what's the GPMI-clock means. | |
302 | * The GPMI-clock is the internal clock in the gpmi nand controller. | |
303 | * If you set 100MHz to gpmi nand controller, the GPMI-clock's period | |
304 | * is 10ns. Mark the GPMI-clock's period as GPMI-clock-period. | |
305 | * | |
306 | * <2> Secondly, we should know what's the frequency on the nand chip pins. | |
307 | * The frequency on the nand chip pins is derived from the GPMI-clock. | |
308 | * We can get it from the following equation: | |
309 | * | |
310 | * F = G / (DS + DH) | |
311 | * | |
312 | * F : the frequency on the nand chip pins. | |
313 | * G : the GPMI clock, such as 100MHz. | |
314 | * DS : GPMI_HW_GPMI_TIMING0:DATA_SETUP | |
315 | * DH : GPMI_HW_GPMI_TIMING0:DATA_HOLD | |
316 | * | |
317 | * <3> Thirdly, when the frequency on the nand chip pins is above 33MHz, | |
318 | * the nand EDO(extended Data Out) timing could be applied. | |
319 | * The GPMI implements a feedback read strobe to sample the read data. | |
320 | * The feedback read strobe can be delayed to support the nand EDO timing | |
321 | * where the read strobe may deasserts before the read data is valid, and | |
322 | * read data is valid for some time after read strobe. | |
323 | * | |
324 | * The following figure illustrates some aspects of a NAND Flash read: | |
325 | * | |
326 | * |<---tREA---->| | |
327 | * | | | |
328 | * | | | | |
329 | * |<--tRP-->| | | |
330 | * | | | | |
331 | * __ ___|__________________________________ | |
332 | * RDN \________/ | | |
333 | * | | |
334 | * /---------\ | |
335 | * Read Data --------------< >--------- | |
336 | * \---------/ | |
337 | * | | | |
338 | * |<-D->| | |
339 | * FeedbackRDN ________ ____________ | |
340 | * \___________/ | |
341 | * | |
342 | * D stands for delay, set in the HW_GPMI_CTRL1:RDN_DELAY. | |
343 | * | |
344 | * | |
345 | * <4> Now, we begin to describe how to compute the right RDN_DELAY. | |
346 | * | |
347 | * 4.1) From the aspect of the nand chip pins: | |
348 | * Delay = (tREA + C - tRP) {1} | |
349 | * | |
b1206122 MR |
350 | * tREA : the maximum read access time. |
351 | * C : a constant to adjust the delay. default is 4000ps. | |
352 | * tRP : the read pulse width, which is exactly: | |
353 | * tRP = (GPMI-clock-period) * DATA_SETUP | |
995fbbf5 HS |
354 | * |
355 | * 4.2) From the aspect of the GPMI nand controller: | |
356 | * Delay = RDN_DELAY * 0.125 * RP {2} | |
357 | * | |
358 | * RP : the DLL reference period. | |
359 | * if (GPMI-clock-period > DLL_THRETHOLD) | |
360 | * RP = GPMI-clock-period / 2; | |
361 | * else | |
362 | * RP = GPMI-clock-period; | |
363 | * | |
364 | * Set the HW_GPMI_CTRL1:HALF_PERIOD if GPMI-clock-period | |
365 | * is greater DLL_THRETHOLD. In other SOCs, the DLL_THRETHOLD | |
b1206122 | 366 | * is 16000ps, but in mx6q, we use 12000ps. |
995fbbf5 HS |
367 | * |
368 | * 4.3) since {1} equals {2}, we get: | |
369 | * | |
b1206122 MR |
370 | * (tREA + 4000 - tRP) * 8 |
371 | * RDN_DELAY = ----------------------- {3} | |
995fbbf5 | 372 | * RP |
995fbbf5 | 373 | */ |
b1206122 MR |
374 | static void gpmi_nfc_compute_timings(struct gpmi_nand_data *this, |
375 | const struct nand_sdr_timings *sdr) | |
995fbbf5 | 376 | { |
76e1a008 | 377 | struct gpmi_nfc_hardware_timing *hw = &this->hw; |
b1206122 MR |
378 | unsigned int dll_threshold_ps = this->devdata->max_chain_delay; |
379 | unsigned int period_ps, reference_period_ps; | |
380 | unsigned int data_setup_cycles, data_hold_cycles, addr_setup_cycles; | |
381 | unsigned int tRP_ps; | |
382 | bool use_half_period; | |
383 | int sample_delay_ps, sample_delay_factor; | |
384 | u16 busy_timeout_cycles; | |
385 | u8 wrn_dly_sel; | |
386 | ||
387 | if (sdr->tRC_min >= 30000) { | |
388 | /* ONFI non-EDO modes [0-3] */ | |
389 | hw->clk_rate = 22000000; | |
390 | wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS; | |
391 | } else if (sdr->tRC_min >= 25000) { | |
392 | /* ONFI EDO mode 4 */ | |
393 | hw->clk_rate = 80000000; | |
394 | wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY; | |
395 | } else { | |
396 | /* ONFI EDO mode 5 */ | |
397 | hw->clk_rate = 100000000; | |
398 | wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY; | |
399 | } | |
995fbbf5 | 400 | |
b1206122 MR |
401 | /* SDR core timings are given in picoseconds */ |
402 | period_ps = div_u64((u64)NSEC_PER_SEC * 1000, hw->clk_rate); | |
995fbbf5 | 403 | |
b1206122 MR |
404 | addr_setup_cycles = TO_CYCLES(sdr->tALS_min, period_ps); |
405 | data_setup_cycles = TO_CYCLES(sdr->tDS_min, period_ps); | |
406 | data_hold_cycles = TO_CYCLES(sdr->tDH_min, period_ps); | |
407 | busy_timeout_cycles = TO_CYCLES(sdr->tWB_max + sdr->tR_max, period_ps); | |
995fbbf5 | 408 | |
b1206122 MR |
409 | hw->timing0 = BF_GPMI_TIMING0_ADDRESS_SETUP(addr_setup_cycles) | |
410 | BF_GPMI_TIMING0_DATA_HOLD(data_hold_cycles) | | |
411 | BF_GPMI_TIMING0_DATA_SETUP(data_setup_cycles); | |
412 | hw->timing1 = BF_GPMI_TIMING1_BUSY_TIMEOUT(busy_timeout_cycles * 4096); | |
995fbbf5 HS |
413 | |
414 | /* | |
b1206122 MR |
415 | * Derive NFC ideal delay from {3}: |
416 | * | |
417 | * (tREA + 4000 - tRP) * 8 | |
418 | * RDN_DELAY = ----------------------- | |
419 | * RP | |
995fbbf5 | 420 | */ |
b1206122 MR |
421 | if (period_ps > dll_threshold_ps) { |
422 | use_half_period = true; | |
423 | reference_period_ps = period_ps / 2; | |
995fbbf5 | 424 | } else { |
b1206122 MR |
425 | use_half_period = false; |
426 | reference_period_ps = period_ps; | |
995fbbf5 HS |
427 | } |
428 | ||
b1206122 MR |
429 | tRP_ps = data_setup_cycles * period_ps; |
430 | sample_delay_ps = (sdr->tREA_max + 4000 - tRP_ps) * 8; | |
431 | if (sample_delay_ps > 0) | |
432 | sample_delay_factor = sample_delay_ps / reference_period_ps; | |
433 | else | |
434 | sample_delay_factor = 0; | |
995fbbf5 | 435 | |
b1206122 MR |
436 | hw->ctrl1n = BF_GPMI_CTRL1_WRN_DLY_SEL(wrn_dly_sel); |
437 | if (sample_delay_factor) | |
438 | hw->ctrl1n |= BF_GPMI_CTRL1_RDN_DELAY(sample_delay_factor) | | |
439 | BM_GPMI_CTRL1_DLL_ENABLE | | |
440 | (use_half_period ? BM_GPMI_CTRL1_HALF_PERIOD : 0); | |
995fbbf5 HS |
441 | } |
442 | ||
76e1a008 | 443 | void gpmi_nfc_apply_timings(struct gpmi_nand_data *this) |
45dfc1a0 | 444 | { |
76e1a008 | 445 | struct gpmi_nfc_hardware_timing *hw = &this->hw; |
45dfc1a0 | 446 | struct resources *r = &this->resources; |
513d57e1 | 447 | void __iomem *gpmi_regs = r->gpmi_regs; |
b1206122 | 448 | unsigned int dll_wait_time_us; |
45dfc1a0 | 449 | |
76e1a008 | 450 | clk_set_rate(r->clock[0], hw->clk_rate); |
45dfc1a0 | 451 | |
b1206122 MR |
452 | writel(hw->timing0, gpmi_regs + HW_GPMI_TIMING0); |
453 | writel(hw->timing1, gpmi_regs + HW_GPMI_TIMING1); | |
45dfc1a0 HS |
454 | |
455 | /* | |
b1206122 MR |
456 | * Clear several CTRL1 fields, DLL must be disabled when setting |
457 | * RDN_DELAY or HALF_PERIOD. | |
45dfc1a0 | 458 | */ |
b1206122 MR |
459 | writel(BM_GPMI_CTRL1_CLEAR_MASK, gpmi_regs + HW_GPMI_CTRL1_CLR); |
460 | writel(hw->ctrl1n, gpmi_regs + HW_GPMI_CTRL1_SET); | |
45dfc1a0 | 461 | |
b1206122 MR |
462 | /* Wait 64 clock cycles before using the GPMI after enabling the DLL */ |
463 | dll_wait_time_us = USEC_PER_SEC / hw->clk_rate * 64; | |
464 | if (!dll_wait_time_us) | |
465 | dll_wait_time_us = 1; | |
45dfc1a0 HS |
466 | |
467 | /* Wait for the DLL to settle. */ | |
b1206122 | 468 | udelay(dll_wait_time_us); |
45dfc1a0 HS |
469 | } |
470 | ||
858838b8 | 471 | int gpmi_setup_data_interface(struct nand_chip *chip, int chipnr, |
76e1a008 | 472 | const struct nand_data_interface *conf) |
45dfc1a0 | 473 | { |
76e1a008 MR |
474 | struct gpmi_nand_data *this = nand_get_controller_data(chip); |
475 | const struct nand_sdr_timings *sdr; | |
76e1a008 MR |
476 | |
477 | /* Retrieve required NAND timings */ | |
478 | sdr = nand_get_sdr_timings(conf); | |
479 | if (IS_ERR(sdr)) | |
480 | return PTR_ERR(sdr); | |
481 | ||
76e1a008 | 482 | /* Only MX6 GPMI controller can reach EDO timings */ |
b1206122 | 483 | if (sdr->tRC_min <= 25000 && !GPMI_IS_MX6(this)) |
76e1a008 MR |
484 | return -ENOTSUPP; |
485 | ||
b1206122 | 486 | /* Stop here if this call was just a check */ |
76e1a008 MR |
487 | if (chipnr < 0) |
488 | return 0; | |
489 | ||
b1206122 MR |
490 | /* Do the actual derivation of the controller timings */ |
491 | gpmi_nfc_compute_timings(this, sdr); | |
76e1a008 MR |
492 | |
493 | this->hw.must_apply_timings = true; | |
494 | ||
495 | return 0; | |
45dfc1a0 HS |
496 | } |
497 | ||
498 | /* Clears a BCH interrupt. */ | |
499 | void gpmi_clear_bch(struct gpmi_nand_data *this) | |
500 | { | |
501 | struct resources *r = &this->resources; | |
502 | writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR); | |
503 | } | |
504 | ||
505 | /* Returns the Ready/Busy status of the given chip. */ | |
506 | int gpmi_is_ready(struct gpmi_nand_data *this, unsigned chip) | |
507 | { | |
508 | struct resources *r = &this->resources; | |
509 | uint32_t mask = 0; | |
510 | uint32_t reg = 0; | |
511 | ||
512 | if (GPMI_IS_MX23(this)) { | |
513 | mask = MX23_BM_GPMI_DEBUG_READY0 << chip; | |
514 | reg = readl(r->gpmi_regs + HW_GPMI_DEBUG); | |
91f5498e | 515 | } else if (GPMI_IS_MX28(this) || GPMI_IS_MX6(this)) { |
7caa4fd2 HS |
516 | /* |
517 | * In the imx6, all the ready/busy pins are bound | |
518 | * together. So we only need to check chip 0. | |
519 | */ | |
91f5498e | 520 | if (GPMI_IS_MX6(this)) |
7caa4fd2 HS |
521 | chip = 0; |
522 | ||
9013bb40 | 523 | /* MX28 shares the same R/B register as MX6Q. */ |
45dfc1a0 HS |
524 | mask = MX28_BF_GPMI_STAT_READY_BUSY(1 << chip); |
525 | reg = readl(r->gpmi_regs + HW_GPMI_STAT); | |
526 | } else | |
f42cf8d6 | 527 | dev_err(this->dev, "unknown arch.\n"); |
45dfc1a0 HS |
528 | return reg & mask; |
529 | } | |
530 | ||
45dfc1a0 HS |
531 | int gpmi_send_command(struct gpmi_nand_data *this) |
532 | { | |
533 | struct dma_chan *channel = get_dma_chan(this); | |
534 | struct dma_async_tx_descriptor *desc; | |
535 | struct scatterlist *sgl; | |
536 | int chip = this->current_chip; | |
c3ee3f3d | 537 | int ret; |
45dfc1a0 HS |
538 | u32 pio[3]; |
539 | ||
540 | /* [1] send out the PIO words */ | |
541 | pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE) | |
542 | | BM_GPMI_CTRL0_WORD_LENGTH | |
543 | | BF_GPMI_CTRL0_CS(chip, this) | |
544 | | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this) | |
545 | | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE) | |
546 | | BM_GPMI_CTRL0_ADDRESS_INCREMENT | |
547 | | BF_GPMI_CTRL0_XFER_COUNT(this->command_length); | |
548 | pio[1] = pio[2] = 0; | |
16052827 | 549 | desc = dmaengine_prep_slave_sg(channel, |
45dfc1a0 | 550 | (struct scatterlist *)pio, |
0ef7e206 | 551 | ARRAY_SIZE(pio), DMA_TRANS_NONE, 0); |
43a34b8b HS |
552 | if (!desc) |
553 | return -EINVAL; | |
45dfc1a0 HS |
554 | |
555 | /* [2] send out the COMMAND + ADDRESS string stored in @buffer */ | |
556 | sgl = &this->cmd_sgl; | |
557 | ||
558 | sg_init_one(sgl, this->cmd_buffer, this->command_length); | |
559 | dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE); | |
623ff773 | 560 | desc = dmaengine_prep_slave_sg(channel, |
921de864 HS |
561 | sgl, 1, DMA_MEM_TO_DEV, |
562 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
43a34b8b HS |
563 | if (!desc) |
564 | return -EINVAL; | |
45dfc1a0 HS |
565 | |
566 | /* [3] submit the DMA */ | |
c3ee3f3d SH |
567 | ret = start_dma_without_bch_irq(this, desc); |
568 | ||
569 | dma_unmap_sg(this->dev, sgl, 1, DMA_TO_DEVICE); | |
570 | ||
571 | return ret; | |
45dfc1a0 HS |
572 | } |
573 | ||
ba3900e6 | 574 | int gpmi_send_data(struct gpmi_nand_data *this, const void *buf, int len) |
45dfc1a0 HS |
575 | { |
576 | struct dma_async_tx_descriptor *desc; | |
577 | struct dma_chan *channel = get_dma_chan(this); | |
578 | int chip = this->current_chip; | |
c3ee3f3d | 579 | int ret; |
45dfc1a0 HS |
580 | uint32_t command_mode; |
581 | uint32_t address; | |
582 | u32 pio[2]; | |
583 | ||
584 | /* [1] PIO */ | |
585 | command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; | |
586 | address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; | |
587 | ||
588 | pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | |
589 | | BM_GPMI_CTRL0_WORD_LENGTH | |
590 | | BF_GPMI_CTRL0_CS(chip, this) | |
591 | | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this) | |
592 | | BF_GPMI_CTRL0_ADDRESS(address) | |
ba3900e6 | 593 | | BF_GPMI_CTRL0_XFER_COUNT(len); |
45dfc1a0 | 594 | pio[1] = 0; |
16052827 | 595 | desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio, |
0ef7e206 | 596 | ARRAY_SIZE(pio), DMA_TRANS_NONE, 0); |
43a34b8b HS |
597 | if (!desc) |
598 | return -EINVAL; | |
45dfc1a0 HS |
599 | |
600 | /* [2] send DMA request */ | |
ba3900e6 | 601 | prepare_data_dma(this, buf, len, DMA_TO_DEVICE); |
16052827 | 602 | desc = dmaengine_prep_slave_sg(channel, &this->data_sgl, |
921de864 HS |
603 | 1, DMA_MEM_TO_DEV, |
604 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
43a34b8b HS |
605 | if (!desc) |
606 | return -EINVAL; | |
607 | ||
45dfc1a0 | 608 | /* [3] submit the DMA */ |
c3ee3f3d SH |
609 | ret = start_dma_without_bch_irq(this, desc); |
610 | ||
611 | dma_unmap_sg(this->dev, &this->data_sgl, 1, DMA_TO_DEVICE); | |
612 | ||
613 | return ret; | |
45dfc1a0 HS |
614 | } |
615 | ||
ba3900e6 | 616 | int gpmi_read_data(struct gpmi_nand_data *this, void *buf, int len) |
45dfc1a0 HS |
617 | { |
618 | struct dma_async_tx_descriptor *desc; | |
619 | struct dma_chan *channel = get_dma_chan(this); | |
620 | int chip = this->current_chip; | |
c3ee3f3d | 621 | int ret; |
45dfc1a0 | 622 | u32 pio[2]; |
111bfed4 | 623 | bool direct; |
45dfc1a0 HS |
624 | |
625 | /* [1] : send PIO */ | |
626 | pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ) | |
627 | | BM_GPMI_CTRL0_WORD_LENGTH | |
628 | | BF_GPMI_CTRL0_CS(chip, this) | |
629 | | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this) | |
630 | | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA) | |
ba3900e6 | 631 | | BF_GPMI_CTRL0_XFER_COUNT(len); |
45dfc1a0 | 632 | pio[1] = 0; |
16052827 | 633 | desc = dmaengine_prep_slave_sg(channel, |
45dfc1a0 | 634 | (struct scatterlist *)pio, |
0ef7e206 | 635 | ARRAY_SIZE(pio), DMA_TRANS_NONE, 0); |
43a34b8b HS |
636 | if (!desc) |
637 | return -EINVAL; | |
45dfc1a0 HS |
638 | |
639 | /* [2] : send DMA request */ | |
111bfed4 | 640 | direct = prepare_data_dma(this, buf, len, DMA_FROM_DEVICE); |
16052827 | 641 | desc = dmaengine_prep_slave_sg(channel, &this->data_sgl, |
921de864 HS |
642 | 1, DMA_DEV_TO_MEM, |
643 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
43a34b8b HS |
644 | if (!desc) |
645 | return -EINVAL; | |
45dfc1a0 HS |
646 | |
647 | /* [3] : submit the DMA */ | |
c3ee3f3d SH |
648 | |
649 | ret = start_dma_without_bch_irq(this, desc); | |
650 | ||
651 | dma_unmap_sg(this->dev, &this->data_sgl, 1, DMA_FROM_DEVICE); | |
111bfed4 | 652 | if (!direct) |
ba3900e6 | 653 | memcpy(buf, this->data_buffer_dma, len); |
c3ee3f3d SH |
654 | |
655 | return ret; | |
45dfc1a0 HS |
656 | } |
657 | ||
658 | int gpmi_send_page(struct gpmi_nand_data *this, | |
659 | dma_addr_t payload, dma_addr_t auxiliary) | |
660 | { | |
661 | struct bch_geometry *geo = &this->bch_geometry; | |
662 | uint32_t command_mode; | |
663 | uint32_t address; | |
664 | uint32_t ecc_command; | |
665 | uint32_t buffer_mask; | |
666 | struct dma_async_tx_descriptor *desc; | |
667 | struct dma_chan *channel = get_dma_chan(this); | |
668 | int chip = this->current_chip; | |
669 | u32 pio[6]; | |
670 | ||
671 | /* A DMA descriptor that does an ECC page read. */ | |
672 | command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE; | |
673 | address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; | |
674 | ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE; | |
675 | buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE | | |
676 | BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY; | |
677 | ||
678 | pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | |
679 | | BM_GPMI_CTRL0_WORD_LENGTH | |
680 | | BF_GPMI_CTRL0_CS(chip, this) | |
681 | | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this) | |
682 | | BF_GPMI_CTRL0_ADDRESS(address) | |
683 | | BF_GPMI_CTRL0_XFER_COUNT(0); | |
684 | pio[1] = 0; | |
685 | pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC | |
686 | | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) | |
687 | | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask); | |
688 | pio[3] = geo->page_size; | |
689 | pio[4] = payload; | |
690 | pio[5] = auxiliary; | |
691 | ||
623ff773 | 692 | desc = dmaengine_prep_slave_sg(channel, |
45dfc1a0 | 693 | (struct scatterlist *)pio, |
921de864 HS |
694 | ARRAY_SIZE(pio), DMA_TRANS_NONE, |
695 | DMA_CTRL_ACK); | |
43a34b8b HS |
696 | if (!desc) |
697 | return -EINVAL; | |
698 | ||
45dfc1a0 HS |
699 | return start_dma_with_bch_irq(this, desc); |
700 | } | |
701 | ||
702 | int gpmi_read_page(struct gpmi_nand_data *this, | |
703 | dma_addr_t payload, dma_addr_t auxiliary) | |
704 | { | |
705 | struct bch_geometry *geo = &this->bch_geometry; | |
706 | uint32_t command_mode; | |
707 | uint32_t address; | |
708 | uint32_t ecc_command; | |
709 | uint32_t buffer_mask; | |
710 | struct dma_async_tx_descriptor *desc; | |
711 | struct dma_chan *channel = get_dma_chan(this); | |
712 | int chip = this->current_chip; | |
713 | u32 pio[6]; | |
714 | ||
715 | /* [1] Wait for the chip to report ready. */ | |
716 | command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY; | |
717 | address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; | |
718 | ||
719 | pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | |
720 | | BM_GPMI_CTRL0_WORD_LENGTH | |
721 | | BF_GPMI_CTRL0_CS(chip, this) | |
722 | | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this) | |
723 | | BF_GPMI_CTRL0_ADDRESS(address) | |
724 | | BF_GPMI_CTRL0_XFER_COUNT(0); | |
725 | pio[1] = 0; | |
16052827 | 726 | desc = dmaengine_prep_slave_sg(channel, |
0ef7e206 SG |
727 | (struct scatterlist *)pio, 2, |
728 | DMA_TRANS_NONE, 0); | |
43a34b8b HS |
729 | if (!desc) |
730 | return -EINVAL; | |
45dfc1a0 HS |
731 | |
732 | /* [2] Enable the BCH block and read. */ | |
733 | command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ; | |
734 | address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; | |
735 | ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE; | |
736 | buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE | |
737 | | BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY; | |
738 | ||
739 | pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | |
740 | | BM_GPMI_CTRL0_WORD_LENGTH | |
741 | | BF_GPMI_CTRL0_CS(chip, this) | |
742 | | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this) | |
743 | | BF_GPMI_CTRL0_ADDRESS(address) | |
744 | | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size); | |
745 | ||
746 | pio[1] = 0; | |
747 | pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC | |
748 | | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) | |
749 | | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask); | |
750 | pio[3] = geo->page_size; | |
751 | pio[4] = payload; | |
752 | pio[5] = auxiliary; | |
16052827 | 753 | desc = dmaengine_prep_slave_sg(channel, |
45dfc1a0 | 754 | (struct scatterlist *)pio, |
921de864 HS |
755 | ARRAY_SIZE(pio), DMA_TRANS_NONE, |
756 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
43a34b8b HS |
757 | if (!desc) |
758 | return -EINVAL; | |
45dfc1a0 HS |
759 | |
760 | /* [3] Disable the BCH block */ | |
761 | command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY; | |
762 | address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA; | |
763 | ||
764 | pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode) | |
765 | | BM_GPMI_CTRL0_WORD_LENGTH | |
766 | | BF_GPMI_CTRL0_CS(chip, this) | |
767 | | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this) | |
768 | | BF_GPMI_CTRL0_ADDRESS(address) | |
769 | | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size); | |
770 | pio[1] = 0; | |
09ef90d9 | 771 | pio[2] = 0; /* clear GPMI_HW_GPMI_ECCCTRL, disable the BCH. */ |
16052827 | 772 | desc = dmaengine_prep_slave_sg(channel, |
09ef90d9 | 773 | (struct scatterlist *)pio, 3, |
921de864 HS |
774 | DMA_TRANS_NONE, |
775 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
43a34b8b HS |
776 | if (!desc) |
777 | return -EINVAL; | |
45dfc1a0 HS |
778 | |
779 | /* [4] submit the DMA */ | |
45dfc1a0 HS |
780 | return start_dma_with_bch_irq(this, desc); |
781 | } | |
66de54a7 BB |
782 | |
783 | /** | |
784 | * gpmi_copy_bits - copy bits from one memory region to another | |
785 | * @dst: destination buffer | |
786 | * @dst_bit_off: bit offset we're starting to write at | |
787 | * @src: source buffer | |
788 | * @src_bit_off: bit offset we're starting to read from | |
789 | * @nbits: number of bits to copy | |
790 | * | |
791 | * This functions copies bits from one memory region to another, and is used by | |
792 | * the GPMI driver to copy ECC sections which are not guaranteed to be byte | |
793 | * aligned. | |
794 | * | |
795 | * src and dst should not overlap. | |
796 | * | |
797 | */ | |
798 | void gpmi_copy_bits(u8 *dst, size_t dst_bit_off, | |
799 | const u8 *src, size_t src_bit_off, | |
800 | size_t nbits) | |
801 | { | |
802 | size_t i; | |
803 | size_t nbytes; | |
804 | u32 src_buffer = 0; | |
805 | size_t bits_in_src_buffer = 0; | |
806 | ||
807 | if (!nbits) | |
808 | return; | |
809 | ||
810 | /* | |
811 | * Move src and dst pointers to the closest byte pointer and store bit | |
812 | * offsets within a byte. | |
813 | */ | |
814 | src += src_bit_off / 8; | |
815 | src_bit_off %= 8; | |
816 | ||
817 | dst += dst_bit_off / 8; | |
818 | dst_bit_off %= 8; | |
819 | ||
820 | /* | |
821 | * Initialize the src_buffer value with bits available in the first | |
822 | * byte of data so that we end up with a byte aligned src pointer. | |
823 | */ | |
824 | if (src_bit_off) { | |
825 | src_buffer = src[0] >> src_bit_off; | |
826 | if (nbits >= (8 - src_bit_off)) { | |
827 | bits_in_src_buffer += 8 - src_bit_off; | |
828 | } else { | |
829 | src_buffer &= GENMASK(nbits - 1, 0); | |
830 | bits_in_src_buffer += nbits; | |
831 | } | |
832 | nbits -= bits_in_src_buffer; | |
833 | src++; | |
834 | } | |
835 | ||
836 | /* Calculate the number of bytes that can be copied from src to dst. */ | |
837 | nbytes = nbits / 8; | |
838 | ||
839 | /* Try to align dst to a byte boundary. */ | |
840 | if (dst_bit_off) { | |
841 | if (bits_in_src_buffer < (8 - dst_bit_off) && nbytes) { | |
842 | src_buffer |= src[0] << bits_in_src_buffer; | |
843 | bits_in_src_buffer += 8; | |
844 | src++; | |
845 | nbytes--; | |
846 | } | |
847 | ||
848 | if (bits_in_src_buffer >= (8 - dst_bit_off)) { | |
849 | dst[0] &= GENMASK(dst_bit_off - 1, 0); | |
850 | dst[0] |= src_buffer << dst_bit_off; | |
851 | src_buffer >>= (8 - dst_bit_off); | |
852 | bits_in_src_buffer -= (8 - dst_bit_off); | |
853 | dst_bit_off = 0; | |
854 | dst++; | |
855 | if (bits_in_src_buffer > 7) { | |
856 | bits_in_src_buffer -= 8; | |
857 | dst[0] = src_buffer; | |
858 | dst++; | |
859 | src_buffer >>= 8; | |
860 | } | |
861 | } | |
862 | } | |
863 | ||
864 | if (!bits_in_src_buffer && !dst_bit_off) { | |
865 | /* | |
866 | * Both src and dst pointers are byte aligned, thus we can | |
867 | * just use the optimized memcpy function. | |
868 | */ | |
869 | if (nbytes) | |
870 | memcpy(dst, src, nbytes); | |
871 | } else { | |
872 | /* | |
873 | * src buffer is not byte aligned, hence we have to copy each | |
874 | * src byte to the src_buffer variable before extracting a byte | |
875 | * to store in dst. | |
876 | */ | |
877 | for (i = 0; i < nbytes; i++) { | |
878 | src_buffer |= src[i] << bits_in_src_buffer; | |
879 | dst[i] = src_buffer; | |
880 | src_buffer >>= 8; | |
881 | } | |
882 | } | |
883 | /* Update dst and src pointers */ | |
884 | dst += nbytes; | |
885 | src += nbytes; | |
886 | ||
887 | /* | |
888 | * nbits is the number of remaining bits. It should not exceed 8 as | |
889 | * we've already copied as much bytes as possible. | |
890 | */ | |
891 | nbits %= 8; | |
892 | ||
893 | /* | |
894 | * If there's no more bits to copy to the destination and src buffer | |
895 | * was already byte aligned, then we're done. | |
896 | */ | |
897 | if (!nbits && !bits_in_src_buffer) | |
898 | return; | |
899 | ||
900 | /* Copy the remaining bits to src_buffer */ | |
901 | if (nbits) | |
902 | src_buffer |= (*src & GENMASK(nbits - 1, 0)) << | |
903 | bits_in_src_buffer; | |
904 | bits_in_src_buffer += nbits; | |
905 | ||
906 | /* | |
907 | * In case there were not enough bits to get a byte aligned dst buffer | |
908 | * prepare the src_buffer variable to match the dst organization (shift | |
909 | * src_buffer by dst_bit_off and retrieve the least significant bits | |
910 | * from dst). | |
911 | */ | |
912 | if (dst_bit_off) | |
913 | src_buffer = (src_buffer << dst_bit_off) | | |
914 | (*dst & GENMASK(dst_bit_off - 1, 0)); | |
915 | bits_in_src_buffer += dst_bit_off; | |
916 | ||
917 | /* | |
918 | * Keep most significant bits from dst if we end up with an unaligned | |
919 | * number of bits. | |
920 | */ | |
921 | nbytes = bits_in_src_buffer / 8; | |
922 | if (bits_in_src_buffer % 8) { | |
923 | src_buffer |= (dst[nbytes] & | |
924 | GENMASK(7, bits_in_src_buffer % 8)) << | |
925 | (nbytes * 8); | |
926 | nbytes++; | |
927 | } | |
928 | ||
929 | /* Copy the remaining bytes to dst */ | |
930 | for (i = 0; i < nbytes; i++) { | |
931 | dst[i] = src_buffer; | |
932 | src_buffer >>= 8; | |
933 | } | |
934 | } |