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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
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2 | /* |
3 | * Copyright (C) 2017 Free Electrons | |
4 | * Copyright (C) 2017 NextThing Co | |
5 | * | |
6 | * Author: Boris Brezillon <boris.brezillon@free-electrons.com> | |
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7 | */ |
8 | ||
348d56a8 | 9 | #include "internals.h" |
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10 | |
11 | static void amd_nand_decode_id(struct nand_chip *chip) | |
12 | { | |
13 | struct mtd_info *mtd = nand_to_mtd(chip); | |
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14 | struct nand_memory_organization *memorg; |
15 | ||
16 | memorg = nanddev_get_memorg(&chip->base); | |
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17 | |
18 | nand_decode_ext_id(chip); | |
19 | ||
20 | /* | |
21 | * Check for Spansion/AMD ID + repeating 5th, 6th byte since | |
22 | * some Spansion chips have erasesize that conflicts with size | |
23 | * listed in nand_ids table. | |
24 | * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) | |
25 | */ | |
26 | if (chip->id.data[4] != 0x00 && chip->id.data[5] == 0x00 && | |
27 | chip->id.data[6] == 0x00 && chip->id.data[7] == 0x00 && | |
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28 | memorg->pagesize == 512) { |
29 | memorg->pages_per_eraseblock = 256; | |
30 | memorg->pages_per_eraseblock <<= ((chip->id.data[3] & 0x03) << 1); | |
31 | mtd->erasesize = memorg->pages_per_eraseblock * | |
32 | memorg->pagesize; | |
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33 | } |
34 | } | |
35 | ||
36 | static int amd_nand_init(struct nand_chip *chip) | |
37 | { | |
38 | if (nand_is_slc(chip)) | |
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39 | /* |
40 | * According to the datasheet of some Cypress SLC NANDs, | |
41 | * the bad block markers can be in the first, second or last | |
42 | * page of a block. So let's check all three locations. | |
43 | */ | |
44 | chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE | | |
45 | NAND_BBM_LASTPAGE; | |
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46 | |
47 | return 0; | |
48 | } | |
49 | ||
50 | const struct nand_manufacturer_ops amd_nand_manuf_ops = { | |
51 | .detect = amd_nand_decode_id, | |
52 | .init = amd_nand_init, | |
53 | }; |