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1da177e4 LT |
1 | /* linux/drivers/mtd/nand/s3c2410.c |
2 | * | |
7e74a507 BD |
3 | * Copyright © 2004-2008 Simtec Electronics |
4 | * http://armlinux.simtec.co.uk/ | |
fdf2fd52 | 5 | * Ben Dooks <ben@simtec.co.uk> |
1da177e4 | 6 | * |
7e74a507 | 7 | * Samsung S3C2410/S3C2440/S3C2412 NAND driver |
1da177e4 | 8 | * |
1da177e4 LT |
9 | * This program is free software; you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | */ | |
23 | ||
92aeb5d2 SK |
24 | #define pr_fmt(fmt) "nand-s3c2410: " fmt |
25 | ||
1da177e4 LT |
26 | #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG |
27 | #define DEBUG | |
28 | #endif | |
29 | ||
30 | #include <linux/module.h> | |
31 | #include <linux/types.h> | |
1da177e4 LT |
32 | #include <linux/kernel.h> |
33 | #include <linux/string.h> | |
d2a89be8 | 34 | #include <linux/io.h> |
1da177e4 | 35 | #include <linux/ioport.h> |
d052d1be | 36 | #include <linux/platform_device.h> |
1da177e4 LT |
37 | #include <linux/delay.h> |
38 | #include <linux/err.h> | |
4e57b681 | 39 | #include <linux/slab.h> |
f8ce2547 | 40 | #include <linux/clk.h> |
30821fee | 41 | #include <linux/cpufreq.h> |
1c825ad1 SP |
42 | #include <linux/of.h> |
43 | #include <linux/of_device.h> | |
1da177e4 LT |
44 | |
45 | #include <linux/mtd/mtd.h> | |
46 | #include <linux/mtd/nand.h> | |
47 | #include <linux/mtd/nand_ecc.h> | |
48 | #include <linux/mtd/partitions.h> | |
49 | ||
436d42c6 | 50 | #include <linux/platform_data/mtd-nand-s3c2410.h> |
1da177e4 | 51 | |
02d01862 SK |
52 | #define S3C2410_NFREG(x) (x) |
53 | ||
54 | #define S3C2410_NFCONF S3C2410_NFREG(0x00) | |
55 | #define S3C2410_NFCMD S3C2410_NFREG(0x04) | |
56 | #define S3C2410_NFADDR S3C2410_NFREG(0x08) | |
57 | #define S3C2410_NFDATA S3C2410_NFREG(0x0C) | |
58 | #define S3C2410_NFSTAT S3C2410_NFREG(0x10) | |
59 | #define S3C2410_NFECC S3C2410_NFREG(0x14) | |
60 | #define S3C2440_NFCONT S3C2410_NFREG(0x04) | |
61 | #define S3C2440_NFCMD S3C2410_NFREG(0x08) | |
62 | #define S3C2440_NFADDR S3C2410_NFREG(0x0C) | |
63 | #define S3C2440_NFDATA S3C2410_NFREG(0x10) | |
64 | #define S3C2440_NFSTAT S3C2410_NFREG(0x20) | |
65 | #define S3C2440_NFMECC0 S3C2410_NFREG(0x2C) | |
66 | #define S3C2412_NFSTAT S3C2410_NFREG(0x28) | |
67 | #define S3C2412_NFMECC0 S3C2410_NFREG(0x34) | |
68 | #define S3C2410_NFCONF_EN (1<<15) | |
69 | #define S3C2410_NFCONF_INITECC (1<<12) | |
70 | #define S3C2410_NFCONF_nFCE (1<<11) | |
71 | #define S3C2410_NFCONF_TACLS(x) ((x)<<8) | |
72 | #define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) | |
73 | #define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) | |
74 | #define S3C2410_NFSTAT_BUSY (1<<0) | |
75 | #define S3C2440_NFCONF_TACLS(x) ((x)<<12) | |
76 | #define S3C2440_NFCONF_TWRPH0(x) ((x)<<8) | |
77 | #define S3C2440_NFCONF_TWRPH1(x) ((x)<<4) | |
78 | #define S3C2440_NFCONT_INITECC (1<<4) | |
79 | #define S3C2440_NFCONT_nFCE (1<<1) | |
80 | #define S3C2440_NFCONT_ENABLE (1<<0) | |
81 | #define S3C2440_NFSTAT_READY (1<<0) | |
82 | #define S3C2412_NFCONF_NANDBOOT (1<<31) | |
83 | #define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5) | |
84 | #define S3C2412_NFCONT_nFCE0 (1<<1) | |
85 | #define S3C2412_NFSTAT_READY (1<<0) | |
86 | ||
1da177e4 LT |
87 | /* new oob placement block for use with hardware ecc generation |
88 | */ | |
bf01e06b BB |
89 | static int s3c2410_ooblayout_ecc(struct mtd_info *mtd, int section, |
90 | struct mtd_oob_region *oobregion) | |
91 | { | |
92 | if (section) | |
93 | return -ERANGE; | |
94 | ||
95 | oobregion->offset = 0; | |
96 | oobregion->length = 3; | |
97 | ||
98 | return 0; | |
99 | } | |
100 | ||
101 | static int s3c2410_ooblayout_free(struct mtd_info *mtd, int section, | |
102 | struct mtd_oob_region *oobregion) | |
103 | { | |
104 | if (section) | |
105 | return -ERANGE; | |
106 | ||
107 | oobregion->offset = 8; | |
108 | oobregion->length = 8; | |
109 | ||
110 | return 0; | |
111 | } | |
1da177e4 | 112 | |
bf01e06b BB |
113 | static const struct mtd_ooblayout_ops s3c2410_ooblayout_ops = { |
114 | .ecc = s3c2410_ooblayout_ecc, | |
115 | .free = s3c2410_ooblayout_free, | |
1da177e4 LT |
116 | }; |
117 | ||
118 | /* controller and mtd information */ | |
119 | ||
120 | struct s3c2410_nand_info; | |
121 | ||
3db72151 BD |
122 | /** |
123 | * struct s3c2410_nand_mtd - driver MTD structure | |
124 | * @mtd: The MTD instance to pass to the MTD layer. | |
125 | * @chip: The NAND chip information. | |
126 | * @set: The platform information supplied for this set of NAND chips. | |
127 | * @info: Link back to the hardware information. | |
128 | * @scan_res: The result from calling nand_scan_ident(). | |
129 | */ | |
1da177e4 | 130 | struct s3c2410_nand_mtd { |
1da177e4 LT |
131 | struct nand_chip chip; |
132 | struct s3c2410_nand_set *set; | |
133 | struct s3c2410_nand_info *info; | |
134 | int scan_res; | |
135 | }; | |
136 | ||
2c06a082 BD |
137 | enum s3c_cpu_type { |
138 | TYPE_S3C2410, | |
139 | TYPE_S3C2412, | |
140 | TYPE_S3C2440, | |
141 | }; | |
142 | ||
ac497c16 JP |
143 | enum s3c_nand_clk_state { |
144 | CLOCK_DISABLE = 0, | |
145 | CLOCK_ENABLE, | |
146 | CLOCK_SUSPEND, | |
147 | }; | |
148 | ||
1da177e4 LT |
149 | /* overview of the s3c2410 nand state */ |
150 | ||
3db72151 BD |
151 | /** |
152 | * struct s3c2410_nand_info - NAND controller state. | |
153 | * @mtds: An array of MTD instances on this controoler. | |
154 | * @platform: The platform data for this board. | |
155 | * @device: The platform device we bound to. | |
3db72151 | 156 | * @clk: The clock resource for this controller. |
6f32a3e2 | 157 | * @regs: The area mapped for the hardware registers. |
3db72151 BD |
158 | * @sel_reg: Pointer to the register controlling the NAND selection. |
159 | * @sel_bit: The bit in @sel_reg to select the NAND chip. | |
160 | * @mtd_count: The number of MTDs created from this controller. | |
161 | * @save_sel: The contents of @sel_reg to be saved over suspend. | |
162 | * @clk_rate: The clock rate from @clk. | |
ac497c16 | 163 | * @clk_state: The current clock state. |
3db72151 BD |
164 | * @cpu_type: The exact type of this controller. |
165 | */ | |
1da177e4 LT |
166 | struct s3c2410_nand_info { |
167 | /* mtd info */ | |
168 | struct nand_hw_control controller; | |
169 | struct s3c2410_nand_mtd *mtds; | |
170 | struct s3c2410_platform_nand *platform; | |
171 | ||
172 | /* device info */ | |
173 | struct device *device; | |
1da177e4 | 174 | struct clk *clk; |
fdf2fd52 | 175 | void __iomem *regs; |
2c06a082 BD |
176 | void __iomem *sel_reg; |
177 | int sel_bit; | |
1da177e4 | 178 | int mtd_count; |
09160832 | 179 | unsigned long save_sel; |
30821fee | 180 | unsigned long clk_rate; |
ac497c16 | 181 | enum s3c_nand_clk_state clk_state; |
03680b1e | 182 | |
2c06a082 | 183 | enum s3c_cpu_type cpu_type; |
30821fee | 184 | |
d9ca77f0 | 185 | #ifdef CONFIG_ARM_S3C24XX_CPUFREQ |
30821fee BD |
186 | struct notifier_block freq_transition; |
187 | #endif | |
1da177e4 LT |
188 | }; |
189 | ||
1c825ad1 SP |
190 | struct s3c24XX_nand_devtype_data { |
191 | enum s3c_cpu_type type; | |
192 | }; | |
193 | ||
194 | static const struct s3c24XX_nand_devtype_data s3c2410_nand_devtype_data = { | |
195 | .type = TYPE_S3C2410, | |
196 | }; | |
197 | ||
198 | static const struct s3c24XX_nand_devtype_data s3c2412_nand_devtype_data = { | |
199 | .type = TYPE_S3C2412, | |
200 | }; | |
201 | ||
202 | static const struct s3c24XX_nand_devtype_data s3c2440_nand_devtype_data = { | |
203 | .type = TYPE_S3C2440, | |
204 | }; | |
205 | ||
1da177e4 LT |
206 | /* conversion functions */ |
207 | ||
208 | static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd) | |
209 | { | |
7208b997 BB |
210 | return container_of(mtd_to_nand(mtd), struct s3c2410_nand_mtd, |
211 | chip); | |
1da177e4 LT |
212 | } |
213 | ||
214 | static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd) | |
215 | { | |
216 | return s3c2410_nand_mtd_toours(mtd)->info; | |
217 | } | |
218 | ||
3ae5eaec | 219 | static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev) |
1da177e4 | 220 | { |
3ae5eaec | 221 | return platform_get_drvdata(dev); |
1da177e4 LT |
222 | } |
223 | ||
3ae5eaec | 224 | static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev) |
1da177e4 | 225 | { |
453810b7 | 226 | return dev_get_platdata(&dev->dev); |
1da177e4 LT |
227 | } |
228 | ||
ac497c16 | 229 | static inline int allow_clk_suspend(struct s3c2410_nand_info *info) |
d1fef3c5 | 230 | { |
a68c5ec8 SK |
231 | #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP |
232 | return 1; | |
233 | #else | |
234 | return 0; | |
235 | #endif | |
d1fef3c5 BD |
236 | } |
237 | ||
ac497c16 JP |
238 | /** |
239 | * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock. | |
240 | * @info: The controller instance. | |
241 | * @new_state: State to which clock should be set. | |
242 | */ | |
243 | static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info, | |
244 | enum s3c_nand_clk_state new_state) | |
245 | { | |
246 | if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND) | |
247 | return; | |
248 | ||
249 | if (info->clk_state == CLOCK_ENABLE) { | |
250 | if (new_state != CLOCK_ENABLE) | |
887957b4 | 251 | clk_disable_unprepare(info->clk); |
ac497c16 JP |
252 | } else { |
253 | if (new_state == CLOCK_ENABLE) | |
887957b4 | 254 | clk_prepare_enable(info->clk); |
ac497c16 JP |
255 | } |
256 | ||
257 | info->clk_state = new_state; | |
258 | } | |
259 | ||
1da177e4 LT |
260 | /* timing calculations */ |
261 | ||
cfd320fb | 262 | #define NS_IN_KHZ 1000000 |
1da177e4 | 263 | |
3db72151 BD |
264 | /** |
265 | * s3c_nand_calc_rate - calculate timing data. | |
266 | * @wanted: The cycle time in nanoseconds. | |
267 | * @clk: The clock rate in kHz. | |
268 | * @max: The maximum divider value. | |
269 | * | |
270 | * Calculate the timing value from the given parameters. | |
271 | */ | |
2c06a082 | 272 | static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max) |
1da177e4 LT |
273 | { |
274 | int result; | |
275 | ||
947391cf | 276 | result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ); |
1da177e4 LT |
277 | |
278 | pr_debug("result %d from %ld, %d\n", result, clk, wanted); | |
279 | ||
280 | if (result > max) { | |
92aeb5d2 SK |
281 | pr_err("%d ns is too big for current clock rate %ld\n", |
282 | wanted, clk); | |
1da177e4 LT |
283 | return -1; |
284 | } | |
285 | ||
286 | if (result < 1) | |
287 | result = 1; | |
288 | ||
289 | return result; | |
290 | } | |
291 | ||
54cd0208 | 292 | #define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk)) |
1da177e4 LT |
293 | |
294 | /* controller setup */ | |
295 | ||
3db72151 BD |
296 | /** |
297 | * s3c2410_nand_setrate - setup controller timing information. | |
298 | * @info: The controller instance. | |
299 | * | |
300 | * Given the information supplied by the platform, calculate and set | |
301 | * the necessary timing registers in the hardware to generate the | |
302 | * necessary timing cycles to the hardware. | |
303 | */ | |
30821fee | 304 | static int s3c2410_nand_setrate(struct s3c2410_nand_info *info) |
1da177e4 | 305 | { |
30821fee | 306 | struct s3c2410_platform_nand *plat = info->platform; |
2c06a082 | 307 | int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4; |
cfd320fb | 308 | int tacls, twrph0, twrph1; |
30821fee | 309 | unsigned long clkrate = clk_get_rate(info->clk); |
2612e523 | 310 | unsigned long uninitialized_var(set), cfg, uninitialized_var(mask); |
30821fee | 311 | unsigned long flags; |
1da177e4 LT |
312 | |
313 | /* calculate the timing information for the controller */ | |
314 | ||
30821fee | 315 | info->clk_rate = clkrate; |
cfd320fb BD |
316 | clkrate /= 1000; /* turn clock into kHz for ease of use */ |
317 | ||
1da177e4 | 318 | if (plat != NULL) { |
2c06a082 BD |
319 | tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max); |
320 | twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8); | |
321 | twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8); | |
1da177e4 LT |
322 | } else { |
323 | /* default timings */ | |
2c06a082 | 324 | tacls = tacls_max; |
1da177e4 LT |
325 | twrph0 = 8; |
326 | twrph1 = 8; | |
327 | } | |
61b03bd7 | 328 | |
1da177e4 | 329 | if (tacls < 0 || twrph0 < 0 || twrph1 < 0) { |
99974c62 | 330 | dev_err(info->device, "cannot get suitable timings\n"); |
1da177e4 LT |
331 | return -EINVAL; |
332 | } | |
333 | ||
99974c62 | 334 | dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", |
54cd0208 SK |
335 | tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), |
336 | twrph1, to_ns(twrph1, clkrate)); | |
1da177e4 | 337 | |
30821fee BD |
338 | switch (info->cpu_type) { |
339 | case TYPE_S3C2410: | |
340 | mask = (S3C2410_NFCONF_TACLS(3) | | |
341 | S3C2410_NFCONF_TWRPH0(7) | | |
342 | S3C2410_NFCONF_TWRPH1(7)); | |
343 | set = S3C2410_NFCONF_EN; | |
344 | set |= S3C2410_NFCONF_TACLS(tacls - 1); | |
345 | set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); | |
346 | set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); | |
347 | break; | |
348 | ||
349 | case TYPE_S3C2440: | |
350 | case TYPE_S3C2412: | |
a755a385 PK |
351 | mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) | |
352 | S3C2440_NFCONF_TWRPH0(7) | | |
353 | S3C2440_NFCONF_TWRPH1(7)); | |
30821fee BD |
354 | |
355 | set = S3C2440_NFCONF_TACLS(tacls - 1); | |
356 | set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1); | |
357 | set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1); | |
358 | break; | |
359 | ||
360 | default: | |
30821fee BD |
361 | BUG(); |
362 | } | |
363 | ||
30821fee BD |
364 | local_irq_save(flags); |
365 | ||
366 | cfg = readl(info->regs + S3C2410_NFCONF); | |
367 | cfg &= ~mask; | |
368 | cfg |= set; | |
369 | writel(cfg, info->regs + S3C2410_NFCONF); | |
370 | ||
371 | local_irq_restore(flags); | |
372 | ||
ae7304e5 AG |
373 | dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg); |
374 | ||
30821fee BD |
375 | return 0; |
376 | } | |
377 | ||
3db72151 BD |
378 | /** |
379 | * s3c2410_nand_inithw - basic hardware initialisation | |
380 | * @info: The hardware state. | |
381 | * | |
382 | * Do the basic initialisation of the hardware, using s3c2410_nand_setrate() | |
383 | * to setup the hardware access speeds and set the controller to be enabled. | |
384 | */ | |
30821fee BD |
385 | static int s3c2410_nand_inithw(struct s3c2410_nand_info *info) |
386 | { | |
387 | int ret; | |
388 | ||
389 | ret = s3c2410_nand_setrate(info); | |
390 | if (ret < 0) | |
391 | return ret; | |
392 | ||
54cd0208 SK |
393 | switch (info->cpu_type) { |
394 | case TYPE_S3C2410: | |
30821fee | 395 | default: |
2c06a082 BD |
396 | break; |
397 | ||
54cd0208 SK |
398 | case TYPE_S3C2440: |
399 | case TYPE_S3C2412: | |
d1fef3c5 BD |
400 | /* enable the controller and de-assert nFCE */ |
401 | ||
2c06a082 | 402 | writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT); |
a4f957f1 | 403 | } |
1da177e4 | 404 | |
1da177e4 LT |
405 | return 0; |
406 | } | |
407 | ||
3db72151 BD |
408 | /** |
409 | * s3c2410_nand_select_chip - select the given nand chip | |
410 | * @mtd: The MTD instance for this chip. | |
411 | * @chip: The chip number. | |
412 | * | |
413 | * This is called by the MTD layer to either select a given chip for the | |
414 | * @mtd instance, or to indicate that the access has finished and the | |
415 | * chip can be de-selected. | |
416 | * | |
417 | * The routine ensures that the nFCE line is correctly setup, and any | |
418 | * platform specific selection code is called to route nFCE to the specific | |
419 | * chip. | |
420 | */ | |
1da177e4 LT |
421 | static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) |
422 | { | |
423 | struct s3c2410_nand_info *info; | |
61b03bd7 | 424 | struct s3c2410_nand_mtd *nmtd; |
4bd4ebcc | 425 | struct nand_chip *this = mtd_to_nand(mtd); |
1da177e4 LT |
426 | unsigned long cur; |
427 | ||
d699ed25 | 428 | nmtd = nand_get_controller_data(this); |
1da177e4 LT |
429 | info = nmtd->info; |
430 | ||
ac497c16 JP |
431 | if (chip != -1) |
432 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); | |
d1fef3c5 | 433 | |
2c06a082 | 434 | cur = readl(info->sel_reg); |
1da177e4 LT |
435 | |
436 | if (chip == -1) { | |
2c06a082 | 437 | cur |= info->sel_bit; |
1da177e4 | 438 | } else { |
fb8d82a8 | 439 | if (nmtd->set != NULL && chip > nmtd->set->nr_chips) { |
99974c62 | 440 | dev_err(info->device, "invalid chip %d\n", chip); |
1da177e4 LT |
441 | return; |
442 | } | |
443 | ||
444 | if (info->platform != NULL) { | |
445 | if (info->platform->select_chip != NULL) | |
e0c7d767 | 446 | (info->platform->select_chip) (nmtd->set, chip); |
1da177e4 LT |
447 | } |
448 | ||
2c06a082 | 449 | cur &= ~info->sel_bit; |
1da177e4 LT |
450 | } |
451 | ||
2c06a082 | 452 | writel(cur, info->sel_reg); |
d1fef3c5 | 453 | |
ac497c16 JP |
454 | if (chip == -1) |
455 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); | |
1da177e4 LT |
456 | } |
457 | ||
ad3b5fb7 | 458 | /* s3c2410_nand_hwcontrol |
a4f957f1 | 459 | * |
ad3b5fb7 | 460 | * Issue command and address cycles to the chip |
a4f957f1 | 461 | */ |
1da177e4 | 462 | |
7abd3ef9 | 463 | static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
f9068876 | 464 | unsigned int ctrl) |
1da177e4 LT |
465 | { |
466 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
c9ac5977 | 467 | |
7abd3ef9 TG |
468 | if (cmd == NAND_CMD_NONE) |
469 | return; | |
470 | ||
f9068876 | 471 | if (ctrl & NAND_CLE) |
7abd3ef9 TG |
472 | writeb(cmd, info->regs + S3C2410_NFCMD); |
473 | else | |
474 | writeb(cmd, info->regs + S3C2410_NFADDR); | |
a4f957f1 BD |
475 | } |
476 | ||
477 | /* command and control functions */ | |
478 | ||
f9068876 DW |
479 | static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
480 | unsigned int ctrl) | |
a4f957f1 BD |
481 | { |
482 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
1da177e4 | 483 | |
7abd3ef9 TG |
484 | if (cmd == NAND_CMD_NONE) |
485 | return; | |
486 | ||
f9068876 | 487 | if (ctrl & NAND_CLE) |
7abd3ef9 TG |
488 | writeb(cmd, info->regs + S3C2440_NFCMD); |
489 | else | |
490 | writeb(cmd, info->regs + S3C2440_NFADDR); | |
1da177e4 LT |
491 | } |
492 | ||
1da177e4 LT |
493 | /* s3c2410_nand_devready() |
494 | * | |
495 | * returns 0 if the nand is busy, 1 if it is ready | |
496 | */ | |
497 | ||
498 | static int s3c2410_nand_devready(struct mtd_info *mtd) | |
499 | { | |
500 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
1da177e4 LT |
501 | return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY; |
502 | } | |
503 | ||
2c06a082 BD |
504 | static int s3c2440_nand_devready(struct mtd_info *mtd) |
505 | { | |
506 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
507 | return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY; | |
508 | } | |
509 | ||
510 | static int s3c2412_nand_devready(struct mtd_info *mtd) | |
511 | { | |
512 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
513 | return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY; | |
514 | } | |
515 | ||
1da177e4 LT |
516 | /* ECC handling functions */ |
517 | ||
2c06a082 BD |
518 | static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, |
519 | u_char *read_ecc, u_char *calc_ecc) | |
1da177e4 | 520 | { |
a2593247 BD |
521 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
522 | unsigned int diff0, diff1, diff2; | |
523 | unsigned int bit, byte; | |
524 | ||
525 | pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc); | |
526 | ||
527 | diff0 = read_ecc[0] ^ calc_ecc[0]; | |
528 | diff1 = read_ecc[1] ^ calc_ecc[1]; | |
529 | diff2 = read_ecc[2] ^ calc_ecc[2]; | |
530 | ||
13e85974 AS |
531 | pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n", |
532 | __func__, 3, read_ecc, 3, calc_ecc, | |
a2593247 BD |
533 | diff0, diff1, diff2); |
534 | ||
535 | if (diff0 == 0 && diff1 == 0 && diff2 == 0) | |
536 | return 0; /* ECC is ok */ | |
537 | ||
c45c6c68 BD |
538 | /* sometimes people do not think about using the ECC, so check |
539 | * to see if we have an 0xff,0xff,0xff read ECC and then ignore | |
540 | * the error, on the assumption that this is an un-eccd page. | |
541 | */ | |
542 | if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff | |
543 | && info->platform->ignore_unset_ecc) | |
544 | return 0; | |
545 | ||
a2593247 BD |
546 | /* Can we correct this ECC (ie, one row and column change). |
547 | * Note, this is similar to the 256 error code on smartmedia */ | |
548 | ||
549 | if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 && | |
550 | ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 && | |
551 | ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) { | |
552 | /* calculate the bit position of the error */ | |
553 | ||
d0bf3793 MR |
554 | bit = ((diff2 >> 3) & 1) | |
555 | ((diff2 >> 4) & 2) | | |
556 | ((diff2 >> 5) & 4); | |
1da177e4 | 557 | |
a2593247 | 558 | /* calculate the byte position of the error */ |
1da177e4 | 559 | |
d0bf3793 MR |
560 | byte = ((diff2 << 7) & 0x100) | |
561 | ((diff1 << 0) & 0x80) | | |
562 | ((diff1 << 1) & 0x40) | | |
563 | ((diff1 << 2) & 0x20) | | |
564 | ((diff1 << 3) & 0x10) | | |
565 | ((diff0 >> 4) & 0x08) | | |
566 | ((diff0 >> 3) & 0x04) | | |
567 | ((diff0 >> 2) & 0x02) | | |
568 | ((diff0 >> 1) & 0x01); | |
a2593247 BD |
569 | |
570 | dev_dbg(info->device, "correcting error bit %d, byte %d\n", | |
571 | bit, byte); | |
572 | ||
573 | dat[byte] ^= (1 << bit); | |
574 | return 1; | |
575 | } | |
576 | ||
577 | /* if there is only one bit difference in the ECC, then | |
578 | * one of only a row or column parity has changed, which | |
579 | * means the error is most probably in the ECC itself */ | |
580 | ||
581 | diff0 |= (diff1 << 8); | |
582 | diff0 |= (diff2 << 16); | |
583 | ||
03a97550 ZZ |
584 | /* equal to "(diff0 & ~(1 << __ffs(diff0)))" */ |
585 | if ((diff0 & (diff0 - 1)) == 0) | |
a2593247 BD |
586 | return 1; |
587 | ||
4fac9f69 | 588 | return -1; |
1da177e4 LT |
589 | } |
590 | ||
a4f957f1 BD |
591 | /* ECC functions |
592 | * | |
593 | * These allow the s3c2410 and s3c2440 to use the controller's ECC | |
594 | * generator block to ECC the data as it passes through] | |
595 | */ | |
596 | ||
1da177e4 LT |
597 | static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
598 | { | |
599 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
600 | unsigned long ctrl; | |
601 | ||
602 | ctrl = readl(info->regs + S3C2410_NFCONF); | |
603 | ctrl |= S3C2410_NFCONF_INITECC; | |
604 | writel(ctrl, info->regs + S3C2410_NFCONF); | |
605 | } | |
606 | ||
4f659923 MC |
607 | static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
608 | { | |
609 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
610 | unsigned long ctrl; | |
611 | ||
612 | ctrl = readl(info->regs + S3C2440_NFCONT); | |
f938bc56 SK |
613 | writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, |
614 | info->regs + S3C2440_NFCONT); | |
4f659923 MC |
615 | } |
616 | ||
a4f957f1 BD |
617 | static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
618 | { | |
619 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
620 | unsigned long ctrl; | |
621 | ||
622 | ctrl = readl(info->regs + S3C2440_NFCONT); | |
623 | writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); | |
624 | } | |
625 | ||
f938bc56 SK |
626 | static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
627 | u_char *ecc_code) | |
1da177e4 LT |
628 | { |
629 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
630 | ||
631 | ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0); | |
632 | ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); | |
633 | ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); | |
634 | ||
13e85974 | 635 | pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code); |
1da177e4 LT |
636 | |
637 | return 0; | |
638 | } | |
639 | ||
f938bc56 SK |
640 | static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
641 | u_char *ecc_code) | |
4f659923 MC |
642 | { |
643 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
644 | unsigned long ecc = readl(info->regs + S3C2412_NFMECC0); | |
645 | ||
646 | ecc_code[0] = ecc; | |
647 | ecc_code[1] = ecc >> 8; | |
648 | ecc_code[2] = ecc >> 16; | |
649 | ||
13e85974 | 650 | pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code); |
4f659923 MC |
651 | |
652 | return 0; | |
653 | } | |
654 | ||
f938bc56 SK |
655 | static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
656 | u_char *ecc_code) | |
a4f957f1 BD |
657 | { |
658 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
659 | unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); | |
660 | ||
661 | ecc_code[0] = ecc; | |
662 | ecc_code[1] = ecc >> 8; | |
663 | ecc_code[2] = ecc >> 16; | |
664 | ||
71d54f38 | 665 | pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff); |
a4f957f1 BD |
666 | |
667 | return 0; | |
668 | } | |
669 | ||
a4f957f1 BD |
670 | /* over-ride the standard functions for a little more speed. We can |
671 | * use read/write block to move the data buffers to/from the controller | |
672 | */ | |
1da177e4 LT |
673 | |
674 | static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) | |
675 | { | |
4bd4ebcc | 676 | struct nand_chip *this = mtd_to_nand(mtd); |
1da177e4 LT |
677 | readsb(this->IO_ADDR_R, buf, len); |
678 | } | |
679 | ||
b773bb2e MR |
680 | static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
681 | { | |
682 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
dea2aa6f BD |
683 | |
684 | readsl(info->regs + S3C2440_NFDATA, buf, len >> 2); | |
685 | ||
686 | /* cleanup if we've got less than a word to do */ | |
687 | if (len & 3) { | |
688 | buf += len & ~3; | |
689 | ||
690 | for (; len & 3; len--) | |
691 | *buf++ = readb(info->regs + S3C2440_NFDATA); | |
692 | } | |
b773bb2e MR |
693 | } |
694 | ||
f938bc56 SK |
695 | static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, |
696 | int len) | |
1da177e4 | 697 | { |
4bd4ebcc | 698 | struct nand_chip *this = mtd_to_nand(mtd); |
1da177e4 LT |
699 | writesb(this->IO_ADDR_W, buf, len); |
700 | } | |
701 | ||
f938bc56 SK |
702 | static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, |
703 | int len) | |
b773bb2e MR |
704 | { |
705 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
dea2aa6f BD |
706 | |
707 | writesl(info->regs + S3C2440_NFDATA, buf, len >> 2); | |
708 | ||
709 | /* cleanup any fractional write */ | |
710 | if (len & 3) { | |
711 | buf += len & ~3; | |
712 | ||
713 | for (; len & 3; len--, buf++) | |
714 | writeb(*buf, info->regs + S3C2440_NFDATA); | |
715 | } | |
b773bb2e MR |
716 | } |
717 | ||
30821fee BD |
718 | /* cpufreq driver support */ |
719 | ||
d9ca77f0 | 720 | #ifdef CONFIG_ARM_S3C24XX_CPUFREQ |
30821fee BD |
721 | |
722 | static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb, | |
723 | unsigned long val, void *data) | |
724 | { | |
725 | struct s3c2410_nand_info *info; | |
726 | unsigned long newclk; | |
727 | ||
728 | info = container_of(nb, struct s3c2410_nand_info, freq_transition); | |
729 | newclk = clk_get_rate(info->clk); | |
730 | ||
731 | if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) || | |
732 | (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) { | |
733 | s3c2410_nand_setrate(info); | |
734 | } | |
735 | ||
736 | return 0; | |
737 | } | |
738 | ||
739 | static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) | |
740 | { | |
741 | info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition; | |
742 | ||
743 | return cpufreq_register_notifier(&info->freq_transition, | |
744 | CPUFREQ_TRANSITION_NOTIFIER); | |
745 | } | |
746 | ||
f938bc56 SK |
747 | static inline void |
748 | s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) | |
30821fee BD |
749 | { |
750 | cpufreq_unregister_notifier(&info->freq_transition, | |
751 | CPUFREQ_TRANSITION_NOTIFIER); | |
752 | } | |
753 | ||
754 | #else | |
755 | static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) | |
756 | { | |
757 | return 0; | |
758 | } | |
759 | ||
f938bc56 SK |
760 | static inline void |
761 | s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) | |
30821fee BD |
762 | { |
763 | } | |
764 | #endif | |
765 | ||
1da177e4 LT |
766 | /* device management functions */ |
767 | ||
ec0482e6 | 768 | static int s3c24xx_nand_remove(struct platform_device *pdev) |
1da177e4 | 769 | { |
3ae5eaec | 770 | struct s3c2410_nand_info *info = to_nand_info(pdev); |
1da177e4 | 771 | |
61b03bd7 | 772 | if (info == NULL) |
1da177e4 LT |
773 | return 0; |
774 | ||
30821fee BD |
775 | s3c2410_nand_cpufreq_deregister(info); |
776 | ||
777 | /* Release all our mtds and their partitions, then go through | |
778 | * freeing the resources used | |
1da177e4 | 779 | */ |
61b03bd7 | 780 | |
1da177e4 LT |
781 | if (info->mtds != NULL) { |
782 | struct s3c2410_nand_mtd *ptr = info->mtds; | |
783 | int mtdno; | |
784 | ||
785 | for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) { | |
786 | pr_debug("releasing mtd %d (%p)\n", mtdno, ptr); | |
7208b997 | 787 | nand_release(nand_to_mtd(&ptr->chip)); |
1da177e4 | 788 | } |
1da177e4 LT |
789 | } |
790 | ||
791 | /* free the common resources */ | |
792 | ||
6f32a3e2 | 793 | if (!IS_ERR(info->clk)) |
ac497c16 | 794 | s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); |
1da177e4 LT |
795 | |
796 | return 0; | |
797 | } | |
798 | ||
1da177e4 LT |
799 | static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, |
800 | struct s3c2410_nand_mtd *mtd, | |
801 | struct s3c2410_nand_set *set) | |
802 | { | |
ded4c55d | 803 | if (set) { |
7208b997 | 804 | struct mtd_info *mtdinfo = nand_to_mtd(&mtd->chip); |
ed27f028 | 805 | |
7208b997 BB |
806 | mtdinfo->name = set->name; |
807 | ||
808 | return mtd_device_parse_register(mtdinfo, NULL, NULL, | |
42d7fbe2 | 809 | set->partitions, set->nr_partitions); |
ded4c55d SK |
810 | } |
811 | ||
812 | return -ENODEV; | |
1da177e4 | 813 | } |
1da177e4 | 814 | |
104e442a BB |
815 | static int s3c2410_nand_setup_data_interface(struct mtd_info *mtd, int csline, |
816 | const struct nand_data_interface *conf) | |
1c825ad1 SP |
817 | { |
818 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); | |
819 | struct s3c2410_platform_nand *pdata = info->platform; | |
820 | const struct nand_sdr_timings *timings; | |
821 | int tacls; | |
822 | ||
823 | timings = nand_get_sdr_timings(conf); | |
824 | if (IS_ERR(timings)) | |
825 | return -ENOTSUPP; | |
826 | ||
827 | tacls = timings->tCLS_min - timings->tWP_min; | |
828 | if (tacls < 0) | |
829 | tacls = 0; | |
830 | ||
831 | pdata->tacls = DIV_ROUND_UP(tacls, 1000); | |
832 | pdata->twrph0 = DIV_ROUND_UP(timings->tWP_min, 1000); | |
833 | pdata->twrph1 = DIV_ROUND_UP(timings->tCLH_min, 1000); | |
834 | ||
835 | return s3c2410_nand_setrate(info); | |
836 | } | |
837 | ||
3db72151 BD |
838 | /** |
839 | * s3c2410_nand_init_chip - initialise a single instance of an chip | |
840 | * @info: The base NAND controller the chip is on. | |
841 | * @nmtd: The new controller MTD instance to fill in. | |
842 | * @set: The information passed from the board specific platform data. | |
1da177e4 | 843 | * |
3db72151 BD |
844 | * Initialise the given @nmtd from the information in @info and @set. This |
845 | * readies the structure for use with the MTD layer functions by ensuring | |
846 | * all pointers are setup and the necessary control routines selected. | |
847 | */ | |
1da177e4 LT |
848 | static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, |
849 | struct s3c2410_nand_mtd *nmtd, | |
850 | struct s3c2410_nand_set *set) | |
851 | { | |
1c825ad1 | 852 | struct device_node *np = info->device->of_node; |
1da177e4 | 853 | struct nand_chip *chip = &nmtd->chip; |
2c06a082 | 854 | void __iomem *regs = info->regs; |
1da177e4 | 855 | |
1c825ad1 SP |
856 | nand_set_flash_node(chip, set->of_node); |
857 | ||
1da177e4 LT |
858 | chip->write_buf = s3c2410_nand_write_buf; |
859 | chip->read_buf = s3c2410_nand_read_buf; | |
860 | chip->select_chip = s3c2410_nand_select_chip; | |
861 | chip->chip_delay = 50; | |
d699ed25 | 862 | nand_set_controller_data(chip, nmtd); |
74218fed | 863 | chip->options = set->options; |
1da177e4 LT |
864 | chip->controller = &info->controller; |
865 | ||
1c825ad1 SP |
866 | /* |
867 | * let's keep behavior unchanged for legacy boards booting via pdata and | |
868 | * auto-detect timings only when booting with a device tree. | |
869 | */ | |
870 | if (np) | |
871 | chip->setup_data_interface = s3c2410_nand_setup_data_interface; | |
872 | ||
2c06a082 BD |
873 | switch (info->cpu_type) { |
874 | case TYPE_S3C2410: | |
875 | chip->IO_ADDR_W = regs + S3C2410_NFDATA; | |
876 | info->sel_reg = regs + S3C2410_NFCONF; | |
877 | info->sel_bit = S3C2410_NFCONF_nFCE; | |
878 | chip->cmd_ctrl = s3c2410_nand_hwcontrol; | |
879 | chip->dev_ready = s3c2410_nand_devready; | |
880 | break; | |
881 | ||
882 | case TYPE_S3C2440: | |
883 | chip->IO_ADDR_W = regs + S3C2440_NFDATA; | |
884 | info->sel_reg = regs + S3C2440_NFCONT; | |
885 | info->sel_bit = S3C2440_NFCONT_nFCE; | |
886 | chip->cmd_ctrl = s3c2440_nand_hwcontrol; | |
887 | chip->dev_ready = s3c2440_nand_devready; | |
b773bb2e MR |
888 | chip->read_buf = s3c2440_nand_read_buf; |
889 | chip->write_buf = s3c2440_nand_write_buf; | |
2c06a082 BD |
890 | break; |
891 | ||
892 | case TYPE_S3C2412: | |
893 | chip->IO_ADDR_W = regs + S3C2440_NFDATA; | |
894 | info->sel_reg = regs + S3C2440_NFCONT; | |
895 | info->sel_bit = S3C2412_NFCONT_nFCE0; | |
896 | chip->cmd_ctrl = s3c2440_nand_hwcontrol; | |
897 | chip->dev_ready = s3c2412_nand_devready; | |
898 | ||
899 | if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT) | |
900 | dev_info(info->device, "System booted from NAND\n"); | |
901 | ||
902 | break; | |
54cd0208 | 903 | } |
2c06a082 BD |
904 | |
905 | chip->IO_ADDR_R = chip->IO_ADDR_W; | |
a4f957f1 | 906 | |
1da177e4 | 907 | nmtd->info = info; |
1da177e4 LT |
908 | nmtd->set = set; |
909 | ||
e9f66ae2 | 910 | chip->ecc.mode = info->platform->ecc_mode; |
9db41f9e | 911 | |
1c825ad1 SP |
912 | /* |
913 | * If you use u-boot BBT creation code, specifying this flag will | |
914 | * let the kernel fish out the BBT from the NAND. | |
915 | */ | |
916 | if (set->flash_bbt) | |
bb9ebd4e | 917 | chip->bbt_options |= NAND_BBT_USE_FLASH; |
1da177e4 LT |
918 | } |
919 | ||
3db72151 BD |
920 | /** |
921 | * s3c2410_nand_update_chip - post probe update | |
922 | * @info: The controller instance. | |
923 | * @nmtd: The driver version of the MTD instance. | |
71d54f38 | 924 | * |
af901ca1 | 925 | * This routine is called after the chip probe has successfully completed |
3db72151 BD |
926 | * and the relevant per-chip information updated. This call ensure that |
927 | * we update the internal state accordingly. | |
928 | * | |
929 | * The internal state is currently limited to the ECC state information. | |
930 | */ | |
e9f66ae2 SP |
931 | static int s3c2410_nand_update_chip(struct s3c2410_nand_info *info, |
932 | struct s3c2410_nand_mtd *nmtd) | |
71d54f38 BD |
933 | { |
934 | struct nand_chip *chip = &nmtd->chip; | |
935 | ||
e9f66ae2 | 936 | switch (chip->ecc.mode) { |
71d54f38 | 937 | |
e9f66ae2 SP |
938 | case NAND_ECC_NONE: |
939 | dev_info(info->device, "ECC disabled\n"); | |
940 | break; | |
941 | ||
942 | case NAND_ECC_SOFT: | |
943 | /* | |
944 | * This driver expects Hamming based ECC when ecc_mode is set | |
945 | * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to | |
946 | * avoid adding an extra ecc_algo field to | |
947 | * s3c2410_platform_nand. | |
948 | */ | |
949 | chip->ecc.algo = NAND_ECC_HAMMING; | |
950 | dev_info(info->device, "soft ECC\n"); | |
951 | break; | |
952 | ||
953 | case NAND_ECC_HW: | |
954 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; | |
955 | chip->ecc.correct = s3c2410_nand_correct_data; | |
956 | chip->ecc.strength = 1; | |
957 | ||
958 | switch (info->cpu_type) { | |
959 | case TYPE_S3C2410: | |
960 | chip->ecc.hwctl = s3c2410_nand_enable_hwecc; | |
961 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; | |
962 | break; | |
963 | ||
964 | case TYPE_S3C2412: | |
965 | chip->ecc.hwctl = s3c2412_nand_enable_hwecc; | |
966 | chip->ecc.calculate = s3c2412_nand_calculate_ecc; | |
967 | break; | |
968 | ||
969 | case TYPE_S3C2440: | |
970 | chip->ecc.hwctl = s3c2440_nand_enable_hwecc; | |
971 | chip->ecc.calculate = s3c2440_nand_calculate_ecc; | |
972 | break; | |
973 | } | |
974 | ||
975 | dev_dbg(info->device, "chip %p => page shift %d\n", | |
976 | chip, chip->page_shift); | |
8c3e843d | 977 | |
48fc7f7e | 978 | /* change the behaviour depending on whether we are using |
71d54f38 | 979 | * the large or small page nand device */ |
e9f66ae2 SP |
980 | if (chip->page_shift > 10) { |
981 | chip->ecc.size = 256; | |
982 | chip->ecc.bytes = 3; | |
983 | } else { | |
984 | chip->ecc.size = 512; | |
985 | chip->ecc.bytes = 3; | |
986 | mtd_set_ooblayout(nand_to_mtd(chip), | |
987 | &s3c2410_ooblayout_ops); | |
988 | } | |
71d54f38 | 989 | |
e9f66ae2 SP |
990 | dev_info(info->device, "hardware ECC\n"); |
991 | break; | |
992 | ||
993 | default: | |
994 | dev_err(info->device, "invalid ECC mode!\n"); | |
995 | return -EINVAL; | |
71d54f38 | 996 | } |
e9f66ae2 | 997 | |
1c825ad1 SP |
998 | if (chip->bbt_options & NAND_BBT_USE_FLASH) |
999 | chip->options |= NAND_SKIP_BBTSCAN; | |
1000 | ||
1001 | return 0; | |
1002 | } | |
1003 | ||
1004 | static const struct of_device_id s3c24xx_nand_dt_ids[] = { | |
1005 | { | |
1006 | .compatible = "samsung,s3c2410-nand", | |
1007 | .data = &s3c2410_nand_devtype_data, | |
1008 | }, { | |
1009 | /* also compatible with s3c6400 */ | |
1010 | .compatible = "samsung,s3c2412-nand", | |
1011 | .data = &s3c2412_nand_devtype_data, | |
1012 | }, { | |
1013 | .compatible = "samsung,s3c2440-nand", | |
1014 | .data = &s3c2440_nand_devtype_data, | |
1015 | }, | |
1016 | { /* sentinel */ } | |
1017 | }; | |
1018 | MODULE_DEVICE_TABLE(of, s3c24xx_nand_dt_ids); | |
1019 | ||
1020 | static int s3c24xx_nand_probe_dt(struct platform_device *pdev) | |
1021 | { | |
1022 | const struct s3c24XX_nand_devtype_data *devtype_data; | |
1023 | struct s3c2410_platform_nand *pdata; | |
1024 | struct s3c2410_nand_info *info = platform_get_drvdata(pdev); | |
1025 | struct device_node *np = pdev->dev.of_node, *child; | |
1026 | struct s3c2410_nand_set *sets; | |
1027 | ||
1028 | devtype_data = of_device_get_match_data(&pdev->dev); | |
1029 | if (!devtype_data) | |
1030 | return -ENODEV; | |
1031 | ||
1032 | info->cpu_type = devtype_data->type; | |
1033 | ||
1034 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1035 | if (!pdata) | |
1036 | return -ENOMEM; | |
1037 | ||
1038 | pdev->dev.platform_data = pdata; | |
1039 | ||
1040 | pdata->nr_sets = of_get_child_count(np); | |
1041 | if (!pdata->nr_sets) | |
1042 | return 0; | |
1043 | ||
1044 | sets = devm_kzalloc(&pdev->dev, sizeof(*sets) * pdata->nr_sets, | |
1045 | GFP_KERNEL); | |
1046 | if (!sets) | |
1047 | return -ENOMEM; | |
1048 | ||
1049 | pdata->sets = sets; | |
1050 | ||
1051 | for_each_available_child_of_node(np, child) { | |
1052 | sets->name = (char *)child->name; | |
1053 | sets->of_node = child; | |
1054 | sets->nr_chips = 1; | |
1055 | ||
1056 | of_node_get(child); | |
1057 | ||
1058 | sets++; | |
1059 | } | |
1060 | ||
1061 | return 0; | |
1062 | } | |
1063 | ||
1064 | static int s3c24xx_nand_probe_pdata(struct platform_device *pdev) | |
1065 | { | |
1066 | struct s3c2410_nand_info *info = platform_get_drvdata(pdev); | |
1067 | ||
1068 | info->cpu_type = platform_get_device_id(pdev)->driver_data; | |
1069 | ||
e9f66ae2 | 1070 | return 0; |
71d54f38 BD |
1071 | } |
1072 | ||
ec0482e6 | 1073 | /* s3c24xx_nand_probe |
1da177e4 LT |
1074 | * |
1075 | * called by device layer when it finds a device matching | |
1076 | * one our driver can handled. This code checks to see if | |
1077 | * it can allocate all necessary resources then calls the | |
1078 | * nand layer to look for devices | |
1079 | */ | |
ec0482e6 | 1080 | static int s3c24xx_nand_probe(struct platform_device *pdev) |
1da177e4 | 1081 | { |
1c825ad1 | 1082 | struct s3c2410_platform_nand *plat; |
1da177e4 LT |
1083 | struct s3c2410_nand_info *info; |
1084 | struct s3c2410_nand_mtd *nmtd; | |
1085 | struct s3c2410_nand_set *sets; | |
1086 | struct resource *res; | |
1087 | int err = 0; | |
1088 | int size; | |
1089 | int nr_sets; | |
1090 | int setno; | |
1091 | ||
6f32a3e2 | 1092 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); |
1da177e4 | 1093 | if (info == NULL) { |
1da177e4 LT |
1094 | err = -ENOMEM; |
1095 | goto exit_error; | |
1096 | } | |
1097 | ||
3ae5eaec | 1098 | platform_set_drvdata(pdev, info); |
1da177e4 | 1099 | |
d45bc58d | 1100 | nand_hw_control_init(&info->controller); |
1da177e4 LT |
1101 | |
1102 | /* get the clock source and enable it */ | |
1103 | ||
6f32a3e2 | 1104 | info->clk = devm_clk_get(&pdev->dev, "nand"); |
1da177e4 | 1105 | if (IS_ERR(info->clk)) { |
898eb71c | 1106 | dev_err(&pdev->dev, "failed to get clock\n"); |
1da177e4 LT |
1107 | err = -ENOENT; |
1108 | goto exit_error; | |
1109 | } | |
1110 | ||
ac497c16 | 1111 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); |
1da177e4 | 1112 | |
1c825ad1 SP |
1113 | if (pdev->dev.of_node) |
1114 | err = s3c24xx_nand_probe_dt(pdev); | |
1115 | else | |
1116 | err = s3c24xx_nand_probe_pdata(pdev); | |
1117 | ||
1118 | if (err) | |
1119 | goto exit_error; | |
1120 | ||
1121 | plat = to_nand_plat(pdev); | |
1122 | ||
1da177e4 LT |
1123 | /* allocate and map the resource */ |
1124 | ||
a4f957f1 | 1125 | /* currently we assume we have the one resource */ |
6f32a3e2 | 1126 | res = pdev->resource; |
fc161c4e | 1127 | size = resource_size(res); |
1da177e4 | 1128 | |
6f32a3e2 SK |
1129 | info->device = &pdev->dev; |
1130 | info->platform = plat; | |
1da177e4 | 1131 | |
b0de774c TR |
1132 | info->regs = devm_ioremap_resource(&pdev->dev, res); |
1133 | if (IS_ERR(info->regs)) { | |
1134 | err = PTR_ERR(info->regs); | |
1da177e4 | 1135 | goto exit_error; |
61b03bd7 | 1136 | } |
1da177e4 | 1137 | |
3ae5eaec | 1138 | dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs); |
1da177e4 | 1139 | |
1da177e4 LT |
1140 | sets = (plat != NULL) ? plat->sets : NULL; |
1141 | nr_sets = (plat != NULL) ? plat->nr_sets : 1; | |
1142 | ||
1143 | info->mtd_count = nr_sets; | |
1144 | ||
1145 | /* allocate our information */ | |
1146 | ||
1147 | size = nr_sets * sizeof(*info->mtds); | |
6f32a3e2 | 1148 | info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); |
1da177e4 | 1149 | if (info->mtds == NULL) { |
1da177e4 LT |
1150 | err = -ENOMEM; |
1151 | goto exit_error; | |
1152 | } | |
1153 | ||
1da177e4 LT |
1154 | /* initialise all possible chips */ |
1155 | ||
1156 | nmtd = info->mtds; | |
1157 | ||
1158 | for (setno = 0; setno < nr_sets; setno++, nmtd++) { | |
7208b997 BB |
1159 | struct mtd_info *mtd = nand_to_mtd(&nmtd->chip); |
1160 | ||
f938bc56 SK |
1161 | pr_debug("initialising set %d (%p, info %p)\n", |
1162 | setno, nmtd, info); | |
61b03bd7 | 1163 | |
7208b997 | 1164 | mtd->dev.parent = &pdev->dev; |
1da177e4 LT |
1165 | s3c2410_nand_init_chip(info, nmtd, sets); |
1166 | ||
7208b997 | 1167 | nmtd->scan_res = nand_scan_ident(mtd, |
5e81e88a DW |
1168 | (sets) ? sets->nr_chips : 1, |
1169 | NULL); | |
1da177e4 LT |
1170 | |
1171 | if (nmtd->scan_res == 0) { | |
e9f66ae2 SP |
1172 | err = s3c2410_nand_update_chip(info, nmtd); |
1173 | if (err < 0) | |
1174 | goto exit_error; | |
7208b997 | 1175 | nand_scan_tail(mtd); |
1da177e4 LT |
1176 | s3c2410_nand_add_partition(info, nmtd, sets); |
1177 | } | |
1178 | ||
1179 | if (sets != NULL) | |
1180 | sets++; | |
1181 | } | |
61b03bd7 | 1182 | |
1c825ad1 SP |
1183 | /* initialise the hardware */ |
1184 | err = s3c2410_nand_inithw(info); | |
1185 | if (err != 0) | |
1186 | goto exit_error; | |
1187 | ||
30821fee BD |
1188 | err = s3c2410_nand_cpufreq_register(info); |
1189 | if (err < 0) { | |
1190 | dev_err(&pdev->dev, "failed to init cpufreq support\n"); | |
1191 | goto exit_error; | |
1192 | } | |
1193 | ||
ac497c16 | 1194 | if (allow_clk_suspend(info)) { |
d1fef3c5 | 1195 | dev_info(&pdev->dev, "clock idle support enabled\n"); |
ac497c16 | 1196 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); |
d1fef3c5 BD |
1197 | } |
1198 | ||
1da177e4 LT |
1199 | return 0; |
1200 | ||
1201 | exit_error: | |
ec0482e6 | 1202 | s3c24xx_nand_remove(pdev); |
1da177e4 LT |
1203 | |
1204 | if (err == 0) | |
1205 | err = -EINVAL; | |
1206 | return err; | |
1207 | } | |
1208 | ||
d1fef3c5 BD |
1209 | /* PM Support */ |
1210 | #ifdef CONFIG_PM | |
1211 | ||
1212 | static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm) | |
1213 | { | |
1214 | struct s3c2410_nand_info *info = platform_get_drvdata(dev); | |
1215 | ||
1216 | if (info) { | |
09160832 | 1217 | info->save_sel = readl(info->sel_reg); |
03680b1e BD |
1218 | |
1219 | /* For the moment, we must ensure nFCE is high during | |
1220 | * the time we are suspended. This really should be | |
1221 | * handled by suspending the MTDs we are using, but | |
1222 | * that is currently not the case. */ | |
1223 | ||
09160832 | 1224 | writel(info->save_sel | info->sel_bit, info->sel_reg); |
03680b1e | 1225 | |
ac497c16 | 1226 | s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); |
d1fef3c5 BD |
1227 | } |
1228 | ||
1229 | return 0; | |
1230 | } | |
1231 | ||
1232 | static int s3c24xx_nand_resume(struct platform_device *dev) | |
1233 | { | |
1234 | struct s3c2410_nand_info *info = platform_get_drvdata(dev); | |
09160832 | 1235 | unsigned long sel; |
d1fef3c5 BD |
1236 | |
1237 | if (info) { | |
ac497c16 | 1238 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); |
30821fee | 1239 | s3c2410_nand_inithw(info); |
d1fef3c5 | 1240 | |
03680b1e BD |
1241 | /* Restore the state of the nFCE line. */ |
1242 | ||
09160832 BD |
1243 | sel = readl(info->sel_reg); |
1244 | sel &= ~info->sel_bit; | |
1245 | sel |= info->save_sel & info->sel_bit; | |
1246 | writel(sel, info->sel_reg); | |
03680b1e | 1247 | |
ac497c16 | 1248 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); |
d1fef3c5 BD |
1249 | } |
1250 | ||
1251 | return 0; | |
1252 | } | |
1253 | ||
1254 | #else | |
1255 | #define s3c24xx_nand_suspend NULL | |
1256 | #define s3c24xx_nand_resume NULL | |
1257 | #endif | |
1258 | ||
a4f957f1 BD |
1259 | /* driver device registration */ |
1260 | ||
0abe75d2 | 1261 | static const struct platform_device_id s3c24xx_driver_ids[] = { |
ec0482e6 BD |
1262 | { |
1263 | .name = "s3c2410-nand", | |
1264 | .driver_data = TYPE_S3C2410, | |
1265 | }, { | |
1266 | .name = "s3c2440-nand", | |
1267 | .driver_data = TYPE_S3C2440, | |
1268 | }, { | |
1269 | .name = "s3c2412-nand", | |
1270 | .driver_data = TYPE_S3C2412, | |
9dbc0902 PK |
1271 | }, { |
1272 | .name = "s3c6400-nand", | |
1273 | .driver_data = TYPE_S3C2412, /* compatible with 2412 */ | |
3ae5eaec | 1274 | }, |
ec0482e6 | 1275 | { } |
1da177e4 LT |
1276 | }; |
1277 | ||
ec0482e6 | 1278 | MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); |
a4f957f1 | 1279 | |
ec0482e6 BD |
1280 | static struct platform_driver s3c24xx_nand_driver = { |
1281 | .probe = s3c24xx_nand_probe, | |
1282 | .remove = s3c24xx_nand_remove, | |
2c06a082 BD |
1283 | .suspend = s3c24xx_nand_suspend, |
1284 | .resume = s3c24xx_nand_resume, | |
ec0482e6 | 1285 | .id_table = s3c24xx_driver_ids, |
2c06a082 | 1286 | .driver = { |
ec0482e6 | 1287 | .name = "s3c24xx-nand", |
1c825ad1 | 1288 | .of_match_table = s3c24xx_nand_dt_ids, |
2c06a082 BD |
1289 | }, |
1290 | }; | |
1291 | ||
056fcab5 | 1292 | module_platform_driver(s3c24xx_nand_driver); |
1da177e4 LT |
1293 | |
1294 | MODULE_LICENSE("GPL"); | |
1295 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
a4f957f1 | 1296 | MODULE_DESCRIPTION("S3C24XX MTD NAND driver"); |