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Commit | Line | Data |
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6028aa01 YS |
1 | /* |
2 | * SuperH FLCTL nand controller | |
3 | * | |
b79c7adf MD |
4 | * Copyright (c) 2008 Renesas Solutions Corp. |
5 | * Copyright (c) 2008 Atom Create Engineering Co., Ltd. | |
6028aa01 | 6 | * |
b79c7adf | 7 | * Based on fsl_elbc_nand.c, Copyright (c) 2006-2007 Freescale Semiconductor |
6028aa01 YS |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/delay.h> | |
3c7ea4ec | 27 | #include <linux/interrupt.h> |
6028aa01 YS |
28 | #include <linux/io.h> |
29 | #include <linux/platform_device.h> | |
cfe78194 | 30 | #include <linux/pm_runtime.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
6028aa01 YS |
32 | |
33 | #include <linux/mtd/mtd.h> | |
34 | #include <linux/mtd/nand.h> | |
35 | #include <linux/mtd/partitions.h> | |
36 | #include <linux/mtd/sh_flctl.h> | |
37 | ||
38 | static struct nand_ecclayout flctl_4secc_oob_16 = { | |
39 | .eccbytes = 10, | |
40 | .eccpos = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, | |
41 | .oobfree = { | |
42 | {.offset = 12, | |
43 | . length = 4} }, | |
44 | }; | |
45 | ||
46 | static struct nand_ecclayout flctl_4secc_oob_64 = { | |
aa32d1f0 BH |
47 | .eccbytes = 4 * 10, |
48 | .eccpos = { | |
49 | 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, | |
50 | 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, | |
51 | 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, | |
52 | 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }, | |
6028aa01 | 53 | .oobfree = { |
aa32d1f0 BH |
54 | {.offset = 2, .length = 4}, |
55 | {.offset = 16, .length = 6}, | |
56 | {.offset = 32, .length = 6}, | |
57 | {.offset = 48, .length = 6} }, | |
6028aa01 YS |
58 | }; |
59 | ||
60 | static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; | |
61 | ||
62 | static struct nand_bbt_descr flctl_4secc_smallpage = { | |
63 | .options = NAND_BBT_SCAN2NDPAGE, | |
64 | .offs = 11, | |
65 | .len = 1, | |
66 | .pattern = scan_ff_pattern, | |
67 | }; | |
68 | ||
69 | static struct nand_bbt_descr flctl_4secc_largepage = { | |
c0e6616a | 70 | .options = NAND_BBT_SCAN2NDPAGE, |
aa32d1f0 | 71 | .offs = 0, |
6028aa01 YS |
72 | .len = 2, |
73 | .pattern = scan_ff_pattern, | |
74 | }; | |
75 | ||
76 | static void empty_fifo(struct sh_flctl *flctl) | |
77 | { | |
3c7ea4ec BH |
78 | writel(flctl->flintdmacr_base | AC1CLR | AC0CLR, FLINTDMACR(flctl)); |
79 | writel(flctl->flintdmacr_base, FLINTDMACR(flctl)); | |
6028aa01 YS |
80 | } |
81 | ||
82 | static void start_translation(struct sh_flctl *flctl) | |
83 | { | |
84 | writeb(TRSTRT, FLTRCR(flctl)); | |
85 | } | |
86 | ||
b79c7adf MD |
87 | static void timeout_error(struct sh_flctl *flctl, const char *str) |
88 | { | |
25985edc | 89 | dev_err(&flctl->pdev->dev, "Timeout occurred in %s\n", str); |
b79c7adf MD |
90 | } |
91 | ||
6028aa01 YS |
92 | static void wait_completion(struct sh_flctl *flctl) |
93 | { | |
94 | uint32_t timeout = LOOP_TIMEOUT_MAX; | |
95 | ||
96 | while (timeout--) { | |
97 | if (readb(FLTRCR(flctl)) & TREND) { | |
98 | writeb(0x0, FLTRCR(flctl)); | |
99 | return; | |
100 | } | |
101 | udelay(1); | |
102 | } | |
103 | ||
b79c7adf | 104 | timeout_error(flctl, __func__); |
6028aa01 YS |
105 | writeb(0x0, FLTRCR(flctl)); |
106 | } | |
107 | ||
108 | static void set_addr(struct mtd_info *mtd, int column, int page_addr) | |
109 | { | |
110 | struct sh_flctl *flctl = mtd_to_flctl(mtd); | |
111 | uint32_t addr = 0; | |
112 | ||
113 | if (column == -1) { | |
114 | addr = page_addr; /* ERASE1 */ | |
115 | } else if (page_addr != -1) { | |
116 | /* SEQIN, READ0, etc.. */ | |
010ab820 MD |
117 | if (flctl->chip.options & NAND_BUSWIDTH_16) |
118 | column >>= 1; | |
6028aa01 YS |
119 | if (flctl->page_size) { |
120 | addr = column & 0x0FFF; | |
121 | addr |= (page_addr & 0xff) << 16; | |
122 | addr |= ((page_addr >> 8) & 0xff) << 24; | |
123 | /* big than 128MB */ | |
124 | if (flctl->rw_ADRCNT == ADRCNT2_E) { | |
125 | uint32_t addr2; | |
126 | addr2 = (page_addr >> 16) & 0xff; | |
127 | writel(addr2, FLADR2(flctl)); | |
128 | } | |
129 | } else { | |
130 | addr = column; | |
131 | addr |= (page_addr & 0xff) << 8; | |
132 | addr |= ((page_addr >> 8) & 0xff) << 16; | |
133 | addr |= ((page_addr >> 16) & 0xff) << 24; | |
134 | } | |
135 | } | |
136 | writel(addr, FLADR(flctl)); | |
137 | } | |
138 | ||
139 | static void wait_rfifo_ready(struct sh_flctl *flctl) | |
140 | { | |
141 | uint32_t timeout = LOOP_TIMEOUT_MAX; | |
142 | ||
143 | while (timeout--) { | |
144 | uint32_t val; | |
145 | /* check FIFO */ | |
146 | val = readl(FLDTCNTR(flctl)) >> 16; | |
147 | if (val & 0xFF) | |
148 | return; | |
149 | udelay(1); | |
150 | } | |
b79c7adf | 151 | timeout_error(flctl, __func__); |
6028aa01 YS |
152 | } |
153 | ||
154 | static void wait_wfifo_ready(struct sh_flctl *flctl) | |
155 | { | |
156 | uint32_t len, timeout = LOOP_TIMEOUT_MAX; | |
157 | ||
158 | while (timeout--) { | |
159 | /* check FIFO */ | |
160 | len = (readl(FLDTCNTR(flctl)) >> 16) & 0xFF; | |
161 | if (len >= 4) | |
162 | return; | |
163 | udelay(1); | |
164 | } | |
b79c7adf | 165 | timeout_error(flctl, __func__); |
6028aa01 YS |
166 | } |
167 | ||
6667a6d5 BH |
168 | static enum flctl_ecc_res_t wait_recfifo_ready |
169 | (struct sh_flctl *flctl, int sector_number) | |
6028aa01 YS |
170 | { |
171 | uint32_t timeout = LOOP_TIMEOUT_MAX; | |
6028aa01 YS |
172 | void __iomem *ecc_reg[4]; |
173 | int i; | |
6667a6d5 | 174 | int state = FL_SUCCESS; |
6028aa01 YS |
175 | uint32_t data, size; |
176 | ||
6667a6d5 BH |
177 | /* |
178 | * First this loops checks in FLDTCNTR if we are ready to read out the | |
179 | * oob data. This is the case if either all went fine without errors or | |
180 | * if the bottom part of the loop corrected the errors or marked them as | |
181 | * uncorrectable and the controller is given time to push the data into | |
182 | * the FIFO. | |
183 | */ | |
6028aa01 | 184 | while (timeout--) { |
6667a6d5 | 185 | /* check if all is ok and we can read out the OOB */ |
6028aa01 | 186 | size = readl(FLDTCNTR(flctl)) >> 24; |
6667a6d5 BH |
187 | if ((size & 0xFF) == 4) |
188 | return state; | |
189 | ||
190 | /* check if a correction code has been calculated */ | |
191 | if (!(readl(FL4ECCCR(flctl)) & _4ECCEND)) { | |
192 | /* | |
193 | * either we wait for the fifo to be filled or a | |
194 | * correction pattern is being generated | |
195 | */ | |
196 | udelay(1); | |
197 | continue; | |
198 | } | |
6028aa01 | 199 | |
6667a6d5 BH |
200 | /* check for an uncorrectable error */ |
201 | if (readl(FL4ECCCR(flctl)) & _4ECCFA) { | |
202 | /* check if we face a non-empty page */ | |
203 | for (i = 0; i < 512; i++) { | |
204 | if (flctl->done_buff[i] != 0xff) { | |
205 | state = FL_ERROR; /* can't correct */ | |
206 | break; | |
207 | } | |
208 | } | |
6028aa01 | 209 | |
6667a6d5 BH |
210 | if (state == FL_SUCCESS) |
211 | dev_dbg(&flctl->pdev->dev, | |
212 | "reading empty sector %d, ecc error ignored\n", | |
213 | sector_number); | |
214 | ||
215 | writel(0, FL4ECCCR(flctl)); | |
6028aa01 | 216 | continue; |
6667a6d5 | 217 | } |
6028aa01 YS |
218 | |
219 | /* start error correction */ | |
220 | ecc_reg[0] = FL4ECCRESULT0(flctl); | |
221 | ecc_reg[1] = FL4ECCRESULT1(flctl); | |
222 | ecc_reg[2] = FL4ECCRESULT2(flctl); | |
223 | ecc_reg[3] = FL4ECCRESULT3(flctl); | |
224 | ||
225 | for (i = 0; i < 3; i++) { | |
6667a6d5 BH |
226 | uint8_t org; |
227 | int index; | |
228 | ||
6028aa01 | 229 | data = readl(ecc_reg[i]); |
6028aa01 | 230 | |
6667a6d5 BH |
231 | if (flctl->page_size) |
232 | index = (512 * sector_number) + | |
233 | (data >> 16); | |
234 | else | |
235 | index = data >> 16; | |
236 | ||
237 | org = flctl->done_buff[index]; | |
238 | flctl->done_buff[index] = org ^ (data & 0xFF); | |
239 | } | |
240 | state = FL_REPAIRABLE; | |
6028aa01 YS |
241 | writel(0, FL4ECCCR(flctl)); |
242 | } | |
243 | ||
b79c7adf | 244 | timeout_error(flctl, __func__); |
6667a6d5 | 245 | return FL_TIMEOUT; /* timeout */ |
6028aa01 YS |
246 | } |
247 | ||
248 | static void wait_wecfifo_ready(struct sh_flctl *flctl) | |
249 | { | |
250 | uint32_t timeout = LOOP_TIMEOUT_MAX; | |
251 | uint32_t len; | |
252 | ||
253 | while (timeout--) { | |
254 | /* check FLECFIFO */ | |
255 | len = (readl(FLDTCNTR(flctl)) >> 24) & 0xFF; | |
256 | if (len >= 4) | |
257 | return; | |
258 | udelay(1); | |
259 | } | |
b79c7adf | 260 | timeout_error(flctl, __func__); |
6028aa01 YS |
261 | } |
262 | ||
263 | static void read_datareg(struct sh_flctl *flctl, int offset) | |
264 | { | |
265 | unsigned long data; | |
266 | unsigned long *buf = (unsigned long *)&flctl->done_buff[offset]; | |
267 | ||
268 | wait_completion(flctl); | |
269 | ||
270 | data = readl(FLDATAR(flctl)); | |
271 | *buf = le32_to_cpu(data); | |
272 | } | |
273 | ||
274 | static void read_fiforeg(struct sh_flctl *flctl, int rlen, int offset) | |
275 | { | |
276 | int i, len_4align; | |
277 | unsigned long *buf = (unsigned long *)&flctl->done_buff[offset]; | |
6028aa01 YS |
278 | |
279 | len_4align = (rlen + 3) / 4; | |
280 | ||
281 | for (i = 0; i < len_4align; i++) { | |
282 | wait_rfifo_ready(flctl); | |
3166df0d | 283 | buf[i] = readl(FLDTFIFO(flctl)); |
6028aa01 YS |
284 | buf[i] = be32_to_cpu(buf[i]); |
285 | } | |
286 | } | |
287 | ||
6667a6d5 BH |
288 | static enum flctl_ecc_res_t read_ecfiforeg |
289 | (struct sh_flctl *flctl, uint8_t *buff, int sector) | |
6028aa01 YS |
290 | { |
291 | int i; | |
6667a6d5 | 292 | enum flctl_ecc_res_t res; |
6028aa01 | 293 | unsigned long *ecc_buf = (unsigned long *)buff; |
6028aa01 | 294 | |
6667a6d5 BH |
295 | res = wait_recfifo_ready(flctl , sector); |
296 | ||
297 | if (res != FL_ERROR) { | |
298 | for (i = 0; i < 4; i++) { | |
299 | ecc_buf[i] = readl(FLECFIFO(flctl)); | |
300 | ecc_buf[i] = be32_to_cpu(ecc_buf[i]); | |
301 | } | |
6028aa01 YS |
302 | } |
303 | ||
6667a6d5 | 304 | return res; |
6028aa01 YS |
305 | } |
306 | ||
307 | static void write_fiforeg(struct sh_flctl *flctl, int rlen, int offset) | |
308 | { | |
309 | int i, len_4align; | |
310 | unsigned long *data = (unsigned long *)&flctl->done_buff[offset]; | |
311 | void *fifo_addr = (void *)FLDTFIFO(flctl); | |
312 | ||
313 | len_4align = (rlen + 3) / 4; | |
314 | for (i = 0; i < len_4align; i++) { | |
315 | wait_wfifo_ready(flctl); | |
316 | writel(cpu_to_be32(data[i]), fifo_addr); | |
317 | } | |
318 | } | |
319 | ||
3166df0d BH |
320 | static void write_ec_fiforeg(struct sh_flctl *flctl, int rlen, int offset) |
321 | { | |
322 | int i, len_4align; | |
323 | unsigned long *data = (unsigned long *)&flctl->done_buff[offset]; | |
324 | ||
325 | len_4align = (rlen + 3) / 4; | |
326 | for (i = 0; i < len_4align; i++) { | |
327 | wait_wecfifo_ready(flctl); | |
328 | writel(cpu_to_be32(data[i]), FLECFIFO(flctl)); | |
329 | } | |
330 | } | |
331 | ||
6028aa01 YS |
332 | static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_val) |
333 | { | |
334 | struct sh_flctl *flctl = mtd_to_flctl(mtd); | |
0b3f0d12 | 335 | uint32_t flcmncr_val = flctl->flcmncr_base & ~SEL_16BIT; |
6028aa01 YS |
336 | uint32_t flcmdcr_val, addr_len_bytes = 0; |
337 | ||
338 | /* Set SNAND bit if page size is 2048byte */ | |
339 | if (flctl->page_size) | |
340 | flcmncr_val |= SNAND_E; | |
341 | else | |
342 | flcmncr_val &= ~SNAND_E; | |
343 | ||
344 | /* default FLCMDCR val */ | |
345 | flcmdcr_val = DOCMD1_E | DOADR_E; | |
346 | ||
347 | /* Set for FLCMDCR */ | |
348 | switch (cmd) { | |
349 | case NAND_CMD_ERASE1: | |
350 | addr_len_bytes = flctl->erase_ADRCNT; | |
351 | flcmdcr_val |= DOCMD2_E; | |
352 | break; | |
353 | case NAND_CMD_READ0: | |
354 | case NAND_CMD_READOOB: | |
dd5ab248 | 355 | case NAND_CMD_RNDOUT: |
6028aa01 YS |
356 | addr_len_bytes = flctl->rw_ADRCNT; |
357 | flcmdcr_val |= CDSRC_E; | |
010ab820 MD |
358 | if (flctl->chip.options & NAND_BUSWIDTH_16) |
359 | flcmncr_val |= SEL_16BIT; | |
6028aa01 YS |
360 | break; |
361 | case NAND_CMD_SEQIN: | |
362 | /* This case is that cmd is READ0 or READ1 or READ00 */ | |
363 | flcmdcr_val &= ~DOADR_E; /* ONLY execute 1st cmd */ | |
364 | break; | |
365 | case NAND_CMD_PAGEPROG: | |
366 | addr_len_bytes = flctl->rw_ADRCNT; | |
35a34799 | 367 | flcmdcr_val |= DOCMD2_E | CDSRC_E | SELRW; |
010ab820 MD |
368 | if (flctl->chip.options & NAND_BUSWIDTH_16) |
369 | flcmncr_val |= SEL_16BIT; | |
35a34799 YS |
370 | break; |
371 | case NAND_CMD_READID: | |
372 | flcmncr_val &= ~SNAND_E; | |
7b6b2303 | 373 | flcmdcr_val |= CDSRC_E; |
35a34799 YS |
374 | addr_len_bytes = ADRCNT_1; |
375 | break; | |
376 | case NAND_CMD_STATUS: | |
377 | case NAND_CMD_RESET: | |
378 | flcmncr_val &= ~SNAND_E; | |
379 | flcmdcr_val &= ~(DOADR_E | DOSR_E); | |
380 | break; | |
381 | default: | |
382 | break; | |
383 | } | |
384 | ||
385 | /* Set address bytes parameter */ | |
386 | flcmdcr_val |= addr_len_bytes; | |
387 | ||
388 | /* Now actually write */ | |
389 | writel(flcmncr_val, FLCMNCR(flctl)); | |
390 | writel(flcmdcr_val, FLCMDCR(flctl)); | |
391 | writel(flcmcdr_val, FLCMCDR(flctl)); | |
392 | } | |
393 | ||
394 | static int flctl_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, | |
1fbb938d | 395 | uint8_t *buf, int oob_required, int page) |
35a34799 | 396 | { |
50ed399c | 397 | chip->read_buf(mtd, buf, mtd->writesize); |
3166df0d | 398 | chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); |
35a34799 YS |
399 | return 0; |
400 | } | |
401 | ||
fdbad98d | 402 | static int flctl_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
1fbb938d | 403 | const uint8_t *buf, int oob_required) |
35a34799 | 404 | { |
50ed399c | 405 | chip->write_buf(mtd, buf, mtd->writesize); |
3166df0d | 406 | chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); |
fdbad98d | 407 | return 0; |
35a34799 YS |
408 | } |
409 | ||
410 | static void execmd_read_page_sector(struct mtd_info *mtd, int page_addr) | |
411 | { | |
412 | struct sh_flctl *flctl = mtd_to_flctl(mtd); | |
413 | int sector, page_sectors; | |
6667a6d5 | 414 | enum flctl_ecc_res_t ecc_result; |
35a34799 | 415 | |
623c55ca BH |
416 | page_sectors = flctl->page_size ? 4 : 1; |
417 | ||
418 | set_cmd_regs(mtd, NAND_CMD_READ0, | |
419 | (NAND_CMD_READSTART << 8) | NAND_CMD_READ0); | |
35a34799 YS |
420 | |
421 | writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE | _4ECCCORRECT, | |
422 | FLCMNCR(flctl)); | |
623c55ca BH |
423 | writel(readl(FLCMDCR(flctl)) | page_sectors, FLCMDCR(flctl)); |
424 | writel(page_addr << 2, FLADR(flctl)); | |
35a34799 | 425 | |
623c55ca BH |
426 | empty_fifo(flctl); |
427 | start_translation(flctl); | |
35a34799 YS |
428 | |
429 | for (sector = 0; sector < page_sectors; sector++) { | |
35a34799 YS |
430 | read_fiforeg(flctl, 512, 512 * sector); |
431 | ||
6667a6d5 | 432 | ecc_result = read_ecfiforeg(flctl, |
c0e6616a YS |
433 | &flctl->done_buff[mtd->writesize + 16 * sector], |
434 | sector); | |
35a34799 | 435 | |
6667a6d5 BH |
436 | switch (ecc_result) { |
437 | case FL_REPAIRABLE: | |
438 | dev_info(&flctl->pdev->dev, | |
439 | "applied ecc on page 0x%x", page_addr); | |
440 | flctl->mtd.ecc_stats.corrected++; | |
441 | break; | |
442 | case FL_ERROR: | |
443 | dev_warn(&flctl->pdev->dev, | |
444 | "page 0x%x contains corrupted data\n", | |
445 | page_addr); | |
446 | flctl->mtd.ecc_stats.failed++; | |
447 | break; | |
448 | default: | |
449 | ; | |
450 | } | |
35a34799 | 451 | } |
623c55ca BH |
452 | |
453 | wait_completion(flctl); | |
454 | ||
35a34799 YS |
455 | writel(readl(FLCMNCR(flctl)) & ~(ACM_SACCES_MODE | _4ECCCORRECT), |
456 | FLCMNCR(flctl)); | |
457 | } | |
458 | ||
459 | static void execmd_read_oob(struct mtd_info *mtd, int page_addr) | |
460 | { | |
461 | struct sh_flctl *flctl = mtd_to_flctl(mtd); | |
ef4ce0bc BH |
462 | int page_sectors = flctl->page_size ? 4 : 1; |
463 | int i; | |
35a34799 YS |
464 | |
465 | set_cmd_regs(mtd, NAND_CMD_READ0, | |
466 | (NAND_CMD_READSTART << 8) | NAND_CMD_READ0); | |
467 | ||
468 | empty_fifo(flctl); | |
35a34799 | 469 | |
ef4ce0bc BH |
470 | for (i = 0; i < page_sectors; i++) { |
471 | set_addr(mtd, (512 + 16) * i + 512 , page_addr); | |
35a34799 YS |
472 | writel(16, FLDTCNTR(flctl)); |
473 | ||
474 | start_translation(flctl); | |
ef4ce0bc | 475 | read_fiforeg(flctl, 16, 16 * i); |
35a34799 YS |
476 | wait_completion(flctl); |
477 | } | |
478 | } | |
479 | ||
480 | static void execmd_write_page_sector(struct mtd_info *mtd) | |
481 | { | |
482 | struct sh_flctl *flctl = mtd_to_flctl(mtd); | |
3166df0d | 483 | int page_addr = flctl->seqin_page_addr; |
35a34799 YS |
484 | int sector, page_sectors; |
485 | ||
623c55ca | 486 | page_sectors = flctl->page_size ? 4 : 1; |
35a34799 YS |
487 | |
488 | set_cmd_regs(mtd, NAND_CMD_PAGEPROG, | |
489 | (NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN); | |
490 | ||
623c55ca BH |
491 | empty_fifo(flctl); |
492 | writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE, FLCMNCR(flctl)); | |
493 | writel(readl(FLCMDCR(flctl)) | page_sectors, FLCMDCR(flctl)); | |
494 | writel(page_addr << 2, FLADR(flctl)); | |
495 | start_translation(flctl); | |
35a34799 | 496 | |
623c55ca | 497 | for (sector = 0; sector < page_sectors; sector++) { |
35a34799 | 498 | write_fiforeg(flctl, 512, 512 * sector); |
3166df0d | 499 | write_ec_fiforeg(flctl, 16, mtd->writesize + 16 * sector); |
35a34799 YS |
500 | } |
501 | ||
623c55ca | 502 | wait_completion(flctl); |
35a34799 YS |
503 | writel(readl(FLCMNCR(flctl)) & ~ACM_SACCES_MODE, FLCMNCR(flctl)); |
504 | } | |
505 | ||
506 | static void execmd_write_oob(struct mtd_info *mtd) | |
507 | { | |
508 | struct sh_flctl *flctl = mtd_to_flctl(mtd); | |
509 | int page_addr = flctl->seqin_page_addr; | |
510 | int sector, page_sectors; | |
511 | ||
ef4ce0bc | 512 | page_sectors = flctl->page_size ? 4 : 1; |
35a34799 YS |
513 | |
514 | set_cmd_regs(mtd, NAND_CMD_PAGEPROG, | |
515 | (NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN); | |
516 | ||
ef4ce0bc | 517 | for (sector = 0; sector < page_sectors; sector++) { |
35a34799 YS |
518 | empty_fifo(flctl); |
519 | set_addr(mtd, sector * 528 + 512, page_addr); | |
520 | writel(16, FLDTCNTR(flctl)); /* set read size */ | |
521 | ||
522 | start_translation(flctl); | |
523 | write_fiforeg(flctl, 16, 16 * sector); | |
524 | wait_completion(flctl); | |
525 | } | |
526 | } | |
527 | ||
528 | static void flctl_cmdfunc(struct mtd_info *mtd, unsigned int command, | |
529 | int column, int page_addr) | |
530 | { | |
531 | struct sh_flctl *flctl = mtd_to_flctl(mtd); | |
532 | uint32_t read_cmd = 0; | |
533 | ||
cfe78194 BH |
534 | pm_runtime_get_sync(&flctl->pdev->dev); |
535 | ||
35a34799 YS |
536 | flctl->read_bytes = 0; |
537 | if (command != NAND_CMD_PAGEPROG) | |
538 | flctl->index = 0; | |
539 | ||
540 | switch (command) { | |
541 | case NAND_CMD_READ1: | |
542 | case NAND_CMD_READ0: | |
543 | if (flctl->hwecc) { | |
544 | /* read page with hwecc */ | |
545 | execmd_read_page_sector(mtd, page_addr); | |
546 | break; | |
547 | } | |
35a34799 YS |
548 | if (flctl->page_size) |
549 | set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8) | |
550 | | command); | |
551 | else | |
552 | set_cmd_regs(mtd, command, command); | |
553 | ||
554 | set_addr(mtd, 0, page_addr); | |
555 | ||
556 | flctl->read_bytes = mtd->writesize + mtd->oobsize; | |
010ab820 MD |
557 | if (flctl->chip.options & NAND_BUSWIDTH_16) |
558 | column >>= 1; | |
35a34799 YS |
559 | flctl->index += column; |
560 | goto read_normal_exit; | |
561 | ||
562 | case NAND_CMD_READOOB: | |
563 | if (flctl->hwecc) { | |
564 | /* read page with hwecc */ | |
565 | execmd_read_oob(mtd, page_addr); | |
566 | break; | |
567 | } | |
568 | ||
35a34799 YS |
569 | if (flctl->page_size) { |
570 | set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8) | |
571 | | NAND_CMD_READ0); | |
572 | set_addr(mtd, mtd->writesize, page_addr); | |
573 | } else { | |
574 | set_cmd_regs(mtd, command, command); | |
575 | set_addr(mtd, 0, page_addr); | |
576 | } | |
577 | flctl->read_bytes = mtd->oobsize; | |
578 | goto read_normal_exit; | |
579 | ||
dd5ab248 BH |
580 | case NAND_CMD_RNDOUT: |
581 | if (flctl->hwecc) | |
582 | break; | |
583 | ||
584 | if (flctl->page_size) | |
585 | set_cmd_regs(mtd, command, (NAND_CMD_RNDOUTSTART << 8) | |
586 | | command); | |
587 | else | |
588 | set_cmd_regs(mtd, command, command); | |
589 | ||
590 | set_addr(mtd, column, 0); | |
591 | ||
592 | flctl->read_bytes = mtd->writesize + mtd->oobsize - column; | |
593 | goto read_normal_exit; | |
594 | ||
35a34799 | 595 | case NAND_CMD_READID: |
35a34799 | 596 | set_cmd_regs(mtd, command, command); |
35a34799 | 597 | |
7b6b2303 BH |
598 | /* READID is always performed using an 8-bit bus */ |
599 | if (flctl->chip.options & NAND_BUSWIDTH_16) | |
600 | column <<= 1; | |
601 | set_addr(mtd, column, 0); | |
602 | ||
603 | flctl->read_bytes = 8; | |
35a34799 | 604 | writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */ |
abb59ef3 | 605 | empty_fifo(flctl); |
35a34799 | 606 | start_translation(flctl); |
7b6b2303 BH |
607 | read_fiforeg(flctl, flctl->read_bytes, 0); |
608 | wait_completion(flctl); | |
35a34799 YS |
609 | break; |
610 | ||
611 | case NAND_CMD_ERASE1: | |
612 | flctl->erase1_page_addr = page_addr; | |
613 | break; | |
614 | ||
615 | case NAND_CMD_ERASE2: | |
616 | set_cmd_regs(mtd, NAND_CMD_ERASE1, | |
617 | (command << 8) | NAND_CMD_ERASE1); | |
618 | set_addr(mtd, -1, flctl->erase1_page_addr); | |
619 | start_translation(flctl); | |
620 | wait_completion(flctl); | |
621 | break; | |
622 | ||
623 | case NAND_CMD_SEQIN: | |
624 | if (!flctl->page_size) { | |
625 | /* output read command */ | |
626 | if (column >= mtd->writesize) { | |
627 | column -= mtd->writesize; | |
628 | read_cmd = NAND_CMD_READOOB; | |
629 | } else if (column < 256) { | |
630 | read_cmd = NAND_CMD_READ0; | |
631 | } else { | |
632 | column -= 256; | |
633 | read_cmd = NAND_CMD_READ1; | |
634 | } | |
635 | } | |
636 | flctl->seqin_column = column; | |
637 | flctl->seqin_page_addr = page_addr; | |
638 | flctl->seqin_read_cmd = read_cmd; | |
639 | break; | |
640 | ||
641 | case NAND_CMD_PAGEPROG: | |
642 | empty_fifo(flctl); | |
643 | if (!flctl->page_size) { | |
644 | set_cmd_regs(mtd, NAND_CMD_SEQIN, | |
645 | flctl->seqin_read_cmd); | |
646 | set_addr(mtd, -1, -1); | |
647 | writel(0, FLDTCNTR(flctl)); /* set 0 size */ | |
648 | start_translation(flctl); | |
649 | wait_completion(flctl); | |
650 | } | |
651 | if (flctl->hwecc) { | |
652 | /* write page with hwecc */ | |
653 | if (flctl->seqin_column == mtd->writesize) | |
654 | execmd_write_oob(mtd); | |
655 | else if (!flctl->seqin_column) | |
656 | execmd_write_page_sector(mtd); | |
657 | else | |
658 | printk(KERN_ERR "Invalid address !?\n"); | |
659 | break; | |
660 | } | |
661 | set_cmd_regs(mtd, command, (command << 8) | NAND_CMD_SEQIN); | |
662 | set_addr(mtd, flctl->seqin_column, flctl->seqin_page_addr); | |
663 | writel(flctl->index, FLDTCNTR(flctl)); /* set write size */ | |
664 | start_translation(flctl); | |
665 | write_fiforeg(flctl, flctl->index, 0); | |
666 | wait_completion(flctl); | |
667 | break; | |
668 | ||
669 | case NAND_CMD_STATUS: | |
670 | set_cmd_regs(mtd, command, command); | |
671 | set_addr(mtd, -1, -1); | |
672 | ||
673 | flctl->read_bytes = 1; | |
674 | writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */ | |
675 | start_translation(flctl); | |
676 | read_datareg(flctl, 0); /* read and end */ | |
677 | break; | |
678 | ||
679 | case NAND_CMD_RESET: | |
680 | set_cmd_regs(mtd, command, command); | |
681 | set_addr(mtd, -1, -1); | |
682 | ||
683 | writel(0, FLDTCNTR(flctl)); /* set 0 size */ | |
684 | start_translation(flctl); | |
685 | wait_completion(flctl); | |
686 | break; | |
687 | ||
688 | default: | |
689 | break; | |
690 | } | |
cfe78194 | 691 | goto runtime_exit; |
35a34799 YS |
692 | |
693 | read_normal_exit: | |
694 | writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */ | |
abb59ef3 | 695 | empty_fifo(flctl); |
35a34799 YS |
696 | start_translation(flctl); |
697 | read_fiforeg(flctl, flctl->read_bytes, 0); | |
698 | wait_completion(flctl); | |
cfe78194 BH |
699 | runtime_exit: |
700 | pm_runtime_put_sync(&flctl->pdev->dev); | |
35a34799 YS |
701 | return; |
702 | } | |
703 | ||
704 | static void flctl_select_chip(struct mtd_info *mtd, int chipnr) | |
705 | { | |
706 | struct sh_flctl *flctl = mtd_to_flctl(mtd); | |
cfe78194 | 707 | int ret; |
35a34799 YS |
708 | |
709 | switch (chipnr) { | |
710 | case -1: | |
0b3f0d12 | 711 | flctl->flcmncr_base &= ~CE0_ENABLE; |
cfe78194 BH |
712 | |
713 | pm_runtime_get_sync(&flctl->pdev->dev); | |
0b3f0d12 | 714 | writel(flctl->flcmncr_base, FLCMNCR(flctl)); |
cfe78194 BH |
715 | |
716 | if (flctl->qos_request) { | |
717 | dev_pm_qos_remove_request(&flctl->pm_qos); | |
718 | flctl->qos_request = 0; | |
719 | } | |
720 | ||
721 | pm_runtime_put_sync(&flctl->pdev->dev); | |
35a34799 YS |
722 | break; |
723 | case 0: | |
0b3f0d12 | 724 | flctl->flcmncr_base |= CE0_ENABLE; |
cfe78194 BH |
725 | |
726 | if (!flctl->qos_request) { | |
727 | ret = dev_pm_qos_add_request(&flctl->pdev->dev, | |
728 | &flctl->pm_qos, 100); | |
729 | if (ret < 0) | |
730 | dev_err(&flctl->pdev->dev, | |
731 | "PM QoS request failed: %d\n", ret); | |
732 | flctl->qos_request = 1; | |
733 | } | |
734 | ||
735 | if (flctl->holden) { | |
736 | pm_runtime_get_sync(&flctl->pdev->dev); | |
3f2e924b | 737 | writel(HOLDEN, FLHOLDCR(flctl)); |
cfe78194 BH |
738 | pm_runtime_put_sync(&flctl->pdev->dev); |
739 | } | |
35a34799 YS |
740 | break; |
741 | default: | |
742 | BUG(); | |
743 | } | |
744 | } | |
745 | ||
746 | static void flctl_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) | |
747 | { | |
748 | struct sh_flctl *flctl = mtd_to_flctl(mtd); | |
749 | int i, index = flctl->index; | |
750 | ||
751 | for (i = 0; i < len; i++) | |
752 | flctl->done_buff[index + i] = buf[i]; | |
753 | flctl->index += len; | |
754 | } | |
755 | ||
756 | static uint8_t flctl_read_byte(struct mtd_info *mtd) | |
757 | { | |
758 | struct sh_flctl *flctl = mtd_to_flctl(mtd); | |
759 | int index = flctl->index; | |
760 | uint8_t data; | |
761 | ||
762 | data = flctl->done_buff[index]; | |
763 | flctl->index++; | |
764 | return data; | |
765 | } | |
766 | ||
010ab820 MD |
767 | static uint16_t flctl_read_word(struct mtd_info *mtd) |
768 | { | |
769 | struct sh_flctl *flctl = mtd_to_flctl(mtd); | |
770 | int index = flctl->index; | |
771 | uint16_t data; | |
772 | uint16_t *buf = (uint16_t *)&flctl->done_buff[index]; | |
773 | ||
774 | data = *buf; | |
775 | flctl->index += 2; | |
776 | return data; | |
777 | } | |
778 | ||
35a34799 YS |
779 | static void flctl_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
780 | { | |
781 | int i; | |
782 | ||
783 | for (i = 0; i < len; i++) | |
784 | buf[i] = flctl_read_byte(mtd); | |
785 | } | |
786 | ||
787 | static int flctl_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) | |
788 | { | |
789 | int i; | |
790 | ||
791 | for (i = 0; i < len; i++) | |
792 | if (buf[i] != flctl_read_byte(mtd)) | |
793 | return -EFAULT; | |
794 | return 0; | |
795 | } | |
796 | ||
35a34799 YS |
797 | static int flctl_chip_init_tail(struct mtd_info *mtd) |
798 | { | |
799 | struct sh_flctl *flctl = mtd_to_flctl(mtd); | |
800 | struct nand_chip *chip = &flctl->chip; | |
801 | ||
802 | if (mtd->writesize == 512) { | |
803 | flctl->page_size = 0; | |
804 | if (chip->chipsize > (32 << 20)) { | |
805 | /* big than 32MB */ | |
806 | flctl->rw_ADRCNT = ADRCNT_4; | |
807 | flctl->erase_ADRCNT = ADRCNT_3; | |
808 | } else if (chip->chipsize > (2 << 16)) { | |
809 | /* big than 128KB */ | |
810 | flctl->rw_ADRCNT = ADRCNT_3; | |
811 | flctl->erase_ADRCNT = ADRCNT_2; | |
812 | } else { | |
813 | flctl->rw_ADRCNT = ADRCNT_2; | |
814 | flctl->erase_ADRCNT = ADRCNT_1; | |
815 | } | |
816 | } else { | |
817 | flctl->page_size = 1; | |
818 | if (chip->chipsize > (128 << 20)) { | |
819 | /* big than 128MB */ | |
820 | flctl->rw_ADRCNT = ADRCNT2_E; | |
821 | flctl->erase_ADRCNT = ADRCNT_3; | |
822 | } else if (chip->chipsize > (8 << 16)) { | |
823 | /* big than 512KB */ | |
824 | flctl->rw_ADRCNT = ADRCNT_4; | |
825 | flctl->erase_ADRCNT = ADRCNT_2; | |
826 | } else { | |
827 | flctl->rw_ADRCNT = ADRCNT_3; | |
828 | flctl->erase_ADRCNT = ADRCNT_1; | |
829 | } | |
830 | } | |
831 | ||
832 | if (flctl->hwecc) { | |
833 | if (mtd->writesize == 512) { | |
834 | chip->ecc.layout = &flctl_4secc_oob_16; | |
835 | chip->badblock_pattern = &flctl_4secc_smallpage; | |
836 | } else { | |
837 | chip->ecc.layout = &flctl_4secc_oob_64; | |
838 | chip->badblock_pattern = &flctl_4secc_largepage; | |
839 | } | |
840 | ||
841 | chip->ecc.size = 512; | |
842 | chip->ecc.bytes = 10; | |
6a918bad | 843 | chip->ecc.strength = 4; |
35a34799 YS |
844 | chip->ecc.read_page = flctl_read_page_hwecc; |
845 | chip->ecc.write_page = flctl_write_page_hwecc; | |
846 | chip->ecc.mode = NAND_ECC_HW; | |
847 | ||
848 | /* 4 symbols ECC enabled */ | |
aa32d1f0 | 849 | flctl->flcmncr_base |= _4ECCEN; |
35a34799 YS |
850 | } else { |
851 | chip->ecc.mode = NAND_ECC_SOFT; | |
852 | } | |
853 | ||
854 | return 0; | |
855 | } | |
856 | ||
3c7ea4ec BH |
857 | static irqreturn_t flctl_handle_flste(int irq, void *dev_id) |
858 | { | |
859 | struct sh_flctl *flctl = dev_id; | |
860 | ||
861 | dev_err(&flctl->pdev->dev, "flste irq: %x\n", readl(FLINTDMACR(flctl))); | |
862 | writel(flctl->flintdmacr_base, FLINTDMACR(flctl)); | |
863 | ||
864 | return IRQ_HANDLED; | |
865 | } | |
866 | ||
b79c7adf | 867 | static int __devinit flctl_probe(struct platform_device *pdev) |
35a34799 YS |
868 | { |
869 | struct resource *res; | |
870 | struct sh_flctl *flctl; | |
871 | struct mtd_info *flctl_mtd; | |
872 | struct nand_chip *nand; | |
873 | struct sh_flctl_platform_data *pdata; | |
b79c7adf | 874 | int ret = -ENXIO; |
3c7ea4ec | 875 | int irq; |
35a34799 YS |
876 | |
877 | pdata = pdev->dev.platform_data; | |
878 | if (pdata == NULL) { | |
b79c7adf MD |
879 | dev_err(&pdev->dev, "no platform data defined\n"); |
880 | return -EINVAL; | |
35a34799 YS |
881 | } |
882 | ||
883 | flctl = kzalloc(sizeof(struct sh_flctl), GFP_KERNEL); | |
884 | if (!flctl) { | |
b79c7adf | 885 | dev_err(&pdev->dev, "failed to allocate driver data\n"); |
35a34799 YS |
886 | return -ENOMEM; |
887 | } | |
888 | ||
889 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
890 | if (!res) { | |
b79c7adf | 891 | dev_err(&pdev->dev, "failed to get I/O memory\n"); |
cfe78194 | 892 | goto err_iomap; |
35a34799 YS |
893 | } |
894 | ||
cbd38a87 | 895 | flctl->reg = ioremap(res->start, resource_size(res)); |
35a34799 | 896 | if (flctl->reg == NULL) { |
b79c7adf | 897 | dev_err(&pdev->dev, "failed to remap I/O memory\n"); |
cfe78194 | 898 | goto err_iomap; |
35a34799 YS |
899 | } |
900 | ||
3c7ea4ec BH |
901 | irq = platform_get_irq(pdev, 0); |
902 | if (irq < 0) { | |
903 | dev_err(&pdev->dev, "failed to get flste irq data\n"); | |
904 | goto err_flste; | |
905 | } | |
906 | ||
907 | ret = request_irq(irq, flctl_handle_flste, IRQF_SHARED, "flste", flctl); | |
908 | if (ret) { | |
909 | dev_err(&pdev->dev, "request interrupt failed.\n"); | |
910 | goto err_flste; | |
911 | } | |
912 | ||
35a34799 YS |
913 | platform_set_drvdata(pdev, flctl); |
914 | flctl_mtd = &flctl->mtd; | |
915 | nand = &flctl->chip; | |
916 | flctl_mtd->priv = nand; | |
b79c7adf | 917 | flctl->pdev = pdev; |
35a34799 | 918 | flctl->hwecc = pdata->has_hwecc; |
3f2e924b | 919 | flctl->holden = pdata->use_holden; |
3c7ea4ec BH |
920 | flctl->flcmncr_base = pdata->flcmncr_val; |
921 | flctl->flintdmacr_base = flctl->hwecc ? (STERINTE | ECERB) : STERINTE; | |
35a34799 | 922 | |
35a34799 YS |
923 | /* Set address of hardware control function */ |
924 | /* 20 us command delay time */ | |
925 | nand->chip_delay = 20; | |
926 | ||
927 | nand->read_byte = flctl_read_byte; | |
928 | nand->write_buf = flctl_write_buf; | |
929 | nand->read_buf = flctl_read_buf; | |
930 | nand->verify_buf = flctl_verify_buf; | |
931 | nand->select_chip = flctl_select_chip; | |
932 | nand->cmdfunc = flctl_cmdfunc; | |
933 | ||
010ab820 MD |
934 | if (pdata->flcmncr_val & SEL_16BIT) { |
935 | nand->options |= NAND_BUSWIDTH_16; | |
936 | nand->read_word = flctl_read_word; | |
937 | } | |
938 | ||
cfe78194 BH |
939 | pm_runtime_enable(&pdev->dev); |
940 | pm_runtime_resume(&pdev->dev); | |
941 | ||
5e81e88a | 942 | ret = nand_scan_ident(flctl_mtd, 1, NULL); |
35a34799 | 943 | if (ret) |
cfe78194 | 944 | goto err_chip; |
35a34799 YS |
945 | |
946 | ret = flctl_chip_init_tail(flctl_mtd); | |
947 | if (ret) | |
cfe78194 | 948 | goto err_chip; |
35a34799 YS |
949 | |
950 | ret = nand_scan_tail(flctl_mtd); | |
951 | if (ret) | |
cfe78194 | 952 | goto err_chip; |
35a34799 | 953 | |
ee0e87b1 | 954 | mtd_device_register(flctl_mtd, pdata->parts, pdata->nr_parts); |
35a34799 YS |
955 | |
956 | return 0; | |
957 | ||
cfe78194 BH |
958 | err_chip: |
959 | pm_runtime_disable(&pdev->dev); | |
3c7ea4ec BH |
960 | free_irq(irq, flctl); |
961 | err_flste: | |
cb54751d | 962 | iounmap(flctl->reg); |
cfe78194 | 963 | err_iomap: |
35a34799 YS |
964 | kfree(flctl); |
965 | return ret; | |
966 | } | |
967 | ||
b79c7adf | 968 | static int __devexit flctl_remove(struct platform_device *pdev) |
35a34799 YS |
969 | { |
970 | struct sh_flctl *flctl = platform_get_drvdata(pdev); | |
971 | ||
972 | nand_release(&flctl->mtd); | |
cfe78194 | 973 | pm_runtime_disable(&pdev->dev); |
3c7ea4ec | 974 | free_irq(platform_get_irq(pdev, 0), flctl); |
cb54751d | 975 | iounmap(flctl->reg); |
35a34799 YS |
976 | kfree(flctl); |
977 | ||
978 | return 0; | |
979 | } | |
980 | ||
981 | static struct platform_driver flctl_driver = { | |
35a34799 YS |
982 | .remove = flctl_remove, |
983 | .driver = { | |
984 | .name = "sh_flctl", | |
985 | .owner = THIS_MODULE, | |
986 | }, | |
987 | }; | |
988 | ||
989 | static int __init flctl_nand_init(void) | |
990 | { | |
894572a3 | 991 | return platform_driver_probe(&flctl_driver, flctl_probe); |
35a34799 YS |
992 | } |
993 | ||
994 | static void __exit flctl_nand_cleanup(void) | |
995 | { | |
996 | platform_driver_unregister(&flctl_driver); | |
997 | } | |
998 | ||
999 | module_init(flctl_nand_init); | |
1000 | module_exit(flctl_nand_cleanup); | |
1001 | ||
1002 | MODULE_LICENSE("GPL"); | |
1003 | MODULE_AUTHOR("Yoshihiro Shimoda"); | |
1004 | MODULE_DESCRIPTION("SuperH FLCTL driver"); | |
1005 | MODULE_ALIAS("platform:sh_flctl"); |