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59dbc86c MG |
1 | /* |
2 | * Copyright (C) 2016 Sigma Designs | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * version 2 as published by the Free Software Foundation. | |
7 | */ | |
8 | ||
6956e238 MG |
9 | #include <linux/io.h> |
10 | #include <linux/of.h> | |
11 | #include <linux/clk.h> | |
12 | #include <linux/iopoll.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/mtd/nand.h> | |
15 | #include <linux/dmaengine.h> | |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/platform_device.h> | |
18 | ||
19 | /* Offsets relative to chip->base */ | |
20 | #define PBUS_CMD 0 | |
21 | #define PBUS_ADDR 4 | |
22 | #define PBUS_DATA 8 | |
23 | ||
24 | /* Offsets relative to reg_base */ | |
25 | #define NFC_STATUS 0x00 | |
26 | #define NFC_FLASH_CMD 0x04 | |
27 | #define NFC_DEVICE_CFG 0x08 | |
28 | #define NFC_TIMING1 0x0c | |
29 | #define NFC_TIMING2 0x10 | |
30 | #define NFC_XFER_CFG 0x14 | |
31 | #define NFC_PKT_0_CFG 0x18 | |
32 | #define NFC_PKT_N_CFG 0x1c | |
33 | #define NFC_BB_CFG 0x20 | |
34 | #define NFC_ADDR_PAGE 0x24 | |
35 | #define NFC_ADDR_OFFSET 0x28 | |
36 | #define NFC_XFER_STATUS 0x2c | |
37 | ||
38 | /* NFC_STATUS values */ | |
39 | #define CMD_READY BIT(31) | |
40 | ||
41 | /* NFC_FLASH_CMD values */ | |
42 | #define NFC_READ 1 | |
43 | #define NFC_WRITE 2 | |
44 | ||
45 | /* NFC_XFER_STATUS values */ | |
46 | #define PAGE_IS_EMPTY BIT(16) | |
47 | ||
48 | /* Offsets relative to mem_base */ | |
49 | #define METADATA 0x000 | |
50 | #define ERROR_REPORT 0x1c0 | |
51 | ||
52 | /* | |
53 | * Error reports are split in two bytes: | |
54 | * byte 0 for the first packet in the page (PKT_0) | |
55 | * byte 1 for other packets in the page (PKT_N, for N > 0) | |
56 | * ERR_COUNT_PKT_N is the max error count over all but the first packet. | |
57 | */ | |
58 | #define DECODE_OK_PKT_0(v) ((v) & BIT(7)) | |
59 | #define DECODE_OK_PKT_N(v) ((v) & BIT(15)) | |
60 | #define ERR_COUNT_PKT_0(v) (((v) >> 0) & 0x3f) | |
61 | #define ERR_COUNT_PKT_N(v) (((v) >> 8) & 0x3f) | |
62 | ||
63 | /* Offsets relative to pbus_base */ | |
64 | #define PBUS_CS_CTRL 0x83c | |
65 | #define PBUS_PAD_MODE 0x8f0 | |
66 | ||
67 | /* PBUS_CS_CTRL values */ | |
68 | #define PBUS_IORDY BIT(31) | |
69 | ||
70 | /* | |
71 | * PBUS_PAD_MODE values | |
72 | * In raw mode, the driver communicates directly with the NAND chips. | |
73 | * In NFC mode, the NAND Flash controller manages the communication. | |
74 | * We use NFC mode for read and write; raw mode for everything else. | |
75 | */ | |
76 | #define MODE_RAW 0 | |
77 | #define MODE_NFC BIT(31) | |
78 | ||
79 | #define METADATA_SIZE 4 | |
80 | #define BBM_SIZE 6 | |
81 | #define FIELD_ORDER 15 | |
82 | ||
83 | #define MAX_CS 4 | |
84 | ||
85 | struct tango_nfc { | |
86 | struct nand_hw_control hw; | |
87 | void __iomem *reg_base; | |
88 | void __iomem *mem_base; | |
89 | void __iomem *pbus_base; | |
90 | struct tango_chip *chips[MAX_CS]; | |
91 | struct dma_chan *chan; | |
92 | int freq_kHz; | |
93 | }; | |
94 | ||
95 | #define to_tango_nfc(ptr) container_of(ptr, struct tango_nfc, hw) | |
96 | ||
97 | struct tango_chip { | |
98 | struct nand_chip nand_chip; | |
99 | void __iomem *base; | |
100 | u32 timing1; | |
101 | u32 timing2; | |
102 | u32 xfer_cfg; | |
103 | u32 pkt_0_cfg; | |
104 | u32 pkt_n_cfg; | |
105 | u32 bb_cfg; | |
106 | }; | |
107 | ||
108 | #define to_tango_chip(ptr) container_of(ptr, struct tango_chip, nand_chip) | |
109 | ||
110 | #define XFER_CFG(cs, page_count, steps, metadata_size) \ | |
111 | ((cs) << 24 | (page_count) << 16 | (steps) << 8 | (metadata_size)) | |
112 | ||
113 | #define PKT_CFG(size, strength) ((size) << 16 | (strength)) | |
114 | ||
115 | #define BB_CFG(bb_offset, bb_size) ((bb_offset) << 16 | (bb_size)) | |
116 | ||
117 | #define TIMING(t0, t1, t2, t3) ((t0) << 24 | (t1) << 16 | (t2) << 8 | (t3)) | |
118 | ||
119 | static void tango_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) | |
120 | { | |
121 | struct tango_chip *tchip = to_tango_chip(mtd_to_nand(mtd)); | |
122 | ||
123 | if (ctrl & NAND_CLE) | |
124 | writeb_relaxed(dat, tchip->base + PBUS_CMD); | |
125 | ||
126 | if (ctrl & NAND_ALE) | |
127 | writeb_relaxed(dat, tchip->base + PBUS_ADDR); | |
128 | } | |
129 | ||
130 | static int tango_dev_ready(struct mtd_info *mtd) | |
131 | { | |
132 | struct nand_chip *chip = mtd_to_nand(mtd); | |
133 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); | |
134 | ||
135 | return readl_relaxed(nfc->pbus_base + PBUS_CS_CTRL) & PBUS_IORDY; | |
136 | } | |
137 | ||
138 | static u8 tango_read_byte(struct mtd_info *mtd) | |
139 | { | |
140 | struct tango_chip *tchip = to_tango_chip(mtd_to_nand(mtd)); | |
141 | ||
142 | return readb_relaxed(tchip->base + PBUS_DATA); | |
143 | } | |
144 | ||
145 | static void tango_read_buf(struct mtd_info *mtd, u8 *buf, int len) | |
146 | { | |
147 | struct tango_chip *tchip = to_tango_chip(mtd_to_nand(mtd)); | |
148 | ||
149 | ioread8_rep(tchip->base + PBUS_DATA, buf, len); | |
150 | } | |
151 | ||
152 | static void tango_write_buf(struct mtd_info *mtd, const u8 *buf, int len) | |
153 | { | |
154 | struct tango_chip *tchip = to_tango_chip(mtd_to_nand(mtd)); | |
155 | ||
156 | iowrite8_rep(tchip->base + PBUS_DATA, buf, len); | |
157 | } | |
158 | ||
159 | static void tango_select_chip(struct mtd_info *mtd, int idx) | |
160 | { | |
161 | struct nand_chip *chip = mtd_to_nand(mtd); | |
162 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); | |
163 | struct tango_chip *tchip = to_tango_chip(chip); | |
164 | ||
165 | if (idx < 0) | |
166 | return; /* No "chip unselect" function */ | |
167 | ||
168 | writel_relaxed(tchip->timing1, nfc->reg_base + NFC_TIMING1); | |
169 | writel_relaxed(tchip->timing2, nfc->reg_base + NFC_TIMING2); | |
170 | writel_relaxed(tchip->xfer_cfg, nfc->reg_base + NFC_XFER_CFG); | |
171 | writel_relaxed(tchip->pkt_0_cfg, nfc->reg_base + NFC_PKT_0_CFG); | |
172 | writel_relaxed(tchip->pkt_n_cfg, nfc->reg_base + NFC_PKT_N_CFG); | |
173 | writel_relaxed(tchip->bb_cfg, nfc->reg_base + NFC_BB_CFG); | |
174 | } | |
175 | ||
176 | /* | |
177 | * The controller does not check for bitflips in erased pages, | |
178 | * therefore software must check instead. | |
179 | */ | |
180 | static int check_erased_page(struct nand_chip *chip, u8 *buf) | |
181 | { | |
8fcfba07 | 182 | struct mtd_info *mtd = nand_to_mtd(chip); |
6956e238 MG |
183 | u8 *meta = chip->oob_poi + BBM_SIZE; |
184 | u8 *ecc = chip->oob_poi + BBM_SIZE + METADATA_SIZE; | |
185 | const int ecc_size = chip->ecc.bytes; | |
186 | const int pkt_size = chip->ecc.size; | |
187 | int i, res, meta_len, bitflips = 0; | |
188 | ||
189 | for (i = 0; i < chip->ecc.steps; ++i) { | |
190 | meta_len = i ? 0 : METADATA_SIZE; | |
191 | res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size, | |
192 | meta, meta_len, | |
193 | chip->ecc.strength); | |
194 | if (res < 0) | |
8fcfba07 | 195 | mtd->ecc_stats.failed++; |
6956e238 MG |
196 | |
197 | bitflips = max(res, bitflips); | |
198 | buf += pkt_size; | |
199 | ecc += ecc_size; | |
200 | } | |
201 | ||
202 | return bitflips; | |
203 | } | |
204 | ||
205 | static int decode_error_report(struct tango_nfc *nfc) | |
206 | { | |
207 | u32 status, res; | |
208 | ||
209 | status = readl_relaxed(nfc->reg_base + NFC_XFER_STATUS); | |
210 | if (status & PAGE_IS_EMPTY) | |
211 | return 0; | |
212 | ||
213 | res = readl_relaxed(nfc->mem_base + ERROR_REPORT); | |
214 | ||
215 | if (DECODE_OK_PKT_0(res) && DECODE_OK_PKT_N(res)) | |
216 | return max(ERR_COUNT_PKT_0(res), ERR_COUNT_PKT_N(res)); | |
217 | ||
218 | return -EBADMSG; | |
219 | } | |
220 | ||
221 | static void tango_dma_callback(void *arg) | |
222 | { | |
223 | complete(arg); | |
224 | } | |
225 | ||
1932a964 BB |
226 | static int do_dma(struct tango_nfc *nfc, enum dma_data_direction dir, int cmd, |
227 | const void *buf, int len, int page) | |
6956e238 MG |
228 | { |
229 | void __iomem *addr = nfc->reg_base + NFC_STATUS; | |
230 | struct dma_chan *chan = nfc->chan; | |
231 | struct dma_async_tx_descriptor *desc; | |
1932a964 | 232 | enum dma_transfer_direction tdir; |
6956e238 MG |
233 | struct scatterlist sg; |
234 | struct completion tx_done; | |
235 | int err = -EIO; | |
236 | u32 res, val; | |
237 | ||
238 | sg_init_one(&sg, buf, len); | |
239 | if (dma_map_sg(chan->device->dev, &sg, 1, dir) != 1) | |
240 | return -EIO; | |
241 | ||
1932a964 BB |
242 | tdir = dir == DMA_TO_DEVICE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; |
243 | desc = dmaengine_prep_slave_sg(chan, &sg, 1, tdir, DMA_PREP_INTERRUPT); | |
6956e238 MG |
244 | if (!desc) |
245 | goto dma_unmap; | |
246 | ||
247 | desc->callback = tango_dma_callback; | |
248 | desc->callback_param = &tx_done; | |
249 | init_completion(&tx_done); | |
250 | ||
251 | writel_relaxed(MODE_NFC, nfc->pbus_base + PBUS_PAD_MODE); | |
252 | ||
253 | writel_relaxed(page, nfc->reg_base + NFC_ADDR_PAGE); | |
254 | writel_relaxed(0, nfc->reg_base + NFC_ADDR_OFFSET); | |
255 | writel_relaxed(cmd, nfc->reg_base + NFC_FLASH_CMD); | |
256 | ||
257 | dmaengine_submit(desc); | |
258 | dma_async_issue_pending(chan); | |
259 | ||
260 | res = wait_for_completion_timeout(&tx_done, HZ); | |
261 | if (res > 0) | |
262 | err = readl_poll_timeout(addr, val, val & CMD_READY, 0, 1000); | |
263 | ||
264 | writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE); | |
265 | ||
266 | dma_unmap: | |
267 | dma_unmap_sg(chan->device->dev, &sg, 1, dir); | |
268 | ||
269 | return err; | |
270 | } | |
271 | ||
272 | static int tango_read_page(struct mtd_info *mtd, struct nand_chip *chip, | |
273 | u8 *buf, int oob_required, int page) | |
274 | { | |
275 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); | |
276 | int err, res, len = mtd->writesize; | |
277 | ||
278 | if (oob_required) | |
279 | chip->ecc.read_oob(mtd, chip, page); | |
280 | ||
281 | err = do_dma(nfc, DMA_FROM_DEVICE, NFC_READ, buf, len, page); | |
282 | if (err) | |
283 | return err; | |
284 | ||
285 | res = decode_error_report(nfc); | |
286 | if (res < 0) { | |
287 | chip->ecc.read_oob_raw(mtd, chip, page); | |
288 | res = check_erased_page(chip, buf); | |
289 | } | |
290 | ||
291 | return res; | |
292 | } | |
293 | ||
294 | static int tango_write_page(struct mtd_info *mtd, struct nand_chip *chip, | |
295 | const u8 *buf, int oob_required, int page) | |
296 | { | |
297 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); | |
298 | int err, len = mtd->writesize; | |
299 | ||
300 | /* Calling tango_write_oob() would send PAGEPROG twice */ | |
301 | if (oob_required) | |
302 | return -ENOTSUPP; | |
303 | ||
304 | writel_relaxed(0xffffffff, nfc->mem_base + METADATA); | |
305 | err = do_dma(nfc, DMA_TO_DEVICE, NFC_WRITE, buf, len, page); | |
306 | if (err) | |
307 | return err; | |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
312 | static void aux_read(struct nand_chip *chip, u8 **buf, int len, int *pos) | |
313 | { | |
8fcfba07 BB |
314 | struct mtd_info *mtd = nand_to_mtd(chip); |
315 | ||
6956e238 MG |
316 | *pos += len; |
317 | ||
318 | if (!*buf) { | |
319 | /* skip over "len" bytes */ | |
8fcfba07 | 320 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, *pos, -1); |
6956e238 | 321 | } else { |
8fcfba07 | 322 | tango_read_buf(mtd, *buf, len); |
6956e238 MG |
323 | *buf += len; |
324 | } | |
325 | } | |
326 | ||
327 | static void aux_write(struct nand_chip *chip, const u8 **buf, int len, int *pos) | |
328 | { | |
8fcfba07 BB |
329 | struct mtd_info *mtd = nand_to_mtd(chip); |
330 | ||
6956e238 MG |
331 | *pos += len; |
332 | ||
333 | if (!*buf) { | |
334 | /* skip over "len" bytes */ | |
8fcfba07 | 335 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, *pos, -1); |
6956e238 | 336 | } else { |
8fcfba07 | 337 | tango_write_buf(mtd, *buf, len); |
6956e238 MG |
338 | *buf += len; |
339 | } | |
340 | } | |
341 | ||
342 | /* | |
343 | * Physical page layout (not drawn to scale) | |
344 | * | |
345 | * NB: Bad Block Marker area splits PKT_N in two (N1, N2). | |
346 | * | |
347 | * +---+-----------------+-------+-----+-----------+-----+----+-------+ | |
348 | * | M | PKT_0 | ECC_0 | ... | N1 | BBM | N2 | ECC_N | | |
349 | * +---+-----------------+-------+-----+-----------+-----+----+-------+ | |
350 | * | |
351 | * Logical page layout: | |
352 | * | |
353 | * +-----+---+-------+-----+-------+ | |
354 | * oob = | BBM | M | ECC_0 | ... | ECC_N | | |
355 | * +-----+---+-------+-----+-------+ | |
356 | * | |
357 | * +-----------------+-----+-----------------+ | |
358 | * buf = | PKT_0 | ... | PKT_N | | |
359 | * +-----------------+-----+-----------------+ | |
360 | */ | |
37871abd | 361 | static void raw_read(struct nand_chip *chip, u8 *buf, u8 *oob) |
6956e238 | 362 | { |
8fcfba07 | 363 | struct mtd_info *mtd = nand_to_mtd(chip); |
6956e238 | 364 | u8 *oob_orig = oob; |
8fcfba07 | 365 | const int page_size = mtd->writesize; |
6956e238 MG |
366 | const int ecc_size = chip->ecc.bytes; |
367 | const int pkt_size = chip->ecc.size; | |
368 | int pos = 0; /* position within physical page */ | |
369 | int rem = page_size; /* bytes remaining until BBM area */ | |
370 | ||
371 | if (oob) | |
372 | oob += BBM_SIZE; | |
373 | ||
374 | aux_read(chip, &oob, METADATA_SIZE, &pos); | |
375 | ||
376 | while (rem > pkt_size) { | |
377 | aux_read(chip, &buf, pkt_size, &pos); | |
378 | aux_read(chip, &oob, ecc_size, &pos); | |
379 | rem = page_size - pos; | |
380 | } | |
381 | ||
382 | aux_read(chip, &buf, rem, &pos); | |
383 | aux_read(chip, &oob_orig, BBM_SIZE, &pos); | |
384 | aux_read(chip, &buf, pkt_size - rem, &pos); | |
385 | aux_read(chip, &oob, ecc_size, &pos); | |
6956e238 MG |
386 | } |
387 | ||
37871abd | 388 | static void raw_write(struct nand_chip *chip, const u8 *buf, const u8 *oob) |
6956e238 | 389 | { |
8fcfba07 | 390 | struct mtd_info *mtd = nand_to_mtd(chip); |
6956e238 | 391 | const u8 *oob_orig = oob; |
8fcfba07 | 392 | const int page_size = mtd->writesize; |
6956e238 MG |
393 | const int ecc_size = chip->ecc.bytes; |
394 | const int pkt_size = chip->ecc.size; | |
395 | int pos = 0; /* position within physical page */ | |
396 | int rem = page_size; /* bytes remaining until BBM area */ | |
397 | ||
398 | if (oob) | |
399 | oob += BBM_SIZE; | |
400 | ||
401 | aux_write(chip, &oob, METADATA_SIZE, &pos); | |
402 | ||
403 | while (rem > pkt_size) { | |
404 | aux_write(chip, &buf, pkt_size, &pos); | |
405 | aux_write(chip, &oob, ecc_size, &pos); | |
406 | rem = page_size - pos; | |
407 | } | |
408 | ||
409 | aux_write(chip, &buf, rem, &pos); | |
410 | aux_write(chip, &oob_orig, BBM_SIZE, &pos); | |
411 | aux_write(chip, &buf, pkt_size - rem, &pos); | |
412 | aux_write(chip, &oob, ecc_size, &pos); | |
6956e238 MG |
413 | } |
414 | ||
415 | static int tango_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
416 | u8 *buf, int oob_required, int page) | |
417 | { | |
ff9e9eae | 418 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); |
37871abd MG |
419 | raw_read(chip, buf, chip->oob_poi); |
420 | return 0; | |
6956e238 MG |
421 | } |
422 | ||
423 | static int tango_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
424 | const u8 *buf, int oob_required, int page) | |
425 | { | |
ff9e9eae MG |
426 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0, page); |
427 | raw_write(chip, buf, chip->oob_poi); | |
428 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
429 | return 0; | |
6956e238 MG |
430 | } |
431 | ||
432 | static int tango_read_oob(struct mtd_info *mtd, struct nand_chip *chip, | |
433 | int page) | |
434 | { | |
435 | chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); | |
37871abd MG |
436 | raw_read(chip, NULL, chip->oob_poi); |
437 | return 0; | |
6956e238 MG |
438 | } |
439 | ||
440 | static int tango_write_oob(struct mtd_info *mtd, struct nand_chip *chip, | |
441 | int page) | |
442 | { | |
443 | chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0, page); | |
444 | raw_write(chip, NULL, chip->oob_poi); | |
445 | chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); | |
446 | chip->waitfunc(mtd, chip); | |
447 | return 0; | |
448 | } | |
449 | ||
450 | static int oob_ecc(struct mtd_info *mtd, int idx, struct mtd_oob_region *res) | |
451 | { | |
452 | struct nand_chip *chip = mtd_to_nand(mtd); | |
453 | struct nand_ecc_ctrl *ecc = &chip->ecc; | |
454 | ||
455 | if (idx >= ecc->steps) | |
456 | return -ERANGE; | |
457 | ||
458 | res->offset = BBM_SIZE + METADATA_SIZE + ecc->bytes * idx; | |
459 | res->length = ecc->bytes; | |
460 | ||
461 | return 0; | |
462 | } | |
463 | ||
464 | static int oob_free(struct mtd_info *mtd, int idx, struct mtd_oob_region *res) | |
465 | { | |
466 | return -ERANGE; /* no free space in spare area */ | |
467 | } | |
468 | ||
469 | static const struct mtd_ooblayout_ops tango_nand_ooblayout_ops = { | |
470 | .ecc = oob_ecc, | |
471 | .free = oob_free, | |
472 | }; | |
473 | ||
474 | static u32 to_ticks(int kHz, int ps) | |
475 | { | |
476 | return DIV_ROUND_UP_ULL((u64)kHz * ps, NSEC_PER_SEC); | |
477 | } | |
478 | ||
479 | static int tango_set_timings(struct mtd_info *mtd, | |
480 | const struct nand_data_interface *conf, | |
481 | bool check_only) | |
482 | { | |
483 | const struct nand_sdr_timings *sdr = nand_get_sdr_timings(conf); | |
484 | struct nand_chip *chip = mtd_to_nand(mtd); | |
485 | struct tango_nfc *nfc = to_tango_nfc(chip->controller); | |
486 | struct tango_chip *tchip = to_tango_chip(chip); | |
487 | u32 Trdy, Textw, Twc, Twpw, Tacc, Thold, Trpw, Textr; | |
488 | int kHz = nfc->freq_kHz; | |
489 | ||
490 | if (IS_ERR(sdr)) | |
491 | return PTR_ERR(sdr); | |
492 | ||
493 | if (check_only) | |
494 | return 0; | |
495 | ||
496 | Trdy = to_ticks(kHz, sdr->tCEA_max - sdr->tREA_max); | |
497 | Textw = to_ticks(kHz, sdr->tWB_max); | |
498 | Twc = to_ticks(kHz, sdr->tWC_min); | |
499 | Twpw = to_ticks(kHz, sdr->tWC_min - sdr->tWP_min); | |
500 | ||
501 | Tacc = to_ticks(kHz, sdr->tREA_max); | |
502 | Thold = to_ticks(kHz, sdr->tREH_min); | |
503 | Trpw = to_ticks(kHz, sdr->tRC_min - sdr->tREH_min); | |
504 | Textr = to_ticks(kHz, sdr->tRHZ_max); | |
505 | ||
506 | tchip->timing1 = TIMING(Trdy, Textw, Twc, Twpw); | |
507 | tchip->timing2 = TIMING(Tacc, Thold, Trpw, Textr); | |
508 | ||
509 | return 0; | |
510 | } | |
511 | ||
512 | static int chip_init(struct device *dev, struct device_node *np) | |
513 | { | |
514 | u32 cs; | |
515 | int err, res; | |
516 | struct mtd_info *mtd; | |
517 | struct nand_chip *chip; | |
518 | struct tango_chip *tchip; | |
519 | struct nand_ecc_ctrl *ecc; | |
520 | struct tango_nfc *nfc = dev_get_drvdata(dev); | |
521 | ||
522 | tchip = devm_kzalloc(dev, sizeof(*tchip), GFP_KERNEL); | |
523 | if (!tchip) | |
524 | return -ENOMEM; | |
525 | ||
526 | res = of_property_count_u32_elems(np, "reg"); | |
527 | if (res < 0) | |
528 | return res; | |
529 | ||
530 | if (res != 1) | |
531 | return -ENOTSUPP; /* Multi-CS chips are not supported */ | |
532 | ||
533 | err = of_property_read_u32_index(np, "reg", 0, &cs); | |
534 | if (err) | |
535 | return err; | |
536 | ||
537 | if (cs >= MAX_CS) | |
538 | return -EINVAL; | |
539 | ||
540 | chip = &tchip->nand_chip; | |
541 | ecc = &chip->ecc; | |
8fcfba07 | 542 | mtd = nand_to_mtd(chip); |
6956e238 MG |
543 | |
544 | chip->read_byte = tango_read_byte; | |
545 | chip->write_buf = tango_write_buf; | |
546 | chip->read_buf = tango_read_buf; | |
547 | chip->select_chip = tango_select_chip; | |
548 | chip->cmd_ctrl = tango_cmd_ctrl; | |
549 | chip->dev_ready = tango_dev_ready; | |
550 | chip->setup_data_interface = tango_set_timings; | |
551 | chip->options = NAND_USE_BOUNCE_BUFFER | | |
552 | NAND_NO_SUBPAGE_WRITE | | |
553 | NAND_WAIT_TCCS; | |
554 | chip->controller = &nfc->hw; | |
555 | tchip->base = nfc->pbus_base + (cs * 256); | |
556 | ||
557 | nand_set_flash_node(chip, np); | |
558 | mtd_set_ooblayout(mtd, &tango_nand_ooblayout_ops); | |
559 | mtd->dev.parent = dev; | |
560 | ||
561 | err = nand_scan_ident(mtd, 1, NULL); | |
562 | if (err) | |
563 | return err; | |
564 | ||
565 | ecc->mode = NAND_ECC_HW; | |
566 | ecc->algo = NAND_ECC_BCH; | |
567 | ecc->bytes = DIV_ROUND_UP(ecc->strength * FIELD_ORDER, BITS_PER_BYTE); | |
568 | ||
569 | ecc->read_page_raw = tango_read_page_raw; | |
570 | ecc->write_page_raw = tango_write_page_raw; | |
571 | ecc->read_page = tango_read_page; | |
572 | ecc->write_page = tango_write_page; | |
573 | ecc->read_oob = tango_read_oob; | |
574 | ecc->write_oob = tango_write_oob; | |
ff9e9eae | 575 | ecc->options = NAND_ECC_CUSTOM_PAGE_ACCESS; |
6956e238 MG |
576 | |
577 | err = nand_scan_tail(mtd); | |
578 | if (err) | |
579 | return err; | |
580 | ||
581 | tchip->xfer_cfg = XFER_CFG(cs, 1, ecc->steps, METADATA_SIZE); | |
582 | tchip->pkt_0_cfg = PKT_CFG(ecc->size + METADATA_SIZE, ecc->strength); | |
583 | tchip->pkt_n_cfg = PKT_CFG(ecc->size, ecc->strength); | |
584 | tchip->bb_cfg = BB_CFG(mtd->writesize, BBM_SIZE); | |
585 | ||
586 | err = mtd_device_register(mtd, NULL, 0); | |
587 | if (err) | |
588 | return err; | |
589 | ||
590 | nfc->chips[cs] = tchip; | |
591 | ||
592 | return 0; | |
593 | } | |
594 | ||
595 | static int tango_nand_remove(struct platform_device *pdev) | |
596 | { | |
597 | int cs; | |
598 | struct tango_nfc *nfc = platform_get_drvdata(pdev); | |
599 | ||
600 | dma_release_channel(nfc->chan); | |
601 | ||
602 | for (cs = 0; cs < MAX_CS; ++cs) { | |
603 | if (nfc->chips[cs]) | |
8fcfba07 | 604 | nand_release(nand_to_mtd(&nfc->chips[cs]->nand_chip)); |
6956e238 MG |
605 | } |
606 | ||
607 | return 0; | |
608 | } | |
609 | ||
610 | static int tango_nand_probe(struct platform_device *pdev) | |
611 | { | |
612 | int err; | |
613 | struct clk *clk; | |
614 | struct resource *res; | |
615 | struct tango_nfc *nfc; | |
616 | struct device_node *np; | |
617 | ||
618 | nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL); | |
619 | if (!nfc) | |
620 | return -ENOMEM; | |
621 | ||
622 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
623 | nfc->reg_base = devm_ioremap_resource(&pdev->dev, res); | |
624 | if (IS_ERR(nfc->reg_base)) | |
625 | return PTR_ERR(nfc->reg_base); | |
626 | ||
627 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
628 | nfc->mem_base = devm_ioremap_resource(&pdev->dev, res); | |
629 | if (IS_ERR(nfc->mem_base)) | |
630 | return PTR_ERR(nfc->mem_base); | |
631 | ||
632 | res = platform_get_resource(pdev, IORESOURCE_MEM, 2); | |
633 | nfc->pbus_base = devm_ioremap_resource(&pdev->dev, res); | |
634 | if (IS_ERR(nfc->pbus_base)) | |
635 | return PTR_ERR(nfc->pbus_base); | |
636 | ||
8043d25b MG |
637 | writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE); |
638 | ||
6956e238 MG |
639 | clk = clk_get(&pdev->dev, NULL); |
640 | if (IS_ERR(clk)) | |
641 | return PTR_ERR(clk); | |
642 | ||
7165b8ad | 643 | nfc->chan = dma_request_chan(&pdev->dev, "rxtx"); |
6956e238 MG |
644 | if (IS_ERR(nfc->chan)) |
645 | return PTR_ERR(nfc->chan); | |
646 | ||
647 | platform_set_drvdata(pdev, nfc); | |
648 | nand_hw_control_init(&nfc->hw); | |
649 | nfc->freq_kHz = clk_get_rate(clk) / 1000; | |
650 | ||
651 | for_each_child_of_node(pdev->dev.of_node, np) { | |
652 | err = chip_init(&pdev->dev, np); | |
653 | if (err) { | |
654 | tango_nand_remove(pdev); | |
655 | return err; | |
656 | } | |
657 | } | |
658 | ||
659 | return 0; | |
660 | } | |
661 | ||
662 | static const struct of_device_id tango_nand_ids[] = { | |
663 | { .compatible = "sigma,smp8758-nand" }, | |
664 | { /* sentinel */ } | |
665 | }; | |
666 | ||
667 | static struct platform_driver tango_nand_driver = { | |
668 | .probe = tango_nand_probe, | |
669 | .remove = tango_nand_remove, | |
670 | .driver = { | |
671 | .name = "tango-nand", | |
672 | .of_match_table = tango_nand_ids, | |
673 | }, | |
674 | }; | |
675 | ||
676 | module_platform_driver(tango_nand_driver); | |
677 | ||
678 | MODULE_LICENSE("GPL"); | |
679 | MODULE_AUTHOR("Sigma Designs"); | |
680 | MODULE_DESCRIPTION("Tango4 NAND Flash controller driver"); |