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1 | /* |
2 | * Samsung S3C64XX/S5PC1XX OneNAND driver | |
3 | * | |
4 | * Copyright © 2008-2010 Samsung Electronics | |
5 | * Kyungmin Park <kyungmin.park@samsung.com> | |
6 | * Marek Szyprowski <m.szyprowski@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Implementation: | |
13 | * S3C64XX and S5PC100: emulate the pseudo BufferRAM | |
14 | * S5PC110: use DMA | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/mtd/mtd.h> | |
22 | #include <linux/mtd/onenand.h> | |
23 | #include <linux/mtd/partitions.h> | |
24 | #include <linux/dma-mapping.h> | |
25 | ||
26 | #include <asm/mach/flash.h> | |
27 | #include <plat/regs-onenand.h> | |
28 | ||
29 | #include <linux/io.h> | |
30 | ||
31 | enum soc_type { | |
32 | TYPE_S3C6400, | |
33 | TYPE_S3C6410, | |
34 | TYPE_S5PC100, | |
35 | TYPE_S5PC110, | |
36 | }; | |
37 | ||
38 | #define ONENAND_ERASE_STATUS 0x00 | |
39 | #define ONENAND_MULTI_ERASE_SET 0x01 | |
40 | #define ONENAND_ERASE_START 0x03 | |
41 | #define ONENAND_UNLOCK_START 0x08 | |
42 | #define ONENAND_UNLOCK_END 0x09 | |
43 | #define ONENAND_LOCK_START 0x0A | |
44 | #define ONENAND_LOCK_END 0x0B | |
45 | #define ONENAND_LOCK_TIGHT_START 0x0C | |
46 | #define ONENAND_LOCK_TIGHT_END 0x0D | |
47 | #define ONENAND_UNLOCK_ALL 0x0E | |
48 | #define ONENAND_OTP_ACCESS 0x12 | |
49 | #define ONENAND_SPARE_ACCESS_ONLY 0x13 | |
50 | #define ONENAND_MAIN_ACCESS_ONLY 0x14 | |
51 | #define ONENAND_ERASE_VERIFY 0x15 | |
52 | #define ONENAND_MAIN_SPARE_ACCESS 0x16 | |
53 | #define ONENAND_PIPELINE_READ 0x4000 | |
54 | ||
55 | #define MAP_00 (0x0) | |
56 | #define MAP_01 (0x1) | |
57 | #define MAP_10 (0x2) | |
58 | #define MAP_11 (0x3) | |
59 | ||
60 | #define S3C64XX_CMD_MAP_SHIFT 24 | |
aa6d1c0e | 61 | #define S5PC100_CMD_MAP_SHIFT 26 |
46f3e88b KP |
62 | |
63 | #define S3C6400_FBA_SHIFT 10 | |
64 | #define S3C6400_FPA_SHIFT 4 | |
65 | #define S3C6400_FSA_SHIFT 2 | |
66 | ||
67 | #define S3C6410_FBA_SHIFT 12 | |
68 | #define S3C6410_FPA_SHIFT 6 | |
69 | #define S3C6410_FSA_SHIFT 4 | |
70 | ||
71 | #define S5PC100_FBA_SHIFT 13 | |
72 | #define S5PC100_FPA_SHIFT 7 | |
73 | #define S5PC100_FSA_SHIFT 5 | |
74 | ||
75 | /* S5PC110 specific definitions */ | |
76 | #define S5PC110_DMA_SRC_ADDR 0x400 | |
77 | #define S5PC110_DMA_SRC_CFG 0x404 | |
78 | #define S5PC110_DMA_DST_ADDR 0x408 | |
79 | #define S5PC110_DMA_DST_CFG 0x40C | |
80 | #define S5PC110_DMA_TRANS_SIZE 0x414 | |
81 | #define S5PC110_DMA_TRANS_CMD 0x418 | |
82 | #define S5PC110_DMA_TRANS_STATUS 0x41C | |
83 | #define S5PC110_DMA_TRANS_DIR 0x420 | |
84 | ||
85 | #define S5PC110_DMA_CFG_SINGLE (0x0 << 16) | |
86 | #define S5PC110_DMA_CFG_4BURST (0x2 << 16) | |
87 | #define S5PC110_DMA_CFG_8BURST (0x3 << 16) | |
88 | #define S5PC110_DMA_CFG_16BURST (0x4 << 16) | |
89 | ||
90 | #define S5PC110_DMA_CFG_INC (0x0 << 8) | |
91 | #define S5PC110_DMA_CFG_CNT (0x1 << 8) | |
92 | ||
93 | #define S5PC110_DMA_CFG_8BIT (0x0 << 0) | |
94 | #define S5PC110_DMA_CFG_16BIT (0x1 << 0) | |
95 | #define S5PC110_DMA_CFG_32BIT (0x2 << 0) | |
96 | ||
97 | #define S5PC110_DMA_SRC_CFG_READ (S5PC110_DMA_CFG_16BURST | \ | |
98 | S5PC110_DMA_CFG_INC | \ | |
99 | S5PC110_DMA_CFG_16BIT) | |
100 | #define S5PC110_DMA_DST_CFG_READ (S5PC110_DMA_CFG_16BURST | \ | |
101 | S5PC110_DMA_CFG_INC | \ | |
102 | S5PC110_DMA_CFG_32BIT) | |
103 | #define S5PC110_DMA_SRC_CFG_WRITE (S5PC110_DMA_CFG_16BURST | \ | |
104 | S5PC110_DMA_CFG_INC | \ | |
105 | S5PC110_DMA_CFG_32BIT) | |
106 | #define S5PC110_DMA_DST_CFG_WRITE (S5PC110_DMA_CFG_16BURST | \ | |
107 | S5PC110_DMA_CFG_INC | \ | |
108 | S5PC110_DMA_CFG_16BIT) | |
109 | ||
110 | #define S5PC110_DMA_TRANS_CMD_TDC (0x1 << 18) | |
111 | #define S5PC110_DMA_TRANS_CMD_TEC (0x1 << 16) | |
112 | #define S5PC110_DMA_TRANS_CMD_TR (0x1 << 0) | |
113 | ||
114 | #define S5PC110_DMA_TRANS_STATUS_TD (0x1 << 18) | |
115 | #define S5PC110_DMA_TRANS_STATUS_TB (0x1 << 17) | |
116 | #define S5PC110_DMA_TRANS_STATUS_TE (0x1 << 16) | |
117 | ||
118 | #define S5PC110_DMA_DIR_READ 0x0 | |
119 | #define S5PC110_DMA_DIR_WRITE 0x1 | |
120 | ||
121 | struct s3c_onenand { | |
122 | struct mtd_info *mtd; | |
123 | struct platform_device *pdev; | |
124 | enum soc_type type; | |
125 | void __iomem *base; | |
126 | struct resource *base_res; | |
127 | void __iomem *ahb_addr; | |
128 | struct resource *ahb_res; | |
129 | int bootram_command; | |
130 | void __iomem *page_buf; | |
131 | void __iomem *oob_buf; | |
132 | unsigned int (*mem_addr)(int fba, int fpa, int fsa); | |
133 | unsigned int (*cmd_map)(unsigned int type, unsigned int val); | |
134 | void __iomem *dma_addr; | |
135 | struct resource *dma_res; | |
136 | unsigned long phys_base; | |
137 | #ifdef CONFIG_MTD_PARTITIONS | |
138 | struct mtd_partition *parts; | |
139 | #endif | |
140 | }; | |
141 | ||
142 | #define CMD_MAP_00(dev, addr) (dev->cmd_map(MAP_00, ((addr) << 1))) | |
143 | #define CMD_MAP_01(dev, mem_addr) (dev->cmd_map(MAP_01, (mem_addr))) | |
144 | #define CMD_MAP_10(dev, mem_addr) (dev->cmd_map(MAP_10, (mem_addr))) | |
145 | #define CMD_MAP_11(dev, addr) (dev->cmd_map(MAP_11, ((addr) << 2))) | |
146 | ||
147 | static struct s3c_onenand *onenand; | |
148 | ||
149 | #ifdef CONFIG_MTD_PARTITIONS | |
150 | static const char *part_probes[] = { "cmdlinepart", NULL, }; | |
151 | #endif | |
152 | ||
153 | static inline int s3c_read_reg(int offset) | |
154 | { | |
155 | return readl(onenand->base + offset); | |
156 | } | |
157 | ||
158 | static inline void s3c_write_reg(int value, int offset) | |
159 | { | |
160 | writel(value, onenand->base + offset); | |
161 | } | |
162 | ||
163 | static inline int s3c_read_cmd(unsigned int cmd) | |
164 | { | |
165 | return readl(onenand->ahb_addr + cmd); | |
166 | } | |
167 | ||
168 | static inline void s3c_write_cmd(int value, unsigned int cmd) | |
169 | { | |
170 | writel(value, onenand->ahb_addr + cmd); | |
171 | } | |
172 | ||
173 | #ifdef SAMSUNG_DEBUG | |
174 | static void s3c_dump_reg(void) | |
175 | { | |
176 | int i; | |
177 | ||
178 | for (i = 0; i < 0x400; i += 0x40) { | |
179 | printk(KERN_INFO "0x%08X: 0x%08x 0x%08x 0x%08x 0x%08x\n", | |
180 | (unsigned int) onenand->base + i, | |
181 | s3c_read_reg(i), s3c_read_reg(i + 0x10), | |
182 | s3c_read_reg(i + 0x20), s3c_read_reg(i + 0x30)); | |
183 | } | |
184 | } | |
185 | #endif | |
186 | ||
187 | static unsigned int s3c64xx_cmd_map(unsigned type, unsigned val) | |
188 | { | |
189 | return (type << S3C64XX_CMD_MAP_SHIFT) | val; | |
190 | } | |
191 | ||
192 | static unsigned int s5pc1xx_cmd_map(unsigned type, unsigned val) | |
193 | { | |
aa6d1c0e | 194 | return (type << S5PC100_CMD_MAP_SHIFT) | val; |
46f3e88b KP |
195 | } |
196 | ||
197 | static unsigned int s3c6400_mem_addr(int fba, int fpa, int fsa) | |
198 | { | |
199 | return (fba << S3C6400_FBA_SHIFT) | (fpa << S3C6400_FPA_SHIFT) | | |
200 | (fsa << S3C6400_FSA_SHIFT); | |
201 | } | |
202 | ||
203 | static unsigned int s3c6410_mem_addr(int fba, int fpa, int fsa) | |
204 | { | |
205 | return (fba << S3C6410_FBA_SHIFT) | (fpa << S3C6410_FPA_SHIFT) | | |
206 | (fsa << S3C6410_FSA_SHIFT); | |
207 | } | |
208 | ||
209 | static unsigned int s5pc100_mem_addr(int fba, int fpa, int fsa) | |
210 | { | |
211 | return (fba << S5PC100_FBA_SHIFT) | (fpa << S5PC100_FPA_SHIFT) | | |
212 | (fsa << S5PC100_FSA_SHIFT); | |
213 | } | |
214 | ||
215 | static void s3c_onenand_reset(void) | |
216 | { | |
217 | unsigned long timeout = 0x10000; | |
218 | int stat; | |
219 | ||
220 | s3c_write_reg(ONENAND_MEM_RESET_COLD, MEM_RESET_OFFSET); | |
221 | while (1 && timeout--) { | |
222 | stat = s3c_read_reg(INT_ERR_STAT_OFFSET); | |
223 | if (stat & RST_CMP) | |
224 | break; | |
225 | } | |
226 | stat = s3c_read_reg(INT_ERR_STAT_OFFSET); | |
227 | s3c_write_reg(stat, INT_ERR_ACK_OFFSET); | |
228 | ||
229 | /* Clear interrupt */ | |
230 | s3c_write_reg(0x0, INT_ERR_ACK_OFFSET); | |
231 | /* Clear the ECC status */ | |
232 | s3c_write_reg(0x0, ECC_ERR_STAT_OFFSET); | |
233 | } | |
234 | ||
235 | static unsigned short s3c_onenand_readw(void __iomem *addr) | |
236 | { | |
237 | struct onenand_chip *this = onenand->mtd->priv; | |
238 | struct device *dev = &onenand->pdev->dev; | |
239 | int reg = addr - this->base; | |
240 | int word_addr = reg >> 1; | |
241 | int value; | |
242 | ||
243 | /* It's used for probing time */ | |
244 | switch (reg) { | |
245 | case ONENAND_REG_MANUFACTURER_ID: | |
246 | return s3c_read_reg(MANUFACT_ID_OFFSET); | |
247 | case ONENAND_REG_DEVICE_ID: | |
248 | return s3c_read_reg(DEVICE_ID_OFFSET); | |
249 | case ONENAND_REG_VERSION_ID: | |
250 | return s3c_read_reg(FLASH_VER_ID_OFFSET); | |
251 | case ONENAND_REG_DATA_BUFFER_SIZE: | |
252 | return s3c_read_reg(DATA_BUF_SIZE_OFFSET); | |
253 | case ONENAND_REG_TECHNOLOGY: | |
254 | return s3c_read_reg(TECH_OFFSET); | |
255 | case ONENAND_REG_SYS_CFG1: | |
256 | return s3c_read_reg(MEM_CFG_OFFSET); | |
257 | ||
258 | /* Used at unlock all status */ | |
259 | case ONENAND_REG_CTRL_STATUS: | |
260 | return 0; | |
261 | ||
262 | case ONENAND_REG_WP_STATUS: | |
263 | return ONENAND_WP_US; | |
264 | ||
265 | default: | |
266 | break; | |
267 | } | |
268 | ||
269 | /* BootRAM access control */ | |
270 | if ((unsigned int) addr < ONENAND_DATARAM && onenand->bootram_command) { | |
271 | if (word_addr == 0) | |
272 | return s3c_read_reg(MANUFACT_ID_OFFSET); | |
273 | if (word_addr == 1) | |
274 | return s3c_read_reg(DEVICE_ID_OFFSET); | |
275 | if (word_addr == 2) | |
276 | return s3c_read_reg(FLASH_VER_ID_OFFSET); | |
277 | } | |
278 | ||
279 | value = s3c_read_cmd(CMD_MAP_11(onenand, word_addr)) & 0xffff; | |
280 | dev_info(dev, "%s: Illegal access at reg 0x%x, value 0x%x\n", __func__, | |
281 | word_addr, value); | |
282 | return value; | |
283 | } | |
284 | ||
285 | static void s3c_onenand_writew(unsigned short value, void __iomem *addr) | |
286 | { | |
287 | struct onenand_chip *this = onenand->mtd->priv; | |
288 | struct device *dev = &onenand->pdev->dev; | |
289 | unsigned int reg = addr - this->base; | |
290 | unsigned int word_addr = reg >> 1; | |
291 | ||
292 | /* It's used for probing time */ | |
293 | switch (reg) { | |
294 | case ONENAND_REG_SYS_CFG1: | |
295 | s3c_write_reg(value, MEM_CFG_OFFSET); | |
296 | return; | |
297 | ||
298 | case ONENAND_REG_START_ADDRESS1: | |
299 | case ONENAND_REG_START_ADDRESS2: | |
300 | return; | |
301 | ||
302 | /* Lock/lock-tight/unlock/unlock_all */ | |
303 | case ONENAND_REG_START_BLOCK_ADDRESS: | |
304 | return; | |
305 | ||
306 | default: | |
307 | break; | |
308 | } | |
309 | ||
310 | /* BootRAM access control */ | |
311 | if ((unsigned int)addr < ONENAND_DATARAM) { | |
312 | if (value == ONENAND_CMD_READID) { | |
313 | onenand->bootram_command = 1; | |
314 | return; | |
315 | } | |
316 | if (value == ONENAND_CMD_RESET) { | |
317 | s3c_write_reg(ONENAND_MEM_RESET_COLD, MEM_RESET_OFFSET); | |
318 | onenand->bootram_command = 0; | |
319 | return; | |
320 | } | |
321 | } | |
322 | ||
323 | dev_info(dev, "%s: Illegal access at reg 0x%x, value 0x%x\n", __func__, | |
324 | word_addr, value); | |
325 | ||
326 | s3c_write_cmd(value, CMD_MAP_11(onenand, word_addr)); | |
327 | } | |
328 | ||
329 | static int s3c_onenand_wait(struct mtd_info *mtd, int state) | |
330 | { | |
331 | struct device *dev = &onenand->pdev->dev; | |
332 | unsigned int flags = INT_ACT; | |
333 | unsigned int stat, ecc; | |
334 | unsigned long timeout; | |
335 | ||
336 | switch (state) { | |
337 | case FL_READING: | |
338 | flags |= BLK_RW_CMP | LOAD_CMP; | |
339 | break; | |
340 | case FL_WRITING: | |
341 | flags |= BLK_RW_CMP | PGM_CMP; | |
342 | break; | |
343 | case FL_ERASING: | |
344 | flags |= BLK_RW_CMP | ERS_CMP; | |
345 | break; | |
346 | case FL_LOCKING: | |
347 | flags |= BLK_RW_CMP; | |
348 | break; | |
349 | default: | |
350 | break; | |
351 | } | |
352 | ||
353 | /* The 20 msec is enough */ | |
354 | timeout = jiffies + msecs_to_jiffies(20); | |
355 | while (time_before(jiffies, timeout)) { | |
356 | stat = s3c_read_reg(INT_ERR_STAT_OFFSET); | |
357 | if (stat & flags) | |
358 | break; | |
359 | ||
360 | if (state != FL_READING) | |
361 | cond_resched(); | |
362 | } | |
363 | /* To get correct interrupt status in timeout case */ | |
364 | stat = s3c_read_reg(INT_ERR_STAT_OFFSET); | |
365 | s3c_write_reg(stat, INT_ERR_ACK_OFFSET); | |
366 | ||
367 | /* | |
368 | * In the Spec. it checks the controller status first | |
369 | * However if you get the correct information in case of | |
370 | * power off recovery (POR) test, it should read ECC status first | |
371 | */ | |
372 | if (stat & LOAD_CMP) { | |
373 | ecc = s3c_read_reg(ECC_ERR_STAT_OFFSET); | |
374 | if (ecc & ONENAND_ECC_4BIT_UNCORRECTABLE) { | |
375 | dev_info(dev, "%s: ECC error = 0x%04x\n", __func__, | |
376 | ecc); | |
377 | mtd->ecc_stats.failed++; | |
378 | return -EBADMSG; | |
379 | } | |
380 | } | |
381 | ||
382 | if (stat & (LOCKED_BLK | ERS_FAIL | PGM_FAIL | LD_FAIL_ECC_ERR)) { | |
383 | dev_info(dev, "%s: controller error = 0x%04x\n", __func__, | |
384 | stat); | |
385 | if (stat & LOCKED_BLK) | |
386 | dev_info(dev, "%s: it's locked error = 0x%04x\n", | |
387 | __func__, stat); | |
388 | ||
389 | return -EIO; | |
390 | } | |
391 | ||
392 | return 0; | |
393 | } | |
394 | ||
395 | static int s3c_onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, | |
396 | size_t len) | |
397 | { | |
398 | struct onenand_chip *this = mtd->priv; | |
399 | unsigned int *m, *s; | |
400 | int fba, fpa, fsa = 0; | |
401 | unsigned int mem_addr, cmd_map_01, cmd_map_10; | |
402 | int i, mcount, scount; | |
403 | int index; | |
404 | ||
405 | fba = (int) (addr >> this->erase_shift); | |
406 | fpa = (int) (addr >> this->page_shift); | |
407 | fpa &= this->page_mask; | |
408 | ||
409 | mem_addr = onenand->mem_addr(fba, fpa, fsa); | |
410 | cmd_map_01 = CMD_MAP_01(onenand, mem_addr); | |
411 | cmd_map_10 = CMD_MAP_10(onenand, mem_addr); | |
412 | ||
413 | switch (cmd) { | |
414 | case ONENAND_CMD_READ: | |
415 | case ONENAND_CMD_READOOB: | |
416 | case ONENAND_CMD_BUFFERRAM: | |
417 | ONENAND_SET_NEXT_BUFFERRAM(this); | |
418 | default: | |
419 | break; | |
420 | } | |
421 | ||
422 | index = ONENAND_CURRENT_BUFFERRAM(this); | |
423 | ||
424 | /* | |
425 | * Emulate Two BufferRAMs and access with 4 bytes pointer | |
426 | */ | |
427 | m = (unsigned int *) onenand->page_buf; | |
428 | s = (unsigned int *) onenand->oob_buf; | |
429 | ||
430 | if (index) { | |
431 | m += (this->writesize >> 2); | |
432 | s += (mtd->oobsize >> 2); | |
433 | } | |
434 | ||
435 | mcount = mtd->writesize >> 2; | |
436 | scount = mtd->oobsize >> 2; | |
437 | ||
438 | switch (cmd) { | |
439 | case ONENAND_CMD_READ: | |
440 | /* Main */ | |
441 | for (i = 0; i < mcount; i++) | |
442 | *m++ = s3c_read_cmd(cmd_map_01); | |
443 | return 0; | |
444 | ||
445 | case ONENAND_CMD_READOOB: | |
446 | s3c_write_reg(TSRF, TRANS_SPARE_OFFSET); | |
447 | /* Main */ | |
448 | for (i = 0; i < mcount; i++) | |
449 | *m++ = s3c_read_cmd(cmd_map_01); | |
450 | ||
451 | /* Spare */ | |
452 | for (i = 0; i < scount; i++) | |
453 | *s++ = s3c_read_cmd(cmd_map_01); | |
454 | ||
455 | s3c_write_reg(0, TRANS_SPARE_OFFSET); | |
456 | return 0; | |
457 | ||
458 | case ONENAND_CMD_PROG: | |
459 | /* Main */ | |
460 | for (i = 0; i < mcount; i++) | |
461 | s3c_write_cmd(*m++, cmd_map_01); | |
462 | return 0; | |
463 | ||
464 | case ONENAND_CMD_PROGOOB: | |
465 | s3c_write_reg(TSRF, TRANS_SPARE_OFFSET); | |
466 | ||
467 | /* Main - dummy write */ | |
468 | for (i = 0; i < mcount; i++) | |
469 | s3c_write_cmd(0xffffffff, cmd_map_01); | |
470 | ||
471 | /* Spare */ | |
472 | for (i = 0; i < scount; i++) | |
473 | s3c_write_cmd(*s++, cmd_map_01); | |
474 | ||
475 | s3c_write_reg(0, TRANS_SPARE_OFFSET); | |
476 | return 0; | |
477 | ||
478 | case ONENAND_CMD_UNLOCK_ALL: | |
479 | s3c_write_cmd(ONENAND_UNLOCK_ALL, cmd_map_10); | |
480 | return 0; | |
481 | ||
482 | case ONENAND_CMD_ERASE: | |
483 | s3c_write_cmd(ONENAND_ERASE_START, cmd_map_10); | |
484 | return 0; | |
485 | ||
486 | default: | |
487 | break; | |
488 | } | |
489 | ||
490 | return 0; | |
491 | } | |
492 | ||
493 | static unsigned char *s3c_get_bufferram(struct mtd_info *mtd, int area) | |
494 | { | |
495 | struct onenand_chip *this = mtd->priv; | |
496 | int index = ONENAND_CURRENT_BUFFERRAM(this); | |
497 | unsigned char *p; | |
498 | ||
499 | if (area == ONENAND_DATARAM) { | |
500 | p = (unsigned char *) onenand->page_buf; | |
501 | if (index == 1) | |
502 | p += this->writesize; | |
503 | } else { | |
504 | p = (unsigned char *) onenand->oob_buf; | |
505 | if (index == 1) | |
506 | p += mtd->oobsize; | |
507 | } | |
508 | ||
509 | return p; | |
510 | } | |
511 | ||
512 | static int onenand_read_bufferram(struct mtd_info *mtd, int area, | |
513 | unsigned char *buffer, int offset, | |
514 | size_t count) | |
515 | { | |
516 | unsigned char *p; | |
517 | ||
518 | p = s3c_get_bufferram(mtd, area); | |
519 | memcpy(buffer, p + offset, count); | |
520 | return 0; | |
521 | } | |
522 | ||
523 | static int onenand_write_bufferram(struct mtd_info *mtd, int area, | |
524 | const unsigned char *buffer, int offset, | |
525 | size_t count) | |
526 | { | |
527 | unsigned char *p; | |
528 | ||
529 | p = s3c_get_bufferram(mtd, area); | |
530 | memcpy(p + offset, buffer, count); | |
531 | return 0; | |
532 | } | |
533 | ||
534 | static int s5pc110_dma_ops(void *dst, void *src, size_t count, int direction) | |
535 | { | |
536 | void __iomem *base = onenand->dma_addr; | |
537 | int status; | |
ebe8a642 | 538 | unsigned long timeout; |
46f3e88b KP |
539 | |
540 | writel(src, base + S5PC110_DMA_SRC_ADDR); | |
541 | writel(dst, base + S5PC110_DMA_DST_ADDR); | |
542 | ||
543 | if (direction == S5PC110_DMA_DIR_READ) { | |
544 | writel(S5PC110_DMA_SRC_CFG_READ, base + S5PC110_DMA_SRC_CFG); | |
545 | writel(S5PC110_DMA_DST_CFG_READ, base + S5PC110_DMA_DST_CFG); | |
546 | } else { | |
547 | writel(S5PC110_DMA_SRC_CFG_WRITE, base + S5PC110_DMA_SRC_CFG); | |
548 | writel(S5PC110_DMA_DST_CFG_WRITE, base + S5PC110_DMA_DST_CFG); | |
549 | } | |
550 | ||
551 | writel(count, base + S5PC110_DMA_TRANS_SIZE); | |
552 | writel(direction, base + S5PC110_DMA_TRANS_DIR); | |
553 | ||
554 | writel(S5PC110_DMA_TRANS_CMD_TR, base + S5PC110_DMA_TRANS_CMD); | |
555 | ||
ebe8a642 KP |
556 | /* |
557 | * There's no exact timeout values at Spec. | |
558 | * In real case it takes under 1 msec. | |
559 | * So 20 msecs are enough. | |
560 | */ | |
561 | timeout = jiffies + msecs_to_jiffies(20); | |
562 | ||
46f3e88b KP |
563 | do { |
564 | status = readl(base + S5PC110_DMA_TRANS_STATUS); | |
53d1e137 KP |
565 | if (status & S5PC110_DMA_TRANS_STATUS_TE) { |
566 | writel(S5PC110_DMA_TRANS_CMD_TEC, | |
567 | base + S5PC110_DMA_TRANS_CMD); | |
568 | return -EIO; | |
569 | } | |
ebe8a642 KP |
570 | } while (!(status & S5PC110_DMA_TRANS_STATUS_TD) && |
571 | time_before(jiffies, timeout)); | |
46f3e88b | 572 | |
46f3e88b KP |
573 | writel(S5PC110_DMA_TRANS_CMD_TDC, base + S5PC110_DMA_TRANS_CMD); |
574 | ||
575 | return 0; | |
576 | } | |
577 | ||
578 | static int s5pc110_read_bufferram(struct mtd_info *mtd, int area, | |
579 | unsigned char *buffer, int offset, size_t count) | |
580 | { | |
581 | struct onenand_chip *this = mtd->priv; | |
46f3e88b KP |
582 | void __iomem *p; |
583 | void *buf = (void *) buffer; | |
584 | dma_addr_t dma_src, dma_dst; | |
dcf08227 KP |
585 | int err, page_dma = 0; |
586 | struct device *dev = &onenand->pdev->dev; | |
46f3e88b | 587 | |
9aba97ad | 588 | p = this->base + area; |
46f3e88b KP |
589 | if (ONENAND_CURRENT_BUFFERRAM(this)) { |
590 | if (area == ONENAND_DATARAM) | |
591 | p += this->writesize; | |
592 | else | |
593 | p += mtd->oobsize; | |
594 | } | |
595 | ||
596 | if (offset & 3 || (size_t) buf & 3 || | |
597 | !onenand->dma_addr || count != mtd->writesize) | |
598 | goto normal; | |
599 | ||
600 | /* Handle vmalloc address */ | |
601 | if (buf >= high_memory) { | |
602 | struct page *page; | |
603 | ||
604 | if (((size_t) buf & PAGE_MASK) != | |
605 | ((size_t) (buf + count - 1) & PAGE_MASK)) | |
606 | goto normal; | |
607 | page = vmalloc_to_page(buf); | |
608 | if (!page) | |
609 | goto normal; | |
46f3e88b | 610 | |
dcf08227 KP |
611 | page_dma = 1; |
612 | /* DMA routine */ | |
613 | dma_src = onenand->phys_base + (p - this->base); | |
614 | dma_dst = dma_map_page(dev, page, 0, count, DMA_FROM_DEVICE); | |
615 | } else { | |
616 | /* DMA routine */ | |
617 | dma_src = onenand->phys_base + (p - this->base); | |
618 | dma_dst = dma_map_single(dev, buf, count, DMA_FROM_DEVICE); | |
619 | } | |
620 | if (dma_mapping_error(dev, dma_dst)) { | |
621 | dev_err(dev, "Couldn't map a %d byte buffer for DMA\n", count); | |
46f3e88b KP |
622 | goto normal; |
623 | } | |
624 | err = s5pc110_dma_ops((void *) dma_dst, (void *) dma_src, | |
625 | count, S5PC110_DMA_DIR_READ); | |
dcf08227 KP |
626 | |
627 | if (page_dma) | |
628 | dma_unmap_page(dev, dma_dst, count, DMA_FROM_DEVICE); | |
629 | else | |
630 | dma_unmap_single(dev, dma_dst, count, DMA_FROM_DEVICE); | |
46f3e88b KP |
631 | |
632 | if (!err) | |
633 | return 0; | |
634 | ||
635 | normal: | |
636 | if (count != mtd->writesize) { | |
637 | /* Copy the bufferram to memory to prevent unaligned access */ | |
9aba97ad | 638 | memcpy(this->page_buf, p, mtd->writesize); |
46f3e88b KP |
639 | p = this->page_buf + offset; |
640 | } | |
641 | ||
642 | memcpy(buffer, p, count); | |
643 | ||
644 | return 0; | |
645 | } | |
646 | ||
7b0507eb KP |
647 | static int s5pc110_chip_probe(struct mtd_info *mtd) |
648 | { | |
649 | /* Now just return 0 */ | |
650 | return 0; | |
651 | } | |
652 | ||
46f3e88b KP |
653 | static int s3c_onenand_bbt_wait(struct mtd_info *mtd, int state) |
654 | { | |
655 | unsigned int flags = INT_ACT | LOAD_CMP; | |
656 | unsigned int stat; | |
657 | unsigned long timeout; | |
658 | ||
659 | /* The 20 msec is enough */ | |
660 | timeout = jiffies + msecs_to_jiffies(20); | |
661 | while (time_before(jiffies, timeout)) { | |
662 | stat = s3c_read_reg(INT_ERR_STAT_OFFSET); | |
663 | if (stat & flags) | |
664 | break; | |
665 | } | |
666 | /* To get correct interrupt status in timeout case */ | |
667 | stat = s3c_read_reg(INT_ERR_STAT_OFFSET); | |
668 | s3c_write_reg(stat, INT_ERR_ACK_OFFSET); | |
669 | ||
670 | if (stat & LD_FAIL_ECC_ERR) { | |
671 | s3c_onenand_reset(); | |
672 | return ONENAND_BBT_READ_ERROR; | |
673 | } | |
674 | ||
675 | if (stat & LOAD_CMP) { | |
676 | int ecc = s3c_read_reg(ECC_ERR_STAT_OFFSET); | |
677 | if (ecc & ONENAND_ECC_4BIT_UNCORRECTABLE) { | |
678 | s3c_onenand_reset(); | |
679 | return ONENAND_BBT_READ_ERROR; | |
680 | } | |
681 | } | |
682 | ||
683 | return 0; | |
684 | } | |
685 | ||
686 | static void s3c_onenand_check_lock_status(struct mtd_info *mtd) | |
687 | { | |
688 | struct onenand_chip *this = mtd->priv; | |
689 | struct device *dev = &onenand->pdev->dev; | |
690 | unsigned int block, end; | |
691 | int tmp; | |
692 | ||
693 | end = this->chipsize >> this->erase_shift; | |
694 | ||
695 | for (block = 0; block < end; block++) { | |
696 | unsigned int mem_addr = onenand->mem_addr(block, 0, 0); | |
697 | tmp = s3c_read_cmd(CMD_MAP_01(onenand, mem_addr)); | |
698 | ||
699 | if (s3c_read_reg(INT_ERR_STAT_OFFSET) & LOCKED_BLK) { | |
700 | dev_err(dev, "block %d is write-protected!\n", block); | |
701 | s3c_write_reg(LOCKED_BLK, INT_ERR_ACK_OFFSET); | |
702 | } | |
703 | } | |
704 | } | |
705 | ||
706 | static void s3c_onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs, | |
707 | size_t len, int cmd) | |
708 | { | |
709 | struct onenand_chip *this = mtd->priv; | |
710 | int start, end, start_mem_addr, end_mem_addr; | |
711 | ||
712 | start = ofs >> this->erase_shift; | |
713 | start_mem_addr = onenand->mem_addr(start, 0, 0); | |
714 | end = start + (len >> this->erase_shift) - 1; | |
715 | end_mem_addr = onenand->mem_addr(end, 0, 0); | |
716 | ||
717 | if (cmd == ONENAND_CMD_LOCK) { | |
718 | s3c_write_cmd(ONENAND_LOCK_START, CMD_MAP_10(onenand, | |
719 | start_mem_addr)); | |
720 | s3c_write_cmd(ONENAND_LOCK_END, CMD_MAP_10(onenand, | |
721 | end_mem_addr)); | |
722 | } else { | |
723 | s3c_write_cmd(ONENAND_UNLOCK_START, CMD_MAP_10(onenand, | |
724 | start_mem_addr)); | |
725 | s3c_write_cmd(ONENAND_UNLOCK_END, CMD_MAP_10(onenand, | |
726 | end_mem_addr)); | |
727 | } | |
728 | ||
729 | this->wait(mtd, FL_LOCKING); | |
730 | } | |
731 | ||
732 | static void s3c_unlock_all(struct mtd_info *mtd) | |
733 | { | |
734 | struct onenand_chip *this = mtd->priv; | |
735 | loff_t ofs = 0; | |
736 | size_t len = this->chipsize; | |
737 | ||
738 | if (this->options & ONENAND_HAS_UNLOCK_ALL) { | |
739 | /* Write unlock command */ | |
740 | this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0); | |
741 | ||
742 | /* No need to check return value */ | |
743 | this->wait(mtd, FL_LOCKING); | |
744 | ||
745 | /* Workaround for all block unlock in DDP */ | |
746 | if (!ONENAND_IS_DDP(this)) { | |
747 | s3c_onenand_check_lock_status(mtd); | |
748 | return; | |
749 | } | |
750 | ||
751 | /* All blocks on another chip */ | |
752 | ofs = this->chipsize >> 1; | |
753 | len = this->chipsize >> 1; | |
754 | } | |
755 | ||
756 | s3c_onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK); | |
757 | ||
758 | s3c_onenand_check_lock_status(mtd); | |
759 | } | |
760 | ||
761 | static void s3c_onenand_setup(struct mtd_info *mtd) | |
762 | { | |
763 | struct onenand_chip *this = mtd->priv; | |
764 | ||
765 | onenand->mtd = mtd; | |
766 | ||
767 | if (onenand->type == TYPE_S3C6400) { | |
768 | onenand->mem_addr = s3c6400_mem_addr; | |
769 | onenand->cmd_map = s3c64xx_cmd_map; | |
770 | } else if (onenand->type == TYPE_S3C6410) { | |
771 | onenand->mem_addr = s3c6410_mem_addr; | |
772 | onenand->cmd_map = s3c64xx_cmd_map; | |
773 | } else if (onenand->type == TYPE_S5PC100) { | |
774 | onenand->mem_addr = s5pc100_mem_addr; | |
775 | onenand->cmd_map = s5pc1xx_cmd_map; | |
776 | } else if (onenand->type == TYPE_S5PC110) { | |
777 | /* Use generic onenand functions */ | |
46f3e88b | 778 | this->read_bufferram = s5pc110_read_bufferram; |
7b0507eb | 779 | this->chip_probe = s5pc110_chip_probe; |
46f3e88b KP |
780 | return; |
781 | } else { | |
782 | BUG(); | |
783 | } | |
784 | ||
785 | this->read_word = s3c_onenand_readw; | |
786 | this->write_word = s3c_onenand_writew; | |
787 | ||
788 | this->wait = s3c_onenand_wait; | |
789 | this->bbt_wait = s3c_onenand_bbt_wait; | |
790 | this->unlock_all = s3c_unlock_all; | |
791 | this->command = s3c_onenand_command; | |
792 | ||
793 | this->read_bufferram = onenand_read_bufferram; | |
794 | this->write_bufferram = onenand_write_bufferram; | |
795 | } | |
796 | ||
797 | static int s3c_onenand_probe(struct platform_device *pdev) | |
798 | { | |
799 | struct onenand_platform_data *pdata; | |
800 | struct onenand_chip *this; | |
801 | struct mtd_info *mtd; | |
802 | struct resource *r; | |
803 | int size, err; | |
46f3e88b KP |
804 | |
805 | pdata = pdev->dev.platform_data; | |
806 | /* No need to check pdata. the platform data is optional */ | |
807 | ||
808 | size = sizeof(struct mtd_info) + sizeof(struct onenand_chip); | |
809 | mtd = kzalloc(size, GFP_KERNEL); | |
810 | if (!mtd) { | |
811 | dev_err(&pdev->dev, "failed to allocate memory\n"); | |
812 | return -ENOMEM; | |
813 | } | |
814 | ||
815 | onenand = kzalloc(sizeof(struct s3c_onenand), GFP_KERNEL); | |
816 | if (!onenand) { | |
817 | err = -ENOMEM; | |
818 | goto onenand_fail; | |
819 | } | |
820 | ||
821 | this = (struct onenand_chip *) &mtd[1]; | |
822 | mtd->priv = this; | |
823 | mtd->dev.parent = &pdev->dev; | |
824 | mtd->owner = THIS_MODULE; | |
825 | onenand->pdev = pdev; | |
826 | onenand->type = platform_get_device_id(pdev)->driver_data; | |
827 | ||
828 | s3c_onenand_setup(mtd); | |
829 | ||
830 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
831 | if (!r) { | |
832 | dev_err(&pdev->dev, "no memory resource defined\n"); | |
833 | return -ENOENT; | |
834 | goto ahb_resource_failed; | |
835 | } | |
836 | ||
837 | onenand->base_res = request_mem_region(r->start, resource_size(r), | |
838 | pdev->name); | |
839 | if (!onenand->base_res) { | |
840 | dev_err(&pdev->dev, "failed to request memory resource\n"); | |
841 | err = -EBUSY; | |
842 | goto resource_failed; | |
843 | } | |
844 | ||
845 | onenand->base = ioremap(r->start, resource_size(r)); | |
846 | if (!onenand->base) { | |
847 | dev_err(&pdev->dev, "failed to map memory resource\n"); | |
848 | err = -EFAULT; | |
849 | goto ioremap_failed; | |
850 | } | |
851 | /* Set onenand_chip also */ | |
852 | this->base = onenand->base; | |
853 | ||
854 | /* Use runtime badblock check */ | |
855 | this->options |= ONENAND_SKIP_UNLOCK_CHECK; | |
856 | ||
857 | if (onenand->type != TYPE_S5PC110) { | |
858 | r = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
859 | if (!r) { | |
860 | dev_err(&pdev->dev, "no buffer memory resource defined\n"); | |
861 | return -ENOENT; | |
862 | goto ahb_resource_failed; | |
863 | } | |
864 | ||
865 | onenand->ahb_res = request_mem_region(r->start, resource_size(r), | |
866 | pdev->name); | |
867 | if (!onenand->ahb_res) { | |
868 | dev_err(&pdev->dev, "failed to request buffer memory resource\n"); | |
869 | err = -EBUSY; | |
870 | goto ahb_resource_failed; | |
871 | } | |
872 | ||
873 | onenand->ahb_addr = ioremap(r->start, resource_size(r)); | |
874 | if (!onenand->ahb_addr) { | |
875 | dev_err(&pdev->dev, "failed to map buffer memory resource\n"); | |
876 | err = -EINVAL; | |
877 | goto ahb_ioremap_failed; | |
878 | } | |
879 | ||
880 | /* Allocate 4KiB BufferRAM */ | |
881 | onenand->page_buf = kzalloc(SZ_4K, GFP_KERNEL); | |
882 | if (!onenand->page_buf) { | |
883 | err = -ENOMEM; | |
884 | goto page_buf_fail; | |
885 | } | |
886 | ||
887 | /* Allocate 128 SpareRAM */ | |
888 | onenand->oob_buf = kzalloc(128, GFP_KERNEL); | |
889 | if (!onenand->oob_buf) { | |
890 | err = -ENOMEM; | |
891 | goto oob_buf_fail; | |
892 | } | |
893 | ||
894 | /* S3C doesn't handle subpage write */ | |
895 | mtd->subpage_sft = 0; | |
896 | this->subpagesize = mtd->writesize; | |
897 | ||
898 | } else { /* S5PC110 */ | |
899 | r = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
900 | if (!r) { | |
901 | dev_err(&pdev->dev, "no dma memory resource defined\n"); | |
902 | return -ENOENT; | |
903 | goto dma_resource_failed; | |
904 | } | |
905 | ||
906 | onenand->dma_res = request_mem_region(r->start, resource_size(r), | |
907 | pdev->name); | |
908 | if (!onenand->dma_res) { | |
909 | dev_err(&pdev->dev, "failed to request dma memory resource\n"); | |
910 | err = -EBUSY; | |
911 | goto dma_resource_failed; | |
912 | } | |
913 | ||
914 | onenand->dma_addr = ioremap(r->start, resource_size(r)); | |
915 | if (!onenand->dma_addr) { | |
916 | dev_err(&pdev->dev, "failed to map dma memory resource\n"); | |
917 | err = -EINVAL; | |
918 | goto dma_ioremap_failed; | |
919 | } | |
920 | ||
921 | onenand->phys_base = onenand->base_res->start; | |
46f3e88b KP |
922 | } |
923 | ||
924 | if (onenand_scan(mtd, 1)) { | |
925 | err = -EFAULT; | |
926 | goto scan_failed; | |
927 | } | |
928 | ||
7b0507eb | 929 | if (onenand->type != TYPE_S5PC110) { |
46f3e88b KP |
930 | /* S3C doesn't handle subpage write */ |
931 | mtd->subpage_sft = 0; | |
932 | this->subpagesize = mtd->writesize; | |
933 | } | |
934 | ||
935 | if (s3c_read_reg(MEM_CFG_OFFSET) & ONENAND_SYS_CFG1_SYNC_READ) | |
936 | dev_info(&onenand->pdev->dev, "OneNAND Sync. Burst Read enabled\n"); | |
937 | ||
938 | #ifdef CONFIG_MTD_PARTITIONS | |
939 | err = parse_mtd_partitions(mtd, part_probes, &onenand->parts, 0); | |
940 | if (err > 0) | |
941 | add_mtd_partitions(mtd, onenand->parts, err); | |
942 | else if (err <= 0 && pdata && pdata->parts) | |
943 | add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts); | |
944 | else | |
945 | #endif | |
946 | err = add_mtd_device(mtd); | |
947 | ||
948 | platform_set_drvdata(pdev, mtd); | |
949 | ||
950 | return 0; | |
951 | ||
952 | scan_failed: | |
953 | if (onenand->dma_addr) | |
954 | iounmap(onenand->dma_addr); | |
955 | dma_ioremap_failed: | |
956 | if (onenand->dma_res) | |
957 | release_mem_region(onenand->dma_res->start, | |
958 | resource_size(onenand->dma_res)); | |
959 | kfree(onenand->oob_buf); | |
960 | oob_buf_fail: | |
961 | kfree(onenand->page_buf); | |
962 | page_buf_fail: | |
963 | if (onenand->ahb_addr) | |
964 | iounmap(onenand->ahb_addr); | |
965 | ahb_ioremap_failed: | |
966 | if (onenand->ahb_res) | |
967 | release_mem_region(onenand->ahb_res->start, | |
968 | resource_size(onenand->ahb_res)); | |
969 | dma_resource_failed: | |
970 | ahb_resource_failed: | |
971 | iounmap(onenand->base); | |
972 | ioremap_failed: | |
973 | if (onenand->base_res) | |
974 | release_mem_region(onenand->base_res->start, | |
975 | resource_size(onenand->base_res)); | |
976 | resource_failed: | |
977 | kfree(onenand); | |
978 | onenand_fail: | |
979 | kfree(mtd); | |
980 | return err; | |
981 | } | |
982 | ||
983 | static int __devexit s3c_onenand_remove(struct platform_device *pdev) | |
984 | { | |
985 | struct mtd_info *mtd = platform_get_drvdata(pdev); | |
986 | ||
987 | onenand_release(mtd); | |
988 | if (onenand->ahb_addr) | |
989 | iounmap(onenand->ahb_addr); | |
990 | if (onenand->ahb_res) | |
991 | release_mem_region(onenand->ahb_res->start, | |
992 | resource_size(onenand->ahb_res)); | |
993 | if (onenand->dma_addr) | |
994 | iounmap(onenand->dma_addr); | |
995 | if (onenand->dma_res) | |
996 | release_mem_region(onenand->dma_res->start, | |
997 | resource_size(onenand->dma_res)); | |
998 | ||
999 | iounmap(onenand->base); | |
1000 | release_mem_region(onenand->base_res->start, | |
1001 | resource_size(onenand->base_res)); | |
1002 | ||
1003 | platform_set_drvdata(pdev, NULL); | |
1004 | kfree(onenand->oob_buf); | |
1005 | kfree(onenand->page_buf); | |
1006 | kfree(onenand); | |
1007 | kfree(mtd); | |
1008 | return 0; | |
1009 | } | |
1010 | ||
1011 | static int s3c_pm_ops_suspend(struct device *dev) | |
1012 | { | |
1013 | struct platform_device *pdev = to_platform_device(dev); | |
1014 | struct mtd_info *mtd = platform_get_drvdata(pdev); | |
1015 | struct onenand_chip *this = mtd->priv; | |
1016 | ||
1017 | this->wait(mtd, FL_PM_SUSPENDED); | |
1018 | return mtd->suspend(mtd); | |
1019 | } | |
1020 | ||
1021 | static int s3c_pm_ops_resume(struct device *dev) | |
1022 | { | |
1023 | struct platform_device *pdev = to_platform_device(dev); | |
1024 | struct mtd_info *mtd = platform_get_drvdata(pdev); | |
1025 | struct onenand_chip *this = mtd->priv; | |
1026 | ||
1027 | mtd->resume(mtd); | |
1028 | this->unlock_all(mtd); | |
1029 | return 0; | |
1030 | } | |
1031 | ||
1032 | static const struct dev_pm_ops s3c_pm_ops = { | |
1033 | .suspend = s3c_pm_ops_suspend, | |
1034 | .resume = s3c_pm_ops_resume, | |
1035 | }; | |
1036 | ||
1037 | static struct platform_device_id s3c_onenand_driver_ids[] = { | |
1038 | { | |
1039 | .name = "s3c6400-onenand", | |
1040 | .driver_data = TYPE_S3C6400, | |
1041 | }, { | |
1042 | .name = "s3c6410-onenand", | |
1043 | .driver_data = TYPE_S3C6410, | |
1044 | }, { | |
1045 | .name = "s5pc100-onenand", | |
1046 | .driver_data = TYPE_S5PC100, | |
1047 | }, { | |
1048 | .name = "s5pc110-onenand", | |
1049 | .driver_data = TYPE_S5PC110, | |
1050 | }, { }, | |
1051 | }; | |
1052 | MODULE_DEVICE_TABLE(platform, s3c_onenand_driver_ids); | |
1053 | ||
1054 | static struct platform_driver s3c_onenand_driver = { | |
1055 | .driver = { | |
1056 | .name = "samsung-onenand", | |
1057 | .pm = &s3c_pm_ops, | |
1058 | }, | |
1059 | .id_table = s3c_onenand_driver_ids, | |
1060 | .probe = s3c_onenand_probe, | |
1061 | .remove = __devexit_p(s3c_onenand_remove), | |
1062 | }; | |
1063 | ||
1064 | static int __init s3c_onenand_init(void) | |
1065 | { | |
1066 | return platform_driver_register(&s3c_onenand_driver); | |
1067 | } | |
1068 | ||
1069 | static void __exit s3c_onenand_exit(void) | |
1070 | { | |
1071 | platform_driver_unregister(&s3c_onenand_driver); | |
1072 | } | |
1073 | ||
1074 | module_init(s3c_onenand_init); | |
1075 | module_exit(s3c_onenand_exit); | |
1076 | ||
1077 | MODULE_LICENSE("GPL"); | |
1078 | MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>"); | |
1079 | MODULE_DESCRIPTION("Samsung OneNAND controller support"); |