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Merge tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
[mirror_ubuntu-artful-kernel.git] / drivers / mtd / spi-nor / atmel-quadspi.c
CommitLineData
161aaab8
CP		 1/*
2 * Driver for Atmel QSPI Controller
3 *
4 * Copyright (C) 2015 Atmel Corporation
5 *
6 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 *
20 * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
21 */
22
23#include <linux/kernel.h>
24#include <linux/clk.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/delay.h>
28#include <linux/err.h>
29#include <linux/interrupt.h>
30#include <linux/mtd/mtd.h>
31#include <linux/mtd/partitions.h>
32#include <linux/mtd/spi-nor.h>
33#include <linux/platform_data/atmel.h>
34#include <linux/of.h>
35
36#include <linux/io.h>
37#include <linux/gpio.h>
38#include <linux/pinctrl/consumer.h>
39
40/* QSPI register offsets */
41#define QSPI_CR 0x0000 /* Control Register */
42#define QSPI_MR 0x0004 /* Mode Register */
43#define QSPI_RD 0x0008 /* Receive Data Register */
44#define QSPI_TD 0x000c /* Transmit Data Register */
45#define QSPI_SR 0x0010 /* Status Register */
46#define QSPI_IER 0x0014 /* Interrupt Enable Register */
47#define QSPI_IDR 0x0018 /* Interrupt Disable Register */
48#define QSPI_IMR 0x001c /* Interrupt Mask Register */
49#define QSPI_SCR 0x0020 /* Serial Clock Register */
50
51#define QSPI_IAR 0x0030 /* Instruction Address Register */
52#define QSPI_ICR 0x0034 /* Instruction Code Register */
53#define QSPI_IFR 0x0038 /* Instruction Frame Register */
54
55#define QSPI_SMR 0x0040 /* Scrambling Mode Register */
56#define QSPI_SKR 0x0044 /* Scrambling Key Register */
57
58#define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
59#define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
60
61#define QSPI_VERSION 0x00FC /* Version Register */
62
63
64/* Bitfields in QSPI_CR (Control Register) */
65#define QSPI_CR_QSPIEN BIT(0)
66#define QSPI_CR_QSPIDIS BIT(1)
67#define QSPI_CR_SWRST BIT(7)
68#define QSPI_CR_LASTXFER BIT(24)
69
70/* Bitfields in QSPI_MR (Mode Register) */
71#define QSPI_MR_SSM BIT(0)
72#define QSPI_MR_LLB BIT(1)
73#define QSPI_MR_WDRBT BIT(2)
74#define QSPI_MR_SMRM BIT(3)
75#define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
76#define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
77#define QSPI_MR_CSMODE_LASTXFER (1 << 4)
78#define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
79#define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
80#define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
81#define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
82#define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
83#define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
84#define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
85
86/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
87#define QSPI_SR_RDRF BIT(0)
88#define QSPI_SR_TDRE BIT(1)
89#define QSPI_SR_TXEMPTY BIT(2)
90#define QSPI_SR_OVRES BIT(3)
91#define QSPI_SR_CSR BIT(8)
92#define QSPI_SR_CSS BIT(9)
93#define QSPI_SR_INSTRE BIT(10)
94#define QSPI_SR_QSPIENS BIT(24)
95
96#define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
97
98/* Bitfields in QSPI_SCR (Serial Clock Register) */
99#define QSPI_SCR_CPOL BIT(0)
100#define QSPI_SCR_CPHA BIT(1)
101#define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
102#define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
103#define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
104#define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
105
106/* Bitfields in QSPI_ICR (Instruction Code Register) */
107#define QSPI_ICR_INST_MASK GENMASK(7, 0)
108#define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
109#define QSPI_ICR_OPT_MASK GENMASK(23, 16)
110#define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
111
112/* Bitfields in QSPI_IFR (Instruction Frame Register) */
113#define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
114#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
115#define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
116#define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
117#define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
118#define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
119#define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
120#define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
121#define QSPI_IFR_INSTEN BIT(4)
122#define QSPI_IFR_ADDREN BIT(5)
123#define QSPI_IFR_OPTEN BIT(6)
124#define QSPI_IFR_DATAEN BIT(7)
125#define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
126#define QSPI_IFR_OPTL_1BIT (0 << 8)
127#define QSPI_IFR_OPTL_2BIT (1 << 8)
128#define QSPI_IFR_OPTL_4BIT (2 << 8)
129#define QSPI_IFR_OPTL_8BIT (3 << 8)
130#define QSPI_IFR_ADDRL BIT(10)
131#define QSPI_IFR_TFRTYP_MASK GENMASK(13, 12)
132#define QSPI_IFR_TFRTYP_TRSFR_READ (0 << 12)
133#define QSPI_IFR_TFRTYP_TRSFR_READ_MEM (1 << 12)
134#define QSPI_IFR_TFRTYP_TRSFR_WRITE (2 << 12)
135#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEM (3 << 13)
136#define QSPI_IFR_CRM BIT(14)
137#define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
138#define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
139
140/* Bitfields in QSPI_SMR (Scrambling Mode Register) */
141#define QSPI_SMR_SCREN BIT(0)
142#define QSPI_SMR_RVDIS BIT(1)
143
144/* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
145#define QSPI_WPMR_WPEN BIT(0)
146#define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
147#define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
148
149/* Bitfields in QSPI_WPSR (Write Protection Status Register) */
150#define QSPI_WPSR_WPVS BIT(0)
151#define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
152#define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
153
154
155struct atmel_qspi {
156 void __iomem *regs;
157 void __iomem *mem;
158 struct clk *clk;
159 struct platform_device *pdev;
160 u32 pending;
161
162 struct spi_nor nor;
163 u32 clk_rate;
164 struct completion cmd_completion;
165};
166
167struct atmel_qspi_command {
168 union {
169 struct {
170 u32 instruction:1;
171 u32 address:3;
172 u32 mode:1;
173 u32 dummy:1;
174 u32 data:1;
175 u32 reserved:25;
176 } bits;
177 u32 word;
178 } enable;
179 u8 instruction;
180 u8 mode;
181 u8 num_mode_cycles;
182 u8 num_dummy_cycles;
183 u32 address;
184
185 size_t buf_len;
186 const void *tx_buf;
187 void *rx_buf;
188};
189
190/* Register access functions */
191static inline u32 qspi_readl(struct atmel_qspi *aq, u32 reg)
192{
193 return readl_relaxed(aq->regs + reg);
194}
195
196static inline void qspi_writel(struct atmel_qspi *aq, u32 reg, u32 value)
197{
198 writel_relaxed(value, aq->regs + reg);
199}
200
201static int atmel_qspi_run_transfer(struct atmel_qspi *aq,
202 const struct atmel_qspi_command *cmd)
203{
204 void __iomem *ahb_mem;
205
206 /* Then fallback to a PIO transfer (memcpy() DOES NOT work!) */
207 ahb_mem = aq->mem;
208 if (cmd->enable.bits.address)
209 ahb_mem += cmd->address;
210 if (cmd->tx_buf)
211 _memcpy_toio(ahb_mem, cmd->tx_buf, cmd->buf_len);
212 else
213 _memcpy_fromio(cmd->rx_buf, ahb_mem, cmd->buf_len);
214
215 return 0;
216}
217
218#ifdef DEBUG
219static void atmel_qspi_debug_command(struct atmel_qspi *aq,
220 const struct atmel_qspi_command *cmd,
221 u32 ifr)
222{
223 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
224 size_t len = 0;
225 int i;
226
227 if (cmd->enable.bits.instruction)
228 cmd_buf[len++] = cmd->instruction;
229
230 for (i = cmd->enable.bits.address-1; i >= 0; --i)
231 cmd_buf[len++] = (cmd->address >> (i << 3)) & 0xff;
232
233 if (cmd->enable.bits.mode)
234 cmd_buf[len++] = cmd->mode;
235
236 if (cmd->enable.bits.dummy) {
237 int num = cmd->num_dummy_cycles;
238
239 switch (ifr & QSPI_IFR_WIDTH_MASK) {
240 case QSPI_IFR_WIDTH_SINGLE_BIT_SPI:
241 case QSPI_IFR_WIDTH_DUAL_OUTPUT:
242 case QSPI_IFR_WIDTH_QUAD_OUTPUT:
243 num >>= 3;
244 break;
245 case QSPI_IFR_WIDTH_DUAL_IO:
246 case QSPI_IFR_WIDTH_DUAL_CMD:
247 num >>= 2;
248 break;
249 case QSPI_IFR_WIDTH_QUAD_IO:
250 case QSPI_IFR_WIDTH_QUAD_CMD:
251 num >>= 1;
252 break;
253 default:
254 return;
255 }
256
257 for (i = 0; i < num; ++i)
258 cmd_buf[len++] = 0;
259 }
260
261 /* Dump the SPI command */
262 print_hex_dump(KERN_DEBUG, "qspi cmd: ", DUMP_PREFIX_NONE,
263 32, 1, cmd_buf, len, false);
264
265#ifdef VERBOSE_DEBUG
266 /* If verbose debug is enabled, also dump the TX data */
267 if (cmd->enable.bits.data && cmd->tx_buf)
268 print_hex_dump(KERN_DEBUG, "qspi tx : ", DUMP_PREFIX_NONE,
269 32, 1, cmd->tx_buf, cmd->buf_len, false);
270#endif
271}
272#else
273#define atmel_qspi_debug_command(aq, cmd, ifr)
274#endif
275
276static int atmel_qspi_run_command(struct atmel_qspi *aq,
277 const struct atmel_qspi_command *cmd,
cfc5604c 278 u32 ifr_tfrtyp, enum spi_nor_protocol proto)
161aaab8
CP		 279{
280 u32 iar, icr, ifr, sr;
281 int err = 0;
282
283 iar = 0;
284 icr = 0;
cfc5604c
CP		 285 ifr = ifr_tfrtyp;
286
287 /* Set the SPI protocol */
288 switch (proto) {
289 case SNOR_PROTO_1_1_1:
290 ifr |= QSPI_IFR_WIDTH_SINGLE_BIT_SPI;
291 break;
292
293 case SNOR_PROTO_1_1_2:
294 ifr |= QSPI_IFR_WIDTH_DUAL_OUTPUT;
295 break;
296
297 case SNOR_PROTO_1_1_4:
298 ifr |= QSPI_IFR_WIDTH_QUAD_OUTPUT;
299 break;
300
301 case SNOR_PROTO_1_2_2:
302 ifr |= QSPI_IFR_WIDTH_DUAL_IO;
303 break;
304
305 case SNOR_PROTO_1_4_4:
306 ifr |= QSPI_IFR_WIDTH_QUAD_IO;
307 break;
308
309 case SNOR_PROTO_2_2_2:
310 ifr |= QSPI_IFR_WIDTH_DUAL_CMD;
311 break;
312
313 case SNOR_PROTO_4_4_4:
314 ifr |= QSPI_IFR_WIDTH_QUAD_CMD;
315 break;
316
317 default:
318 return -EINVAL;
319 }
161aaab8
CP		 320
321 /* Compute instruction parameters */
322 if (cmd->enable.bits.instruction) {
323 icr |= QSPI_ICR_INST(cmd->instruction);
324 ifr |= QSPI_IFR_INSTEN;
325 }
326
327 /* Compute address parameters */
328 switch (cmd->enable.bits.address) {
329 case 4:
330 ifr |= QSPI_IFR_ADDRL;
331 /* fall through to the 24bit (3 byte) address case. */
332 case 3:
333 iar = (cmd->enable.bits.data) ? 0 : cmd->address;
334 ifr |= QSPI_IFR_ADDREN;
335 break;
336 case 0:
337 break;
338 default:
339 return -EINVAL;
340 }
341
342 /* Compute option parameters */
343 if (cmd->enable.bits.mode && cmd->num_mode_cycles) {
344 u32 mode_cycle_bits, mode_bits;
345
346 icr |= QSPI_ICR_OPT(cmd->mode);
347 ifr |= QSPI_IFR_OPTEN;
348
349 switch (ifr & QSPI_IFR_WIDTH_MASK) {
350 case QSPI_IFR_WIDTH_SINGLE_BIT_SPI:
351 case QSPI_IFR_WIDTH_DUAL_OUTPUT:
352 case QSPI_IFR_WIDTH_QUAD_OUTPUT:
353 mode_cycle_bits = 1;
354 break;
355 case QSPI_IFR_WIDTH_DUAL_IO:
356 case QSPI_IFR_WIDTH_DUAL_CMD:
357 mode_cycle_bits = 2;
358 break;
359 case QSPI_IFR_WIDTH_QUAD_IO:
360 case QSPI_IFR_WIDTH_QUAD_CMD:
361 mode_cycle_bits = 4;
362 break;
363 default:
364 return -EINVAL;
365 }
366
367 mode_bits = cmd->num_mode_cycles * mode_cycle_bits;
368 switch (mode_bits) {
369 case 1:
370 ifr |= QSPI_IFR_OPTL_1BIT;
371 break;
372
373 case 2:
374 ifr |= QSPI_IFR_OPTL_2BIT;
375 break;
376
377 case 4:
378 ifr |= QSPI_IFR_OPTL_4BIT;
379 break;
380
381 case 8:
382 ifr |= QSPI_IFR_OPTL_8BIT;
383 break;
384
385 default:
386 return -EINVAL;
387 }
388 }
389
390 /* Set number of dummy cycles */
391 if (cmd->enable.bits.dummy)
392 ifr |= QSPI_IFR_NBDUM(cmd->num_dummy_cycles);
393
394 /* Set data enable */
395 if (cmd->enable.bits.data) {
396 ifr |= QSPI_IFR_DATAEN;
397
398 /* Special case for Continuous Read Mode */
399 if (!cmd->tx_buf && !cmd->rx_buf)
400 ifr |= QSPI_IFR_CRM;
401 }
402
403 /* Clear pending interrupts */
404 (void)qspi_readl(aq, QSPI_SR);
405
406 /* Set QSPI Instruction Frame registers */
407 atmel_qspi_debug_command(aq, cmd, ifr);
408 qspi_writel(aq, QSPI_IAR, iar);
409 qspi_writel(aq, QSPI_ICR, icr);
410 qspi_writel(aq, QSPI_IFR, ifr);
411
412 /* Skip to the final steps if there is no data */
413 if (!cmd->enable.bits.data)
414 goto no_data;
415
416 /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
417 (void)qspi_readl(aq, QSPI_IFR);
418
419 /* Stop here for continuous read */
420 if (!cmd->tx_buf && !cmd->rx_buf)
421 return 0;
422 /* Send/Receive data */
423 err = atmel_qspi_run_transfer(aq, cmd);
424
425 /* Release the chip-select */
426 qspi_writel(aq, QSPI_CR, QSPI_CR_LASTXFER);
427
428 if (err)
429 return err;
430
431#if defined(DEBUG) && defined(VERBOSE_DEBUG)
432 /*
433 * If verbose debug is enabled, also dump the RX data in addition to
434 * the SPI command previously dumped by atmel_qspi_debug_command()
435 */
436 if (cmd->rx_buf)
437 print_hex_dump(KERN_DEBUG, "qspi rx : ", DUMP_PREFIX_NONE,
438 32, 1, cmd->rx_buf, cmd->buf_len, false);
439#endif
440no_data:
441 /* Poll INSTRuction End status */
442 sr = qspi_readl(aq, QSPI_SR);
443 if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
444 return err;
445
446 /* Wait for INSTRuction End interrupt */
447 reinit_completion(&aq->cmd_completion);
448 aq->pending = sr & QSPI_SR_CMD_COMPLETED;
449 qspi_writel(aq, QSPI_IER, QSPI_SR_CMD_COMPLETED);
450 if (!wait_for_completion_timeout(&aq->cmd_completion,
451 msecs_to_jiffies(1000)))
452 err = -ETIMEDOUT;
453 qspi_writel(aq, QSPI_IDR, QSPI_SR_CMD_COMPLETED);
454
455 return err;
456}
457
458static int atmel_qspi_read_reg(struct spi_nor *nor, u8 opcode,
459 u8 *buf, int len)
460{
461 struct atmel_qspi *aq = nor->priv;
462 struct atmel_qspi_command cmd;
463
464 memset(&cmd, 0, sizeof(cmd));
465 cmd.enable.bits.instruction = 1;
466 cmd.enable.bits.data = 1;
467 cmd.instruction = opcode;
468 cmd.rx_buf = buf;
469 cmd.buf_len = len;
470 return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_READ,
cfc5604c 471 nor->reg_proto);
161aaab8
CP		 472}
473
474static int atmel_qspi_write_reg(struct spi_nor *nor, u8 opcode,
475 u8 *buf, int len)
476{
477 struct atmel_qspi *aq = nor->priv;
478 struct atmel_qspi_command cmd;
479
480 memset(&cmd, 0, sizeof(cmd));
481 cmd.enable.bits.instruction = 1;
482 cmd.enable.bits.data = (buf != NULL && len > 0);
483 cmd.instruction = opcode;
484 cmd.tx_buf = buf;
485 cmd.buf_len = len;
486 return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE,
cfc5604c 487 nor->reg_proto);
161aaab8
CP		 488}
489
490static ssize_t atmel_qspi_write(struct spi_nor *nor, loff_t to, size_t len,
491 const u_char *write_buf)
492{
493 struct atmel_qspi *aq = nor->priv;
494 struct atmel_qspi_command cmd;
495 ssize_t ret;
496
497 memset(&cmd, 0, sizeof(cmd));
498 cmd.enable.bits.instruction = 1;
499 cmd.enable.bits.address = nor->addr_width;
500 cmd.enable.bits.data = 1;
501 cmd.instruction = nor->program_opcode;
502 cmd.address = (u32)to;
503 cmd.tx_buf = write_buf;
504 cmd.buf_len = len;
505 ret = atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE_MEM,
cfc5604c 506 nor->write_proto);
161aaab8
CP		 507 return (ret < 0) ? ret : len;
508}
509
510static int atmel_qspi_erase(struct spi_nor *nor, loff_t offs)
511{
512 struct atmel_qspi *aq = nor->priv;
513 struct atmel_qspi_command cmd;
514
515 memset(&cmd, 0, sizeof(cmd));
516 cmd.enable.bits.instruction = 1;
517 cmd.enable.bits.address = nor->addr_width;
518 cmd.instruction = nor->erase_opcode;
519 cmd.address = (u32)offs;
520 return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE,
cfc5604c 521 nor->reg_proto);
161aaab8
CP		 522}
523
524static ssize_t atmel_qspi_read(struct spi_nor *nor, loff_t from, size_t len,
525 u_char *read_buf)
526{
527 struct atmel_qspi *aq = nor->priv;
528 struct atmel_qspi_command cmd;
529 u8 num_mode_cycles, num_dummy_cycles;
161aaab8
CP		 530 ssize_t ret;
531
161aaab8
CP		 532 if (nor->read_dummy >= 2) {
533 num_mode_cycles = 2;
534 num_dummy_cycles = nor->read_dummy - 2;
535 } else {
536 num_mode_cycles = nor->read_dummy;
537 num_dummy_cycles = 0;
538 }
539
540 memset(&cmd, 0, sizeof(cmd));
541 cmd.enable.bits.instruction = 1;
542 cmd.enable.bits.address = nor->addr_width;
543 cmd.enable.bits.mode = (num_mode_cycles > 0);
544 cmd.enable.bits.dummy = (num_dummy_cycles > 0);
545 cmd.enable.bits.data = 1;
546 cmd.instruction = nor->read_opcode;
547 cmd.address = (u32)from;
548 cmd.mode = 0xff; /* This value prevents from entering the 0-4-4 mode */
549 cmd.num_mode_cycles = num_mode_cycles;
550 cmd.num_dummy_cycles = num_dummy_cycles;
551 cmd.rx_buf = read_buf;
552 cmd.buf_len = len;
553 ret = atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_READ_MEM,
cfc5604c 554 nor->read_proto);
161aaab8
CP		 555 return (ret < 0) ? ret : len;
556}
557
558static int atmel_qspi_init(struct atmel_qspi *aq)
559{
560 unsigned long src_rate;
561 u32 mr, scr, scbr;
562
563 /* Reset the QSPI controller */
564 qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST);
565
566 /* Set the QSPI controller in Serial Memory Mode */
567 mr = QSPI_MR_NBBITS(8) | QSPI_MR_SSM;
568 qspi_writel(aq, QSPI_MR, mr);
569
570 src_rate = clk_get_rate(aq->clk);
571 if (!src_rate)
572 return -EINVAL;
573
574 /* Compute the QSPI baudrate */
575 scbr = DIV_ROUND_UP(src_rate, aq->clk_rate);
576 if (scbr > 0)
577 scbr--;
578 scr = QSPI_SCR_SCBR(scbr);
579 qspi_writel(aq, QSPI_SCR, scr);
580
581 /* Enable the QSPI controller */
582 qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN);
583
584 return 0;
585}
586
587static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
588{
589 struct atmel_qspi *aq = (struct atmel_qspi *)dev_id;
590 u32 status, mask, pending;
591
592 status = qspi_readl(aq, QSPI_SR);
593 mask = qspi_readl(aq, QSPI_IMR);
594 pending = status & mask;
595
596 if (!pending)
597 return IRQ_NONE;
598
599 aq->pending |= pending;
600 if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
601 complete(&aq->cmd_completion);
602
603 return IRQ_HANDLED;
604}
605
606static int atmel_qspi_probe(struct platform_device *pdev)
607{
cfc5604c
CP		 608 const struct spi_nor_hwcaps hwcaps = {
609 .mask = SNOR_HWCAPS_READ |
610 SNOR_HWCAPS_READ_FAST |
611 SNOR_HWCAPS_READ_1_1_2 |
612 SNOR_HWCAPS_READ_1_2_2 |
613 SNOR_HWCAPS_READ_2_2_2 |
614 SNOR_HWCAPS_READ_1_1_4 |
615 SNOR_HWCAPS_READ_1_4_4 |
616 SNOR_HWCAPS_READ_4_4_4 |
617 SNOR_HWCAPS_PP |
618 SNOR_HWCAPS_PP_1_1_4 |
619 SNOR_HWCAPS_PP_1_4_4 |
620 SNOR_HWCAPS_PP_4_4_4,
621 };
161aaab8
CP		 622 struct device_node *child, *np = pdev->dev.of_node;
623 struct atmel_qspi *aq;
624 struct resource *res;
625 struct spi_nor *nor;
626 struct mtd_info *mtd;
627 int irq, err = 0;
628
629 if (of_get_child_count(np) != 1)
630 return -ENODEV;
631 child = of_get_next_child(np, NULL);
632
633 aq = devm_kzalloc(&pdev->dev, sizeof(*aq), GFP_KERNEL);
634 if (!aq) {
635 err = -ENOMEM;
636 goto exit;
637 }
638
639 platform_set_drvdata(pdev, aq);
640 init_completion(&aq->cmd_completion);
641 aq->pdev = pdev;
642
643 /* Map the registers */
644 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
645 aq->regs = devm_ioremap_resource(&pdev->dev, res);
646 if (IS_ERR(aq->regs)) {
647 dev_err(&pdev->dev, "missing registers\n");
648 err = PTR_ERR(aq->regs);
649 goto exit;
650 }
651
652 /* Map the AHB memory */
653 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap");
654 aq->mem = devm_ioremap_resource(&pdev->dev, res);
655 if (IS_ERR(aq->mem)) {
656 dev_err(&pdev->dev, "missing AHB memory\n");
657 err = PTR_ERR(aq->mem);
658 goto exit;
659 }
660
661 /* Get the peripheral clock */
662 aq->clk = devm_clk_get(&pdev->dev, NULL);
663 if (IS_ERR(aq->clk)) {
664 dev_err(&pdev->dev, "missing peripheral clock\n");
665 err = PTR_ERR(aq->clk);
666 goto exit;
667 }
668
669 /* Enable the peripheral clock */
670 err = clk_prepare_enable(aq->clk);
671 if (err) {
672 dev_err(&pdev->dev, "failed to enable the peripheral clock\n");
673 goto exit;
674 }
675
676 /* Request the IRQ */
677 irq = platform_get_irq(pdev, 0);
678 if (irq < 0) {
679 dev_err(&pdev->dev, "missing IRQ\n");
680 err = irq;
681 goto disable_clk;
682 }
683 err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
684 0, dev_name(&pdev->dev), aq);
685 if (err)
686 goto disable_clk;
687
688 /* Setup the spi-nor */
689 nor = &aq->nor;
690 mtd = &nor->mtd;
691
692 nor->dev = &pdev->dev;
693 spi_nor_set_flash_node(nor, child);
694 nor->priv = aq;
695 mtd->priv = nor;
696
697 nor->read_reg = atmel_qspi_read_reg;
698 nor->write_reg = atmel_qspi_write_reg;
699 nor->read = atmel_qspi_read;
700 nor->write = atmel_qspi_write;
701 nor->erase = atmel_qspi_erase;
702
703 err = of_property_read_u32(child, "spi-max-frequency", &aq->clk_rate);
704 if (err < 0)
705 goto disable_clk;
706
707 err = atmel_qspi_init(aq);
708 if (err)
709 goto disable_clk;
710
cfc5604c 711 err = spi_nor_scan(nor, NULL, &hwcaps);
161aaab8
CP		 712 if (err)
713 goto disable_clk;
714
715 err = mtd_device_register(mtd, NULL, 0);
716 if (err)
717 goto disable_clk;
718
719 of_node_put(child);
720
721 return 0;
722
723disable_clk:
724 clk_disable_unprepare(aq->clk);
725exit:
726 of_node_put(child);
727
728 return err;
729}
730
731static int atmel_qspi_remove(struct platform_device *pdev)
732{
733 struct atmel_qspi *aq = platform_get_drvdata(pdev);
734
735 mtd_device_unregister(&aq->nor.mtd);
736 qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIDIS);
737 clk_disable_unprepare(aq->clk);
738 return 0;
739}
740
741
742static const struct of_device_id atmel_qspi_dt_ids[] = {
743 { .compatible = "atmel,sama5d2-qspi" },
744 { /* sentinel */ }
745};
746
747MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);
748
749static struct platform_driver atmel_qspi_driver = {
750 .driver = {
751 .name = "atmel_qspi",
752 .of_match_table = atmel_qspi_dt_ids,
753 },
754 .probe = atmel_qspi_probe,
755 .remove = atmel_qspi_remove,
756};
757module_platform_driver(atmel_qspi_driver);
758
759MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
760MODULE_DESCRIPTION("Atmel QSPI Controller driver");
761MODULE_LICENSE("GPL v2");
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