[mirror_ubuntu-jammy-kernel.git] / drivers / mtd / spi-nor / mtk-quadspi.c

/*
 * Copyright (c) 2015 MediaTek Inc.
 * Author: Bayi Cheng <bayi.cheng@mediatek.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/ioport.h>
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/spi-nor.h>

#define MTK_NOR_CMD_REG			0x00
#define MTK_NOR_CNT_REG			0x04
#define MTK_NOR_RDSR_REG		0x08
#define MTK_NOR_RDATA_REG		0x0c
#define MTK_NOR_RADR0_REG		0x10
#define MTK_NOR_RADR1_REG		0x14
#define MTK_NOR_RADR2_REG		0x18
#define MTK_NOR_WDATA_REG		0x1c
#define MTK_NOR_PRGDATA0_REG		0x20
#define MTK_NOR_PRGDATA1_REG		0x24
#define MTK_NOR_PRGDATA2_REG		0x28
#define MTK_NOR_PRGDATA3_REG		0x2c
#define MTK_NOR_PRGDATA4_REG		0x30
#define MTK_NOR_PRGDATA5_REG		0x34
#define MTK_NOR_SHREG0_REG		0x38
#define MTK_NOR_SHREG1_REG		0x3c
#define MTK_NOR_SHREG2_REG		0x40
#define MTK_NOR_SHREG3_REG		0x44
#define MTK_NOR_SHREG4_REG		0x48
#define MTK_NOR_SHREG5_REG		0x4c
#define MTK_NOR_SHREG6_REG		0x50
#define MTK_NOR_SHREG7_REG		0x54
#define MTK_NOR_SHREG8_REG		0x58
#define MTK_NOR_SHREG9_REG		0x5c
#define MTK_NOR_CFG1_REG		0x60
#define MTK_NOR_CFG2_REG		0x64
#define MTK_NOR_CFG3_REG		0x68
#define MTK_NOR_STATUS0_REG		0x70
#define MTK_NOR_STATUS1_REG		0x74
#define MTK_NOR_STATUS2_REG		0x78
#define MTK_NOR_STATUS3_REG		0x7c
#define MTK_NOR_FLHCFG_REG		0x84
#define MTK_NOR_TIME_REG		0x94
#define MTK_NOR_PP_DATA_REG		0x98
#define MTK_NOR_PREBUF_STUS_REG		0x9c
#define MTK_NOR_DELSEL0_REG		0xa0
#define MTK_NOR_DELSEL1_REG		0xa4
#define MTK_NOR_INTRSTUS_REG		0xa8
#define MTK_NOR_INTREN_REG		0xac
#define MTK_NOR_CHKSUM_CTL_REG		0xb8
#define MTK_NOR_CHKSUM_REG		0xbc
#define MTK_NOR_CMD2_REG		0xc0
#define MTK_NOR_WRPROT_REG		0xc4
#define MTK_NOR_RADR3_REG		0xc8
#define MTK_NOR_DUAL_REG		0xcc
#define MTK_NOR_DELSEL2_REG		0xd0
#define MTK_NOR_DELSEL3_REG		0xd4
#define MTK_NOR_DELSEL4_REG		0xd8

/* commands for mtk nor controller */
#define MTK_NOR_READ_CMD		0x0
#define MTK_NOR_RDSR_CMD		0x2
#define MTK_NOR_PRG_CMD			0x4
#define MTK_NOR_WR_CMD			0x10
#define MTK_NOR_PIO_WR_CMD		0x90
#define MTK_NOR_WRSR_CMD		0x20
#define MTK_NOR_PIO_READ_CMD		0x81
#define MTK_NOR_WR_BUF_ENABLE		0x1
#define MTK_NOR_WR_BUF_DISABLE		0x0
#define MTK_NOR_ENABLE_SF_CMD		0x30
#define MTK_NOR_DUAD_ADDR_EN		0x8
#define MTK_NOR_QUAD_READ_EN		0x4
#define MTK_NOR_DUAL_ADDR_EN		0x2
#define MTK_NOR_DUAL_READ_EN		0x1
#define MTK_NOR_DUAL_DISABLE		0x0
#define MTK_NOR_FAST_READ		0x1

#define SFLASH_WRBUF_SIZE		128

/* Can shift up to 48 bits (6 bytes) of TX/RX */
#define MTK_NOR_MAX_RX_TX_SHIFT		6
/* can shift up to 56 bits (7 bytes) transfer by MTK_NOR_PRG_CMD */
#define MTK_NOR_MAX_SHIFT		7
/* nor controller 4-byte address mode enable bit */
#define MTK_NOR_4B_ADDR_EN		BIT(4)

/* Helpers for accessing the program data / shift data registers */
#define MTK_NOR_PRG_REG(n)		(MTK_NOR_PRGDATA0_REG + 4 * (n))
#define MTK_NOR_SHREG(n)		(MTK_NOR_SHREG0_REG + 4 * (n))

struct mtk_nor {
	struct spi_nor nor;
	struct device *dev;
	void __iomem *base;	/* nor flash base address */
	struct clk *spi_clk;
	struct clk *nor_clk;
};

static void mtk_nor_set_read_mode(struct mtk_nor *mtk_nor)
{
	struct spi_nor *nor = &mtk_nor->nor;

	switch (nor->read_proto) {
	case SNOR_PROTO_1_1_1:
		writeb(nor->read_opcode, mtk_nor->base +
		       MTK_NOR_PRGDATA3_REG);
		writeb(MTK_NOR_FAST_READ, mtk_nor->base +
		       MTK_NOR_CFG1_REG);
		break;
	case SNOR_PROTO_1_1_2:
		writeb(nor->read_opcode, mtk_nor->base +
		       MTK_NOR_PRGDATA3_REG);
		writeb(MTK_NOR_DUAL_READ_EN, mtk_nor->base +
		       MTK_NOR_DUAL_REG);
		break;
	case SNOR_PROTO_1_1_4:
		writeb(nor->read_opcode, mtk_nor->base +
		       MTK_NOR_PRGDATA4_REG);
		writeb(MTK_NOR_QUAD_READ_EN, mtk_nor->base +
		       MTK_NOR_DUAL_REG);
		break;
	default:
		writeb(MTK_NOR_DUAL_DISABLE, mtk_nor->base +
		       MTK_NOR_DUAL_REG);
		break;
	}
}

static int mtk_nor_execute_cmd(struct mtk_nor *mtk_nor, u8 cmdval)
{
	int reg;
	u8 val = cmdval & 0x1f;

	writeb(cmdval, mtk_nor->base + MTK_NOR_CMD_REG);
	return readl_poll_timeout(mtk_nor->base + MTK_NOR_CMD_REG, reg,
				  !(reg & val), 100, 10000);
}

static int mtk_nor_do_tx_rx(struct mtk_nor *mtk_nor, u8 op,
			    u8 *tx, int txlen, u8 *rx, int rxlen)
{
	int len = 1 + txlen + rxlen;
	int i, ret, idx;

	if (len > MTK_NOR_MAX_SHIFT)
		return -EINVAL;

	writeb(len * 8, mtk_nor->base + MTK_NOR_CNT_REG);

	/* start at PRGDATA5, go down to PRGDATA0 */
	idx = MTK_NOR_MAX_RX_TX_SHIFT - 1;

	/* opcode */
	writeb(op, mtk_nor->base + MTK_NOR_PRG_REG(idx));
	idx--;

	/* program TX data */
	for (i = 0; i < txlen; i++, idx--)
		writeb(tx[i], mtk_nor->base + MTK_NOR_PRG_REG(idx));

	/* clear out rest of TX registers */
	while (idx >= 0) {
		writeb(0, mtk_nor->base + MTK_NOR_PRG_REG(idx));
		idx--;
	}

	ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PRG_CMD);
	if (ret)
		return ret;

	/* restart at first RX byte */
	idx = rxlen - 1;

	/* read out RX data */
	for (i = 0; i < rxlen; i++, idx--)
		rx[i] = readb(mtk_nor->base + MTK_NOR_SHREG(idx));

	return 0;
}

/* Do a WRSR (Write Status Register) command */
static int mtk_nor_wr_sr(struct mtk_nor *mtk_nor, u8 sr)
{
	writeb(sr, mtk_nor->base + MTK_NOR_PRGDATA5_REG);
	writeb(8, mtk_nor->base + MTK_NOR_CNT_REG);
	return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WRSR_CMD);
}

static int mtk_nor_write_buffer_enable(struct mtk_nor *mtk_nor)
{
	u8 reg;

	/* the bit0 of MTK_NOR_CFG2_REG is pre-fetch buffer
	 * 0: pre-fetch buffer use for read
	 * 1: pre-fetch buffer use for page program
	 */
	writel(MTK_NOR_WR_BUF_ENABLE, mtk_nor->base + MTK_NOR_CFG2_REG);
	return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg,
				  0x01 == (reg & 0x01), 100, 10000);
}

static int mtk_nor_write_buffer_disable(struct mtk_nor *mtk_nor)
{
	u8 reg;

	writel(MTK_NOR_WR_BUF_DISABLE, mtk_nor->base + MTK_NOR_CFG2_REG);
	return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg,
				  MTK_NOR_WR_BUF_DISABLE == (reg & 0x1), 100,
				  10000);
}

static void mtk_nor_set_addr_width(struct mtk_nor *mtk_nor)
{
	u8 val;
	struct spi_nor *nor = &mtk_nor->nor;

	val = readb(mtk_nor->base + MTK_NOR_DUAL_REG);

	switch (nor->addr_width) {
	case 3:
		val &= ~MTK_NOR_4B_ADDR_EN;
		break;
	case 4:
		val |= MTK_NOR_4B_ADDR_EN;
		break;
	default:
		dev_warn(mtk_nor->dev, "Unexpected address width %u.\n",
			 nor->addr_width);
		break;
	}

	writeb(val, mtk_nor->base + MTK_NOR_DUAL_REG);
}

static void mtk_nor_set_addr(struct mtk_nor *mtk_nor, u32 addr)
{
	int i;

	mtk_nor_set_addr_width(mtk_nor);

	for (i = 0; i < 3; i++) {
		writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR0_REG + i * 4);
		addr >>= 8;
	}
	/* Last register is non-contiguous */
	writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR3_REG);
}

static ssize_t mtk_nor_read(struct spi_nor *nor, loff_t from, size_t length,
			    u_char *buffer)
{
	int i, ret;
	int addr = (int)from;
	u8 *buf = (u8 *)buffer;
	struct mtk_nor *mtk_nor = nor->priv;

	/* set mode for fast read mode ,dual mode or quad mode */
	mtk_nor_set_read_mode(mtk_nor);
	mtk_nor_set_addr(mtk_nor, addr);

	for (i = 0; i < length; i++) {
		ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_READ_CMD);
		if (ret < 0)
			return ret;
		buf[i] = readb(mtk_nor->base + MTK_NOR_RDATA_REG);
	}
	return length;
}

static int mtk_nor_write_single_byte(struct mtk_nor *mtk_nor,
				     int addr, int length, u8 *data)
{
	int i, ret;

	mtk_nor_set_addr(mtk_nor, addr);

	for (i = 0; i < length; i++) {
		writeb(*data++, mtk_nor->base + MTK_NOR_WDATA_REG);
		ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_WR_CMD);
		if (ret < 0)
			return ret;
	}
	return 0;
}

static int mtk_nor_write_buffer(struct mtk_nor *mtk_nor, int addr,
				const u8 *buf)
{
	int i, bufidx, data;

	mtk_nor_set_addr(mtk_nor, addr);

	bufidx = 0;
	for (i = 0; i < SFLASH_WRBUF_SIZE; i += 4) {
		data = buf[bufidx + 3]<<24 | buf[bufidx + 2]<<16 |
		       buf[bufidx + 1]<<8 | buf[bufidx];
		bufidx += 4;
		writel(data, mtk_nor->base + MTK_NOR_PP_DATA_REG);
	}
	return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WR_CMD);
}

static ssize_t mtk_nor_write(struct spi_nor *nor, loff_t to, size_t len,
			     const u_char *buf)
{
	int ret;
	struct mtk_nor *mtk_nor = nor->priv;
	size_t i;

	ret = mtk_nor_write_buffer_enable(mtk_nor);
	if (ret < 0) {
		dev_warn(mtk_nor->dev, "write buffer enable failed!\n");
		return ret;
	}

	for (i = 0; i + SFLASH_WRBUF_SIZE <= len; i += SFLASH_WRBUF_SIZE) {
		ret = mtk_nor_write_buffer(mtk_nor, to, buf);
		if (ret < 0) {
			dev_err(mtk_nor->dev, "write buffer failed!\n");
			return ret;
		}
		to += SFLASH_WRBUF_SIZE;
		buf += SFLASH_WRBUF_SIZE;
	}
	ret = mtk_nor_write_buffer_disable(mtk_nor);
	if (ret < 0) {
		dev_warn(mtk_nor->dev, "write buffer disable failed!\n");
		return ret;
	}

	if (i < len) {
		ret = mtk_nor_write_single_byte(mtk_nor, to,
						(int)(len - i), (u8 *)buf);
		if (ret < 0) {
			dev_err(mtk_nor->dev, "write single byte failed!\n");
			return ret;
		}
	}

	return len;
}

static int mtk_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
{
	int ret;
	struct mtk_nor *mtk_nor = nor->priv;

	switch (opcode) {
	case SPINOR_OP_RDSR:
		ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_RDSR_CMD);
		if (ret < 0)
			return ret;
		if (len == 1)
			*buf = readb(mtk_nor->base + MTK_NOR_RDSR_REG);
		else
			dev_err(mtk_nor->dev, "len should be 1 for read status!\n");
		break;
	default:
		ret = mtk_nor_do_tx_rx(mtk_nor, opcode, NULL, 0, buf, len);
		break;
	}
	return ret;
}

static int mtk_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
			     int len)
{
	int ret;
	struct mtk_nor *mtk_nor = nor->priv;

	switch (opcode) {
	case SPINOR_OP_WRSR:
		/* We only handle 1 byte */
		ret = mtk_nor_wr_sr(mtk_nor, *buf);
		break;
	default:
		ret = mtk_nor_do_tx_rx(mtk_nor, opcode, buf, len, NULL, 0);
		if (ret)
			dev_warn(mtk_nor->dev, "write reg failure!\n");
		break;
	}
	return ret;
}

static void mtk_nor_disable_clk(struct mtk_nor *mtk_nor)
{
	clk_disable_unprepare(mtk_nor->spi_clk);
	clk_disable_unprepare(mtk_nor->nor_clk);
}

static int mtk_nor_enable_clk(struct mtk_nor *mtk_nor)
{
	int ret;

	ret = clk_prepare_enable(mtk_nor->spi_clk);
	if (ret)
		return ret;

	ret = clk_prepare_enable(mtk_nor->nor_clk);
	if (ret) {
		clk_disable_unprepare(mtk_nor->spi_clk);
		return ret;
	}

	return 0;
}

static int mtk_nor_init(struct mtk_nor *mtk_nor,
			struct device_node *flash_node)
{
	const struct spi_nor_hwcaps hwcaps = {
		.mask = SNOR_HWCAPS_READ_FAST |
			SNOR_HWCAPS_READ_1_1_2 |
			SNOR_HWCAPS_PP,
	};
	int ret;
	struct spi_nor *nor;

	/* initialize controller to accept commands */
	writel(MTK_NOR_ENABLE_SF_CMD, mtk_nor->base + MTK_NOR_WRPROT_REG);

	nor = &mtk_nor->nor;
	nor->dev = mtk_nor->dev;
	nor->priv = mtk_nor;
	spi_nor_set_flash_node(nor, flash_node);

	/* fill the hooks to spi nor */
	nor->read = mtk_nor_read;
	nor->read_reg = mtk_nor_read_reg;
	nor->write = mtk_nor_write;
	nor->write_reg = mtk_nor_write_reg;
	nor->mtd.name = "mtk_nor";
	/* initialized with NULL */
	ret = spi_nor_scan(nor, NULL, &hwcaps);
	if (ret)
		return ret;

	return mtd_device_register(&nor->mtd, NULL, 0);
}

static int mtk_nor_drv_probe(struct platform_device *pdev)
{
	struct device_node *flash_np;
	struct resource *res;
	int ret;
	struct mtk_nor *mtk_nor;

	if (!pdev->dev.of_node) {
		dev_err(&pdev->dev, "No DT found\n");
		return -EINVAL;
	}

	mtk_nor = devm_kzalloc(&pdev->dev, sizeof(*mtk_nor), GFP_KERNEL);
	if (!mtk_nor)
		return -ENOMEM;
	platform_set_drvdata(pdev, mtk_nor);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mtk_nor->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mtk_nor->base))
		return PTR_ERR(mtk_nor->base);

	mtk_nor->spi_clk = devm_clk_get(&pdev->dev, "spi");
	if (IS_ERR(mtk_nor->spi_clk))
		return PTR_ERR(mtk_nor->spi_clk);

	mtk_nor->nor_clk = devm_clk_get(&pdev->dev, "sf");
	if (IS_ERR(mtk_nor->nor_clk))
		return PTR_ERR(mtk_nor->nor_clk);

	mtk_nor->dev = &pdev->dev;

	ret = mtk_nor_enable_clk(mtk_nor);
	if (ret)
		return ret;

	/* only support one attached flash */
	flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
	if (!flash_np) {
		dev_err(&pdev->dev, "no SPI flash device to configure\n");
		ret = -ENODEV;
		goto nor_free;
	}
	ret = mtk_nor_init(mtk_nor, flash_np);

nor_free:
	if (ret)
		mtk_nor_disable_clk(mtk_nor);

	return ret;
}

static int mtk_nor_drv_remove(struct platform_device *pdev)
{
	struct mtk_nor *mtk_nor = platform_get_drvdata(pdev);

	mtk_nor_disable_clk(mtk_nor);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int mtk_nor_suspend(struct device *dev)
{
	struct mtk_nor *mtk_nor = dev_get_drvdata(dev);

	mtk_nor_disable_clk(mtk_nor);

	return 0;
}

static int mtk_nor_resume(struct device *dev)
{
	struct mtk_nor *mtk_nor = dev_get_drvdata(dev);

	return mtk_nor_enable_clk(mtk_nor);
}

static const struct dev_pm_ops mtk_nor_dev_pm_ops = {
	.suspend = mtk_nor_suspend,
	.resume = mtk_nor_resume,
};

#define MTK_NOR_DEV_PM_OPS	(&mtk_nor_dev_pm_ops)
#else
#define MTK_NOR_DEV_PM_OPS	NULL
#endif

static const struct of_device_id mtk_nor_of_ids[] = {
	{ .compatible = "mediatek,mt8173-nor"},
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_nor_of_ids);

static struct platform_driver mtk_nor_driver = {
	.probe = mtk_nor_drv_probe,
	.remove = mtk_nor_drv_remove,
	.driver = {
		.name = "mtk-nor",
		.pm = MTK_NOR_DEV_PM_OPS,
		.of_match_table = mtk_nor_of_ids,
	},
};

module_platform_driver(mtk_nor_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("MediaTek SPI NOR Flash Driver");
Commit	Line	Data
3ce351b5 BC	1	/*
	2	* Copyright (c) 2015 MediaTek Inc.
	3	* Author: Bayi Cheng <bayi.cheng@mediatek.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
	15	#include <linux/clk.h>
	16	#include <linux/delay.h>
	17	#include <linux/device.h>
	18	#include <linux/init.h>
	19	#include <linux/io.h>
	20	#include <linux/iopoll.h>
	21	#include <linux/ioport.h>
	22	#include <linux/math64.h>
	23	#include <linux/module.h>
3ce351b5 BC	24	#include <linux/mutex.h>
	25	#include <linux/of.h>
	26	#include <linux/of_device.h>
3ce351b5 BC	27	#include <linux/platform_device.h>
	28	#include <linux/slab.h>
	29	#include <linux/mtd/mtd.h>
	30	#include <linux/mtd/partitions.h>
	31	#include <linux/mtd/spi-nor.h>
	32
	33	#define MTK_NOR_CMD_REG 0x00
	34	#define MTK_NOR_CNT_REG 0x04
	35	#define MTK_NOR_RDSR_REG 0x08
	36	#define MTK_NOR_RDATA_REG 0x0c
	37	#define MTK_NOR_RADR0_REG 0x10
	38	#define MTK_NOR_RADR1_REG 0x14
	39	#define MTK_NOR_RADR2_REG 0x18
	40	#define MTK_NOR_WDATA_REG 0x1c
	41	#define MTK_NOR_PRGDATA0_REG 0x20
	42	#define MTK_NOR_PRGDATA1_REG 0x24
	43	#define MTK_NOR_PRGDATA2_REG 0x28
	44	#define MTK_NOR_PRGDATA3_REG 0x2c
	45	#define MTK_NOR_PRGDATA4_REG 0x30
	46	#define MTK_NOR_PRGDATA5_REG 0x34
	47	#define MTK_NOR_SHREG0_REG 0x38
	48	#define MTK_NOR_SHREG1_REG 0x3c
	49	#define MTK_NOR_SHREG2_REG 0x40
	50	#define MTK_NOR_SHREG3_REG 0x44
	51	#define MTK_NOR_SHREG4_REG 0x48
	52	#define MTK_NOR_SHREG5_REG 0x4c
	53	#define MTK_NOR_SHREG6_REG 0x50
	54	#define MTK_NOR_SHREG7_REG 0x54
	55	#define MTK_NOR_SHREG8_REG 0x58
	56	#define MTK_NOR_SHREG9_REG 0x5c
	57	#define MTK_NOR_CFG1_REG 0x60
	58	#define MTK_NOR_CFG2_REG 0x64
	59	#define MTK_NOR_CFG3_REG 0x68
	60	#define MTK_NOR_STATUS0_REG 0x70
	61	#define MTK_NOR_STATUS1_REG 0x74
	62	#define MTK_NOR_STATUS2_REG 0x78
	63	#define MTK_NOR_STATUS3_REG 0x7c
	64	#define MTK_NOR_FLHCFG_REG 0x84
	65	#define MTK_NOR_TIME_REG 0x94
	66	#define MTK_NOR_PP_DATA_REG 0x98
	67	#define MTK_NOR_PREBUF_STUS_REG 0x9c
	68	#define MTK_NOR_DELSEL0_REG 0xa0
	69	#define MTK_NOR_DELSEL1_REG 0xa4
	70	#define MTK_NOR_INTRSTUS_REG 0xa8
	71	#define MTK_NOR_INTREN_REG 0xac
	72	#define MTK_NOR_CHKSUM_CTL_REG 0xb8
	73	#define MTK_NOR_CHKSUM_REG 0xbc
	74	#define MTK_NOR_CMD2_REG 0xc0
	75	#define MTK_NOR_WRPROT_REG 0xc4
	76	#define MTK_NOR_RADR3_REG 0xc8
	77	#define MTK_NOR_DUAL_REG 0xcc
	78	#define MTK_NOR_DELSEL2_REG 0xd0
	79	#define MTK_NOR_DELSEL3_REG 0xd4
	80	#define MTK_NOR_DELSEL4_REG 0xd8
	81
	82	/* commands for mtk nor controller */
	83	#define MTK_NOR_READ_CMD 0x0
	84	#define MTK_NOR_RDSR_CMD 0x2
	85	#define MTK_NOR_PRG_CMD 0x4
	86	#define MTK_NOR_WR_CMD 0x10
	87	#define MTK_NOR_PIO_WR_CMD 0x90
	88	#define MTK_NOR_WRSR_CMD 0x20
	89	#define MTK_NOR_PIO_READ_CMD 0x81
	90	#define MTK_NOR_WR_BUF_ENABLE 0x1
91	#define MTK_NOR_WR_BUF_DISABLE 0x0
92	#define MTK_NOR_ENABLE_SF_CMD 0x30
93	#define MTK_NOR_DUAD_ADDR_EN 0x8
94	#define MTK_NOR_QUAD_READ_EN 0x4
95	#define MTK_NOR_DUAL_ADDR_EN 0x2
96	#define MTK_NOR_DUAL_READ_EN 0x1
97	#define MTK_NOR_DUAL_DISABLE 0x0
98	#define MTK_NOR_FAST_READ 0x1
99
100	#define SFLASH_WRBUF_SIZE 128
101
102	/* Can shift up to 48 bits (6 bytes) of TX/RX */
103	#define MTK_NOR_MAX_RX_TX_SHIFT 6
104	/* can shift up to 56 bits (7 bytes) transfer by MTK_NOR_PRG_CMD */
105	#define MTK_NOR_MAX_SHIFT 7
8abe904d GM	106	/* nor controller 4-byte address mode enable bit */
8abe904d GM	107	#define MTK_NOR_4B_ADDR_EN BIT(4)
3ce351b5 BC	108
	109	/* Helpers for accessing the program data / shift data registers */
	110	#define MTK_NOR_PRG_REG(n) (MTK_NOR_PRGDATA0_REG + 4 * (n))
	111	#define MTK_NOR_SHREG(n) (MTK_NOR_SHREG0_REG + 4 * (n))
	112
23bae78e	113	struct mtk_nor {
3ce351b5 BC	114	struct spi_nor nor;
	115	struct device *dev;
	116	void __iomem base; / nor flash base address */
	117	struct clk *spi_clk;
	118	struct clk *nor_clk;
	119	};
	120
23bae78e	121	static void mtk_nor_set_read_mode(struct mtk_nor *mtk_nor)
3ce351b5	122	{
23bae78e	123	struct spi_nor *nor = &mtk_nor->nor;
3ce351b5	124
cfc5604c CP	125	switch (nor->read_proto) {
cfc5604c CP	126	case SNOR_PROTO_1_1_1:
23bae78e	127	writeb(nor->read_opcode, mtk_nor->base +
3ce351b5	128	MTK_NOR_PRGDATA3_REG);
23bae78e	129	writeb(MTK_NOR_FAST_READ, mtk_nor->base +
3ce351b5 BC	130	MTK_NOR_CFG1_REG);
3ce351b5 BC	131	break;
cfc5604c	132	case SNOR_PROTO_1_1_2:
23bae78e	133	writeb(nor->read_opcode, mtk_nor->base +
3ce351b5	134	MTK_NOR_PRGDATA3_REG);
23bae78e	135	writeb(MTK_NOR_DUAL_READ_EN, mtk_nor->base +
3ce351b5 BC	136	MTK_NOR_DUAL_REG);
3ce351b5 BC	137	break;
cfc5604c	138	case SNOR_PROTO_1_1_4:
23bae78e	139	writeb(nor->read_opcode, mtk_nor->base +
3ce351b5	140	MTK_NOR_PRGDATA4_REG);
23bae78e	141	writeb(MTK_NOR_QUAD_READ_EN, mtk_nor->base +
3ce351b5 BC	142	MTK_NOR_DUAL_REG);
	143	break;
	144	default:
23bae78e	145	writeb(MTK_NOR_DUAL_DISABLE, mtk_nor->base +
3ce351b5 BC	146	MTK_NOR_DUAL_REG);
	147	break;
	148	}
	149	}
	150
23bae78e	151	static int mtk_nor_execute_cmd(struct mtk_nor *mtk_nor, u8 cmdval)
3ce351b5 BC	152	{
	153	int reg;
	154	u8 val = cmdval & 0x1f;
	155
23bae78e GM	156	writeb(cmdval, mtk_nor->base + MTK_NOR_CMD_REG);
23bae78e GM	157	return readl_poll_timeout(mtk_nor->base + MTK_NOR_CMD_REG, reg,
3ce351b5 BC	158	!(reg & val), 100, 10000);
	159	}
	160
23bae78e GM	161	static int mtk_nor_do_tx_rx(struct mtk_nor *mtk_nor, u8 op,
23bae78e GM	162	u8 tx, int txlen, u8 rx, int rxlen)
3ce351b5 BC	163	{
	164	int len = 1 + txlen + rxlen;
	165	int i, ret, idx;
	166
	167	if (len > MTK_NOR_MAX_SHIFT)
	168	return -EINVAL;
	169
23bae78e	170	writeb(len * 8, mtk_nor->base + MTK_NOR_CNT_REG);
3ce351b5 BC	171
	172	/* start at PRGDATA5, go down to PRGDATA0 */
	173	idx = MTK_NOR_MAX_RX_TX_SHIFT - 1;
	174
	175	/* opcode */
23bae78e	176	writeb(op, mtk_nor->base + MTK_NOR_PRG_REG(idx));
3ce351b5 BC	177	idx--;
	178
	179	/* program TX data */
	180	for (i = 0; i < txlen; i++, idx--)
23bae78e	181	writeb(tx[i], mtk_nor->base + MTK_NOR_PRG_REG(idx));
3ce351b5 BC	182
	183	/* clear out rest of TX registers */
	184	while (idx >= 0) {
23bae78e	185	writeb(0, mtk_nor->base + MTK_NOR_PRG_REG(idx));
3ce351b5 BC	186	idx--;
	187	}
	188
23bae78e	189	ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PRG_CMD);
3ce351b5 BC	190	if (ret)
	191	return ret;
	192
	193	/* restart at first RX byte */
	194	idx = rxlen - 1;
	195
	196	/* read out RX data */
	197	for (i = 0; i < rxlen; i++, idx--)
23bae78e	198	rx[i] = readb(mtk_nor->base + MTK_NOR_SHREG(idx));
3ce351b5 BC	199
	200	return 0;
	201	}
	202
	203	/* Do a WRSR (Write Status Register) command */
23bae78e	204	static int mtk_nor_wr_sr(struct mtk_nor *mtk_nor, u8 sr)
3ce351b5	205	{
23bae78e GM	206	writeb(sr, mtk_nor->base + MTK_NOR_PRGDATA5_REG);
	207	writeb(8, mtk_nor->base + MTK_NOR_CNT_REG);
	208	return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WRSR_CMD);
3ce351b5 BC	209	}
3ce351b5 BC	210
23bae78e	211	static int mtk_nor_write_buffer_enable(struct mtk_nor *mtk_nor)
3ce351b5 BC	212	{
	213	u8 reg;
	214
	215	/* the bit0 of MTK_NOR_CFG2_REG is pre-fetch buffer
	216	* 0: pre-fetch buffer use for read
	217	* 1: pre-fetch buffer use for page program
	218	*/
23bae78e GM	219	writel(MTK_NOR_WR_BUF_ENABLE, mtk_nor->base + MTK_NOR_CFG2_REG);
23bae78e GM	220	return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg,
3ce351b5 BC	221	0x01 == (reg & 0x01), 100, 10000);
	222	}
	223
23bae78e	224	static int mtk_nor_write_buffer_disable(struct mtk_nor *mtk_nor)
3ce351b5 BC	225	{
	226	u8 reg;
	227
23bae78e GM	228	writel(MTK_NOR_WR_BUF_DISABLE, mtk_nor->base + MTK_NOR_CFG2_REG);
23bae78e GM	229	return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg,
3ce351b5 BC	230	MTK_NOR_WR_BUF_DISABLE == (reg & 0x1), 100,
	231	10000);
	232	}
	233
23bae78e	234	static void mtk_nor_set_addr_width(struct mtk_nor *mtk_nor)
8abe904d GM	235	{
8abe904d GM	236	u8 val;
23bae78e	237	struct spi_nor *nor = &mtk_nor->nor;
8abe904d	238
23bae78e	239	val = readb(mtk_nor->base + MTK_NOR_DUAL_REG);
8abe904d GM	240
	241	switch (nor->addr_width) {
	242	case 3:
	243	val &= ~MTK_NOR_4B_ADDR_EN;
	244	break;
	245	case 4:
	246	val \|= MTK_NOR_4B_ADDR_EN;
	247	break;
	248	default:
23bae78e	249	dev_warn(mtk_nor->dev, "Unexpected address width %u.\n",
8abe904d GM	250	nor->addr_width);
	251	break;
	252	}
	253
23bae78e	254	writeb(val, mtk_nor->base + MTK_NOR_DUAL_REG);
8abe904d GM	255	}
8abe904d GM	256
23bae78e	257	static void mtk_nor_set_addr(struct mtk_nor *mtk_nor, u32 addr)
3ce351b5 BC	258	{
	259	int i;
	260
23bae78e	261	mtk_nor_set_addr_width(mtk_nor);
8abe904d	262
3ce351b5	263	for (i = 0; i < 3; i++) {
23bae78e	264	writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR0_REG + i * 4);
3ce351b5 BC	265	addr >>= 8;
	266	}
	267	/* Last register is non-contiguous */
23bae78e	268	writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR3_REG);
3ce351b5 BC	269	}
3ce351b5 BC	270
23bae78e GM	271	static ssize_t mtk_nor_read(struct spi_nor *nor, loff_t from, size_t length,
23bae78e GM	272	u_char *buffer)
3ce351b5 BC	273	{
	274	int i, ret;
	275	int addr = (int)from;
	276	u8 buf = (u8 )buffer;
23bae78e	277	struct mtk_nor *mtk_nor = nor->priv;
3ce351b5 BC	278
3ce351b5 BC	279	/* set mode for fast read mode ,dual mode or quad mode */
23bae78e GM	280	mtk_nor_set_read_mode(mtk_nor);
23bae78e GM	281	mtk_nor_set_addr(mtk_nor, addr);
3ce351b5	282
2dd087b1	283	for (i = 0; i < length; i++) {
23bae78e	284	ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_READ_CMD);
3ce351b5 BC	285	if (ret < 0)
3ce351b5 BC	286	return ret;
23bae78e	287	buf[i] = readb(mtk_nor->base + MTK_NOR_RDATA_REG);
3ce351b5	288	}
78b400fd	289	return length;
3ce351b5 BC	290	}
3ce351b5 BC	291
23bae78e GM	292	static int mtk_nor_write_single_byte(struct mtk_nor *mtk_nor,
23bae78e GM	293	int addr, int length, u8 *data)
3ce351b5 BC	294	{
	295	int i, ret;
	296
23bae78e	297	mtk_nor_set_addr(mtk_nor, addr);
3ce351b5 BC	298
3ce351b5 BC	299	for (i = 0; i < length; i++) {
23bae78e GM	300	writeb(*data++, mtk_nor->base + MTK_NOR_WDATA_REG);
23bae78e GM	301	ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_WR_CMD);
3ce351b5 BC	302	if (ret < 0)
3ce351b5 BC	303	return ret;
3ce351b5 BC	304	}
	305	return 0;
	306	}
	307
23bae78e GM	308	static int mtk_nor_write_buffer(struct mtk_nor *mtk_nor, int addr,
23bae78e GM	309	const u8 *buf)
3ce351b5 BC	310	{
	311	int i, bufidx, data;
	312
23bae78e	313	mtk_nor_set_addr(mtk_nor, addr);
3ce351b5 BC	314
	315	bufidx = 0;
	316	for (i = 0; i < SFLASH_WRBUF_SIZE; i += 4) {
	317	data = buf[bufidx + 3]<<24 \| buf[bufidx + 2]<<16 \|
	318	buf[bufidx + 1]<<8 \| buf[bufidx];
	319	bufidx += 4;
23bae78e	320	writel(data, mtk_nor->base + MTK_NOR_PP_DATA_REG);
3ce351b5	321	}
23bae78e	322	return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WR_CMD);
3ce351b5 BC	323	}
3ce351b5 BC	324
23bae78e GM	325	static ssize_t mtk_nor_write(struct spi_nor *nor, loff_t to, size_t len,
23bae78e GM	326	const u_char *buf)
3ce351b5 BC	327	{
3ce351b5 BC	328	int ret;
23bae78e	329	struct mtk_nor *mtk_nor = nor->priv;
78b400fd	330	size_t i;
3ce351b5	331
23bae78e	332	ret = mtk_nor_write_buffer_enable(mtk_nor);
59451e12	333	if (ret < 0) {
23bae78e	334	dev_warn(mtk_nor->dev, "write buffer enable failed!\n");
59451e12 MS	335	return ret;
59451e12 MS	336	}
3ce351b5	337
78b400fd	338	for (i = 0; i + SFLASH_WRBUF_SIZE <= len; i += SFLASH_WRBUF_SIZE) {
23bae78e	339	ret = mtk_nor_write_buffer(mtk_nor, to, buf);
59451e12	340	if (ret < 0) {
23bae78e	341	dev_err(mtk_nor->dev, "write buffer failed!\n");
59451e12 MS	342	return ret;
59451e12 MS	343	}
3ce351b5 BC	344	to += SFLASH_WRBUF_SIZE;
3ce351b5 BC	345	buf += SFLASH_WRBUF_SIZE;
3ce351b5	346	}
23bae78e	347	ret = mtk_nor_write_buffer_disable(mtk_nor);
59451e12	348	if (ret < 0) {
23bae78e	349	dev_warn(mtk_nor->dev, "write buffer disable failed!\n");
59451e12 MS	350	return ret;
59451e12 MS	351	}
3ce351b5	352
78b400fd	353	if (i < len) {
23bae78e GM	354	ret = mtk_nor_write_single_byte(mtk_nor, to,
23bae78e GM	355	(int)(len - i), (u8 *)buf);
59451e12	356	if (ret < 0) {
23bae78e	357	dev_err(mtk_nor->dev, "write single byte failed!\n");
59451e12 MS	358	return ret;
59451e12 MS	359	}
3ce351b5	360	}
59451e12	361
78b400fd	362	return len;
3ce351b5 BC	363	}
3ce351b5 BC	364
23bae78e	365	static int mtk_nor_read_reg(struct spi_nor nor, u8 opcode, u8 buf, int len)
3ce351b5 BC	366	{
3ce351b5 BC	367	int ret;
23bae78e	368	struct mtk_nor *mtk_nor = nor->priv;
3ce351b5 BC	369
	370	switch (opcode) {
	371	case SPINOR_OP_RDSR:
23bae78e	372	ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_RDSR_CMD);
3ce351b5 BC	373	if (ret < 0)
	374	return ret;
	375	if (len == 1)
23bae78e	376	*buf = readb(mtk_nor->base + MTK_NOR_RDSR_REG);
3ce351b5	377	else
23bae78e	378	dev_err(mtk_nor->dev, "len should be 1 for read status!\n");
3ce351b5 BC	379	break;
3ce351b5 BC	380	default:
23bae78e	381	ret = mtk_nor_do_tx_rx(mtk_nor, opcode, NULL, 0, buf, len);
3ce351b5 BC	382	break;
	383	}
	384	return ret;
	385	}
	386
23bae78e GM	387	static int mtk_nor_write_reg(struct spi_nor nor, u8 opcode, u8 buf,
23bae78e GM	388	int len)
3ce351b5 BC	389	{
3ce351b5 BC	390	int ret;
23bae78e	391	struct mtk_nor *mtk_nor = nor->priv;
3ce351b5 BC	392
	393	switch (opcode) {
	394	case SPINOR_OP_WRSR:
	395	/* We only handle 1 byte */
23bae78e	396	ret = mtk_nor_wr_sr(mtk_nor, *buf);
3ce351b5 BC	397	break;
3ce351b5 BC	398	default:
23bae78e	399	ret = mtk_nor_do_tx_rx(mtk_nor, opcode, buf, len, NULL, 0);
3ce351b5	400	if (ret)
23bae78e	401	dev_warn(mtk_nor->dev, "write reg failure!\n");
3ce351b5 BC	402	break;
	403	}
	404	return ret;
	405	}
	406
23bae78e	407	static void mtk_nor_disable_clk(struct mtk_nor *mtk_nor)
2ea68b75	408	{
23bae78e GM	409	clk_disable_unprepare(mtk_nor->spi_clk);
23bae78e GM	410	clk_disable_unprepare(mtk_nor->nor_clk);
2ea68b75 GM	411	}
2ea68b75 GM	412
23bae78e	413	static int mtk_nor_enable_clk(struct mtk_nor *mtk_nor)
2ea68b75 GM	414	{
	415	int ret;
	416
23bae78e	417	ret = clk_prepare_enable(mtk_nor->spi_clk);
2ea68b75 GM	418	if (ret)
	419	return ret;
	420
23bae78e	421	ret = clk_prepare_enable(mtk_nor->nor_clk);
2ea68b75	422	if (ret) {
23bae78e	423	clk_disable_unprepare(mtk_nor->spi_clk);
2ea68b75 GM	424	return ret;
	425	}
	426
	427	return 0;
	428	}
	429
23bae78e	430	static int mtk_nor_init(struct mtk_nor *mtk_nor,
92752d99	431	struct device_node *flash_node)
3ce351b5	432	{
cfc5604c CP	433	const struct spi_nor_hwcaps hwcaps = {
	434	.mask = SNOR_HWCAPS_READ_FAST \|
	435	SNOR_HWCAPS_READ_1_1_2 \|
	436	SNOR_HWCAPS_PP,
	437	};
3ce351b5 BC	438	int ret;
	439	struct spi_nor *nor;
	440
	441	/* initialize controller to accept commands */
23bae78e	442	writel(MTK_NOR_ENABLE_SF_CMD, mtk_nor->base + MTK_NOR_WRPROT_REG);
3ce351b5	443
23bae78e GM	444	nor = &mtk_nor->nor;
	445	nor->dev = mtk_nor->dev;
	446	nor->priv = mtk_nor;
3ce351b5 BC	447	spi_nor_set_flash_node(nor, flash_node);
	448
	449	/* fill the hooks to spi nor */
23bae78e GM	450	nor->read = mtk_nor_read;
	451	nor->read_reg = mtk_nor_read_reg;
	452	nor->write = mtk_nor_write;
	453	nor->write_reg = mtk_nor_write_reg;
3ce351b5 BC	454	nor->mtd.name = "mtk_nor";
3ce351b5 BC	455	/* initialized with NULL */
cfc5604c	456	ret = spi_nor_scan(nor, NULL, &hwcaps);
3ce351b5 BC	457	if (ret)
	458	return ret;
	459
	460	return mtd_device_register(&nor->mtd, NULL, 0);
	461	}
	462
	463	static int mtk_nor_drv_probe(struct platform_device *pdev)
	464	{
	465	struct device_node *flash_np;
	466	struct resource *res;
	467	int ret;
23bae78e	468	struct mtk_nor *mtk_nor;
3ce351b5 BC	469
	470	if (!pdev->dev.of_node) {
	471	dev_err(&pdev->dev, "No DT found\n");
	472	return -EINVAL;
	473	}
	474
23bae78e GM	475	mtk_nor = devm_kzalloc(&pdev->dev, sizeof(*mtk_nor), GFP_KERNEL);
23bae78e GM	476	if (!mtk_nor)
3ce351b5	477	return -ENOMEM;
23bae78e	478	platform_set_drvdata(pdev, mtk_nor);
3ce351b5 BC	479
3ce351b5 BC	480	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
23bae78e GM	481	mtk_nor->base = devm_ioremap_resource(&pdev->dev, res);
	482	if (IS_ERR(mtk_nor->base))
	483	return PTR_ERR(mtk_nor->base);
3ce351b5	484
23bae78e GM	485	mtk_nor->spi_clk = devm_clk_get(&pdev->dev, "spi");
	486	if (IS_ERR(mtk_nor->spi_clk))
	487	return PTR_ERR(mtk_nor->spi_clk);
3ce351b5	488
23bae78e GM	489	mtk_nor->nor_clk = devm_clk_get(&pdev->dev, "sf");
	490	if (IS_ERR(mtk_nor->nor_clk))
	491	return PTR_ERR(mtk_nor->nor_clk);
3ce351b5	492
23bae78e	493	mtk_nor->dev = &pdev->dev;
2ea68b75	494
23bae78e	495	ret = mtk_nor_enable_clk(mtk_nor);
3ce351b5 BC	496	if (ret)
	497	return ret;
	498
3ce351b5 BC	499	/* only support one attached flash */
	500	flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
	501	if (!flash_np) {
	502	dev_err(&pdev->dev, "no SPI flash device to configure\n");
	503	ret = -ENODEV;
	504	goto nor_free;
	505	}
23bae78e	506	ret = mtk_nor_init(mtk_nor, flash_np);
3ce351b5 BC	507
3ce351b5 BC	508	nor_free:
2ea68b75	509	if (ret)
23bae78e	510	mtk_nor_disable_clk(mtk_nor);
2ea68b75	511
3ce351b5 BC	512	return ret;
	513	}
	514
	515	static int mtk_nor_drv_remove(struct platform_device *pdev)
	516	{
23bae78e	517	struct mtk_nor *mtk_nor = platform_get_drvdata(pdev);
3ce351b5	518
23bae78e	519	mtk_nor_disable_clk(mtk_nor);
2ea68b75 GM	520
	521	return 0;
	522	}
	523
	524	#ifdef CONFIG_PM_SLEEP
	525	static int mtk_nor_suspend(struct device *dev)
	526	{
23bae78e	527	struct mtk_nor *mtk_nor = dev_get_drvdata(dev);
2ea68b75	528
23bae78e	529	mtk_nor_disable_clk(mtk_nor);
2ea68b75	530
3ce351b5 BC	531	return 0;
	532	}
	533
2ea68b75 GM	534	static int mtk_nor_resume(struct device *dev)
2ea68b75 GM	535	{
23bae78e	536	struct mtk_nor *mtk_nor = dev_get_drvdata(dev);
2ea68b75	537
23bae78e	538	return mtk_nor_enable_clk(mtk_nor);
2ea68b75 GM	539	}
	540
	541	static const struct dev_pm_ops mtk_nor_dev_pm_ops = {
	542	.suspend = mtk_nor_suspend,
	543	.resume = mtk_nor_resume,
	544	};
	545
	546	#define MTK_NOR_DEV_PM_OPS (&mtk_nor_dev_pm_ops)
	547	#else
	548	#define MTK_NOR_DEV_PM_OPS NULL
	549	#endif
	550
3ce351b5 BC	551	static const struct of_device_id mtk_nor_of_ids[] = {
	552	{ .compatible = "mediatek,mt8173-nor"},
	553	{ /* sentinel */ }
	554	};
	555	MODULE_DEVICE_TABLE(of, mtk_nor_of_ids);
	556
	557	static struct platform_driver mtk_nor_driver = {
	558	.probe = mtk_nor_drv_probe,
	559	.remove = mtk_nor_drv_remove,
	560	.driver = {
	561	.name = "mtk-nor",
2ea68b75	562	.pm = MTK_NOR_DEV_PM_OPS,
3ce351b5 BC	563	.of_match_table = mtk_nor_of_ids,
	564	},
	565	};
	566
	567	module_platform_driver(mtk_nor_driver);
	568	MODULE_LICENSE("GPL v2");
	569	MODULE_DESCRIPTION("MediaTek SPI NOR Flash Driver");