[mirror_ubuntu-artful-kernel.git] / drivers / mtd / spi-nor / nxp-spifi.c

/*
 * SPI-NOR driver for NXP SPI Flash Interface (SPIFI)
 *
 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
 *
 * Based on Freescale QuadSPI driver:
 * Copyright (C) 2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/spi-nor.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>

/* NXP SPIFI registers, bits and macros */
#define SPIFI_CTRL				0x000
#define  SPIFI_CTRL_TIMEOUT(timeout)		(timeout)
#define  SPIFI_CTRL_CSHIGH(cshigh)		((cshigh) << 16)
#define  SPIFI_CTRL_MODE3			BIT(23)
#define  SPIFI_CTRL_DUAL			BIT(28)
#define  SPIFI_CTRL_FBCLK			BIT(30)
#define SPIFI_CMD				0x004
#define  SPIFI_CMD_DATALEN(dlen)		((dlen) & 0x3fff)
#define  SPIFI_CMD_DOUT				BIT(15)
#define  SPIFI_CMD_INTLEN(ilen)			((ilen) << 16)
#define  SPIFI_CMD_FIELDFORM(field)		((field) << 19)
#define  SPIFI_CMD_FIELDFORM_ALL_SERIAL		SPIFI_CMD_FIELDFORM(0x0)
#define  SPIFI_CMD_FIELDFORM_QUAD_DUAL_DATA	SPIFI_CMD_FIELDFORM(0x1)
#define  SPIFI_CMD_FRAMEFORM(frame)		((frame) << 21)
#define  SPIFI_CMD_FRAMEFORM_OPCODE_ONLY	SPIFI_CMD_FRAMEFORM(0x1)
#define  SPIFI_CMD_OPCODE(op)			((op) << 24)
#define SPIFI_ADDR				0x008
#define SPIFI_IDATA				0x00c
#define SPIFI_CLIMIT				0x010
#define SPIFI_DATA				0x014
#define SPIFI_MCMD				0x018
#define SPIFI_STAT				0x01c
#define  SPIFI_STAT_MCINIT			BIT(0)
#define  SPIFI_STAT_CMD				BIT(1)
#define  SPIFI_STAT_RESET			BIT(4)

#define SPI_NOR_MAX_ID_LEN	6

struct nxp_spifi {
	struct device *dev;
	struct clk *clk_spifi;
	struct clk *clk_reg;
	void __iomem *io_base;
	void __iomem *flash_base;
	struct spi_nor nor;
	bool memory_mode;
	u32 mcmd;
};

static int nxp_spifi_wait_for_cmd(struct nxp_spifi *spifi)
{
	u8 stat;
	int ret;

	ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
				 !(stat & SPIFI_STAT_CMD), 10, 30);
	if (ret)
		dev_warn(spifi->dev, "command timed out\n");

	return ret;
}

static int nxp_spifi_reset(struct nxp_spifi *spifi)
{
	u8 stat;
	int ret;

	writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT);
	ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
				 !(stat & SPIFI_STAT_RESET), 10, 30);
	if (ret)
		dev_warn(spifi->dev, "state reset timed out\n");

	return ret;
}

static int nxp_spifi_set_memory_mode_off(struct nxp_spifi *spifi)
{
	int ret;

	if (!spifi->memory_mode)
		return 0;

	ret = nxp_spifi_reset(spifi);
	if (ret)
		dev_err(spifi->dev, "unable to enter command mode\n");
	else
		spifi->memory_mode = false;

	return ret;
}

static int nxp_spifi_set_memory_mode_on(struct nxp_spifi *spifi)
{
	u8 stat;
	int ret;

	if (spifi->memory_mode)
		return 0;

	writel(spifi->mcmd, spifi->io_base + SPIFI_MCMD);
	ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
				 stat & SPIFI_STAT_MCINIT, 10, 30);
	if (ret)
		dev_err(spifi->dev, "unable to enter memory mode\n");
	else
		spifi->memory_mode = true;

	return ret;
}

static int nxp_spifi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
{
	struct nxp_spifi *spifi = nor->priv;
	u32 cmd;
	int ret;

	ret = nxp_spifi_set_memory_mode_off(spifi);
	if (ret)
		return ret;

	cmd = SPIFI_CMD_DATALEN(len) |
	      SPIFI_CMD_OPCODE(opcode) |
	      SPIFI_CMD_FIELDFORM_ALL_SERIAL |
	      SPIFI_CMD_FRAMEFORM_OPCODE_ONLY;
	writel(cmd, spifi->io_base + SPIFI_CMD);

	while (len--)
		*buf++ = readb(spifi->io_base + SPIFI_DATA);

	return nxp_spifi_wait_for_cmd(spifi);
}

static int nxp_spifi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
{
	struct nxp_spifi *spifi = nor->priv;
	u32 cmd;
	int ret;

	ret = nxp_spifi_set_memory_mode_off(spifi);
	if (ret)
		return ret;

	cmd = SPIFI_CMD_DOUT |
	      SPIFI_CMD_DATALEN(len) |
	      SPIFI_CMD_OPCODE(opcode) |
	      SPIFI_CMD_FIELDFORM_ALL_SERIAL |
	      SPIFI_CMD_FRAMEFORM_OPCODE_ONLY;
	writel(cmd, spifi->io_base + SPIFI_CMD);

	while (len--)
		writeb(*buf++, spifi->io_base + SPIFI_DATA);

	return nxp_spifi_wait_for_cmd(spifi);
}

static ssize_t nxp_spifi_read(struct spi_nor *nor, loff_t from, size_t len,
			      u_char *buf)
{
	struct nxp_spifi *spifi = nor->priv;
	int ret;

	ret = nxp_spifi_set_memory_mode_on(spifi);
	if (ret)
		return ret;

	memcpy_fromio(buf, spifi->flash_base + from, len);

	return len;
}

static ssize_t nxp_spifi_write(struct spi_nor *nor, loff_t to, size_t len,
			       const u_char *buf)
{
	struct nxp_spifi *spifi = nor->priv;
	u32 cmd;
	int ret;
	size_t i;

	ret = nxp_spifi_set_memory_mode_off(spifi);
	if (ret)
		return ret;

	writel(to, spifi->io_base + SPIFI_ADDR);

	cmd = SPIFI_CMD_DOUT |
	      SPIFI_CMD_DATALEN(len) |
	      SPIFI_CMD_FIELDFORM_ALL_SERIAL |
	      SPIFI_CMD_OPCODE(nor->program_opcode) |
	      SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);
	writel(cmd, spifi->io_base + SPIFI_CMD);

	for (i = 0; i < len; i++)
		writeb(buf[i], spifi->io_base + SPIFI_DATA);

	ret = nxp_spifi_wait_for_cmd(spifi);
	if (ret)
		return ret;

	return len;
}

static int nxp_spifi_erase(struct spi_nor *nor, loff_t offs)
{
	struct nxp_spifi *spifi = nor->priv;
	u32 cmd;
	int ret;

	ret = nxp_spifi_set_memory_mode_off(spifi);
	if (ret)
		return ret;

	writel(offs, spifi->io_base + SPIFI_ADDR);

	cmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL |
	      SPIFI_CMD_OPCODE(nor->erase_opcode) |
	      SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);
	writel(cmd, spifi->io_base + SPIFI_CMD);

	return nxp_spifi_wait_for_cmd(spifi);
}

static int nxp_spifi_setup_memory_cmd(struct nxp_spifi *spifi)
{
	switch (spifi->nor.read_proto) {
	case SNOR_PROTO_1_1_1:
		spifi->mcmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL;
		break;
	case SNOR_PROTO_1_1_2:
	case SNOR_PROTO_1_1_4:
		spifi->mcmd = SPIFI_CMD_FIELDFORM_QUAD_DUAL_DATA;
		break;
	default:
		dev_err(spifi->dev, "unsupported SPI read mode\n");
		return -EINVAL;
	}

	/* Memory mode supports address length between 1 and 4 */
	if (spifi->nor.addr_width < 1 || spifi->nor.addr_width > 4)
		return -EINVAL;

	spifi->mcmd |= SPIFI_CMD_OPCODE(spifi->nor.read_opcode) |
		       SPIFI_CMD_INTLEN(spifi->nor.read_dummy / 8) |
		       SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);

	return 0;
}

static void nxp_spifi_dummy_id_read(struct spi_nor *nor)
{
	u8 id[SPI_NOR_MAX_ID_LEN];
	nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
}

static int nxp_spifi_setup_flash(struct nxp_spifi *spifi,
				 struct device_node *np)
{
	struct spi_nor_hwcaps hwcaps = {
		.mask = SNOR_HWCAPS_READ |
			SNOR_HWCAPS_READ_FAST |
			SNOR_HWCAPS_PP,
	};
	u32 ctrl, property;
	u16 mode = 0;
	int ret;

	if (!of_property_read_u32(np, "spi-rx-bus-width", &property)) {
		switch (property) {
		case 1:
			break;
		case 2:
			mode |= SPI_RX_DUAL;
			break;
		case 4:
			mode |= SPI_RX_QUAD;
			break;
		default:
			dev_err(spifi->dev, "unsupported rx-bus-width\n");
			return -EINVAL;
		}
	}

	if (of_find_property(np, "spi-cpha", NULL))
		mode |= SPI_CPHA;

	if (of_find_property(np, "spi-cpol", NULL))
		mode |= SPI_CPOL;

	/* Setup control register defaults */
	ctrl = SPIFI_CTRL_TIMEOUT(1000) |
	       SPIFI_CTRL_CSHIGH(15) |
	       SPIFI_CTRL_FBCLK;

	if (mode & SPI_RX_DUAL) {
		ctrl |= SPIFI_CTRL_DUAL;
		hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
	} else if (mode & SPI_RX_QUAD) {
		ctrl &= ~SPIFI_CTRL_DUAL;
		hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
	} else {
		ctrl |= SPIFI_CTRL_DUAL;
	}

	switch (mode & (SPI_CPHA | SPI_CPOL)) {
	case SPI_MODE_0:
		ctrl &= ~SPIFI_CTRL_MODE3;
		break;
	case SPI_MODE_3:
		ctrl |= SPIFI_CTRL_MODE3;
		break;
	default:
		dev_err(spifi->dev, "only mode 0 and 3 supported\n");
		return -EINVAL;
	}

	writel(ctrl, spifi->io_base + SPIFI_CTRL);

	spifi->nor.dev   = spifi->dev;
	spi_nor_set_flash_node(&spifi->nor, np);
	spifi->nor.priv  = spifi;
	spifi->nor.read  = nxp_spifi_read;
	spifi->nor.write = nxp_spifi_write;
	spifi->nor.erase = nxp_spifi_erase;
	spifi->nor.read_reg  = nxp_spifi_read_reg;
	spifi->nor.write_reg = nxp_spifi_write_reg;

	/*
	 * The first read on a hard reset isn't reliable so do a
	 * dummy read of the id before calling spi_nor_scan().
	 * The reason for this problem is unknown.
	 *
	 * The official NXP spifilib uses more or less the same
	 * workaround that is applied here by reading the device
	 * id multiple times.
	 */
	nxp_spifi_dummy_id_read(&spifi->nor);

	ret = spi_nor_scan(&spifi->nor, NULL, &hwcaps);
	if (ret) {
		dev_err(spifi->dev, "device scan failed\n");
		return ret;
	}

	ret = nxp_spifi_setup_memory_cmd(spifi);
	if (ret) {
		dev_err(spifi->dev, "memory command setup failed\n");
		return ret;
	}

	ret = mtd_device_register(&spifi->nor.mtd, NULL, 0);
	if (ret) {
		dev_err(spifi->dev, "mtd device parse failed\n");
		return ret;
	}

	return 0;
}

static int nxp_spifi_probe(struct platform_device *pdev)
{
	struct device_node *flash_np;
	struct nxp_spifi *spifi;
	struct resource *res;
	int ret;

	spifi = devm_kzalloc(&pdev->dev, sizeof(*spifi), GFP_KERNEL);
	if (!spifi)
		return -ENOMEM;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spifi");
	spifi->io_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(spifi->io_base))
		return PTR_ERR(spifi->io_base);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash");
	spifi->flash_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(spifi->flash_base))
		return PTR_ERR(spifi->flash_base);

	spifi->clk_spifi = devm_clk_get(&pdev->dev, "spifi");
	if (IS_ERR(spifi->clk_spifi)) {
		dev_err(&pdev->dev, "spifi clock not found\n");
		return PTR_ERR(spifi->clk_spifi);
	}

	spifi->clk_reg = devm_clk_get(&pdev->dev, "reg");
	if (IS_ERR(spifi->clk_reg)) {
		dev_err(&pdev->dev, "reg clock not found\n");
		return PTR_ERR(spifi->clk_reg);
	}

	ret = clk_prepare_enable(spifi->clk_reg);
	if (ret) {
		dev_err(&pdev->dev, "unable to enable reg clock\n");
		return ret;
	}

	ret = clk_prepare_enable(spifi->clk_spifi);
	if (ret) {
		dev_err(&pdev->dev, "unable to enable spifi clock\n");
		goto dis_clk_reg;
	}

	spifi->dev = &pdev->dev;
	platform_set_drvdata(pdev, spifi);

	/* Initialize and reset device */
	nxp_spifi_reset(spifi);
	writel(0, spifi->io_base + SPIFI_IDATA);
	writel(0, spifi->io_base + SPIFI_MCMD);
	nxp_spifi_reset(spifi);

	flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
	if (!flash_np) {
		dev_err(&pdev->dev, "no SPI flash device to configure\n");
		ret = -ENODEV;
		goto dis_clks;
	}

	ret = nxp_spifi_setup_flash(spifi, flash_np);
	if (ret) {
		dev_err(&pdev->dev, "unable to setup flash chip\n");
		goto dis_clks;
	}

	return 0;

dis_clks:
	clk_disable_unprepare(spifi->clk_spifi);
dis_clk_reg:
	clk_disable_unprepare(spifi->clk_reg);
	return ret;
}

static int nxp_spifi_remove(struct platform_device *pdev)
{
	struct nxp_spifi *spifi = platform_get_drvdata(pdev);

	mtd_device_unregister(&spifi->nor.mtd);
	clk_disable_unprepare(spifi->clk_spifi);
	clk_disable_unprepare(spifi->clk_reg);

	return 0;
}

static const struct of_device_id nxp_spifi_match[] = {
	{.compatible = "nxp,lpc1773-spifi"},
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, nxp_spifi_match);

static struct platform_driver nxp_spifi_driver = {
	.probe	= nxp_spifi_probe,
	.remove	= nxp_spifi_remove,
	.driver	= {
		.name = "nxp-spifi",
		.of_match_table = nxp_spifi_match,
	},
};
module_platform_driver(nxp_spifi_driver);

MODULE_DESCRIPTION("NXP SPI Flash Interface driver");
MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
f617b958 JE	1	/*
	2	* SPI-NOR driver for NXP SPI Flash Interface (SPIFI)
	3	*
	4	* Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
	5	*
	6	* Based on Freescale QuadSPI driver:
	7	* Copyright (C) 2013 Freescale Semiconductor, Inc.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	*/
	14
	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/io.h>
	18	#include <linux/iopoll.h>
	19	#include <linux/module.h>
	20	#include <linux/mtd/mtd.h>
	21	#include <linux/mtd/partitions.h>
	22	#include <linux/mtd/spi-nor.h>
	23	#include <linux/of.h>
	24	#include <linux/of_device.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/spi/spi.h>
	27
	28	/* NXP SPIFI registers, bits and macros */
	29	#define SPIFI_CTRL 0x000
	30	#define SPIFI_CTRL_TIMEOUT(timeout) (timeout)
	31	#define SPIFI_CTRL_CSHIGH(cshigh) ((cshigh) << 16)
	32	#define SPIFI_CTRL_MODE3 BIT(23)
	33	#define SPIFI_CTRL_DUAL BIT(28)
	34	#define SPIFI_CTRL_FBCLK BIT(30)
	35	#define SPIFI_CMD 0x004
	36	#define SPIFI_CMD_DATALEN(dlen) ((dlen) & 0x3fff)
	37	#define SPIFI_CMD_DOUT BIT(15)
	38	#define SPIFI_CMD_INTLEN(ilen) ((ilen) << 16)
	39	#define SPIFI_CMD_FIELDFORM(field) ((field) << 19)
	40	#define SPIFI_CMD_FIELDFORM_ALL_SERIAL SPIFI_CMD_FIELDFORM(0x0)
	41	#define SPIFI_CMD_FIELDFORM_QUAD_DUAL_DATA SPIFI_CMD_FIELDFORM(0x1)
	42	#define SPIFI_CMD_FRAMEFORM(frame) ((frame) << 21)
	43	#define SPIFI_CMD_FRAMEFORM_OPCODE_ONLY SPIFI_CMD_FRAMEFORM(0x1)
	44	#define SPIFI_CMD_OPCODE(op) ((op) << 24)
	45	#define SPIFI_ADDR 0x008
	46	#define SPIFI_IDATA 0x00c
	47	#define SPIFI_CLIMIT 0x010
	48	#define SPIFI_DATA 0x014
	49	#define SPIFI_MCMD 0x018
	50	#define SPIFI_STAT 0x01c
	51	#define SPIFI_STAT_MCINIT BIT(0)
	52	#define SPIFI_STAT_CMD BIT(1)
	53	#define SPIFI_STAT_RESET BIT(4)
	54
	55	#define SPI_NOR_MAX_ID_LEN 6
	56
	57	struct nxp_spifi {
	58	struct device *dev;
	59	struct clk *clk_spifi;
	60	struct clk *clk_reg;
	61	void __iomem *io_base;
	62	void __iomem *flash_base;
f617b958 JE	63	struct spi_nor nor;
	64	bool memory_mode;
	65	u32 mcmd;
	66	};
	67
	68	static int nxp_spifi_wait_for_cmd(struct nxp_spifi *spifi)
	69	{
	70	u8 stat;
	71	int ret;
	72
	73	ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
	74	!(stat & SPIFI_STAT_CMD), 10, 30);
	75	if (ret)
	76	dev_warn(spifi->dev, "command timed out\n");
	77
	78	return ret;
	79	}
	80
	81	static int nxp_spifi_reset(struct nxp_spifi *spifi)
	82	{
	83	u8 stat;
	84	int ret;
	85
	86	writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT);
	87	ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
	88	!(stat & SPIFI_STAT_RESET), 10, 30);
	89	if (ret)
	90	dev_warn(spifi->dev, "state reset timed out\n");
	91
	92	return ret;
	93	}
	94
	95	static int nxp_spifi_set_memory_mode_off(struct nxp_spifi *spifi)
	96	{
	97	int ret;
	98
	99	if (!spifi->memory_mode)
	100	return 0;
	101
	102	ret = nxp_spifi_reset(spifi);
	103	if (ret)
	104	dev_err(spifi->dev, "unable to enter command mode\n");
	105	else
	106	spifi->memory_mode = false;
	107
	108	return ret;
	109	}
	110
	111	static int nxp_spifi_set_memory_mode_on(struct nxp_spifi *spifi)
	112	{
	113	u8 stat;
	114	int ret;
	115
	116	if (spifi->memory_mode)
	117	return 0;
	118
	119	writel(spifi->mcmd, spifi->io_base + SPIFI_MCMD);
	120	ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
	121	stat & SPIFI_STAT_MCINIT, 10, 30);
	122	if (ret)
	123	dev_err(spifi->dev, "unable to enter memory mode\n");
	124	else
	125	spifi->memory_mode = true;
	126
127	return ret;
128	}
129
130	static int nxp_spifi_read_reg(struct spi_nor nor, u8 opcode, u8 buf, int len)
131	{
132	struct nxp_spifi *spifi = nor->priv;
133	u32 cmd;
134	int ret;
135
136	ret = nxp_spifi_set_memory_mode_off(spifi);
137	if (ret)
138	return ret;
139
140	cmd = SPIFI_CMD_DATALEN(len) \|
141	SPIFI_CMD_OPCODE(opcode) \|
142	SPIFI_CMD_FIELDFORM_ALL_SERIAL \|
143	SPIFI_CMD_FRAMEFORM_OPCODE_ONLY;
144	writel(cmd, spifi->io_base + SPIFI_CMD);
145
146	while (len--)
147	*buf++ = readb(spifi->io_base + SPIFI_DATA);
148
149	return nxp_spifi_wait_for_cmd(spifi);
150	}
151
f9f3ce83	152	static int nxp_spifi_write_reg(struct spi_nor nor, u8 opcode, u8 buf, int len)
f617b958 JE	153	{
	154	struct nxp_spifi *spifi = nor->priv;
	155	u32 cmd;
	156	int ret;
	157
	158	ret = nxp_spifi_set_memory_mode_off(spifi);
	159	if (ret)
	160	return ret;
	161
	162	cmd = SPIFI_CMD_DOUT \|
	163	SPIFI_CMD_DATALEN(len) \|
	164	SPIFI_CMD_OPCODE(opcode) \|
	165	SPIFI_CMD_FIELDFORM_ALL_SERIAL \|
	166	SPIFI_CMD_FRAMEFORM_OPCODE_ONLY;
	167	writel(cmd, spifi->io_base + SPIFI_CMD);
	168
	169	while (len--)
	170	writeb(*buf++, spifi->io_base + SPIFI_DATA);
	171
	172	return nxp_spifi_wait_for_cmd(spifi);
	173	}
	174
59451e12	175	static ssize_t nxp_spifi_read(struct spi_nor *nor, loff_t from, size_t len,
2dd087b1	176	u_char *buf)
f617b958 JE	177	{
	178	struct nxp_spifi *spifi = nor->priv;
	179	int ret;
	180
	181	ret = nxp_spifi_set_memory_mode_on(spifi);
	182	if (ret)
	183	return ret;
	184
	185	memcpy_fromio(buf, spifi->flash_base + from, len);
f617b958	186
bc418cd2	187	return len;
f617b958 JE	188	}
f617b958 JE	189
59451e12	190	static ssize_t nxp_spifi_write(struct spi_nor *nor, loff_t to, size_t len,
2dd087b1	191	const u_char *buf)
f617b958 JE	192	{
	193	struct nxp_spifi *spifi = nor->priv;
	194	u32 cmd;
	195	int ret;
bc418cd2	196	size_t i;
f617b958 JE	197
	198	ret = nxp_spifi_set_memory_mode_off(spifi);
	199	if (ret)
59451e12	200	return ret;
f617b958 JE	201
f617b958 JE	202	writel(to, spifi->io_base + SPIFI_ADDR);
f617b958 JE	203
	204	cmd = SPIFI_CMD_DOUT \|
	205	SPIFI_CMD_DATALEN(len) \|
	206	SPIFI_CMD_FIELDFORM_ALL_SERIAL \|
	207	SPIFI_CMD_OPCODE(nor->program_opcode) \|
	208	SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);
	209	writel(cmd, spifi->io_base + SPIFI_CMD);
	210
bc418cd2 BN	211	for (i = 0; i < len; i++)
bc418cd2 BN	212	writeb(buf[i], spifi->io_base + SPIFI_DATA);
f617b958	213
bc418cd2 BN	214	ret = nxp_spifi_wait_for_cmd(spifi);
	215	if (ret)
	216	return ret;
	217
	218	return len;
f617b958 JE	219	}
	220
	221	static int nxp_spifi_erase(struct spi_nor *nor, loff_t offs)
	222	{
	223	struct nxp_spifi *spifi = nor->priv;
	224	u32 cmd;
	225	int ret;
	226
	227	ret = nxp_spifi_set_memory_mode_off(spifi);
	228	if (ret)
	229	return ret;
	230
	231	writel(offs, spifi->io_base + SPIFI_ADDR);
	232
	233	cmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL \|
	234	SPIFI_CMD_OPCODE(nor->erase_opcode) \|
	235	SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);
	236	writel(cmd, spifi->io_base + SPIFI_CMD);
	237
	238	return nxp_spifi_wait_for_cmd(spifi);
	239	}
	240
	241	static int nxp_spifi_setup_memory_cmd(struct nxp_spifi *spifi)
	242	{
cfc5604c CP	243	switch (spifi->nor.read_proto) {
cfc5604c CP	244	case SNOR_PROTO_1_1_1:
f617b958 JE	245	spifi->mcmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL;
f617b958 JE	246	break;
cfc5604c CP	247	case SNOR_PROTO_1_1_2:
cfc5604c CP	248	case SNOR_PROTO_1_1_4:
f617b958 JE	249	spifi->mcmd = SPIFI_CMD_FIELDFORM_QUAD_DUAL_DATA;
	250	break;
	251	default:
	252	dev_err(spifi->dev, "unsupported SPI read mode\n");
	253	return -EINVAL;
	254	}
	255
	256	/* Memory mode supports address length between 1 and 4 */
	257	if (spifi->nor.addr_width < 1 \|\| spifi->nor.addr_width > 4)
	258	return -EINVAL;
	259
	260	spifi->mcmd \|= SPIFI_CMD_OPCODE(spifi->nor.read_opcode) \|
	261	SPIFI_CMD_INTLEN(spifi->nor.read_dummy / 8) \|
	262	SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);
	263
	264	return 0;
	265	}
	266
	267	static void nxp_spifi_dummy_id_read(struct spi_nor *nor)
	268	{
	269	u8 id[SPI_NOR_MAX_ID_LEN];
	270	nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
	271	}
	272
	273	static int nxp_spifi_setup_flash(struct nxp_spifi *spifi,
	274	struct device_node *np)
	275	{
cfc5604c CP	276	struct spi_nor_hwcaps hwcaps = {
	277	.mask = SNOR_HWCAPS_READ \|
	278	SNOR_HWCAPS_READ_FAST \|
	279	SNOR_HWCAPS_PP,
	280	};
f617b958 JE	281	u32 ctrl, property;
	282	u16 mode = 0;
	283	int ret;
	284
	285	if (!of_property_read_u32(np, "spi-rx-bus-width", &property)) {
	286	switch (property) {
	287	case 1:
	288	break;
	289	case 2:
	290	mode \|= SPI_RX_DUAL;
	291	break;
	292	case 4:
	293	mode \|= SPI_RX_QUAD;
	294	break;
	295	default:
	296	dev_err(spifi->dev, "unsupported rx-bus-width\n");
	297	return -EINVAL;
	298	}
	299	}
	300
	301	if (of_find_property(np, "spi-cpha", NULL))
	302	mode \|= SPI_CPHA;
	303
	304	if (of_find_property(np, "spi-cpol", NULL))
	305	mode \|= SPI_CPOL;
	306
	307	/* Setup control register defaults */
	308	ctrl = SPIFI_CTRL_TIMEOUT(1000) \|
	309	SPIFI_CTRL_CSHIGH(15) \|
	310	SPIFI_CTRL_FBCLK;
	311
	312	if (mode & SPI_RX_DUAL) {
	313	ctrl \|= SPIFI_CTRL_DUAL;
cfc5604c	314	hwcaps.mask \|= SNOR_HWCAPS_READ_1_1_2;
f617b958 JE	315	} else if (mode & SPI_RX_QUAD) {
f617b958 JE	316	ctrl &= ~SPIFI_CTRL_DUAL;
cfc5604c	317	hwcaps.mask \|= SNOR_HWCAPS_READ_1_1_4;
f617b958 JE	318	} else {
f617b958 JE	319	ctrl \|= SPIFI_CTRL_DUAL;
f617b958 JE	320	}
	321
	322	switch (mode & (SPI_CPHA \| SPI_CPOL)) {
	323	case SPI_MODE_0:
	324	ctrl &= ~SPIFI_CTRL_MODE3;
	325	break;
	326	case SPI_MODE_3:
	327	ctrl \|= SPIFI_CTRL_MODE3;
	328	break;
	329	default:
	330	dev_err(spifi->dev, "only mode 0 and 3 supported\n");
	331	return -EINVAL;
	332	}
	333
	334	writel(ctrl, spifi->io_base + SPIFI_CTRL);
	335
f617b958	336	spifi->nor.dev = spifi->dev;
9c7d7875	337	spi_nor_set_flash_node(&spifi->nor, np);
f617b958 JE	338	spifi->nor.priv = spifi;
	339	spifi->nor.read = nxp_spifi_read;
	340	spifi->nor.write = nxp_spifi_write;
	341	spifi->nor.erase = nxp_spifi_erase;
	342	spifi->nor.read_reg = nxp_spifi_read_reg;
	343	spifi->nor.write_reg = nxp_spifi_write_reg;
	344
	345	/*
	346	* The first read on a hard reset isn't reliable so do a
	347	* dummy read of the id before calling spi_nor_scan().
	348	* The reason for this problem is unknown.
	349	*
	350	* The official NXP spifilib uses more or less the same
	351	* workaround that is applied here by reading the device
	352	* id multiple times.
	353	*/
	354	nxp_spifi_dummy_id_read(&spifi->nor);
	355
cfc5604c	356	ret = spi_nor_scan(&spifi->nor, NULL, &hwcaps);
f617b958 JE	357	if (ret) {
	358	dev_err(spifi->dev, "device scan failed\n");
	359	return ret;
	360	}
	361
	362	ret = nxp_spifi_setup_memory_cmd(spifi);
	363	if (ret) {
	364	dev_err(spifi->dev, "memory command setup failed\n");
	365	return ret;
	366	}
	367
df02c885	368	ret = mtd_device_register(&spifi->nor.mtd, NULL, 0);
f617b958 JE	369	if (ret) {
	370	dev_err(spifi->dev, "mtd device parse failed\n");
	371	return ret;
	372	}
	373
	374	return 0;
	375	}
	376
	377	static int nxp_spifi_probe(struct platform_device *pdev)
	378	{
	379	struct device_node *flash_np;
	380	struct nxp_spifi *spifi;
	381	struct resource *res;
	382	int ret;
	383
	384	spifi = devm_kzalloc(&pdev->dev, sizeof(*spifi), GFP_KERNEL);
	385	if (!spifi)
	386	return -ENOMEM;
	387
	388	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spifi");
	389	spifi->io_base = devm_ioremap_resource(&pdev->dev, res);
	390	if (IS_ERR(spifi->io_base))
	391	return PTR_ERR(spifi->io_base);
	392
	393	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash");
	394	spifi->flash_base = devm_ioremap_resource(&pdev->dev, res);
	395	if (IS_ERR(spifi->flash_base))
	396	return PTR_ERR(spifi->flash_base);
	397
	398	spifi->clk_spifi = devm_clk_get(&pdev->dev, "spifi");
	399	if (IS_ERR(spifi->clk_spifi)) {
	400	dev_err(&pdev->dev, "spifi clock not found\n");
	401	return PTR_ERR(spifi->clk_spifi);
	402	}
	403
	404	spifi->clk_reg = devm_clk_get(&pdev->dev, "reg");
	405	if (IS_ERR(spifi->clk_reg)) {
	406	dev_err(&pdev->dev, "reg clock not found\n");
	407	return PTR_ERR(spifi->clk_reg);
	408	}
	409
	410	ret = clk_prepare_enable(spifi->clk_reg);
	411	if (ret) {
	412	dev_err(&pdev->dev, "unable to enable reg clock\n");
	413	return ret;
	414	}
	415
	416	ret = clk_prepare_enable(spifi->clk_spifi);
	417	if (ret) {
	418	dev_err(&pdev->dev, "unable to enable spifi clock\n");
	419	goto dis_clk_reg;
	420	}
	421
	422	spifi->dev = &pdev->dev;
	423	platform_set_drvdata(pdev, spifi);
	424
	425	/* Initialize and reset device */
	426	nxp_spifi_reset(spifi);
	427	writel(0, spifi->io_base + SPIFI_IDATA);
	428	writel(0, spifi->io_base + SPIFI_MCMD);
	429	nxp_spifi_reset(spifi);
	430
	431	flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
	432	if (!flash_np) {
433	dev_err(&pdev->dev, "no SPI flash device to configure\n");
434	ret = -ENODEV;
435	goto dis_clks;
436	}
437
438	ret = nxp_spifi_setup_flash(spifi, flash_np);
439	if (ret) {
440	dev_err(&pdev->dev, "unable to setup flash chip\n");
441	goto dis_clks;
442	}
443
444	return 0;
445
446	dis_clks:
447	clk_disable_unprepare(spifi->clk_spifi);
448	dis_clk_reg:
449	clk_disable_unprepare(spifi->clk_reg);
450	return ret;
451	}
452
453	static int nxp_spifi_remove(struct platform_device *pdev)
454	{
455	struct nxp_spifi *spifi = platform_get_drvdata(pdev);
456
19763671	457	mtd_device_unregister(&spifi->nor.mtd);
f617b958 JE	458	clk_disable_unprepare(spifi->clk_spifi);
	459	clk_disable_unprepare(spifi->clk_reg);
	460
	461	return 0;
	462	}
	463
	464	static const struct of_device_id nxp_spifi_match[] = {
	465	{.compatible = "nxp,lpc1773-spifi"},
	466	{ /* sentinel */ }
	467	};
	468	MODULE_DEVICE_TABLE(of, nxp_spifi_match);
	469
	470	static struct platform_driver nxp_spifi_driver = {
	471	.probe = nxp_spifi_probe,
	472	.remove = nxp_spifi_remove,
	473	.driver = {
	474	.name = "nxp-spifi",
	475	.of_match_table = nxp_spifi_match,
	476	},
	477	};
	478	module_platform_driver(nxp_spifi_driver);
	479
	480	MODULE_DESCRIPTION("NXP SPI Flash Interface driver");
	481	MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
	482	MODULE_LICENSE("GPL v2");