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[mirror_ubuntu-artful-kernel.git] / drivers / mtd / spi-nor / spi-nor.c
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b199489d 1/*
8eabdd1e
HS		 2 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
3 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
4 *
5 * Copyright (C) 2005, Intec Automation Inc.
6 * Copyright (C) 2014, Freescale Semiconductor, Inc.
b199489d
HS		 7 *
8 * This code is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/err.h>
14#include <linux/errno.h>
15#include <linux/module.h>
16#include <linux/device.h>
17#include <linux/mutex.h>
18#include <linux/math64.h>
19
20#include <linux/mtd/cfi.h>
21#include <linux/mtd/mtd.h>
22#include <linux/of_platform.h>
23#include <linux/spi/flash.h>
24#include <linux/mtd/spi-nor.h>
25
26/* Define max times to check status register before we give up. */
27#define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
28
29#define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
30
70f3ce05
BH		 31static const struct spi_device_id *spi_nor_match_id(const char *name);
32
b199489d
HS		 33/*
34 * Read the status register, returning its value in the location
35 * Return the status register value.
36 * Returns negative if error occurred.
37 */
38static int read_sr(struct spi_nor *nor)
39{
40 int ret;
41 u8 val;
42
b02e7f3e 43 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
b199489d
HS		 44 if (ret < 0) {
45 pr_err("error %d reading SR\n", (int) ret);
46 return ret;
47 }
48
49 return val;
50}
51
c14dedde 52/*
53 * Read the flag status register, returning its value in the location
54 * Return the status register value.
55 * Returns negative if error occurred.
56 */
57static int read_fsr(struct spi_nor *nor)
58{
59 int ret;
60 u8 val;
61
62 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
63 if (ret < 0) {
64 pr_err("error %d reading FSR\n", ret);
65 return ret;
66 }
67
68 return val;
69}
70
b199489d
HS		 71/*
72 * Read configuration register, returning its value in the
73 * location. Return the configuration register value.
74 * Returns negative if error occured.
75 */
76static int read_cr(struct spi_nor *nor)
77{
78 int ret;
79 u8 val;
80
b02e7f3e 81 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
b199489d
HS		 82 if (ret < 0) {
83 dev_err(nor->dev, "error %d reading CR\n", ret);
84 return ret;
85 }
86
87 return val;
88}
89
90/*
91 * Dummy Cycle calculation for different type of read.
92 * It can be used to support more commands with
93 * different dummy cycle requirements.
94 */
95static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
96{
97 switch (nor->flash_read) {
98 case SPI_NOR_FAST:
99 case SPI_NOR_DUAL:
100 case SPI_NOR_QUAD:
101 return 1;
102 case SPI_NOR_NORMAL:
103 return 0;
104 }
105 return 0;
106}
107
108/*
109 * Write status register 1 byte
110 * Returns negative if error occurred.
111 */
112static inline int write_sr(struct spi_nor *nor, u8 val)
113{
114 nor->cmd_buf[0] = val;
b02e7f3e 115 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
b199489d
HS		 116}
117
118/*
119 * Set write enable latch with Write Enable command.
120 * Returns negative if error occurred.
121 */
122static inline int write_enable(struct spi_nor *nor)
123{
b02e7f3e 124 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
b199489d
HS		 125}
126
127/*
128 * Send write disble instruction to the chip.
129 */
130static inline int write_disable(struct spi_nor *nor)
131{
b02e7f3e 132 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0);
b199489d
HS		 133}
134
135static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
136{
137 return mtd->priv;
138}
139
140/* Enable/disable 4-byte addressing mode. */
141static inline int set_4byte(struct spi_nor *nor, u32 jedec_id, int enable)
142{
143 int status;
144 bool need_wren = false;
145 u8 cmd;
146
147 switch (JEDEC_MFR(jedec_id)) {
148 case CFI_MFR_ST: /* Micron, actually */
149 /* Some Micron need WREN command; all will accept it */
150 need_wren = true;
151 case CFI_MFR_MACRONIX:
152 case 0xEF /* winbond */:
153 if (need_wren)
154 write_enable(nor);
155
b02e7f3e 156 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
b199489d
HS		 157 status = nor->write_reg(nor, cmd, NULL, 0, 0);
158 if (need_wren)
159 write_disable(nor);
160
161 return status;
162 default:
163 /* Spansion style */
164 nor->cmd_buf[0] = enable << 7;
b02e7f3e 165 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0);
b199489d
HS		 166 }
167}
168
169static int spi_nor_wait_till_ready(struct spi_nor *nor)
170{
171 unsigned long deadline;
172 int sr;
173
174 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
175
176 do {
177 cond_resched();
178
179 sr = read_sr(nor);
180 if (sr < 0)
181 break;
182 else if (!(sr & SR_WIP))
183 return 0;
184 } while (!time_after_eq(jiffies, deadline));
185
186 return -ETIMEDOUT;
187}
188
c14dedde 189static int spi_nor_wait_till_fsr_ready(struct spi_nor *nor)
190{
191 unsigned long deadline;
192 int sr;
193 int fsr;
194
195 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
196
197 do {
198 cond_resched();
199
200 sr = read_sr(nor);
201 if (sr < 0) {
202 break;
203 } else if (!(sr & SR_WIP)) {
204 fsr = read_fsr(nor);
205 if (fsr < 0)
206 break;
207 if (fsr & FSR_READY)
208 return 0;
209 }
210 } while (!time_after_eq(jiffies, deadline));
211
212 return -ETIMEDOUT;
213}
214
b199489d
HS		 215/*
216 * Service routine to read status register until ready, or timeout occurs.
217 * Returns non-zero if error.
218 */
219static int wait_till_ready(struct spi_nor *nor)
220{
221 return nor->wait_till_ready(nor);
222}
223
224/*
225 * Erase the whole flash memory
226 *
227 * Returns 0 if successful, non-zero otherwise.
228 */
229static int erase_chip(struct spi_nor *nor)
230{
231 int ret;
232
233 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd->size >> 10));
234
235 /* Wait until finished previous write command. */
236 ret = wait_till_ready(nor);
237 if (ret)
238 return ret;
239
240 /* Send write enable, then erase commands. */
241 write_enable(nor);
242
b02e7f3e 243 return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0);
b199489d
HS		 244}
245
246static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
247{
248 int ret = 0;
249
250 mutex_lock(&nor->lock);
251
252 if (nor->prepare) {
253 ret = nor->prepare(nor, ops);
254 if (ret) {
255 dev_err(nor->dev, "failed in the preparation.\n");
256 mutex_unlock(&nor->lock);
257 return ret;
258 }
259 }
260 return ret;
261}
262
263static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
264{
265 if (nor->unprepare)
266 nor->unprepare(nor, ops);
267 mutex_unlock(&nor->lock);
268}
269
270/*
271 * Erase an address range on the nor chip. The address range may extend
272 * one or more erase sectors. Return an error is there is a problem erasing.
273 */
274static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
275{
276 struct spi_nor *nor = mtd_to_spi_nor(mtd);
277 u32 addr, len;
278 uint32_t rem;
279 int ret;
280
281 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
282 (long long)instr->len);
283
284 div_u64_rem(instr->len, mtd->erasesize, &rem);
285 if (rem)
286 return -EINVAL;
287
288 addr = instr->addr;
289 len = instr->len;
290
291 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
292 if (ret)
293 return ret;
294
295 /* whole-chip erase? */
296 if (len == mtd->size) {
297 if (erase_chip(nor)) {
298 ret = -EIO;
299 goto erase_err;
300 }
301
302 /* REVISIT in some cases we could speed up erasing large regions
b02e7f3e 303 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
b199489d
HS		 304 * to use "small sector erase", but that's not always optimal.
305 */
306
307 /* "sector"-at-a-time erase */
308 } else {
309 while (len) {
310 if (nor->erase(nor, addr)) {
311 ret = -EIO;
312 goto erase_err;
313 }
314
315 addr += mtd->erasesize;
316 len -= mtd->erasesize;
317 }
318 }
319
320 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
321
322 instr->state = MTD_ERASE_DONE;
323 mtd_erase_callback(instr);
324
325 return ret;
326
327erase_err:
328 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
329 instr->state = MTD_ERASE_FAILED;
330 return ret;
331}
332
333static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
334{
335 struct spi_nor *nor = mtd_to_spi_nor(mtd);
336 uint32_t offset = ofs;
337 uint8_t status_old, status_new;
338 int ret = 0;
339
340 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
341 if (ret)
342 return ret;
343
344 /* Wait until finished previous command */
345 ret = wait_till_ready(nor);
346 if (ret)
347 goto err;
348
349 status_old = read_sr(nor);
350
351 if (offset < mtd->size - (mtd->size / 2))
352 status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
353 else if (offset < mtd->size - (mtd->size / 4))
354 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
355 else if (offset < mtd->size - (mtd->size / 8))
356 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
357 else if (offset < mtd->size - (mtd->size / 16))
358 status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
359 else if (offset < mtd->size - (mtd->size / 32))
360 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
361 else if (offset < mtd->size - (mtd->size / 64))
362 status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
363 else
364 status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
365
366 /* Only modify protection if it will not unlock other areas */
367 if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) >
368 (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
369 write_enable(nor);
370 ret = write_sr(nor, status_new);
371 if (ret)
372 goto err;
373 }
374
375err:
376 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
377 return ret;
378}
379
380static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
381{
382 struct spi_nor *nor = mtd_to_spi_nor(mtd);
383 uint32_t offset = ofs;
384 uint8_t status_old, status_new;
385 int ret = 0;
386
387 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
388 if (ret)
389 return ret;
390
391 /* Wait until finished previous command */
392 ret = wait_till_ready(nor);
393 if (ret)
394 goto err;
395
396 status_old = read_sr(nor);
397
398 if (offset+len > mtd->size - (mtd->size / 64))
399 status_new = status_old & ~(SR_BP2 | SR_BP1 | SR_BP0);
400 else if (offset+len > mtd->size - (mtd->size / 32))
401 status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
402 else if (offset+len > mtd->size - (mtd->size / 16))
403 status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
404 else if (offset+len > mtd->size - (mtd->size / 8))
405 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
406 else if (offset+len > mtd->size - (mtd->size / 4))
407 status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
408 else if (offset+len > mtd->size - (mtd->size / 2))
409 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
410 else
411 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
412
413 /* Only modify protection if it will not lock other areas */
414 if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) <
415 (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
416 write_enable(nor);
417 ret = write_sr(nor, status_new);
418 if (ret)
419 goto err;
420 }
421
422err:
423 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
424 return ret;
425}
426
427struct flash_info {
428 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
429 * a high byte of zero plus three data bytes: the manufacturer id,
430 * then a two byte device id.
431 */
432 u32 jedec_id;
433 u16 ext_id;
434
b02e7f3e 435 /* The size listed here is what works with SPINOR_OP_SE, which isn't
b199489d
HS		 436 * necessarily called a "sector" by the vendor.
437 */
438 unsigned sector_size;
439 u16 n_sectors;
440
441 u16 page_size;
442 u16 addr_width;
443
444 u16 flags;
b02e7f3e 445#define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
b199489d
HS		 446#define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
447#define SST_WRITE 0x04 /* use SST byte programming */
448#define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
b02e7f3e 449#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
b199489d
HS		 450#define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
451#define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
c14dedde 452#define USE_FSR 0x80 /* use flag status register */
b199489d
HS		 453};
454
455#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
456 ((kernel_ulong_t)&(struct flash_info) { \
457 .jedec_id = (_jedec_id), \
458 .ext_id = (_ext_id), \
459 .sector_size = (_sector_size), \
460 .n_sectors = (_n_sectors), \
461 .page_size = 256, \
462 .flags = (_flags), \
463 })
464
465#define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
466 ((kernel_ulong_t)&(struct flash_info) { \
467 .sector_size = (_sector_size), \
468 .n_sectors = (_n_sectors), \
469 .page_size = (_page_size), \
470 .addr_width = (_addr_width), \
471 .flags = (_flags), \
472 })
473
474/* NOTE: double check command sets and memory organization when you add
475 * more nor chips. This current list focusses on newer chips, which
476 * have been converging on command sets which including JEDEC ID.
477 */
a5b7616c 478static const struct spi_device_id spi_nor_ids[] = {
b199489d
HS		 479 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
480 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
481 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
482
483 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
484 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
485 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
486
487 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
488 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
489 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
490 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
491
492 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
493
494 /* EON -- en25xxx */
495 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
496 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
497 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
498 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
499 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
a41595b3 500 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
b199489d
HS		 501 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
502
503 /* ESMT */
504 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
505
506 /* Everspin */
507 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
508 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
509
510 /* GigaDevice */
511 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
512 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
513
514 /* Intel/Numonyx -- xxxs33b */
515 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
516 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
517 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
518
519 /* Macronix */
520 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
521 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
522 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
523 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
524 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
525 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
526 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
527 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
528 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
529 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
530 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
531 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
532 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
533
534 /* Micron */
535 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
536 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
537 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
538 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
539 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
c14dedde 540 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, USE_FSR) },
541 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, USE_FSR) },
b199489d
HS		 542
543 /* PMC */
544 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
545 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
546 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
547
548 /* Spansion -- single (large) sector size only, at least
549 * for the chips listed here (without boot sectors).
550 */
9ab86995 551 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
b199489d
HS		 552 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
553 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
554 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
555 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
556 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
557 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
558 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
559 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
560 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
561 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
562 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
563 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
564 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
565 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
566 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
567 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
568 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
569
570 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
571 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
572 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
573 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
574 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
575 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
576 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
577 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
578 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
579 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
580
581 /* ST Microelectronics -- newer production may have feature updates */
582 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
583 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
584 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
585 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
586 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
587 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
588 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
589 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
590 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
591 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
592
593 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
594 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
595 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
596 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
597 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
598 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
599 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
600 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
601 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
602
603 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
604 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
605 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
606
607 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
608 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
609 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
610
611 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
612 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
613 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
614 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
615 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
f2fabe16 616 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
b199489d
HS		 617
618 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
619 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
620 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
621 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
622 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
623 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
624 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
625 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
626 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
627 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
628 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
b199489d
HS		 629 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
630 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
631 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
632 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
633
634 /* Catalyst / On Semiconductor -- non-JEDEC */
635 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
636 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
637 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
638 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
639 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
640 { },
641};
642
643static const struct spi_device_id *spi_nor_read_id(struct spi_nor *nor)
644{
645 int tmp;
646 u8 id[5];
647 u32 jedec;
648 u16 ext_jedec;
649 struct flash_info *info;
650
b02e7f3e 651 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, 5);
b199489d
HS		 652 if (tmp < 0) {
653 dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp);
654 return ERR_PTR(tmp);
655 }
656 jedec = id[0];
657 jedec = jedec << 8;
658 jedec |= id[1];
659 jedec = jedec << 8;
660 jedec |= id[2];
661
662 ext_jedec = id[3] << 8 | id[4];
663
664 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
665 info = (void *)spi_nor_ids[tmp].driver_data;
666 if (info->jedec_id == jedec) {
667 if (info->ext_id == 0 || info->ext_id == ext_jedec)
668 return &spi_nor_ids[tmp];
669 }
670 }
671 dev_err(nor->dev, "unrecognized JEDEC id %06x\n", jedec);
672 return ERR_PTR(-ENODEV);
673}
674
b199489d
HS		 675static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
676 size_t *retlen, u_char *buf)
677{
678 struct spi_nor *nor = mtd_to_spi_nor(mtd);
679 int ret;
680
681 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
682
683 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
684 if (ret)
685 return ret;
686
687 ret = nor->read(nor, from, len, retlen, buf);
688
689 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
690 return ret;
691}
692
693static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
694 size_t *retlen, const u_char *buf)
695{
696 struct spi_nor *nor = mtd_to_spi_nor(mtd);
697 size_t actual;
698 int ret;
699
700 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
701
702 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
703 if (ret)
704 return ret;
705
706 /* Wait until finished previous write command. */
707 ret = wait_till_ready(nor);
708 if (ret)
709 goto time_out;
710
711 write_enable(nor);
712
713 nor->sst_write_second = false;
714
715 actual = to % 2;
716 /* Start write from odd address. */
717 if (actual) {
b02e7f3e 718 nor->program_opcode = SPINOR_OP_BP;
b199489d
HS		 719
720 /* write one byte. */
721 nor->write(nor, to, 1, retlen, buf);
722 ret = wait_till_ready(nor);
723 if (ret)
724 goto time_out;
725 }
726 to += actual;
727
728 /* Write out most of the data here. */
729 for (; actual < len - 1; actual += 2) {
b02e7f3e 730 nor->program_opcode = SPINOR_OP_AAI_WP;
b199489d
HS		 731
732 /* write two bytes. */
733 nor->write(nor, to, 2, retlen, buf + actual);
734 ret = wait_till_ready(nor);
735 if (ret)
736 goto time_out;
737 to += 2;
738 nor->sst_write_second = true;
739 }
740 nor->sst_write_second = false;
741
742 write_disable(nor);
743 ret = wait_till_ready(nor);
744 if (ret)
745 goto time_out;
746
747 /* Write out trailing byte if it exists. */
748 if (actual != len) {
749 write_enable(nor);
750
b02e7f3e 751 nor->program_opcode = SPINOR_OP_BP;
b199489d
HS		 752 nor->write(nor, to, 1, retlen, buf + actual);
753
754 ret = wait_till_ready(nor);
755 if (ret)
756 goto time_out;
757 write_disable(nor);
758 }
759time_out:
760 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
761 return ret;
762}
763
764/*
765 * Write an address range to the nor chip. Data must be written in
766 * FLASH_PAGESIZE chunks. The address range may be any size provided
767 * it is within the physical boundaries.
768 */
769static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
770 size_t *retlen, const u_char *buf)
771{
772 struct spi_nor *nor = mtd_to_spi_nor(mtd);
773 u32 page_offset, page_size, i;
774 int ret;
775
776 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
777
778 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
779 if (ret)
780 return ret;
781
782 /* Wait until finished previous write command. */
783 ret = wait_till_ready(nor);
784 if (ret)
785 goto write_err;
786
787 write_enable(nor);
788
789 page_offset = to & (nor->page_size - 1);
790
791 /* do all the bytes fit onto one page? */
792 if (page_offset + len <= nor->page_size) {
793 nor->write(nor, to, len, retlen, buf);
794 } else {
795 /* the size of data remaining on the first page */
796 page_size = nor->page_size - page_offset;
797 nor->write(nor, to, page_size, retlen, buf);
798
799 /* write everything in nor->page_size chunks */
800 for (i = page_size; i < len; i += page_size) {
801 page_size = len - i;
802 if (page_size > nor->page_size)
803 page_size = nor->page_size;
804
805 wait_till_ready(nor);
806 write_enable(nor);
807
808 nor->write(nor, to + i, page_size, retlen, buf + i);
809 }
810 }
811
812write_err:
813 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
814 return 0;
815}
816
817static int macronix_quad_enable(struct spi_nor *nor)
818{
819 int ret, val;
820
821 val = read_sr(nor);
822 write_enable(nor);
823
824 nor->cmd_buf[0] = val | SR_QUAD_EN_MX;
b02e7f3e 825 nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
b199489d
HS		 826
827 if (wait_till_ready(nor))
828 return 1;
829
830 ret = read_sr(nor);
831 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
832 dev_err(nor->dev, "Macronix Quad bit not set\n");
833 return -EINVAL;
834 }
835
836 return 0;
837}
838
839/*
840 * Write status Register and configuration register with 2 bytes
841 * The first byte will be written to the status register, while the
842 * second byte will be written to the configuration register.
843 * Return negative if error occured.
844 */
845static int write_sr_cr(struct spi_nor *nor, u16 val)
846{
847 nor->cmd_buf[0] = val & 0xff;
848 nor->cmd_buf[1] = (val >> 8);
849
b02e7f3e 850 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0);
b199489d
HS		 851}
852
853static int spansion_quad_enable(struct spi_nor *nor)
854{
855 int ret;
856 int quad_en = CR_QUAD_EN_SPAN << 8;
857
858 write_enable(nor);
859
860 ret = write_sr_cr(nor, quad_en);
861 if (ret < 0) {
862 dev_err(nor->dev,
863 "error while writing configuration register\n");
864 return -EINVAL;
865 }
866
867 /* read back and check it */
868 ret = read_cr(nor);
869 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
870 dev_err(nor->dev, "Spansion Quad bit not set\n");
871 return -EINVAL;
872 }
873
874 return 0;
875}
876
877static int set_quad_mode(struct spi_nor *nor, u32 jedec_id)
878{
879 int status;
880
881 switch (JEDEC_MFR(jedec_id)) {
882 case CFI_MFR_MACRONIX:
883 status = macronix_quad_enable(nor);
884 if (status) {
885 dev_err(nor->dev, "Macronix quad-read not enabled\n");
886 return -EINVAL;
887 }
888 return status;
889 default:
890 status = spansion_quad_enable(nor);
891 if (status) {
892 dev_err(nor->dev, "Spansion quad-read not enabled\n");
893 return -EINVAL;
894 }
895 return status;
896 }
897}
898
899static int spi_nor_check(struct spi_nor *nor)
900{
901 if (!nor->dev || !nor->read || !nor->write ||
902 !nor->read_reg || !nor->write_reg || !nor->erase) {
903 pr_err("spi-nor: please fill all the necessary fields!\n");
904 return -EINVAL;
905 }
906
907 if (!nor->read_id)
908 nor->read_id = spi_nor_read_id;
909 if (!nor->wait_till_ready)
910 nor->wait_till_ready = spi_nor_wait_till_ready;
911
912 return 0;
913}
914
70f3ce05 915int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
b199489d 916{
70f3ce05 917 const struct spi_device_id *id = NULL;
b199489d 918 struct flash_info *info;
b199489d
HS		 919 struct device *dev = nor->dev;
920 struct mtd_info *mtd = nor->mtd;
921 struct device_node *np = dev->of_node;
922 int ret;
923 int i;
924
925 ret = spi_nor_check(nor);
926 if (ret)
927 return ret;
928
70f3ce05
BH		 929 id = spi_nor_match_id(name);
930 if (!id)
931 return -ENOENT;
932
b199489d
HS		 933 info = (void *)id->driver_data;
934
935 if (info->jedec_id) {
936 const struct spi_device_id *jid;
937
54ea17a5 938 jid = nor->read_id(nor);
b199489d
HS		 939 if (IS_ERR(jid)) {
940 return PTR_ERR(jid);
941 } else if (jid != id) {
942 /*
943 * JEDEC knows better, so overwrite platform ID. We
944 * can't trust partitions any longer, but we'll let
945 * mtd apply them anyway, since some partitions may be
946 * marked read-only, and we don't want to lose that
947 * information, even if it's not 100% accurate.
948 */
949 dev_warn(dev, "found %s, expected %s\n",
950 jid->name, id->name);
951 id = jid;
952 info = (void *)jid->driver_data;
953 }
954 }
955
956 mutex_init(&nor->lock);
957
958 /*
959 * Atmel, SST and Intel/Numonyx serial nor tend to power
960 * up with the software protection bits set
961 */
962
963 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
964 JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
965 JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
966 write_enable(nor);
967 write_sr(nor, 0);
968 }
969
32f1b7c8 970 if (!mtd->name)
b199489d 971 mtd->name = dev_name(dev);
b199489d
HS		 972 mtd->type = MTD_NORFLASH;
973 mtd->writesize = 1;
974 mtd->flags = MTD_CAP_NORFLASH;
975 mtd->size = info->sector_size * info->n_sectors;
976 mtd->_erase = spi_nor_erase;
977 mtd->_read = spi_nor_read;
978
979 /* nor protection support for STmicro chips */
980 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
981 mtd->_lock = spi_nor_lock;
982 mtd->_unlock = spi_nor_unlock;
983 }
984
985 /* sst nor chips use AAI word program */
986 if (info->flags & SST_WRITE)
987 mtd->_write = sst_write;
988 else
989 mtd->_write = spi_nor_write;
990
c14dedde 991 if ((info->flags & USE_FSR) &&
992 nor->wait_till_ready == spi_nor_wait_till_ready)
993 nor->wait_till_ready = spi_nor_wait_till_fsr_ready;
994
57cf26c1 995#ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
b199489d
HS		 996 /* prefer "small sector" erase if possible */
997 if (info->flags & SECT_4K) {
b02e7f3e 998 nor->erase_opcode = SPINOR_OP_BE_4K;
b199489d
HS		 999 mtd->erasesize = 4096;
1000 } else if (info->flags & SECT_4K_PMC) {
b02e7f3e 1001 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
b199489d 1002 mtd->erasesize = 4096;
57cf26c1
RM		 1003 } else
1004#endif
1005 {
b02e7f3e 1006 nor->erase_opcode = SPINOR_OP_SE;
b199489d
HS		 1007 mtd->erasesize = info->sector_size;
1008 }
1009
1010 if (info->flags & SPI_NOR_NO_ERASE)
1011 mtd->flags |= MTD_NO_ERASE;
1012
1013 mtd->dev.parent = dev;
1014 nor->page_size = info->page_size;
1015 mtd->writebufsize = nor->page_size;
1016
1017 if (np) {
1018 /* If we were instantiated by DT, use it */
1019 if (of_property_read_bool(np, "m25p,fast-read"))
1020 nor->flash_read = SPI_NOR_FAST;
1021 else
1022 nor->flash_read = SPI_NOR_NORMAL;
1023 } else {
1024 /* If we weren't instantiated by DT, default to fast-read */
1025 nor->flash_read = SPI_NOR_FAST;
1026 }
1027
1028 /* Some devices cannot do fast-read, no matter what DT tells us */
1029 if (info->flags & SPI_NOR_NO_FR)
1030 nor->flash_read = SPI_NOR_NORMAL;
1031
1032 /* Quad/Dual-read mode takes precedence over fast/normal */
1033 if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
1034 ret = set_quad_mode(nor, info->jedec_id);
1035 if (ret) {
1036 dev_err(dev, "quad mode not supported\n");
1037 return ret;
1038 }
1039 nor->flash_read = SPI_NOR_QUAD;
1040 } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) {
1041 nor->flash_read = SPI_NOR_DUAL;
1042 }
1043
1044 /* Default commands */
1045 switch (nor->flash_read) {
1046 case SPI_NOR_QUAD:
58b89a1f 1047 nor->read_opcode = SPINOR_OP_READ_1_1_4;
b199489d
HS		 1048 break;
1049 case SPI_NOR_DUAL:
58b89a1f 1050 nor->read_opcode = SPINOR_OP_READ_1_1_2;
b199489d
HS		 1051 break;
1052 case SPI_NOR_FAST:
58b89a1f 1053 nor->read_opcode = SPINOR_OP_READ_FAST;
b199489d
HS		 1054 break;
1055 case SPI_NOR_NORMAL:
58b89a1f 1056 nor->read_opcode = SPINOR_OP_READ;
b199489d
HS		 1057 break;
1058 default:
1059 dev_err(dev, "No Read opcode defined\n");
1060 return -EINVAL;
1061 }
1062
b02e7f3e 1063 nor->program_opcode = SPINOR_OP_PP;
b199489d
HS		 1064
1065 if (info->addr_width)
1066 nor->addr_width = info->addr_width;
1067 else if (mtd->size > 0x1000000) {
1068 /* enable 4-byte addressing if the device exceeds 16MiB */
1069 nor->addr_width = 4;
1070 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) {
1071 /* Dedicated 4-byte command set */
1072 switch (nor->flash_read) {
1073 case SPI_NOR_QUAD:
58b89a1f 1074 nor->read_opcode = SPINOR_OP_READ4_1_1_4;
b199489d
HS		 1075 break;
1076 case SPI_NOR_DUAL:
58b89a1f 1077 nor->read_opcode = SPINOR_OP_READ4_1_1_2;
b199489d
HS		 1078 break;
1079 case SPI_NOR_FAST:
58b89a1f 1080 nor->read_opcode = SPINOR_OP_READ4_FAST;
b199489d
HS		 1081 break;
1082 case SPI_NOR_NORMAL:
58b89a1f 1083 nor->read_opcode = SPINOR_OP_READ4;
b199489d
HS		 1084 break;
1085 }
b02e7f3e 1086 nor->program_opcode = SPINOR_OP_PP_4B;
b199489d 1087 /* No small sector erase for 4-byte command set */
b02e7f3e 1088 nor->erase_opcode = SPINOR_OP_SE_4B;
b199489d
HS		 1089 mtd->erasesize = info->sector_size;
1090 } else
1091 set_4byte(nor, info->jedec_id, 1);
1092 } else {
1093 nor->addr_width = 3;
1094 }
1095
1096 nor->read_dummy = spi_nor_read_dummy_cycles(nor);
1097
1098 dev_info(dev, "%s (%lld Kbytes)\n", id->name,
1099 (long long)mtd->size >> 10);
1100
1101 dev_dbg(dev,
1102 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
1103 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1104 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
1105 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
1106
1107 if (mtd->numeraseregions)
1108 for (i = 0; i < mtd->numeraseregions; i++)
1109 dev_dbg(dev,
1110 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
1111 ".erasesize = 0x%.8x (%uKiB), "
1112 ".numblocks = %d }\n",
1113 i, (long long)mtd->eraseregions[i].offset,
1114 mtd->eraseregions[i].erasesize,
1115 mtd->eraseregions[i].erasesize / 1024,
1116 mtd->eraseregions[i].numblocks);
1117 return 0;
1118}
b61834b0 1119EXPORT_SYMBOL_GPL(spi_nor_scan);
b199489d 1120
70f3ce05 1121static const struct spi_device_id *spi_nor_match_id(const char *name)
0d8c11c0
HS		 1122{
1123 const struct spi_device_id *id = spi_nor_ids;
1124
1125 while (id->name[0]) {
1126 if (!strcmp(name, id->name))
1127 return id;
1128 id++;
1129 }
1130 return NULL;
1131}
1132
b199489d
HS		 1133MODULE_LICENSE("GPL");
1134MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
1135MODULE_AUTHOR("Mike Lavender");
1136MODULE_DESCRIPTION("framework for SPI NOR");
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