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Commit | Line | Data |
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b199489d | 1 | /* |
8eabdd1e HS |
2 | * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with |
3 | * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c | |
4 | * | |
5 | * Copyright (C) 2005, Intec Automation Inc. | |
6 | * Copyright (C) 2014, Freescale Semiconductor, Inc. | |
b199489d HS |
7 | * |
8 | * This code is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/err.h> | |
14 | #include <linux/errno.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/mutex.h> | |
18 | #include <linux/math64.h> | |
09b6a377 | 19 | #include <linux/sizes.h> |
b199489d | 20 | |
b199489d HS |
21 | #include <linux/mtd/mtd.h> |
22 | #include <linux/of_platform.h> | |
23 | #include <linux/spi/flash.h> | |
24 | #include <linux/mtd/spi-nor.h> | |
25 | ||
26 | /* Define max times to check status register before we give up. */ | |
09b6a377 FS |
27 | |
28 | /* | |
29 | * For everything but full-chip erase; probably could be much smaller, but kept | |
30 | * around for safety for now | |
31 | */ | |
32 | #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) | |
33 | ||
34 | /* | |
35 | * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up | |
36 | * for larger flash | |
37 | */ | |
38 | #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ) | |
b199489d | 39 | |
d928a259 | 40 | #define SPI_NOR_MAX_ID_LEN 6 |
c67cbb83 | 41 | #define SPI_NOR_MAX_ADDR_WIDTH 4 |
d928a259 HS |
42 | |
43 | struct flash_info { | |
06bb6f5a RM |
44 | char *name; |
45 | ||
d928a259 HS |
46 | /* |
47 | * This array stores the ID bytes. | |
48 | * The first three bytes are the JEDIC ID. | |
49 | * JEDEC ID zero means "no ID" (mostly older chips). | |
50 | */ | |
51 | u8 id[SPI_NOR_MAX_ID_LEN]; | |
52 | u8 id_len; | |
53 | ||
54 | /* The size listed here is what works with SPINOR_OP_SE, which isn't | |
55 | * necessarily called a "sector" by the vendor. | |
56 | */ | |
57 | unsigned sector_size; | |
58 | u16 n_sectors; | |
59 | ||
60 | u16 page_size; | |
61 | u16 addr_width; | |
62 | ||
63 | u16 flags; | |
0618114e BN |
64 | #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */ |
65 | #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */ | |
66 | #define SST_WRITE BIT(2) /* use SST byte programming */ | |
67 | #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */ | |
68 | #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */ | |
69 | #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */ | |
70 | #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */ | |
71 | #define USE_FSR BIT(7) /* use flag status register */ | |
76a4707d | 72 | #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */ |
3dd8012a BN |
73 | #define SPI_NOR_HAS_TB BIT(9) /* |
74 | * Flash SR has Top/Bottom (TB) protect | |
75 | * bit. Must be used with | |
76 | * SPI_NOR_HAS_LOCK. | |
77 | */ | |
e99ca98f RRD |
78 | #define SPI_S3AN BIT(10) /* |
79 | * Xilinx Spartan 3AN In-System Flash | |
80 | * (MFR cannot be used for probing | |
81 | * because it has the same value as | |
82 | * ATMEL flashes) | |
83 | */ | |
ba3ae6a1 CP |
84 | #define SPI_NOR_4B_OPCODES BIT(11) /* |
85 | * Use dedicated 4byte address op codes | |
86 | * to support memory size above 128Mib. | |
87 | */ | |
2f5ad7f0 | 88 | #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */ |
d928a259 HS |
89 | }; |
90 | ||
91 | #define JEDEC_MFR(info) ((info)->id[0]) | |
b199489d | 92 | |
06bb6f5a | 93 | static const struct flash_info *spi_nor_match_id(const char *name); |
70f3ce05 | 94 | |
b199489d HS |
95 | /* |
96 | * Read the status register, returning its value in the location | |
97 | * Return the status register value. | |
98 | * Returns negative if error occurred. | |
99 | */ | |
100 | static int read_sr(struct spi_nor *nor) | |
101 | { | |
102 | int ret; | |
103 | u8 val; | |
104 | ||
b02e7f3e | 105 | ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1); |
b199489d HS |
106 | if (ret < 0) { |
107 | pr_err("error %d reading SR\n", (int) ret); | |
108 | return ret; | |
109 | } | |
110 | ||
111 | return val; | |
112 | } | |
113 | ||
c14dedde | 114 | /* |
115 | * Read the flag status register, returning its value in the location | |
116 | * Return the status register value. | |
117 | * Returns negative if error occurred. | |
118 | */ | |
119 | static int read_fsr(struct spi_nor *nor) | |
120 | { | |
121 | int ret; | |
122 | u8 val; | |
123 | ||
124 | ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1); | |
125 | if (ret < 0) { | |
126 | pr_err("error %d reading FSR\n", ret); | |
127 | return ret; | |
128 | } | |
129 | ||
130 | return val; | |
131 | } | |
132 | ||
b199489d HS |
133 | /* |
134 | * Read configuration register, returning its value in the | |
135 | * location. Return the configuration register value. | |
5d708ecc | 136 | * Returns negative if error occurred. |
b199489d HS |
137 | */ |
138 | static int read_cr(struct spi_nor *nor) | |
139 | { | |
140 | int ret; | |
141 | u8 val; | |
142 | ||
b02e7f3e | 143 | ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1); |
b199489d HS |
144 | if (ret < 0) { |
145 | dev_err(nor->dev, "error %d reading CR\n", ret); | |
146 | return ret; | |
147 | } | |
148 | ||
149 | return val; | |
150 | } | |
151 | ||
b199489d HS |
152 | /* |
153 | * Write status register 1 byte | |
154 | * Returns negative if error occurred. | |
155 | */ | |
156 | static inline int write_sr(struct spi_nor *nor, u8 val) | |
157 | { | |
158 | nor->cmd_buf[0] = val; | |
f9f3ce83 | 159 | return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1); |
b199489d HS |
160 | } |
161 | ||
162 | /* | |
163 | * Set write enable latch with Write Enable command. | |
164 | * Returns negative if error occurred. | |
165 | */ | |
166 | static inline int write_enable(struct spi_nor *nor) | |
167 | { | |
f9f3ce83 | 168 | return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0); |
b199489d HS |
169 | } |
170 | ||
171 | /* | |
8a1115ff | 172 | * Send write disable instruction to the chip. |
b199489d HS |
173 | */ |
174 | static inline int write_disable(struct spi_nor *nor) | |
175 | { | |
f9f3ce83 | 176 | return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0); |
b199489d HS |
177 | } |
178 | ||
179 | static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) | |
180 | { | |
181 | return mtd->priv; | |
182 | } | |
183 | ||
ba3ae6a1 CP |
184 | |
185 | static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size) | |
186 | { | |
187 | size_t i; | |
188 | ||
189 | for (i = 0; i < size; i++) | |
190 | if (table[i][0] == opcode) | |
191 | return table[i][1]; | |
192 | ||
193 | /* No conversion found, keep input op code. */ | |
194 | return opcode; | |
195 | } | |
196 | ||
197 | static inline u8 spi_nor_convert_3to4_read(u8 opcode) | |
198 | { | |
199 | static const u8 spi_nor_3to4_read[][2] = { | |
200 | { SPINOR_OP_READ, SPINOR_OP_READ_4B }, | |
201 | { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B }, | |
202 | { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B }, | |
203 | { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B }, | |
204 | { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B }, | |
205 | { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B }, | |
15f55331 CP |
206 | |
207 | { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B }, | |
208 | { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B }, | |
209 | { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B }, | |
ba3ae6a1 CP |
210 | }; |
211 | ||
212 | return spi_nor_convert_opcode(opcode, spi_nor_3to4_read, | |
213 | ARRAY_SIZE(spi_nor_3to4_read)); | |
214 | } | |
215 | ||
216 | static inline u8 spi_nor_convert_3to4_program(u8 opcode) | |
217 | { | |
218 | static const u8 spi_nor_3to4_program[][2] = { | |
219 | { SPINOR_OP_PP, SPINOR_OP_PP_4B }, | |
220 | { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B }, | |
221 | { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B }, | |
222 | }; | |
223 | ||
224 | return spi_nor_convert_opcode(opcode, spi_nor_3to4_program, | |
225 | ARRAY_SIZE(spi_nor_3to4_program)); | |
226 | } | |
227 | ||
228 | static inline u8 spi_nor_convert_3to4_erase(u8 opcode) | |
229 | { | |
230 | static const u8 spi_nor_3to4_erase[][2] = { | |
231 | { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B }, | |
232 | { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B }, | |
233 | { SPINOR_OP_SE, SPINOR_OP_SE_4B }, | |
234 | }; | |
235 | ||
236 | return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase, | |
237 | ARRAY_SIZE(spi_nor_3to4_erase)); | |
238 | } | |
239 | ||
240 | static void spi_nor_set_4byte_opcodes(struct spi_nor *nor, | |
241 | const struct flash_info *info) | |
242 | { | |
243 | /* Do some manufacturer fixups first */ | |
244 | switch (JEDEC_MFR(info)) { | |
245 | case SNOR_MFR_SPANSION: | |
246 | /* No small sector erase for 4-byte command set */ | |
247 | nor->erase_opcode = SPINOR_OP_SE; | |
248 | nor->mtd.erasesize = info->sector_size; | |
249 | break; | |
250 | ||
251 | default: | |
252 | break; | |
253 | } | |
254 | ||
255 | nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode); | |
256 | nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode); | |
257 | nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode); | |
258 | } | |
259 | ||
b199489d | 260 | /* Enable/disable 4-byte addressing mode. */ |
06bb6f5a | 261 | static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info, |
d928a259 | 262 | int enable) |
b199489d HS |
263 | { |
264 | int status; | |
265 | bool need_wren = false; | |
266 | u8 cmd; | |
267 | ||
d928a259 | 268 | switch (JEDEC_MFR(info)) { |
f0d2448e | 269 | case SNOR_MFR_MICRON: |
b199489d HS |
270 | /* Some Micron need WREN command; all will accept it */ |
271 | need_wren = true; | |
f0d2448e BN |
272 | case SNOR_MFR_MACRONIX: |
273 | case SNOR_MFR_WINBOND: | |
b199489d HS |
274 | if (need_wren) |
275 | write_enable(nor); | |
276 | ||
b02e7f3e | 277 | cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; |
f9f3ce83 | 278 | status = nor->write_reg(nor, cmd, NULL, 0); |
b199489d HS |
279 | if (need_wren) |
280 | write_disable(nor); | |
281 | ||
282 | return status; | |
283 | default: | |
284 | /* Spansion style */ | |
285 | nor->cmd_buf[0] = enable << 7; | |
f9f3ce83 | 286 | return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1); |
b199489d HS |
287 | } |
288 | } | |
e99ca98f RRD |
289 | |
290 | static int s3an_sr_ready(struct spi_nor *nor) | |
291 | { | |
292 | int ret; | |
293 | u8 val; | |
294 | ||
295 | ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1); | |
296 | if (ret < 0) { | |
297 | dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret); | |
298 | return ret; | |
299 | } | |
300 | ||
301 | return !!(val & XSR_RDY); | |
302 | } | |
303 | ||
51983b7d | 304 | static inline int spi_nor_sr_ready(struct spi_nor *nor) |
b199489d | 305 | { |
51983b7d BN |
306 | int sr = read_sr(nor); |
307 | if (sr < 0) | |
308 | return sr; | |
309 | else | |
310 | return !(sr & SR_WIP); | |
311 | } | |
b199489d | 312 | |
51983b7d BN |
313 | static inline int spi_nor_fsr_ready(struct spi_nor *nor) |
314 | { | |
315 | int fsr = read_fsr(nor); | |
316 | if (fsr < 0) | |
317 | return fsr; | |
318 | else | |
319 | return fsr & FSR_READY; | |
320 | } | |
b199489d | 321 | |
51983b7d BN |
322 | static int spi_nor_ready(struct spi_nor *nor) |
323 | { | |
324 | int sr, fsr; | |
e99ca98f RRD |
325 | |
326 | if (nor->flags & SNOR_F_READY_XSR_RDY) | |
327 | sr = s3an_sr_ready(nor); | |
328 | else | |
329 | sr = spi_nor_sr_ready(nor); | |
51983b7d BN |
330 | if (sr < 0) |
331 | return sr; | |
332 | fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; | |
333 | if (fsr < 0) | |
334 | return fsr; | |
335 | return sr && fsr; | |
b199489d HS |
336 | } |
337 | ||
b94ed087 BN |
338 | /* |
339 | * Service routine to read status register until ready, or timeout occurs. | |
340 | * Returns non-zero if error. | |
341 | */ | |
09b6a377 FS |
342 | static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, |
343 | unsigned long timeout_jiffies) | |
c14dedde | 344 | { |
345 | unsigned long deadline; | |
a95ce92e | 346 | int timeout = 0, ret; |
c14dedde | 347 | |
09b6a377 | 348 | deadline = jiffies + timeout_jiffies; |
c14dedde | 349 | |
a95ce92e BN |
350 | while (!timeout) { |
351 | if (time_after_eq(jiffies, deadline)) | |
352 | timeout = 1; | |
c14dedde | 353 | |
51983b7d BN |
354 | ret = spi_nor_ready(nor); |
355 | if (ret < 0) | |
356 | return ret; | |
357 | if (ret) | |
358 | return 0; | |
a95ce92e BN |
359 | |
360 | cond_resched(); | |
361 | } | |
362 | ||
363 | dev_err(nor->dev, "flash operation timed out\n"); | |
c14dedde | 364 | |
365 | return -ETIMEDOUT; | |
366 | } | |
367 | ||
09b6a377 FS |
368 | static int spi_nor_wait_till_ready(struct spi_nor *nor) |
369 | { | |
370 | return spi_nor_wait_till_ready_with_timeout(nor, | |
371 | DEFAULT_READY_WAIT_JIFFIES); | |
372 | } | |
373 | ||
b199489d HS |
374 | /* |
375 | * Erase the whole flash memory | |
376 | * | |
377 | * Returns 0 if successful, non-zero otherwise. | |
378 | */ | |
379 | static int erase_chip(struct spi_nor *nor) | |
380 | { | |
19763671 | 381 | dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10)); |
b199489d | 382 | |
f9f3ce83 | 383 | return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0); |
b199489d HS |
384 | } |
385 | ||
386 | static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops) | |
387 | { | |
388 | int ret = 0; | |
389 | ||
390 | mutex_lock(&nor->lock); | |
391 | ||
392 | if (nor->prepare) { | |
393 | ret = nor->prepare(nor, ops); | |
394 | if (ret) { | |
395 | dev_err(nor->dev, "failed in the preparation.\n"); | |
396 | mutex_unlock(&nor->lock); | |
397 | return ret; | |
398 | } | |
399 | } | |
400 | return ret; | |
401 | } | |
402 | ||
403 | static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops) | |
404 | { | |
405 | if (nor->unprepare) | |
406 | nor->unprepare(nor, ops); | |
407 | mutex_unlock(&nor->lock); | |
408 | } | |
409 | ||
e99ca98f RRD |
410 | /* |
411 | * This code converts an address to the Default Address Mode, that has non | |
412 | * power of two page sizes. We must support this mode because it is the default | |
413 | * mode supported by Xilinx tools, it can access the whole flash area and | |
414 | * changing over to the Power-of-two mode is irreversible and corrupts the | |
415 | * original data. | |
416 | * Addr can safely be unsigned int, the biggest S3AN device is smaller than | |
417 | * 4 MiB. | |
418 | */ | |
419 | static loff_t spi_nor_s3an_addr_convert(struct spi_nor *nor, unsigned int addr) | |
420 | { | |
56c5c328 RRD |
421 | unsigned int offset; |
422 | unsigned int page; | |
e99ca98f | 423 | |
56c5c328 RRD |
424 | offset = addr % nor->page_size; |
425 | page = addr / nor->page_size; | |
426 | page <<= (nor->page_size > 512) ? 10 : 9; | |
e99ca98f | 427 | |
56c5c328 | 428 | return page | offset; |
e99ca98f RRD |
429 | } |
430 | ||
c67cbb83 BN |
431 | /* |
432 | * Initiate the erasure of a single sector | |
433 | */ | |
434 | static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) | |
435 | { | |
436 | u8 buf[SPI_NOR_MAX_ADDR_WIDTH]; | |
437 | int i; | |
438 | ||
e99ca98f RRD |
439 | if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT) |
440 | addr = spi_nor_s3an_addr_convert(nor, addr); | |
441 | ||
c67cbb83 BN |
442 | if (nor->erase) |
443 | return nor->erase(nor, addr); | |
444 | ||
445 | /* | |
446 | * Default implementation, if driver doesn't have a specialized HW | |
447 | * control | |
448 | */ | |
449 | for (i = nor->addr_width - 1; i >= 0; i--) { | |
450 | buf[i] = addr & 0xff; | |
451 | addr >>= 8; | |
452 | } | |
453 | ||
454 | return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width); | |
455 | } | |
456 | ||
b199489d HS |
457 | /* |
458 | * Erase an address range on the nor chip. The address range may extend | |
459 | * one or more erase sectors. Return an error is there is a problem erasing. | |
460 | */ | |
461 | static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) | |
462 | { | |
463 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
464 | u32 addr, len; | |
465 | uint32_t rem; | |
466 | int ret; | |
467 | ||
468 | dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, | |
469 | (long long)instr->len); | |
470 | ||
471 | div_u64_rem(instr->len, mtd->erasesize, &rem); | |
472 | if (rem) | |
473 | return -EINVAL; | |
474 | ||
475 | addr = instr->addr; | |
476 | len = instr->len; | |
477 | ||
478 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE); | |
479 | if (ret) | |
480 | return ret; | |
481 | ||
482 | /* whole-chip erase? */ | |
e99ca98f | 483 | if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { |
09b6a377 FS |
484 | unsigned long timeout; |
485 | ||
05241aea BN |
486 | write_enable(nor); |
487 | ||
b199489d HS |
488 | if (erase_chip(nor)) { |
489 | ret = -EIO; | |
490 | goto erase_err; | |
491 | } | |
492 | ||
09b6a377 FS |
493 | /* |
494 | * Scale the timeout linearly with the size of the flash, with | |
495 | * a minimum calibrated to an old 2MB flash. We could try to | |
496 | * pull these from CFI/SFDP, but these values should be good | |
497 | * enough for now. | |
498 | */ | |
499 | timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, | |
500 | CHIP_ERASE_2MB_READY_WAIT_JIFFIES * | |
501 | (unsigned long)(mtd->size / SZ_2M)); | |
502 | ret = spi_nor_wait_till_ready_with_timeout(nor, timeout); | |
dfa9c0cb BN |
503 | if (ret) |
504 | goto erase_err; | |
505 | ||
b199489d | 506 | /* REVISIT in some cases we could speed up erasing large regions |
b02e7f3e | 507 | * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up |
b199489d HS |
508 | * to use "small sector erase", but that's not always optimal. |
509 | */ | |
510 | ||
511 | /* "sector"-at-a-time erase */ | |
512 | } else { | |
513 | while (len) { | |
05241aea BN |
514 | write_enable(nor); |
515 | ||
c67cbb83 BN |
516 | ret = spi_nor_erase_sector(nor, addr); |
517 | if (ret) | |
b199489d | 518 | goto erase_err; |
b199489d HS |
519 | |
520 | addr += mtd->erasesize; | |
521 | len -= mtd->erasesize; | |
dfa9c0cb BN |
522 | |
523 | ret = spi_nor_wait_till_ready(nor); | |
524 | if (ret) | |
525 | goto erase_err; | |
b199489d HS |
526 | } |
527 | } | |
528 | ||
05241aea BN |
529 | write_disable(nor); |
530 | ||
d6af2694 | 531 | erase_err: |
b199489d HS |
532 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); |
533 | ||
d6af2694 | 534 | instr->state = ret ? MTD_ERASE_FAILED : MTD_ERASE_DONE; |
b199489d HS |
535 | mtd_erase_callback(instr); |
536 | ||
537 | return ret; | |
b199489d HS |
538 | } |
539 | ||
62593cf4 BN |
540 | static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs, |
541 | uint64_t *len) | |
542 | { | |
543 | struct mtd_info *mtd = &nor->mtd; | |
544 | u8 mask = SR_BP2 | SR_BP1 | SR_BP0; | |
545 | int shift = ffs(mask) - 1; | |
546 | int pow; | |
547 | ||
548 | if (!(sr & mask)) { | |
549 | /* No protection */ | |
550 | *ofs = 0; | |
551 | *len = 0; | |
552 | } else { | |
553 | pow = ((sr & mask) ^ mask) >> shift; | |
554 | *len = mtd->size >> pow; | |
3dd8012a BN |
555 | if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB) |
556 | *ofs = 0; | |
557 | else | |
558 | *ofs = mtd->size - *len; | |
62593cf4 BN |
559 | } |
560 | } | |
561 | ||
562 | /* | |
f8860802 BN |
563 | * Return 1 if the entire region is locked (if @locked is true) or unlocked (if |
564 | * @locked is false); 0 otherwise | |
62593cf4 | 565 | */ |
f8860802 BN |
566 | static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, |
567 | u8 sr, bool locked) | |
62593cf4 BN |
568 | { |
569 | loff_t lock_offs; | |
570 | uint64_t lock_len; | |
571 | ||
f8860802 BN |
572 | if (!len) |
573 | return 1; | |
574 | ||
62593cf4 BN |
575 | stm_get_locked_range(nor, sr, &lock_offs, &lock_len); |
576 | ||
f8860802 BN |
577 | if (locked) |
578 | /* Requested range is a sub-range of locked range */ | |
579 | return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); | |
580 | else | |
581 | /* Requested range does not overlap with locked range */ | |
582 | return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs); | |
583 | } | |
584 | ||
585 | static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, | |
586 | u8 sr) | |
587 | { | |
588 | return stm_check_lock_status_sr(nor, ofs, len, sr, true); | |
589 | } | |
590 | ||
591 | static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, | |
592 | u8 sr) | |
593 | { | |
594 | return stm_check_lock_status_sr(nor, ofs, len, sr, false); | |
62593cf4 BN |
595 | } |
596 | ||
597 | /* | |
598 | * Lock a region of the flash. Compatible with ST Micro and similar flash. | |
3dd8012a | 599 | * Supports the block protection bits BP{0,1,2} in the status register |
62593cf4 | 600 | * (SR). Does not support these features found in newer SR bitfields: |
62593cf4 BN |
601 | * - SEC: sector/block protect - only handle SEC=0 (block protect) |
602 | * - CMP: complement protect - only support CMP=0 (range is not complemented) | |
603 | * | |
3dd8012a BN |
604 | * Support for the following is provided conditionally for some flash: |
605 | * - TB: top/bottom protect | |
606 | * | |
62593cf4 BN |
607 | * Sample table portion for 8MB flash (Winbond w25q64fw): |
608 | * | |
609 | * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion | |
610 | * -------------------------------------------------------------------------- | |
611 | * X | X | 0 | 0 | 0 | NONE | NONE | |
612 | * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 | |
613 | * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 | |
614 | * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 | |
615 | * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 | |
616 | * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 | |
617 | * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 | |
618 | * X | X | 1 | 1 | 1 | 8 MB | ALL | |
3dd8012a BN |
619 | * ------|-------|-------|-------|-------|---------------|------------------- |
620 | * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64 | |
621 | * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32 | |
622 | * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16 | |
623 | * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8 | |
624 | * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4 | |
625 | * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2 | |
62593cf4 BN |
626 | * |
627 | * Returns negative on errors, 0 on success. | |
628 | */ | |
8cc7f33a | 629 | static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) |
b199489d | 630 | { |
19763671 | 631 | struct mtd_info *mtd = &nor->mtd; |
f49289ce | 632 | int status_old, status_new; |
62593cf4 BN |
633 | u8 mask = SR_BP2 | SR_BP1 | SR_BP0; |
634 | u8 shift = ffs(mask) - 1, pow, val; | |
f8860802 | 635 | loff_t lock_len; |
3dd8012a BN |
636 | bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; |
637 | bool use_top; | |
32321e95 | 638 | int ret; |
b199489d | 639 | |
b199489d | 640 | status_old = read_sr(nor); |
f49289ce FE |
641 | if (status_old < 0) |
642 | return status_old; | |
b199489d | 643 | |
f8860802 BN |
644 | /* If nothing in our range is unlocked, we don't need to do anything */ |
645 | if (stm_is_locked_sr(nor, ofs, len, status_old)) | |
646 | return 0; | |
647 | ||
3dd8012a BN |
648 | /* If anything below us is unlocked, we can't use 'bottom' protection */ |
649 | if (!stm_is_locked_sr(nor, 0, ofs, status_old)) | |
650 | can_be_bottom = false; | |
651 | ||
f8860802 BN |
652 | /* If anything above us is unlocked, we can't use 'top' protection */ |
653 | if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len), | |
654 | status_old)) | |
3dd8012a BN |
655 | can_be_top = false; |
656 | ||
657 | if (!can_be_bottom && !can_be_top) | |
f8860802 BN |
658 | return -EINVAL; |
659 | ||
3dd8012a BN |
660 | /* Prefer top, if both are valid */ |
661 | use_top = can_be_top; | |
662 | ||
f8860802 | 663 | /* lock_len: length of region that should end up locked */ |
3dd8012a BN |
664 | if (use_top) |
665 | lock_len = mtd->size - ofs; | |
666 | else | |
667 | lock_len = ofs + len; | |
62593cf4 BN |
668 | |
669 | /* | |
670 | * Need smallest pow such that: | |
671 | * | |
672 | * 1 / (2^pow) <= (len / size) | |
673 | * | |
674 | * so (assuming power-of-2 size) we do: | |
675 | * | |
676 | * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) | |
677 | */ | |
f8860802 | 678 | pow = ilog2(mtd->size) - ilog2(lock_len); |
62593cf4 BN |
679 | val = mask - (pow << shift); |
680 | if (val & ~mask) | |
681 | return -EINVAL; | |
682 | /* Don't "lock" with no region! */ | |
683 | if (!(val & mask)) | |
684 | return -EINVAL; | |
685 | ||
3dd8012a | 686 | status_new = (status_old & ~mask & ~SR_TB) | val; |
b199489d | 687 | |
47b8edbf BN |
688 | /* Disallow further writes if WP pin is asserted */ |
689 | status_new |= SR_SRWD; | |
690 | ||
3dd8012a BN |
691 | if (!use_top) |
692 | status_new |= SR_TB; | |
693 | ||
4c0dba44 BN |
694 | /* Don't bother if they're the same */ |
695 | if (status_new == status_old) | |
696 | return 0; | |
697 | ||
b199489d | 698 | /* Only modify protection if it will not unlock other areas */ |
4c0dba44 | 699 | if ((status_new & mask) < (status_old & mask)) |
62593cf4 | 700 | return -EINVAL; |
b199489d | 701 | |
62593cf4 | 702 | write_enable(nor); |
32321e95 EG |
703 | ret = write_sr(nor, status_new); |
704 | if (ret) | |
705 | return ret; | |
706 | return spi_nor_wait_till_ready(nor); | |
b199489d HS |
707 | } |
708 | ||
62593cf4 BN |
709 | /* |
710 | * Unlock a region of the flash. See stm_lock() for more info | |
711 | * | |
712 | * Returns negative on errors, 0 on success. | |
713 | */ | |
8cc7f33a | 714 | static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) |
b199489d | 715 | { |
19763671 | 716 | struct mtd_info *mtd = &nor->mtd; |
f49289ce | 717 | int status_old, status_new; |
62593cf4 BN |
718 | u8 mask = SR_BP2 | SR_BP1 | SR_BP0; |
719 | u8 shift = ffs(mask) - 1, pow, val; | |
f8860802 | 720 | loff_t lock_len; |
3dd8012a BN |
721 | bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; |
722 | bool use_top; | |
32321e95 | 723 | int ret; |
b199489d | 724 | |
b199489d | 725 | status_old = read_sr(nor); |
f49289ce FE |
726 | if (status_old < 0) |
727 | return status_old; | |
b199489d | 728 | |
f8860802 BN |
729 | /* If nothing in our range is locked, we don't need to do anything */ |
730 | if (stm_is_unlocked_sr(nor, ofs, len, status_old)) | |
731 | return 0; | |
732 | ||
733 | /* If anything below us is locked, we can't use 'top' protection */ | |
734 | if (!stm_is_unlocked_sr(nor, 0, ofs, status_old)) | |
3dd8012a BN |
735 | can_be_top = false; |
736 | ||
737 | /* If anything above us is locked, we can't use 'bottom' protection */ | |
738 | if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len), | |
739 | status_old)) | |
740 | can_be_bottom = false; | |
741 | ||
742 | if (!can_be_bottom && !can_be_top) | |
62593cf4 | 743 | return -EINVAL; |
b199489d | 744 | |
3dd8012a BN |
745 | /* Prefer top, if both are valid */ |
746 | use_top = can_be_top; | |
747 | ||
f8860802 | 748 | /* lock_len: length of region that should remain locked */ |
3dd8012a BN |
749 | if (use_top) |
750 | lock_len = mtd->size - (ofs + len); | |
751 | else | |
752 | lock_len = ofs; | |
f8860802 | 753 | |
62593cf4 BN |
754 | /* |
755 | * Need largest pow such that: | |
756 | * | |
757 | * 1 / (2^pow) >= (len / size) | |
758 | * | |
759 | * so (assuming power-of-2 size) we do: | |
760 | * | |
761 | * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) | |
762 | */ | |
f8860802 BN |
763 | pow = ilog2(mtd->size) - order_base_2(lock_len); |
764 | if (lock_len == 0) { | |
62593cf4 BN |
765 | val = 0; /* fully unlocked */ |
766 | } else { | |
767 | val = mask - (pow << shift); | |
768 | /* Some power-of-two sizes are not supported */ | |
769 | if (val & ~mask) | |
770 | return -EINVAL; | |
b199489d HS |
771 | } |
772 | ||
3dd8012a | 773 | status_new = (status_old & ~mask & ~SR_TB) | val; |
62593cf4 | 774 | |
47b8edbf | 775 | /* Don't protect status register if we're fully unlocked */ |
06586204 | 776 | if (lock_len == 0) |
47b8edbf BN |
777 | status_new &= ~SR_SRWD; |
778 | ||
3dd8012a BN |
779 | if (!use_top) |
780 | status_new |= SR_TB; | |
781 | ||
4c0dba44 BN |
782 | /* Don't bother if they're the same */ |
783 | if (status_new == status_old) | |
784 | return 0; | |
785 | ||
62593cf4 | 786 | /* Only modify protection if it will not lock other areas */ |
4c0dba44 | 787 | if ((status_new & mask) > (status_old & mask)) |
62593cf4 BN |
788 | return -EINVAL; |
789 | ||
790 | write_enable(nor); | |
32321e95 EG |
791 | ret = write_sr(nor, status_new); |
792 | if (ret) | |
793 | return ret; | |
794 | return spi_nor_wait_till_ready(nor); | |
8cc7f33a BN |
795 | } |
796 | ||
5bf0e69b BN |
797 | /* |
798 | * Check if a region of the flash is (completely) locked. See stm_lock() for | |
799 | * more info. | |
800 | * | |
801 | * Returns 1 if entire region is locked, 0 if any portion is unlocked, and | |
802 | * negative on errors. | |
803 | */ | |
804 | static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) | |
805 | { | |
806 | int status; | |
807 | ||
808 | status = read_sr(nor); | |
809 | if (status < 0) | |
810 | return status; | |
811 | ||
812 | return stm_is_locked_sr(nor, ofs, len, status); | |
813 | } | |
814 | ||
8cc7f33a BN |
815 | static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
816 | { | |
817 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
818 | int ret; | |
819 | ||
820 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK); | |
821 | if (ret) | |
822 | return ret; | |
823 | ||
824 | ret = nor->flash_lock(nor, ofs, len); | |
825 | ||
b199489d HS |
826 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK); |
827 | return ret; | |
828 | } | |
829 | ||
8cc7f33a BN |
830 | static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
831 | { | |
832 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
833 | int ret; | |
834 | ||
835 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK); | |
836 | if (ret) | |
837 | return ret; | |
838 | ||
839 | ret = nor->flash_unlock(nor, ofs, len); | |
840 | ||
841 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK); | |
842 | return ret; | |
843 | } | |
844 | ||
5bf0e69b BN |
845 | static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
846 | { | |
847 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
848 | int ret; | |
849 | ||
850 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK); | |
851 | if (ret) | |
852 | return ret; | |
853 | ||
854 | ret = nor->flash_is_locked(nor, ofs, len); | |
855 | ||
856 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK); | |
857 | return ret; | |
858 | } | |
859 | ||
09ffafb6 | 860 | /* Used when the "_ext_id" is two bytes at most */ |
b199489d | 861 | #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
09ffafb6 HS |
862 | .id = { \ |
863 | ((_jedec_id) >> 16) & 0xff, \ | |
864 | ((_jedec_id) >> 8) & 0xff, \ | |
865 | (_jedec_id) & 0xff, \ | |
866 | ((_ext_id) >> 8) & 0xff, \ | |
867 | (_ext_id) & 0xff, \ | |
868 | }, \ | |
869 | .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ | |
b199489d HS |
870 | .sector_size = (_sector_size), \ |
871 | .n_sectors = (_n_sectors), \ | |
872 | .page_size = 256, \ | |
06bb6f5a | 873 | .flags = (_flags), |
b199489d | 874 | |
6d7604e5 | 875 | #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
6d7604e5 HS |
876 | .id = { \ |
877 | ((_jedec_id) >> 16) & 0xff, \ | |
878 | ((_jedec_id) >> 8) & 0xff, \ | |
879 | (_jedec_id) & 0xff, \ | |
880 | ((_ext_id) >> 16) & 0xff, \ | |
881 | ((_ext_id) >> 8) & 0xff, \ | |
882 | (_ext_id) & 0xff, \ | |
883 | }, \ | |
884 | .id_len = 6, \ | |
885 | .sector_size = (_sector_size), \ | |
886 | .n_sectors = (_n_sectors), \ | |
887 | .page_size = 256, \ | |
06bb6f5a | 888 | .flags = (_flags), |
6d7604e5 | 889 | |
b199489d | 890 | #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \ |
b199489d HS |
891 | .sector_size = (_sector_size), \ |
892 | .n_sectors = (_n_sectors), \ | |
893 | .page_size = (_page_size), \ | |
894 | .addr_width = (_addr_width), \ | |
06bb6f5a | 895 | .flags = (_flags), |
b199489d | 896 | |
e99ca98f RRD |
897 | #define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \ |
898 | .id = { \ | |
899 | ((_jedec_id) >> 16) & 0xff, \ | |
900 | ((_jedec_id) >> 8) & 0xff, \ | |
901 | (_jedec_id) & 0xff \ | |
902 | }, \ | |
903 | .id_len = 3, \ | |
904 | .sector_size = (8*_page_size), \ | |
905 | .n_sectors = (_n_sectors), \ | |
906 | .page_size = _page_size, \ | |
907 | .addr_width = 3, \ | |
908 | .flags = SPI_NOR_NO_FR | SPI_S3AN, | |
909 | ||
b199489d HS |
910 | /* NOTE: double check command sets and memory organization when you add |
911 | * more nor chips. This current list focusses on newer chips, which | |
912 | * have been converging on command sets which including JEDEC ID. | |
c19900ed RM |
913 | * |
914 | * All newly added entries should describe *hardware* and should use SECT_4K | |
915 | * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage | |
916 | * scenarios excluding small sectors there is config option that can be | |
917 | * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS. | |
918 | * For historical (and compatibility) reasons (before we got above config) some | |
919 | * old entries may be missing 4K flag. | |
b199489d | 920 | */ |
06bb6f5a | 921 | static const struct flash_info spi_nor_ids[] = { |
b199489d HS |
922 | /* Atmel -- some are (confusingly) marketed as "DataFlash" */ |
923 | { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) }, | |
924 | { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) }, | |
925 | ||
926 | { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) }, | |
b08618c9 | 927 | { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, |
b199489d HS |
928 | { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, |
929 | { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) }, | |
930 | ||
931 | { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) }, | |
932 | { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, | |
933 | { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) }, | |
934 | { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, | |
935 | ||
936 | { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, | |
937 | ||
938 | /* EON -- en25xxx */ | |
939 | { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, | |
940 | { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, | |
941 | { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) }, | |
942 | { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) }, | |
943 | { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, | |
a41595b3 | 944 | { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) }, |
b199489d | 945 | { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) }, |
c19900ed | 946 | { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, |
b199489d HS |
947 | |
948 | /* ESMT */ | |
fcf690a2 | 949 | { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) }, |
ca1fa1a8 P |
950 | { "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) }, |
951 | { "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) }, | |
b199489d HS |
952 | |
953 | /* Everspin */ | |
954 | { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
955 | { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
edd0c8f4 | 956 | { "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, |
b199489d | 957 | |
ce56ce7d RL |
958 | /* Fujitsu */ |
959 | { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) }, | |
960 | ||
b199489d | 961 | /* GigaDevice */ |
e9cf64de KD |
962 | { |
963 | "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32, | |
964 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | | |
965 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) | |
966 | }, | |
595f0e10 BN |
967 | { |
968 | "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, | |
969 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | | |
970 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) | |
971 | }, | |
972 | { | |
973 | "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, | |
974 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | | |
975 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) | |
976 | }, | |
977 | { | |
978 | "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128, | |
979 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | | |
980 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) | |
981 | }, | |
982 | { | |
983 | "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, | |
984 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | | |
985 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) | |
986 | }, | |
b199489d HS |
987 | |
988 | /* Intel/Numonyx -- xxxs33b */ | |
989 | { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) }, | |
990 | { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, | |
991 | { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, | |
992 | ||
b79c332f GJ |
993 | /* ISSI */ |
994 | { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) }, | |
995 | ||
b199489d | 996 | /* Macronix */ |
660b5b07 | 997 | { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) }, |
b199489d HS |
998 | { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, |
999 | { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, | |
1000 | { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, | |
1001 | { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, | |
0501f2e5 | 1002 | { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) }, |
b199489d | 1003 | { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) }, |
0501f2e5 | 1004 | { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) }, |
9f3cd453 AK |
1005 | { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) }, |
1006 | { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) }, | |
1007 | { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) }, | |
81a1209c | 1008 | { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) }, |
b199489d HS |
1009 | { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, |
1010 | { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, | |
d7c9ade2 | 1011 | { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
b0fcb4b4 | 1012 | { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) }, |
b199489d | 1013 | { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, |
d7c9ade2 | 1014 | { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
af18ba48 | 1015 | { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, |
ce398a81 | 1016 | { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
b199489d HS |
1017 | { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) }, |
1018 | ||
1019 | /* Micron */ | |
61e46118 | 1020 | { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) }, |
548cd3ab | 1021 | { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, |
f9bcb6dc | 1022 | { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, |
0db7fae2 | 1023 | { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, |
2a06c7b1 | 1024 | { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, |
4607777c EG |
1025 | { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, |
1026 | { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, | |
d7c9ade2 | 1027 | { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
835ed7bf | 1028 | { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, |
548cd3ab BH |
1029 | { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, |
1030 | { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, | |
193fb3c1 | 1031 | { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, |
1032 | { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, | |
b199489d HS |
1033 | |
1034 | /* PMC */ | |
1035 | { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) }, | |
1036 | { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) }, | |
1037 | { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) }, | |
1038 | ||
1039 | /* Spansion -- single (large) sector size only, at least | |
1040 | * for the chips listed here (without boot sectors). | |
1041 | */ | |
9ab86995 | 1042 | { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
0f12a27b | 1043 | { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
b199489d HS |
1044 | { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) }, |
1045 | { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
1046 | { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
1047 | { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, | |
1048 | { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, | |
1049 | { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, | |
4287916d | 1050 | { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
c1752086 JG |
1051 | { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
1052 | { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
b199489d HS |
1053 | { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, |
1054 | { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, | |
1055 | { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, | |
1056 | { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, | |
1057 | { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, | |
7c748f57 | 1058 | { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
adf508c3 JE |
1059 | { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
1060 | { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
b199489d | 1061 | { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, |
c0826679 | 1062 | { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
c19900ed | 1063 | { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) }, |
413780d7 | 1064 | { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) }, |
aada20cd | 1065 | { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) }, |
022a400f | 1066 | { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) }, |
d8b494a3 | 1067 | { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, |
b199489d HS |
1068 | |
1069 | /* SST -- large erase sizes are "overlays", "sectors" are 4K */ | |
1070 | { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, | |
1071 | { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, | |
1072 | { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, | |
1073 | { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, | |
1074 | { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, | |
1075 | { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, | |
1076 | { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, | |
1077 | { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, | |
a1d97ef9 | 1078 | { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) }, |
c887be71 | 1079 | { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) }, |
b199489d | 1080 | { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, |
f02985b7 | 1081 | { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, |
b199489d HS |
1082 | |
1083 | /* ST Microelectronics -- newer production may have feature updates */ | |
1084 | { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) }, | |
1085 | { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) }, | |
1086 | { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) }, | |
1087 | { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) }, | |
1088 | { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) }, | |
1089 | { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) }, | |
1090 | { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) }, | |
1091 | { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) }, | |
1092 | { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) }, | |
b199489d HS |
1093 | |
1094 | { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) }, | |
1095 | { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) }, | |
1096 | { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) }, | |
1097 | { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) }, | |
1098 | { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) }, | |
1099 | { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) }, | |
1100 | { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) }, | |
1101 | { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) }, | |
1102 | { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) }, | |
1103 | ||
1104 | { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) }, | |
1105 | { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) }, | |
1106 | { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) }, | |
1107 | ||
1108 | { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) }, | |
1109 | { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) }, | |
1110 | { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) }, | |
1111 | ||
1112 | { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) }, | |
1113 | { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) }, | |
1114 | { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) }, | |
1115 | { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) }, | |
1116 | { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) }, | |
f2fabe16 | 1117 | { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) }, |
b199489d HS |
1118 | |
1119 | /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ | |
40d19ab6 | 1120 | { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) }, |
b199489d HS |
1121 | { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, |
1122 | { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, | |
1123 | { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, | |
1124 | { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, | |
1125 | { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, | |
1126 | { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, | |
34fc99db AK |
1127 | { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) }, |
1128 | { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) }, | |
1129 | { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) }, | |
b199489d | 1130 | { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, |
9648388f BN |
1131 | { |
1132 | "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, | |
1133 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | | |
1134 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) | |
1135 | }, | |
b199489d HS |
1136 | { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, |
1137 | { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, | |
9648388f BN |
1138 | { |
1139 | "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, | |
1140 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | | |
1141 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) | |
1142 | }, | |
1143 | { | |
1144 | "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, | |
1145 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | | |
1146 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) | |
1147 | }, | |
b199489d HS |
1148 | { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, |
1149 | { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, | |
1150 | { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, | |
d7c9ade2 | 1151 | { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
0cbef932 BH |
1152 | { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024, |
1153 | SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) }, | |
b199489d HS |
1154 | |
1155 | /* Catalyst / On Semiconductor -- non-JEDEC */ | |
1156 | { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
1157 | { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
1158 | { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
1159 | { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
1160 | { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
e99ca98f RRD |
1161 | |
1162 | /* Xilinx S3AN Internal Flash */ | |
1163 | { "3S50AN", S3AN_INFO(0x1f2200, 64, 264) }, | |
1164 | { "3S200AN", S3AN_INFO(0x1f2400, 256, 264) }, | |
1165 | { "3S400AN", S3AN_INFO(0x1f2400, 256, 264) }, | |
1166 | { "3S700AN", S3AN_INFO(0x1f2500, 512, 264) }, | |
1167 | { "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) }, | |
b199489d HS |
1168 | { }, |
1169 | }; | |
1170 | ||
06bb6f5a | 1171 | static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) |
b199489d HS |
1172 | { |
1173 | int tmp; | |
09ffafb6 | 1174 | u8 id[SPI_NOR_MAX_ID_LEN]; |
06bb6f5a | 1175 | const struct flash_info *info; |
b199489d | 1176 | |
09ffafb6 | 1177 | tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); |
b199489d | 1178 | if (tmp < 0) { |
20625dfe | 1179 | dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp); |
b199489d HS |
1180 | return ERR_PTR(tmp); |
1181 | } | |
b199489d HS |
1182 | |
1183 | for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) { | |
06bb6f5a | 1184 | info = &spi_nor_ids[tmp]; |
09ffafb6 HS |
1185 | if (info->id_len) { |
1186 | if (!memcmp(info->id, id, info->id_len)) | |
b199489d HS |
1187 | return &spi_nor_ids[tmp]; |
1188 | } | |
1189 | } | |
9b9f1033 | 1190 | dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n", |
09ffafb6 | 1191 | id[0], id[1], id[2]); |
b199489d HS |
1192 | return ERR_PTR(-ENODEV); |
1193 | } | |
1194 | ||
b199489d HS |
1195 | static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, |
1196 | size_t *retlen, u_char *buf) | |
1197 | { | |
1198 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
1199 | int ret; | |
1200 | ||
1201 | dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); | |
1202 | ||
1203 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ); | |
1204 | if (ret) | |
1205 | return ret; | |
1206 | ||
26f9bcad | 1207 | while (len) { |
e99ca98f RRD |
1208 | loff_t addr = from; |
1209 | ||
1210 | if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT) | |
1211 | addr = spi_nor_s3an_addr_convert(nor, addr); | |
1212 | ||
1213 | ret = nor->read(nor, addr, len, buf); | |
26f9bcad MS |
1214 | if (ret == 0) { |
1215 | /* We shouldn't see 0-length reads */ | |
1216 | ret = -EIO; | |
1217 | goto read_err; | |
1218 | } | |
1219 | if (ret < 0) | |
1220 | goto read_err; | |
b199489d | 1221 | |
26f9bcad MS |
1222 | WARN_ON(ret > len); |
1223 | *retlen += ret; | |
1224 | buf += ret; | |
1225 | from += ret; | |
1226 | len -= ret; | |
1227 | } | |
1228 | ret = 0; | |
59451e12 | 1229 | |
26f9bcad MS |
1230 | read_err: |
1231 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ); | |
1232 | return ret; | |
b199489d HS |
1233 | } |
1234 | ||
1235 | static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, | |
1236 | size_t *retlen, const u_char *buf) | |
1237 | { | |
1238 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
1239 | size_t actual; | |
1240 | int ret; | |
1241 | ||
1242 | dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); | |
1243 | ||
1244 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE); | |
1245 | if (ret) | |
1246 | return ret; | |
1247 | ||
b199489d HS |
1248 | write_enable(nor); |
1249 | ||
1250 | nor->sst_write_second = false; | |
1251 | ||
1252 | actual = to % 2; | |
1253 | /* Start write from odd address. */ | |
1254 | if (actual) { | |
b02e7f3e | 1255 | nor->program_opcode = SPINOR_OP_BP; |
b199489d HS |
1256 | |
1257 | /* write one byte. */ | |
2dd087b1 | 1258 | ret = nor->write(nor, to, 1, buf); |
0bad7b93 MS |
1259 | if (ret < 0) |
1260 | goto sst_write_err; | |
1261 | WARN(ret != 1, "While writing 1 byte written %i bytes\n", | |
1262 | (int)ret); | |
b94ed087 | 1263 | ret = spi_nor_wait_till_ready(nor); |
b199489d | 1264 | if (ret) |
0bad7b93 | 1265 | goto sst_write_err; |
b199489d HS |
1266 | } |
1267 | to += actual; | |
1268 | ||
1269 | /* Write out most of the data here. */ | |
1270 | for (; actual < len - 1; actual += 2) { | |
b02e7f3e | 1271 | nor->program_opcode = SPINOR_OP_AAI_WP; |
b199489d HS |
1272 | |
1273 | /* write two bytes. */ | |
2dd087b1 | 1274 | ret = nor->write(nor, to, 2, buf + actual); |
0bad7b93 MS |
1275 | if (ret < 0) |
1276 | goto sst_write_err; | |
1277 | WARN(ret != 2, "While writing 2 bytes written %i bytes\n", | |
1278 | (int)ret); | |
b94ed087 | 1279 | ret = spi_nor_wait_till_ready(nor); |
b199489d | 1280 | if (ret) |
0bad7b93 | 1281 | goto sst_write_err; |
b199489d HS |
1282 | to += 2; |
1283 | nor->sst_write_second = true; | |
1284 | } | |
1285 | nor->sst_write_second = false; | |
1286 | ||
1287 | write_disable(nor); | |
b94ed087 | 1288 | ret = spi_nor_wait_till_ready(nor); |
b199489d | 1289 | if (ret) |
0bad7b93 | 1290 | goto sst_write_err; |
b199489d HS |
1291 | |
1292 | /* Write out trailing byte if it exists. */ | |
1293 | if (actual != len) { | |
1294 | write_enable(nor); | |
1295 | ||
b02e7f3e | 1296 | nor->program_opcode = SPINOR_OP_BP; |
2dd087b1 | 1297 | ret = nor->write(nor, to, 1, buf + actual); |
0bad7b93 MS |
1298 | if (ret < 0) |
1299 | goto sst_write_err; | |
1300 | WARN(ret != 1, "While writing 1 byte written %i bytes\n", | |
1301 | (int)ret); | |
b94ed087 | 1302 | ret = spi_nor_wait_till_ready(nor); |
b199489d | 1303 | if (ret) |
0bad7b93 | 1304 | goto sst_write_err; |
b199489d | 1305 | write_disable(nor); |
2dd087b1 | 1306 | actual += 1; |
b199489d | 1307 | } |
0bad7b93 | 1308 | sst_write_err: |
2dd087b1 | 1309 | *retlen += actual; |
b199489d HS |
1310 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE); |
1311 | return ret; | |
1312 | } | |
1313 | ||
1314 | /* | |
1315 | * Write an address range to the nor chip. Data must be written in | |
1316 | * FLASH_PAGESIZE chunks. The address range may be any size provided | |
1317 | * it is within the physical boundaries. | |
1318 | */ | |
1319 | static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, | |
1320 | size_t *retlen, const u_char *buf) | |
1321 | { | |
1322 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
e5d05cbd MS |
1323 | size_t page_offset, page_remain, i; |
1324 | ssize_t ret; | |
b199489d HS |
1325 | |
1326 | dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); | |
1327 | ||
1328 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE); | |
1329 | if (ret) | |
1330 | return ret; | |
1331 | ||
e5d05cbd MS |
1332 | for (i = 0; i < len; ) { |
1333 | ssize_t written; | |
e99ca98f | 1334 | loff_t addr = to + i; |
b199489d | 1335 | |
e99ca98f RRD |
1336 | /* |
1337 | * If page_size is a power of two, the offset can be quickly | |
1338 | * calculated with an AND operation. On the other cases we | |
1339 | * need to do a modulus operation (more expensive). | |
1340 | * Power of two numbers have only one bit set and we can use | |
1341 | * the instruction hweight32 to detect if we need to do a | |
1342 | * modulus (do_div()) or not. | |
1343 | */ | |
1344 | if (hweight32(nor->page_size) == 1) { | |
1345 | page_offset = addr & (nor->page_size - 1); | |
1346 | } else { | |
1347 | uint64_t aux = addr; | |
b199489d | 1348 | |
e99ca98f RRD |
1349 | page_offset = do_div(aux, nor->page_size); |
1350 | } | |
b199489d | 1351 | /* the size of data remaining on the first page */ |
e5d05cbd MS |
1352 | page_remain = min_t(size_t, |
1353 | nor->page_size - page_offset, len - i); | |
1354 | ||
e99ca98f RRD |
1355 | if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT) |
1356 | addr = spi_nor_s3an_addr_convert(nor, addr); | |
1357 | ||
e5d05cbd | 1358 | write_enable(nor); |
e99ca98f | 1359 | ret = nor->write(nor, addr, page_remain, buf + i); |
0bad7b93 MS |
1360 | if (ret < 0) |
1361 | goto write_err; | |
e5d05cbd | 1362 | written = ret; |
1d61dcb3 | 1363 | |
e5d05cbd MS |
1364 | ret = spi_nor_wait_till_ready(nor); |
1365 | if (ret) | |
1366 | goto write_err; | |
1367 | *retlen += written; | |
1368 | i += written; | |
1369 | if (written != page_remain) { | |
1370 | dev_err(nor->dev, | |
1371 | "While writing %zu bytes written %zd bytes\n", | |
1372 | page_remain, written); | |
1373 | ret = -EIO; | |
1374 | goto write_err; | |
b199489d HS |
1375 | } |
1376 | } | |
1377 | ||
1378 | write_err: | |
1379 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE); | |
1d61dcb3 | 1380 | return ret; |
b199489d HS |
1381 | } |
1382 | ||
1383 | static int macronix_quad_enable(struct spi_nor *nor) | |
1384 | { | |
1385 | int ret, val; | |
1386 | ||
1387 | val = read_sr(nor); | |
f49289ce FE |
1388 | if (val < 0) |
1389 | return val; | |
32c90f16 CP |
1390 | if (val & SR_QUAD_EN_MX) |
1391 | return 0; | |
1392 | ||
b199489d HS |
1393 | write_enable(nor); |
1394 | ||
fd725234 | 1395 | write_sr(nor, val | SR_QUAD_EN_MX); |
b199489d | 1396 | |
05d090f0 DC |
1397 | ret = spi_nor_wait_till_ready(nor); |
1398 | if (ret) | |
1399 | return ret; | |
b199489d HS |
1400 | |
1401 | ret = read_sr(nor); | |
1402 | if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) { | |
1403 | dev_err(nor->dev, "Macronix Quad bit not set\n"); | |
1404 | return -EINVAL; | |
1405 | } | |
1406 | ||
1407 | return 0; | |
1408 | } | |
1409 | ||
1410 | /* | |
1411 | * Write status Register and configuration register with 2 bytes | |
1412 | * The first byte will be written to the status register, while the | |
1413 | * second byte will be written to the configuration register. | |
5d708ecc | 1414 | * Return negative if error occurred. |
b199489d HS |
1415 | */ |
1416 | static int write_sr_cr(struct spi_nor *nor, u16 val) | |
1417 | { | |
1418 | nor->cmd_buf[0] = val & 0xff; | |
1419 | nor->cmd_buf[1] = (val >> 8); | |
1420 | ||
f9f3ce83 | 1421 | return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2); |
b199489d HS |
1422 | } |
1423 | ||
1424 | static int spansion_quad_enable(struct spi_nor *nor) | |
1425 | { | |
1426 | int ret; | |
1427 | int quad_en = CR_QUAD_EN_SPAN << 8; | |
1428 | ||
1429 | write_enable(nor); | |
1430 | ||
1431 | ret = write_sr_cr(nor, quad_en); | |
1432 | if (ret < 0) { | |
1433 | dev_err(nor->dev, | |
1434 | "error while writing configuration register\n"); | |
1435 | return -EINVAL; | |
1436 | } | |
1437 | ||
807c1625 JE |
1438 | ret = spi_nor_wait_till_ready(nor); |
1439 | if (ret) { | |
1440 | dev_err(nor->dev, | |
1441 | "timeout while writing configuration register\n"); | |
1442 | return ret; | |
1443 | } | |
1444 | ||
b199489d HS |
1445 | /* read back and check it */ |
1446 | ret = read_cr(nor); | |
1447 | if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) { | |
1448 | dev_err(nor->dev, "Spansion Quad bit not set\n"); | |
1449 | return -EINVAL; | |
1450 | } | |
1451 | ||
1452 | return 0; | |
1453 | } | |
1454 | ||
b199489d HS |
1455 | static int spi_nor_check(struct spi_nor *nor) |
1456 | { | |
1457 | if (!nor->dev || !nor->read || !nor->write || | |
c67cbb83 | 1458 | !nor->read_reg || !nor->write_reg) { |
b199489d HS |
1459 | pr_err("spi-nor: please fill all the necessary fields!\n"); |
1460 | return -EINVAL; | |
1461 | } | |
1462 | ||
b199489d HS |
1463 | return 0; |
1464 | } | |
1465 | ||
e99ca98f RRD |
1466 | static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor) |
1467 | { | |
1468 | int ret; | |
1469 | u8 val; | |
1470 | ||
1471 | ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1); | |
1472 | if (ret < 0) { | |
1473 | dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret); | |
1474 | return ret; | |
1475 | } | |
1476 | ||
1477 | nor->erase_opcode = SPINOR_OP_XSE; | |
1478 | nor->program_opcode = SPINOR_OP_XPP; | |
1479 | nor->read_opcode = SPINOR_OP_READ; | |
1480 | nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; | |
1481 | ||
1482 | /* | |
1483 | * This flashes have a page size of 264 or 528 bytes (known as | |
1484 | * Default addressing mode). It can be changed to a more standard | |
1485 | * Power of two mode where the page size is 256/512. This comes | |
1486 | * with a price: there is 3% less of space, the data is corrupted | |
1487 | * and the page size cannot be changed back to default addressing | |
1488 | * mode. | |
1489 | * | |
1490 | * The current addressing mode can be read from the XRDSR register | |
1491 | * and should not be changed, because is a destructive operation. | |
1492 | */ | |
1493 | if (val & XSR_PAGESIZE) { | |
1494 | /* Flash in Power of 2 mode */ | |
1495 | nor->page_size = (nor->page_size == 264) ? 256 : 512; | |
1496 | nor->mtd.writebufsize = nor->page_size; | |
1497 | nor->mtd.size = 8 * nor->page_size * info->n_sectors; | |
1498 | nor->mtd.erasesize = 8 * nor->page_size; | |
1499 | } else { | |
1500 | /* Flash in Default addressing mode */ | |
1501 | nor->flags |= SNOR_F_S3AN_ADDR_DEFAULT; | |
1502 | } | |
1503 | ||
1504 | return 0; | |
1505 | } | |
1506 | ||
cfc5604c CP |
1507 | struct spi_nor_read_command { |
1508 | u8 num_mode_clocks; | |
1509 | u8 num_wait_states; | |
1510 | u8 opcode; | |
1511 | enum spi_nor_protocol proto; | |
1512 | }; | |
1513 | ||
1514 | struct spi_nor_pp_command { | |
1515 | u8 opcode; | |
1516 | enum spi_nor_protocol proto; | |
1517 | }; | |
1518 | ||
1519 | enum spi_nor_read_command_index { | |
1520 | SNOR_CMD_READ, | |
1521 | SNOR_CMD_READ_FAST, | |
15f55331 | 1522 | SNOR_CMD_READ_1_1_1_DTR, |
cfc5604c CP |
1523 | |
1524 | /* Dual SPI */ | |
1525 | SNOR_CMD_READ_1_1_2, | |
1526 | SNOR_CMD_READ_1_2_2, | |
1527 | SNOR_CMD_READ_2_2_2, | |
15f55331 | 1528 | SNOR_CMD_READ_1_2_2_DTR, |
cfc5604c CP |
1529 | |
1530 | /* Quad SPI */ | |
1531 | SNOR_CMD_READ_1_1_4, | |
1532 | SNOR_CMD_READ_1_4_4, | |
1533 | SNOR_CMD_READ_4_4_4, | |
15f55331 | 1534 | SNOR_CMD_READ_1_4_4_DTR, |
cfc5604c | 1535 | |
fe488a5e CP |
1536 | /* Octo SPI */ |
1537 | SNOR_CMD_READ_1_1_8, | |
1538 | SNOR_CMD_READ_1_8_8, | |
1539 | SNOR_CMD_READ_8_8_8, | |
1540 | SNOR_CMD_READ_1_8_8_DTR, | |
1541 | ||
cfc5604c CP |
1542 | SNOR_CMD_READ_MAX |
1543 | }; | |
1544 | ||
1545 | enum spi_nor_pp_command_index { | |
1546 | SNOR_CMD_PP, | |
1547 | ||
1548 | /* Quad SPI */ | |
1549 | SNOR_CMD_PP_1_1_4, | |
1550 | SNOR_CMD_PP_1_4_4, | |
1551 | SNOR_CMD_PP_4_4_4, | |
1552 | ||
fe488a5e CP |
1553 | /* Octo SPI */ |
1554 | SNOR_CMD_PP_1_1_8, | |
1555 | SNOR_CMD_PP_1_8_8, | |
1556 | SNOR_CMD_PP_8_8_8, | |
1557 | ||
cfc5604c CP |
1558 | SNOR_CMD_PP_MAX |
1559 | }; | |
1560 | ||
1561 | struct spi_nor_flash_parameter { | |
1562 | u64 size; | |
1563 | u32 page_size; | |
1564 | ||
1565 | struct spi_nor_hwcaps hwcaps; | |
1566 | struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; | |
1567 | struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX]; | |
1568 | ||
1569 | int (*quad_enable)(struct spi_nor *nor); | |
1570 | }; | |
1571 | ||
1572 | static void | |
1573 | spi_nor_set_read_settings(struct spi_nor_read_command *read, | |
1574 | u8 num_mode_clocks, | |
1575 | u8 num_wait_states, | |
1576 | u8 opcode, | |
1577 | enum spi_nor_protocol proto) | |
1578 | { | |
1579 | read->num_mode_clocks = num_mode_clocks; | |
1580 | read->num_wait_states = num_wait_states; | |
1581 | read->opcode = opcode; | |
1582 | read->proto = proto; | |
1583 | } | |
1584 | ||
1585 | static void | |
1586 | spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, | |
1587 | u8 opcode, | |
1588 | enum spi_nor_protocol proto) | |
1589 | { | |
1590 | pp->opcode = opcode; | |
1591 | pp->proto = proto; | |
1592 | } | |
1593 | ||
1594 | static int spi_nor_init_params(struct spi_nor *nor, | |
1595 | const struct flash_info *info, | |
1596 | struct spi_nor_flash_parameter *params) | |
1597 | { | |
1598 | /* Set legacy flash parameters as default. */ | |
1599 | memset(params, 0, sizeof(*params)); | |
1600 | ||
1601 | /* Set SPI NOR sizes. */ | |
1602 | params->size = info->sector_size * info->n_sectors; | |
1603 | params->page_size = info->page_size; | |
1604 | ||
1605 | /* (Fast) Read settings. */ | |
1606 | params->hwcaps.mask |= SNOR_HWCAPS_READ; | |
1607 | spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], | |
1608 | 0, 0, SPINOR_OP_READ, | |
1609 | SNOR_PROTO_1_1_1); | |
1610 | ||
1611 | if (!(info->flags & SPI_NOR_NO_FR)) { | |
1612 | params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST; | |
1613 | spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST], | |
1614 | 0, 8, SPINOR_OP_READ_FAST, | |
1615 | SNOR_PROTO_1_1_1); | |
1616 | } | |
1617 | ||
1618 | if (info->flags & SPI_NOR_DUAL_READ) { | |
1619 | params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; | |
1620 | spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2], | |
1621 | 0, 8, SPINOR_OP_READ_1_1_2, | |
1622 | SNOR_PROTO_1_1_2); | |
1623 | } | |
1624 | ||
1625 | if (info->flags & SPI_NOR_QUAD_READ) { | |
1626 | params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; | |
1627 | spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4], | |
1628 | 0, 8, SPINOR_OP_READ_1_1_4, | |
1629 | SNOR_PROTO_1_1_4); | |
1630 | } | |
1631 | ||
1632 | /* Page Program settings. */ | |
1633 | params->hwcaps.mask |= SNOR_HWCAPS_PP; | |
1634 | spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], | |
1635 | SPINOR_OP_PP, SNOR_PROTO_1_1_1); | |
1636 | ||
1637 | /* Select the procedure to set the Quad Enable bit. */ | |
1638 | if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD | | |
1639 | SNOR_HWCAPS_PP_QUAD)) { | |
1640 | switch (JEDEC_MFR(info)) { | |
1641 | case SNOR_MFR_MACRONIX: | |
1642 | params->quad_enable = macronix_quad_enable; | |
1643 | break; | |
1644 | ||
1645 | case SNOR_MFR_MICRON: | |
1646 | break; | |
1647 | ||
1648 | default: | |
1649 | params->quad_enable = spansion_quad_enable; | |
1650 | break; | |
1651 | } | |
1652 | } | |
1653 | ||
1654 | return 0; | |
1655 | } | |
1656 | ||
1657 | static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size) | |
1658 | { | |
1659 | size_t i; | |
1660 | ||
1661 | for (i = 0; i < size; i++) | |
1662 | if (table[i][0] == (int)hwcaps) | |
1663 | return table[i][1]; | |
1664 | ||
1665 | return -EINVAL; | |
1666 | } | |
1667 | ||
1668 | static int spi_nor_hwcaps_read2cmd(u32 hwcaps) | |
1669 | { | |
1670 | static const int hwcaps_read2cmd[][2] = { | |
1671 | { SNOR_HWCAPS_READ, SNOR_CMD_READ }, | |
1672 | { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST }, | |
15f55331 | 1673 | { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR }, |
cfc5604c CP |
1674 | { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 }, |
1675 | { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 }, | |
1676 | { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 }, | |
15f55331 | 1677 | { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR }, |
cfc5604c CP |
1678 | { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 }, |
1679 | { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 }, | |
1680 | { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 }, | |
15f55331 | 1681 | { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR }, |
fe488a5e CP |
1682 | { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 }, |
1683 | { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 }, | |
1684 | { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 }, | |
1685 | { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR }, | |
cfc5604c CP |
1686 | }; |
1687 | ||
1688 | return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd, | |
1689 | ARRAY_SIZE(hwcaps_read2cmd)); | |
1690 | } | |
1691 | ||
1692 | static int spi_nor_hwcaps_pp2cmd(u32 hwcaps) | |
1693 | { | |
1694 | static const int hwcaps_pp2cmd[][2] = { | |
1695 | { SNOR_HWCAPS_PP, SNOR_CMD_PP }, | |
1696 | { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 }, | |
1697 | { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 }, | |
1698 | { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 }, | |
fe488a5e CP |
1699 | { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 }, |
1700 | { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 }, | |
1701 | { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 }, | |
cfc5604c CP |
1702 | }; |
1703 | ||
1704 | return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd, | |
1705 | ARRAY_SIZE(hwcaps_pp2cmd)); | |
1706 | } | |
1707 | ||
1708 | static int spi_nor_select_read(struct spi_nor *nor, | |
1709 | const struct spi_nor_flash_parameter *params, | |
1710 | u32 shared_hwcaps) | |
1711 | { | |
1712 | int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1; | |
1713 | const struct spi_nor_read_command *read; | |
1714 | ||
1715 | if (best_match < 0) | |
1716 | return -EINVAL; | |
1717 | ||
1718 | cmd = spi_nor_hwcaps_read2cmd(BIT(best_match)); | |
1719 | if (cmd < 0) | |
1720 | return -EINVAL; | |
1721 | ||
1722 | read = ¶ms->reads[cmd]; | |
1723 | nor->read_opcode = read->opcode; | |
1724 | nor->read_proto = read->proto; | |
1725 | ||
1726 | /* | |
1727 | * In the spi-nor framework, we don't need to make the difference | |
1728 | * between mode clock cycles and wait state clock cycles. | |
1729 | * Indeed, the value of the mode clock cycles is used by a QSPI | |
1730 | * flash memory to know whether it should enter or leave its 0-4-4 | |
1731 | * (Continuous Read / XIP) mode. | |
1732 | * eXecution In Place is out of the scope of the mtd sub-system. | |
1733 | * Hence we choose to merge both mode and wait state clock cycles | |
1734 | * into the so called dummy clock cycles. | |
1735 | */ | |
1736 | nor->read_dummy = read->num_mode_clocks + read->num_wait_states; | |
1737 | return 0; | |
1738 | } | |
1739 | ||
1740 | static int spi_nor_select_pp(struct spi_nor *nor, | |
1741 | const struct spi_nor_flash_parameter *params, | |
1742 | u32 shared_hwcaps) | |
1743 | { | |
1744 | int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1; | |
1745 | const struct spi_nor_pp_command *pp; | |
1746 | ||
1747 | if (best_match < 0) | |
1748 | return -EINVAL; | |
1749 | ||
1750 | cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match)); | |
1751 | if (cmd < 0) | |
1752 | return -EINVAL; | |
1753 | ||
1754 | pp = ¶ms->page_programs[cmd]; | |
1755 | nor->program_opcode = pp->opcode; | |
1756 | nor->write_proto = pp->proto; | |
1757 | return 0; | |
1758 | } | |
1759 | ||
1760 | static int spi_nor_select_erase(struct spi_nor *nor, | |
1761 | const struct flash_info *info) | |
1762 | { | |
1763 | struct mtd_info *mtd = &nor->mtd; | |
1764 | ||
1765 | #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS | |
1766 | /* prefer "small sector" erase if possible */ | |
1767 | if (info->flags & SECT_4K) { | |
1768 | nor->erase_opcode = SPINOR_OP_BE_4K; | |
1769 | mtd->erasesize = 4096; | |
1770 | } else if (info->flags & SECT_4K_PMC) { | |
1771 | nor->erase_opcode = SPINOR_OP_BE_4K_PMC; | |
1772 | mtd->erasesize = 4096; | |
1773 | } else | |
1774 | #endif | |
1775 | { | |
1776 | nor->erase_opcode = SPINOR_OP_SE; | |
1777 | mtd->erasesize = info->sector_size; | |
1778 | } | |
1779 | return 0; | |
1780 | } | |
1781 | ||
1782 | static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, | |
1783 | const struct spi_nor_flash_parameter *params, | |
1784 | const struct spi_nor_hwcaps *hwcaps) | |
1785 | { | |
1786 | u32 ignored_mask, shared_mask; | |
1787 | bool enable_quad_io; | |
1788 | int err; | |
1789 | ||
1790 | /* | |
1791 | * Keep only the hardware capabilities supported by both the SPI | |
1792 | * controller and the SPI flash memory. | |
1793 | */ | |
1794 | shared_mask = hwcaps->mask & params->hwcaps.mask; | |
1795 | ||
1796 | /* SPI n-n-n protocols are not supported yet. */ | |
1797 | ignored_mask = (SNOR_HWCAPS_READ_2_2_2 | | |
1798 | SNOR_HWCAPS_READ_4_4_4 | | |
fe488a5e CP |
1799 | SNOR_HWCAPS_READ_8_8_8 | |
1800 | SNOR_HWCAPS_PP_4_4_4 | | |
1801 | SNOR_HWCAPS_PP_8_8_8); | |
cfc5604c CP |
1802 | if (shared_mask & ignored_mask) { |
1803 | dev_dbg(nor->dev, | |
1804 | "SPI n-n-n protocols are not supported yet.\n"); | |
1805 | shared_mask &= ~ignored_mask; | |
1806 | } | |
1807 | ||
1808 | /* Select the (Fast) Read command. */ | |
1809 | err = spi_nor_select_read(nor, params, shared_mask); | |
1810 | if (err) { | |
1811 | dev_err(nor->dev, | |
1812 | "can't select read settings supported by both the SPI controller and memory.\n"); | |
1813 | return err; | |
1814 | } | |
1815 | ||
1816 | /* Select the Page Program command. */ | |
1817 | err = spi_nor_select_pp(nor, params, shared_mask); | |
1818 | if (err) { | |
1819 | dev_err(nor->dev, | |
1820 | "can't select write settings supported by both the SPI controller and memory.\n"); | |
1821 | return err; | |
1822 | } | |
1823 | ||
1824 | /* Select the Sector Erase command. */ | |
1825 | err = spi_nor_select_erase(nor, info); | |
1826 | if (err) { | |
1827 | dev_err(nor->dev, | |
1828 | "can't select erase settings supported by both the SPI controller and memory.\n"); | |
1829 | return err; | |
1830 | } | |
1831 | ||
1832 | /* Enable Quad I/O if needed. */ | |
1833 | enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 || | |
1834 | spi_nor_get_protocol_width(nor->write_proto) == 4); | |
1835 | if (enable_quad_io && params->quad_enable) { | |
1836 | err = params->quad_enable(nor); | |
1837 | if (err) { | |
1838 | dev_err(nor->dev, "quad mode not supported\n"); | |
1839 | return err; | |
1840 | } | |
1841 | } | |
1842 | ||
1843 | return 0; | |
1844 | } | |
1845 | ||
1846 | int spi_nor_scan(struct spi_nor *nor, const char *name, | |
1847 | const struct spi_nor_hwcaps *hwcaps) | |
b199489d | 1848 | { |
cfc5604c | 1849 | struct spi_nor_flash_parameter params; |
06bb6f5a | 1850 | const struct flash_info *info = NULL; |
b199489d | 1851 | struct device *dev = nor->dev; |
19763671 | 1852 | struct mtd_info *mtd = &nor->mtd; |
9c7d7875 | 1853 | struct device_node *np = spi_nor_get_flash_node(nor); |
b199489d HS |
1854 | int ret; |
1855 | int i; | |
1856 | ||
1857 | ret = spi_nor_check(nor); | |
1858 | if (ret) | |
1859 | return ret; | |
1860 | ||
cfc5604c CP |
1861 | /* Reset SPI protocol for all commands. */ |
1862 | nor->reg_proto = SNOR_PROTO_1_1_1; | |
1863 | nor->read_proto = SNOR_PROTO_1_1_1; | |
1864 | nor->write_proto = SNOR_PROTO_1_1_1; | |
1865 | ||
43163022 | 1866 | if (name) |
06bb6f5a | 1867 | info = spi_nor_match_id(name); |
43163022 | 1868 | /* Try to auto-detect if chip name wasn't specified or not found */ |
06bb6f5a RM |
1869 | if (!info) |
1870 | info = spi_nor_read_id(nor); | |
1871 | if (IS_ERR_OR_NULL(info)) | |
70f3ce05 BH |
1872 | return -ENOENT; |
1873 | ||
58c81957 RM |
1874 | /* |
1875 | * If caller has specified name of flash model that can normally be | |
1876 | * detected using JEDEC, let's verify it. | |
1877 | */ | |
1878 | if (name && info->id_len) { | |
06bb6f5a | 1879 | const struct flash_info *jinfo; |
b199489d | 1880 | |
06bb6f5a RM |
1881 | jinfo = spi_nor_read_id(nor); |
1882 | if (IS_ERR(jinfo)) { | |
1883 | return PTR_ERR(jinfo); | |
1884 | } else if (jinfo != info) { | |
b199489d HS |
1885 | /* |
1886 | * JEDEC knows better, so overwrite platform ID. We | |
1887 | * can't trust partitions any longer, but we'll let | |
1888 | * mtd apply them anyway, since some partitions may be | |
1889 | * marked read-only, and we don't want to lose that | |
1890 | * information, even if it's not 100% accurate. | |
1891 | */ | |
1892 | dev_warn(dev, "found %s, expected %s\n", | |
06bb6f5a RM |
1893 | jinfo->name, info->name); |
1894 | info = jinfo; | |
b199489d HS |
1895 | } |
1896 | } | |
1897 | ||
1898 | mutex_init(&nor->lock); | |
1899 | ||
e99ca98f RRD |
1900 | /* |
1901 | * Make sure the XSR_RDY flag is set before calling | |
1902 | * spi_nor_wait_till_ready(). Xilinx S3AN share MFR | |
1903 | * with Atmel spi-nor | |
1904 | */ | |
1905 | if (info->flags & SPI_S3AN) | |
1906 | nor->flags |= SNOR_F_READY_XSR_RDY; | |
1907 | ||
cfc5604c CP |
1908 | /* Parse the Serial Flash Discoverable Parameters table. */ |
1909 | ret = spi_nor_init_params(nor, info, ¶ms); | |
1910 | if (ret) | |
1911 | return ret; | |
1912 | ||
b199489d | 1913 | /* |
c6fc2171 BN |
1914 | * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up |
1915 | * with the software protection bits set | |
b199489d HS |
1916 | */ |
1917 | ||
f0d2448e BN |
1918 | if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || |
1919 | JEDEC_MFR(info) == SNOR_MFR_INTEL || | |
76a4707d BN |
1920 | JEDEC_MFR(info) == SNOR_MFR_SST || |
1921 | info->flags & SPI_NOR_HAS_LOCK) { | |
b199489d HS |
1922 | write_enable(nor); |
1923 | write_sr(nor, 0); | |
edf891ef | 1924 | spi_nor_wait_till_ready(nor); |
b199489d HS |
1925 | } |
1926 | ||
32f1b7c8 | 1927 | if (!mtd->name) |
b199489d | 1928 | mtd->name = dev_name(dev); |
c9ec3900 | 1929 | mtd->priv = nor; |
b199489d HS |
1930 | mtd->type = MTD_NORFLASH; |
1931 | mtd->writesize = 1; | |
1932 | mtd->flags = MTD_CAP_NORFLASH; | |
cfc5604c | 1933 | mtd->size = params.size; |
b199489d HS |
1934 | mtd->_erase = spi_nor_erase; |
1935 | mtd->_read = spi_nor_read; | |
1936 | ||
357ca38d | 1937 | /* NOR protection support for STmicro/Micron chips and similar */ |
76a4707d BN |
1938 | if (JEDEC_MFR(info) == SNOR_MFR_MICRON || |
1939 | info->flags & SPI_NOR_HAS_LOCK) { | |
8cc7f33a BN |
1940 | nor->flash_lock = stm_lock; |
1941 | nor->flash_unlock = stm_unlock; | |
5bf0e69b | 1942 | nor->flash_is_locked = stm_is_locked; |
8cc7f33a BN |
1943 | } |
1944 | ||
5bf0e69b | 1945 | if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) { |
b199489d HS |
1946 | mtd->_lock = spi_nor_lock; |
1947 | mtd->_unlock = spi_nor_unlock; | |
5bf0e69b | 1948 | mtd->_is_locked = spi_nor_is_locked; |
b199489d HS |
1949 | } |
1950 | ||
1951 | /* sst nor chips use AAI word program */ | |
1952 | if (info->flags & SST_WRITE) | |
1953 | mtd->_write = sst_write; | |
1954 | else | |
1955 | mtd->_write = spi_nor_write; | |
1956 | ||
51983b7d BN |
1957 | if (info->flags & USE_FSR) |
1958 | nor->flags |= SNOR_F_USE_FSR; | |
3dd8012a BN |
1959 | if (info->flags & SPI_NOR_HAS_TB) |
1960 | nor->flags |= SNOR_F_HAS_SR_TB; | |
2f5ad7f0 | 1961 | if (info->flags & NO_CHIP_ERASE) |
1962 | nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; | |
c14dedde | 1963 | |
b199489d HS |
1964 | if (info->flags & SPI_NOR_NO_ERASE) |
1965 | mtd->flags |= MTD_NO_ERASE; | |
1966 | ||
1967 | mtd->dev.parent = dev; | |
cfc5604c | 1968 | nor->page_size = params.page_size; |
b199489d HS |
1969 | mtd->writebufsize = nor->page_size; |
1970 | ||
1971 | if (np) { | |
1972 | /* If we were instantiated by DT, use it */ | |
1973 | if (of_property_read_bool(np, "m25p,fast-read")) | |
cfc5604c | 1974 | params.hwcaps.mask |= SNOR_HWCAPS_READ_FAST; |
b199489d | 1975 | else |
cfc5604c | 1976 | params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST; |
b199489d HS |
1977 | } else { |
1978 | /* If we weren't instantiated by DT, default to fast-read */ | |
cfc5604c | 1979 | params.hwcaps.mask |= SNOR_HWCAPS_READ_FAST; |
b199489d HS |
1980 | } |
1981 | ||
1982 | /* Some devices cannot do fast-read, no matter what DT tells us */ | |
1983 | if (info->flags & SPI_NOR_NO_FR) | |
cfc5604c | 1984 | params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST; |
b199489d | 1985 | |
cfc5604c CP |
1986 | /* |
1987 | * Configure the SPI memory: | |
1988 | * - select op codes for (Fast) Read, Page Program and Sector Erase. | |
1989 | * - set the number of dummy cycles (mode cycles + wait states). | |
1990 | * - set the SPI protocols for register and memory accesses. | |
1991 | * - set the Quad Enable bit if needed (required by SPI x-y-4 protos). | |
1992 | */ | |
1993 | ret = spi_nor_setup(nor, info, ¶ms, hwcaps); | |
1994 | if (ret) | |
1995 | return ret; | |
b199489d HS |
1996 | |
1997 | if (info->addr_width) | |
1998 | nor->addr_width = info->addr_width; | |
1999 | else if (mtd->size > 0x1000000) { | |
2000 | /* enable 4-byte addressing if the device exceeds 16MiB */ | |
2001 | nor->addr_width = 4; | |
ba3ae6a1 CP |
2002 | if (JEDEC_MFR(info) == SNOR_MFR_SPANSION || |
2003 | info->flags & SPI_NOR_4B_OPCODES) | |
2004 | spi_nor_set_4byte_opcodes(nor, info); | |
2005 | else | |
d928a259 | 2006 | set_4byte(nor, info, 1); |
b199489d HS |
2007 | } else { |
2008 | nor->addr_width = 3; | |
2009 | } | |
2010 | ||
c67cbb83 BN |
2011 | if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { |
2012 | dev_err(dev, "address width is too large: %u\n", | |
2013 | nor->addr_width); | |
2014 | return -EINVAL; | |
2015 | } | |
2016 | ||
e99ca98f RRD |
2017 | if (info->flags & SPI_S3AN) { |
2018 | ret = s3an_nor_scan(info, nor); | |
2019 | if (ret) | |
2020 | return ret; | |
2021 | } | |
2022 | ||
06bb6f5a | 2023 | dev_info(dev, "%s (%lld Kbytes)\n", info->name, |
b199489d HS |
2024 | (long long)mtd->size >> 10); |
2025 | ||
2026 | dev_dbg(dev, | |
2027 | "mtd .name = %s, .size = 0x%llx (%lldMiB), " | |
2028 | ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", | |
2029 | mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20), | |
2030 | mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions); | |
2031 | ||
2032 | if (mtd->numeraseregions) | |
2033 | for (i = 0; i < mtd->numeraseregions; i++) | |
2034 | dev_dbg(dev, | |
2035 | "mtd.eraseregions[%d] = { .offset = 0x%llx, " | |
2036 | ".erasesize = 0x%.8x (%uKiB), " | |
2037 | ".numblocks = %d }\n", | |
2038 | i, (long long)mtd->eraseregions[i].offset, | |
2039 | mtd->eraseregions[i].erasesize, | |
2040 | mtd->eraseregions[i].erasesize / 1024, | |
2041 | mtd->eraseregions[i].numblocks); | |
2042 | return 0; | |
2043 | } | |
b61834b0 | 2044 | EXPORT_SYMBOL_GPL(spi_nor_scan); |
b199489d | 2045 | |
06bb6f5a | 2046 | static const struct flash_info *spi_nor_match_id(const char *name) |
0d8c11c0 | 2047 | { |
06bb6f5a | 2048 | const struct flash_info *id = spi_nor_ids; |
0d8c11c0 | 2049 | |
2ff46e6f | 2050 | while (id->name) { |
0d8c11c0 HS |
2051 | if (!strcmp(name, id->name)) |
2052 | return id; | |
2053 | id++; | |
2054 | } | |
2055 | return NULL; | |
2056 | } | |
2057 | ||
b199489d HS |
2058 | MODULE_LICENSE("GPL"); |
2059 | MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>"); | |
2060 | MODULE_AUTHOR("Mike Lavender"); | |
2061 | MODULE_DESCRIPTION("framework for SPI NOR"); |