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nandsim: remove unused STATE_DATAOUT_STATUS_M and OPT_SMARTMEDIA
[mirror_ubuntu-artful-kernel.git] / drivers / mtd / spi-nor / spi-nor.c
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b199489d 1/*
8eabdd1e
HS		 2 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
3 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
4 *
5 * Copyright (C) 2005, Intec Automation Inc.
6 * Copyright (C) 2014, Freescale Semiconductor, Inc.
b199489d
HS		 7 *
8 * This code is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/err.h>
14#include <linux/errno.h>
15#include <linux/module.h>
16#include <linux/device.h>
17#include <linux/mutex.h>
18#include <linux/math64.h>
19
20#include <linux/mtd/cfi.h>
21#include <linux/mtd/mtd.h>
22#include <linux/of_platform.h>
23#include <linux/spi/flash.h>
24#include <linux/mtd/spi-nor.h>
25
26/* Define max times to check status register before we give up. */
27#define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
28
d928a259
HS		 29#define SPI_NOR_MAX_ID_LEN 6
30
31struct flash_info {
32 /*
33 * This array stores the ID bytes.
34 * The first three bytes are the JEDIC ID.
35 * JEDEC ID zero means "no ID" (mostly older chips).
36 */
37 u8 id[SPI_NOR_MAX_ID_LEN];
38 u8 id_len;
39
40 /* The size listed here is what works with SPINOR_OP_SE, which isn't
41 * necessarily called a "sector" by the vendor.
42 */
43 unsigned sector_size;
44 u16 n_sectors;
45
46 u16 page_size;
47 u16 addr_width;
48
49 u16 flags;
50#define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
51#define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
52#define SST_WRITE 0x04 /* use SST byte programming */
53#define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
54#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
55#define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
56#define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
57#define USE_FSR 0x80 /* use flag status register */
58};
59
60#define JEDEC_MFR(info) ((info)->id[0])
b199489d 61
70f3ce05
BH		 62static const struct spi_device_id *spi_nor_match_id(const char *name);
63
b199489d
HS		 64/*
65 * Read the status register, returning its value in the location
66 * Return the status register value.
67 * Returns negative if error occurred.
68 */
69static int read_sr(struct spi_nor *nor)
70{
71 int ret;
72 u8 val;
73
b02e7f3e 74 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
b199489d
HS		 75 if (ret < 0) {
76 pr_err("error %d reading SR\n", (int) ret);
77 return ret;
78 }
79
80 return val;
81}
82
c14dedde 83/*
84 * Read the flag status register, returning its value in the location
85 * Return the status register value.
86 * Returns negative if error occurred.
87 */
88static int read_fsr(struct spi_nor *nor)
89{
90 int ret;
91 u8 val;
92
93 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
94 if (ret < 0) {
95 pr_err("error %d reading FSR\n", ret);
96 return ret;
97 }
98
99 return val;
100}
101
b199489d
HS		 102/*
103 * Read configuration register, returning its value in the
104 * location. Return the configuration register value.
105 * Returns negative if error occured.
106 */
107static int read_cr(struct spi_nor *nor)
108{
109 int ret;
110 u8 val;
111
b02e7f3e 112 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
b199489d
HS		 113 if (ret < 0) {
114 dev_err(nor->dev, "error %d reading CR\n", ret);
115 return ret;
116 }
117
118 return val;
119}
120
121/*
122 * Dummy Cycle calculation for different type of read.
123 * It can be used to support more commands with
124 * different dummy cycle requirements.
125 */
126static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
127{
128 switch (nor->flash_read) {
129 case SPI_NOR_FAST:
130 case SPI_NOR_DUAL:
131 case SPI_NOR_QUAD:
0b78a2cf 132 return 8;
b199489d
HS		 133 case SPI_NOR_NORMAL:
134 return 0;
135 }
136 return 0;
137}
138
139/*
140 * Write status register 1 byte
141 * Returns negative if error occurred.
142 */
143static inline int write_sr(struct spi_nor *nor, u8 val)
144{
145 nor->cmd_buf[0] = val;
b02e7f3e 146 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
b199489d
HS		 147}
148
149/*
150 * Set write enable latch with Write Enable command.
151 * Returns negative if error occurred.
152 */
153static inline int write_enable(struct spi_nor *nor)
154{
b02e7f3e 155 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
b199489d
HS		 156}
157
158/*
159 * Send write disble instruction to the chip.
160 */
161static inline int write_disable(struct spi_nor *nor)
162{
b02e7f3e 163 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0);
b199489d
HS		 164}
165
166static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
167{
168 return mtd->priv;
169}
170
171/* Enable/disable 4-byte addressing mode. */
d928a259
HS		 172static inline int set_4byte(struct spi_nor *nor, struct flash_info *info,
173 int enable)
b199489d
HS		 174{
175 int status;
176 bool need_wren = false;
177 u8 cmd;
178
d928a259 179 switch (JEDEC_MFR(info)) {
b199489d
HS		 180 case CFI_MFR_ST: /* Micron, actually */
181 /* Some Micron need WREN command; all will accept it */
182 need_wren = true;
183 case CFI_MFR_MACRONIX:
184 case 0xEF /* winbond */:
185 if (need_wren)
186 write_enable(nor);
187
b02e7f3e 188 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
b199489d
HS		 189 status = nor->write_reg(nor, cmd, NULL, 0, 0);
190 if (need_wren)
191 write_disable(nor);
192
193 return status;
194 default:
195 /* Spansion style */
196 nor->cmd_buf[0] = enable << 7;
b02e7f3e 197 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0);
b199489d
HS		 198 }
199}
51983b7d 200static inline int spi_nor_sr_ready(struct spi_nor *nor)
b199489d 201{
51983b7d
BN		 202 int sr = read_sr(nor);
203 if (sr < 0)
204 return sr;
205 else
206 return !(sr & SR_WIP);
207}
b199489d 208
51983b7d
BN		 209static inline int spi_nor_fsr_ready(struct spi_nor *nor)
210{
211 int fsr = read_fsr(nor);
212 if (fsr < 0)
213 return fsr;
214 else
215 return fsr & FSR_READY;
216}
b199489d 217
51983b7d
BN		 218static int spi_nor_ready(struct spi_nor *nor)
219{
220 int sr, fsr;
221 sr = spi_nor_sr_ready(nor);
222 if (sr < 0)
223 return sr;
224 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
225 if (fsr < 0)
226 return fsr;
227 return sr && fsr;
b199489d
HS		 228}
229
b94ed087
BN		 230/*
231 * Service routine to read status register until ready, or timeout occurs.
232 * Returns non-zero if error.
233 */
51983b7d 234static int spi_nor_wait_till_ready(struct spi_nor *nor)
c14dedde 235{
236 unsigned long deadline;
a95ce92e 237 int timeout = 0, ret;
c14dedde 238
239 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
240
a95ce92e
BN		 241 while (!timeout) {
242 if (time_after_eq(jiffies, deadline))
243 timeout = 1;
c14dedde 244
51983b7d
BN		 245 ret = spi_nor_ready(nor);
246 if (ret < 0)
247 return ret;
248 if (ret)
249 return 0;
a95ce92e
BN		 250
251 cond_resched();
252 }
253
254 dev_err(nor->dev, "flash operation timed out\n");
c14dedde 255
256 return -ETIMEDOUT;
257}
258
b199489d
HS		 259/*
260 * Erase the whole flash memory
261 *
262 * Returns 0 if successful, non-zero otherwise.
263 */
264static int erase_chip(struct spi_nor *nor)
265{
b199489d
HS		 266 dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd->size >> 10));
267
b02e7f3e 268 return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0);
b199489d
HS		 269}
270
271static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
272{
273 int ret = 0;
274
275 mutex_lock(&nor->lock);
276
277 if (nor->prepare) {
278 ret = nor->prepare(nor, ops);
279 if (ret) {
280 dev_err(nor->dev, "failed in the preparation.\n");
281 mutex_unlock(&nor->lock);
282 return ret;
283 }
284 }
285 return ret;
286}
287
288static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
289{
290 if (nor->unprepare)
291 nor->unprepare(nor, ops);
292 mutex_unlock(&nor->lock);
293}
294
295/*
296 * Erase an address range on the nor chip. The address range may extend
297 * one or more erase sectors. Return an error is there is a problem erasing.
298 */
299static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
300{
301 struct spi_nor *nor = mtd_to_spi_nor(mtd);
302 u32 addr, len;
303 uint32_t rem;
304 int ret;
305
306 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
307 (long long)instr->len);
308
309 div_u64_rem(instr->len, mtd->erasesize, &rem);
310 if (rem)
311 return -EINVAL;
312
313 addr = instr->addr;
314 len = instr->len;
315
316 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
317 if (ret)
318 return ret;
319
320 /* whole-chip erase? */
321 if (len == mtd->size) {
05241aea
BN		 322 write_enable(nor);
323
b199489d
HS		 324 if (erase_chip(nor)) {
325 ret = -EIO;
326 goto erase_err;
327 }
328
dfa9c0cb
BN		 329 ret = spi_nor_wait_till_ready(nor);
330 if (ret)
331 goto erase_err;
332
b199489d 333 /* REVISIT in some cases we could speed up erasing large regions
b02e7f3e 334 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
b199489d
HS		 335 * to use "small sector erase", but that's not always optimal.
336 */
337
338 /* "sector"-at-a-time erase */
339 } else {
340 while (len) {
05241aea
BN		 341 write_enable(nor);
342
b199489d
HS		 343 if (nor->erase(nor, addr)) {
344 ret = -EIO;
345 goto erase_err;
346 }
347
348 addr += mtd->erasesize;
349 len -= mtd->erasesize;
dfa9c0cb
BN		 350
351 ret = spi_nor_wait_till_ready(nor);
352 if (ret)
353 goto erase_err;
b199489d
HS		 354 }
355 }
356
05241aea
BN		 357 write_disable(nor);
358
b199489d
HS		 359 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
360
361 instr->state = MTD_ERASE_DONE;
362 mtd_erase_callback(instr);
363
364 return ret;
365
366erase_err:
367 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
368 instr->state = MTD_ERASE_FAILED;
369 return ret;
370}
371
372static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
373{
374 struct spi_nor *nor = mtd_to_spi_nor(mtd);
375 uint32_t offset = ofs;
376 uint8_t status_old, status_new;
377 int ret = 0;
378
379 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
380 if (ret)
381 return ret;
382
b199489d
HS		 383 status_old = read_sr(nor);
384
385 if (offset < mtd->size - (mtd->size / 2))
386 status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
387 else if (offset < mtd->size - (mtd->size / 4))
388 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
389 else if (offset < mtd->size - (mtd->size / 8))
390 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
391 else if (offset < mtd->size - (mtd->size / 16))
392 status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
393 else if (offset < mtd->size - (mtd->size / 32))
394 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
395 else if (offset < mtd->size - (mtd->size / 64))
396 status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
397 else
398 status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
399
400 /* Only modify protection if it will not unlock other areas */
401 if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) >
402 (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
403 write_enable(nor);
404 ret = write_sr(nor, status_new);
405 if (ret)
406 goto err;
407 }
408
409err:
410 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
411 return ret;
412}
413
414static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
415{
416 struct spi_nor *nor = mtd_to_spi_nor(mtd);
417 uint32_t offset = ofs;
418 uint8_t status_old, status_new;
419 int ret = 0;
420
421 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
422 if (ret)
423 return ret;
424
b199489d
HS		 425 status_old = read_sr(nor);
426
427 if (offset+len > mtd->size - (mtd->size / 64))
428 status_new = status_old & ~(SR_BP2 | SR_BP1 | SR_BP0);
429 else if (offset+len > mtd->size - (mtd->size / 32))
430 status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
431 else if (offset+len > mtd->size - (mtd->size / 16))
432 status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
433 else if (offset+len > mtd->size - (mtd->size / 8))
434 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
435 else if (offset+len > mtd->size - (mtd->size / 4))
436 status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
437 else if (offset+len > mtd->size - (mtd->size / 2))
438 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
439 else
440 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
441
442 /* Only modify protection if it will not lock other areas */
443 if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) <
444 (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
445 write_enable(nor);
446 ret = write_sr(nor, status_new);
447 if (ret)
448 goto err;
449 }
450
451err:
452 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
453 return ret;
454}
455
09ffafb6 456/* Used when the "_ext_id" is two bytes at most */
b199489d
HS		 457#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
458 ((kernel_ulong_t)&(struct flash_info) { \
09ffafb6
HS		 459 .id = { \
460 ((_jedec_id) >> 16) & 0xff, \
461 ((_jedec_id) >> 8) & 0xff, \
462 (_jedec_id) & 0xff, \
463 ((_ext_id) >> 8) & 0xff, \
464 (_ext_id) & 0xff, \
465 }, \
466 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
b199489d
HS		 467 .sector_size = (_sector_size), \
468 .n_sectors = (_n_sectors), \
469 .page_size = 256, \
470 .flags = (_flags), \
471 })
472
6d7604e5
HS		 473#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
474 ((kernel_ulong_t)&(struct flash_info) { \
475 .id = { \
476 ((_jedec_id) >> 16) & 0xff, \
477 ((_jedec_id) >> 8) & 0xff, \
478 (_jedec_id) & 0xff, \
479 ((_ext_id) >> 16) & 0xff, \
480 ((_ext_id) >> 8) & 0xff, \
481 (_ext_id) & 0xff, \
482 }, \
483 .id_len = 6, \
484 .sector_size = (_sector_size), \
485 .n_sectors = (_n_sectors), \
486 .page_size = 256, \
487 .flags = (_flags), \
488 })
489
b199489d
HS		 490#define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
491 ((kernel_ulong_t)&(struct flash_info) { \
492 .sector_size = (_sector_size), \
493 .n_sectors = (_n_sectors), \
494 .page_size = (_page_size), \
495 .addr_width = (_addr_width), \
496 .flags = (_flags), \
497 })
498
499/* NOTE: double check command sets and memory organization when you add
500 * more nor chips. This current list focusses on newer chips, which
501 * have been converging on command sets which including JEDEC ID.
502 */
a5b7616c 503static const struct spi_device_id spi_nor_ids[] = {
b199489d
HS		 504 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
505 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
506 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
507
508 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
509 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
510 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
511
512 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
513 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
514 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
515 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
516
517 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
518
519 /* EON -- en25xxx */
520 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
521 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
522 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
523 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
524 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
a41595b3 525 { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
b199489d
HS		 526 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
527
528 /* ESMT */
529 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
530
531 /* Everspin */
532 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
533 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
534
ce56ce7d
RL		 535 /* Fujitsu */
536 { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
537
b199489d
HS		 538 /* GigaDevice */
539 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
540 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
541
542 /* Intel/Numonyx -- xxxs33b */
543 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
544 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
545 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
546
547 /* Macronix */
548 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
549 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
550 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
551 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
552 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
553 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
554 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
555 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
556 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
557 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
558 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
559 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
560 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
561
562 /* Micron */
548cd3ab
BH		 563 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
564 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ) },
565 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
566 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
567 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
568 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
569 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
570 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
b199489d
HS		 571
572 /* PMC */
573 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
574 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
575 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
576
577 /* Spansion -- single (large) sector size only, at least
578 * for the chips listed here (without boot sectors).
579 */
9ab86995 580 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
b199489d
HS		 581 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
582 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
583 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
584 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
585 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
586 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
587 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
6d7604e5 588 { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
b199489d
HS		 589 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
590 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
591 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
592 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
593 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
594 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
595 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
596 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
597 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
598 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
3e38933d 599 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, 0) },
b199489d
HS		 600
601 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
602 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
603 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
604 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
605 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
606 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
607 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
608 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
609 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
610 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
f02985b7 611 { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
b199489d
HS		 612
613 /* ST Microelectronics -- newer production may have feature updates */
614 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
615 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
616 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
617 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
618 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
619 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
620 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
621 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
622 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
b199489d
HS		 623
624 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
625 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
626 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
627 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
628 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
629 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
630 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
631 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
632 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
633
634 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
635 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
636 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
637
638 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
639 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
640 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
641
642 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
643 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
644 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
645 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
646 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
f2fabe16 647 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
b199489d
HS		 648
649 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
650 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
651 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
652 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
653 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
654 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
655 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
656 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
657 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
658 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
659 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
b199489d
HS		 660 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
661 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
662 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
663 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
664
665 /* Catalyst / On Semiconductor -- non-JEDEC */
666 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
667 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
668 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
669 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
670 { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
671 { },
672};
673
674static const struct spi_device_id *spi_nor_read_id(struct spi_nor *nor)
675{
676 int tmp;
09ffafb6 677 u8 id[SPI_NOR_MAX_ID_LEN];
b199489d
HS		 678 struct flash_info *info;
679
09ffafb6 680 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
b199489d
HS		 681 if (tmp < 0) {
682 dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp);
683 return ERR_PTR(tmp);
684 }
b199489d
HS		 685
686 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
687 info = (void *)spi_nor_ids[tmp].driver_data;
09ffafb6
HS		 688 if (info->id_len) {
689 if (!memcmp(info->id, id, info->id_len))
b199489d
HS		 690 return &spi_nor_ids[tmp];
691 }
692 }
09ffafb6
HS		 693 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %2x, %2x\n",
694 id[0], id[1], id[2]);
b199489d
HS		 695 return ERR_PTR(-ENODEV);
696}
697
b199489d
HS		 698static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
699 size_t *retlen, u_char *buf)
700{
701 struct spi_nor *nor = mtd_to_spi_nor(mtd);
702 int ret;
703
704 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
705
706 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
707 if (ret)
708 return ret;
709
710 ret = nor->read(nor, from, len, retlen, buf);
711
712 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
713 return ret;
714}
715
716static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
717 size_t *retlen, const u_char *buf)
718{
719 struct spi_nor *nor = mtd_to_spi_nor(mtd);
720 size_t actual;
721 int ret;
722
723 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
724
725 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
726 if (ret)
727 return ret;
728
b199489d
HS		 729 write_enable(nor);
730
731 nor->sst_write_second = false;
732
733 actual = to % 2;
734 /* Start write from odd address. */
735 if (actual) {
b02e7f3e 736 nor->program_opcode = SPINOR_OP_BP;
b199489d
HS		 737
738 /* write one byte. */
739 nor->write(nor, to, 1, retlen, buf);
b94ed087 740 ret = spi_nor_wait_till_ready(nor);
b199489d
HS		 741 if (ret)
742 goto time_out;
743 }
744 to += actual;
745
746 /* Write out most of the data here. */
747 for (; actual < len - 1; actual += 2) {
b02e7f3e 748 nor->program_opcode = SPINOR_OP_AAI_WP;
b199489d
HS		 749
750 /* write two bytes. */
751 nor->write(nor, to, 2, retlen, buf + actual);
b94ed087 752 ret = spi_nor_wait_till_ready(nor);
b199489d
HS		 753 if (ret)
754 goto time_out;
755 to += 2;
756 nor->sst_write_second = true;
757 }
758 nor->sst_write_second = false;
759
760 write_disable(nor);
b94ed087 761 ret = spi_nor_wait_till_ready(nor);
b199489d
HS		 762 if (ret)
763 goto time_out;
764
765 /* Write out trailing byte if it exists. */
766 if (actual != len) {
767 write_enable(nor);
768
b02e7f3e 769 nor->program_opcode = SPINOR_OP_BP;
b199489d
HS		 770 nor->write(nor, to, 1, retlen, buf + actual);
771
b94ed087 772 ret = spi_nor_wait_till_ready(nor);
b199489d
HS		 773 if (ret)
774 goto time_out;
775 write_disable(nor);
776 }
777time_out:
778 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
779 return ret;
780}
781
782/*
783 * Write an address range to the nor chip. Data must be written in
784 * FLASH_PAGESIZE chunks. The address range may be any size provided
785 * it is within the physical boundaries.
786 */
787static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
788 size_t *retlen, const u_char *buf)
789{
790 struct spi_nor *nor = mtd_to_spi_nor(mtd);
791 u32 page_offset, page_size, i;
792 int ret;
793
794 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
795
796 ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
797 if (ret)
798 return ret;
799
b199489d
HS		 800 write_enable(nor);
801
802 page_offset = to & (nor->page_size - 1);
803
804 /* do all the bytes fit onto one page? */
805 if (page_offset + len <= nor->page_size) {
806 nor->write(nor, to, len, retlen, buf);
807 } else {
808 /* the size of data remaining on the first page */
809 page_size = nor->page_size - page_offset;
810 nor->write(nor, to, page_size, retlen, buf);
811
812 /* write everything in nor->page_size chunks */
813 for (i = page_size; i < len; i += page_size) {
814 page_size = len - i;
815 if (page_size > nor->page_size)
816 page_size = nor->page_size;
817
b94ed087 818 ret = spi_nor_wait_till_ready(nor);
1d61dcb3
BN		 819 if (ret)
820 goto write_err;
821
b199489d
HS		 822 write_enable(nor);
823
824 nor->write(nor, to + i, page_size, retlen, buf + i);
825 }
826 }
827
dfa9c0cb 828 ret = spi_nor_wait_till_ready(nor);
b199489d
HS		 829write_err:
830 spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
1d61dcb3 831 return ret;
b199489d
HS		 832}
833
834static int macronix_quad_enable(struct spi_nor *nor)
835{
836 int ret, val;
837
838 val = read_sr(nor);
839 write_enable(nor);
840
841 nor->cmd_buf[0] = val | SR_QUAD_EN_MX;
b02e7f3e 842 nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
b199489d 843
b94ed087 844 if (spi_nor_wait_till_ready(nor))
b199489d
HS		 845 return 1;
846
847 ret = read_sr(nor);
848 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
849 dev_err(nor->dev, "Macronix Quad bit not set\n");
850 return -EINVAL;
851 }
852
853 return 0;
854}
855
856/*
857 * Write status Register and configuration register with 2 bytes
858 * The first byte will be written to the status register, while the
859 * second byte will be written to the configuration register.
860 * Return negative if error occured.
861 */
862static int write_sr_cr(struct spi_nor *nor, u16 val)
863{
864 nor->cmd_buf[0] = val & 0xff;
865 nor->cmd_buf[1] = (val >> 8);
866
b02e7f3e 867 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0);
b199489d
HS		 868}
869
870static int spansion_quad_enable(struct spi_nor *nor)
871{
872 int ret;
873 int quad_en = CR_QUAD_EN_SPAN << 8;
874
875 write_enable(nor);
876
877 ret = write_sr_cr(nor, quad_en);
878 if (ret < 0) {
879 dev_err(nor->dev,
880 "error while writing configuration register\n");
881 return -EINVAL;
882 }
883
884 /* read back and check it */
885 ret = read_cr(nor);
886 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
887 dev_err(nor->dev, "Spansion Quad bit not set\n");
888 return -EINVAL;
889 }
890
891 return 0;
892}
893
548cd3ab
BH		 894static int micron_quad_enable(struct spi_nor *nor)
895{
896 int ret;
897 u8 val;
898
899 ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
900 if (ret < 0) {
901 dev_err(nor->dev, "error %d reading EVCR\n", ret);
902 return ret;
903 }
904
905 write_enable(nor);
906
907 /* set EVCR, enable quad I/O */
908 nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON;
909 ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1, 0);
910 if (ret < 0) {
911 dev_err(nor->dev, "error while writing EVCR register\n");
912 return ret;
913 }
914
915 ret = spi_nor_wait_till_ready(nor);
916 if (ret)
917 return ret;
918
919 /* read EVCR and check it */
920 ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
921 if (ret < 0) {
922 dev_err(nor->dev, "error %d reading EVCR\n", ret);
923 return ret;
924 }
925 if (val & EVCR_QUAD_EN_MICRON) {
926 dev_err(nor->dev, "Micron EVCR Quad bit not clear\n");
927 return -EINVAL;
928 }
929
930 return 0;
931}
932
d928a259 933static int set_quad_mode(struct spi_nor *nor, struct flash_info *info)
b199489d
HS		 934{
935 int status;
936
d928a259 937 switch (JEDEC_MFR(info)) {
b199489d
HS		 938 case CFI_MFR_MACRONIX:
939 status = macronix_quad_enable(nor);
940 if (status) {
941 dev_err(nor->dev, "Macronix quad-read not enabled\n");
942 return -EINVAL;
943 }
944 return status;
548cd3ab
BH		 945 case CFI_MFR_ST:
946 status = micron_quad_enable(nor);
947 if (status) {
948 dev_err(nor->dev, "Micron quad-read not enabled\n");
949 return -EINVAL;
950 }
951 return status;
b199489d
HS		 952 default:
953 status = spansion_quad_enable(nor);
954 if (status) {
955 dev_err(nor->dev, "Spansion quad-read not enabled\n");
956 return -EINVAL;
957 }
958 return status;
959 }
960}
961
962static int spi_nor_check(struct spi_nor *nor)
963{
964 if (!nor->dev || !nor->read || !nor->write ||
965 !nor->read_reg || !nor->write_reg || !nor->erase) {
966 pr_err("spi-nor: please fill all the necessary fields!\n");
967 return -EINVAL;
968 }
969
b199489d
HS		 970 return 0;
971}
972
70f3ce05 973int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
b199489d 974{
70f3ce05 975 const struct spi_device_id *id = NULL;
b199489d 976 struct flash_info *info;
b199489d
HS		 977 struct device *dev = nor->dev;
978 struct mtd_info *mtd = nor->mtd;
979 struct device_node *np = dev->of_node;
980 int ret;
981 int i;
982
983 ret = spi_nor_check(nor);
984 if (ret)
985 return ret;
986
58c81957
RM		 987 /* Try to auto-detect if chip name wasn't specified */
988 if (!name)
989 id = spi_nor_read_id(nor);
990 else
991 id = spi_nor_match_id(name);
992 if (IS_ERR_OR_NULL(id))
70f3ce05
BH		 993 return -ENOENT;
994
b199489d
HS		 995 info = (void *)id->driver_data;
996
58c81957
RM		 997 /*
998 * If caller has specified name of flash model that can normally be
999 * detected using JEDEC, let's verify it.
1000 */
1001 if (name && info->id_len) {
b199489d
HS		 1002 const struct spi_device_id *jid;
1003
e66fcf72 1004 jid = spi_nor_read_id(nor);
b199489d
HS		 1005 if (IS_ERR(jid)) {
1006 return PTR_ERR(jid);
1007 } else if (jid != id) {
1008 /*
1009 * JEDEC knows better, so overwrite platform ID. We
1010 * can't trust partitions any longer, but we'll let
1011 * mtd apply them anyway, since some partitions may be
1012 * marked read-only, and we don't want to lose that
1013 * information, even if it's not 100% accurate.
1014 */
1015 dev_warn(dev, "found %s, expected %s\n",
1016 jid->name, id->name);
1017 id = jid;
1018 info = (void *)jid->driver_data;
1019 }
1020 }
1021
1022 mutex_init(&nor->lock);
1023
1024 /*
1025 * Atmel, SST and Intel/Numonyx serial nor tend to power
1026 * up with the software protection bits set
1027 */
1028
d928a259
HS		 1029 if (JEDEC_MFR(info) == CFI_MFR_ATMEL ||
1030 JEDEC_MFR(info) == CFI_MFR_INTEL ||
1031 JEDEC_MFR(info) == CFI_MFR_SST) {
b199489d
HS		 1032 write_enable(nor);
1033 write_sr(nor, 0);
1034 }
1035
32f1b7c8 1036 if (!mtd->name)
b199489d 1037 mtd->name = dev_name(dev);
b199489d
HS		 1038 mtd->type = MTD_NORFLASH;
1039 mtd->writesize = 1;
1040 mtd->flags = MTD_CAP_NORFLASH;
1041 mtd->size = info->sector_size * info->n_sectors;
1042 mtd->_erase = spi_nor_erase;
1043 mtd->_read = spi_nor_read;
1044
1045 /* nor protection support for STmicro chips */
d928a259 1046 if (JEDEC_MFR(info) == CFI_MFR_ST) {
b199489d
HS		 1047 mtd->_lock = spi_nor_lock;
1048 mtd->_unlock = spi_nor_unlock;
1049 }
1050
1051 /* sst nor chips use AAI word program */
1052 if (info->flags & SST_WRITE)
1053 mtd->_write = sst_write;
1054 else
1055 mtd->_write = spi_nor_write;
1056
51983b7d
BN		 1057 if (info->flags & USE_FSR)
1058 nor->flags |= SNOR_F_USE_FSR;
c14dedde 1059
57cf26c1 1060#ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
b199489d
HS		 1061 /* prefer "small sector" erase if possible */
1062 if (info->flags & SECT_4K) {
b02e7f3e 1063 nor->erase_opcode = SPINOR_OP_BE_4K;
b199489d
HS		 1064 mtd->erasesize = 4096;
1065 } else if (info->flags & SECT_4K_PMC) {
b02e7f3e 1066 nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
b199489d 1067 mtd->erasesize = 4096;
57cf26c1
RM		 1068 } else
1069#endif
1070 {
b02e7f3e 1071 nor->erase_opcode = SPINOR_OP_SE;
b199489d
HS		 1072 mtd->erasesize = info->sector_size;
1073 }
1074
1075 if (info->flags & SPI_NOR_NO_ERASE)
1076 mtd->flags |= MTD_NO_ERASE;
1077
1078 mtd->dev.parent = dev;
1079 nor->page_size = info->page_size;
1080 mtd->writebufsize = nor->page_size;
1081
1082 if (np) {
1083 /* If we were instantiated by DT, use it */
1084 if (of_property_read_bool(np, "m25p,fast-read"))
1085 nor->flash_read = SPI_NOR_FAST;
1086 else
1087 nor->flash_read = SPI_NOR_NORMAL;
1088 } else {
1089 /* If we weren't instantiated by DT, default to fast-read */
1090 nor->flash_read = SPI_NOR_FAST;
1091 }
1092
1093 /* Some devices cannot do fast-read, no matter what DT tells us */
1094 if (info->flags & SPI_NOR_NO_FR)
1095 nor->flash_read = SPI_NOR_NORMAL;
1096
1097 /* Quad/Dual-read mode takes precedence over fast/normal */
1098 if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
d928a259 1099 ret = set_quad_mode(nor, info);
b199489d
HS		 1100 if (ret) {
1101 dev_err(dev, "quad mode not supported\n");
1102 return ret;
1103 }
1104 nor->flash_read = SPI_NOR_QUAD;
1105 } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) {
1106 nor->flash_read = SPI_NOR_DUAL;
1107 }
1108
1109 /* Default commands */
1110 switch (nor->flash_read) {
1111 case SPI_NOR_QUAD:
58b89a1f 1112 nor->read_opcode = SPINOR_OP_READ_1_1_4;
b199489d
HS		 1113 break;
1114 case SPI_NOR_DUAL:
58b89a1f 1115 nor->read_opcode = SPINOR_OP_READ_1_1_2;
b199489d
HS		 1116 break;
1117 case SPI_NOR_FAST:
58b89a1f 1118 nor->read_opcode = SPINOR_OP_READ_FAST;
b199489d
HS		 1119 break;
1120 case SPI_NOR_NORMAL:
58b89a1f 1121 nor->read_opcode = SPINOR_OP_READ;
b199489d
HS		 1122 break;
1123 default:
1124 dev_err(dev, "No Read opcode defined\n");
1125 return -EINVAL;
1126 }
1127
b02e7f3e 1128 nor->program_opcode = SPINOR_OP_PP;
b199489d
HS		 1129
1130 if (info->addr_width)
1131 nor->addr_width = info->addr_width;
1132 else if (mtd->size > 0x1000000) {
1133 /* enable 4-byte addressing if the device exceeds 16MiB */
1134 nor->addr_width = 4;
d928a259 1135 if (JEDEC_MFR(info) == CFI_MFR_AMD) {
b199489d
HS		 1136 /* Dedicated 4-byte command set */
1137 switch (nor->flash_read) {
1138 case SPI_NOR_QUAD:
58b89a1f 1139 nor->read_opcode = SPINOR_OP_READ4_1_1_4;
b199489d
HS		 1140 break;
1141 case SPI_NOR_DUAL:
58b89a1f 1142 nor->read_opcode = SPINOR_OP_READ4_1_1_2;
b199489d
HS		 1143 break;
1144 case SPI_NOR_FAST:
58b89a1f 1145 nor->read_opcode = SPINOR_OP_READ4_FAST;
b199489d
HS		 1146 break;
1147 case SPI_NOR_NORMAL:
58b89a1f 1148 nor->read_opcode = SPINOR_OP_READ4;
b199489d
HS		 1149 break;
1150 }
b02e7f3e 1151 nor->program_opcode = SPINOR_OP_PP_4B;
b199489d 1152 /* No small sector erase for 4-byte command set */
b02e7f3e 1153 nor->erase_opcode = SPINOR_OP_SE_4B;
b199489d
HS		 1154 mtd->erasesize = info->sector_size;
1155 } else
d928a259 1156 set_4byte(nor, info, 1);
b199489d
HS		 1157 } else {
1158 nor->addr_width = 3;
1159 }
1160
1161 nor->read_dummy = spi_nor_read_dummy_cycles(nor);
1162
1163 dev_info(dev, "%s (%lld Kbytes)\n", id->name,
1164 (long long)mtd->size >> 10);
1165
1166 dev_dbg(dev,
1167 "mtd .name = %s, .size = 0x%llx (%lldMiB), "
1168 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1169 mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
1170 mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
1171
1172 if (mtd->numeraseregions)
1173 for (i = 0; i < mtd->numeraseregions; i++)
1174 dev_dbg(dev,
1175 "mtd.eraseregions[%d] = { .offset = 0x%llx, "
1176 ".erasesize = 0x%.8x (%uKiB), "
1177 ".numblocks = %d }\n",
1178 i, (long long)mtd->eraseregions[i].offset,
1179 mtd->eraseregions[i].erasesize,
1180 mtd->eraseregions[i].erasesize / 1024,
1181 mtd->eraseregions[i].numblocks);
1182 return 0;
1183}
b61834b0 1184EXPORT_SYMBOL_GPL(spi_nor_scan);
b199489d 1185
70f3ce05 1186static const struct spi_device_id *spi_nor_match_id(const char *name)
0d8c11c0
HS		 1187{
1188 const struct spi_device_id *id = spi_nor_ids;
1189
1190 while (id->name[0]) {
1191 if (!strcmp(name, id->name))
1192 return id;
1193 id++;
1194 }
1195 return NULL;
1196}
1197
b199489d
HS		 1198MODULE_LICENSE("GPL");
1199MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
1200MODULE_AUTHOR("Mike Lavender");
1201MODULE_DESCRIPTION("framework for SPI NOR");
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