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Commit | Line | Data |
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b199489d | 1 | /* |
8eabdd1e HS |
2 | * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with |
3 | * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c | |
4 | * | |
5 | * Copyright (C) 2005, Intec Automation Inc. | |
6 | * Copyright (C) 2014, Freescale Semiconductor, Inc. | |
b199489d HS |
7 | * |
8 | * This code is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/err.h> | |
14 | #include <linux/errno.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/mutex.h> | |
18 | #include <linux/math64.h> | |
19 | ||
20 | #include <linux/mtd/cfi.h> | |
21 | #include <linux/mtd/mtd.h> | |
22 | #include <linux/of_platform.h> | |
23 | #include <linux/spi/flash.h> | |
24 | #include <linux/mtd/spi-nor.h> | |
25 | ||
26 | /* Define max times to check status register before we give up. */ | |
27 | #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */ | |
28 | ||
d928a259 HS |
29 | #define SPI_NOR_MAX_ID_LEN 6 |
30 | ||
31 | struct flash_info { | |
32 | /* | |
33 | * This array stores the ID bytes. | |
34 | * The first three bytes are the JEDIC ID. | |
35 | * JEDEC ID zero means "no ID" (mostly older chips). | |
36 | */ | |
37 | u8 id[SPI_NOR_MAX_ID_LEN]; | |
38 | u8 id_len; | |
39 | ||
40 | /* The size listed here is what works with SPINOR_OP_SE, which isn't | |
41 | * necessarily called a "sector" by the vendor. | |
42 | */ | |
43 | unsigned sector_size; | |
44 | u16 n_sectors; | |
45 | ||
46 | u16 page_size; | |
47 | u16 addr_width; | |
48 | ||
49 | u16 flags; | |
50 | #define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */ | |
51 | #define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */ | |
52 | #define SST_WRITE 0x04 /* use SST byte programming */ | |
53 | #define SPI_NOR_NO_FR 0x08 /* Can't do fastread */ | |
54 | #define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */ | |
55 | #define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */ | |
56 | #define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */ | |
57 | #define USE_FSR 0x80 /* use flag status register */ | |
58 | }; | |
59 | ||
60 | #define JEDEC_MFR(info) ((info)->id[0]) | |
b199489d | 61 | |
70f3ce05 BH |
62 | static const struct spi_device_id *spi_nor_match_id(const char *name); |
63 | ||
b199489d HS |
64 | /* |
65 | * Read the status register, returning its value in the location | |
66 | * Return the status register value. | |
67 | * Returns negative if error occurred. | |
68 | */ | |
69 | static int read_sr(struct spi_nor *nor) | |
70 | { | |
71 | int ret; | |
72 | u8 val; | |
73 | ||
b02e7f3e | 74 | ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1); |
b199489d HS |
75 | if (ret < 0) { |
76 | pr_err("error %d reading SR\n", (int) ret); | |
77 | return ret; | |
78 | } | |
79 | ||
80 | return val; | |
81 | } | |
82 | ||
c14dedde | 83 | /* |
84 | * Read the flag status register, returning its value in the location | |
85 | * Return the status register value. | |
86 | * Returns negative if error occurred. | |
87 | */ | |
88 | static int read_fsr(struct spi_nor *nor) | |
89 | { | |
90 | int ret; | |
91 | u8 val; | |
92 | ||
93 | ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1); | |
94 | if (ret < 0) { | |
95 | pr_err("error %d reading FSR\n", ret); | |
96 | return ret; | |
97 | } | |
98 | ||
99 | return val; | |
100 | } | |
101 | ||
b199489d HS |
102 | /* |
103 | * Read configuration register, returning its value in the | |
104 | * location. Return the configuration register value. | |
105 | * Returns negative if error occured. | |
106 | */ | |
107 | static int read_cr(struct spi_nor *nor) | |
108 | { | |
109 | int ret; | |
110 | u8 val; | |
111 | ||
b02e7f3e | 112 | ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1); |
b199489d HS |
113 | if (ret < 0) { |
114 | dev_err(nor->dev, "error %d reading CR\n", ret); | |
115 | return ret; | |
116 | } | |
117 | ||
118 | return val; | |
119 | } | |
120 | ||
121 | /* | |
122 | * Dummy Cycle calculation for different type of read. | |
123 | * It can be used to support more commands with | |
124 | * different dummy cycle requirements. | |
125 | */ | |
126 | static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor) | |
127 | { | |
128 | switch (nor->flash_read) { | |
129 | case SPI_NOR_FAST: | |
130 | case SPI_NOR_DUAL: | |
131 | case SPI_NOR_QUAD: | |
0b78a2cf | 132 | return 8; |
b199489d HS |
133 | case SPI_NOR_NORMAL: |
134 | return 0; | |
135 | } | |
136 | return 0; | |
137 | } | |
138 | ||
139 | /* | |
140 | * Write status register 1 byte | |
141 | * Returns negative if error occurred. | |
142 | */ | |
143 | static inline int write_sr(struct spi_nor *nor, u8 val) | |
144 | { | |
145 | nor->cmd_buf[0] = val; | |
b02e7f3e | 146 | return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0); |
b199489d HS |
147 | } |
148 | ||
149 | /* | |
150 | * Set write enable latch with Write Enable command. | |
151 | * Returns negative if error occurred. | |
152 | */ | |
153 | static inline int write_enable(struct spi_nor *nor) | |
154 | { | |
b02e7f3e | 155 | return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0); |
b199489d HS |
156 | } |
157 | ||
158 | /* | |
159 | * Send write disble instruction to the chip. | |
160 | */ | |
161 | static inline int write_disable(struct spi_nor *nor) | |
162 | { | |
b02e7f3e | 163 | return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0); |
b199489d HS |
164 | } |
165 | ||
166 | static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) | |
167 | { | |
168 | return mtd->priv; | |
169 | } | |
170 | ||
171 | /* Enable/disable 4-byte addressing mode. */ | |
d928a259 HS |
172 | static inline int set_4byte(struct spi_nor *nor, struct flash_info *info, |
173 | int enable) | |
b199489d HS |
174 | { |
175 | int status; | |
176 | bool need_wren = false; | |
177 | u8 cmd; | |
178 | ||
d928a259 | 179 | switch (JEDEC_MFR(info)) { |
b199489d HS |
180 | case CFI_MFR_ST: /* Micron, actually */ |
181 | /* Some Micron need WREN command; all will accept it */ | |
182 | need_wren = true; | |
183 | case CFI_MFR_MACRONIX: | |
184 | case 0xEF /* winbond */: | |
185 | if (need_wren) | |
186 | write_enable(nor); | |
187 | ||
b02e7f3e | 188 | cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; |
b199489d HS |
189 | status = nor->write_reg(nor, cmd, NULL, 0, 0); |
190 | if (need_wren) | |
191 | write_disable(nor); | |
192 | ||
193 | return status; | |
194 | default: | |
195 | /* Spansion style */ | |
196 | nor->cmd_buf[0] = enable << 7; | |
b02e7f3e | 197 | return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0); |
b199489d HS |
198 | } |
199 | } | |
51983b7d | 200 | static inline int spi_nor_sr_ready(struct spi_nor *nor) |
b199489d | 201 | { |
51983b7d BN |
202 | int sr = read_sr(nor); |
203 | if (sr < 0) | |
204 | return sr; | |
205 | else | |
206 | return !(sr & SR_WIP); | |
207 | } | |
b199489d | 208 | |
51983b7d BN |
209 | static inline int spi_nor_fsr_ready(struct spi_nor *nor) |
210 | { | |
211 | int fsr = read_fsr(nor); | |
212 | if (fsr < 0) | |
213 | return fsr; | |
214 | else | |
215 | return fsr & FSR_READY; | |
216 | } | |
b199489d | 217 | |
51983b7d BN |
218 | static int spi_nor_ready(struct spi_nor *nor) |
219 | { | |
220 | int sr, fsr; | |
221 | sr = spi_nor_sr_ready(nor); | |
222 | if (sr < 0) | |
223 | return sr; | |
224 | fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; | |
225 | if (fsr < 0) | |
226 | return fsr; | |
227 | return sr && fsr; | |
b199489d HS |
228 | } |
229 | ||
b94ed087 BN |
230 | /* |
231 | * Service routine to read status register until ready, or timeout occurs. | |
232 | * Returns non-zero if error. | |
233 | */ | |
51983b7d | 234 | static int spi_nor_wait_till_ready(struct spi_nor *nor) |
c14dedde | 235 | { |
236 | unsigned long deadline; | |
a95ce92e | 237 | int timeout = 0, ret; |
c14dedde | 238 | |
239 | deadline = jiffies + MAX_READY_WAIT_JIFFIES; | |
240 | ||
a95ce92e BN |
241 | while (!timeout) { |
242 | if (time_after_eq(jiffies, deadline)) | |
243 | timeout = 1; | |
c14dedde | 244 | |
51983b7d BN |
245 | ret = spi_nor_ready(nor); |
246 | if (ret < 0) | |
247 | return ret; | |
248 | if (ret) | |
249 | return 0; | |
a95ce92e BN |
250 | |
251 | cond_resched(); | |
252 | } | |
253 | ||
254 | dev_err(nor->dev, "flash operation timed out\n"); | |
c14dedde | 255 | |
256 | return -ETIMEDOUT; | |
257 | } | |
258 | ||
b199489d HS |
259 | /* |
260 | * Erase the whole flash memory | |
261 | * | |
262 | * Returns 0 if successful, non-zero otherwise. | |
263 | */ | |
264 | static int erase_chip(struct spi_nor *nor) | |
265 | { | |
b199489d HS |
266 | dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd->size >> 10)); |
267 | ||
b02e7f3e | 268 | return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0); |
b199489d HS |
269 | } |
270 | ||
271 | static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops) | |
272 | { | |
273 | int ret = 0; | |
274 | ||
275 | mutex_lock(&nor->lock); | |
276 | ||
277 | if (nor->prepare) { | |
278 | ret = nor->prepare(nor, ops); | |
279 | if (ret) { | |
280 | dev_err(nor->dev, "failed in the preparation.\n"); | |
281 | mutex_unlock(&nor->lock); | |
282 | return ret; | |
283 | } | |
284 | } | |
285 | return ret; | |
286 | } | |
287 | ||
288 | static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops) | |
289 | { | |
290 | if (nor->unprepare) | |
291 | nor->unprepare(nor, ops); | |
292 | mutex_unlock(&nor->lock); | |
293 | } | |
294 | ||
295 | /* | |
296 | * Erase an address range on the nor chip. The address range may extend | |
297 | * one or more erase sectors. Return an error is there is a problem erasing. | |
298 | */ | |
299 | static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) | |
300 | { | |
301 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
302 | u32 addr, len; | |
303 | uint32_t rem; | |
304 | int ret; | |
305 | ||
306 | dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, | |
307 | (long long)instr->len); | |
308 | ||
309 | div_u64_rem(instr->len, mtd->erasesize, &rem); | |
310 | if (rem) | |
311 | return -EINVAL; | |
312 | ||
313 | addr = instr->addr; | |
314 | len = instr->len; | |
315 | ||
316 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE); | |
317 | if (ret) | |
318 | return ret; | |
319 | ||
320 | /* whole-chip erase? */ | |
321 | if (len == mtd->size) { | |
05241aea BN |
322 | write_enable(nor); |
323 | ||
b199489d HS |
324 | if (erase_chip(nor)) { |
325 | ret = -EIO; | |
326 | goto erase_err; | |
327 | } | |
328 | ||
dfa9c0cb BN |
329 | ret = spi_nor_wait_till_ready(nor); |
330 | if (ret) | |
331 | goto erase_err; | |
332 | ||
b199489d | 333 | /* REVISIT in some cases we could speed up erasing large regions |
b02e7f3e | 334 | * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up |
b199489d HS |
335 | * to use "small sector erase", but that's not always optimal. |
336 | */ | |
337 | ||
338 | /* "sector"-at-a-time erase */ | |
339 | } else { | |
340 | while (len) { | |
05241aea BN |
341 | write_enable(nor); |
342 | ||
b199489d HS |
343 | if (nor->erase(nor, addr)) { |
344 | ret = -EIO; | |
345 | goto erase_err; | |
346 | } | |
347 | ||
348 | addr += mtd->erasesize; | |
349 | len -= mtd->erasesize; | |
dfa9c0cb BN |
350 | |
351 | ret = spi_nor_wait_till_ready(nor); | |
352 | if (ret) | |
353 | goto erase_err; | |
b199489d HS |
354 | } |
355 | } | |
356 | ||
05241aea BN |
357 | write_disable(nor); |
358 | ||
b199489d HS |
359 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); |
360 | ||
361 | instr->state = MTD_ERASE_DONE; | |
362 | mtd_erase_callback(instr); | |
363 | ||
364 | return ret; | |
365 | ||
366 | erase_err: | |
367 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); | |
368 | instr->state = MTD_ERASE_FAILED; | |
369 | return ret; | |
370 | } | |
371 | ||
8cc7f33a | 372 | static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) |
b199489d | 373 | { |
8cc7f33a | 374 | struct mtd_info *mtd = nor->mtd; |
b199489d HS |
375 | uint32_t offset = ofs; |
376 | uint8_t status_old, status_new; | |
377 | int ret = 0; | |
378 | ||
b199489d HS |
379 | status_old = read_sr(nor); |
380 | ||
381 | if (offset < mtd->size - (mtd->size / 2)) | |
382 | status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0; | |
383 | else if (offset < mtd->size - (mtd->size / 4)) | |
384 | status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1; | |
385 | else if (offset < mtd->size - (mtd->size / 8)) | |
386 | status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0; | |
387 | else if (offset < mtd->size - (mtd->size / 16)) | |
388 | status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2; | |
389 | else if (offset < mtd->size - (mtd->size / 32)) | |
390 | status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0; | |
391 | else if (offset < mtd->size - (mtd->size / 64)) | |
392 | status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1; | |
393 | else | |
394 | status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0; | |
395 | ||
396 | /* Only modify protection if it will not unlock other areas */ | |
397 | if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) > | |
398 | (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) { | |
399 | write_enable(nor); | |
400 | ret = write_sr(nor, status_new); | |
b199489d HS |
401 | } |
402 | ||
b199489d HS |
403 | return ret; |
404 | } | |
405 | ||
8cc7f33a | 406 | static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) |
b199489d | 407 | { |
8cc7f33a | 408 | struct mtd_info *mtd = nor->mtd; |
b199489d HS |
409 | uint32_t offset = ofs; |
410 | uint8_t status_old, status_new; | |
411 | int ret = 0; | |
412 | ||
b199489d HS |
413 | status_old = read_sr(nor); |
414 | ||
415 | if (offset+len > mtd->size - (mtd->size / 64)) | |
416 | status_new = status_old & ~(SR_BP2 | SR_BP1 | SR_BP0); | |
417 | else if (offset+len > mtd->size - (mtd->size / 32)) | |
418 | status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0; | |
419 | else if (offset+len > mtd->size - (mtd->size / 16)) | |
420 | status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1; | |
421 | else if (offset+len > mtd->size - (mtd->size / 8)) | |
422 | status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0; | |
423 | else if (offset+len > mtd->size - (mtd->size / 4)) | |
424 | status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2; | |
425 | else if (offset+len > mtd->size - (mtd->size / 2)) | |
426 | status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0; | |
427 | else | |
428 | status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1; | |
429 | ||
430 | /* Only modify protection if it will not lock other areas */ | |
431 | if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) < | |
432 | (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) { | |
433 | write_enable(nor); | |
434 | ret = write_sr(nor, status_new); | |
b199489d HS |
435 | } |
436 | ||
8cc7f33a BN |
437 | return ret; |
438 | } | |
439 | ||
440 | static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) | |
441 | { | |
442 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
443 | int ret; | |
444 | ||
445 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK); | |
446 | if (ret) | |
447 | return ret; | |
448 | ||
449 | ret = nor->flash_lock(nor, ofs, len); | |
450 | ||
b199489d HS |
451 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK); |
452 | return ret; | |
453 | } | |
454 | ||
8cc7f33a BN |
455 | static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
456 | { | |
457 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
458 | int ret; | |
459 | ||
460 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK); | |
461 | if (ret) | |
462 | return ret; | |
463 | ||
464 | ret = nor->flash_unlock(nor, ofs, len); | |
465 | ||
466 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK); | |
467 | return ret; | |
468 | } | |
469 | ||
09ffafb6 | 470 | /* Used when the "_ext_id" is two bytes at most */ |
b199489d HS |
471 | #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
472 | ((kernel_ulong_t)&(struct flash_info) { \ | |
09ffafb6 HS |
473 | .id = { \ |
474 | ((_jedec_id) >> 16) & 0xff, \ | |
475 | ((_jedec_id) >> 8) & 0xff, \ | |
476 | (_jedec_id) & 0xff, \ | |
477 | ((_ext_id) >> 8) & 0xff, \ | |
478 | (_ext_id) & 0xff, \ | |
479 | }, \ | |
480 | .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ | |
b199489d HS |
481 | .sector_size = (_sector_size), \ |
482 | .n_sectors = (_n_sectors), \ | |
483 | .page_size = 256, \ | |
484 | .flags = (_flags), \ | |
485 | }) | |
486 | ||
6d7604e5 HS |
487 | #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
488 | ((kernel_ulong_t)&(struct flash_info) { \ | |
489 | .id = { \ | |
490 | ((_jedec_id) >> 16) & 0xff, \ | |
491 | ((_jedec_id) >> 8) & 0xff, \ | |
492 | (_jedec_id) & 0xff, \ | |
493 | ((_ext_id) >> 16) & 0xff, \ | |
494 | ((_ext_id) >> 8) & 0xff, \ | |
495 | (_ext_id) & 0xff, \ | |
496 | }, \ | |
497 | .id_len = 6, \ | |
498 | .sector_size = (_sector_size), \ | |
499 | .n_sectors = (_n_sectors), \ | |
500 | .page_size = 256, \ | |
501 | .flags = (_flags), \ | |
502 | }) | |
503 | ||
b199489d HS |
504 | #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \ |
505 | ((kernel_ulong_t)&(struct flash_info) { \ | |
506 | .sector_size = (_sector_size), \ | |
507 | .n_sectors = (_n_sectors), \ | |
508 | .page_size = (_page_size), \ | |
509 | .addr_width = (_addr_width), \ | |
510 | .flags = (_flags), \ | |
511 | }) | |
512 | ||
513 | /* NOTE: double check command sets and memory organization when you add | |
514 | * more nor chips. This current list focusses on newer chips, which | |
515 | * have been converging on command sets which including JEDEC ID. | |
516 | */ | |
a5b7616c | 517 | static const struct spi_device_id spi_nor_ids[] = { |
b199489d HS |
518 | /* Atmel -- some are (confusingly) marketed as "DataFlash" */ |
519 | { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) }, | |
520 | { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) }, | |
521 | ||
522 | { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) }, | |
523 | { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, | |
524 | { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) }, | |
525 | ||
526 | { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) }, | |
527 | { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, | |
528 | { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) }, | |
529 | { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, | |
530 | ||
531 | { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, | |
532 | ||
533 | /* EON -- en25xxx */ | |
534 | { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, | |
535 | { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, | |
536 | { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) }, | |
537 | { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) }, | |
538 | { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, | |
a41595b3 | 539 | { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) }, |
b199489d | 540 | { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) }, |
072b56ab | 541 | { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, 0) }, |
b199489d HS |
542 | |
543 | /* ESMT */ | |
544 | { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) }, | |
545 | ||
546 | /* Everspin */ | |
547 | { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
548 | { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
549 | ||
ce56ce7d RL |
550 | /* Fujitsu */ |
551 | { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) }, | |
552 | ||
b199489d HS |
553 | /* GigaDevice */ |
554 | { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) }, | |
555 | { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) }, | |
fcc87a95 | 556 | { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K) }, |
b199489d HS |
557 | |
558 | /* Intel/Numonyx -- xxxs33b */ | |
559 | { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) }, | |
560 | { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, | |
561 | { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, | |
562 | ||
563 | /* Macronix */ | |
564 | { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, | |
565 | { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, | |
566 | { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, | |
567 | { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, | |
568 | { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) }, | |
569 | { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) }, | |
570 | { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) }, | |
81a1209c | 571 | { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) }, |
b199489d HS |
572 | { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, |
573 | { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, | |
574 | { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) }, | |
575 | { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, | |
576 | { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) }, | |
577 | { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) }, | |
578 | ||
579 | /* Micron */ | |
548cd3ab BH |
580 | { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, |
581 | { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ) }, | |
582 | { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, | |
583 | { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, | |
584 | { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, | |
585 | { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, | |
586 | { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, | |
587 | { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, | |
b199489d HS |
588 | |
589 | /* PMC */ | |
590 | { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) }, | |
591 | { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) }, | |
592 | { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) }, | |
593 | ||
594 | /* Spansion -- single (large) sector size only, at least | |
595 | * for the chips listed here (without boot sectors). | |
596 | */ | |
9ab86995 | 597 | { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
b199489d HS |
598 | { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) }, |
599 | { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) }, | |
600 | { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
601 | { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
602 | { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, | |
603 | { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, | |
604 | { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, | |
6d7604e5 | 605 | { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, |
b199489d HS |
606 | { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) }, |
607 | { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) }, | |
608 | { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, | |
609 | { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, | |
610 | { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, | |
611 | { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, | |
612 | { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, | |
613 | { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, | |
614 | { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) }, | |
615 | { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, | |
3e38933d | 616 | { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, 0) }, |
b199489d HS |
617 | |
618 | /* SST -- large erase sizes are "overlays", "sectors" are 4K */ | |
619 | { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, | |
620 | { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, | |
621 | { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, | |
622 | { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, | |
623 | { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, | |
624 | { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, | |
625 | { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, | |
626 | { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, | |
627 | { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, | |
f02985b7 | 628 | { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, |
b199489d HS |
629 | |
630 | /* ST Microelectronics -- newer production may have feature updates */ | |
631 | { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) }, | |
632 | { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) }, | |
633 | { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) }, | |
634 | { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) }, | |
635 | { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) }, | |
636 | { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) }, | |
637 | { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) }, | |
638 | { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) }, | |
639 | { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) }, | |
b199489d HS |
640 | |
641 | { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) }, | |
642 | { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) }, | |
643 | { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) }, | |
644 | { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) }, | |
645 | { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) }, | |
646 | { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) }, | |
647 | { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) }, | |
648 | { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) }, | |
649 | { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) }, | |
650 | ||
651 | { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) }, | |
652 | { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) }, | |
653 | { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) }, | |
654 | ||
655 | { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) }, | |
656 | { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) }, | |
657 | { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) }, | |
658 | ||
659 | { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) }, | |
660 | { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) }, | |
661 | { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) }, | |
662 | { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) }, | |
663 | { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) }, | |
f2fabe16 | 664 | { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) }, |
b199489d HS |
665 | |
666 | /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ | |
40d19ab6 | 667 | { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) }, |
b199489d HS |
668 | { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, |
669 | { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, | |
670 | { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, | |
671 | { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, | |
672 | { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, | |
673 | { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, | |
674 | { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, | |
675 | { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) }, | |
676 | { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, | |
677 | { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, | |
e88e567f | 678 | { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K) }, |
b199489d HS |
679 | { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, |
680 | { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, | |
681 | { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, | |
682 | { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) }, | |
683 | ||
684 | /* Catalyst / On Semiconductor -- non-JEDEC */ | |
685 | { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
686 | { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
687 | { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
688 | { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
689 | { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
690 | { }, | |
691 | }; | |
692 | ||
693 | static const struct spi_device_id *spi_nor_read_id(struct spi_nor *nor) | |
694 | { | |
695 | int tmp; | |
09ffafb6 | 696 | u8 id[SPI_NOR_MAX_ID_LEN]; |
b199489d HS |
697 | struct flash_info *info; |
698 | ||
09ffafb6 | 699 | tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); |
b199489d HS |
700 | if (tmp < 0) { |
701 | dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp); | |
702 | return ERR_PTR(tmp); | |
703 | } | |
b199489d HS |
704 | |
705 | for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) { | |
706 | info = (void *)spi_nor_ids[tmp].driver_data; | |
09ffafb6 HS |
707 | if (info->id_len) { |
708 | if (!memcmp(info->id, id, info->id_len)) | |
b199489d HS |
709 | return &spi_nor_ids[tmp]; |
710 | } | |
711 | } | |
09ffafb6 HS |
712 | dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %2x, %2x\n", |
713 | id[0], id[1], id[2]); | |
b199489d HS |
714 | return ERR_PTR(-ENODEV); |
715 | } | |
716 | ||
b199489d HS |
717 | static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, |
718 | size_t *retlen, u_char *buf) | |
719 | { | |
720 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
721 | int ret; | |
722 | ||
723 | dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); | |
724 | ||
725 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ); | |
726 | if (ret) | |
727 | return ret; | |
728 | ||
729 | ret = nor->read(nor, from, len, retlen, buf); | |
730 | ||
731 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ); | |
732 | return ret; | |
733 | } | |
734 | ||
735 | static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, | |
736 | size_t *retlen, const u_char *buf) | |
737 | { | |
738 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
739 | size_t actual; | |
740 | int ret; | |
741 | ||
742 | dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); | |
743 | ||
744 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE); | |
745 | if (ret) | |
746 | return ret; | |
747 | ||
b199489d HS |
748 | write_enable(nor); |
749 | ||
750 | nor->sst_write_second = false; | |
751 | ||
752 | actual = to % 2; | |
753 | /* Start write from odd address. */ | |
754 | if (actual) { | |
b02e7f3e | 755 | nor->program_opcode = SPINOR_OP_BP; |
b199489d HS |
756 | |
757 | /* write one byte. */ | |
758 | nor->write(nor, to, 1, retlen, buf); | |
b94ed087 | 759 | ret = spi_nor_wait_till_ready(nor); |
b199489d HS |
760 | if (ret) |
761 | goto time_out; | |
762 | } | |
763 | to += actual; | |
764 | ||
765 | /* Write out most of the data here. */ | |
766 | for (; actual < len - 1; actual += 2) { | |
b02e7f3e | 767 | nor->program_opcode = SPINOR_OP_AAI_WP; |
b199489d HS |
768 | |
769 | /* write two bytes. */ | |
770 | nor->write(nor, to, 2, retlen, buf + actual); | |
b94ed087 | 771 | ret = spi_nor_wait_till_ready(nor); |
b199489d HS |
772 | if (ret) |
773 | goto time_out; | |
774 | to += 2; | |
775 | nor->sst_write_second = true; | |
776 | } | |
777 | nor->sst_write_second = false; | |
778 | ||
779 | write_disable(nor); | |
b94ed087 | 780 | ret = spi_nor_wait_till_ready(nor); |
b199489d HS |
781 | if (ret) |
782 | goto time_out; | |
783 | ||
784 | /* Write out trailing byte if it exists. */ | |
785 | if (actual != len) { | |
786 | write_enable(nor); | |
787 | ||
b02e7f3e | 788 | nor->program_opcode = SPINOR_OP_BP; |
b199489d HS |
789 | nor->write(nor, to, 1, retlen, buf + actual); |
790 | ||
b94ed087 | 791 | ret = spi_nor_wait_till_ready(nor); |
b199489d HS |
792 | if (ret) |
793 | goto time_out; | |
794 | write_disable(nor); | |
795 | } | |
796 | time_out: | |
797 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE); | |
798 | return ret; | |
799 | } | |
800 | ||
801 | /* | |
802 | * Write an address range to the nor chip. Data must be written in | |
803 | * FLASH_PAGESIZE chunks. The address range may be any size provided | |
804 | * it is within the physical boundaries. | |
805 | */ | |
806 | static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, | |
807 | size_t *retlen, const u_char *buf) | |
808 | { | |
809 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
810 | u32 page_offset, page_size, i; | |
811 | int ret; | |
812 | ||
813 | dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); | |
814 | ||
815 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE); | |
816 | if (ret) | |
817 | return ret; | |
818 | ||
b199489d HS |
819 | write_enable(nor); |
820 | ||
821 | page_offset = to & (nor->page_size - 1); | |
822 | ||
823 | /* do all the bytes fit onto one page? */ | |
824 | if (page_offset + len <= nor->page_size) { | |
825 | nor->write(nor, to, len, retlen, buf); | |
826 | } else { | |
827 | /* the size of data remaining on the first page */ | |
828 | page_size = nor->page_size - page_offset; | |
829 | nor->write(nor, to, page_size, retlen, buf); | |
830 | ||
831 | /* write everything in nor->page_size chunks */ | |
832 | for (i = page_size; i < len; i += page_size) { | |
833 | page_size = len - i; | |
834 | if (page_size > nor->page_size) | |
835 | page_size = nor->page_size; | |
836 | ||
b94ed087 | 837 | ret = spi_nor_wait_till_ready(nor); |
1d61dcb3 BN |
838 | if (ret) |
839 | goto write_err; | |
840 | ||
b199489d HS |
841 | write_enable(nor); |
842 | ||
843 | nor->write(nor, to + i, page_size, retlen, buf + i); | |
844 | } | |
845 | } | |
846 | ||
dfa9c0cb | 847 | ret = spi_nor_wait_till_ready(nor); |
b199489d HS |
848 | write_err: |
849 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE); | |
1d61dcb3 | 850 | return ret; |
b199489d HS |
851 | } |
852 | ||
853 | static int macronix_quad_enable(struct spi_nor *nor) | |
854 | { | |
855 | int ret, val; | |
856 | ||
857 | val = read_sr(nor); | |
858 | write_enable(nor); | |
859 | ||
860 | nor->cmd_buf[0] = val | SR_QUAD_EN_MX; | |
b02e7f3e | 861 | nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0); |
b199489d | 862 | |
b94ed087 | 863 | if (spi_nor_wait_till_ready(nor)) |
b199489d HS |
864 | return 1; |
865 | ||
866 | ret = read_sr(nor); | |
867 | if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) { | |
868 | dev_err(nor->dev, "Macronix Quad bit not set\n"); | |
869 | return -EINVAL; | |
870 | } | |
871 | ||
872 | return 0; | |
873 | } | |
874 | ||
875 | /* | |
876 | * Write status Register and configuration register with 2 bytes | |
877 | * The first byte will be written to the status register, while the | |
878 | * second byte will be written to the configuration register. | |
879 | * Return negative if error occured. | |
880 | */ | |
881 | static int write_sr_cr(struct spi_nor *nor, u16 val) | |
882 | { | |
883 | nor->cmd_buf[0] = val & 0xff; | |
884 | nor->cmd_buf[1] = (val >> 8); | |
885 | ||
b02e7f3e | 886 | return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0); |
b199489d HS |
887 | } |
888 | ||
889 | static int spansion_quad_enable(struct spi_nor *nor) | |
890 | { | |
891 | int ret; | |
892 | int quad_en = CR_QUAD_EN_SPAN << 8; | |
893 | ||
894 | write_enable(nor); | |
895 | ||
896 | ret = write_sr_cr(nor, quad_en); | |
897 | if (ret < 0) { | |
898 | dev_err(nor->dev, | |
899 | "error while writing configuration register\n"); | |
900 | return -EINVAL; | |
901 | } | |
902 | ||
903 | /* read back and check it */ | |
904 | ret = read_cr(nor); | |
905 | if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) { | |
906 | dev_err(nor->dev, "Spansion Quad bit not set\n"); | |
907 | return -EINVAL; | |
908 | } | |
909 | ||
910 | return 0; | |
911 | } | |
912 | ||
548cd3ab BH |
913 | static int micron_quad_enable(struct spi_nor *nor) |
914 | { | |
915 | int ret; | |
916 | u8 val; | |
917 | ||
918 | ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1); | |
919 | if (ret < 0) { | |
920 | dev_err(nor->dev, "error %d reading EVCR\n", ret); | |
921 | return ret; | |
922 | } | |
923 | ||
924 | write_enable(nor); | |
925 | ||
926 | /* set EVCR, enable quad I/O */ | |
927 | nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON; | |
928 | ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1, 0); | |
929 | if (ret < 0) { | |
930 | dev_err(nor->dev, "error while writing EVCR register\n"); | |
931 | return ret; | |
932 | } | |
933 | ||
934 | ret = spi_nor_wait_till_ready(nor); | |
935 | if (ret) | |
936 | return ret; | |
937 | ||
938 | /* read EVCR and check it */ | |
939 | ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1); | |
940 | if (ret < 0) { | |
941 | dev_err(nor->dev, "error %d reading EVCR\n", ret); | |
942 | return ret; | |
943 | } | |
944 | if (val & EVCR_QUAD_EN_MICRON) { | |
945 | dev_err(nor->dev, "Micron EVCR Quad bit not clear\n"); | |
946 | return -EINVAL; | |
947 | } | |
948 | ||
949 | return 0; | |
950 | } | |
951 | ||
d928a259 | 952 | static int set_quad_mode(struct spi_nor *nor, struct flash_info *info) |
b199489d HS |
953 | { |
954 | int status; | |
955 | ||
d928a259 | 956 | switch (JEDEC_MFR(info)) { |
b199489d HS |
957 | case CFI_MFR_MACRONIX: |
958 | status = macronix_quad_enable(nor); | |
959 | if (status) { | |
960 | dev_err(nor->dev, "Macronix quad-read not enabled\n"); | |
961 | return -EINVAL; | |
962 | } | |
963 | return status; | |
548cd3ab BH |
964 | case CFI_MFR_ST: |
965 | status = micron_quad_enable(nor); | |
966 | if (status) { | |
967 | dev_err(nor->dev, "Micron quad-read not enabled\n"); | |
968 | return -EINVAL; | |
969 | } | |
970 | return status; | |
b199489d HS |
971 | default: |
972 | status = spansion_quad_enable(nor); | |
973 | if (status) { | |
974 | dev_err(nor->dev, "Spansion quad-read not enabled\n"); | |
975 | return -EINVAL; | |
976 | } | |
977 | return status; | |
978 | } | |
979 | } | |
980 | ||
981 | static int spi_nor_check(struct spi_nor *nor) | |
982 | { | |
983 | if (!nor->dev || !nor->read || !nor->write || | |
984 | !nor->read_reg || !nor->write_reg || !nor->erase) { | |
985 | pr_err("spi-nor: please fill all the necessary fields!\n"); | |
986 | return -EINVAL; | |
987 | } | |
988 | ||
b199489d HS |
989 | return 0; |
990 | } | |
991 | ||
70f3ce05 | 992 | int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) |
b199489d | 993 | { |
70f3ce05 | 994 | const struct spi_device_id *id = NULL; |
b199489d | 995 | struct flash_info *info; |
b199489d HS |
996 | struct device *dev = nor->dev; |
997 | struct mtd_info *mtd = nor->mtd; | |
998 | struct device_node *np = dev->of_node; | |
999 | int ret; | |
1000 | int i; | |
1001 | ||
1002 | ret = spi_nor_check(nor); | |
1003 | if (ret) | |
1004 | return ret; | |
1005 | ||
58c81957 RM |
1006 | /* Try to auto-detect if chip name wasn't specified */ |
1007 | if (!name) | |
1008 | id = spi_nor_read_id(nor); | |
1009 | else | |
1010 | id = spi_nor_match_id(name); | |
1011 | if (IS_ERR_OR_NULL(id)) | |
70f3ce05 BH |
1012 | return -ENOENT; |
1013 | ||
b199489d HS |
1014 | info = (void *)id->driver_data; |
1015 | ||
58c81957 RM |
1016 | /* |
1017 | * If caller has specified name of flash model that can normally be | |
1018 | * detected using JEDEC, let's verify it. | |
1019 | */ | |
1020 | if (name && info->id_len) { | |
b199489d HS |
1021 | const struct spi_device_id *jid; |
1022 | ||
e66fcf72 | 1023 | jid = spi_nor_read_id(nor); |
b199489d HS |
1024 | if (IS_ERR(jid)) { |
1025 | return PTR_ERR(jid); | |
1026 | } else if (jid != id) { | |
1027 | /* | |
1028 | * JEDEC knows better, so overwrite platform ID. We | |
1029 | * can't trust partitions any longer, but we'll let | |
1030 | * mtd apply them anyway, since some partitions may be | |
1031 | * marked read-only, and we don't want to lose that | |
1032 | * information, even if it's not 100% accurate. | |
1033 | */ | |
1034 | dev_warn(dev, "found %s, expected %s\n", | |
1035 | jid->name, id->name); | |
1036 | id = jid; | |
1037 | info = (void *)jid->driver_data; | |
1038 | } | |
1039 | } | |
1040 | ||
1041 | mutex_init(&nor->lock); | |
1042 | ||
1043 | /* | |
1044 | * Atmel, SST and Intel/Numonyx serial nor tend to power | |
1045 | * up with the software protection bits set | |
1046 | */ | |
1047 | ||
d928a259 HS |
1048 | if (JEDEC_MFR(info) == CFI_MFR_ATMEL || |
1049 | JEDEC_MFR(info) == CFI_MFR_INTEL || | |
1050 | JEDEC_MFR(info) == CFI_MFR_SST) { | |
b199489d HS |
1051 | write_enable(nor); |
1052 | write_sr(nor, 0); | |
1053 | } | |
1054 | ||
32f1b7c8 | 1055 | if (!mtd->name) |
b199489d | 1056 | mtd->name = dev_name(dev); |
b199489d HS |
1057 | mtd->type = MTD_NORFLASH; |
1058 | mtd->writesize = 1; | |
1059 | mtd->flags = MTD_CAP_NORFLASH; | |
1060 | mtd->size = info->sector_size * info->n_sectors; | |
1061 | mtd->_erase = spi_nor_erase; | |
1062 | mtd->_read = spi_nor_read; | |
1063 | ||
1064 | /* nor protection support for STmicro chips */ | |
d928a259 | 1065 | if (JEDEC_MFR(info) == CFI_MFR_ST) { |
8cc7f33a BN |
1066 | nor->flash_lock = stm_lock; |
1067 | nor->flash_unlock = stm_unlock; | |
1068 | } | |
1069 | ||
1070 | if (nor->flash_lock && nor->flash_unlock) { | |
b199489d HS |
1071 | mtd->_lock = spi_nor_lock; |
1072 | mtd->_unlock = spi_nor_unlock; | |
1073 | } | |
1074 | ||
1075 | /* sst nor chips use AAI word program */ | |
1076 | if (info->flags & SST_WRITE) | |
1077 | mtd->_write = sst_write; | |
1078 | else | |
1079 | mtd->_write = spi_nor_write; | |
1080 | ||
51983b7d BN |
1081 | if (info->flags & USE_FSR) |
1082 | nor->flags |= SNOR_F_USE_FSR; | |
c14dedde | 1083 | |
57cf26c1 | 1084 | #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS |
b199489d HS |
1085 | /* prefer "small sector" erase if possible */ |
1086 | if (info->flags & SECT_4K) { | |
b02e7f3e | 1087 | nor->erase_opcode = SPINOR_OP_BE_4K; |
b199489d HS |
1088 | mtd->erasesize = 4096; |
1089 | } else if (info->flags & SECT_4K_PMC) { | |
b02e7f3e | 1090 | nor->erase_opcode = SPINOR_OP_BE_4K_PMC; |
b199489d | 1091 | mtd->erasesize = 4096; |
57cf26c1 RM |
1092 | } else |
1093 | #endif | |
1094 | { | |
b02e7f3e | 1095 | nor->erase_opcode = SPINOR_OP_SE; |
b199489d HS |
1096 | mtd->erasesize = info->sector_size; |
1097 | } | |
1098 | ||
1099 | if (info->flags & SPI_NOR_NO_ERASE) | |
1100 | mtd->flags |= MTD_NO_ERASE; | |
1101 | ||
1102 | mtd->dev.parent = dev; | |
1103 | nor->page_size = info->page_size; | |
1104 | mtd->writebufsize = nor->page_size; | |
1105 | ||
1106 | if (np) { | |
1107 | /* If we were instantiated by DT, use it */ | |
1108 | if (of_property_read_bool(np, "m25p,fast-read")) | |
1109 | nor->flash_read = SPI_NOR_FAST; | |
1110 | else | |
1111 | nor->flash_read = SPI_NOR_NORMAL; | |
1112 | } else { | |
1113 | /* If we weren't instantiated by DT, default to fast-read */ | |
1114 | nor->flash_read = SPI_NOR_FAST; | |
1115 | } | |
1116 | ||
1117 | /* Some devices cannot do fast-read, no matter what DT tells us */ | |
1118 | if (info->flags & SPI_NOR_NO_FR) | |
1119 | nor->flash_read = SPI_NOR_NORMAL; | |
1120 | ||
1121 | /* Quad/Dual-read mode takes precedence over fast/normal */ | |
1122 | if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) { | |
d928a259 | 1123 | ret = set_quad_mode(nor, info); |
b199489d HS |
1124 | if (ret) { |
1125 | dev_err(dev, "quad mode not supported\n"); | |
1126 | return ret; | |
1127 | } | |
1128 | nor->flash_read = SPI_NOR_QUAD; | |
1129 | } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) { | |
1130 | nor->flash_read = SPI_NOR_DUAL; | |
1131 | } | |
1132 | ||
1133 | /* Default commands */ | |
1134 | switch (nor->flash_read) { | |
1135 | case SPI_NOR_QUAD: | |
58b89a1f | 1136 | nor->read_opcode = SPINOR_OP_READ_1_1_4; |
b199489d HS |
1137 | break; |
1138 | case SPI_NOR_DUAL: | |
58b89a1f | 1139 | nor->read_opcode = SPINOR_OP_READ_1_1_2; |
b199489d HS |
1140 | break; |
1141 | case SPI_NOR_FAST: | |
58b89a1f | 1142 | nor->read_opcode = SPINOR_OP_READ_FAST; |
b199489d HS |
1143 | break; |
1144 | case SPI_NOR_NORMAL: | |
58b89a1f | 1145 | nor->read_opcode = SPINOR_OP_READ; |
b199489d HS |
1146 | break; |
1147 | default: | |
1148 | dev_err(dev, "No Read opcode defined\n"); | |
1149 | return -EINVAL; | |
1150 | } | |
1151 | ||
b02e7f3e | 1152 | nor->program_opcode = SPINOR_OP_PP; |
b199489d HS |
1153 | |
1154 | if (info->addr_width) | |
1155 | nor->addr_width = info->addr_width; | |
1156 | else if (mtd->size > 0x1000000) { | |
1157 | /* enable 4-byte addressing if the device exceeds 16MiB */ | |
1158 | nor->addr_width = 4; | |
d928a259 | 1159 | if (JEDEC_MFR(info) == CFI_MFR_AMD) { |
b199489d HS |
1160 | /* Dedicated 4-byte command set */ |
1161 | switch (nor->flash_read) { | |
1162 | case SPI_NOR_QUAD: | |
58b89a1f | 1163 | nor->read_opcode = SPINOR_OP_READ4_1_1_4; |
b199489d HS |
1164 | break; |
1165 | case SPI_NOR_DUAL: | |
58b89a1f | 1166 | nor->read_opcode = SPINOR_OP_READ4_1_1_2; |
b199489d HS |
1167 | break; |
1168 | case SPI_NOR_FAST: | |
58b89a1f | 1169 | nor->read_opcode = SPINOR_OP_READ4_FAST; |
b199489d HS |
1170 | break; |
1171 | case SPI_NOR_NORMAL: | |
58b89a1f | 1172 | nor->read_opcode = SPINOR_OP_READ4; |
b199489d HS |
1173 | break; |
1174 | } | |
b02e7f3e | 1175 | nor->program_opcode = SPINOR_OP_PP_4B; |
b199489d | 1176 | /* No small sector erase for 4-byte command set */ |
b02e7f3e | 1177 | nor->erase_opcode = SPINOR_OP_SE_4B; |
b199489d HS |
1178 | mtd->erasesize = info->sector_size; |
1179 | } else | |
d928a259 | 1180 | set_4byte(nor, info, 1); |
b199489d HS |
1181 | } else { |
1182 | nor->addr_width = 3; | |
1183 | } | |
1184 | ||
1185 | nor->read_dummy = spi_nor_read_dummy_cycles(nor); | |
1186 | ||
1187 | dev_info(dev, "%s (%lld Kbytes)\n", id->name, | |
1188 | (long long)mtd->size >> 10); | |
1189 | ||
1190 | dev_dbg(dev, | |
1191 | "mtd .name = %s, .size = 0x%llx (%lldMiB), " | |
1192 | ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", | |
1193 | mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20), | |
1194 | mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions); | |
1195 | ||
1196 | if (mtd->numeraseregions) | |
1197 | for (i = 0; i < mtd->numeraseregions; i++) | |
1198 | dev_dbg(dev, | |
1199 | "mtd.eraseregions[%d] = { .offset = 0x%llx, " | |
1200 | ".erasesize = 0x%.8x (%uKiB), " | |
1201 | ".numblocks = %d }\n", | |
1202 | i, (long long)mtd->eraseregions[i].offset, | |
1203 | mtd->eraseregions[i].erasesize, | |
1204 | mtd->eraseregions[i].erasesize / 1024, | |
1205 | mtd->eraseregions[i].numblocks); | |
1206 | return 0; | |
1207 | } | |
b61834b0 | 1208 | EXPORT_SYMBOL_GPL(spi_nor_scan); |
b199489d | 1209 | |
70f3ce05 | 1210 | static const struct spi_device_id *spi_nor_match_id(const char *name) |
0d8c11c0 HS |
1211 | { |
1212 | const struct spi_device_id *id = spi_nor_ids; | |
1213 | ||
1214 | while (id->name[0]) { | |
1215 | if (!strcmp(name, id->name)) | |
1216 | return id; | |
1217 | id++; | |
1218 | } | |
1219 | return NULL; | |
1220 | } | |
1221 | ||
b199489d HS |
1222 | MODULE_LICENSE("GPL"); |
1223 | MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>"); | |
1224 | MODULE_AUTHOR("Mike Lavender"); | |
1225 | MODULE_DESCRIPTION("framework for SPI NOR"); |