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Commit | Line | Data |
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b199489d | 1 | /* |
8eabdd1e HS |
2 | * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with |
3 | * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c | |
4 | * | |
5 | * Copyright (C) 2005, Intec Automation Inc. | |
6 | * Copyright (C) 2014, Freescale Semiconductor, Inc. | |
b199489d HS |
7 | * |
8 | * This code is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/err.h> | |
14 | #include <linux/errno.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/mutex.h> | |
18 | #include <linux/math64.h> | |
09b6a377 | 19 | #include <linux/sizes.h> |
b199489d | 20 | |
b199489d HS |
21 | #include <linux/mtd/mtd.h> |
22 | #include <linux/of_platform.h> | |
23 | #include <linux/spi/flash.h> | |
24 | #include <linux/mtd/spi-nor.h> | |
25 | ||
26 | /* Define max times to check status register before we give up. */ | |
09b6a377 FS |
27 | |
28 | /* | |
29 | * For everything but full-chip erase; probably could be much smaller, but kept | |
30 | * around for safety for now | |
31 | */ | |
32 | #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) | |
33 | ||
34 | /* | |
35 | * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up | |
36 | * for larger flash | |
37 | */ | |
38 | #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ) | |
b199489d | 39 | |
d928a259 | 40 | #define SPI_NOR_MAX_ID_LEN 6 |
c67cbb83 | 41 | #define SPI_NOR_MAX_ADDR_WIDTH 4 |
d928a259 HS |
42 | |
43 | struct flash_info { | |
06bb6f5a RM |
44 | char *name; |
45 | ||
d928a259 HS |
46 | /* |
47 | * This array stores the ID bytes. | |
48 | * The first three bytes are the JEDIC ID. | |
49 | * JEDEC ID zero means "no ID" (mostly older chips). | |
50 | */ | |
51 | u8 id[SPI_NOR_MAX_ID_LEN]; | |
52 | u8 id_len; | |
53 | ||
54 | /* The size listed here is what works with SPINOR_OP_SE, which isn't | |
55 | * necessarily called a "sector" by the vendor. | |
56 | */ | |
57 | unsigned sector_size; | |
58 | u16 n_sectors; | |
59 | ||
60 | u16 page_size; | |
61 | u16 addr_width; | |
62 | ||
63 | u16 flags; | |
0618114e BN |
64 | #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */ |
65 | #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */ | |
66 | #define SST_WRITE BIT(2) /* use SST byte programming */ | |
67 | #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */ | |
68 | #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */ | |
69 | #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */ | |
70 | #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */ | |
71 | #define USE_FSR BIT(7) /* use flag status register */ | |
76a4707d | 72 | #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */ |
3dd8012a BN |
73 | #define SPI_NOR_HAS_TB BIT(9) /* |
74 | * Flash SR has Top/Bottom (TB) protect | |
75 | * bit. Must be used with | |
76 | * SPI_NOR_HAS_LOCK. | |
77 | */ | |
d928a259 HS |
78 | }; |
79 | ||
80 | #define JEDEC_MFR(info) ((info)->id[0]) | |
b199489d | 81 | |
06bb6f5a | 82 | static const struct flash_info *spi_nor_match_id(const char *name); |
70f3ce05 | 83 | |
b199489d HS |
84 | /* |
85 | * Read the status register, returning its value in the location | |
86 | * Return the status register value. | |
87 | * Returns negative if error occurred. | |
88 | */ | |
89 | static int read_sr(struct spi_nor *nor) | |
90 | { | |
91 | int ret; | |
92 | u8 val; | |
93 | ||
b02e7f3e | 94 | ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1); |
b199489d HS |
95 | if (ret < 0) { |
96 | pr_err("error %d reading SR\n", (int) ret); | |
97 | return ret; | |
98 | } | |
99 | ||
100 | return val; | |
101 | } | |
102 | ||
c14dedde | 103 | /* |
104 | * Read the flag status register, returning its value in the location | |
105 | * Return the status register value. | |
106 | * Returns negative if error occurred. | |
107 | */ | |
108 | static int read_fsr(struct spi_nor *nor) | |
109 | { | |
110 | int ret; | |
111 | u8 val; | |
112 | ||
113 | ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1); | |
114 | if (ret < 0) { | |
115 | pr_err("error %d reading FSR\n", ret); | |
116 | return ret; | |
117 | } | |
118 | ||
119 | return val; | |
120 | } | |
121 | ||
b199489d HS |
122 | /* |
123 | * Read configuration register, returning its value in the | |
124 | * location. Return the configuration register value. | |
125 | * Returns negative if error occured. | |
126 | */ | |
127 | static int read_cr(struct spi_nor *nor) | |
128 | { | |
129 | int ret; | |
130 | u8 val; | |
131 | ||
b02e7f3e | 132 | ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1); |
b199489d HS |
133 | if (ret < 0) { |
134 | dev_err(nor->dev, "error %d reading CR\n", ret); | |
135 | return ret; | |
136 | } | |
137 | ||
138 | return val; | |
139 | } | |
140 | ||
141 | /* | |
142 | * Dummy Cycle calculation for different type of read. | |
143 | * It can be used to support more commands with | |
144 | * different dummy cycle requirements. | |
145 | */ | |
146 | static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor) | |
147 | { | |
148 | switch (nor->flash_read) { | |
149 | case SPI_NOR_FAST: | |
150 | case SPI_NOR_DUAL: | |
151 | case SPI_NOR_QUAD: | |
0b78a2cf | 152 | return 8; |
b199489d HS |
153 | case SPI_NOR_NORMAL: |
154 | return 0; | |
155 | } | |
156 | return 0; | |
157 | } | |
158 | ||
159 | /* | |
160 | * Write status register 1 byte | |
161 | * Returns negative if error occurred. | |
162 | */ | |
163 | static inline int write_sr(struct spi_nor *nor, u8 val) | |
164 | { | |
165 | nor->cmd_buf[0] = val; | |
f9f3ce83 | 166 | return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1); |
b199489d HS |
167 | } |
168 | ||
169 | /* | |
170 | * Set write enable latch with Write Enable command. | |
171 | * Returns negative if error occurred. | |
172 | */ | |
173 | static inline int write_enable(struct spi_nor *nor) | |
174 | { | |
f9f3ce83 | 175 | return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0); |
b199489d HS |
176 | } |
177 | ||
178 | /* | |
179 | * Send write disble instruction to the chip. | |
180 | */ | |
181 | static inline int write_disable(struct spi_nor *nor) | |
182 | { | |
f9f3ce83 | 183 | return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0); |
b199489d HS |
184 | } |
185 | ||
186 | static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) | |
187 | { | |
188 | return mtd->priv; | |
189 | } | |
190 | ||
191 | /* Enable/disable 4-byte addressing mode. */ | |
06bb6f5a | 192 | static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info, |
d928a259 | 193 | int enable) |
b199489d HS |
194 | { |
195 | int status; | |
196 | bool need_wren = false; | |
197 | u8 cmd; | |
198 | ||
d928a259 | 199 | switch (JEDEC_MFR(info)) { |
f0d2448e | 200 | case SNOR_MFR_MICRON: |
b199489d HS |
201 | /* Some Micron need WREN command; all will accept it */ |
202 | need_wren = true; | |
f0d2448e BN |
203 | case SNOR_MFR_MACRONIX: |
204 | case SNOR_MFR_WINBOND: | |
b199489d HS |
205 | if (need_wren) |
206 | write_enable(nor); | |
207 | ||
b02e7f3e | 208 | cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; |
f9f3ce83 | 209 | status = nor->write_reg(nor, cmd, NULL, 0); |
b199489d HS |
210 | if (need_wren) |
211 | write_disable(nor); | |
212 | ||
213 | return status; | |
214 | default: | |
215 | /* Spansion style */ | |
216 | nor->cmd_buf[0] = enable << 7; | |
f9f3ce83 | 217 | return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1); |
b199489d HS |
218 | } |
219 | } | |
51983b7d | 220 | static inline int spi_nor_sr_ready(struct spi_nor *nor) |
b199489d | 221 | { |
51983b7d BN |
222 | int sr = read_sr(nor); |
223 | if (sr < 0) | |
224 | return sr; | |
225 | else | |
226 | return !(sr & SR_WIP); | |
227 | } | |
b199489d | 228 | |
51983b7d BN |
229 | static inline int spi_nor_fsr_ready(struct spi_nor *nor) |
230 | { | |
231 | int fsr = read_fsr(nor); | |
232 | if (fsr < 0) | |
233 | return fsr; | |
234 | else | |
235 | return fsr & FSR_READY; | |
236 | } | |
b199489d | 237 | |
51983b7d BN |
238 | static int spi_nor_ready(struct spi_nor *nor) |
239 | { | |
240 | int sr, fsr; | |
241 | sr = spi_nor_sr_ready(nor); | |
242 | if (sr < 0) | |
243 | return sr; | |
244 | fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; | |
245 | if (fsr < 0) | |
246 | return fsr; | |
247 | return sr && fsr; | |
b199489d HS |
248 | } |
249 | ||
b94ed087 BN |
250 | /* |
251 | * Service routine to read status register until ready, or timeout occurs. | |
252 | * Returns non-zero if error. | |
253 | */ | |
09b6a377 FS |
254 | static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, |
255 | unsigned long timeout_jiffies) | |
c14dedde | 256 | { |
257 | unsigned long deadline; | |
a95ce92e | 258 | int timeout = 0, ret; |
c14dedde | 259 | |
09b6a377 | 260 | deadline = jiffies + timeout_jiffies; |
c14dedde | 261 | |
a95ce92e BN |
262 | while (!timeout) { |
263 | if (time_after_eq(jiffies, deadline)) | |
264 | timeout = 1; | |
c14dedde | 265 | |
51983b7d BN |
266 | ret = spi_nor_ready(nor); |
267 | if (ret < 0) | |
268 | return ret; | |
269 | if (ret) | |
270 | return 0; | |
a95ce92e BN |
271 | |
272 | cond_resched(); | |
273 | } | |
274 | ||
275 | dev_err(nor->dev, "flash operation timed out\n"); | |
c14dedde | 276 | |
277 | return -ETIMEDOUT; | |
278 | } | |
279 | ||
09b6a377 FS |
280 | static int spi_nor_wait_till_ready(struct spi_nor *nor) |
281 | { | |
282 | return spi_nor_wait_till_ready_with_timeout(nor, | |
283 | DEFAULT_READY_WAIT_JIFFIES); | |
284 | } | |
285 | ||
b199489d HS |
286 | /* |
287 | * Erase the whole flash memory | |
288 | * | |
289 | * Returns 0 if successful, non-zero otherwise. | |
290 | */ | |
291 | static int erase_chip(struct spi_nor *nor) | |
292 | { | |
19763671 | 293 | dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10)); |
b199489d | 294 | |
f9f3ce83 | 295 | return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0); |
b199489d HS |
296 | } |
297 | ||
298 | static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops) | |
299 | { | |
300 | int ret = 0; | |
301 | ||
302 | mutex_lock(&nor->lock); | |
303 | ||
304 | if (nor->prepare) { | |
305 | ret = nor->prepare(nor, ops); | |
306 | if (ret) { | |
307 | dev_err(nor->dev, "failed in the preparation.\n"); | |
308 | mutex_unlock(&nor->lock); | |
309 | return ret; | |
310 | } | |
311 | } | |
312 | return ret; | |
313 | } | |
314 | ||
315 | static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops) | |
316 | { | |
317 | if (nor->unprepare) | |
318 | nor->unprepare(nor, ops); | |
319 | mutex_unlock(&nor->lock); | |
320 | } | |
321 | ||
c67cbb83 BN |
322 | /* |
323 | * Initiate the erasure of a single sector | |
324 | */ | |
325 | static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) | |
326 | { | |
327 | u8 buf[SPI_NOR_MAX_ADDR_WIDTH]; | |
328 | int i; | |
329 | ||
330 | if (nor->erase) | |
331 | return nor->erase(nor, addr); | |
332 | ||
333 | /* | |
334 | * Default implementation, if driver doesn't have a specialized HW | |
335 | * control | |
336 | */ | |
337 | for (i = nor->addr_width - 1; i >= 0; i--) { | |
338 | buf[i] = addr & 0xff; | |
339 | addr >>= 8; | |
340 | } | |
341 | ||
342 | return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width); | |
343 | } | |
344 | ||
b199489d HS |
345 | /* |
346 | * Erase an address range on the nor chip. The address range may extend | |
347 | * one or more erase sectors. Return an error is there is a problem erasing. | |
348 | */ | |
349 | static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) | |
350 | { | |
351 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
352 | u32 addr, len; | |
353 | uint32_t rem; | |
354 | int ret; | |
355 | ||
356 | dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, | |
357 | (long long)instr->len); | |
358 | ||
359 | div_u64_rem(instr->len, mtd->erasesize, &rem); | |
360 | if (rem) | |
361 | return -EINVAL; | |
362 | ||
363 | addr = instr->addr; | |
364 | len = instr->len; | |
365 | ||
366 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE); | |
367 | if (ret) | |
368 | return ret; | |
369 | ||
370 | /* whole-chip erase? */ | |
371 | if (len == mtd->size) { | |
09b6a377 FS |
372 | unsigned long timeout; |
373 | ||
05241aea BN |
374 | write_enable(nor); |
375 | ||
b199489d HS |
376 | if (erase_chip(nor)) { |
377 | ret = -EIO; | |
378 | goto erase_err; | |
379 | } | |
380 | ||
09b6a377 FS |
381 | /* |
382 | * Scale the timeout linearly with the size of the flash, with | |
383 | * a minimum calibrated to an old 2MB flash. We could try to | |
384 | * pull these from CFI/SFDP, but these values should be good | |
385 | * enough for now. | |
386 | */ | |
387 | timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, | |
388 | CHIP_ERASE_2MB_READY_WAIT_JIFFIES * | |
389 | (unsigned long)(mtd->size / SZ_2M)); | |
390 | ret = spi_nor_wait_till_ready_with_timeout(nor, timeout); | |
dfa9c0cb BN |
391 | if (ret) |
392 | goto erase_err; | |
393 | ||
b199489d | 394 | /* REVISIT in some cases we could speed up erasing large regions |
b02e7f3e | 395 | * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up |
b199489d HS |
396 | * to use "small sector erase", but that's not always optimal. |
397 | */ | |
398 | ||
399 | /* "sector"-at-a-time erase */ | |
400 | } else { | |
401 | while (len) { | |
05241aea BN |
402 | write_enable(nor); |
403 | ||
c67cbb83 BN |
404 | ret = spi_nor_erase_sector(nor, addr); |
405 | if (ret) | |
b199489d | 406 | goto erase_err; |
b199489d HS |
407 | |
408 | addr += mtd->erasesize; | |
409 | len -= mtd->erasesize; | |
dfa9c0cb BN |
410 | |
411 | ret = spi_nor_wait_till_ready(nor); | |
412 | if (ret) | |
413 | goto erase_err; | |
b199489d HS |
414 | } |
415 | } | |
416 | ||
05241aea BN |
417 | write_disable(nor); |
418 | ||
d6af2694 | 419 | erase_err: |
b199489d HS |
420 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); |
421 | ||
d6af2694 | 422 | instr->state = ret ? MTD_ERASE_FAILED : MTD_ERASE_DONE; |
b199489d HS |
423 | mtd_erase_callback(instr); |
424 | ||
425 | return ret; | |
b199489d HS |
426 | } |
427 | ||
62593cf4 BN |
428 | static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs, |
429 | uint64_t *len) | |
430 | { | |
431 | struct mtd_info *mtd = &nor->mtd; | |
432 | u8 mask = SR_BP2 | SR_BP1 | SR_BP0; | |
433 | int shift = ffs(mask) - 1; | |
434 | int pow; | |
435 | ||
436 | if (!(sr & mask)) { | |
437 | /* No protection */ | |
438 | *ofs = 0; | |
439 | *len = 0; | |
440 | } else { | |
441 | pow = ((sr & mask) ^ mask) >> shift; | |
442 | *len = mtd->size >> pow; | |
3dd8012a BN |
443 | if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB) |
444 | *ofs = 0; | |
445 | else | |
446 | *ofs = mtd->size - *len; | |
62593cf4 BN |
447 | } |
448 | } | |
449 | ||
450 | /* | |
f8860802 BN |
451 | * Return 1 if the entire region is locked (if @locked is true) or unlocked (if |
452 | * @locked is false); 0 otherwise | |
62593cf4 | 453 | */ |
f8860802 BN |
454 | static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, |
455 | u8 sr, bool locked) | |
62593cf4 BN |
456 | { |
457 | loff_t lock_offs; | |
458 | uint64_t lock_len; | |
459 | ||
f8860802 BN |
460 | if (!len) |
461 | return 1; | |
462 | ||
62593cf4 BN |
463 | stm_get_locked_range(nor, sr, &lock_offs, &lock_len); |
464 | ||
f8860802 BN |
465 | if (locked) |
466 | /* Requested range is a sub-range of locked range */ | |
467 | return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); | |
468 | else | |
469 | /* Requested range does not overlap with locked range */ | |
470 | return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs); | |
471 | } | |
472 | ||
473 | static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, | |
474 | u8 sr) | |
475 | { | |
476 | return stm_check_lock_status_sr(nor, ofs, len, sr, true); | |
477 | } | |
478 | ||
479 | static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, | |
480 | u8 sr) | |
481 | { | |
482 | return stm_check_lock_status_sr(nor, ofs, len, sr, false); | |
62593cf4 BN |
483 | } |
484 | ||
485 | /* | |
486 | * Lock a region of the flash. Compatible with ST Micro and similar flash. | |
3dd8012a | 487 | * Supports the block protection bits BP{0,1,2} in the status register |
62593cf4 | 488 | * (SR). Does not support these features found in newer SR bitfields: |
62593cf4 BN |
489 | * - SEC: sector/block protect - only handle SEC=0 (block protect) |
490 | * - CMP: complement protect - only support CMP=0 (range is not complemented) | |
491 | * | |
3dd8012a BN |
492 | * Support for the following is provided conditionally for some flash: |
493 | * - TB: top/bottom protect | |
494 | * | |
62593cf4 BN |
495 | * Sample table portion for 8MB flash (Winbond w25q64fw): |
496 | * | |
497 | * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion | |
498 | * -------------------------------------------------------------------------- | |
499 | * X | X | 0 | 0 | 0 | NONE | NONE | |
500 | * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 | |
501 | * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 | |
502 | * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 | |
503 | * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 | |
504 | * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 | |
505 | * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 | |
506 | * X | X | 1 | 1 | 1 | 8 MB | ALL | |
3dd8012a BN |
507 | * ------|-------|-------|-------|-------|---------------|------------------- |
508 | * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64 | |
509 | * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32 | |
510 | * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16 | |
511 | * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8 | |
512 | * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4 | |
513 | * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2 | |
62593cf4 BN |
514 | * |
515 | * Returns negative on errors, 0 on success. | |
516 | */ | |
8cc7f33a | 517 | static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) |
b199489d | 518 | { |
19763671 | 519 | struct mtd_info *mtd = &nor->mtd; |
f49289ce | 520 | int status_old, status_new; |
62593cf4 BN |
521 | u8 mask = SR_BP2 | SR_BP1 | SR_BP0; |
522 | u8 shift = ffs(mask) - 1, pow, val; | |
f8860802 | 523 | loff_t lock_len; |
3dd8012a BN |
524 | bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; |
525 | bool use_top; | |
32321e95 | 526 | int ret; |
b199489d | 527 | |
b199489d | 528 | status_old = read_sr(nor); |
f49289ce FE |
529 | if (status_old < 0) |
530 | return status_old; | |
b199489d | 531 | |
f8860802 BN |
532 | /* If nothing in our range is unlocked, we don't need to do anything */ |
533 | if (stm_is_locked_sr(nor, ofs, len, status_old)) | |
534 | return 0; | |
535 | ||
3dd8012a BN |
536 | /* If anything below us is unlocked, we can't use 'bottom' protection */ |
537 | if (!stm_is_locked_sr(nor, 0, ofs, status_old)) | |
538 | can_be_bottom = false; | |
539 | ||
f8860802 BN |
540 | /* If anything above us is unlocked, we can't use 'top' protection */ |
541 | if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len), | |
542 | status_old)) | |
3dd8012a BN |
543 | can_be_top = false; |
544 | ||
545 | if (!can_be_bottom && !can_be_top) | |
f8860802 BN |
546 | return -EINVAL; |
547 | ||
3dd8012a BN |
548 | /* Prefer top, if both are valid */ |
549 | use_top = can_be_top; | |
550 | ||
f8860802 | 551 | /* lock_len: length of region that should end up locked */ |
3dd8012a BN |
552 | if (use_top) |
553 | lock_len = mtd->size - ofs; | |
554 | else | |
555 | lock_len = ofs + len; | |
62593cf4 BN |
556 | |
557 | /* | |
558 | * Need smallest pow such that: | |
559 | * | |
560 | * 1 / (2^pow) <= (len / size) | |
561 | * | |
562 | * so (assuming power-of-2 size) we do: | |
563 | * | |
564 | * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) | |
565 | */ | |
f8860802 | 566 | pow = ilog2(mtd->size) - ilog2(lock_len); |
62593cf4 BN |
567 | val = mask - (pow << shift); |
568 | if (val & ~mask) | |
569 | return -EINVAL; | |
570 | /* Don't "lock" with no region! */ | |
571 | if (!(val & mask)) | |
572 | return -EINVAL; | |
573 | ||
3dd8012a | 574 | status_new = (status_old & ~mask & ~SR_TB) | val; |
b199489d | 575 | |
47b8edbf BN |
576 | /* Disallow further writes if WP pin is asserted */ |
577 | status_new |= SR_SRWD; | |
578 | ||
3dd8012a BN |
579 | if (!use_top) |
580 | status_new |= SR_TB; | |
581 | ||
4c0dba44 BN |
582 | /* Don't bother if they're the same */ |
583 | if (status_new == status_old) | |
584 | return 0; | |
585 | ||
b199489d | 586 | /* Only modify protection if it will not unlock other areas */ |
4c0dba44 | 587 | if ((status_new & mask) < (status_old & mask)) |
62593cf4 | 588 | return -EINVAL; |
b199489d | 589 | |
62593cf4 | 590 | write_enable(nor); |
32321e95 EG |
591 | ret = write_sr(nor, status_new); |
592 | if (ret) | |
593 | return ret; | |
594 | return spi_nor_wait_till_ready(nor); | |
b199489d HS |
595 | } |
596 | ||
62593cf4 BN |
597 | /* |
598 | * Unlock a region of the flash. See stm_lock() for more info | |
599 | * | |
600 | * Returns negative on errors, 0 on success. | |
601 | */ | |
8cc7f33a | 602 | static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) |
b199489d | 603 | { |
19763671 | 604 | struct mtd_info *mtd = &nor->mtd; |
f49289ce | 605 | int status_old, status_new; |
62593cf4 BN |
606 | u8 mask = SR_BP2 | SR_BP1 | SR_BP0; |
607 | u8 shift = ffs(mask) - 1, pow, val; | |
f8860802 | 608 | loff_t lock_len; |
3dd8012a BN |
609 | bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; |
610 | bool use_top; | |
32321e95 | 611 | int ret; |
b199489d | 612 | |
b199489d | 613 | status_old = read_sr(nor); |
f49289ce FE |
614 | if (status_old < 0) |
615 | return status_old; | |
b199489d | 616 | |
f8860802 BN |
617 | /* If nothing in our range is locked, we don't need to do anything */ |
618 | if (stm_is_unlocked_sr(nor, ofs, len, status_old)) | |
619 | return 0; | |
620 | ||
621 | /* If anything below us is locked, we can't use 'top' protection */ | |
622 | if (!stm_is_unlocked_sr(nor, 0, ofs, status_old)) | |
3dd8012a BN |
623 | can_be_top = false; |
624 | ||
625 | /* If anything above us is locked, we can't use 'bottom' protection */ | |
626 | if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len), | |
627 | status_old)) | |
628 | can_be_bottom = false; | |
629 | ||
630 | if (!can_be_bottom && !can_be_top) | |
62593cf4 | 631 | return -EINVAL; |
b199489d | 632 | |
3dd8012a BN |
633 | /* Prefer top, if both are valid */ |
634 | use_top = can_be_top; | |
635 | ||
f8860802 | 636 | /* lock_len: length of region that should remain locked */ |
3dd8012a BN |
637 | if (use_top) |
638 | lock_len = mtd->size - (ofs + len); | |
639 | else | |
640 | lock_len = ofs; | |
f8860802 | 641 | |
62593cf4 BN |
642 | /* |
643 | * Need largest pow such that: | |
644 | * | |
645 | * 1 / (2^pow) >= (len / size) | |
646 | * | |
647 | * so (assuming power-of-2 size) we do: | |
648 | * | |
649 | * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) | |
650 | */ | |
f8860802 BN |
651 | pow = ilog2(mtd->size) - order_base_2(lock_len); |
652 | if (lock_len == 0) { | |
62593cf4 BN |
653 | val = 0; /* fully unlocked */ |
654 | } else { | |
655 | val = mask - (pow << shift); | |
656 | /* Some power-of-two sizes are not supported */ | |
657 | if (val & ~mask) | |
658 | return -EINVAL; | |
b199489d HS |
659 | } |
660 | ||
3dd8012a | 661 | status_new = (status_old & ~mask & ~SR_TB) | val; |
62593cf4 | 662 | |
47b8edbf | 663 | /* Don't protect status register if we're fully unlocked */ |
06586204 | 664 | if (lock_len == 0) |
47b8edbf BN |
665 | status_new &= ~SR_SRWD; |
666 | ||
3dd8012a BN |
667 | if (!use_top) |
668 | status_new |= SR_TB; | |
669 | ||
4c0dba44 BN |
670 | /* Don't bother if they're the same */ |
671 | if (status_new == status_old) | |
672 | return 0; | |
673 | ||
62593cf4 | 674 | /* Only modify protection if it will not lock other areas */ |
4c0dba44 | 675 | if ((status_new & mask) > (status_old & mask)) |
62593cf4 BN |
676 | return -EINVAL; |
677 | ||
678 | write_enable(nor); | |
32321e95 EG |
679 | ret = write_sr(nor, status_new); |
680 | if (ret) | |
681 | return ret; | |
682 | return spi_nor_wait_till_ready(nor); | |
8cc7f33a BN |
683 | } |
684 | ||
5bf0e69b BN |
685 | /* |
686 | * Check if a region of the flash is (completely) locked. See stm_lock() for | |
687 | * more info. | |
688 | * | |
689 | * Returns 1 if entire region is locked, 0 if any portion is unlocked, and | |
690 | * negative on errors. | |
691 | */ | |
692 | static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) | |
693 | { | |
694 | int status; | |
695 | ||
696 | status = read_sr(nor); | |
697 | if (status < 0) | |
698 | return status; | |
699 | ||
700 | return stm_is_locked_sr(nor, ofs, len, status); | |
701 | } | |
702 | ||
8cc7f33a BN |
703 | static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
704 | { | |
705 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
706 | int ret; | |
707 | ||
708 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK); | |
709 | if (ret) | |
710 | return ret; | |
711 | ||
712 | ret = nor->flash_lock(nor, ofs, len); | |
713 | ||
b199489d HS |
714 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK); |
715 | return ret; | |
716 | } | |
717 | ||
8cc7f33a BN |
718 | static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
719 | { | |
720 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
721 | int ret; | |
722 | ||
723 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK); | |
724 | if (ret) | |
725 | return ret; | |
726 | ||
727 | ret = nor->flash_unlock(nor, ofs, len); | |
728 | ||
729 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK); | |
730 | return ret; | |
731 | } | |
732 | ||
5bf0e69b BN |
733 | static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
734 | { | |
735 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
736 | int ret; | |
737 | ||
738 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK); | |
739 | if (ret) | |
740 | return ret; | |
741 | ||
742 | ret = nor->flash_is_locked(nor, ofs, len); | |
743 | ||
744 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK); | |
745 | return ret; | |
746 | } | |
747 | ||
09ffafb6 | 748 | /* Used when the "_ext_id" is two bytes at most */ |
b199489d | 749 | #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
09ffafb6 HS |
750 | .id = { \ |
751 | ((_jedec_id) >> 16) & 0xff, \ | |
752 | ((_jedec_id) >> 8) & 0xff, \ | |
753 | (_jedec_id) & 0xff, \ | |
754 | ((_ext_id) >> 8) & 0xff, \ | |
755 | (_ext_id) & 0xff, \ | |
756 | }, \ | |
757 | .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ | |
b199489d HS |
758 | .sector_size = (_sector_size), \ |
759 | .n_sectors = (_n_sectors), \ | |
760 | .page_size = 256, \ | |
06bb6f5a | 761 | .flags = (_flags), |
b199489d | 762 | |
6d7604e5 | 763 | #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
6d7604e5 HS |
764 | .id = { \ |
765 | ((_jedec_id) >> 16) & 0xff, \ | |
766 | ((_jedec_id) >> 8) & 0xff, \ | |
767 | (_jedec_id) & 0xff, \ | |
768 | ((_ext_id) >> 16) & 0xff, \ | |
769 | ((_ext_id) >> 8) & 0xff, \ | |
770 | (_ext_id) & 0xff, \ | |
771 | }, \ | |
772 | .id_len = 6, \ | |
773 | .sector_size = (_sector_size), \ | |
774 | .n_sectors = (_n_sectors), \ | |
775 | .page_size = 256, \ | |
06bb6f5a | 776 | .flags = (_flags), |
6d7604e5 | 777 | |
b199489d | 778 | #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \ |
b199489d HS |
779 | .sector_size = (_sector_size), \ |
780 | .n_sectors = (_n_sectors), \ | |
781 | .page_size = (_page_size), \ | |
782 | .addr_width = (_addr_width), \ | |
06bb6f5a | 783 | .flags = (_flags), |
b199489d HS |
784 | |
785 | /* NOTE: double check command sets and memory organization when you add | |
786 | * more nor chips. This current list focusses on newer chips, which | |
787 | * have been converging on command sets which including JEDEC ID. | |
c19900ed RM |
788 | * |
789 | * All newly added entries should describe *hardware* and should use SECT_4K | |
790 | * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage | |
791 | * scenarios excluding small sectors there is config option that can be | |
792 | * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS. | |
793 | * For historical (and compatibility) reasons (before we got above config) some | |
794 | * old entries may be missing 4K flag. | |
b199489d | 795 | */ |
06bb6f5a | 796 | static const struct flash_info spi_nor_ids[] = { |
b199489d HS |
797 | /* Atmel -- some are (confusingly) marketed as "DataFlash" */ |
798 | { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) }, | |
799 | { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) }, | |
800 | ||
801 | { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) }, | |
802 | { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, | |
803 | { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) }, | |
804 | ||
805 | { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) }, | |
806 | { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, | |
807 | { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) }, | |
808 | { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, | |
809 | ||
810 | { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, | |
811 | ||
812 | /* EON -- en25xxx */ | |
813 | { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, | |
814 | { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, | |
815 | { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) }, | |
816 | { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) }, | |
817 | { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, | |
a41595b3 | 818 | { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) }, |
b199489d | 819 | { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) }, |
c19900ed | 820 | { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, |
b199489d HS |
821 | |
822 | /* ESMT */ | |
823 | { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) }, | |
824 | ||
825 | /* Everspin */ | |
826 | { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
827 | { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
828 | ||
ce56ce7d RL |
829 | /* Fujitsu */ |
830 | { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) }, | |
831 | ||
b199489d HS |
832 | /* GigaDevice */ |
833 | { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) }, | |
834 | { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) }, | |
e5366a26 | 835 | { "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
fcc87a95 | 836 | { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K) }, |
b199489d HS |
837 | |
838 | /* Intel/Numonyx -- xxxs33b */ | |
839 | { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) }, | |
840 | { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, | |
841 | { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, | |
842 | ||
b79c332f GJ |
843 | /* ISSI */ |
844 | { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) }, | |
845 | ||
b199489d | 846 | /* Macronix */ |
660b5b07 | 847 | { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) }, |
b199489d HS |
848 | { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, |
849 | { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, | |
850 | { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, | |
851 | { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, | |
0501f2e5 | 852 | { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) }, |
b199489d | 853 | { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) }, |
0501f2e5 | 854 | { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) }, |
81a1209c | 855 | { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) }, |
b199489d HS |
856 | { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, |
857 | { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, | |
858 | { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) }, | |
859 | { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, | |
860 | { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) }, | |
861 | { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) }, | |
862 | ||
863 | /* Micron */ | |
548cd3ab | 864 | { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, |
f9bcb6dc | 865 | { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, |
0db7fae2 | 866 | { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, |
2a06c7b1 | 867 | { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, |
4607777c EG |
868 | { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, |
869 | { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, | |
548cd3ab BH |
870 | { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, |
871 | { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, | |
872 | { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, | |
873 | { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, | |
b199489d HS |
874 | |
875 | /* PMC */ | |
876 | { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) }, | |
877 | { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) }, | |
878 | { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) }, | |
879 | ||
880 | /* Spansion -- single (large) sector size only, at least | |
881 | * for the chips listed here (without boot sectors). | |
882 | */ | |
9ab86995 | 883 | { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
0f12a27b | 884 | { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
b199489d HS |
885 | { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) }, |
886 | { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
887 | { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
888 | { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, | |
889 | { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, | |
890 | { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, | |
c19900ed | 891 | { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, |
c1752086 JG |
892 | { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
893 | { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
b199489d HS |
894 | { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, |
895 | { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, | |
896 | { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, | |
897 | { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, | |
898 | { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, | |
7c748f57 | 899 | { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
adf508c3 JE |
900 | { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
901 | { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
b199489d | 902 | { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, |
c0826679 | 903 | { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
c19900ed | 904 | { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) }, |
413780d7 | 905 | { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) }, |
aada20cd | 906 | { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) }, |
b199489d HS |
907 | |
908 | /* SST -- large erase sizes are "overlays", "sectors" are 4K */ | |
909 | { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, | |
910 | { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, | |
911 | { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, | |
912 | { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, | |
913 | { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, | |
914 | { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, | |
915 | { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, | |
916 | { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, | |
a1d97ef9 | 917 | { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) }, |
c887be71 | 918 | { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) }, |
b199489d | 919 | { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, |
f02985b7 | 920 | { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, |
b199489d HS |
921 | |
922 | /* ST Microelectronics -- newer production may have feature updates */ | |
923 | { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) }, | |
924 | { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) }, | |
925 | { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) }, | |
926 | { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) }, | |
927 | { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) }, | |
928 | { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) }, | |
929 | { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) }, | |
930 | { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) }, | |
931 | { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) }, | |
b199489d HS |
932 | |
933 | { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) }, | |
934 | { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) }, | |
935 | { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) }, | |
936 | { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) }, | |
937 | { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) }, | |
938 | { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) }, | |
939 | { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) }, | |
940 | { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) }, | |
941 | { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) }, | |
942 | ||
943 | { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) }, | |
944 | { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) }, | |
945 | { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) }, | |
946 | ||
947 | { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) }, | |
948 | { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) }, | |
949 | { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) }, | |
950 | ||
951 | { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) }, | |
952 | { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) }, | |
953 | { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) }, | |
954 | { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) }, | |
955 | { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) }, | |
f2fabe16 | 956 | { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) }, |
b199489d HS |
957 | |
958 | /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ | |
40d19ab6 | 959 | { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) }, |
b199489d HS |
960 | { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, |
961 | { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, | |
962 | { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, | |
963 | { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, | |
964 | { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, | |
965 | { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, | |
966 | { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, | |
9648388f BN |
967 | { |
968 | "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, | |
969 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | | |
970 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) | |
971 | }, | |
b199489d HS |
972 | { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, |
973 | { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, | |
9648388f BN |
974 | { |
975 | "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, | |
976 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | | |
977 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) | |
978 | }, | |
979 | { | |
980 | "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, | |
981 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | | |
982 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) | |
983 | }, | |
b199489d HS |
984 | { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, |
985 | { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, | |
986 | { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, | |
987 | { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) }, | |
988 | ||
989 | /* Catalyst / On Semiconductor -- non-JEDEC */ | |
990 | { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
991 | { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
992 | { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
993 | { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
994 | { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
995 | { }, | |
996 | }; | |
997 | ||
06bb6f5a | 998 | static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) |
b199489d HS |
999 | { |
1000 | int tmp; | |
09ffafb6 | 1001 | u8 id[SPI_NOR_MAX_ID_LEN]; |
06bb6f5a | 1002 | const struct flash_info *info; |
b199489d | 1003 | |
09ffafb6 | 1004 | tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); |
b199489d | 1005 | if (tmp < 0) { |
20625dfe | 1006 | dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp); |
b199489d HS |
1007 | return ERR_PTR(tmp); |
1008 | } | |
b199489d HS |
1009 | |
1010 | for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) { | |
06bb6f5a | 1011 | info = &spi_nor_ids[tmp]; |
09ffafb6 HS |
1012 | if (info->id_len) { |
1013 | if (!memcmp(info->id, id, info->id_len)) | |
b199489d HS |
1014 | return &spi_nor_ids[tmp]; |
1015 | } | |
1016 | } | |
9b9f1033 | 1017 | dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n", |
09ffafb6 | 1018 | id[0], id[1], id[2]); |
b199489d HS |
1019 | return ERR_PTR(-ENODEV); |
1020 | } | |
1021 | ||
b199489d HS |
1022 | static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, |
1023 | size_t *retlen, u_char *buf) | |
1024 | { | |
1025 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
1026 | int ret; | |
1027 | ||
1028 | dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); | |
1029 | ||
1030 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ); | |
1031 | if (ret) | |
1032 | return ret; | |
1033 | ||
26f9bcad MS |
1034 | while (len) { |
1035 | ret = nor->read(nor, from, len, buf); | |
1036 | if (ret == 0) { | |
1037 | /* We shouldn't see 0-length reads */ | |
1038 | ret = -EIO; | |
1039 | goto read_err; | |
1040 | } | |
1041 | if (ret < 0) | |
1042 | goto read_err; | |
b199489d | 1043 | |
26f9bcad MS |
1044 | WARN_ON(ret > len); |
1045 | *retlen += ret; | |
1046 | buf += ret; | |
1047 | from += ret; | |
1048 | len -= ret; | |
1049 | } | |
1050 | ret = 0; | |
59451e12 | 1051 | |
26f9bcad MS |
1052 | read_err: |
1053 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ); | |
1054 | return ret; | |
b199489d HS |
1055 | } |
1056 | ||
1057 | static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, | |
1058 | size_t *retlen, const u_char *buf) | |
1059 | { | |
1060 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
1061 | size_t actual; | |
1062 | int ret; | |
1063 | ||
1064 | dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); | |
1065 | ||
1066 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE); | |
1067 | if (ret) | |
1068 | return ret; | |
1069 | ||
b199489d HS |
1070 | write_enable(nor); |
1071 | ||
1072 | nor->sst_write_second = false; | |
1073 | ||
1074 | actual = to % 2; | |
1075 | /* Start write from odd address. */ | |
1076 | if (actual) { | |
b02e7f3e | 1077 | nor->program_opcode = SPINOR_OP_BP; |
b199489d HS |
1078 | |
1079 | /* write one byte. */ | |
2dd087b1 | 1080 | ret = nor->write(nor, to, 1, buf); |
0bad7b93 MS |
1081 | if (ret < 0) |
1082 | goto sst_write_err; | |
1083 | WARN(ret != 1, "While writing 1 byte written %i bytes\n", | |
1084 | (int)ret); | |
b94ed087 | 1085 | ret = spi_nor_wait_till_ready(nor); |
b199489d | 1086 | if (ret) |
0bad7b93 | 1087 | goto sst_write_err; |
b199489d HS |
1088 | } |
1089 | to += actual; | |
1090 | ||
1091 | /* Write out most of the data here. */ | |
1092 | for (; actual < len - 1; actual += 2) { | |
b02e7f3e | 1093 | nor->program_opcode = SPINOR_OP_AAI_WP; |
b199489d HS |
1094 | |
1095 | /* write two bytes. */ | |
2dd087b1 | 1096 | ret = nor->write(nor, to, 2, buf + actual); |
0bad7b93 MS |
1097 | if (ret < 0) |
1098 | goto sst_write_err; | |
1099 | WARN(ret != 2, "While writing 2 bytes written %i bytes\n", | |
1100 | (int)ret); | |
b94ed087 | 1101 | ret = spi_nor_wait_till_ready(nor); |
b199489d | 1102 | if (ret) |
0bad7b93 | 1103 | goto sst_write_err; |
b199489d HS |
1104 | to += 2; |
1105 | nor->sst_write_second = true; | |
1106 | } | |
1107 | nor->sst_write_second = false; | |
1108 | ||
1109 | write_disable(nor); | |
b94ed087 | 1110 | ret = spi_nor_wait_till_ready(nor); |
b199489d | 1111 | if (ret) |
0bad7b93 | 1112 | goto sst_write_err; |
b199489d HS |
1113 | |
1114 | /* Write out trailing byte if it exists. */ | |
1115 | if (actual != len) { | |
1116 | write_enable(nor); | |
1117 | ||
b02e7f3e | 1118 | nor->program_opcode = SPINOR_OP_BP; |
2dd087b1 | 1119 | ret = nor->write(nor, to, 1, buf + actual); |
0bad7b93 MS |
1120 | if (ret < 0) |
1121 | goto sst_write_err; | |
1122 | WARN(ret != 1, "While writing 1 byte written %i bytes\n", | |
1123 | (int)ret); | |
b94ed087 | 1124 | ret = spi_nor_wait_till_ready(nor); |
b199489d | 1125 | if (ret) |
0bad7b93 | 1126 | goto sst_write_err; |
b199489d | 1127 | write_disable(nor); |
2dd087b1 | 1128 | actual += 1; |
b199489d | 1129 | } |
0bad7b93 | 1130 | sst_write_err: |
2dd087b1 | 1131 | *retlen += actual; |
b199489d HS |
1132 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE); |
1133 | return ret; | |
1134 | } | |
1135 | ||
1136 | /* | |
1137 | * Write an address range to the nor chip. Data must be written in | |
1138 | * FLASH_PAGESIZE chunks. The address range may be any size provided | |
1139 | * it is within the physical boundaries. | |
1140 | */ | |
1141 | static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, | |
1142 | size_t *retlen, const u_char *buf) | |
1143 | { | |
1144 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
e5d05cbd MS |
1145 | size_t page_offset, page_remain, i; |
1146 | ssize_t ret; | |
b199489d HS |
1147 | |
1148 | dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); | |
1149 | ||
1150 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE); | |
1151 | if (ret) | |
1152 | return ret; | |
1153 | ||
e5d05cbd MS |
1154 | for (i = 0; i < len; ) { |
1155 | ssize_t written; | |
b199489d | 1156 | |
e5d05cbd MS |
1157 | page_offset = (to + i) & (nor->page_size - 1); |
1158 | WARN_ONCE(page_offset, | |
1159 | "Writing at offset %zu into a NOR page. Writing partial pages may decrease reliability and increase wear of NOR flash.", | |
1160 | page_offset); | |
b199489d | 1161 | /* the size of data remaining on the first page */ |
e5d05cbd MS |
1162 | page_remain = min_t(size_t, |
1163 | nor->page_size - page_offset, len - i); | |
1164 | ||
1165 | write_enable(nor); | |
1166 | ret = nor->write(nor, to + i, page_remain, buf + i); | |
0bad7b93 MS |
1167 | if (ret < 0) |
1168 | goto write_err; | |
e5d05cbd | 1169 | written = ret; |
1d61dcb3 | 1170 | |
e5d05cbd MS |
1171 | ret = spi_nor_wait_till_ready(nor); |
1172 | if (ret) | |
1173 | goto write_err; | |
1174 | *retlen += written; | |
1175 | i += written; | |
1176 | if (written != page_remain) { | |
1177 | dev_err(nor->dev, | |
1178 | "While writing %zu bytes written %zd bytes\n", | |
1179 | page_remain, written); | |
1180 | ret = -EIO; | |
1181 | goto write_err; | |
b199489d HS |
1182 | } |
1183 | } | |
1184 | ||
1185 | write_err: | |
1186 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE); | |
1d61dcb3 | 1187 | return ret; |
b199489d HS |
1188 | } |
1189 | ||
1190 | static int macronix_quad_enable(struct spi_nor *nor) | |
1191 | { | |
1192 | int ret, val; | |
1193 | ||
1194 | val = read_sr(nor); | |
f49289ce FE |
1195 | if (val < 0) |
1196 | return val; | |
b199489d HS |
1197 | write_enable(nor); |
1198 | ||
fd725234 | 1199 | write_sr(nor, val | SR_QUAD_EN_MX); |
b199489d | 1200 | |
b94ed087 | 1201 | if (spi_nor_wait_till_ready(nor)) |
b199489d HS |
1202 | return 1; |
1203 | ||
1204 | ret = read_sr(nor); | |
1205 | if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) { | |
1206 | dev_err(nor->dev, "Macronix Quad bit not set\n"); | |
1207 | return -EINVAL; | |
1208 | } | |
1209 | ||
1210 | return 0; | |
1211 | } | |
1212 | ||
1213 | /* | |
1214 | * Write status Register and configuration register with 2 bytes | |
1215 | * The first byte will be written to the status register, while the | |
1216 | * second byte will be written to the configuration register. | |
1217 | * Return negative if error occured. | |
1218 | */ | |
1219 | static int write_sr_cr(struct spi_nor *nor, u16 val) | |
1220 | { | |
1221 | nor->cmd_buf[0] = val & 0xff; | |
1222 | nor->cmd_buf[1] = (val >> 8); | |
1223 | ||
f9f3ce83 | 1224 | return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2); |
b199489d HS |
1225 | } |
1226 | ||
1227 | static int spansion_quad_enable(struct spi_nor *nor) | |
1228 | { | |
1229 | int ret; | |
1230 | int quad_en = CR_QUAD_EN_SPAN << 8; | |
1231 | ||
1232 | write_enable(nor); | |
1233 | ||
1234 | ret = write_sr_cr(nor, quad_en); | |
1235 | if (ret < 0) { | |
1236 | dev_err(nor->dev, | |
1237 | "error while writing configuration register\n"); | |
1238 | return -EINVAL; | |
1239 | } | |
1240 | ||
1241 | /* read back and check it */ | |
1242 | ret = read_cr(nor); | |
1243 | if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) { | |
1244 | dev_err(nor->dev, "Spansion Quad bit not set\n"); | |
1245 | return -EINVAL; | |
1246 | } | |
1247 | ||
1248 | return 0; | |
1249 | } | |
1250 | ||
06bb6f5a | 1251 | static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info) |
b199489d HS |
1252 | { |
1253 | int status; | |
1254 | ||
d928a259 | 1255 | switch (JEDEC_MFR(info)) { |
f0d2448e | 1256 | case SNOR_MFR_MACRONIX: |
b199489d HS |
1257 | status = macronix_quad_enable(nor); |
1258 | if (status) { | |
1259 | dev_err(nor->dev, "Macronix quad-read not enabled\n"); | |
1260 | return -EINVAL; | |
1261 | } | |
1262 | return status; | |
f0d2448e | 1263 | case SNOR_MFR_MICRON: |
3b5394a3 | 1264 | return 0; |
b199489d HS |
1265 | default: |
1266 | status = spansion_quad_enable(nor); | |
1267 | if (status) { | |
1268 | dev_err(nor->dev, "Spansion quad-read not enabled\n"); | |
1269 | return -EINVAL; | |
1270 | } | |
1271 | return status; | |
1272 | } | |
1273 | } | |
1274 | ||
1275 | static int spi_nor_check(struct spi_nor *nor) | |
1276 | { | |
1277 | if (!nor->dev || !nor->read || !nor->write || | |
c67cbb83 | 1278 | !nor->read_reg || !nor->write_reg) { |
b199489d HS |
1279 | pr_err("spi-nor: please fill all the necessary fields!\n"); |
1280 | return -EINVAL; | |
1281 | } | |
1282 | ||
b199489d HS |
1283 | return 0; |
1284 | } | |
1285 | ||
70f3ce05 | 1286 | int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) |
b199489d | 1287 | { |
06bb6f5a | 1288 | const struct flash_info *info = NULL; |
b199489d | 1289 | struct device *dev = nor->dev; |
19763671 | 1290 | struct mtd_info *mtd = &nor->mtd; |
9c7d7875 | 1291 | struct device_node *np = spi_nor_get_flash_node(nor); |
b199489d HS |
1292 | int ret; |
1293 | int i; | |
1294 | ||
1295 | ret = spi_nor_check(nor); | |
1296 | if (ret) | |
1297 | return ret; | |
1298 | ||
43163022 | 1299 | if (name) |
06bb6f5a | 1300 | info = spi_nor_match_id(name); |
43163022 | 1301 | /* Try to auto-detect if chip name wasn't specified or not found */ |
06bb6f5a RM |
1302 | if (!info) |
1303 | info = spi_nor_read_id(nor); | |
1304 | if (IS_ERR_OR_NULL(info)) | |
70f3ce05 BH |
1305 | return -ENOENT; |
1306 | ||
58c81957 RM |
1307 | /* |
1308 | * If caller has specified name of flash model that can normally be | |
1309 | * detected using JEDEC, let's verify it. | |
1310 | */ | |
1311 | if (name && info->id_len) { | |
06bb6f5a | 1312 | const struct flash_info *jinfo; |
b199489d | 1313 | |
06bb6f5a RM |
1314 | jinfo = spi_nor_read_id(nor); |
1315 | if (IS_ERR(jinfo)) { | |
1316 | return PTR_ERR(jinfo); | |
1317 | } else if (jinfo != info) { | |
b199489d HS |
1318 | /* |
1319 | * JEDEC knows better, so overwrite platform ID. We | |
1320 | * can't trust partitions any longer, but we'll let | |
1321 | * mtd apply them anyway, since some partitions may be | |
1322 | * marked read-only, and we don't want to lose that | |
1323 | * information, even if it's not 100% accurate. | |
1324 | */ | |
1325 | dev_warn(dev, "found %s, expected %s\n", | |
06bb6f5a RM |
1326 | jinfo->name, info->name); |
1327 | info = jinfo; | |
b199489d HS |
1328 | } |
1329 | } | |
1330 | ||
1331 | mutex_init(&nor->lock); | |
1332 | ||
1333 | /* | |
c6fc2171 BN |
1334 | * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up |
1335 | * with the software protection bits set | |
b199489d HS |
1336 | */ |
1337 | ||
f0d2448e BN |
1338 | if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || |
1339 | JEDEC_MFR(info) == SNOR_MFR_INTEL || | |
76a4707d BN |
1340 | JEDEC_MFR(info) == SNOR_MFR_SST || |
1341 | info->flags & SPI_NOR_HAS_LOCK) { | |
b199489d HS |
1342 | write_enable(nor); |
1343 | write_sr(nor, 0); | |
edf891ef | 1344 | spi_nor_wait_till_ready(nor); |
b199489d HS |
1345 | } |
1346 | ||
32f1b7c8 | 1347 | if (!mtd->name) |
b199489d | 1348 | mtd->name = dev_name(dev); |
c9ec3900 | 1349 | mtd->priv = nor; |
b199489d HS |
1350 | mtd->type = MTD_NORFLASH; |
1351 | mtd->writesize = 1; | |
1352 | mtd->flags = MTD_CAP_NORFLASH; | |
1353 | mtd->size = info->sector_size * info->n_sectors; | |
1354 | mtd->_erase = spi_nor_erase; | |
1355 | mtd->_read = spi_nor_read; | |
1356 | ||
357ca38d | 1357 | /* NOR protection support for STmicro/Micron chips and similar */ |
76a4707d BN |
1358 | if (JEDEC_MFR(info) == SNOR_MFR_MICRON || |
1359 | info->flags & SPI_NOR_HAS_LOCK) { | |
8cc7f33a BN |
1360 | nor->flash_lock = stm_lock; |
1361 | nor->flash_unlock = stm_unlock; | |
5bf0e69b | 1362 | nor->flash_is_locked = stm_is_locked; |
8cc7f33a BN |
1363 | } |
1364 | ||
5bf0e69b | 1365 | if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) { |
b199489d HS |
1366 | mtd->_lock = spi_nor_lock; |
1367 | mtd->_unlock = spi_nor_unlock; | |
5bf0e69b | 1368 | mtd->_is_locked = spi_nor_is_locked; |
b199489d HS |
1369 | } |
1370 | ||
1371 | /* sst nor chips use AAI word program */ | |
1372 | if (info->flags & SST_WRITE) | |
1373 | mtd->_write = sst_write; | |
1374 | else | |
1375 | mtd->_write = spi_nor_write; | |
1376 | ||
51983b7d BN |
1377 | if (info->flags & USE_FSR) |
1378 | nor->flags |= SNOR_F_USE_FSR; | |
3dd8012a BN |
1379 | if (info->flags & SPI_NOR_HAS_TB) |
1380 | nor->flags |= SNOR_F_HAS_SR_TB; | |
c14dedde | 1381 | |
57cf26c1 | 1382 | #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS |
b199489d HS |
1383 | /* prefer "small sector" erase if possible */ |
1384 | if (info->flags & SECT_4K) { | |
b02e7f3e | 1385 | nor->erase_opcode = SPINOR_OP_BE_4K; |
b199489d HS |
1386 | mtd->erasesize = 4096; |
1387 | } else if (info->flags & SECT_4K_PMC) { | |
b02e7f3e | 1388 | nor->erase_opcode = SPINOR_OP_BE_4K_PMC; |
b199489d | 1389 | mtd->erasesize = 4096; |
57cf26c1 RM |
1390 | } else |
1391 | #endif | |
1392 | { | |
b02e7f3e | 1393 | nor->erase_opcode = SPINOR_OP_SE; |
b199489d HS |
1394 | mtd->erasesize = info->sector_size; |
1395 | } | |
1396 | ||
1397 | if (info->flags & SPI_NOR_NO_ERASE) | |
1398 | mtd->flags |= MTD_NO_ERASE; | |
1399 | ||
1400 | mtd->dev.parent = dev; | |
1401 | nor->page_size = info->page_size; | |
1402 | mtd->writebufsize = nor->page_size; | |
1403 | ||
1404 | if (np) { | |
1405 | /* If we were instantiated by DT, use it */ | |
1406 | if (of_property_read_bool(np, "m25p,fast-read")) | |
1407 | nor->flash_read = SPI_NOR_FAST; | |
1408 | else | |
1409 | nor->flash_read = SPI_NOR_NORMAL; | |
1410 | } else { | |
1411 | /* If we weren't instantiated by DT, default to fast-read */ | |
1412 | nor->flash_read = SPI_NOR_FAST; | |
1413 | } | |
1414 | ||
1415 | /* Some devices cannot do fast-read, no matter what DT tells us */ | |
1416 | if (info->flags & SPI_NOR_NO_FR) | |
1417 | nor->flash_read = SPI_NOR_NORMAL; | |
1418 | ||
1419 | /* Quad/Dual-read mode takes precedence over fast/normal */ | |
1420 | if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) { | |
d928a259 | 1421 | ret = set_quad_mode(nor, info); |
b199489d HS |
1422 | if (ret) { |
1423 | dev_err(dev, "quad mode not supported\n"); | |
1424 | return ret; | |
1425 | } | |
1426 | nor->flash_read = SPI_NOR_QUAD; | |
1427 | } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) { | |
1428 | nor->flash_read = SPI_NOR_DUAL; | |
1429 | } | |
1430 | ||
1431 | /* Default commands */ | |
1432 | switch (nor->flash_read) { | |
1433 | case SPI_NOR_QUAD: | |
58b89a1f | 1434 | nor->read_opcode = SPINOR_OP_READ_1_1_4; |
b199489d HS |
1435 | break; |
1436 | case SPI_NOR_DUAL: | |
58b89a1f | 1437 | nor->read_opcode = SPINOR_OP_READ_1_1_2; |
b199489d HS |
1438 | break; |
1439 | case SPI_NOR_FAST: | |
58b89a1f | 1440 | nor->read_opcode = SPINOR_OP_READ_FAST; |
b199489d HS |
1441 | break; |
1442 | case SPI_NOR_NORMAL: | |
58b89a1f | 1443 | nor->read_opcode = SPINOR_OP_READ; |
b199489d HS |
1444 | break; |
1445 | default: | |
1446 | dev_err(dev, "No Read opcode defined\n"); | |
1447 | return -EINVAL; | |
1448 | } | |
1449 | ||
b02e7f3e | 1450 | nor->program_opcode = SPINOR_OP_PP; |
b199489d HS |
1451 | |
1452 | if (info->addr_width) | |
1453 | nor->addr_width = info->addr_width; | |
1454 | else if (mtd->size > 0x1000000) { | |
1455 | /* enable 4-byte addressing if the device exceeds 16MiB */ | |
1456 | nor->addr_width = 4; | |
f0d2448e | 1457 | if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) { |
b199489d HS |
1458 | /* Dedicated 4-byte command set */ |
1459 | switch (nor->flash_read) { | |
1460 | case SPI_NOR_QUAD: | |
58b89a1f | 1461 | nor->read_opcode = SPINOR_OP_READ4_1_1_4; |
b199489d HS |
1462 | break; |
1463 | case SPI_NOR_DUAL: | |
58b89a1f | 1464 | nor->read_opcode = SPINOR_OP_READ4_1_1_2; |
b199489d HS |
1465 | break; |
1466 | case SPI_NOR_FAST: | |
58b89a1f | 1467 | nor->read_opcode = SPINOR_OP_READ4_FAST; |
b199489d HS |
1468 | break; |
1469 | case SPI_NOR_NORMAL: | |
58b89a1f | 1470 | nor->read_opcode = SPINOR_OP_READ4; |
b199489d HS |
1471 | break; |
1472 | } | |
b02e7f3e | 1473 | nor->program_opcode = SPINOR_OP_PP_4B; |
b199489d | 1474 | /* No small sector erase for 4-byte command set */ |
b02e7f3e | 1475 | nor->erase_opcode = SPINOR_OP_SE_4B; |
b199489d HS |
1476 | mtd->erasesize = info->sector_size; |
1477 | } else | |
d928a259 | 1478 | set_4byte(nor, info, 1); |
b199489d HS |
1479 | } else { |
1480 | nor->addr_width = 3; | |
1481 | } | |
1482 | ||
c67cbb83 BN |
1483 | if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { |
1484 | dev_err(dev, "address width is too large: %u\n", | |
1485 | nor->addr_width); | |
1486 | return -EINVAL; | |
1487 | } | |
1488 | ||
b199489d HS |
1489 | nor->read_dummy = spi_nor_read_dummy_cycles(nor); |
1490 | ||
06bb6f5a | 1491 | dev_info(dev, "%s (%lld Kbytes)\n", info->name, |
b199489d HS |
1492 | (long long)mtd->size >> 10); |
1493 | ||
1494 | dev_dbg(dev, | |
1495 | "mtd .name = %s, .size = 0x%llx (%lldMiB), " | |
1496 | ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", | |
1497 | mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20), | |
1498 | mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions); | |
1499 | ||
1500 | if (mtd->numeraseregions) | |
1501 | for (i = 0; i < mtd->numeraseregions; i++) | |
1502 | dev_dbg(dev, | |
1503 | "mtd.eraseregions[%d] = { .offset = 0x%llx, " | |
1504 | ".erasesize = 0x%.8x (%uKiB), " | |
1505 | ".numblocks = %d }\n", | |
1506 | i, (long long)mtd->eraseregions[i].offset, | |
1507 | mtd->eraseregions[i].erasesize, | |
1508 | mtd->eraseregions[i].erasesize / 1024, | |
1509 | mtd->eraseregions[i].numblocks); | |
1510 | return 0; | |
1511 | } | |
b61834b0 | 1512 | EXPORT_SYMBOL_GPL(spi_nor_scan); |
b199489d | 1513 | |
06bb6f5a | 1514 | static const struct flash_info *spi_nor_match_id(const char *name) |
0d8c11c0 | 1515 | { |
06bb6f5a | 1516 | const struct flash_info *id = spi_nor_ids; |
0d8c11c0 | 1517 | |
2ff46e6f | 1518 | while (id->name) { |
0d8c11c0 HS |
1519 | if (!strcmp(name, id->name)) |
1520 | return id; | |
1521 | id++; | |
1522 | } | |
1523 | return NULL; | |
1524 | } | |
1525 | ||
b199489d HS |
1526 | MODULE_LICENSE("GPL"); |
1527 | MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>"); | |
1528 | MODULE_AUTHOR("Mike Lavender"); | |
1529 | MODULE_DESCRIPTION("framework for SPI NOR"); |