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Commit | Line | Data |
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b199489d | 1 | /* |
8eabdd1e HS |
2 | * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with |
3 | * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c | |
4 | * | |
5 | * Copyright (C) 2005, Intec Automation Inc. | |
6 | * Copyright (C) 2014, Freescale Semiconductor, Inc. | |
b199489d HS |
7 | * |
8 | * This code is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/err.h> | |
14 | #include <linux/errno.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/mutex.h> | |
18 | #include <linux/math64.h> | |
09b6a377 | 19 | #include <linux/sizes.h> |
b199489d | 20 | |
b199489d HS |
21 | #include <linux/mtd/mtd.h> |
22 | #include <linux/of_platform.h> | |
23 | #include <linux/spi/flash.h> | |
24 | #include <linux/mtd/spi-nor.h> | |
25 | ||
26 | /* Define max times to check status register before we give up. */ | |
09b6a377 FS |
27 | |
28 | /* | |
29 | * For everything but full-chip erase; probably could be much smaller, but kept | |
30 | * around for safety for now | |
31 | */ | |
32 | #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) | |
33 | ||
34 | /* | |
35 | * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up | |
36 | * for larger flash | |
37 | */ | |
38 | #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ) | |
b199489d | 39 | |
d928a259 | 40 | #define SPI_NOR_MAX_ID_LEN 6 |
c67cbb83 | 41 | #define SPI_NOR_MAX_ADDR_WIDTH 4 |
d928a259 HS |
42 | |
43 | struct flash_info { | |
06bb6f5a RM |
44 | char *name; |
45 | ||
d928a259 HS |
46 | /* |
47 | * This array stores the ID bytes. | |
48 | * The first three bytes are the JEDIC ID. | |
49 | * JEDEC ID zero means "no ID" (mostly older chips). | |
50 | */ | |
51 | u8 id[SPI_NOR_MAX_ID_LEN]; | |
52 | u8 id_len; | |
53 | ||
54 | /* The size listed here is what works with SPINOR_OP_SE, which isn't | |
55 | * necessarily called a "sector" by the vendor. | |
56 | */ | |
57 | unsigned sector_size; | |
58 | u16 n_sectors; | |
59 | ||
60 | u16 page_size; | |
61 | u16 addr_width; | |
62 | ||
63 | u16 flags; | |
64 | #define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */ | |
65 | #define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */ | |
66 | #define SST_WRITE 0x04 /* use SST byte programming */ | |
67 | #define SPI_NOR_NO_FR 0x08 /* Can't do fastread */ | |
68 | #define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */ | |
69 | #define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */ | |
70 | #define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */ | |
71 | #define USE_FSR 0x80 /* use flag status register */ | |
72 | }; | |
73 | ||
74 | #define JEDEC_MFR(info) ((info)->id[0]) | |
b199489d | 75 | |
06bb6f5a | 76 | static const struct flash_info *spi_nor_match_id(const char *name); |
70f3ce05 | 77 | |
b199489d HS |
78 | /* |
79 | * Read the status register, returning its value in the location | |
80 | * Return the status register value. | |
81 | * Returns negative if error occurred. | |
82 | */ | |
83 | static int read_sr(struct spi_nor *nor) | |
84 | { | |
85 | int ret; | |
86 | u8 val; | |
87 | ||
b02e7f3e | 88 | ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1); |
b199489d HS |
89 | if (ret < 0) { |
90 | pr_err("error %d reading SR\n", (int) ret); | |
91 | return ret; | |
92 | } | |
93 | ||
94 | return val; | |
95 | } | |
96 | ||
c14dedde | 97 | /* |
98 | * Read the flag status register, returning its value in the location | |
99 | * Return the status register value. | |
100 | * Returns negative if error occurred. | |
101 | */ | |
102 | static int read_fsr(struct spi_nor *nor) | |
103 | { | |
104 | int ret; | |
105 | u8 val; | |
106 | ||
107 | ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1); | |
108 | if (ret < 0) { | |
109 | pr_err("error %d reading FSR\n", ret); | |
110 | return ret; | |
111 | } | |
112 | ||
113 | return val; | |
114 | } | |
115 | ||
b199489d HS |
116 | /* |
117 | * Read configuration register, returning its value in the | |
118 | * location. Return the configuration register value. | |
119 | * Returns negative if error occured. | |
120 | */ | |
121 | static int read_cr(struct spi_nor *nor) | |
122 | { | |
123 | int ret; | |
124 | u8 val; | |
125 | ||
b02e7f3e | 126 | ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1); |
b199489d HS |
127 | if (ret < 0) { |
128 | dev_err(nor->dev, "error %d reading CR\n", ret); | |
129 | return ret; | |
130 | } | |
131 | ||
132 | return val; | |
133 | } | |
134 | ||
135 | /* | |
136 | * Dummy Cycle calculation for different type of read. | |
137 | * It can be used to support more commands with | |
138 | * different dummy cycle requirements. | |
139 | */ | |
140 | static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor) | |
141 | { | |
142 | switch (nor->flash_read) { | |
143 | case SPI_NOR_FAST: | |
144 | case SPI_NOR_DUAL: | |
145 | case SPI_NOR_QUAD: | |
0b78a2cf | 146 | return 8; |
b199489d HS |
147 | case SPI_NOR_NORMAL: |
148 | return 0; | |
149 | } | |
150 | return 0; | |
151 | } | |
152 | ||
153 | /* | |
154 | * Write status register 1 byte | |
155 | * Returns negative if error occurred. | |
156 | */ | |
157 | static inline int write_sr(struct spi_nor *nor, u8 val) | |
158 | { | |
159 | nor->cmd_buf[0] = val; | |
f9f3ce83 | 160 | return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1); |
b199489d HS |
161 | } |
162 | ||
163 | /* | |
164 | * Set write enable latch with Write Enable command. | |
165 | * Returns negative if error occurred. | |
166 | */ | |
167 | static inline int write_enable(struct spi_nor *nor) | |
168 | { | |
f9f3ce83 | 169 | return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0); |
b199489d HS |
170 | } |
171 | ||
172 | /* | |
173 | * Send write disble instruction to the chip. | |
174 | */ | |
175 | static inline int write_disable(struct spi_nor *nor) | |
176 | { | |
f9f3ce83 | 177 | return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0); |
b199489d HS |
178 | } |
179 | ||
180 | static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) | |
181 | { | |
182 | return mtd->priv; | |
183 | } | |
184 | ||
185 | /* Enable/disable 4-byte addressing mode. */ | |
06bb6f5a | 186 | static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info, |
d928a259 | 187 | int enable) |
b199489d HS |
188 | { |
189 | int status; | |
190 | bool need_wren = false; | |
191 | u8 cmd; | |
192 | ||
d928a259 | 193 | switch (JEDEC_MFR(info)) { |
f0d2448e | 194 | case SNOR_MFR_MICRON: |
b199489d HS |
195 | /* Some Micron need WREN command; all will accept it */ |
196 | need_wren = true; | |
f0d2448e BN |
197 | case SNOR_MFR_MACRONIX: |
198 | case SNOR_MFR_WINBOND: | |
b199489d HS |
199 | if (need_wren) |
200 | write_enable(nor); | |
201 | ||
b02e7f3e | 202 | cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; |
f9f3ce83 | 203 | status = nor->write_reg(nor, cmd, NULL, 0); |
b199489d HS |
204 | if (need_wren) |
205 | write_disable(nor); | |
206 | ||
207 | return status; | |
208 | default: | |
209 | /* Spansion style */ | |
210 | nor->cmd_buf[0] = enable << 7; | |
f9f3ce83 | 211 | return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1); |
b199489d HS |
212 | } |
213 | } | |
51983b7d | 214 | static inline int spi_nor_sr_ready(struct spi_nor *nor) |
b199489d | 215 | { |
51983b7d BN |
216 | int sr = read_sr(nor); |
217 | if (sr < 0) | |
218 | return sr; | |
219 | else | |
220 | return !(sr & SR_WIP); | |
221 | } | |
b199489d | 222 | |
51983b7d BN |
223 | static inline int spi_nor_fsr_ready(struct spi_nor *nor) |
224 | { | |
225 | int fsr = read_fsr(nor); | |
226 | if (fsr < 0) | |
227 | return fsr; | |
228 | else | |
229 | return fsr & FSR_READY; | |
230 | } | |
b199489d | 231 | |
51983b7d BN |
232 | static int spi_nor_ready(struct spi_nor *nor) |
233 | { | |
234 | int sr, fsr; | |
235 | sr = spi_nor_sr_ready(nor); | |
236 | if (sr < 0) | |
237 | return sr; | |
238 | fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; | |
239 | if (fsr < 0) | |
240 | return fsr; | |
241 | return sr && fsr; | |
b199489d HS |
242 | } |
243 | ||
b94ed087 BN |
244 | /* |
245 | * Service routine to read status register until ready, or timeout occurs. | |
246 | * Returns non-zero if error. | |
247 | */ | |
09b6a377 FS |
248 | static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, |
249 | unsigned long timeout_jiffies) | |
c14dedde | 250 | { |
251 | unsigned long deadline; | |
a95ce92e | 252 | int timeout = 0, ret; |
c14dedde | 253 | |
09b6a377 | 254 | deadline = jiffies + timeout_jiffies; |
c14dedde | 255 | |
a95ce92e BN |
256 | while (!timeout) { |
257 | if (time_after_eq(jiffies, deadline)) | |
258 | timeout = 1; | |
c14dedde | 259 | |
51983b7d BN |
260 | ret = spi_nor_ready(nor); |
261 | if (ret < 0) | |
262 | return ret; | |
263 | if (ret) | |
264 | return 0; | |
a95ce92e BN |
265 | |
266 | cond_resched(); | |
267 | } | |
268 | ||
269 | dev_err(nor->dev, "flash operation timed out\n"); | |
c14dedde | 270 | |
271 | return -ETIMEDOUT; | |
272 | } | |
273 | ||
09b6a377 FS |
274 | static int spi_nor_wait_till_ready(struct spi_nor *nor) |
275 | { | |
276 | return spi_nor_wait_till_ready_with_timeout(nor, | |
277 | DEFAULT_READY_WAIT_JIFFIES); | |
278 | } | |
279 | ||
b199489d HS |
280 | /* |
281 | * Erase the whole flash memory | |
282 | * | |
283 | * Returns 0 if successful, non-zero otherwise. | |
284 | */ | |
285 | static int erase_chip(struct spi_nor *nor) | |
286 | { | |
19763671 | 287 | dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10)); |
b199489d | 288 | |
f9f3ce83 | 289 | return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0); |
b199489d HS |
290 | } |
291 | ||
292 | static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops) | |
293 | { | |
294 | int ret = 0; | |
295 | ||
296 | mutex_lock(&nor->lock); | |
297 | ||
298 | if (nor->prepare) { | |
299 | ret = nor->prepare(nor, ops); | |
300 | if (ret) { | |
301 | dev_err(nor->dev, "failed in the preparation.\n"); | |
302 | mutex_unlock(&nor->lock); | |
303 | return ret; | |
304 | } | |
305 | } | |
306 | return ret; | |
307 | } | |
308 | ||
309 | static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops) | |
310 | { | |
311 | if (nor->unprepare) | |
312 | nor->unprepare(nor, ops); | |
313 | mutex_unlock(&nor->lock); | |
314 | } | |
315 | ||
c67cbb83 BN |
316 | /* |
317 | * Initiate the erasure of a single sector | |
318 | */ | |
319 | static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) | |
320 | { | |
321 | u8 buf[SPI_NOR_MAX_ADDR_WIDTH]; | |
322 | int i; | |
323 | ||
324 | if (nor->erase) | |
325 | return nor->erase(nor, addr); | |
326 | ||
327 | /* | |
328 | * Default implementation, if driver doesn't have a specialized HW | |
329 | * control | |
330 | */ | |
331 | for (i = nor->addr_width - 1; i >= 0; i--) { | |
332 | buf[i] = addr & 0xff; | |
333 | addr >>= 8; | |
334 | } | |
335 | ||
336 | return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width); | |
337 | } | |
338 | ||
b199489d HS |
339 | /* |
340 | * Erase an address range on the nor chip. The address range may extend | |
341 | * one or more erase sectors. Return an error is there is a problem erasing. | |
342 | */ | |
343 | static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) | |
344 | { | |
345 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
346 | u32 addr, len; | |
347 | uint32_t rem; | |
348 | int ret; | |
349 | ||
350 | dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, | |
351 | (long long)instr->len); | |
352 | ||
353 | div_u64_rem(instr->len, mtd->erasesize, &rem); | |
354 | if (rem) | |
355 | return -EINVAL; | |
356 | ||
357 | addr = instr->addr; | |
358 | len = instr->len; | |
359 | ||
360 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE); | |
361 | if (ret) | |
362 | return ret; | |
363 | ||
364 | /* whole-chip erase? */ | |
365 | if (len == mtd->size) { | |
09b6a377 FS |
366 | unsigned long timeout; |
367 | ||
05241aea BN |
368 | write_enable(nor); |
369 | ||
b199489d HS |
370 | if (erase_chip(nor)) { |
371 | ret = -EIO; | |
372 | goto erase_err; | |
373 | } | |
374 | ||
09b6a377 FS |
375 | /* |
376 | * Scale the timeout linearly with the size of the flash, with | |
377 | * a minimum calibrated to an old 2MB flash. We could try to | |
378 | * pull these from CFI/SFDP, but these values should be good | |
379 | * enough for now. | |
380 | */ | |
381 | timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, | |
382 | CHIP_ERASE_2MB_READY_WAIT_JIFFIES * | |
383 | (unsigned long)(mtd->size / SZ_2M)); | |
384 | ret = spi_nor_wait_till_ready_with_timeout(nor, timeout); | |
dfa9c0cb BN |
385 | if (ret) |
386 | goto erase_err; | |
387 | ||
b199489d | 388 | /* REVISIT in some cases we could speed up erasing large regions |
b02e7f3e | 389 | * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up |
b199489d HS |
390 | * to use "small sector erase", but that's not always optimal. |
391 | */ | |
392 | ||
393 | /* "sector"-at-a-time erase */ | |
394 | } else { | |
395 | while (len) { | |
05241aea BN |
396 | write_enable(nor); |
397 | ||
c67cbb83 BN |
398 | ret = spi_nor_erase_sector(nor, addr); |
399 | if (ret) | |
b199489d | 400 | goto erase_err; |
b199489d HS |
401 | |
402 | addr += mtd->erasesize; | |
403 | len -= mtd->erasesize; | |
dfa9c0cb BN |
404 | |
405 | ret = spi_nor_wait_till_ready(nor); | |
406 | if (ret) | |
407 | goto erase_err; | |
b199489d HS |
408 | } |
409 | } | |
410 | ||
05241aea BN |
411 | write_disable(nor); |
412 | ||
d6af2694 | 413 | erase_err: |
b199489d HS |
414 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); |
415 | ||
d6af2694 | 416 | instr->state = ret ? MTD_ERASE_FAILED : MTD_ERASE_DONE; |
b199489d HS |
417 | mtd_erase_callback(instr); |
418 | ||
419 | return ret; | |
b199489d HS |
420 | } |
421 | ||
62593cf4 BN |
422 | static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs, |
423 | uint64_t *len) | |
424 | { | |
425 | struct mtd_info *mtd = &nor->mtd; | |
426 | u8 mask = SR_BP2 | SR_BP1 | SR_BP0; | |
427 | int shift = ffs(mask) - 1; | |
428 | int pow; | |
429 | ||
430 | if (!(sr & mask)) { | |
431 | /* No protection */ | |
432 | *ofs = 0; | |
433 | *len = 0; | |
434 | } else { | |
435 | pow = ((sr & mask) ^ mask) >> shift; | |
436 | *len = mtd->size >> pow; | |
437 | *ofs = mtd->size - *len; | |
438 | } | |
439 | } | |
440 | ||
441 | /* | |
442 | * Return 1 if the entire region is locked, 0 otherwise | |
443 | */ | |
444 | static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, | |
445 | u8 sr) | |
446 | { | |
447 | loff_t lock_offs; | |
448 | uint64_t lock_len; | |
449 | ||
450 | stm_get_locked_range(nor, sr, &lock_offs, &lock_len); | |
451 | ||
452 | return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); | |
453 | } | |
454 | ||
455 | /* | |
456 | * Lock a region of the flash. Compatible with ST Micro and similar flash. | |
457 | * Supports only the block protection bits BP{0,1,2} in the status register | |
458 | * (SR). Does not support these features found in newer SR bitfields: | |
459 | * - TB: top/bottom protect - only handle TB=0 (top protect) | |
460 | * - SEC: sector/block protect - only handle SEC=0 (block protect) | |
461 | * - CMP: complement protect - only support CMP=0 (range is not complemented) | |
462 | * | |
463 | * Sample table portion for 8MB flash (Winbond w25q64fw): | |
464 | * | |
465 | * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion | |
466 | * -------------------------------------------------------------------------- | |
467 | * X | X | 0 | 0 | 0 | NONE | NONE | |
468 | * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 | |
469 | * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 | |
470 | * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 | |
471 | * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 | |
472 | * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 | |
473 | * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 | |
474 | * X | X | 1 | 1 | 1 | 8 MB | ALL | |
475 | * | |
476 | * Returns negative on errors, 0 on success. | |
477 | */ | |
8cc7f33a | 478 | static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) |
b199489d | 479 | { |
19763671 | 480 | struct mtd_info *mtd = &nor->mtd; |
f49289ce | 481 | int status_old, status_new; |
62593cf4 BN |
482 | u8 mask = SR_BP2 | SR_BP1 | SR_BP0; |
483 | u8 shift = ffs(mask) - 1, pow, val; | |
32321e95 | 484 | int ret; |
b199489d | 485 | |
b199489d | 486 | status_old = read_sr(nor); |
f49289ce FE |
487 | if (status_old < 0) |
488 | return status_old; | |
b199489d | 489 | |
62593cf4 BN |
490 | /* SPI NOR always locks to the end */ |
491 | if (ofs + len != mtd->size) { | |
492 | /* Does combined region extend to end? */ | |
493 | if (!stm_is_locked_sr(nor, ofs + len, mtd->size - ofs - len, | |
494 | status_old)) | |
495 | return -EINVAL; | |
496 | len = mtd->size - ofs; | |
497 | } | |
498 | ||
499 | /* | |
500 | * Need smallest pow such that: | |
501 | * | |
502 | * 1 / (2^pow) <= (len / size) | |
503 | * | |
504 | * so (assuming power-of-2 size) we do: | |
505 | * | |
506 | * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) | |
507 | */ | |
508 | pow = ilog2(mtd->size) - ilog2(len); | |
509 | val = mask - (pow << shift); | |
510 | if (val & ~mask) | |
511 | return -EINVAL; | |
512 | /* Don't "lock" with no region! */ | |
513 | if (!(val & mask)) | |
514 | return -EINVAL; | |
515 | ||
516 | status_new = (status_old & ~mask) | val; | |
b199489d HS |
517 | |
518 | /* Only modify protection if it will not unlock other areas */ | |
62593cf4 BN |
519 | if ((status_new & mask) <= (status_old & mask)) |
520 | return -EINVAL; | |
b199489d | 521 | |
62593cf4 | 522 | write_enable(nor); |
32321e95 EG |
523 | ret = write_sr(nor, status_new); |
524 | if (ret) | |
525 | return ret; | |
526 | return spi_nor_wait_till_ready(nor); | |
b199489d HS |
527 | } |
528 | ||
62593cf4 BN |
529 | /* |
530 | * Unlock a region of the flash. See stm_lock() for more info | |
531 | * | |
532 | * Returns negative on errors, 0 on success. | |
533 | */ | |
8cc7f33a | 534 | static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) |
b199489d | 535 | { |
19763671 | 536 | struct mtd_info *mtd = &nor->mtd; |
f49289ce | 537 | int status_old, status_new; |
62593cf4 BN |
538 | u8 mask = SR_BP2 | SR_BP1 | SR_BP0; |
539 | u8 shift = ffs(mask) - 1, pow, val; | |
32321e95 | 540 | int ret; |
b199489d | 541 | |
b199489d | 542 | status_old = read_sr(nor); |
f49289ce FE |
543 | if (status_old < 0) |
544 | return status_old; | |
b199489d | 545 | |
62593cf4 | 546 | /* Cannot unlock; would unlock larger region than requested */ |
a32d5b72 BN |
547 | if (stm_is_locked_sr(nor, ofs - mtd->erasesize, mtd->erasesize, |
548 | status_old)) | |
62593cf4 | 549 | return -EINVAL; |
b199489d | 550 | |
62593cf4 BN |
551 | /* |
552 | * Need largest pow such that: | |
553 | * | |
554 | * 1 / (2^pow) >= (len / size) | |
555 | * | |
556 | * so (assuming power-of-2 size) we do: | |
557 | * | |
558 | * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) | |
559 | */ | |
560 | pow = ilog2(mtd->size) - order_base_2(mtd->size - (ofs + len)); | |
561 | if (ofs + len == mtd->size) { | |
562 | val = 0; /* fully unlocked */ | |
563 | } else { | |
564 | val = mask - (pow << shift); | |
565 | /* Some power-of-two sizes are not supported */ | |
566 | if (val & ~mask) | |
567 | return -EINVAL; | |
b199489d HS |
568 | } |
569 | ||
62593cf4 BN |
570 | status_new = (status_old & ~mask) | val; |
571 | ||
572 | /* Only modify protection if it will not lock other areas */ | |
573 | if ((status_new & mask) >= (status_old & mask)) | |
574 | return -EINVAL; | |
575 | ||
576 | write_enable(nor); | |
32321e95 EG |
577 | ret = write_sr(nor, status_new); |
578 | if (ret) | |
579 | return ret; | |
580 | return spi_nor_wait_till_ready(nor); | |
8cc7f33a BN |
581 | } |
582 | ||
5bf0e69b BN |
583 | /* |
584 | * Check if a region of the flash is (completely) locked. See stm_lock() for | |
585 | * more info. | |
586 | * | |
587 | * Returns 1 if entire region is locked, 0 if any portion is unlocked, and | |
588 | * negative on errors. | |
589 | */ | |
590 | static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) | |
591 | { | |
592 | int status; | |
593 | ||
594 | status = read_sr(nor); | |
595 | if (status < 0) | |
596 | return status; | |
597 | ||
598 | return stm_is_locked_sr(nor, ofs, len, status); | |
599 | } | |
600 | ||
8cc7f33a BN |
601 | static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
602 | { | |
603 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
604 | int ret; | |
605 | ||
606 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK); | |
607 | if (ret) | |
608 | return ret; | |
609 | ||
610 | ret = nor->flash_lock(nor, ofs, len); | |
611 | ||
b199489d HS |
612 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK); |
613 | return ret; | |
614 | } | |
615 | ||
8cc7f33a BN |
616 | static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
617 | { | |
618 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
619 | int ret; | |
620 | ||
621 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK); | |
622 | if (ret) | |
623 | return ret; | |
624 | ||
625 | ret = nor->flash_unlock(nor, ofs, len); | |
626 | ||
627 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK); | |
628 | return ret; | |
629 | } | |
630 | ||
5bf0e69b BN |
631 | static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
632 | { | |
633 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
634 | int ret; | |
635 | ||
636 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK); | |
637 | if (ret) | |
638 | return ret; | |
639 | ||
640 | ret = nor->flash_is_locked(nor, ofs, len); | |
641 | ||
642 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK); | |
643 | return ret; | |
644 | } | |
645 | ||
09ffafb6 | 646 | /* Used when the "_ext_id" is two bytes at most */ |
b199489d | 647 | #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
09ffafb6 HS |
648 | .id = { \ |
649 | ((_jedec_id) >> 16) & 0xff, \ | |
650 | ((_jedec_id) >> 8) & 0xff, \ | |
651 | (_jedec_id) & 0xff, \ | |
652 | ((_ext_id) >> 8) & 0xff, \ | |
653 | (_ext_id) & 0xff, \ | |
654 | }, \ | |
655 | .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ | |
b199489d HS |
656 | .sector_size = (_sector_size), \ |
657 | .n_sectors = (_n_sectors), \ | |
658 | .page_size = 256, \ | |
06bb6f5a | 659 | .flags = (_flags), |
b199489d | 660 | |
6d7604e5 | 661 | #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
6d7604e5 HS |
662 | .id = { \ |
663 | ((_jedec_id) >> 16) & 0xff, \ | |
664 | ((_jedec_id) >> 8) & 0xff, \ | |
665 | (_jedec_id) & 0xff, \ | |
666 | ((_ext_id) >> 16) & 0xff, \ | |
667 | ((_ext_id) >> 8) & 0xff, \ | |
668 | (_ext_id) & 0xff, \ | |
669 | }, \ | |
670 | .id_len = 6, \ | |
671 | .sector_size = (_sector_size), \ | |
672 | .n_sectors = (_n_sectors), \ | |
673 | .page_size = 256, \ | |
06bb6f5a | 674 | .flags = (_flags), |
6d7604e5 | 675 | |
b199489d | 676 | #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \ |
b199489d HS |
677 | .sector_size = (_sector_size), \ |
678 | .n_sectors = (_n_sectors), \ | |
679 | .page_size = (_page_size), \ | |
680 | .addr_width = (_addr_width), \ | |
06bb6f5a | 681 | .flags = (_flags), |
b199489d HS |
682 | |
683 | /* NOTE: double check command sets and memory organization when you add | |
684 | * more nor chips. This current list focusses on newer chips, which | |
685 | * have been converging on command sets which including JEDEC ID. | |
c19900ed RM |
686 | * |
687 | * All newly added entries should describe *hardware* and should use SECT_4K | |
688 | * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage | |
689 | * scenarios excluding small sectors there is config option that can be | |
690 | * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS. | |
691 | * For historical (and compatibility) reasons (before we got above config) some | |
692 | * old entries may be missing 4K flag. | |
b199489d | 693 | */ |
06bb6f5a | 694 | static const struct flash_info spi_nor_ids[] = { |
b199489d HS |
695 | /* Atmel -- some are (confusingly) marketed as "DataFlash" */ |
696 | { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) }, | |
697 | { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) }, | |
698 | ||
699 | { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) }, | |
700 | { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, | |
701 | { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) }, | |
702 | ||
703 | { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) }, | |
704 | { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, | |
705 | { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) }, | |
706 | { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, | |
707 | ||
708 | { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, | |
709 | ||
710 | /* EON -- en25xxx */ | |
711 | { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, | |
712 | { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, | |
713 | { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) }, | |
714 | { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) }, | |
715 | { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, | |
a41595b3 | 716 | { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) }, |
b199489d | 717 | { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) }, |
c19900ed | 718 | { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, |
b199489d HS |
719 | |
720 | /* ESMT */ | |
721 | { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) }, | |
722 | ||
723 | /* Everspin */ | |
724 | { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
725 | { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
726 | ||
ce56ce7d RL |
727 | /* Fujitsu */ |
728 | { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) }, | |
729 | ||
b199489d HS |
730 | /* GigaDevice */ |
731 | { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) }, | |
732 | { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) }, | |
fcc87a95 | 733 | { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K) }, |
b199489d HS |
734 | |
735 | /* Intel/Numonyx -- xxxs33b */ | |
736 | { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) }, | |
737 | { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, | |
738 | { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, | |
739 | ||
b79c332f GJ |
740 | /* ISSI */ |
741 | { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) }, | |
742 | ||
b199489d | 743 | /* Macronix */ |
660b5b07 | 744 | { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) }, |
b199489d HS |
745 | { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, |
746 | { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, | |
747 | { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, | |
748 | { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, | |
0501f2e5 | 749 | { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) }, |
b199489d | 750 | { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) }, |
0501f2e5 | 751 | { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) }, |
81a1209c | 752 | { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) }, |
b199489d HS |
753 | { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, |
754 | { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, | |
755 | { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) }, | |
756 | { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, | |
757 | { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) }, | |
758 | { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) }, | |
759 | ||
760 | /* Micron */ | |
548cd3ab | 761 | { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, |
f9bcb6dc | 762 | { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, |
0db7fae2 | 763 | { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, |
2a06c7b1 | 764 | { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, |
548cd3ab BH |
765 | { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, |
766 | { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) }, | |
767 | { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, | |
768 | { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, | |
769 | { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, | |
770 | { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, | |
b199489d HS |
771 | |
772 | /* PMC */ | |
773 | { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) }, | |
774 | { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) }, | |
775 | { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) }, | |
776 | ||
777 | /* Spansion -- single (large) sector size only, at least | |
778 | * for the chips listed here (without boot sectors). | |
779 | */ | |
9ab86995 | 780 | { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
0f12a27b | 781 | { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
b199489d HS |
782 | { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) }, |
783 | { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
784 | { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
785 | { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, | |
786 | { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, | |
787 | { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, | |
c19900ed | 788 | { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, |
c1752086 JG |
789 | { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
790 | { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
b199489d HS |
791 | { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, |
792 | { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, | |
793 | { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, | |
794 | { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, | |
795 | { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, | |
7c748f57 | 796 | { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
adf508c3 JE |
797 | { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
798 | { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
b199489d | 799 | { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, |
c0826679 | 800 | { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
c19900ed | 801 | { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) }, |
413780d7 | 802 | { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) }, |
aada20cd | 803 | { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) }, |
b199489d HS |
804 | |
805 | /* SST -- large erase sizes are "overlays", "sectors" are 4K */ | |
806 | { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, | |
807 | { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, | |
808 | { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, | |
809 | { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, | |
810 | { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, | |
811 | { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, | |
812 | { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, | |
813 | { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, | |
a1d97ef9 | 814 | { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) }, |
c887be71 | 815 | { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) }, |
b199489d | 816 | { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, |
f02985b7 | 817 | { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, |
b199489d HS |
818 | |
819 | /* ST Microelectronics -- newer production may have feature updates */ | |
820 | { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) }, | |
821 | { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) }, | |
822 | { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) }, | |
823 | { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) }, | |
824 | { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) }, | |
825 | { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) }, | |
826 | { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) }, | |
827 | { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) }, | |
828 | { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) }, | |
b199489d HS |
829 | |
830 | { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) }, | |
831 | { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) }, | |
832 | { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) }, | |
833 | { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) }, | |
834 | { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) }, | |
835 | { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) }, | |
836 | { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) }, | |
837 | { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) }, | |
838 | { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) }, | |
839 | ||
840 | { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) }, | |
841 | { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) }, | |
842 | { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) }, | |
843 | ||
844 | { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) }, | |
845 | { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) }, | |
846 | { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) }, | |
847 | ||
848 | { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) }, | |
849 | { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) }, | |
850 | { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) }, | |
851 | { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) }, | |
852 | { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) }, | |
f2fabe16 | 853 | { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) }, |
b199489d HS |
854 | |
855 | /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ | |
40d19ab6 | 856 | { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) }, |
b199489d HS |
857 | { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, |
858 | { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, | |
859 | { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, | |
860 | { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, | |
861 | { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, | |
862 | { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, | |
863 | { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, | |
a23eb341 | 864 | { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
b199489d HS |
865 | { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, |
866 | { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, | |
a23eb341 | 867 | { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
4404bd74 | 868 | { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
b199489d HS |
869 | { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, |
870 | { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, | |
871 | { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, | |
872 | { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) }, | |
873 | ||
874 | /* Catalyst / On Semiconductor -- non-JEDEC */ | |
875 | { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
876 | { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
877 | { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
878 | { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
879 | { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
880 | { }, | |
881 | }; | |
882 | ||
06bb6f5a | 883 | static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) |
b199489d HS |
884 | { |
885 | int tmp; | |
09ffafb6 | 886 | u8 id[SPI_NOR_MAX_ID_LEN]; |
06bb6f5a | 887 | const struct flash_info *info; |
b199489d | 888 | |
09ffafb6 | 889 | tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); |
b199489d | 890 | if (tmp < 0) { |
20625dfe | 891 | dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp); |
b199489d HS |
892 | return ERR_PTR(tmp); |
893 | } | |
b199489d HS |
894 | |
895 | for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) { | |
06bb6f5a | 896 | info = &spi_nor_ids[tmp]; |
09ffafb6 HS |
897 | if (info->id_len) { |
898 | if (!memcmp(info->id, id, info->id_len)) | |
b199489d HS |
899 | return &spi_nor_ids[tmp]; |
900 | } | |
901 | } | |
9b9f1033 | 902 | dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n", |
09ffafb6 | 903 | id[0], id[1], id[2]); |
b199489d HS |
904 | return ERR_PTR(-ENODEV); |
905 | } | |
906 | ||
b199489d HS |
907 | static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, |
908 | size_t *retlen, u_char *buf) | |
909 | { | |
910 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
911 | int ret; | |
912 | ||
913 | dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); | |
914 | ||
915 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ); | |
916 | if (ret) | |
917 | return ret; | |
918 | ||
919 | ret = nor->read(nor, from, len, retlen, buf); | |
920 | ||
921 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ); | |
922 | return ret; | |
923 | } | |
924 | ||
925 | static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, | |
926 | size_t *retlen, const u_char *buf) | |
927 | { | |
928 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
929 | size_t actual; | |
930 | int ret; | |
931 | ||
932 | dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); | |
933 | ||
934 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE); | |
935 | if (ret) | |
936 | return ret; | |
937 | ||
b199489d HS |
938 | write_enable(nor); |
939 | ||
940 | nor->sst_write_second = false; | |
941 | ||
942 | actual = to % 2; | |
943 | /* Start write from odd address. */ | |
944 | if (actual) { | |
b02e7f3e | 945 | nor->program_opcode = SPINOR_OP_BP; |
b199489d HS |
946 | |
947 | /* write one byte. */ | |
948 | nor->write(nor, to, 1, retlen, buf); | |
b94ed087 | 949 | ret = spi_nor_wait_till_ready(nor); |
b199489d HS |
950 | if (ret) |
951 | goto time_out; | |
952 | } | |
953 | to += actual; | |
954 | ||
955 | /* Write out most of the data here. */ | |
956 | for (; actual < len - 1; actual += 2) { | |
b02e7f3e | 957 | nor->program_opcode = SPINOR_OP_AAI_WP; |
b199489d HS |
958 | |
959 | /* write two bytes. */ | |
960 | nor->write(nor, to, 2, retlen, buf + actual); | |
b94ed087 | 961 | ret = spi_nor_wait_till_ready(nor); |
b199489d HS |
962 | if (ret) |
963 | goto time_out; | |
964 | to += 2; | |
965 | nor->sst_write_second = true; | |
966 | } | |
967 | nor->sst_write_second = false; | |
968 | ||
969 | write_disable(nor); | |
b94ed087 | 970 | ret = spi_nor_wait_till_ready(nor); |
b199489d HS |
971 | if (ret) |
972 | goto time_out; | |
973 | ||
974 | /* Write out trailing byte if it exists. */ | |
975 | if (actual != len) { | |
976 | write_enable(nor); | |
977 | ||
b02e7f3e | 978 | nor->program_opcode = SPINOR_OP_BP; |
b199489d HS |
979 | nor->write(nor, to, 1, retlen, buf + actual); |
980 | ||
b94ed087 | 981 | ret = spi_nor_wait_till_ready(nor); |
b199489d HS |
982 | if (ret) |
983 | goto time_out; | |
984 | write_disable(nor); | |
985 | } | |
986 | time_out: | |
987 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE); | |
988 | return ret; | |
989 | } | |
990 | ||
991 | /* | |
992 | * Write an address range to the nor chip. Data must be written in | |
993 | * FLASH_PAGESIZE chunks. The address range may be any size provided | |
994 | * it is within the physical boundaries. | |
995 | */ | |
996 | static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, | |
997 | size_t *retlen, const u_char *buf) | |
998 | { | |
999 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
1000 | u32 page_offset, page_size, i; | |
1001 | int ret; | |
1002 | ||
1003 | dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); | |
1004 | ||
1005 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE); | |
1006 | if (ret) | |
1007 | return ret; | |
1008 | ||
b199489d HS |
1009 | write_enable(nor); |
1010 | ||
1011 | page_offset = to & (nor->page_size - 1); | |
1012 | ||
1013 | /* do all the bytes fit onto one page? */ | |
1014 | if (page_offset + len <= nor->page_size) { | |
1015 | nor->write(nor, to, len, retlen, buf); | |
1016 | } else { | |
1017 | /* the size of data remaining on the first page */ | |
1018 | page_size = nor->page_size - page_offset; | |
1019 | nor->write(nor, to, page_size, retlen, buf); | |
1020 | ||
1021 | /* write everything in nor->page_size chunks */ | |
1022 | for (i = page_size; i < len; i += page_size) { | |
1023 | page_size = len - i; | |
1024 | if (page_size > nor->page_size) | |
1025 | page_size = nor->page_size; | |
1026 | ||
b94ed087 | 1027 | ret = spi_nor_wait_till_ready(nor); |
1d61dcb3 BN |
1028 | if (ret) |
1029 | goto write_err; | |
1030 | ||
b199489d HS |
1031 | write_enable(nor); |
1032 | ||
1033 | nor->write(nor, to + i, page_size, retlen, buf + i); | |
1034 | } | |
1035 | } | |
1036 | ||
dfa9c0cb | 1037 | ret = spi_nor_wait_till_ready(nor); |
b199489d HS |
1038 | write_err: |
1039 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE); | |
1d61dcb3 | 1040 | return ret; |
b199489d HS |
1041 | } |
1042 | ||
1043 | static int macronix_quad_enable(struct spi_nor *nor) | |
1044 | { | |
1045 | int ret, val; | |
1046 | ||
1047 | val = read_sr(nor); | |
f49289ce FE |
1048 | if (val < 0) |
1049 | return val; | |
b199489d HS |
1050 | write_enable(nor); |
1051 | ||
fd725234 | 1052 | write_sr(nor, val | SR_QUAD_EN_MX); |
b199489d | 1053 | |
b94ed087 | 1054 | if (spi_nor_wait_till_ready(nor)) |
b199489d HS |
1055 | return 1; |
1056 | ||
1057 | ret = read_sr(nor); | |
1058 | if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) { | |
1059 | dev_err(nor->dev, "Macronix Quad bit not set\n"); | |
1060 | return -EINVAL; | |
1061 | } | |
1062 | ||
1063 | return 0; | |
1064 | } | |
1065 | ||
1066 | /* | |
1067 | * Write status Register and configuration register with 2 bytes | |
1068 | * The first byte will be written to the status register, while the | |
1069 | * second byte will be written to the configuration register. | |
1070 | * Return negative if error occured. | |
1071 | */ | |
1072 | static int write_sr_cr(struct spi_nor *nor, u16 val) | |
1073 | { | |
1074 | nor->cmd_buf[0] = val & 0xff; | |
1075 | nor->cmd_buf[1] = (val >> 8); | |
1076 | ||
f9f3ce83 | 1077 | return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2); |
b199489d HS |
1078 | } |
1079 | ||
1080 | static int spansion_quad_enable(struct spi_nor *nor) | |
1081 | { | |
1082 | int ret; | |
1083 | int quad_en = CR_QUAD_EN_SPAN << 8; | |
1084 | ||
1085 | write_enable(nor); | |
1086 | ||
1087 | ret = write_sr_cr(nor, quad_en); | |
1088 | if (ret < 0) { | |
1089 | dev_err(nor->dev, | |
1090 | "error while writing configuration register\n"); | |
1091 | return -EINVAL; | |
1092 | } | |
1093 | ||
1094 | /* read back and check it */ | |
1095 | ret = read_cr(nor); | |
1096 | if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) { | |
1097 | dev_err(nor->dev, "Spansion Quad bit not set\n"); | |
1098 | return -EINVAL; | |
1099 | } | |
1100 | ||
1101 | return 0; | |
1102 | } | |
1103 | ||
06bb6f5a | 1104 | static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info) |
b199489d HS |
1105 | { |
1106 | int status; | |
1107 | ||
d928a259 | 1108 | switch (JEDEC_MFR(info)) { |
f0d2448e | 1109 | case SNOR_MFR_MACRONIX: |
b199489d HS |
1110 | status = macronix_quad_enable(nor); |
1111 | if (status) { | |
1112 | dev_err(nor->dev, "Macronix quad-read not enabled\n"); | |
1113 | return -EINVAL; | |
1114 | } | |
1115 | return status; | |
f0d2448e | 1116 | case SNOR_MFR_MICRON: |
3b5394a3 | 1117 | return 0; |
b199489d HS |
1118 | default: |
1119 | status = spansion_quad_enable(nor); | |
1120 | if (status) { | |
1121 | dev_err(nor->dev, "Spansion quad-read not enabled\n"); | |
1122 | return -EINVAL; | |
1123 | } | |
1124 | return status; | |
1125 | } | |
1126 | } | |
1127 | ||
1128 | static int spi_nor_check(struct spi_nor *nor) | |
1129 | { | |
1130 | if (!nor->dev || !nor->read || !nor->write || | |
c67cbb83 | 1131 | !nor->read_reg || !nor->write_reg) { |
b199489d HS |
1132 | pr_err("spi-nor: please fill all the necessary fields!\n"); |
1133 | return -EINVAL; | |
1134 | } | |
1135 | ||
b199489d HS |
1136 | return 0; |
1137 | } | |
1138 | ||
70f3ce05 | 1139 | int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) |
b199489d | 1140 | { |
06bb6f5a | 1141 | const struct flash_info *info = NULL; |
b199489d | 1142 | struct device *dev = nor->dev; |
19763671 | 1143 | struct mtd_info *mtd = &nor->mtd; |
9c7d7875 | 1144 | struct device_node *np = spi_nor_get_flash_node(nor); |
b199489d HS |
1145 | int ret; |
1146 | int i; | |
1147 | ||
1148 | ret = spi_nor_check(nor); | |
1149 | if (ret) | |
1150 | return ret; | |
1151 | ||
43163022 | 1152 | if (name) |
06bb6f5a | 1153 | info = spi_nor_match_id(name); |
43163022 | 1154 | /* Try to auto-detect if chip name wasn't specified or not found */ |
06bb6f5a RM |
1155 | if (!info) |
1156 | info = spi_nor_read_id(nor); | |
1157 | if (IS_ERR_OR_NULL(info)) | |
70f3ce05 BH |
1158 | return -ENOENT; |
1159 | ||
58c81957 RM |
1160 | /* |
1161 | * If caller has specified name of flash model that can normally be | |
1162 | * detected using JEDEC, let's verify it. | |
1163 | */ | |
1164 | if (name && info->id_len) { | |
06bb6f5a | 1165 | const struct flash_info *jinfo; |
b199489d | 1166 | |
06bb6f5a RM |
1167 | jinfo = spi_nor_read_id(nor); |
1168 | if (IS_ERR(jinfo)) { | |
1169 | return PTR_ERR(jinfo); | |
1170 | } else if (jinfo != info) { | |
b199489d HS |
1171 | /* |
1172 | * JEDEC knows better, so overwrite platform ID. We | |
1173 | * can't trust partitions any longer, but we'll let | |
1174 | * mtd apply them anyway, since some partitions may be | |
1175 | * marked read-only, and we don't want to lose that | |
1176 | * information, even if it's not 100% accurate. | |
1177 | */ | |
1178 | dev_warn(dev, "found %s, expected %s\n", | |
06bb6f5a RM |
1179 | jinfo->name, info->name); |
1180 | info = jinfo; | |
b199489d HS |
1181 | } |
1182 | } | |
1183 | ||
1184 | mutex_init(&nor->lock); | |
1185 | ||
1186 | /* | |
c6fc2171 BN |
1187 | * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up |
1188 | * with the software protection bits set | |
b199489d HS |
1189 | */ |
1190 | ||
f0d2448e BN |
1191 | if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || |
1192 | JEDEC_MFR(info) == SNOR_MFR_INTEL || | |
67b9bcd3 | 1193 | JEDEC_MFR(info) == SNOR_MFR_SST) { |
b199489d HS |
1194 | write_enable(nor); |
1195 | write_sr(nor, 0); | |
1196 | } | |
1197 | ||
32f1b7c8 | 1198 | if (!mtd->name) |
b199489d | 1199 | mtd->name = dev_name(dev); |
c9ec3900 | 1200 | mtd->priv = nor; |
b199489d HS |
1201 | mtd->type = MTD_NORFLASH; |
1202 | mtd->writesize = 1; | |
1203 | mtd->flags = MTD_CAP_NORFLASH; | |
1204 | mtd->size = info->sector_size * info->n_sectors; | |
1205 | mtd->_erase = spi_nor_erase; | |
1206 | mtd->_read = spi_nor_read; | |
1207 | ||
357ca38d | 1208 | /* NOR protection support for STmicro/Micron chips and similar */ |
67b9bcd3 | 1209 | if (JEDEC_MFR(info) == SNOR_MFR_MICRON) { |
8cc7f33a BN |
1210 | nor->flash_lock = stm_lock; |
1211 | nor->flash_unlock = stm_unlock; | |
5bf0e69b | 1212 | nor->flash_is_locked = stm_is_locked; |
8cc7f33a BN |
1213 | } |
1214 | ||
5bf0e69b | 1215 | if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) { |
b199489d HS |
1216 | mtd->_lock = spi_nor_lock; |
1217 | mtd->_unlock = spi_nor_unlock; | |
5bf0e69b | 1218 | mtd->_is_locked = spi_nor_is_locked; |
b199489d HS |
1219 | } |
1220 | ||
1221 | /* sst nor chips use AAI word program */ | |
1222 | if (info->flags & SST_WRITE) | |
1223 | mtd->_write = sst_write; | |
1224 | else | |
1225 | mtd->_write = spi_nor_write; | |
1226 | ||
51983b7d BN |
1227 | if (info->flags & USE_FSR) |
1228 | nor->flags |= SNOR_F_USE_FSR; | |
c14dedde | 1229 | |
57cf26c1 | 1230 | #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS |
b199489d HS |
1231 | /* prefer "small sector" erase if possible */ |
1232 | if (info->flags & SECT_4K) { | |
b02e7f3e | 1233 | nor->erase_opcode = SPINOR_OP_BE_4K; |
b199489d HS |
1234 | mtd->erasesize = 4096; |
1235 | } else if (info->flags & SECT_4K_PMC) { | |
b02e7f3e | 1236 | nor->erase_opcode = SPINOR_OP_BE_4K_PMC; |
b199489d | 1237 | mtd->erasesize = 4096; |
57cf26c1 RM |
1238 | } else |
1239 | #endif | |
1240 | { | |
b02e7f3e | 1241 | nor->erase_opcode = SPINOR_OP_SE; |
b199489d HS |
1242 | mtd->erasesize = info->sector_size; |
1243 | } | |
1244 | ||
1245 | if (info->flags & SPI_NOR_NO_ERASE) | |
1246 | mtd->flags |= MTD_NO_ERASE; | |
1247 | ||
1248 | mtd->dev.parent = dev; | |
1249 | nor->page_size = info->page_size; | |
1250 | mtd->writebufsize = nor->page_size; | |
1251 | ||
1252 | if (np) { | |
1253 | /* If we were instantiated by DT, use it */ | |
1254 | if (of_property_read_bool(np, "m25p,fast-read")) | |
1255 | nor->flash_read = SPI_NOR_FAST; | |
1256 | else | |
1257 | nor->flash_read = SPI_NOR_NORMAL; | |
1258 | } else { | |
1259 | /* If we weren't instantiated by DT, default to fast-read */ | |
1260 | nor->flash_read = SPI_NOR_FAST; | |
1261 | } | |
1262 | ||
1263 | /* Some devices cannot do fast-read, no matter what DT tells us */ | |
1264 | if (info->flags & SPI_NOR_NO_FR) | |
1265 | nor->flash_read = SPI_NOR_NORMAL; | |
1266 | ||
1267 | /* Quad/Dual-read mode takes precedence over fast/normal */ | |
1268 | if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) { | |
d928a259 | 1269 | ret = set_quad_mode(nor, info); |
b199489d HS |
1270 | if (ret) { |
1271 | dev_err(dev, "quad mode not supported\n"); | |
1272 | return ret; | |
1273 | } | |
1274 | nor->flash_read = SPI_NOR_QUAD; | |
1275 | } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) { | |
1276 | nor->flash_read = SPI_NOR_DUAL; | |
1277 | } | |
1278 | ||
1279 | /* Default commands */ | |
1280 | switch (nor->flash_read) { | |
1281 | case SPI_NOR_QUAD: | |
58b89a1f | 1282 | nor->read_opcode = SPINOR_OP_READ_1_1_4; |
b199489d HS |
1283 | break; |
1284 | case SPI_NOR_DUAL: | |
58b89a1f | 1285 | nor->read_opcode = SPINOR_OP_READ_1_1_2; |
b199489d HS |
1286 | break; |
1287 | case SPI_NOR_FAST: | |
58b89a1f | 1288 | nor->read_opcode = SPINOR_OP_READ_FAST; |
b199489d HS |
1289 | break; |
1290 | case SPI_NOR_NORMAL: | |
58b89a1f | 1291 | nor->read_opcode = SPINOR_OP_READ; |
b199489d HS |
1292 | break; |
1293 | default: | |
1294 | dev_err(dev, "No Read opcode defined\n"); | |
1295 | return -EINVAL; | |
1296 | } | |
1297 | ||
b02e7f3e | 1298 | nor->program_opcode = SPINOR_OP_PP; |
b199489d HS |
1299 | |
1300 | if (info->addr_width) | |
1301 | nor->addr_width = info->addr_width; | |
1302 | else if (mtd->size > 0x1000000) { | |
1303 | /* enable 4-byte addressing if the device exceeds 16MiB */ | |
1304 | nor->addr_width = 4; | |
f0d2448e | 1305 | if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) { |
b199489d HS |
1306 | /* Dedicated 4-byte command set */ |
1307 | switch (nor->flash_read) { | |
1308 | case SPI_NOR_QUAD: | |
58b89a1f | 1309 | nor->read_opcode = SPINOR_OP_READ4_1_1_4; |
b199489d HS |
1310 | break; |
1311 | case SPI_NOR_DUAL: | |
58b89a1f | 1312 | nor->read_opcode = SPINOR_OP_READ4_1_1_2; |
b199489d HS |
1313 | break; |
1314 | case SPI_NOR_FAST: | |
58b89a1f | 1315 | nor->read_opcode = SPINOR_OP_READ4_FAST; |
b199489d HS |
1316 | break; |
1317 | case SPI_NOR_NORMAL: | |
58b89a1f | 1318 | nor->read_opcode = SPINOR_OP_READ4; |
b199489d HS |
1319 | break; |
1320 | } | |
b02e7f3e | 1321 | nor->program_opcode = SPINOR_OP_PP_4B; |
b199489d | 1322 | /* No small sector erase for 4-byte command set */ |
b02e7f3e | 1323 | nor->erase_opcode = SPINOR_OP_SE_4B; |
b199489d HS |
1324 | mtd->erasesize = info->sector_size; |
1325 | } else | |
d928a259 | 1326 | set_4byte(nor, info, 1); |
b199489d HS |
1327 | } else { |
1328 | nor->addr_width = 3; | |
1329 | } | |
1330 | ||
c67cbb83 BN |
1331 | if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { |
1332 | dev_err(dev, "address width is too large: %u\n", | |
1333 | nor->addr_width); | |
1334 | return -EINVAL; | |
1335 | } | |
1336 | ||
b199489d HS |
1337 | nor->read_dummy = spi_nor_read_dummy_cycles(nor); |
1338 | ||
06bb6f5a | 1339 | dev_info(dev, "%s (%lld Kbytes)\n", info->name, |
b199489d HS |
1340 | (long long)mtd->size >> 10); |
1341 | ||
1342 | dev_dbg(dev, | |
1343 | "mtd .name = %s, .size = 0x%llx (%lldMiB), " | |
1344 | ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", | |
1345 | mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20), | |
1346 | mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions); | |
1347 | ||
1348 | if (mtd->numeraseregions) | |
1349 | for (i = 0; i < mtd->numeraseregions; i++) | |
1350 | dev_dbg(dev, | |
1351 | "mtd.eraseregions[%d] = { .offset = 0x%llx, " | |
1352 | ".erasesize = 0x%.8x (%uKiB), " | |
1353 | ".numblocks = %d }\n", | |
1354 | i, (long long)mtd->eraseregions[i].offset, | |
1355 | mtd->eraseregions[i].erasesize, | |
1356 | mtd->eraseregions[i].erasesize / 1024, | |
1357 | mtd->eraseregions[i].numblocks); | |
1358 | return 0; | |
1359 | } | |
b61834b0 | 1360 | EXPORT_SYMBOL_GPL(spi_nor_scan); |
b199489d | 1361 | |
06bb6f5a | 1362 | static const struct flash_info *spi_nor_match_id(const char *name) |
0d8c11c0 | 1363 | { |
06bb6f5a | 1364 | const struct flash_info *id = spi_nor_ids; |
0d8c11c0 | 1365 | |
2ff46e6f | 1366 | while (id->name) { |
0d8c11c0 HS |
1367 | if (!strcmp(name, id->name)) |
1368 | return id; | |
1369 | id++; | |
1370 | } | |
1371 | return NULL; | |
1372 | } | |
1373 | ||
b199489d HS |
1374 | MODULE_LICENSE("GPL"); |
1375 | MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>"); | |
1376 | MODULE_AUTHOR("Mike Lavender"); | |
1377 | MODULE_DESCRIPTION("framework for SPI NOR"); |