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Commit | Line | Data |
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b199489d | 1 | /* |
8eabdd1e HS |
2 | * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with |
3 | * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c | |
4 | * | |
5 | * Copyright (C) 2005, Intec Automation Inc. | |
6 | * Copyright (C) 2014, Freescale Semiconductor, Inc. | |
b199489d HS |
7 | * |
8 | * This code is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/err.h> | |
14 | #include <linux/errno.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/mutex.h> | |
18 | #include <linux/math64.h> | |
09b6a377 | 19 | #include <linux/sizes.h> |
b199489d | 20 | |
b199489d HS |
21 | #include <linux/mtd/mtd.h> |
22 | #include <linux/of_platform.h> | |
23 | #include <linux/spi/flash.h> | |
24 | #include <linux/mtd/spi-nor.h> | |
25 | ||
26 | /* Define max times to check status register before we give up. */ | |
09b6a377 FS |
27 | |
28 | /* | |
29 | * For everything but full-chip erase; probably could be much smaller, but kept | |
30 | * around for safety for now | |
31 | */ | |
32 | #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) | |
33 | ||
34 | /* | |
35 | * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up | |
36 | * for larger flash | |
37 | */ | |
38 | #define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ) | |
b199489d | 39 | |
d928a259 | 40 | #define SPI_NOR_MAX_ID_LEN 6 |
c67cbb83 | 41 | #define SPI_NOR_MAX_ADDR_WIDTH 4 |
d928a259 HS |
42 | |
43 | struct flash_info { | |
06bb6f5a RM |
44 | char *name; |
45 | ||
d928a259 HS |
46 | /* |
47 | * This array stores the ID bytes. | |
48 | * The first three bytes are the JEDIC ID. | |
49 | * JEDEC ID zero means "no ID" (mostly older chips). | |
50 | */ | |
51 | u8 id[SPI_NOR_MAX_ID_LEN]; | |
52 | u8 id_len; | |
53 | ||
54 | /* The size listed here is what works with SPINOR_OP_SE, which isn't | |
55 | * necessarily called a "sector" by the vendor. | |
56 | */ | |
57 | unsigned sector_size; | |
58 | u16 n_sectors; | |
59 | ||
60 | u16 page_size; | |
61 | u16 addr_width; | |
62 | ||
63 | u16 flags; | |
0618114e BN |
64 | #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */ |
65 | #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */ | |
66 | #define SST_WRITE BIT(2) /* use SST byte programming */ | |
67 | #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */ | |
68 | #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */ | |
69 | #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */ | |
70 | #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */ | |
71 | #define USE_FSR BIT(7) /* use flag status register */ | |
76a4707d | 72 | #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */ |
3dd8012a BN |
73 | #define SPI_NOR_HAS_TB BIT(9) /* |
74 | * Flash SR has Top/Bottom (TB) protect | |
75 | * bit. Must be used with | |
76 | * SPI_NOR_HAS_LOCK. | |
77 | */ | |
e99ca98f RRD |
78 | #define SPI_S3AN BIT(10) /* |
79 | * Xilinx Spartan 3AN In-System Flash | |
80 | * (MFR cannot be used for probing | |
81 | * because it has the same value as | |
82 | * ATMEL flashes) | |
83 | */ | |
ba3ae6a1 CP |
84 | #define SPI_NOR_4B_OPCODES BIT(11) /* |
85 | * Use dedicated 4byte address op codes | |
86 | * to support memory size above 128Mib. | |
87 | */ | |
d928a259 HS |
88 | }; |
89 | ||
90 | #define JEDEC_MFR(info) ((info)->id[0]) | |
b199489d | 91 | |
06bb6f5a | 92 | static const struct flash_info *spi_nor_match_id(const char *name); |
70f3ce05 | 93 | |
b199489d HS |
94 | /* |
95 | * Read the status register, returning its value in the location | |
96 | * Return the status register value. | |
97 | * Returns negative if error occurred. | |
98 | */ | |
99 | static int read_sr(struct spi_nor *nor) | |
100 | { | |
101 | int ret; | |
102 | u8 val; | |
103 | ||
b02e7f3e | 104 | ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1); |
b199489d HS |
105 | if (ret < 0) { |
106 | pr_err("error %d reading SR\n", (int) ret); | |
107 | return ret; | |
108 | } | |
109 | ||
110 | return val; | |
111 | } | |
112 | ||
c14dedde | 113 | /* |
114 | * Read the flag status register, returning its value in the location | |
115 | * Return the status register value. | |
116 | * Returns negative if error occurred. | |
117 | */ | |
118 | static int read_fsr(struct spi_nor *nor) | |
119 | { | |
120 | int ret; | |
121 | u8 val; | |
122 | ||
123 | ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1); | |
124 | if (ret < 0) { | |
125 | pr_err("error %d reading FSR\n", ret); | |
126 | return ret; | |
127 | } | |
128 | ||
129 | return val; | |
130 | } | |
131 | ||
b199489d HS |
132 | /* |
133 | * Read configuration register, returning its value in the | |
134 | * location. Return the configuration register value. | |
135 | * Returns negative if error occured. | |
136 | */ | |
137 | static int read_cr(struct spi_nor *nor) | |
138 | { | |
139 | int ret; | |
140 | u8 val; | |
141 | ||
b02e7f3e | 142 | ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1); |
b199489d HS |
143 | if (ret < 0) { |
144 | dev_err(nor->dev, "error %d reading CR\n", ret); | |
145 | return ret; | |
146 | } | |
147 | ||
148 | return val; | |
149 | } | |
150 | ||
151 | /* | |
152 | * Dummy Cycle calculation for different type of read. | |
153 | * It can be used to support more commands with | |
154 | * different dummy cycle requirements. | |
155 | */ | |
156 | static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor) | |
157 | { | |
158 | switch (nor->flash_read) { | |
159 | case SPI_NOR_FAST: | |
160 | case SPI_NOR_DUAL: | |
161 | case SPI_NOR_QUAD: | |
0b78a2cf | 162 | return 8; |
b199489d HS |
163 | case SPI_NOR_NORMAL: |
164 | return 0; | |
165 | } | |
166 | return 0; | |
167 | } | |
168 | ||
169 | /* | |
170 | * Write status register 1 byte | |
171 | * Returns negative if error occurred. | |
172 | */ | |
173 | static inline int write_sr(struct spi_nor *nor, u8 val) | |
174 | { | |
175 | nor->cmd_buf[0] = val; | |
f9f3ce83 | 176 | return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1); |
b199489d HS |
177 | } |
178 | ||
179 | /* | |
180 | * Set write enable latch with Write Enable command. | |
181 | * Returns negative if error occurred. | |
182 | */ | |
183 | static inline int write_enable(struct spi_nor *nor) | |
184 | { | |
f9f3ce83 | 185 | return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0); |
b199489d HS |
186 | } |
187 | ||
188 | /* | |
189 | * Send write disble instruction to the chip. | |
190 | */ | |
191 | static inline int write_disable(struct spi_nor *nor) | |
192 | { | |
f9f3ce83 | 193 | return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0); |
b199489d HS |
194 | } |
195 | ||
196 | static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) | |
197 | { | |
198 | return mtd->priv; | |
199 | } | |
200 | ||
ba3ae6a1 CP |
201 | |
202 | static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size) | |
203 | { | |
204 | size_t i; | |
205 | ||
206 | for (i = 0; i < size; i++) | |
207 | if (table[i][0] == opcode) | |
208 | return table[i][1]; | |
209 | ||
210 | /* No conversion found, keep input op code. */ | |
211 | return opcode; | |
212 | } | |
213 | ||
214 | static inline u8 spi_nor_convert_3to4_read(u8 opcode) | |
215 | { | |
216 | static const u8 spi_nor_3to4_read[][2] = { | |
217 | { SPINOR_OP_READ, SPINOR_OP_READ_4B }, | |
218 | { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B }, | |
219 | { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B }, | |
220 | { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B }, | |
221 | { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B }, | |
222 | { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B }, | |
223 | }; | |
224 | ||
225 | return spi_nor_convert_opcode(opcode, spi_nor_3to4_read, | |
226 | ARRAY_SIZE(spi_nor_3to4_read)); | |
227 | } | |
228 | ||
229 | static inline u8 spi_nor_convert_3to4_program(u8 opcode) | |
230 | { | |
231 | static const u8 spi_nor_3to4_program[][2] = { | |
232 | { SPINOR_OP_PP, SPINOR_OP_PP_4B }, | |
233 | { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B }, | |
234 | { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B }, | |
235 | }; | |
236 | ||
237 | return spi_nor_convert_opcode(opcode, spi_nor_3to4_program, | |
238 | ARRAY_SIZE(spi_nor_3to4_program)); | |
239 | } | |
240 | ||
241 | static inline u8 spi_nor_convert_3to4_erase(u8 opcode) | |
242 | { | |
243 | static const u8 spi_nor_3to4_erase[][2] = { | |
244 | { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B }, | |
245 | { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B }, | |
246 | { SPINOR_OP_SE, SPINOR_OP_SE_4B }, | |
247 | }; | |
248 | ||
249 | return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase, | |
250 | ARRAY_SIZE(spi_nor_3to4_erase)); | |
251 | } | |
252 | ||
253 | static void spi_nor_set_4byte_opcodes(struct spi_nor *nor, | |
254 | const struct flash_info *info) | |
255 | { | |
256 | /* Do some manufacturer fixups first */ | |
257 | switch (JEDEC_MFR(info)) { | |
258 | case SNOR_MFR_SPANSION: | |
259 | /* No small sector erase for 4-byte command set */ | |
260 | nor->erase_opcode = SPINOR_OP_SE; | |
261 | nor->mtd.erasesize = info->sector_size; | |
262 | break; | |
263 | ||
264 | default: | |
265 | break; | |
266 | } | |
267 | ||
268 | nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode); | |
269 | nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode); | |
270 | nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode); | |
271 | } | |
272 | ||
b199489d | 273 | /* Enable/disable 4-byte addressing mode. */ |
06bb6f5a | 274 | static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info, |
d928a259 | 275 | int enable) |
b199489d HS |
276 | { |
277 | int status; | |
278 | bool need_wren = false; | |
279 | u8 cmd; | |
280 | ||
d928a259 | 281 | switch (JEDEC_MFR(info)) { |
f0d2448e | 282 | case SNOR_MFR_MICRON: |
b199489d HS |
283 | /* Some Micron need WREN command; all will accept it */ |
284 | need_wren = true; | |
f0d2448e BN |
285 | case SNOR_MFR_MACRONIX: |
286 | case SNOR_MFR_WINBOND: | |
b199489d HS |
287 | if (need_wren) |
288 | write_enable(nor); | |
289 | ||
b02e7f3e | 290 | cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; |
f9f3ce83 | 291 | status = nor->write_reg(nor, cmd, NULL, 0); |
b199489d HS |
292 | if (need_wren) |
293 | write_disable(nor); | |
294 | ||
295 | return status; | |
296 | default: | |
297 | /* Spansion style */ | |
298 | nor->cmd_buf[0] = enable << 7; | |
f9f3ce83 | 299 | return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1); |
b199489d HS |
300 | } |
301 | } | |
e99ca98f RRD |
302 | |
303 | static int s3an_sr_ready(struct spi_nor *nor) | |
304 | { | |
305 | int ret; | |
306 | u8 val; | |
307 | ||
308 | ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1); | |
309 | if (ret < 0) { | |
310 | dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret); | |
311 | return ret; | |
312 | } | |
313 | ||
314 | return !!(val & XSR_RDY); | |
315 | } | |
316 | ||
51983b7d | 317 | static inline int spi_nor_sr_ready(struct spi_nor *nor) |
b199489d | 318 | { |
51983b7d BN |
319 | int sr = read_sr(nor); |
320 | if (sr < 0) | |
321 | return sr; | |
322 | else | |
323 | return !(sr & SR_WIP); | |
324 | } | |
b199489d | 325 | |
51983b7d BN |
326 | static inline int spi_nor_fsr_ready(struct spi_nor *nor) |
327 | { | |
328 | int fsr = read_fsr(nor); | |
329 | if (fsr < 0) | |
330 | return fsr; | |
331 | else | |
332 | return fsr & FSR_READY; | |
333 | } | |
b199489d | 334 | |
51983b7d BN |
335 | static int spi_nor_ready(struct spi_nor *nor) |
336 | { | |
337 | int sr, fsr; | |
e99ca98f RRD |
338 | |
339 | if (nor->flags & SNOR_F_READY_XSR_RDY) | |
340 | sr = s3an_sr_ready(nor); | |
341 | else | |
342 | sr = spi_nor_sr_ready(nor); | |
51983b7d BN |
343 | if (sr < 0) |
344 | return sr; | |
345 | fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; | |
346 | if (fsr < 0) | |
347 | return fsr; | |
348 | return sr && fsr; | |
b199489d HS |
349 | } |
350 | ||
b94ed087 BN |
351 | /* |
352 | * Service routine to read status register until ready, or timeout occurs. | |
353 | * Returns non-zero if error. | |
354 | */ | |
09b6a377 FS |
355 | static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, |
356 | unsigned long timeout_jiffies) | |
c14dedde | 357 | { |
358 | unsigned long deadline; | |
a95ce92e | 359 | int timeout = 0, ret; |
c14dedde | 360 | |
09b6a377 | 361 | deadline = jiffies + timeout_jiffies; |
c14dedde | 362 | |
a95ce92e BN |
363 | while (!timeout) { |
364 | if (time_after_eq(jiffies, deadline)) | |
365 | timeout = 1; | |
c14dedde | 366 | |
51983b7d BN |
367 | ret = spi_nor_ready(nor); |
368 | if (ret < 0) | |
369 | return ret; | |
370 | if (ret) | |
371 | return 0; | |
a95ce92e BN |
372 | |
373 | cond_resched(); | |
374 | } | |
375 | ||
376 | dev_err(nor->dev, "flash operation timed out\n"); | |
c14dedde | 377 | |
378 | return -ETIMEDOUT; | |
379 | } | |
380 | ||
09b6a377 FS |
381 | static int spi_nor_wait_till_ready(struct spi_nor *nor) |
382 | { | |
383 | return spi_nor_wait_till_ready_with_timeout(nor, | |
384 | DEFAULT_READY_WAIT_JIFFIES); | |
385 | } | |
386 | ||
b199489d HS |
387 | /* |
388 | * Erase the whole flash memory | |
389 | * | |
390 | * Returns 0 if successful, non-zero otherwise. | |
391 | */ | |
392 | static int erase_chip(struct spi_nor *nor) | |
393 | { | |
19763671 | 394 | dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10)); |
b199489d | 395 | |
f9f3ce83 | 396 | return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0); |
b199489d HS |
397 | } |
398 | ||
399 | static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops) | |
400 | { | |
401 | int ret = 0; | |
402 | ||
403 | mutex_lock(&nor->lock); | |
404 | ||
405 | if (nor->prepare) { | |
406 | ret = nor->prepare(nor, ops); | |
407 | if (ret) { | |
408 | dev_err(nor->dev, "failed in the preparation.\n"); | |
409 | mutex_unlock(&nor->lock); | |
410 | return ret; | |
411 | } | |
412 | } | |
413 | return ret; | |
414 | } | |
415 | ||
416 | static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops) | |
417 | { | |
418 | if (nor->unprepare) | |
419 | nor->unprepare(nor, ops); | |
420 | mutex_unlock(&nor->lock); | |
421 | } | |
422 | ||
e99ca98f RRD |
423 | /* |
424 | * This code converts an address to the Default Address Mode, that has non | |
425 | * power of two page sizes. We must support this mode because it is the default | |
426 | * mode supported by Xilinx tools, it can access the whole flash area and | |
427 | * changing over to the Power-of-two mode is irreversible and corrupts the | |
428 | * original data. | |
429 | * Addr can safely be unsigned int, the biggest S3AN device is smaller than | |
430 | * 4 MiB. | |
431 | */ | |
432 | static loff_t spi_nor_s3an_addr_convert(struct spi_nor *nor, unsigned int addr) | |
433 | { | |
434 | unsigned int offset = addr; | |
435 | ||
436 | offset %= nor->page_size; | |
437 | ||
438 | return ((addr - offset) << 1) | offset; | |
439 | } | |
440 | ||
c67cbb83 BN |
441 | /* |
442 | * Initiate the erasure of a single sector | |
443 | */ | |
444 | static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) | |
445 | { | |
446 | u8 buf[SPI_NOR_MAX_ADDR_WIDTH]; | |
447 | int i; | |
448 | ||
e99ca98f RRD |
449 | if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT) |
450 | addr = spi_nor_s3an_addr_convert(nor, addr); | |
451 | ||
c67cbb83 BN |
452 | if (nor->erase) |
453 | return nor->erase(nor, addr); | |
454 | ||
455 | /* | |
456 | * Default implementation, if driver doesn't have a specialized HW | |
457 | * control | |
458 | */ | |
459 | for (i = nor->addr_width - 1; i >= 0; i--) { | |
460 | buf[i] = addr & 0xff; | |
461 | addr >>= 8; | |
462 | } | |
463 | ||
464 | return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width); | |
465 | } | |
466 | ||
b199489d HS |
467 | /* |
468 | * Erase an address range on the nor chip. The address range may extend | |
469 | * one or more erase sectors. Return an error is there is a problem erasing. | |
470 | */ | |
471 | static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) | |
472 | { | |
473 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
474 | u32 addr, len; | |
475 | uint32_t rem; | |
476 | int ret; | |
477 | ||
478 | dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, | |
479 | (long long)instr->len); | |
480 | ||
481 | div_u64_rem(instr->len, mtd->erasesize, &rem); | |
482 | if (rem) | |
483 | return -EINVAL; | |
484 | ||
485 | addr = instr->addr; | |
486 | len = instr->len; | |
487 | ||
488 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE); | |
489 | if (ret) | |
490 | return ret; | |
491 | ||
492 | /* whole-chip erase? */ | |
e99ca98f | 493 | if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { |
09b6a377 FS |
494 | unsigned long timeout; |
495 | ||
05241aea BN |
496 | write_enable(nor); |
497 | ||
b199489d HS |
498 | if (erase_chip(nor)) { |
499 | ret = -EIO; | |
500 | goto erase_err; | |
501 | } | |
502 | ||
09b6a377 FS |
503 | /* |
504 | * Scale the timeout linearly with the size of the flash, with | |
505 | * a minimum calibrated to an old 2MB flash. We could try to | |
506 | * pull these from CFI/SFDP, but these values should be good | |
507 | * enough for now. | |
508 | */ | |
509 | timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, | |
510 | CHIP_ERASE_2MB_READY_WAIT_JIFFIES * | |
511 | (unsigned long)(mtd->size / SZ_2M)); | |
512 | ret = spi_nor_wait_till_ready_with_timeout(nor, timeout); | |
dfa9c0cb BN |
513 | if (ret) |
514 | goto erase_err; | |
515 | ||
b199489d | 516 | /* REVISIT in some cases we could speed up erasing large regions |
b02e7f3e | 517 | * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up |
b199489d HS |
518 | * to use "small sector erase", but that's not always optimal. |
519 | */ | |
520 | ||
521 | /* "sector"-at-a-time erase */ | |
522 | } else { | |
523 | while (len) { | |
05241aea BN |
524 | write_enable(nor); |
525 | ||
c67cbb83 BN |
526 | ret = spi_nor_erase_sector(nor, addr); |
527 | if (ret) | |
b199489d | 528 | goto erase_err; |
b199489d HS |
529 | |
530 | addr += mtd->erasesize; | |
531 | len -= mtd->erasesize; | |
dfa9c0cb BN |
532 | |
533 | ret = spi_nor_wait_till_ready(nor); | |
534 | if (ret) | |
535 | goto erase_err; | |
b199489d HS |
536 | } |
537 | } | |
538 | ||
05241aea BN |
539 | write_disable(nor); |
540 | ||
d6af2694 | 541 | erase_err: |
b199489d HS |
542 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE); |
543 | ||
d6af2694 | 544 | instr->state = ret ? MTD_ERASE_FAILED : MTD_ERASE_DONE; |
b199489d HS |
545 | mtd_erase_callback(instr); |
546 | ||
547 | return ret; | |
b199489d HS |
548 | } |
549 | ||
62593cf4 BN |
550 | static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs, |
551 | uint64_t *len) | |
552 | { | |
553 | struct mtd_info *mtd = &nor->mtd; | |
554 | u8 mask = SR_BP2 | SR_BP1 | SR_BP0; | |
555 | int shift = ffs(mask) - 1; | |
556 | int pow; | |
557 | ||
558 | if (!(sr & mask)) { | |
559 | /* No protection */ | |
560 | *ofs = 0; | |
561 | *len = 0; | |
562 | } else { | |
563 | pow = ((sr & mask) ^ mask) >> shift; | |
564 | *len = mtd->size >> pow; | |
3dd8012a BN |
565 | if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB) |
566 | *ofs = 0; | |
567 | else | |
568 | *ofs = mtd->size - *len; | |
62593cf4 BN |
569 | } |
570 | } | |
571 | ||
572 | /* | |
f8860802 BN |
573 | * Return 1 if the entire region is locked (if @locked is true) or unlocked (if |
574 | * @locked is false); 0 otherwise | |
62593cf4 | 575 | */ |
f8860802 BN |
576 | static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, |
577 | u8 sr, bool locked) | |
62593cf4 BN |
578 | { |
579 | loff_t lock_offs; | |
580 | uint64_t lock_len; | |
581 | ||
f8860802 BN |
582 | if (!len) |
583 | return 1; | |
584 | ||
62593cf4 BN |
585 | stm_get_locked_range(nor, sr, &lock_offs, &lock_len); |
586 | ||
f8860802 BN |
587 | if (locked) |
588 | /* Requested range is a sub-range of locked range */ | |
589 | return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); | |
590 | else | |
591 | /* Requested range does not overlap with locked range */ | |
592 | return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs); | |
593 | } | |
594 | ||
595 | static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, | |
596 | u8 sr) | |
597 | { | |
598 | return stm_check_lock_status_sr(nor, ofs, len, sr, true); | |
599 | } | |
600 | ||
601 | static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, | |
602 | u8 sr) | |
603 | { | |
604 | return stm_check_lock_status_sr(nor, ofs, len, sr, false); | |
62593cf4 BN |
605 | } |
606 | ||
607 | /* | |
608 | * Lock a region of the flash. Compatible with ST Micro and similar flash. | |
3dd8012a | 609 | * Supports the block protection bits BP{0,1,2} in the status register |
62593cf4 | 610 | * (SR). Does not support these features found in newer SR bitfields: |
62593cf4 BN |
611 | * - SEC: sector/block protect - only handle SEC=0 (block protect) |
612 | * - CMP: complement protect - only support CMP=0 (range is not complemented) | |
613 | * | |
3dd8012a BN |
614 | * Support for the following is provided conditionally for some flash: |
615 | * - TB: top/bottom protect | |
616 | * | |
62593cf4 BN |
617 | * Sample table portion for 8MB flash (Winbond w25q64fw): |
618 | * | |
619 | * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion | |
620 | * -------------------------------------------------------------------------- | |
621 | * X | X | 0 | 0 | 0 | NONE | NONE | |
622 | * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 | |
623 | * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 | |
624 | * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 | |
625 | * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 | |
626 | * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 | |
627 | * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 | |
628 | * X | X | 1 | 1 | 1 | 8 MB | ALL | |
3dd8012a BN |
629 | * ------|-------|-------|-------|-------|---------------|------------------- |
630 | * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64 | |
631 | * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32 | |
632 | * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16 | |
633 | * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8 | |
634 | * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4 | |
635 | * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2 | |
62593cf4 BN |
636 | * |
637 | * Returns negative on errors, 0 on success. | |
638 | */ | |
8cc7f33a | 639 | static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) |
b199489d | 640 | { |
19763671 | 641 | struct mtd_info *mtd = &nor->mtd; |
f49289ce | 642 | int status_old, status_new; |
62593cf4 BN |
643 | u8 mask = SR_BP2 | SR_BP1 | SR_BP0; |
644 | u8 shift = ffs(mask) - 1, pow, val; | |
f8860802 | 645 | loff_t lock_len; |
3dd8012a BN |
646 | bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; |
647 | bool use_top; | |
32321e95 | 648 | int ret; |
b199489d | 649 | |
b199489d | 650 | status_old = read_sr(nor); |
f49289ce FE |
651 | if (status_old < 0) |
652 | return status_old; | |
b199489d | 653 | |
f8860802 BN |
654 | /* If nothing in our range is unlocked, we don't need to do anything */ |
655 | if (stm_is_locked_sr(nor, ofs, len, status_old)) | |
656 | return 0; | |
657 | ||
3dd8012a BN |
658 | /* If anything below us is unlocked, we can't use 'bottom' protection */ |
659 | if (!stm_is_locked_sr(nor, 0, ofs, status_old)) | |
660 | can_be_bottom = false; | |
661 | ||
f8860802 BN |
662 | /* If anything above us is unlocked, we can't use 'top' protection */ |
663 | if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len), | |
664 | status_old)) | |
3dd8012a BN |
665 | can_be_top = false; |
666 | ||
667 | if (!can_be_bottom && !can_be_top) | |
f8860802 BN |
668 | return -EINVAL; |
669 | ||
3dd8012a BN |
670 | /* Prefer top, if both are valid */ |
671 | use_top = can_be_top; | |
672 | ||
f8860802 | 673 | /* lock_len: length of region that should end up locked */ |
3dd8012a BN |
674 | if (use_top) |
675 | lock_len = mtd->size - ofs; | |
676 | else | |
677 | lock_len = ofs + len; | |
62593cf4 BN |
678 | |
679 | /* | |
680 | * Need smallest pow such that: | |
681 | * | |
682 | * 1 / (2^pow) <= (len / size) | |
683 | * | |
684 | * so (assuming power-of-2 size) we do: | |
685 | * | |
686 | * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) | |
687 | */ | |
f8860802 | 688 | pow = ilog2(mtd->size) - ilog2(lock_len); |
62593cf4 BN |
689 | val = mask - (pow << shift); |
690 | if (val & ~mask) | |
691 | return -EINVAL; | |
692 | /* Don't "lock" with no region! */ | |
693 | if (!(val & mask)) | |
694 | return -EINVAL; | |
695 | ||
3dd8012a | 696 | status_new = (status_old & ~mask & ~SR_TB) | val; |
b199489d | 697 | |
47b8edbf BN |
698 | /* Disallow further writes if WP pin is asserted */ |
699 | status_new |= SR_SRWD; | |
700 | ||
3dd8012a BN |
701 | if (!use_top) |
702 | status_new |= SR_TB; | |
703 | ||
4c0dba44 BN |
704 | /* Don't bother if they're the same */ |
705 | if (status_new == status_old) | |
706 | return 0; | |
707 | ||
b199489d | 708 | /* Only modify protection if it will not unlock other areas */ |
4c0dba44 | 709 | if ((status_new & mask) < (status_old & mask)) |
62593cf4 | 710 | return -EINVAL; |
b199489d | 711 | |
62593cf4 | 712 | write_enable(nor); |
32321e95 EG |
713 | ret = write_sr(nor, status_new); |
714 | if (ret) | |
715 | return ret; | |
716 | return spi_nor_wait_till_ready(nor); | |
b199489d HS |
717 | } |
718 | ||
62593cf4 BN |
719 | /* |
720 | * Unlock a region of the flash. See stm_lock() for more info | |
721 | * | |
722 | * Returns negative on errors, 0 on success. | |
723 | */ | |
8cc7f33a | 724 | static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) |
b199489d | 725 | { |
19763671 | 726 | struct mtd_info *mtd = &nor->mtd; |
f49289ce | 727 | int status_old, status_new; |
62593cf4 BN |
728 | u8 mask = SR_BP2 | SR_BP1 | SR_BP0; |
729 | u8 shift = ffs(mask) - 1, pow, val; | |
f8860802 | 730 | loff_t lock_len; |
3dd8012a BN |
731 | bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; |
732 | bool use_top; | |
32321e95 | 733 | int ret; |
b199489d | 734 | |
b199489d | 735 | status_old = read_sr(nor); |
f49289ce FE |
736 | if (status_old < 0) |
737 | return status_old; | |
b199489d | 738 | |
f8860802 BN |
739 | /* If nothing in our range is locked, we don't need to do anything */ |
740 | if (stm_is_unlocked_sr(nor, ofs, len, status_old)) | |
741 | return 0; | |
742 | ||
743 | /* If anything below us is locked, we can't use 'top' protection */ | |
744 | if (!stm_is_unlocked_sr(nor, 0, ofs, status_old)) | |
3dd8012a BN |
745 | can_be_top = false; |
746 | ||
747 | /* If anything above us is locked, we can't use 'bottom' protection */ | |
748 | if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len), | |
749 | status_old)) | |
750 | can_be_bottom = false; | |
751 | ||
752 | if (!can_be_bottom && !can_be_top) | |
62593cf4 | 753 | return -EINVAL; |
b199489d | 754 | |
3dd8012a BN |
755 | /* Prefer top, if both are valid */ |
756 | use_top = can_be_top; | |
757 | ||
f8860802 | 758 | /* lock_len: length of region that should remain locked */ |
3dd8012a BN |
759 | if (use_top) |
760 | lock_len = mtd->size - (ofs + len); | |
761 | else | |
762 | lock_len = ofs; | |
f8860802 | 763 | |
62593cf4 BN |
764 | /* |
765 | * Need largest pow such that: | |
766 | * | |
767 | * 1 / (2^pow) >= (len / size) | |
768 | * | |
769 | * so (assuming power-of-2 size) we do: | |
770 | * | |
771 | * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) | |
772 | */ | |
f8860802 BN |
773 | pow = ilog2(mtd->size) - order_base_2(lock_len); |
774 | if (lock_len == 0) { | |
62593cf4 BN |
775 | val = 0; /* fully unlocked */ |
776 | } else { | |
777 | val = mask - (pow << shift); | |
778 | /* Some power-of-two sizes are not supported */ | |
779 | if (val & ~mask) | |
780 | return -EINVAL; | |
b199489d HS |
781 | } |
782 | ||
3dd8012a | 783 | status_new = (status_old & ~mask & ~SR_TB) | val; |
62593cf4 | 784 | |
47b8edbf | 785 | /* Don't protect status register if we're fully unlocked */ |
06586204 | 786 | if (lock_len == 0) |
47b8edbf BN |
787 | status_new &= ~SR_SRWD; |
788 | ||
3dd8012a BN |
789 | if (!use_top) |
790 | status_new |= SR_TB; | |
791 | ||
4c0dba44 BN |
792 | /* Don't bother if they're the same */ |
793 | if (status_new == status_old) | |
794 | return 0; | |
795 | ||
62593cf4 | 796 | /* Only modify protection if it will not lock other areas */ |
4c0dba44 | 797 | if ((status_new & mask) > (status_old & mask)) |
62593cf4 BN |
798 | return -EINVAL; |
799 | ||
800 | write_enable(nor); | |
32321e95 EG |
801 | ret = write_sr(nor, status_new); |
802 | if (ret) | |
803 | return ret; | |
804 | return spi_nor_wait_till_ready(nor); | |
8cc7f33a BN |
805 | } |
806 | ||
5bf0e69b BN |
807 | /* |
808 | * Check if a region of the flash is (completely) locked. See stm_lock() for | |
809 | * more info. | |
810 | * | |
811 | * Returns 1 if entire region is locked, 0 if any portion is unlocked, and | |
812 | * negative on errors. | |
813 | */ | |
814 | static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) | |
815 | { | |
816 | int status; | |
817 | ||
818 | status = read_sr(nor); | |
819 | if (status < 0) | |
820 | return status; | |
821 | ||
822 | return stm_is_locked_sr(nor, ofs, len, status); | |
823 | } | |
824 | ||
8cc7f33a BN |
825 | static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
826 | { | |
827 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
828 | int ret; | |
829 | ||
830 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK); | |
831 | if (ret) | |
832 | return ret; | |
833 | ||
834 | ret = nor->flash_lock(nor, ofs, len); | |
835 | ||
b199489d HS |
836 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK); |
837 | return ret; | |
838 | } | |
839 | ||
8cc7f33a BN |
840 | static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
841 | { | |
842 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
843 | int ret; | |
844 | ||
845 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK); | |
846 | if (ret) | |
847 | return ret; | |
848 | ||
849 | ret = nor->flash_unlock(nor, ofs, len); | |
850 | ||
851 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK); | |
852 | return ret; | |
853 | } | |
854 | ||
5bf0e69b BN |
855 | static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) |
856 | { | |
857 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
858 | int ret; | |
859 | ||
860 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK); | |
861 | if (ret) | |
862 | return ret; | |
863 | ||
864 | ret = nor->flash_is_locked(nor, ofs, len); | |
865 | ||
866 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK); | |
867 | return ret; | |
868 | } | |
869 | ||
09ffafb6 | 870 | /* Used when the "_ext_id" is two bytes at most */ |
b199489d | 871 | #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
09ffafb6 HS |
872 | .id = { \ |
873 | ((_jedec_id) >> 16) & 0xff, \ | |
874 | ((_jedec_id) >> 8) & 0xff, \ | |
875 | (_jedec_id) & 0xff, \ | |
876 | ((_ext_id) >> 8) & 0xff, \ | |
877 | (_ext_id) & 0xff, \ | |
878 | }, \ | |
879 | .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ | |
b199489d HS |
880 | .sector_size = (_sector_size), \ |
881 | .n_sectors = (_n_sectors), \ | |
882 | .page_size = 256, \ | |
06bb6f5a | 883 | .flags = (_flags), |
b199489d | 884 | |
6d7604e5 | 885 | #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
6d7604e5 HS |
886 | .id = { \ |
887 | ((_jedec_id) >> 16) & 0xff, \ | |
888 | ((_jedec_id) >> 8) & 0xff, \ | |
889 | (_jedec_id) & 0xff, \ | |
890 | ((_ext_id) >> 16) & 0xff, \ | |
891 | ((_ext_id) >> 8) & 0xff, \ | |
892 | (_ext_id) & 0xff, \ | |
893 | }, \ | |
894 | .id_len = 6, \ | |
895 | .sector_size = (_sector_size), \ | |
896 | .n_sectors = (_n_sectors), \ | |
897 | .page_size = 256, \ | |
06bb6f5a | 898 | .flags = (_flags), |
6d7604e5 | 899 | |
b199489d | 900 | #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \ |
b199489d HS |
901 | .sector_size = (_sector_size), \ |
902 | .n_sectors = (_n_sectors), \ | |
903 | .page_size = (_page_size), \ | |
904 | .addr_width = (_addr_width), \ | |
06bb6f5a | 905 | .flags = (_flags), |
b199489d | 906 | |
e99ca98f RRD |
907 | #define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \ |
908 | .id = { \ | |
909 | ((_jedec_id) >> 16) & 0xff, \ | |
910 | ((_jedec_id) >> 8) & 0xff, \ | |
911 | (_jedec_id) & 0xff \ | |
912 | }, \ | |
913 | .id_len = 3, \ | |
914 | .sector_size = (8*_page_size), \ | |
915 | .n_sectors = (_n_sectors), \ | |
916 | .page_size = _page_size, \ | |
917 | .addr_width = 3, \ | |
918 | .flags = SPI_NOR_NO_FR | SPI_S3AN, | |
919 | ||
b199489d HS |
920 | /* NOTE: double check command sets and memory organization when you add |
921 | * more nor chips. This current list focusses on newer chips, which | |
922 | * have been converging on command sets which including JEDEC ID. | |
c19900ed RM |
923 | * |
924 | * All newly added entries should describe *hardware* and should use SECT_4K | |
925 | * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage | |
926 | * scenarios excluding small sectors there is config option that can be | |
927 | * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS. | |
928 | * For historical (and compatibility) reasons (before we got above config) some | |
929 | * old entries may be missing 4K flag. | |
b199489d | 930 | */ |
06bb6f5a | 931 | static const struct flash_info spi_nor_ids[] = { |
b199489d HS |
932 | /* Atmel -- some are (confusingly) marketed as "DataFlash" */ |
933 | { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) }, | |
934 | { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) }, | |
935 | ||
936 | { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) }, | |
b08618c9 | 937 | { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, |
b199489d HS |
938 | { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, |
939 | { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) }, | |
940 | ||
941 | { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) }, | |
942 | { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, | |
943 | { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) }, | |
944 | { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, | |
945 | ||
946 | { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, | |
947 | ||
948 | /* EON -- en25xxx */ | |
949 | { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, | |
950 | { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, | |
951 | { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) }, | |
952 | { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) }, | |
953 | { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, | |
a41595b3 | 954 | { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) }, |
b199489d | 955 | { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) }, |
c19900ed | 956 | { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, |
b199489d HS |
957 | |
958 | /* ESMT */ | |
959 | { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) }, | |
960 | ||
961 | /* Everspin */ | |
962 | { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
963 | { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
edd0c8f4 | 964 | { "mr25h40", CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, |
b199489d | 965 | |
ce56ce7d RL |
966 | /* Fujitsu */ |
967 | { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) }, | |
968 | ||
b199489d | 969 | /* GigaDevice */ |
595f0e10 BN |
970 | { |
971 | "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, | |
972 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | | |
973 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) | |
974 | }, | |
975 | { | |
976 | "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, | |
977 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | | |
978 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) | |
979 | }, | |
980 | { | |
981 | "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128, | |
982 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | | |
983 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) | |
984 | }, | |
985 | { | |
986 | "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, | |
987 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | | |
988 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) | |
989 | }, | |
b199489d HS |
990 | |
991 | /* Intel/Numonyx -- xxxs33b */ | |
992 | { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) }, | |
993 | { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, | |
994 | { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, | |
995 | ||
b79c332f GJ |
996 | /* ISSI */ |
997 | { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) }, | |
998 | ||
b199489d | 999 | /* Macronix */ |
660b5b07 | 1000 | { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) }, |
b199489d HS |
1001 | { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, |
1002 | { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, | |
1003 | { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, | |
1004 | { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, | |
0501f2e5 | 1005 | { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) }, |
b199489d | 1006 | { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) }, |
0501f2e5 | 1007 | { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) }, |
81a1209c | 1008 | { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) }, |
b199489d HS |
1009 | { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, |
1010 | { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, | |
1011 | { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) }, | |
355445b8 | 1012 | { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K) }, |
b199489d HS |
1013 | { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, |
1014 | { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) }, | |
1015 | { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) }, | |
1016 | ||
1017 | /* Micron */ | |
61e46118 | 1018 | { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) }, |
548cd3ab | 1019 | { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, |
f9bcb6dc | 1020 | { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, |
0db7fae2 | 1021 | { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, |
2a06c7b1 | 1022 | { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, |
4607777c EG |
1023 | { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, |
1024 | { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, | |
548cd3ab BH |
1025 | { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, |
1026 | { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, | |
1027 | { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, | |
1028 | { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, | |
cebc1fd0 | 1029 | { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, |
b199489d HS |
1030 | |
1031 | /* PMC */ | |
1032 | { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) }, | |
1033 | { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) }, | |
1034 | { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) }, | |
1035 | ||
1036 | /* Spansion -- single (large) sector size only, at least | |
1037 | * for the chips listed here (without boot sectors). | |
1038 | */ | |
9ab86995 | 1039 | { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
0f12a27b | 1040 | { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
b199489d HS |
1041 | { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) }, |
1042 | { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
1043 | { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
1044 | { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, | |
1045 | { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, | |
1046 | { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, | |
4287916d | 1047 | { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
c1752086 JG |
1048 | { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
1049 | { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
b199489d HS |
1050 | { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, |
1051 | { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, | |
1052 | { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, | |
1053 | { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, | |
1054 | { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, | |
7c748f57 | 1055 | { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
adf508c3 JE |
1056 | { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
1057 | { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, | |
b199489d | 1058 | { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, |
c0826679 | 1059 | { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
c19900ed | 1060 | { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) }, |
413780d7 | 1061 | { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) }, |
aada20cd | 1062 | { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) }, |
022a400f | 1063 | { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) }, |
b199489d HS |
1064 | |
1065 | /* SST -- large erase sizes are "overlays", "sectors" are 4K */ | |
1066 | { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, | |
1067 | { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, | |
1068 | { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, | |
1069 | { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, | |
1070 | { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, | |
1071 | { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, | |
1072 | { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, | |
1073 | { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, | |
a1d97ef9 | 1074 | { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) }, |
c887be71 | 1075 | { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) }, |
b199489d | 1076 | { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, |
f02985b7 | 1077 | { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, |
b199489d HS |
1078 | |
1079 | /* ST Microelectronics -- newer production may have feature updates */ | |
1080 | { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) }, | |
1081 | { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) }, | |
1082 | { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) }, | |
1083 | { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) }, | |
1084 | { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) }, | |
1085 | { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) }, | |
1086 | { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) }, | |
1087 | { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) }, | |
1088 | { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) }, | |
b199489d HS |
1089 | |
1090 | { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) }, | |
1091 | { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) }, | |
1092 | { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) }, | |
1093 | { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) }, | |
1094 | { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) }, | |
1095 | { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) }, | |
1096 | { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) }, | |
1097 | { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) }, | |
1098 | { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) }, | |
1099 | ||
1100 | { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) }, | |
1101 | { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) }, | |
1102 | { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) }, | |
1103 | ||
1104 | { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) }, | |
1105 | { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) }, | |
1106 | { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) }, | |
1107 | ||
1108 | { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) }, | |
1109 | { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) }, | |
1110 | { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) }, | |
1111 | { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) }, | |
1112 | { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) }, | |
f2fabe16 | 1113 | { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) }, |
b199489d HS |
1114 | |
1115 | /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ | |
40d19ab6 | 1116 | { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) }, |
b199489d HS |
1117 | { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, |
1118 | { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, | |
1119 | { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, | |
1120 | { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, | |
1121 | { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, | |
1122 | { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, | |
1123 | { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, | |
9648388f BN |
1124 | { |
1125 | "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, | |
1126 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | | |
1127 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) | |
1128 | }, | |
b199489d HS |
1129 | { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, |
1130 | { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, | |
9648388f BN |
1131 | { |
1132 | "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, | |
1133 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | | |
1134 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) | |
1135 | }, | |
1136 | { | |
1137 | "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, | |
1138 | SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | | |
1139 | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) | |
1140 | }, | |
b199489d HS |
1141 | { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, |
1142 | { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, | |
1143 | { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, | |
1144 | { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) }, | |
1145 | ||
1146 | /* Catalyst / On Semiconductor -- non-JEDEC */ | |
1147 | { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
1148 | { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
1149 | { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
1150 | { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
1151 | { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) }, | |
e99ca98f RRD |
1152 | |
1153 | /* Xilinx S3AN Internal Flash */ | |
1154 | { "3S50AN", S3AN_INFO(0x1f2200, 64, 264) }, | |
1155 | { "3S200AN", S3AN_INFO(0x1f2400, 256, 264) }, | |
1156 | { "3S400AN", S3AN_INFO(0x1f2400, 256, 264) }, | |
1157 | { "3S700AN", S3AN_INFO(0x1f2500, 512, 264) }, | |
1158 | { "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) }, | |
b199489d HS |
1159 | { }, |
1160 | }; | |
1161 | ||
06bb6f5a | 1162 | static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) |
b199489d HS |
1163 | { |
1164 | int tmp; | |
09ffafb6 | 1165 | u8 id[SPI_NOR_MAX_ID_LEN]; |
06bb6f5a | 1166 | const struct flash_info *info; |
b199489d | 1167 | |
09ffafb6 | 1168 | tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); |
b199489d | 1169 | if (tmp < 0) { |
20625dfe | 1170 | dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp); |
b199489d HS |
1171 | return ERR_PTR(tmp); |
1172 | } | |
b199489d HS |
1173 | |
1174 | for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) { | |
06bb6f5a | 1175 | info = &spi_nor_ids[tmp]; |
09ffafb6 HS |
1176 | if (info->id_len) { |
1177 | if (!memcmp(info->id, id, info->id_len)) | |
b199489d HS |
1178 | return &spi_nor_ids[tmp]; |
1179 | } | |
1180 | } | |
9b9f1033 | 1181 | dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n", |
09ffafb6 | 1182 | id[0], id[1], id[2]); |
b199489d HS |
1183 | return ERR_PTR(-ENODEV); |
1184 | } | |
1185 | ||
b199489d HS |
1186 | static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, |
1187 | size_t *retlen, u_char *buf) | |
1188 | { | |
1189 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
1190 | int ret; | |
1191 | ||
1192 | dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); | |
1193 | ||
1194 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ); | |
1195 | if (ret) | |
1196 | return ret; | |
1197 | ||
26f9bcad | 1198 | while (len) { |
e99ca98f RRD |
1199 | loff_t addr = from; |
1200 | ||
1201 | if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT) | |
1202 | addr = spi_nor_s3an_addr_convert(nor, addr); | |
1203 | ||
1204 | ret = nor->read(nor, addr, len, buf); | |
26f9bcad MS |
1205 | if (ret == 0) { |
1206 | /* We shouldn't see 0-length reads */ | |
1207 | ret = -EIO; | |
1208 | goto read_err; | |
1209 | } | |
1210 | if (ret < 0) | |
1211 | goto read_err; | |
b199489d | 1212 | |
26f9bcad MS |
1213 | WARN_ON(ret > len); |
1214 | *retlen += ret; | |
1215 | buf += ret; | |
1216 | from += ret; | |
1217 | len -= ret; | |
1218 | } | |
1219 | ret = 0; | |
59451e12 | 1220 | |
26f9bcad MS |
1221 | read_err: |
1222 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ); | |
1223 | return ret; | |
b199489d HS |
1224 | } |
1225 | ||
1226 | static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, | |
1227 | size_t *retlen, const u_char *buf) | |
1228 | { | |
1229 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
1230 | size_t actual; | |
1231 | int ret; | |
1232 | ||
1233 | dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); | |
1234 | ||
1235 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE); | |
1236 | if (ret) | |
1237 | return ret; | |
1238 | ||
b199489d HS |
1239 | write_enable(nor); |
1240 | ||
1241 | nor->sst_write_second = false; | |
1242 | ||
1243 | actual = to % 2; | |
1244 | /* Start write from odd address. */ | |
1245 | if (actual) { | |
b02e7f3e | 1246 | nor->program_opcode = SPINOR_OP_BP; |
b199489d HS |
1247 | |
1248 | /* write one byte. */ | |
2dd087b1 | 1249 | ret = nor->write(nor, to, 1, buf); |
0bad7b93 MS |
1250 | if (ret < 0) |
1251 | goto sst_write_err; | |
1252 | WARN(ret != 1, "While writing 1 byte written %i bytes\n", | |
1253 | (int)ret); | |
b94ed087 | 1254 | ret = spi_nor_wait_till_ready(nor); |
b199489d | 1255 | if (ret) |
0bad7b93 | 1256 | goto sst_write_err; |
b199489d HS |
1257 | } |
1258 | to += actual; | |
1259 | ||
1260 | /* Write out most of the data here. */ | |
1261 | for (; actual < len - 1; actual += 2) { | |
b02e7f3e | 1262 | nor->program_opcode = SPINOR_OP_AAI_WP; |
b199489d HS |
1263 | |
1264 | /* write two bytes. */ | |
2dd087b1 | 1265 | ret = nor->write(nor, to, 2, buf + actual); |
0bad7b93 MS |
1266 | if (ret < 0) |
1267 | goto sst_write_err; | |
1268 | WARN(ret != 2, "While writing 2 bytes written %i bytes\n", | |
1269 | (int)ret); | |
b94ed087 | 1270 | ret = spi_nor_wait_till_ready(nor); |
b199489d | 1271 | if (ret) |
0bad7b93 | 1272 | goto sst_write_err; |
b199489d HS |
1273 | to += 2; |
1274 | nor->sst_write_second = true; | |
1275 | } | |
1276 | nor->sst_write_second = false; | |
1277 | ||
1278 | write_disable(nor); | |
b94ed087 | 1279 | ret = spi_nor_wait_till_ready(nor); |
b199489d | 1280 | if (ret) |
0bad7b93 | 1281 | goto sst_write_err; |
b199489d HS |
1282 | |
1283 | /* Write out trailing byte if it exists. */ | |
1284 | if (actual != len) { | |
1285 | write_enable(nor); | |
1286 | ||
b02e7f3e | 1287 | nor->program_opcode = SPINOR_OP_BP; |
2dd087b1 | 1288 | ret = nor->write(nor, to, 1, buf + actual); |
0bad7b93 MS |
1289 | if (ret < 0) |
1290 | goto sst_write_err; | |
1291 | WARN(ret != 1, "While writing 1 byte written %i bytes\n", | |
1292 | (int)ret); | |
b94ed087 | 1293 | ret = spi_nor_wait_till_ready(nor); |
b199489d | 1294 | if (ret) |
0bad7b93 | 1295 | goto sst_write_err; |
b199489d | 1296 | write_disable(nor); |
2dd087b1 | 1297 | actual += 1; |
b199489d | 1298 | } |
0bad7b93 | 1299 | sst_write_err: |
2dd087b1 | 1300 | *retlen += actual; |
b199489d HS |
1301 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE); |
1302 | return ret; | |
1303 | } | |
1304 | ||
1305 | /* | |
1306 | * Write an address range to the nor chip. Data must be written in | |
1307 | * FLASH_PAGESIZE chunks. The address range may be any size provided | |
1308 | * it is within the physical boundaries. | |
1309 | */ | |
1310 | static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, | |
1311 | size_t *retlen, const u_char *buf) | |
1312 | { | |
1313 | struct spi_nor *nor = mtd_to_spi_nor(mtd); | |
e5d05cbd MS |
1314 | size_t page_offset, page_remain, i; |
1315 | ssize_t ret; | |
b199489d HS |
1316 | |
1317 | dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); | |
1318 | ||
1319 | ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE); | |
1320 | if (ret) | |
1321 | return ret; | |
1322 | ||
e5d05cbd MS |
1323 | for (i = 0; i < len; ) { |
1324 | ssize_t written; | |
e99ca98f | 1325 | loff_t addr = to + i; |
b199489d | 1326 | |
e99ca98f RRD |
1327 | /* |
1328 | * If page_size is a power of two, the offset can be quickly | |
1329 | * calculated with an AND operation. On the other cases we | |
1330 | * need to do a modulus operation (more expensive). | |
1331 | * Power of two numbers have only one bit set and we can use | |
1332 | * the instruction hweight32 to detect if we need to do a | |
1333 | * modulus (do_div()) or not. | |
1334 | */ | |
1335 | if (hweight32(nor->page_size) == 1) { | |
1336 | page_offset = addr & (nor->page_size - 1); | |
1337 | } else { | |
1338 | uint64_t aux = addr; | |
1339 | ||
1340 | page_offset = do_div(aux, nor->page_size); | |
1341 | } | |
b199489d | 1342 | /* the size of data remaining on the first page */ |
e5d05cbd MS |
1343 | page_remain = min_t(size_t, |
1344 | nor->page_size - page_offset, len - i); | |
1345 | ||
e99ca98f RRD |
1346 | if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT) |
1347 | addr = spi_nor_s3an_addr_convert(nor, addr); | |
1348 | ||
e5d05cbd | 1349 | write_enable(nor); |
e99ca98f | 1350 | ret = nor->write(nor, addr, page_remain, buf + i); |
0bad7b93 MS |
1351 | if (ret < 0) |
1352 | goto write_err; | |
e5d05cbd | 1353 | written = ret; |
1d61dcb3 | 1354 | |
e5d05cbd MS |
1355 | ret = spi_nor_wait_till_ready(nor); |
1356 | if (ret) | |
1357 | goto write_err; | |
1358 | *retlen += written; | |
1359 | i += written; | |
1360 | if (written != page_remain) { | |
1361 | dev_err(nor->dev, | |
1362 | "While writing %zu bytes written %zd bytes\n", | |
1363 | page_remain, written); | |
1364 | ret = -EIO; | |
1365 | goto write_err; | |
b199489d HS |
1366 | } |
1367 | } | |
1368 | ||
1369 | write_err: | |
1370 | spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE); | |
1d61dcb3 | 1371 | return ret; |
b199489d HS |
1372 | } |
1373 | ||
1374 | static int macronix_quad_enable(struct spi_nor *nor) | |
1375 | { | |
1376 | int ret, val; | |
1377 | ||
1378 | val = read_sr(nor); | |
f49289ce FE |
1379 | if (val < 0) |
1380 | return val; | |
32c90f16 CP |
1381 | if (val & SR_QUAD_EN_MX) |
1382 | return 0; | |
1383 | ||
b199489d HS |
1384 | write_enable(nor); |
1385 | ||
fd725234 | 1386 | write_sr(nor, val | SR_QUAD_EN_MX); |
b199489d | 1387 | |
b94ed087 | 1388 | if (spi_nor_wait_till_ready(nor)) |
b199489d HS |
1389 | return 1; |
1390 | ||
1391 | ret = read_sr(nor); | |
1392 | if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) { | |
1393 | dev_err(nor->dev, "Macronix Quad bit not set\n"); | |
1394 | return -EINVAL; | |
1395 | } | |
1396 | ||
1397 | return 0; | |
1398 | } | |
1399 | ||
1400 | /* | |
1401 | * Write status Register and configuration register with 2 bytes | |
1402 | * The first byte will be written to the status register, while the | |
1403 | * second byte will be written to the configuration register. | |
1404 | * Return negative if error occured. | |
1405 | */ | |
1406 | static int write_sr_cr(struct spi_nor *nor, u16 val) | |
1407 | { | |
1408 | nor->cmd_buf[0] = val & 0xff; | |
1409 | nor->cmd_buf[1] = (val >> 8); | |
1410 | ||
f9f3ce83 | 1411 | return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2); |
b199489d HS |
1412 | } |
1413 | ||
1414 | static int spansion_quad_enable(struct spi_nor *nor) | |
1415 | { | |
1416 | int ret; | |
1417 | int quad_en = CR_QUAD_EN_SPAN << 8; | |
1418 | ||
1419 | write_enable(nor); | |
1420 | ||
1421 | ret = write_sr_cr(nor, quad_en); | |
1422 | if (ret < 0) { | |
1423 | dev_err(nor->dev, | |
1424 | "error while writing configuration register\n"); | |
1425 | return -EINVAL; | |
1426 | } | |
1427 | ||
807c1625 JE |
1428 | ret = spi_nor_wait_till_ready(nor); |
1429 | if (ret) { | |
1430 | dev_err(nor->dev, | |
1431 | "timeout while writing configuration register\n"); | |
1432 | return ret; | |
1433 | } | |
1434 | ||
b199489d HS |
1435 | /* read back and check it */ |
1436 | ret = read_cr(nor); | |
1437 | if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) { | |
1438 | dev_err(nor->dev, "Spansion Quad bit not set\n"); | |
1439 | return -EINVAL; | |
1440 | } | |
1441 | ||
1442 | return 0; | |
1443 | } | |
1444 | ||
06bb6f5a | 1445 | static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info) |
b199489d HS |
1446 | { |
1447 | int status; | |
1448 | ||
d928a259 | 1449 | switch (JEDEC_MFR(info)) { |
f0d2448e | 1450 | case SNOR_MFR_MACRONIX: |
b199489d HS |
1451 | status = macronix_quad_enable(nor); |
1452 | if (status) { | |
1453 | dev_err(nor->dev, "Macronix quad-read not enabled\n"); | |
1454 | return -EINVAL; | |
1455 | } | |
1456 | return status; | |
f0d2448e | 1457 | case SNOR_MFR_MICRON: |
3b5394a3 | 1458 | return 0; |
b199489d HS |
1459 | default: |
1460 | status = spansion_quad_enable(nor); | |
1461 | if (status) { | |
1462 | dev_err(nor->dev, "Spansion quad-read not enabled\n"); | |
1463 | return -EINVAL; | |
1464 | } | |
1465 | return status; | |
1466 | } | |
1467 | } | |
1468 | ||
1469 | static int spi_nor_check(struct spi_nor *nor) | |
1470 | { | |
1471 | if (!nor->dev || !nor->read || !nor->write || | |
c67cbb83 | 1472 | !nor->read_reg || !nor->write_reg) { |
b199489d HS |
1473 | pr_err("spi-nor: please fill all the necessary fields!\n"); |
1474 | return -EINVAL; | |
1475 | } | |
1476 | ||
b199489d HS |
1477 | return 0; |
1478 | } | |
1479 | ||
e99ca98f RRD |
1480 | static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor) |
1481 | { | |
1482 | int ret; | |
1483 | u8 val; | |
1484 | ||
1485 | ret = nor->read_reg(nor, SPINOR_OP_XRDSR, &val, 1); | |
1486 | if (ret < 0) { | |
1487 | dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret); | |
1488 | return ret; | |
1489 | } | |
1490 | ||
1491 | nor->erase_opcode = SPINOR_OP_XSE; | |
1492 | nor->program_opcode = SPINOR_OP_XPP; | |
1493 | nor->read_opcode = SPINOR_OP_READ; | |
1494 | nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; | |
1495 | ||
1496 | /* | |
1497 | * This flashes have a page size of 264 or 528 bytes (known as | |
1498 | * Default addressing mode). It can be changed to a more standard | |
1499 | * Power of two mode where the page size is 256/512. This comes | |
1500 | * with a price: there is 3% less of space, the data is corrupted | |
1501 | * and the page size cannot be changed back to default addressing | |
1502 | * mode. | |
1503 | * | |
1504 | * The current addressing mode can be read from the XRDSR register | |
1505 | * and should not be changed, because is a destructive operation. | |
1506 | */ | |
1507 | if (val & XSR_PAGESIZE) { | |
1508 | /* Flash in Power of 2 mode */ | |
1509 | nor->page_size = (nor->page_size == 264) ? 256 : 512; | |
1510 | nor->mtd.writebufsize = nor->page_size; | |
1511 | nor->mtd.size = 8 * nor->page_size * info->n_sectors; | |
1512 | nor->mtd.erasesize = 8 * nor->page_size; | |
1513 | } else { | |
1514 | /* Flash in Default addressing mode */ | |
1515 | nor->flags |= SNOR_F_S3AN_ADDR_DEFAULT; | |
1516 | } | |
1517 | ||
1518 | return 0; | |
1519 | } | |
1520 | ||
70f3ce05 | 1521 | int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode) |
b199489d | 1522 | { |
06bb6f5a | 1523 | const struct flash_info *info = NULL; |
b199489d | 1524 | struct device *dev = nor->dev; |
19763671 | 1525 | struct mtd_info *mtd = &nor->mtd; |
9c7d7875 | 1526 | struct device_node *np = spi_nor_get_flash_node(nor); |
b199489d HS |
1527 | int ret; |
1528 | int i; | |
1529 | ||
1530 | ret = spi_nor_check(nor); | |
1531 | if (ret) | |
1532 | return ret; | |
1533 | ||
43163022 | 1534 | if (name) |
06bb6f5a | 1535 | info = spi_nor_match_id(name); |
43163022 | 1536 | /* Try to auto-detect if chip name wasn't specified or not found */ |
06bb6f5a RM |
1537 | if (!info) |
1538 | info = spi_nor_read_id(nor); | |
1539 | if (IS_ERR_OR_NULL(info)) | |
70f3ce05 BH |
1540 | return -ENOENT; |
1541 | ||
58c81957 RM |
1542 | /* |
1543 | * If caller has specified name of flash model that can normally be | |
1544 | * detected using JEDEC, let's verify it. | |
1545 | */ | |
1546 | if (name && info->id_len) { | |
06bb6f5a | 1547 | const struct flash_info *jinfo; |
b199489d | 1548 | |
06bb6f5a RM |
1549 | jinfo = spi_nor_read_id(nor); |
1550 | if (IS_ERR(jinfo)) { | |
1551 | return PTR_ERR(jinfo); | |
1552 | } else if (jinfo != info) { | |
b199489d HS |
1553 | /* |
1554 | * JEDEC knows better, so overwrite platform ID. We | |
1555 | * can't trust partitions any longer, but we'll let | |
1556 | * mtd apply them anyway, since some partitions may be | |
1557 | * marked read-only, and we don't want to lose that | |
1558 | * information, even if it's not 100% accurate. | |
1559 | */ | |
1560 | dev_warn(dev, "found %s, expected %s\n", | |
06bb6f5a RM |
1561 | jinfo->name, info->name); |
1562 | info = jinfo; | |
b199489d HS |
1563 | } |
1564 | } | |
1565 | ||
1566 | mutex_init(&nor->lock); | |
1567 | ||
e99ca98f RRD |
1568 | /* |
1569 | * Make sure the XSR_RDY flag is set before calling | |
1570 | * spi_nor_wait_till_ready(). Xilinx S3AN share MFR | |
1571 | * with Atmel spi-nor | |
1572 | */ | |
1573 | if (info->flags & SPI_S3AN) | |
1574 | nor->flags |= SNOR_F_READY_XSR_RDY; | |
1575 | ||
b199489d | 1576 | /* |
c6fc2171 BN |
1577 | * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up |
1578 | * with the software protection bits set | |
b199489d HS |
1579 | */ |
1580 | ||
f0d2448e BN |
1581 | if (JEDEC_MFR(info) == SNOR_MFR_ATMEL || |
1582 | JEDEC_MFR(info) == SNOR_MFR_INTEL || | |
76a4707d BN |
1583 | JEDEC_MFR(info) == SNOR_MFR_SST || |
1584 | info->flags & SPI_NOR_HAS_LOCK) { | |
b199489d HS |
1585 | write_enable(nor); |
1586 | write_sr(nor, 0); | |
edf891ef | 1587 | spi_nor_wait_till_ready(nor); |
b199489d HS |
1588 | } |
1589 | ||
32f1b7c8 | 1590 | if (!mtd->name) |
b199489d | 1591 | mtd->name = dev_name(dev); |
c9ec3900 | 1592 | mtd->priv = nor; |
b199489d HS |
1593 | mtd->type = MTD_NORFLASH; |
1594 | mtd->writesize = 1; | |
1595 | mtd->flags = MTD_CAP_NORFLASH; | |
1596 | mtd->size = info->sector_size * info->n_sectors; | |
1597 | mtd->_erase = spi_nor_erase; | |
1598 | mtd->_read = spi_nor_read; | |
1599 | ||
357ca38d | 1600 | /* NOR protection support for STmicro/Micron chips and similar */ |
76a4707d BN |
1601 | if (JEDEC_MFR(info) == SNOR_MFR_MICRON || |
1602 | info->flags & SPI_NOR_HAS_LOCK) { | |
8cc7f33a BN |
1603 | nor->flash_lock = stm_lock; |
1604 | nor->flash_unlock = stm_unlock; | |
5bf0e69b | 1605 | nor->flash_is_locked = stm_is_locked; |
8cc7f33a BN |
1606 | } |
1607 | ||
5bf0e69b | 1608 | if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) { |
b199489d HS |
1609 | mtd->_lock = spi_nor_lock; |
1610 | mtd->_unlock = spi_nor_unlock; | |
5bf0e69b | 1611 | mtd->_is_locked = spi_nor_is_locked; |
b199489d HS |
1612 | } |
1613 | ||
1614 | /* sst nor chips use AAI word program */ | |
1615 | if (info->flags & SST_WRITE) | |
1616 | mtd->_write = sst_write; | |
1617 | else | |
1618 | mtd->_write = spi_nor_write; | |
1619 | ||
51983b7d BN |
1620 | if (info->flags & USE_FSR) |
1621 | nor->flags |= SNOR_F_USE_FSR; | |
3dd8012a BN |
1622 | if (info->flags & SPI_NOR_HAS_TB) |
1623 | nor->flags |= SNOR_F_HAS_SR_TB; | |
c14dedde | 1624 | |
57cf26c1 | 1625 | #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS |
b199489d HS |
1626 | /* prefer "small sector" erase if possible */ |
1627 | if (info->flags & SECT_4K) { | |
b02e7f3e | 1628 | nor->erase_opcode = SPINOR_OP_BE_4K; |
b199489d HS |
1629 | mtd->erasesize = 4096; |
1630 | } else if (info->flags & SECT_4K_PMC) { | |
b02e7f3e | 1631 | nor->erase_opcode = SPINOR_OP_BE_4K_PMC; |
b199489d | 1632 | mtd->erasesize = 4096; |
57cf26c1 RM |
1633 | } else |
1634 | #endif | |
1635 | { | |
b02e7f3e | 1636 | nor->erase_opcode = SPINOR_OP_SE; |
b199489d HS |
1637 | mtd->erasesize = info->sector_size; |
1638 | } | |
1639 | ||
1640 | if (info->flags & SPI_NOR_NO_ERASE) | |
1641 | mtd->flags |= MTD_NO_ERASE; | |
1642 | ||
1643 | mtd->dev.parent = dev; | |
1644 | nor->page_size = info->page_size; | |
1645 | mtd->writebufsize = nor->page_size; | |
1646 | ||
1647 | if (np) { | |
1648 | /* If we were instantiated by DT, use it */ | |
1649 | if (of_property_read_bool(np, "m25p,fast-read")) | |
1650 | nor->flash_read = SPI_NOR_FAST; | |
1651 | else | |
1652 | nor->flash_read = SPI_NOR_NORMAL; | |
1653 | } else { | |
1654 | /* If we weren't instantiated by DT, default to fast-read */ | |
1655 | nor->flash_read = SPI_NOR_FAST; | |
1656 | } | |
1657 | ||
1658 | /* Some devices cannot do fast-read, no matter what DT tells us */ | |
1659 | if (info->flags & SPI_NOR_NO_FR) | |
1660 | nor->flash_read = SPI_NOR_NORMAL; | |
1661 | ||
1662 | /* Quad/Dual-read mode takes precedence over fast/normal */ | |
1663 | if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) { | |
d928a259 | 1664 | ret = set_quad_mode(nor, info); |
b199489d HS |
1665 | if (ret) { |
1666 | dev_err(dev, "quad mode not supported\n"); | |
1667 | return ret; | |
1668 | } | |
1669 | nor->flash_read = SPI_NOR_QUAD; | |
1670 | } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) { | |
1671 | nor->flash_read = SPI_NOR_DUAL; | |
1672 | } | |
1673 | ||
1674 | /* Default commands */ | |
1675 | switch (nor->flash_read) { | |
1676 | case SPI_NOR_QUAD: | |
58b89a1f | 1677 | nor->read_opcode = SPINOR_OP_READ_1_1_4; |
b199489d HS |
1678 | break; |
1679 | case SPI_NOR_DUAL: | |
58b89a1f | 1680 | nor->read_opcode = SPINOR_OP_READ_1_1_2; |
b199489d HS |
1681 | break; |
1682 | case SPI_NOR_FAST: | |
58b89a1f | 1683 | nor->read_opcode = SPINOR_OP_READ_FAST; |
b199489d HS |
1684 | break; |
1685 | case SPI_NOR_NORMAL: | |
58b89a1f | 1686 | nor->read_opcode = SPINOR_OP_READ; |
b199489d HS |
1687 | break; |
1688 | default: | |
1689 | dev_err(dev, "No Read opcode defined\n"); | |
1690 | return -EINVAL; | |
1691 | } | |
1692 | ||
b02e7f3e | 1693 | nor->program_opcode = SPINOR_OP_PP; |
b199489d HS |
1694 | |
1695 | if (info->addr_width) | |
1696 | nor->addr_width = info->addr_width; | |
1697 | else if (mtd->size > 0x1000000) { | |
1698 | /* enable 4-byte addressing if the device exceeds 16MiB */ | |
1699 | nor->addr_width = 4; | |
ba3ae6a1 CP |
1700 | if (JEDEC_MFR(info) == SNOR_MFR_SPANSION || |
1701 | info->flags & SPI_NOR_4B_OPCODES) | |
1702 | spi_nor_set_4byte_opcodes(nor, info); | |
1703 | else | |
d928a259 | 1704 | set_4byte(nor, info, 1); |
b199489d HS |
1705 | } else { |
1706 | nor->addr_width = 3; | |
1707 | } | |
1708 | ||
c67cbb83 BN |
1709 | if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { |
1710 | dev_err(dev, "address width is too large: %u\n", | |
1711 | nor->addr_width); | |
1712 | return -EINVAL; | |
1713 | } | |
1714 | ||
b199489d HS |
1715 | nor->read_dummy = spi_nor_read_dummy_cycles(nor); |
1716 | ||
e99ca98f RRD |
1717 | if (info->flags & SPI_S3AN) { |
1718 | ret = s3an_nor_scan(info, nor); | |
1719 | if (ret) | |
1720 | return ret; | |
1721 | } | |
1722 | ||
06bb6f5a | 1723 | dev_info(dev, "%s (%lld Kbytes)\n", info->name, |
b199489d HS |
1724 | (long long)mtd->size >> 10); |
1725 | ||
1726 | dev_dbg(dev, | |
1727 | "mtd .name = %s, .size = 0x%llx (%lldMiB), " | |
1728 | ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", | |
1729 | mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20), | |
1730 | mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions); | |
1731 | ||
1732 | if (mtd->numeraseregions) | |
1733 | for (i = 0; i < mtd->numeraseregions; i++) | |
1734 | dev_dbg(dev, | |
1735 | "mtd.eraseregions[%d] = { .offset = 0x%llx, " | |
1736 | ".erasesize = 0x%.8x (%uKiB), " | |
1737 | ".numblocks = %d }\n", | |
1738 | i, (long long)mtd->eraseregions[i].offset, | |
1739 | mtd->eraseregions[i].erasesize, | |
1740 | mtd->eraseregions[i].erasesize / 1024, | |
1741 | mtd->eraseregions[i].numblocks); | |
1742 | return 0; | |
1743 | } | |
b61834b0 | 1744 | EXPORT_SYMBOL_GPL(spi_nor_scan); |
b199489d | 1745 | |
06bb6f5a | 1746 | static const struct flash_info *spi_nor_match_id(const char *name) |
0d8c11c0 | 1747 | { |
06bb6f5a | 1748 | const struct flash_info *id = spi_nor_ids; |
0d8c11c0 | 1749 | |
2ff46e6f | 1750 | while (id->name) { |
0d8c11c0 HS |
1751 | if (!strcmp(name, id->name)) |
1752 | return id; | |
1753 | id++; | |
1754 | } | |
1755 | return NULL; | |
1756 | } | |
1757 | ||
b199489d HS |
1758 | MODULE_LICENSE("GPL"); |
1759 | MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>"); | |
1760 | MODULE_AUTHOR("Mike Lavender"); | |
1761 | MODULE_DESCRIPTION("framework for SPI NOR"); |