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[netdrvr 8139cp] TSO support
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1da177e4
LT		 1/* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2/*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29 * Implement dev->tx_timeout
30
31 Low priority TODO:
32 * Complete reset on PciErr
33 * Consider Rx interrupt mitigation using TimerIntr
34 * Investigate using skb->priority with h/w VLAN priority
35 * Investigate using High Priority Tx Queue with skb->priority
36 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
37 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
38 * Implement Tx software interrupt mitigation via
39 Tx descriptor bit
40 * The real minimum of CP_MIN_MTU is 4 bytes. However,
41 for this to be supported, one must(?) turn on packet padding.
42 * Support external MII transceivers (patch available)
43
44 NOTES:
45 * TX checksumming is considered experimental. It is off by
46 default, use ethtool to turn it on.
47
48 */
49
50#define DRV_NAME "8139cp"
51#define DRV_VERSION "1.2"
52#define DRV_RELDATE "Mar 22, 2004"
53
54
55#include <linux/config.h>
56#include <linux/module.h>
57#include <linux/kernel.h>
58#include <linux/compiler.h>
59#include <linux/netdevice.h>
60#include <linux/etherdevice.h>
61#include <linux/init.h>
62#include <linux/pci.h>
63#include <linux/delay.h>
64#include <linux/ethtool.h>
65#include <linux/mii.h>
66#include <linux/if_vlan.h>
67#include <linux/crc32.h>
68#include <linux/in.h>
69#include <linux/ip.h>
70#include <linux/tcp.h>
71#include <linux/udp.h>
72#include <linux/cache.h>
73#include <asm/io.h>
74#include <asm/irq.h>
75#include <asm/uaccess.h>
76
77/* VLAN tagging feature enable/disable */
78#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
79#define CP_VLAN_TAG_USED 1
80#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
81 do { (tx_desc)->opts2 = (vlan_tag_value); } while (0)
82#else
83#define CP_VLAN_TAG_USED 0
84#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
85 do { (tx_desc)->opts2 = 0; } while (0)
86#endif
87
88/* These identify the driver base version and may not be removed. */
89static char version[] =
90KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
91
92MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
93MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
94MODULE_LICENSE("GPL");
95
96static int debug = -1;
97MODULE_PARM (debug, "i");
98MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
99
100/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
101 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
102static int multicast_filter_limit = 32;
103MODULE_PARM (multicast_filter_limit, "i");
104MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
105
106#define PFX DRV_NAME ": "
107
108#ifndef TRUE
109#define FALSE 0
110#define TRUE (!FALSE)
111#endif
112
113#define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
114 NETIF_MSG_PROBE | \
115 NETIF_MSG_LINK)
116#define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
117#define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
118#define CP_REGS_SIZE (0xff + 1)
119#define CP_REGS_VER 1 /* version 1 */
120#define CP_RX_RING_SIZE 64
121#define CP_TX_RING_SIZE 64
122#define CP_RING_BYTES \
123 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
124 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
125 CP_STATS_SIZE)
126#define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
127#define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
128#define TX_BUFFS_AVAIL(CP) \
129 (((CP)->tx_tail <= (CP)->tx_head) ? \
130 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
131 (CP)->tx_tail - (CP)->tx_head - 1)
132
133#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
134#define RX_OFFSET 2
135#define CP_INTERNAL_PHY 32
136
137/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
138#define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
139#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
140#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
141#define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
142
143/* Time in jiffies before concluding the transmitter is hung. */
144#define TX_TIMEOUT (6*HZ)
145
146/* hardware minimum and maximum for a single frame's data payload */
147#define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
148#define CP_MAX_MTU 4096
149
150enum {
151 /* NIC register offsets */
152 MAC0 = 0x00, /* Ethernet hardware address. */
153 MAR0 = 0x08, /* Multicast filter. */
154 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
155 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
156 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
157 Cmd = 0x37, /* Command register */
158 IntrMask = 0x3C, /* Interrupt mask */
159 IntrStatus = 0x3E, /* Interrupt status */
160 TxConfig = 0x40, /* Tx configuration */
161 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
162 RxConfig = 0x44, /* Rx configuration */
163 RxMissed = 0x4C, /* 24 bits valid, write clears */
164 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
165 Config1 = 0x52, /* Config1 */
166 Config3 = 0x59, /* Config3 */
167 Config4 = 0x5A, /* Config4 */
168 MultiIntr = 0x5C, /* Multiple interrupt select */
169 BasicModeCtrl = 0x62, /* MII BMCR */
170 BasicModeStatus = 0x64, /* MII BMSR */
171 NWayAdvert = 0x66, /* MII ADVERTISE */
172 NWayLPAR = 0x68, /* MII LPA */
173 NWayExpansion = 0x6A, /* MII Expansion */
174 Config5 = 0xD8, /* Config5 */
175 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
176 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
177 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
178 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
179 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
180 TxThresh = 0xEC, /* Early Tx threshold */
181 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
182 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
183
184 /* Tx and Rx status descriptors */
185 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
186 RingEnd = (1 << 30), /* End of descriptor ring */
187 FirstFrag = (1 << 29), /* First segment of a packet */
188 LastFrag = (1 << 28), /* Final segment of a packet */
fcec3456
JG		 189 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
190 MSSShift = 16, /* MSS value position */
191 MSSMask = 0xfff, /* MSS value: 11 bits */
1da177e4
LT		 192 TxError = (1 << 23), /* Tx error summary */
193 RxError = (1 << 20), /* Rx error summary */
194 IPCS = (1 << 18), /* Calculate IP checksum */
195 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
196 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
197 TxVlanTag = (1 << 17), /* Add VLAN tag */
198 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
199 IPFail = (1 << 15), /* IP checksum failed */
200 UDPFail = (1 << 14), /* UDP/IP checksum failed */
201 TCPFail = (1 << 13), /* TCP/IP checksum failed */
202 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
203 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
204 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
205 RxProtoTCP = 1,
206 RxProtoUDP = 2,
207 RxProtoIP = 3,
208 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
209 TxOWC = (1 << 22), /* Tx Out-of-window collision */
210 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
211 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
212 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
213 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
214 RxErrFrame = (1 << 27), /* Rx frame alignment error */
215 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
216 RxErrCRC = (1 << 18), /* Rx CRC error */
217 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
218 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
219 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
220
221 /* StatsAddr register */
222 DumpStats = (1 << 3), /* Begin stats dump */
223
224 /* RxConfig register */
225 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
226 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
227 AcceptErr = 0x20, /* Accept packets with CRC errors */
228 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
229 AcceptBroadcast = 0x08, /* Accept broadcast packets */
230 AcceptMulticast = 0x04, /* Accept multicast packets */
231 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
232 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
233
234 /* IntrMask / IntrStatus registers */
235 PciErr = (1 << 15), /* System error on the PCI bus */
236 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
237 LenChg = (1 << 13), /* Cable length change */
238 SWInt = (1 << 8), /* Software-requested interrupt */
239 TxEmpty = (1 << 7), /* No Tx descriptors available */
240 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
241 LinkChg = (1 << 5), /* Packet underrun, or link change */
242 RxEmpty = (1 << 4), /* No Rx descriptors available */
243 TxErr = (1 << 3), /* Tx error */
244 TxOK = (1 << 2), /* Tx packet sent */
245 RxErr = (1 << 1), /* Rx error */
246 RxOK = (1 << 0), /* Rx packet received */
247 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
248 but hardware likes to raise it */
249
250 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
251 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
252 RxErr | RxOK | IntrResvd,
253
254 /* C mode command register */
255 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
256 RxOn = (1 << 3), /* Rx mode enable */
257 TxOn = (1 << 2), /* Tx mode enable */
258
259 /* C+ mode command register */
260 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
261 RxChkSum = (1 << 5), /* Rx checksum offload enable */
262 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
263 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
264 CpRxOn = (1 << 1), /* Rx mode enable */
265 CpTxOn = (1 << 0), /* Tx mode enable */
266
267 /* Cfg9436 EEPROM control register */
268 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
269 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
270
271 /* TxConfig register */
272 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
273 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
274
275 /* Early Tx Threshold register */
276 TxThreshMask = 0x3f, /* Mask bits 5-0 */
277 TxThreshMax = 2048, /* Max early Tx threshold */
278
279 /* Config1 register */
280 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
281 LWACT = (1 << 4), /* LWAKE active mode */
282 PMEnable = (1 << 0), /* Enable various PM features of chip */
283
284 /* Config3 register */
285 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
286 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
287 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
288
289 /* Config4 register */
290 LWPTN = (1 << 1), /* LWAKE Pattern */
291 LWPME = (1 << 4), /* LANWAKE vs PMEB */
292
293 /* Config5 register */
294 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
295 MWF = (1 << 5), /* Accept Multicast wakeup frame */
296 UWF = (1 << 4), /* Accept Unicast wakeup frame */
297 LANWake = (1 << 1), /* Enable LANWake signal */
298 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
299
300 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
301 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
302 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
303};
304
305static const unsigned int cp_rx_config =
306 (RX_FIFO_THRESH << RxCfgFIFOShift) |
307 (RX_DMA_BURST << RxCfgDMAShift);
308
309struct cp_desc {
310 u32 opts1;
311 u32 opts2;
312 u64 addr;
313};
314
315struct ring_info {
316 struct sk_buff *skb;
317 dma_addr_t mapping;
318 unsigned frag;
319};
320
321struct cp_dma_stats {
322 u64 tx_ok;
323 u64 rx_ok;
324 u64 tx_err;
325 u32 rx_err;
326 u16 rx_fifo;
327 u16 frame_align;
328 u32 tx_ok_1col;
329 u32 tx_ok_mcol;
330 u64 rx_ok_phys;
331 u64 rx_ok_bcast;
332 u32 rx_ok_mcast;
333 u16 tx_abort;
334 u16 tx_underrun;
335} __attribute__((packed));
336
337struct cp_extra_stats {
338 unsigned long rx_frags;
339};
340
341struct cp_private {
342 void __iomem *regs;
343 struct net_device *dev;
344 spinlock_t lock;
345 u32 msg_enable;
346
347 struct pci_dev *pdev;
348 u32 rx_config;
349 u16 cpcmd;
350
351 struct net_device_stats net_stats;
352 struct cp_extra_stats cp_stats;
353 struct cp_dma_stats *nic_stats;
354 dma_addr_t nic_stats_dma;
355
356 unsigned rx_tail ____cacheline_aligned;
357 struct cp_desc *rx_ring;
358 struct ring_info rx_skb[CP_RX_RING_SIZE];
359 unsigned rx_buf_sz;
360
361 unsigned tx_head ____cacheline_aligned;
362 unsigned tx_tail;
363
364 struct cp_desc *tx_ring;
365 struct ring_info tx_skb[CP_TX_RING_SIZE];
366 dma_addr_t ring_dma;
367
368#if CP_VLAN_TAG_USED
369 struct vlan_group *vlgrp;
370#endif
371
372 unsigned int wol_enabled : 1; /* Is Wake-on-LAN enabled? */
373
374 struct mii_if_info mii_if;
375};
376
377#define cpr8(reg) readb(cp->regs + (reg))
378#define cpr16(reg) readw(cp->regs + (reg))
379#define cpr32(reg) readl(cp->regs + (reg))
380#define cpw8(reg,val) writeb((val), cp->regs + (reg))
381#define cpw16(reg,val) writew((val), cp->regs + (reg))
382#define cpw32(reg,val) writel((val), cp->regs + (reg))
383#define cpw8_f(reg,val) do { \
384 writeb((val), cp->regs + (reg)); \
385 readb(cp->regs + (reg)); \
386 } while (0)
387#define cpw16_f(reg,val) do { \
388 writew((val), cp->regs + (reg)); \
389 readw(cp->regs + (reg)); \
390 } while (0)
391#define cpw32_f(reg,val) do { \
392 writel((val), cp->regs + (reg)); \
393 readl(cp->regs + (reg)); \
394 } while (0)
395
396
397static void __cp_set_rx_mode (struct net_device *dev);
398static void cp_tx (struct cp_private *cp);
399static void cp_clean_rings (struct cp_private *cp);
400
401static struct pci_device_id cp_pci_tbl[] = {
402 { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139,
403 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
404 { PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322,
405 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
406 { },
407};
408MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
409
410static struct {
411 const char str[ETH_GSTRING_LEN];
412} ethtool_stats_keys[] = {
413 { "tx_ok" },
414 { "rx_ok" },
415 { "tx_err" },
416 { "rx_err" },
417 { "rx_fifo" },
418 { "frame_align" },
419 { "tx_ok_1col" },
420 { "tx_ok_mcol" },
421 { "rx_ok_phys" },
422 { "rx_ok_bcast" },
423 { "rx_ok_mcast" },
424 { "tx_abort" },
425 { "tx_underrun" },
426 { "rx_frags" },
427};
428
429
430#if CP_VLAN_TAG_USED
431static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
432{
433 struct cp_private *cp = netdev_priv(dev);
434 unsigned long flags;
435
436 spin_lock_irqsave(&cp->lock, flags);
437 cp->vlgrp = grp;
438 cp->cpcmd |= RxVlanOn;
439 cpw16(CpCmd, cp->cpcmd);
440 spin_unlock_irqrestore(&cp->lock, flags);
441}
442
443static void cp_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
444{
445 struct cp_private *cp = netdev_priv(dev);
446 unsigned long flags;
447
448 spin_lock_irqsave(&cp->lock, flags);
449 cp->cpcmd &= ~RxVlanOn;
450 cpw16(CpCmd, cp->cpcmd);
451 if (cp->vlgrp)
452 cp->vlgrp->vlan_devices[vid] = NULL;
453 spin_unlock_irqrestore(&cp->lock, flags);
454}
455#endif /* CP_VLAN_TAG_USED */
456
457static inline void cp_set_rxbufsize (struct cp_private *cp)
458{
459 unsigned int mtu = cp->dev->mtu;
460
461 if (mtu > ETH_DATA_LEN)
462 /* MTU + ethernet header + FCS + optional VLAN tag */
463 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
464 else
465 cp->rx_buf_sz = PKT_BUF_SZ;
466}
467
468static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
469 struct cp_desc *desc)
470{
471 skb->protocol = eth_type_trans (skb, cp->dev);
472
473 cp->net_stats.rx_packets++;
474 cp->net_stats.rx_bytes += skb->len;
475 cp->dev->last_rx = jiffies;
476
477#if CP_VLAN_TAG_USED
478 if (cp->vlgrp && (desc->opts2 & RxVlanTagged)) {
479 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
480 be16_to_cpu(desc->opts2 & 0xffff));
481 } else
482#endif
483 netif_receive_skb(skb);
484}
485
486static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
487 u32 status, u32 len)
488{
489 if (netif_msg_rx_err (cp))
490 printk (KERN_DEBUG
491 "%s: rx err, slot %d status 0x%x len %d\n",
492 cp->dev->name, rx_tail, status, len);
493 cp->net_stats.rx_errors++;
494 if (status & RxErrFrame)
495 cp->net_stats.rx_frame_errors++;
496 if (status & RxErrCRC)
497 cp->net_stats.rx_crc_errors++;
498 if ((status & RxErrRunt) || (status & RxErrLong))
499 cp->net_stats.rx_length_errors++;
500 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
501 cp->net_stats.rx_length_errors++;
502 if (status & RxErrFIFO)
503 cp->net_stats.rx_fifo_errors++;
504}
505
506static inline unsigned int cp_rx_csum_ok (u32 status)
507{
508 unsigned int protocol = (status >> 16) & 0x3;
509
510 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
511 return 1;
512 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
513 return 1;
514 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
515 return 1;
516 return 0;
517}
518
519static int cp_rx_poll (struct net_device *dev, int *budget)
520{
521 struct cp_private *cp = netdev_priv(dev);
522 unsigned rx_tail = cp->rx_tail;
523 unsigned rx_work = dev->quota;
524 unsigned rx;
525
526rx_status_loop:
527 rx = 0;
528 cpw16(IntrStatus, cp_rx_intr_mask);
529
530 while (1) {
531 u32 status, len;
532 dma_addr_t mapping;
533 struct sk_buff *skb, *new_skb;
534 struct cp_desc *desc;
535 unsigned buflen;
536
537 skb = cp->rx_skb[rx_tail].skb;
538 if (!skb)
539 BUG();
540
541 desc = &cp->rx_ring[rx_tail];
542 status = le32_to_cpu(desc->opts1);
543 if (status & DescOwn)
544 break;
545
546 len = (status & 0x1fff) - 4;
547 mapping = cp->rx_skb[rx_tail].mapping;
548
549 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
550 /* we don't support incoming fragmented frames.
551 * instead, we attempt to ensure that the
552 * pre-allocated RX skbs are properly sized such
553 * that RX fragments are never encountered
554 */
555 cp_rx_err_acct(cp, rx_tail, status, len);
556 cp->net_stats.rx_dropped++;
557 cp->cp_stats.rx_frags++;
558 goto rx_next;
559 }
560
561 if (status & (RxError | RxErrFIFO)) {
562 cp_rx_err_acct(cp, rx_tail, status, len);
563 goto rx_next;
564 }
565
566 if (netif_msg_rx_status(cp))
567 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
568 cp->dev->name, rx_tail, status, len);
569
570 buflen = cp->rx_buf_sz + RX_OFFSET;
571 new_skb = dev_alloc_skb (buflen);
572 if (!new_skb) {
573 cp->net_stats.rx_dropped++;
574 goto rx_next;
575 }
576
577 skb_reserve(new_skb, RX_OFFSET);
578 new_skb->dev = cp->dev;
579
580 pci_unmap_single(cp->pdev, mapping,
581 buflen, PCI_DMA_FROMDEVICE);
582
583 /* Handle checksum offloading for incoming packets. */
584 if (cp_rx_csum_ok(status))
585 skb->ip_summed = CHECKSUM_UNNECESSARY;
586 else
587 skb->ip_summed = CHECKSUM_NONE;
588
589 skb_put(skb, len);
590
591 mapping =
592 cp->rx_skb[rx_tail].mapping =
593 pci_map_single(cp->pdev, new_skb->tail,
594 buflen, PCI_DMA_FROMDEVICE);
595 cp->rx_skb[rx_tail].skb = new_skb;
596
597 cp_rx_skb(cp, skb, desc);
598 rx++;
599
600rx_next:
601 cp->rx_ring[rx_tail].opts2 = 0;
602 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
603 if (rx_tail == (CP_RX_RING_SIZE - 1))
604 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
605 cp->rx_buf_sz);
606 else
607 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
608 rx_tail = NEXT_RX(rx_tail);
609
610 if (!rx_work--)
611 break;
612 }
613
614 cp->rx_tail = rx_tail;
615
616 dev->quota -= rx;
617 *budget -= rx;
618
619 /* if we did not reach work limit, then we're done with
620 * this round of polling
621 */
622 if (rx_work) {
623 if (cpr16(IntrStatus) & cp_rx_intr_mask)
624 goto rx_status_loop;
625
626 local_irq_disable();
627 cpw16_f(IntrMask, cp_intr_mask);
628 __netif_rx_complete(dev);
629 local_irq_enable();
630
631 return 0; /* done */
632 }
633
634 return 1; /* not done */
635}
636
637static irqreturn_t
638cp_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
639{
640 struct net_device *dev = dev_instance;
641 struct cp_private *cp;
642 u16 status;
643
644 if (unlikely(dev == NULL))
645 return IRQ_NONE;
646 cp = netdev_priv(dev);
647
648 status = cpr16(IntrStatus);
649 if (!status || (status == 0xFFFF))
650 return IRQ_NONE;
651
652 if (netif_msg_intr(cp))
653 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
654 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
655
656 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
657
658 spin_lock(&cp->lock);
659
660 /* close possible race's with dev_close */
661 if (unlikely(!netif_running(dev))) {
662 cpw16(IntrMask, 0);
663 spin_unlock(&cp->lock);
664 return IRQ_HANDLED;
665 }
666
667 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
668 if (netif_rx_schedule_prep(dev)) {
669 cpw16_f(IntrMask, cp_norx_intr_mask);
670 __netif_rx_schedule(dev);
671 }
672
673 if (status & (TxOK | TxErr | TxEmpty | SWInt))
674 cp_tx(cp);
675 if (status & LinkChg)
676 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
677
678 spin_unlock(&cp->lock);
679
680 if (status & PciErr) {
681 u16 pci_status;
682
683 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
684 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
685 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
686 dev->name, status, pci_status);
687
688 /* TODO: reset hardware */
689 }
690
691 return IRQ_HANDLED;
692}
693
694static void cp_tx (struct cp_private *cp)
695{
696 unsigned tx_head = cp->tx_head;
697 unsigned tx_tail = cp->tx_tail;
698
699 while (tx_tail != tx_head) {
700 struct sk_buff *skb;
701 u32 status;
702
703 rmb();
704 status = le32_to_cpu(cp->tx_ring[tx_tail].opts1);
705 if (status & DescOwn)
706 break;
707
708 skb = cp->tx_skb[tx_tail].skb;
709 if (!skb)
710 BUG();
711
712 pci_unmap_single(cp->pdev, cp->tx_skb[tx_tail].mapping,
713 skb->len, PCI_DMA_TODEVICE);
714
715 if (status & LastFrag) {
716 if (status & (TxError | TxFIFOUnder)) {
717 if (netif_msg_tx_err(cp))
718 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
719 cp->dev->name, status);
720 cp->net_stats.tx_errors++;
721 if (status & TxOWC)
722 cp->net_stats.tx_window_errors++;
723 if (status & TxMaxCol)
724 cp->net_stats.tx_aborted_errors++;
725 if (status & TxLinkFail)
726 cp->net_stats.tx_carrier_errors++;
727 if (status & TxFIFOUnder)
728 cp->net_stats.tx_fifo_errors++;
729 } else {
730 cp->net_stats.collisions +=
731 ((status >> TxColCntShift) & TxColCntMask);
732 cp->net_stats.tx_packets++;
733 cp->net_stats.tx_bytes += skb->len;
734 if (netif_msg_tx_done(cp))
735 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
736 }
737 dev_kfree_skb_irq(skb);
738 }
739
740 cp->tx_skb[tx_tail].skb = NULL;
741
742 tx_tail = NEXT_TX(tx_tail);
743 }
744
745 cp->tx_tail = tx_tail;
746
747 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
748 netif_wake_queue(cp->dev);
749}
750
751static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
752{
753 struct cp_private *cp = netdev_priv(dev);
754 unsigned entry;
fcec3456 755 u32 eor, flags;
1da177e4
LT		 756#if CP_VLAN_TAG_USED
757 u32 vlan_tag = 0;
758#endif
fcec3456 759 int mss = 0;
1da177e4
LT		 760
761 spin_lock_irq(&cp->lock);
762
763 /* This is a hard error, log it. */
764 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
765 netif_stop_queue(dev);
766 spin_unlock_irq(&cp->lock);
767 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
768 dev->name);
769 return 1;
770 }
771
772#if CP_VLAN_TAG_USED
773 if (cp->vlgrp && vlan_tx_tag_present(skb))
774 vlan_tag = TxVlanTag | cpu_to_be16(vlan_tx_tag_get(skb));
775#endif
776
777 entry = cp->tx_head;
778 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
fcec3456
JG		 779 if (dev->features & NETIF_F_TSO)
780 mss = skb_shinfo(skb)->tso_size;
781
1da177e4
LT		 782 if (skb_shinfo(skb)->nr_frags == 0) {
783 struct cp_desc *txd = &cp->tx_ring[entry];
784 u32 len;
785 dma_addr_t mapping;
786
787 len = skb->len;
788 mapping = pci_map_single(cp->pdev, skb->data, len, PCI_DMA_TODEVICE);
789 CP_VLAN_TX_TAG(txd, vlan_tag);
790 txd->addr = cpu_to_le64(mapping);
791 wmb();
792
fcec3456
JG		 793 flags = eor | len | DescOwn | FirstFrag | LastFrag;
794
795 if (mss)
796 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
797 else if (skb->ip_summed == CHECKSUM_HW) {
1da177e4
LT		 798 const struct iphdr *ip = skb->nh.iph;
799 if (ip->protocol == IPPROTO_TCP)
fcec3456 800 flags |= IPCS | TCPCS;
1da177e4 801 else if (ip->protocol == IPPROTO_UDP)
fcec3456 802 flags |= IPCS | UDPCS;
1da177e4
LT		 803 else
804 BUG();
fcec3456
JG		 805 }
806
807 txd->opts1 = cpu_to_le32(flags);
1da177e4
LT		 808 wmb();
809
810 cp->tx_skb[entry].skb = skb;
811 cp->tx_skb[entry].mapping = mapping;
812 cp->tx_skb[entry].frag = 0;
813 entry = NEXT_TX(entry);
814 } else {
815 struct cp_desc *txd;
816 u32 first_len, first_eor;
817 dma_addr_t first_mapping;
818 int frag, first_entry = entry;
819 const struct iphdr *ip = skb->nh.iph;
820
821 /* We must give this initial chunk to the device last.
822 * Otherwise we could race with the device.
823 */
824 first_eor = eor;
825 first_len = skb_headlen(skb);
826 first_mapping = pci_map_single(cp->pdev, skb->data,
827 first_len, PCI_DMA_TODEVICE);
828 cp->tx_skb[entry].skb = skb;
829 cp->tx_skb[entry].mapping = first_mapping;
830 cp->tx_skb[entry].frag = 1;
831 entry = NEXT_TX(entry);
832
833 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
834 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
835 u32 len;
836 u32 ctrl;
837 dma_addr_t mapping;
838
839 len = this_frag->size;
840 mapping = pci_map_single(cp->pdev,
841 ((void *) page_address(this_frag->page) +
842 this_frag->page_offset),
843 len, PCI_DMA_TODEVICE);
844 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
845
fcec3456
JG		 846 ctrl = eor | len | DescOwn;
847
848 if (mss)
849 ctrl |= LargeSend |
850 ((mss & MSSMask) << MSSShift);
851 else if (skb->ip_summed == CHECKSUM_HW) {
1da177e4 852 if (ip->protocol == IPPROTO_TCP)
fcec3456 853 ctrl |= IPCS | TCPCS;
1da177e4 854 else if (ip->protocol == IPPROTO_UDP)
fcec3456 855 ctrl |= IPCS | UDPCS;
1da177e4
LT		 856 else
857 BUG();
fcec3456 858 }
1da177e4
LT		 859
860 if (frag == skb_shinfo(skb)->nr_frags - 1)
861 ctrl |= LastFrag;
862
863 txd = &cp->tx_ring[entry];
864 CP_VLAN_TX_TAG(txd, vlan_tag);
865 txd->addr = cpu_to_le64(mapping);
866 wmb();
867
868 txd->opts1 = cpu_to_le32(ctrl);
869 wmb();
870
871 cp->tx_skb[entry].skb = skb;
872 cp->tx_skb[entry].mapping = mapping;
873 cp->tx_skb[entry].frag = frag + 2;
874 entry = NEXT_TX(entry);
875 }
876
877 txd = &cp->tx_ring[first_entry];
878 CP_VLAN_TX_TAG(txd, vlan_tag);
879 txd->addr = cpu_to_le64(first_mapping);
880 wmb();
881
882 if (skb->ip_summed == CHECKSUM_HW) {
883 if (ip->protocol == IPPROTO_TCP)
884 txd->opts1 = cpu_to_le32(first_eor | first_len |
885 FirstFrag | DescOwn |
886 IPCS | TCPCS);
887 else if (ip->protocol == IPPROTO_UDP)
888 txd->opts1 = cpu_to_le32(first_eor | first_len |
889 FirstFrag | DescOwn |
890 IPCS | UDPCS);
891 else
892 BUG();
893 } else
894 txd->opts1 = cpu_to_le32(first_eor | first_len |
895 FirstFrag | DescOwn);
896 wmb();
897 }
898 cp->tx_head = entry;
899 if (netif_msg_tx_queued(cp))
900 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
901 dev->name, entry, skb->len);
902 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
903 netif_stop_queue(dev);
904
905 spin_unlock_irq(&cp->lock);
906
907 cpw8(TxPoll, NormalTxPoll);
908 dev->trans_start = jiffies;
909
910 return 0;
911}
912
913/* Set or clear the multicast filter for this adaptor.
914 This routine is not state sensitive and need not be SMP locked. */
915
916static void __cp_set_rx_mode (struct net_device *dev)
917{
918 struct cp_private *cp = netdev_priv(dev);
919 u32 mc_filter[2]; /* Multicast hash filter */
920 int i, rx_mode;
921 u32 tmp;
922
923 /* Note: do not reorder, GCC is clever about common statements. */
924 if (dev->flags & IFF_PROMISC) {
925 /* Unconditionally log net taps. */
926 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
927 dev->name);
928 rx_mode =
929 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
930 AcceptAllPhys;
931 mc_filter[1] = mc_filter[0] = 0xffffffff;
932 } else if ((dev->mc_count > multicast_filter_limit)
933 || (dev->flags & IFF_ALLMULTI)) {
934 /* Too many to filter perfectly -- accept all multicasts. */
935 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
936 mc_filter[1] = mc_filter[0] = 0xffffffff;
937 } else {
938 struct dev_mc_list *mclist;
939 rx_mode = AcceptBroadcast | AcceptMyPhys;
940 mc_filter[1] = mc_filter[0] = 0;
941 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
942 i++, mclist = mclist->next) {
943 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
944
945 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
946 rx_mode |= AcceptMulticast;
947 }
948 }
949
950 /* We can safely update without stopping the chip. */
951 tmp = cp_rx_config | rx_mode;
952 if (cp->rx_config != tmp) {
953 cpw32_f (RxConfig, tmp);
954 cp->rx_config = tmp;
955 }
956 cpw32_f (MAR0 + 0, mc_filter[0]);
957 cpw32_f (MAR0 + 4, mc_filter[1]);
958}
959
960static void cp_set_rx_mode (struct net_device *dev)
961{
962 unsigned long flags;
963 struct cp_private *cp = netdev_priv(dev);
964
965 spin_lock_irqsave (&cp->lock, flags);
966 __cp_set_rx_mode(dev);
967 spin_unlock_irqrestore (&cp->lock, flags);
968}
969
970static void __cp_get_stats(struct cp_private *cp)
971{
972 /* only lower 24 bits valid; write any value to clear */
973 cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
974 cpw32 (RxMissed, 0);
975}
976
977static struct net_device_stats *cp_get_stats(struct net_device *dev)
978{
979 struct cp_private *cp = netdev_priv(dev);
980 unsigned long flags;
981
982 /* The chip only need report frame silently dropped. */
983 spin_lock_irqsave(&cp->lock, flags);
984 if (netif_running(dev) && netif_device_present(dev))
985 __cp_get_stats(cp);
986 spin_unlock_irqrestore(&cp->lock, flags);
987
988 return &cp->net_stats;
989}
990
991static void cp_stop_hw (struct cp_private *cp)
992{
993 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
994 cpw16_f(IntrMask, 0);
995 cpw8(Cmd, 0);
996 cpw16_f(CpCmd, 0);
997 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
998
999 cp->rx_tail = 0;
1000 cp->tx_head = cp->tx_tail = 0;
1001}
1002
1003static void cp_reset_hw (struct cp_private *cp)
1004{
1005 unsigned work = 1000;
1006
1007 cpw8(Cmd, CmdReset);
1008
1009 while (work--) {
1010 if (!(cpr8(Cmd) & CmdReset))
1011 return;
1012
1013 set_current_state(TASK_UNINTERRUPTIBLE);
1014 schedule_timeout(10);
1015 }
1016
1017 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1018}
1019
1020static inline void cp_start_hw (struct cp_private *cp)
1021{
1022 cpw16(CpCmd, cp->cpcmd);
1023 cpw8(Cmd, RxOn | TxOn);
1024}
1025
1026static void cp_init_hw (struct cp_private *cp)
1027{
1028 struct net_device *dev = cp->dev;
1029 dma_addr_t ring_dma;
1030
1031 cp_reset_hw(cp);
1032
1033 cpw8_f (Cfg9346, Cfg9346_Unlock);
1034
1035 /* Restore our idea of the MAC address. */
1036 cpw32_f (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1037 cpw32_f (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1038
1039 cp_start_hw(cp);
1040 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1041
1042 __cp_set_rx_mode(dev);
1043 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1044
1045 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1046 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1047 cpw8(Config3, PARMEnable);
1048 cp->wol_enabled = 0;
1049
1050 cpw8(Config5, cpr8(Config5) & PMEStatus);
1051
1052 cpw32_f(HiTxRingAddr, 0);
1053 cpw32_f(HiTxRingAddr + 4, 0);
1054
1055 ring_dma = cp->ring_dma;
1056 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1057 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1058
1059 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1060 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1061 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1062
1063 cpw16(MultiIntr, 0);
1064
1065 cpw16_f(IntrMask, cp_intr_mask);
1066
1067 cpw8_f(Cfg9346, Cfg9346_Lock);
1068}
1069
1070static int cp_refill_rx (struct cp_private *cp)
1071{
1072 unsigned i;
1073
1074 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1075 struct sk_buff *skb;
1076
1077 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1078 if (!skb)
1079 goto err_out;
1080
1081 skb->dev = cp->dev;
1082 skb_reserve(skb, RX_OFFSET);
1083
1084 cp->rx_skb[i].mapping = pci_map_single(cp->pdev,
1085 skb->tail, cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1086 cp->rx_skb[i].skb = skb;
1087 cp->rx_skb[i].frag = 0;
1088
1089 cp->rx_ring[i].opts2 = 0;
1090 cp->rx_ring[i].addr = cpu_to_le64(cp->rx_skb[i].mapping);
1091 if (i == (CP_RX_RING_SIZE - 1))
1092 cp->rx_ring[i].opts1 =
1093 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1094 else
1095 cp->rx_ring[i].opts1 =
1096 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1097 }
1098
1099 return 0;
1100
1101err_out:
1102 cp_clean_rings(cp);
1103 return -ENOMEM;
1104}
1105
1106static int cp_init_rings (struct cp_private *cp)
1107{
1108 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1109 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1110
1111 cp->rx_tail = 0;
1112 cp->tx_head = cp->tx_tail = 0;
1113
1114 return cp_refill_rx (cp);
1115}
1116
1117static int cp_alloc_rings (struct cp_private *cp)
1118{
1119 void *mem;
1120
1121 mem = pci_alloc_consistent(cp->pdev, CP_RING_BYTES, &cp->ring_dma);
1122 if (!mem)
1123 return -ENOMEM;
1124
1125 cp->rx_ring = mem;
1126 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1127
1128 mem += (CP_RING_BYTES - CP_STATS_SIZE);
1129 cp->nic_stats = mem;
1130 cp->nic_stats_dma = cp->ring_dma + (CP_RING_BYTES - CP_STATS_SIZE);
1131
1132 return cp_init_rings(cp);
1133}
1134
1135static void cp_clean_rings (struct cp_private *cp)
1136{
1137 unsigned i;
1138
1139 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1140 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1141
1142 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1143 if (cp->rx_skb[i].skb) {
1144 pci_unmap_single(cp->pdev, cp->rx_skb[i].mapping,
1145 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1146 dev_kfree_skb(cp->rx_skb[i].skb);
1147 }
1148 }
1149
1150 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1151 if (cp->tx_skb[i].skb) {
1152 struct sk_buff *skb = cp->tx_skb[i].skb;
1153 pci_unmap_single(cp->pdev, cp->tx_skb[i].mapping,
1154 skb->len, PCI_DMA_TODEVICE);
1155 dev_kfree_skb(skb);
1156 cp->net_stats.tx_dropped++;
1157 }
1158 }
1159
1160 memset(&cp->rx_skb, 0, sizeof(struct ring_info) * CP_RX_RING_SIZE);
1161 memset(&cp->tx_skb, 0, sizeof(struct ring_info) * CP_TX_RING_SIZE);
1162}
1163
1164static void cp_free_rings (struct cp_private *cp)
1165{
1166 cp_clean_rings(cp);
1167 pci_free_consistent(cp->pdev, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1168 cp->rx_ring = NULL;
1169 cp->tx_ring = NULL;
1170 cp->nic_stats = NULL;
1171}
1172
1173static int cp_open (struct net_device *dev)
1174{
1175 struct cp_private *cp = netdev_priv(dev);
1176 int rc;
1177
1178 if (netif_msg_ifup(cp))
1179 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1180
1181 rc = cp_alloc_rings(cp);
1182 if (rc)
1183 return rc;
1184
1185 cp_init_hw(cp);
1186
1187 rc = request_irq(dev->irq, cp_interrupt, SA_SHIRQ, dev->name, dev);
1188 if (rc)
1189 goto err_out_hw;
1190
1191 netif_carrier_off(dev);
1192 mii_check_media(&cp->mii_if, netif_msg_link(cp), TRUE);
1193 netif_start_queue(dev);
1194
1195 return 0;
1196
1197err_out_hw:
1198 cp_stop_hw(cp);
1199 cp_free_rings(cp);
1200 return rc;
1201}
1202
1203static int cp_close (struct net_device *dev)
1204{
1205 struct cp_private *cp = netdev_priv(dev);
1206 unsigned long flags;
1207
1208 if (netif_msg_ifdown(cp))
1209 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1210
1211 spin_lock_irqsave(&cp->lock, flags);
1212
1213 netif_stop_queue(dev);
1214 netif_carrier_off(dev);
1215
1216 cp_stop_hw(cp);
1217
1218 spin_unlock_irqrestore(&cp->lock, flags);
1219
1220 synchronize_irq(dev->irq);
1221 free_irq(dev->irq, dev);
1222
1223 cp_free_rings(cp);
1224 return 0;
1225}
1226
1227#ifdef BROKEN
1228static int cp_change_mtu(struct net_device *dev, int new_mtu)
1229{
1230 struct cp_private *cp = netdev_priv(dev);
1231 int rc;
1232 unsigned long flags;
1233
1234 /* check for invalid MTU, according to hardware limits */
1235 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1236 return -EINVAL;
1237
1238 /* if network interface not up, no need for complexity */
1239 if (!netif_running(dev)) {
1240 dev->mtu = new_mtu;
1241 cp_set_rxbufsize(cp); /* set new rx buf size */
1242 return 0;
1243 }
1244
1245 spin_lock_irqsave(&cp->lock, flags);
1246
1247 cp_stop_hw(cp); /* stop h/w and free rings */
1248 cp_clean_rings(cp);
1249
1250 dev->mtu = new_mtu;
1251 cp_set_rxbufsize(cp); /* set new rx buf size */
1252
1253 rc = cp_init_rings(cp); /* realloc and restart h/w */
1254 cp_start_hw(cp);
1255
1256 spin_unlock_irqrestore(&cp->lock, flags);
1257
1258 return rc;
1259}
1260#endif /* BROKEN */
1261
1262static char mii_2_8139_map[8] = {
1263 BasicModeCtrl,
1264 BasicModeStatus,
1265 0,
1266 0,
1267 NWayAdvert,
1268 NWayLPAR,
1269 NWayExpansion,
1270 0
1271};
1272
1273static int mdio_read(struct net_device *dev, int phy_id, int location)
1274{
1275 struct cp_private *cp = netdev_priv(dev);
1276
1277 return location < 8 && mii_2_8139_map[location] ?
1278 readw(cp->regs + mii_2_8139_map[location]) : 0;
1279}
1280
1281
1282static void mdio_write(struct net_device *dev, int phy_id, int location,
1283 int value)
1284{
1285 struct cp_private *cp = netdev_priv(dev);
1286
1287 if (location == 0) {
1288 cpw8(Cfg9346, Cfg9346_Unlock);
1289 cpw16(BasicModeCtrl, value);
1290 cpw8(Cfg9346, Cfg9346_Lock);
1291 } else if (location < 8 && mii_2_8139_map[location])
1292 cpw16(mii_2_8139_map[location], value);
1293}
1294
1295/* Set the ethtool Wake-on-LAN settings */
1296static int netdev_set_wol (struct cp_private *cp,
1297 const struct ethtool_wolinfo *wol)
1298{
1299 u8 options;
1300
1301 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1302 /* If WOL is being disabled, no need for complexity */
1303 if (wol->wolopts) {
1304 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1305 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1306 }
1307
1308 cpw8 (Cfg9346, Cfg9346_Unlock);
1309 cpw8 (Config3, options);
1310 cpw8 (Cfg9346, Cfg9346_Lock);
1311
1312 options = 0; /* Paranoia setting */
1313 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1314 /* If WOL is being disabled, no need for complexity */
1315 if (wol->wolopts) {
1316 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1317 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1318 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1319 }
1320
1321 cpw8 (Config5, options);
1322
1323 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1324
1325 return 0;
1326}
1327
1328/* Get the ethtool Wake-on-LAN settings */
1329static void netdev_get_wol (struct cp_private *cp,
1330 struct ethtool_wolinfo *wol)
1331{
1332 u8 options;
1333
1334 wol->wolopts = 0; /* Start from scratch */
1335 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1336 WAKE_MCAST | WAKE_UCAST;
1337 /* We don't need to go on if WOL is disabled */
1338 if (!cp->wol_enabled) return;
1339
1340 options = cpr8 (Config3);
1341 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1342 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1343
1344 options = 0; /* Paranoia setting */
1345 options = cpr8 (Config5);
1346 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1347 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1348 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1349}
1350
1351static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1352{
1353 struct cp_private *cp = netdev_priv(dev);
1354
1355 strcpy (info->driver, DRV_NAME);
1356 strcpy (info->version, DRV_VERSION);
1357 strcpy (info->bus_info, pci_name(cp->pdev));
1358}
1359
1360static int cp_get_regs_len(struct net_device *dev)
1361{
1362 return CP_REGS_SIZE;
1363}
1364
1365static int cp_get_stats_count (struct net_device *dev)
1366{
1367 return CP_NUM_STATS;
1368}
1369
1370static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1371{
1372 struct cp_private *cp = netdev_priv(dev);
1373 int rc;
1374 unsigned long flags;
1375
1376 spin_lock_irqsave(&cp->lock, flags);
1377 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1378 spin_unlock_irqrestore(&cp->lock, flags);
1379
1380 return rc;
1381}
1382
1383static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1384{
1385 struct cp_private *cp = netdev_priv(dev);
1386 int rc;
1387 unsigned long flags;
1388
1389 spin_lock_irqsave(&cp->lock, flags);
1390 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1391 spin_unlock_irqrestore(&cp->lock, flags);
1392
1393 return rc;
1394}
1395
1396static int cp_nway_reset(struct net_device *dev)
1397{
1398 struct cp_private *cp = netdev_priv(dev);
1399 return mii_nway_restart(&cp->mii_if);
1400}
1401
1402static u32 cp_get_msglevel(struct net_device *dev)
1403{
1404 struct cp_private *cp = netdev_priv(dev);
1405 return cp->msg_enable;
1406}
1407
1408static void cp_set_msglevel(struct net_device *dev, u32 value)
1409{
1410 struct cp_private *cp = netdev_priv(dev);
1411 cp->msg_enable = value;
1412}
1413
1414static u32 cp_get_rx_csum(struct net_device *dev)
1415{
1416 struct cp_private *cp = netdev_priv(dev);
1417 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1418}
1419
1420static int cp_set_rx_csum(struct net_device *dev, u32 data)
1421{
1422 struct cp_private *cp = netdev_priv(dev);
1423 u16 cmd = cp->cpcmd, newcmd;
1424
1425 newcmd = cmd;
1426
1427 if (data)
1428 newcmd |= RxChkSum;
1429 else
1430 newcmd &= ~RxChkSum;
1431
1432 if (newcmd != cmd) {
1433 unsigned long flags;
1434
1435 spin_lock_irqsave(&cp->lock, flags);
1436 cp->cpcmd = newcmd;
1437 cpw16_f(CpCmd, newcmd);
1438 spin_unlock_irqrestore(&cp->lock, flags);
1439 }
1440
1441 return 0;
1442}
1443
1444static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1445 void *p)
1446{
1447 struct cp_private *cp = netdev_priv(dev);
1448 unsigned long flags;
1449
1450 if (regs->len < CP_REGS_SIZE)
1451 return /* -EINVAL */;
1452
1453 regs->version = CP_REGS_VER;
1454
1455 spin_lock_irqsave(&cp->lock, flags);
1456 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1457 spin_unlock_irqrestore(&cp->lock, flags);
1458}
1459
1460static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1461{
1462 struct cp_private *cp = netdev_priv(dev);
1463 unsigned long flags;
1464
1465 spin_lock_irqsave (&cp->lock, flags);
1466 netdev_get_wol (cp, wol);
1467 spin_unlock_irqrestore (&cp->lock, flags);
1468}
1469
1470static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1471{
1472 struct cp_private *cp = netdev_priv(dev);
1473 unsigned long flags;
1474 int rc;
1475
1476 spin_lock_irqsave (&cp->lock, flags);
1477 rc = netdev_set_wol (cp, wol);
1478 spin_unlock_irqrestore (&cp->lock, flags);
1479
1480 return rc;
1481}
1482
1483static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1484{
1485 switch (stringset) {
1486 case ETH_SS_STATS:
1487 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1488 break;
1489 default:
1490 BUG();
1491 break;
1492 }
1493}
1494
1495static void cp_get_ethtool_stats (struct net_device *dev,
1496 struct ethtool_stats *estats, u64 *tmp_stats)
1497{
1498 struct cp_private *cp = netdev_priv(dev);
1499 unsigned int work = 100;
1500 int i;
1501
1502 /* begin NIC statistics dump */
1503 cpw32(StatsAddr + 4, (cp->nic_stats_dma >> 16) >> 16);
1504 cpw32(StatsAddr, (cp->nic_stats_dma & 0xffffffff) | DumpStats);
1505 cpr32(StatsAddr);
1506
1507 while (work-- > 0) {
1508 if ((cpr32(StatsAddr) & DumpStats) == 0)
1509 break;
1510 cpu_relax();
1511 }
1512
1513 if (cpr32(StatsAddr) & DumpStats)
1514 return /* -EIO */;
1515
1516 i = 0;
1517 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->tx_ok);
1518 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->rx_ok);
1519 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->tx_err);
1520 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->rx_err);
1521 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->rx_fifo);
1522 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->frame_align);
1523 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->tx_ok_1col);
1524 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->tx_ok_mcol);
1525 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->rx_ok_phys);
1526 tmp_stats[i++] = le64_to_cpu(cp->nic_stats->rx_ok_bcast);
1527 tmp_stats[i++] = le32_to_cpu(cp->nic_stats->rx_ok_mcast);
1528 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->tx_abort);
1529 tmp_stats[i++] = le16_to_cpu(cp->nic_stats->tx_underrun);
1530 tmp_stats[i++] = cp->cp_stats.rx_frags;
1531 if (i != CP_NUM_STATS)
1532 BUG();
1533}
1534
1535static struct ethtool_ops cp_ethtool_ops = {
1536 .get_drvinfo = cp_get_drvinfo,
1537 .get_regs_len = cp_get_regs_len,
1538 .get_stats_count = cp_get_stats_count,
1539 .get_settings = cp_get_settings,
1540 .set_settings = cp_set_settings,
1541 .nway_reset = cp_nway_reset,
1542 .get_link = ethtool_op_get_link,
1543 .get_msglevel = cp_get_msglevel,
1544 .set_msglevel = cp_set_msglevel,
1545 .get_rx_csum = cp_get_rx_csum,
1546 .set_rx_csum = cp_set_rx_csum,
1547 .get_tx_csum = ethtool_op_get_tx_csum,
1548 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1549 .get_sg = ethtool_op_get_sg,
1550 .set_sg = ethtool_op_set_sg,
fcec3456
JG		 1551 .get_tso = ethtool_op_get_tso,
1552 .set_tso = ethtool_op_set_tso,
1da177e4
LT		 1553 .get_regs = cp_get_regs,
1554 .get_wol = cp_get_wol,
1555 .set_wol = cp_set_wol,
1556 .get_strings = cp_get_strings,
1557 .get_ethtool_stats = cp_get_ethtool_stats,
1558};
1559
1560static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1561{
1562 struct cp_private *cp = netdev_priv(dev);
1563 int rc;
1564 unsigned long flags;
1565
1566 if (!netif_running(dev))
1567 return -EINVAL;
1568
1569 spin_lock_irqsave(&cp->lock, flags);
1570 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1571 spin_unlock_irqrestore(&cp->lock, flags);
1572 return rc;
1573}
1574
1575/* Serial EEPROM section. */
1576
1577/* EEPROM_Ctrl bits. */
1578#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1579#define EE_CS 0x08 /* EEPROM chip select. */
1580#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1581#define EE_WRITE_0 0x00
1582#define EE_WRITE_1 0x02
1583#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1584#define EE_ENB (0x80 | EE_CS)
1585
1586/* Delay between EEPROM clock transitions.
1587 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1588 */
1589
1590#define eeprom_delay() readl(ee_addr)
1591
1592/* The EEPROM commands include the alway-set leading bit. */
1593#define EE_WRITE_CMD (5)
1594#define EE_READ_CMD (6)
1595#define EE_ERASE_CMD (7)
1596
1597static int read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1598{
1599 int i;
1600 unsigned retval = 0;
1601 void __iomem *ee_addr = ioaddr + Cfg9346;
1602 int read_cmd = location | (EE_READ_CMD << addr_len);
1603
1604 writeb (EE_ENB & ~EE_CS, ee_addr);
1605 writeb (EE_ENB, ee_addr);
1606 eeprom_delay ();
1607
1608 /* Shift the read command bits out. */
1609 for (i = 4 + addr_len; i >= 0; i--) {
1610 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1611 writeb (EE_ENB | dataval, ee_addr);
1612 eeprom_delay ();
1613 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1614 eeprom_delay ();
1615 }
1616 writeb (EE_ENB, ee_addr);
1617 eeprom_delay ();
1618
1619 for (i = 16; i > 0; i--) {
1620 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1621 eeprom_delay ();
1622 retval =
1623 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1624 0);
1625 writeb (EE_ENB, ee_addr);
1626 eeprom_delay ();
1627 }
1628
1629 /* Terminate the EEPROM access. */
1630 writeb (~EE_CS, ee_addr);
1631 eeprom_delay ();
1632
1633 return retval;
1634}
1635
1636/* Put the board into D3cold state and wait for WakeUp signal */
1637static void cp_set_d3_state (struct cp_private *cp)
1638{
1639 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1640 pci_set_power_state (cp->pdev, PCI_D3hot);
1641}
1642
1643static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1644{
1645 struct net_device *dev;
1646 struct cp_private *cp;
1647 int rc;
1648 void __iomem *regs;
1649 long pciaddr;
1650 unsigned int addr_len, i, pci_using_dac;
1651 u8 pci_rev;
1652
1653#ifndef MODULE
1654 static int version_printed;
1655 if (version_printed++ == 0)
1656 printk("%s", version);
1657#endif
1658
1659 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
1660
1661 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1662 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev < 0x20) {
1663 printk(KERN_ERR PFX "pci dev %s (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
1664 pci_name(pdev), pdev->vendor, pdev->device, pci_rev);
1665 printk(KERN_ERR PFX "Try the \"8139too\" driver instead.\n");
1666 return -ENODEV;
1667 }
1668
1669 dev = alloc_etherdev(sizeof(struct cp_private));
1670 if (!dev)
1671 return -ENOMEM;
1672 SET_MODULE_OWNER(dev);
1673 SET_NETDEV_DEV(dev, &pdev->dev);
1674
1675 cp = netdev_priv(dev);
1676 cp->pdev = pdev;
1677 cp->dev = dev;
1678 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1679 spin_lock_init (&cp->lock);
1680 cp->mii_if.dev = dev;
1681 cp->mii_if.mdio_read = mdio_read;
1682 cp->mii_if.mdio_write = mdio_write;
1683 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1684 cp->mii_if.phy_id_mask = 0x1f;
1685 cp->mii_if.reg_num_mask = 0x1f;
1686 cp_set_rxbufsize(cp);
1687
1688 rc = pci_enable_device(pdev);
1689 if (rc)
1690 goto err_out_free;
1691
1692 rc = pci_set_mwi(pdev);
1693 if (rc)
1694 goto err_out_disable;
1695
1696 rc = pci_request_regions(pdev, DRV_NAME);
1697 if (rc)
1698 goto err_out_mwi;
1699
1700 pciaddr = pci_resource_start(pdev, 1);
1701 if (!pciaddr) {
1702 rc = -EIO;
1703 printk(KERN_ERR PFX "no MMIO resource for pci dev %s\n",
1704 pci_name(pdev));
1705 goto err_out_res;
1706 }
1707 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1708 rc = -EIO;
1709 printk(KERN_ERR PFX "MMIO resource (%lx) too small on pci dev %s\n",
1710 pci_resource_len(pdev, 1), pci_name(pdev));
1711 goto err_out_res;
1712 }
1713
1714 /* Configure DMA attributes. */
1715 if ((sizeof(dma_addr_t) > 4) &&
1716 !pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL) &&
1717 !pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) {
1718 pci_using_dac = 1;
1719 } else {
1720 pci_using_dac = 0;
1721
1722 rc = pci_set_dma_mask(pdev, 0xffffffffULL);
1723 if (rc) {
1724 printk(KERN_ERR PFX "No usable DMA configuration, "
1725 "aborting.\n");
1726 goto err_out_res;
1727 }
1728 rc = pci_set_consistent_dma_mask(pdev, 0xffffffffULL);
1729 if (rc) {
1730 printk(KERN_ERR PFX "No usable consistent DMA configuration, "
1731 "aborting.\n");
1732 goto err_out_res;
1733 }
1734 }
1735
1736 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1737 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1738
1739 regs = ioremap(pciaddr, CP_REGS_SIZE);
1740 if (!regs) {
1741 rc = -EIO;
1742 printk(KERN_ERR PFX "Cannot map PCI MMIO (%lx@%lx) on pci dev %s\n",
1743 pci_resource_len(pdev, 1), pciaddr, pci_name(pdev));
1744 goto err_out_res;
1745 }
1746 dev->base_addr = (unsigned long) regs;
1747 cp->regs = regs;
1748
1749 cp_stop_hw(cp);
1750
1751 /* read MAC address from EEPROM */
1752 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1753 for (i = 0; i < 3; i++)
1754 ((u16 *) (dev->dev_addr))[i] =
1755 le16_to_cpu (read_eeprom (regs, i + 7, addr_len));
1756
1757 dev->open = cp_open;
1758 dev->stop = cp_close;
1759 dev->set_multicast_list = cp_set_rx_mode;
1760 dev->hard_start_xmit = cp_start_xmit;
1761 dev->get_stats = cp_get_stats;
1762 dev->do_ioctl = cp_ioctl;
1763 dev->poll = cp_rx_poll;
1764 dev->weight = 16; /* arbitrary? from NAPI_HOWTO.txt. */
1765#ifdef BROKEN
1766 dev->change_mtu = cp_change_mtu;
1767#endif
1768 dev->ethtool_ops = &cp_ethtool_ops;
1769#if 0
1770 dev->tx_timeout = cp_tx_timeout;
1771 dev->watchdog_timeo = TX_TIMEOUT;
1772#endif
1773
1774#if CP_VLAN_TAG_USED
1775 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1776 dev->vlan_rx_register = cp_vlan_rx_register;
1777 dev->vlan_rx_kill_vid = cp_vlan_rx_kill_vid;
1778#endif
1779
1780 if (pci_using_dac)
1781 dev->features |= NETIF_F_HIGHDMA;
1782
fcec3456
JG		 1783#if 0 /* disabled by default until verified */
1784 dev->features |= NETIF_F_TSO;
1785#endif
1786
1da177e4
LT		 1787 dev->irq = pdev->irq;
1788
1789 rc = register_netdev(dev);
1790 if (rc)
1791 goto err_out_iomap;
1792
1793 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
1794 "%02x:%02x:%02x:%02x:%02x:%02x, "
1795 "IRQ %d\n",
1796 dev->name,
1797 dev->base_addr,
1798 dev->dev_addr[0], dev->dev_addr[1],
1799 dev->dev_addr[2], dev->dev_addr[3],
1800 dev->dev_addr[4], dev->dev_addr[5],
1801 dev->irq);
1802
1803 pci_set_drvdata(pdev, dev);
1804
1805 /* enable busmastering and memory-write-invalidate */
1806 pci_set_master(pdev);
1807
1808 if (cp->wol_enabled) cp_set_d3_state (cp);
1809
1810 return 0;
1811
1812err_out_iomap:
1813 iounmap(regs);
1814err_out_res:
1815 pci_release_regions(pdev);
1816err_out_mwi:
1817 pci_clear_mwi(pdev);
1818err_out_disable:
1819 pci_disable_device(pdev);
1820err_out_free:
1821 free_netdev(dev);
1822 return rc;
1823}
1824
1825static void cp_remove_one (struct pci_dev *pdev)
1826{
1827 struct net_device *dev = pci_get_drvdata(pdev);
1828 struct cp_private *cp = netdev_priv(dev);
1829
1830 if (!dev)
1831 BUG();
1832 unregister_netdev(dev);
1833 iounmap(cp->regs);
1834 if (cp->wol_enabled) pci_set_power_state (pdev, PCI_D0);
1835 pci_release_regions(pdev);
1836 pci_clear_mwi(pdev);
1837 pci_disable_device(pdev);
1838 pci_set_drvdata(pdev, NULL);
1839 free_netdev(dev);
1840}
1841
1842#ifdef CONFIG_PM
05adc3b7 1843static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 1844{
1845 struct net_device *dev;
1846 struct cp_private *cp;
1847 unsigned long flags;
1848
1849 dev = pci_get_drvdata (pdev);
1850 cp = netdev_priv(dev);
1851
1852 if (!dev || !netif_running (dev)) return 0;
1853
1854 netif_device_detach (dev);
1855 netif_stop_queue (dev);
1856
1857 spin_lock_irqsave (&cp->lock, flags);
1858
1859 /* Disable Rx and Tx */
1860 cpw16 (IntrMask, 0);
1861 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
1862
1863 spin_unlock_irqrestore (&cp->lock, flags);
1864
1865 if (cp->pdev && cp->wol_enabled) {
1866 pci_save_state (cp->pdev);
1867 cp_set_d3_state (cp);
1868 }
1869
1870 return 0;
1871}
1872
1873static int cp_resume (struct pci_dev *pdev)
1874{
1875 struct net_device *dev;
1876 struct cp_private *cp;
1877
1878 dev = pci_get_drvdata (pdev);
1879 cp = netdev_priv(dev);
1880
1881 netif_device_attach (dev);
1882
1883 if (cp->pdev && cp->wol_enabled) {
1884 pci_set_power_state (cp->pdev, PCI_D0);
1885 pci_restore_state (cp->pdev);
1886 }
1887
1888 cp_init_hw (cp);
1889 netif_start_queue (dev);
1890
1891 return 0;
1892}
1893#endif /* CONFIG_PM */
1894
1895static struct pci_driver cp_driver = {
1896 .name = DRV_NAME,
1897 .id_table = cp_pci_tbl,
1898 .probe = cp_init_one,
1899 .remove = cp_remove_one,
1900#ifdef CONFIG_PM
1901 .resume = cp_resume,
1902 .suspend = cp_suspend,
1903#endif
1904};
1905
1906static int __init cp_init (void)
1907{
1908#ifdef MODULE
1909 printk("%s", version);
1910#endif
1911 return pci_module_init (&cp_driver);
1912}
1913
1914static void __exit cp_exit (void)
1915{
1916 pci_unregister_driver (&cp_driver);
1917}
1918
1919module_init(cp_init);
1920module_exit(cp_exit);
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