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1da177e4 LT |
1 | /* |
2 | * linux/drivers/acorn/net/ether3.h | |
3 | * | |
4 | * Copyright (C) 1995-2000 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * network driver for Acorn/ANT Ether3 cards | |
11 | */ | |
12 | ||
13 | #ifndef _LINUX_ether3_H | |
14 | #define _LINUX_ether3_H | |
15 | ||
16 | /* use 0 for production, 1 for verification, >2 for debug. debug flags: */ | |
17 | #define DEBUG_TX 2 | |
18 | #define DEBUG_RX 4 | |
19 | #define DEBUG_INT 8 | |
20 | #define DEBUG_IC 16 | |
21 | #ifndef NET_DEBUG | |
22 | #define NET_DEBUG 0 | |
23 | #endif | |
24 | ||
25 | #define priv(dev) ((struct dev_priv *)netdev_priv(dev)) | |
26 | ||
27 | /* Command register definitions & bits */ | |
28 | #define REG_COMMAND (priv(dev)->seeq + 0x0000) | |
29 | #define CMD_ENINTDMA 0x0001 | |
30 | #define CMD_ENINTRX 0x0002 | |
31 | #define CMD_ENINTTX 0x0004 | |
32 | #define CMD_ENINTBUFWIN 0x0008 | |
33 | #define CMD_ACKINTDMA 0x0010 | |
34 | #define CMD_ACKINTRX 0x0020 | |
35 | #define CMD_ACKINTTX 0x0040 | |
36 | #define CMD_ACKINTBUFWIN 0x0080 | |
37 | #define CMD_DMAON 0x0100 | |
38 | #define CMD_RXON 0x0200 | |
39 | #define CMD_TXON 0x0400 | |
40 | #define CMD_DMAOFF 0x0800 | |
41 | #define CMD_RXOFF 0x1000 | |
42 | #define CMD_TXOFF 0x2000 | |
43 | #define CMD_FIFOREAD 0x4000 | |
44 | #define CMD_FIFOWRITE 0x8000 | |
45 | ||
46 | /* status register */ | |
47 | #define REG_STATUS (priv(dev)->seeq + 0x0000) | |
48 | #define STAT_ENINTSTAT 0x0001 | |
49 | #define STAT_ENINTRX 0x0002 | |
50 | #define STAT_ENINTTX 0x0004 | |
51 | #define STAT_ENINTBUFWIN 0x0008 | |
52 | #define STAT_INTDMA 0x0010 | |
53 | #define STAT_INTRX 0x0020 | |
54 | #define STAT_INTTX 0x0040 | |
55 | #define STAT_INTBUFWIN 0x0080 | |
56 | #define STAT_DMAON 0x0100 | |
57 | #define STAT_RXON 0x0200 | |
58 | #define STAT_TXON 0x0400 | |
59 | #define STAT_FIFOFULL 0x2000 | |
60 | #define STAT_FIFOEMPTY 0x4000 | |
61 | #define STAT_FIFODIR 0x8000 | |
62 | ||
63 | /* configuration register 1 */ | |
64 | #define REG_CONFIG1 (priv(dev)->seeq + 0x0040) | |
65 | #define CFG1_BUFSELSTAT0 0x0000 | |
66 | #define CFG1_BUFSELSTAT1 0x0001 | |
67 | #define CFG1_BUFSELSTAT2 0x0002 | |
68 | #define CFG1_BUFSELSTAT3 0x0003 | |
69 | #define CFG1_BUFSELSTAT4 0x0004 | |
70 | #define CFG1_BUFSELSTAT5 0x0005 | |
71 | #define CFG1_ADDRPROM 0x0006 | |
72 | #define CFG1_TRANSEND 0x0007 | |
73 | #define CFG1_LOCBUFMEM 0x0008 | |
74 | #define CFG1_INTVECTOR 0x0009 | |
75 | #define CFG1_RECVSPECONLY 0x0000 | |
76 | #define CFG1_RECVSPECBROAD 0x4000 | |
77 | #define CFG1_RECVSPECBRMULTI 0x8000 | |
78 | #define CFG1_RECVPROMISC 0xC000 | |
79 | ||
80 | /* The following aren't in 8004 */ | |
81 | #define CFG1_DMABURSTCONT 0x0000 | |
82 | #define CFG1_DMABURST800NS 0x0010 | |
83 | #define CFG1_DMABURST1600NS 0x0020 | |
84 | #define CFG1_DMABURST3200NS 0x0030 | |
85 | #define CFG1_DMABURST1 0x0000 | |
86 | #define CFG1_DMABURST4 0x0040 | |
87 | #define CFG1_DMABURST8 0x0080 | |
88 | #define CFG1_DMABURST16 0x00C0 | |
89 | #define CFG1_RECVCOMPSTAT0 0x0100 | |
90 | #define CFG1_RECVCOMPSTAT1 0x0200 | |
91 | #define CFG1_RECVCOMPSTAT2 0x0400 | |
92 | #define CFG1_RECVCOMPSTAT3 0x0800 | |
93 | #define CFG1_RECVCOMPSTAT4 0x1000 | |
94 | #define CFG1_RECVCOMPSTAT5 0x2000 | |
95 | ||
96 | /* configuration register 2 */ | |
97 | #define REG_CONFIG2 (priv(dev)->seeq + 0x0080) | |
98 | #define CFG2_BYTESWAP 0x0001 | |
99 | #define CFG2_ERRENCRC 0x0008 | |
100 | #define CFG2_ERRENDRIBBLE 0x0010 | |
101 | #define CFG2_ERRSHORTFRAME 0x0020 | |
102 | #define CFG2_SLOTSELECT 0x0040 | |
103 | #define CFG2_PREAMSELECT 0x0080 | |
104 | #define CFG2_ADDRLENGTH 0x0100 | |
105 | #define CFG2_RECVCRC 0x0200 | |
106 | #define CFG2_XMITNOCRC 0x0400 | |
107 | #define CFG2_LOOPBACK 0x0800 | |
108 | #define CFG2_CTRLO 0x1000 | |
109 | #define CFG2_RESET 0x8000 | |
110 | ||
111 | #define REG_RECVEND (priv(dev)->seeq + 0x00c0) | |
112 | ||
113 | #define REG_BUFWIN (priv(dev)->seeq + 0x0100) | |
114 | ||
115 | #define REG_RECVPTR (priv(dev)->seeq + 0x0140) | |
116 | ||
117 | #define REG_TRANSMITPTR (priv(dev)->seeq + 0x0180) | |
118 | ||
119 | #define REG_DMAADDR (priv(dev)->seeq + 0x01c0) | |
120 | ||
121 | /* | |
122 | * Cards transmit/receive headers | |
123 | */ | |
124 | #define TX_NEXT (0xffff) | |
125 | #define TXHDR_ENBABBLEINT (1 << 16) | |
126 | #define TXHDR_ENCOLLISIONINT (1 << 17) | |
127 | #define TXHDR_EN16COLLISION (1 << 18) | |
128 | #define TXHDR_ENSUCCESS (1 << 19) | |
129 | #define TXHDR_DATAFOLLOWS (1 << 21) | |
130 | #define TXHDR_CHAINCONTINUE (1 << 22) | |
131 | #define TXHDR_TRANSMIT (1 << 23) | |
132 | #define TXSTAT_BABBLED (1 << 24) | |
133 | #define TXSTAT_COLLISION (1 << 25) | |
134 | #define TXSTAT_16COLLISIONS (1 << 26) | |
135 | #define TXSTAT_DONE (1 << 31) | |
136 | ||
137 | #define RX_NEXT (0xffff) | |
138 | #define RXHDR_CHAINCONTINUE (1 << 6) | |
139 | #define RXHDR_RECEIVE (1 << 7) | |
140 | #define RXSTAT_OVERSIZE (1 << 8) | |
141 | #define RXSTAT_CRCERROR (1 << 9) | |
142 | #define RXSTAT_DRIBBLEERROR (1 << 10) | |
143 | #define RXSTAT_SHORTPACKET (1 << 11) | |
144 | #define RXSTAT_DONE (1 << 15) | |
145 | ||
146 | ||
147 | #define TX_START 0x0000 | |
148 | #define TX_END 0x6000 | |
149 | #define RX_START 0x6000 | |
150 | #define RX_LEN 0xA000 | |
151 | #define RX_END 0x10000 | |
152 | /* must be a power of 2 and greater than MAX_TX_BUFFERED */ | |
153 | #define MAX_TXED 16 | |
154 | #define MAX_TX_BUFFERED 10 | |
155 | ||
156 | struct dev_priv { | |
157 | void __iomem *base; | |
158 | void __iomem *seeq; | |
159 | struct { | |
160 | unsigned int command; | |
161 | unsigned int config1; | |
162 | unsigned int config2; | |
163 | } regs; | |
164 | unsigned char tx_head; /* buffer nr to insert next packet */ | |
165 | unsigned char tx_tail; /* buffer nr of transmitting packet */ | |
166 | unsigned int rx_head; /* address to fetch next packet from */ | |
167 | struct net_device_stats stats; | |
168 | struct timer_list timer; | |
169 | int broken; /* 0 = ok, 1 = something went wrong */ | |
170 | }; | |
171 | ||
172 | struct ether3_data { | |
173 | const char name[8]; | |
174 | unsigned long base_offset; | |
175 | }; | |
176 | ||
177 | #endif |