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dac2f83f KH |
1 | /* |
2 | * Intel IXP4xx Ethernet driver for Linux | |
3 | * | |
4 | * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of version 2 of the GNU General Public License | |
8 | * as published by the Free Software Foundation. | |
9 | * | |
10 | * Ethernet port config (0x00 is not present on IXP42X): | |
11 | * | |
12 | * logical port 0x00 0x10 0x20 | |
13 | * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C) | |
14 | * physical PortId 2 0 1 | |
15 | * TX queue 23 24 25 | |
16 | * RX-free queue 26 27 28 | |
17 | * TX-done queue is always 31, per-port RX and TX-ready queues are configurable | |
18 | * | |
19 | * | |
20 | * Queue entries: | |
21 | * bits 0 -> 1 - NPE ID (RX and TX-done) | |
22 | * bits 0 -> 2 - priority (TX, per 802.1D) | |
23 | * bits 3 -> 4 - port ID (user-set?) | |
24 | * bits 5 -> 31 - physical descriptor address | |
25 | */ | |
26 | ||
27 | #include <linux/delay.h> | |
28 | #include <linux/dma-mapping.h> | |
29 | #include <linux/dmapool.h> | |
30 | #include <linux/etherdevice.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/kernel.h> | |
2098c18d | 33 | #include <linux/phy.h> |
dac2f83f | 34 | #include <linux/platform_device.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
a09e64fb RK |
36 | #include <mach/npe.h> |
37 | #include <mach/qmgr.h> | |
dac2f83f | 38 | |
dac2f83f KH |
39 | #define DEBUG_DESC 0 |
40 | #define DEBUG_RX 0 | |
41 | #define DEBUG_TX 0 | |
42 | #define DEBUG_PKT_BYTES 0 | |
43 | #define DEBUG_MDIO 0 | |
44 | #define DEBUG_CLOSE 0 | |
45 | ||
46 | #define DRV_NAME "ixp4xx_eth" | |
47 | ||
48 | #define MAX_NPES 3 | |
49 | ||
50 | #define RX_DESCS 64 /* also length of all RX queues */ | |
51 | #define TX_DESCS 16 /* also length of all TX queues */ | |
52 | #define TXDONE_QUEUE_LEN 64 /* dwords */ | |
53 | ||
54 | #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) | |
55 | #define REGS_SIZE 0x1000 | |
56 | #define MAX_MRU 1536 /* 0x600 */ | |
57 | #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4) | |
58 | ||
59 | #define NAPI_WEIGHT 16 | |
60 | #define MDIO_INTERVAL (3 * HZ) | |
61 | #define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */ | |
dac2f83f KH |
62 | #define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */ |
63 | ||
64 | #define NPE_ID(port_id) ((port_id) >> 4) | |
65 | #define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3) | |
66 | #define TX_QUEUE(port_id) (NPE_ID(port_id) + 23) | |
67 | #define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26) | |
68 | #define TXDONE_QUEUE 31 | |
69 | ||
70 | /* TX Control Registers */ | |
71 | #define TX_CNTRL0_TX_EN 0x01 | |
72 | #define TX_CNTRL0_HALFDUPLEX 0x02 | |
73 | #define TX_CNTRL0_RETRY 0x04 | |
74 | #define TX_CNTRL0_PAD_EN 0x08 | |
75 | #define TX_CNTRL0_APPEND_FCS 0x10 | |
76 | #define TX_CNTRL0_2DEFER 0x20 | |
77 | #define TX_CNTRL0_RMII 0x40 /* reduced MII */ | |
78 | #define TX_CNTRL1_RETRIES 0x0F /* 4 bits */ | |
79 | ||
80 | /* RX Control Registers */ | |
81 | #define RX_CNTRL0_RX_EN 0x01 | |
82 | #define RX_CNTRL0_PADSTRIP_EN 0x02 | |
83 | #define RX_CNTRL0_SEND_FCS 0x04 | |
84 | #define RX_CNTRL0_PAUSE_EN 0x08 | |
85 | #define RX_CNTRL0_LOOP_EN 0x10 | |
86 | #define RX_CNTRL0_ADDR_FLTR_EN 0x20 | |
87 | #define RX_CNTRL0_RX_RUNT_EN 0x40 | |
88 | #define RX_CNTRL0_BCAST_DIS 0x80 | |
89 | #define RX_CNTRL1_DEFER_EN 0x01 | |
90 | ||
91 | /* Core Control Register */ | |
92 | #define CORE_RESET 0x01 | |
93 | #define CORE_RX_FIFO_FLUSH 0x02 | |
94 | #define CORE_TX_FIFO_FLUSH 0x04 | |
95 | #define CORE_SEND_JAM 0x08 | |
96 | #define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */ | |
97 | ||
98 | #define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \ | |
99 | TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \ | |
100 | TX_CNTRL0_2DEFER) | |
101 | #define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN | |
102 | #define DEFAULT_CORE_CNTRL CORE_MDC_EN | |
103 | ||
104 | ||
105 | /* NPE message codes */ | |
106 | #define NPE_GETSTATUS 0x00 | |
107 | #define NPE_EDB_SETPORTADDRESS 0x01 | |
108 | #define NPE_EDB_GETMACADDRESSDATABASE 0x02 | |
109 | #define NPE_EDB_SETMACADDRESSSDATABASE 0x03 | |
110 | #define NPE_GETSTATS 0x04 | |
111 | #define NPE_RESETSTATS 0x05 | |
112 | #define NPE_SETMAXFRAMELENGTHS 0x06 | |
113 | #define NPE_VLAN_SETRXTAGMODE 0x07 | |
114 | #define NPE_VLAN_SETDEFAULTRXVID 0x08 | |
115 | #define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09 | |
116 | #define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A | |
117 | #define NPE_VLAN_SETRXQOSENTRY 0x0B | |
118 | #define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C | |
119 | #define NPE_STP_SETBLOCKINGSTATE 0x0D | |
120 | #define NPE_FW_SETFIREWALLMODE 0x0E | |
121 | #define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F | |
122 | #define NPE_PC_SETAPMACTABLE 0x11 | |
123 | #define NPE_SETLOOPBACK_MODE 0x12 | |
124 | #define NPE_PC_SETBSSIDTABLE 0x13 | |
125 | #define NPE_ADDRESS_FILTER_CONFIG 0x14 | |
126 | #define NPE_APPENDFCSCONFIG 0x15 | |
127 | #define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16 | |
128 | #define NPE_MAC_RECOVERY_START 0x17 | |
129 | ||
130 | ||
131 | #ifdef __ARMEB__ | |
132 | typedef struct sk_buff buffer_t; | |
133 | #define free_buffer dev_kfree_skb | |
134 | #define free_buffer_irq dev_kfree_skb_irq | |
135 | #else | |
136 | typedef void buffer_t; | |
137 | #define free_buffer kfree | |
138 | #define free_buffer_irq kfree | |
139 | #endif | |
140 | ||
141 | struct eth_regs { | |
142 | u32 tx_control[2], __res1[2]; /* 000 */ | |
143 | u32 rx_control[2], __res2[2]; /* 010 */ | |
144 | u32 random_seed, __res3[3]; /* 020 */ | |
145 | u32 partial_empty_threshold, __res4; /* 030 */ | |
146 | u32 partial_full_threshold, __res5; /* 038 */ | |
147 | u32 tx_start_bytes, __res6[3]; /* 040 */ | |
148 | u32 tx_deferral, rx_deferral, __res7[2];/* 050 */ | |
149 | u32 tx_2part_deferral[2], __res8[2]; /* 060 */ | |
150 | u32 slot_time, __res9[3]; /* 070 */ | |
151 | u32 mdio_command[4]; /* 080 */ | |
152 | u32 mdio_status[4]; /* 090 */ | |
153 | u32 mcast_mask[6], __res10[2]; /* 0A0 */ | |
154 | u32 mcast_addr[6], __res11[2]; /* 0C0 */ | |
155 | u32 int_clock_threshold, __res12[3]; /* 0E0 */ | |
156 | u32 hw_addr[6], __res13[61]; /* 0F0 */ | |
157 | u32 core_control; /* 1FC */ | |
158 | }; | |
159 | ||
160 | struct port { | |
161 | struct resource *mem_res; | |
162 | struct eth_regs __iomem *regs; | |
163 | struct npe *npe; | |
164 | struct net_device *netdev; | |
165 | struct napi_struct napi; | |
2098c18d | 166 | struct phy_device *phydev; |
dac2f83f KH |
167 | struct eth_plat_info *plat; |
168 | buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS]; | |
169 | struct desc *desc_tab; /* coherent */ | |
170 | u32 desc_tab_phys; | |
171 | int id; /* logical port ID */ | |
2098c18d | 172 | int speed, duplex; |
490b7722 | 173 | u8 firmware[4]; |
dac2f83f KH |
174 | }; |
175 | ||
176 | /* NPE message structure */ | |
177 | struct msg { | |
178 | #ifdef __ARMEB__ | |
179 | u8 cmd, eth_id, byte2, byte3; | |
180 | u8 byte4, byte5, byte6, byte7; | |
181 | #else | |
182 | u8 byte3, byte2, eth_id, cmd; | |
183 | u8 byte7, byte6, byte5, byte4; | |
184 | #endif | |
185 | }; | |
186 | ||
187 | /* Ethernet packet descriptor */ | |
188 | struct desc { | |
189 | u32 next; /* pointer to next buffer, unused */ | |
190 | ||
191 | #ifdef __ARMEB__ | |
192 | u16 buf_len; /* buffer length */ | |
193 | u16 pkt_len; /* packet length */ | |
194 | u32 data; /* pointer to data buffer in RAM */ | |
195 | u8 dest_id; | |
196 | u8 src_id; | |
197 | u16 flags; | |
198 | u8 qos; | |
199 | u8 padlen; | |
200 | u16 vlan_tci; | |
201 | #else | |
202 | u16 pkt_len; /* packet length */ | |
203 | u16 buf_len; /* buffer length */ | |
204 | u32 data; /* pointer to data buffer in RAM */ | |
205 | u16 flags; | |
206 | u8 src_id; | |
207 | u8 dest_id; | |
208 | u16 vlan_tci; | |
209 | u8 padlen; | |
210 | u8 qos; | |
211 | #endif | |
212 | ||
213 | #ifdef __ARMEB__ | |
214 | u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3; | |
215 | u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1; | |
216 | u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5; | |
217 | #else | |
218 | u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0; | |
219 | u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4; | |
220 | u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2; | |
221 | #endif | |
222 | }; | |
223 | ||
224 | ||
225 | #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \ | |
226 | (n) * sizeof(struct desc)) | |
227 | #define rx_desc_ptr(port, n) (&(port)->desc_tab[n]) | |
228 | ||
229 | #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \ | |
230 | ((n) + RX_DESCS) * sizeof(struct desc)) | |
231 | #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS]) | |
232 | ||
233 | #ifndef __ARMEB__ | |
234 | static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) | |
235 | { | |
236 | int i; | |
237 | for (i = 0; i < cnt; i++) | |
238 | dest[i] = swab32(src[i]); | |
239 | } | |
240 | #endif | |
241 | ||
242 | static spinlock_t mdio_lock; | |
243 | static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */ | |
2098c18d | 244 | struct mii_bus *mdio_bus; |
dac2f83f KH |
245 | static int ports_open; |
246 | static struct port *npe_port_tab[MAX_NPES]; | |
247 | static struct dma_pool *dma_pool; | |
248 | ||
249 | ||
2098c18d KH |
250 | static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location, |
251 | int write, u16 cmd) | |
dac2f83f KH |
252 | { |
253 | int cycles = 0; | |
254 | ||
255 | if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) { | |
2098c18d KH |
256 | printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name); |
257 | return -1; | |
dac2f83f KH |
258 | } |
259 | ||
260 | if (write) { | |
261 | __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]); | |
262 | __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]); | |
263 | } | |
264 | __raw_writel(((phy_id << 5) | location) & 0xFF, | |
265 | &mdio_regs->mdio_command[2]); | |
266 | __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */, | |
267 | &mdio_regs->mdio_command[3]); | |
268 | ||
269 | while ((cycles < MAX_MDIO_RETRIES) && | |
270 | (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) { | |
271 | udelay(1); | |
272 | cycles++; | |
273 | } | |
274 | ||
275 | if (cycles == MAX_MDIO_RETRIES) { | |
2098c18d KH |
276 | printk(KERN_ERR "%s #%i: MII write failed\n", bus->name, |
277 | phy_id); | |
278 | return -1; | |
dac2f83f KH |
279 | } |
280 | ||
281 | #if DEBUG_MDIO | |
2098c18d KH |
282 | printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name, |
283 | phy_id, write ? "write" : "read", cycles); | |
dac2f83f KH |
284 | #endif |
285 | ||
286 | if (write) | |
287 | return 0; | |
288 | ||
289 | if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) { | |
2098c18d KH |
290 | #if DEBUG_MDIO |
291 | printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name, | |
292 | phy_id); | |
293 | #endif | |
294 | return 0xFFFF; /* don't return error */ | |
dac2f83f KH |
295 | } |
296 | ||
297 | return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) | | |
2098c18d | 298 | ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8); |
dac2f83f KH |
299 | } |
300 | ||
2098c18d | 301 | static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location) |
dac2f83f KH |
302 | { |
303 | unsigned long flags; | |
2098c18d | 304 | int ret; |
dac2f83f KH |
305 | |
306 | spin_lock_irqsave(&mdio_lock, flags); | |
2098c18d | 307 | ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0); |
dac2f83f | 308 | spin_unlock_irqrestore(&mdio_lock, flags); |
2098c18d KH |
309 | #if DEBUG_MDIO |
310 | printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name, | |
311 | phy_id, location, ret); | |
312 | #endif | |
313 | return ret; | |
dac2f83f KH |
314 | } |
315 | ||
2098c18d KH |
316 | static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location, |
317 | u16 val) | |
dac2f83f KH |
318 | { |
319 | unsigned long flags; | |
2098c18d | 320 | int ret; |
dac2f83f KH |
321 | |
322 | spin_lock_irqsave(&mdio_lock, flags); | |
2098c18d | 323 | ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val); |
dac2f83f | 324 | spin_unlock_irqrestore(&mdio_lock, flags); |
2098c18d | 325 | #if DEBUG_MDIO |
8ae45a53 | 326 | printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n", |
2098c18d KH |
327 | bus->name, phy_id, location, val, ret); |
328 | #endif | |
329 | return ret; | |
dac2f83f KH |
330 | } |
331 | ||
2098c18d | 332 | static int ixp4xx_mdio_register(void) |
dac2f83f | 333 | { |
2098c18d | 334 | int err; |
dac2f83f | 335 | |
2098c18d KH |
336 | if (!(mdio_bus = mdiobus_alloc())) |
337 | return -ENOMEM; | |
dac2f83f | 338 | |
5ca328d2 KH |
339 | if (cpu_is_ixp43x()) { |
340 | /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */ | |
341 | if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEC_ETH)) | |
3ba8c792 | 342 | return -ENODEV; |
5ca328d2 KH |
343 | mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT; |
344 | } else { | |
345 | /* All MII PHY accesses use NPE-B Ethernet registers */ | |
346 | if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0)) | |
3ba8c792 | 347 | return -ENODEV; |
5ca328d2 KH |
348 | mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT; |
349 | } | |
dac2f83f | 350 | |
5ca328d2 KH |
351 | __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control); |
352 | spin_lock_init(&mdio_lock); | |
2098c18d KH |
353 | mdio_bus->name = "IXP4xx MII Bus"; |
354 | mdio_bus->read = &ixp4xx_mdio_read; | |
355 | mdio_bus->write = &ixp4xx_mdio_write; | |
356 | strcpy(mdio_bus->id, "0"); | |
dac2f83f | 357 | |
2098c18d KH |
358 | if ((err = mdiobus_register(mdio_bus))) |
359 | mdiobus_free(mdio_bus); | |
360 | return err; | |
dac2f83f KH |
361 | } |
362 | ||
2098c18d | 363 | static void ixp4xx_mdio_remove(void) |
dac2f83f | 364 | { |
2098c18d KH |
365 | mdiobus_unregister(mdio_bus); |
366 | mdiobus_free(mdio_bus); | |
dac2f83f KH |
367 | } |
368 | ||
369 | ||
2098c18d | 370 | static void ixp4xx_adjust_link(struct net_device *dev) |
dac2f83f | 371 | { |
2098c18d KH |
372 | struct port *port = netdev_priv(dev); |
373 | struct phy_device *phydev = port->phydev; | |
374 | ||
375 | if (!phydev->link) { | |
376 | if (port->speed) { | |
377 | port->speed = 0; | |
dac2f83f | 378 | printk(KERN_INFO "%s: link down\n", dev->name); |
dac2f83f | 379 | } |
2098c18d | 380 | return; |
dac2f83f | 381 | } |
dac2f83f | 382 | |
2098c18d KH |
383 | if (port->speed == phydev->speed && port->duplex == phydev->duplex) |
384 | return; | |
dac2f83f | 385 | |
2098c18d KH |
386 | port->speed = phydev->speed; |
387 | port->duplex = phydev->duplex; | |
dac2f83f | 388 | |
2098c18d KH |
389 | if (port->duplex) |
390 | __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX, | |
391 | &port->regs->tx_control[0]); | |
392 | else | |
393 | __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX, | |
394 | &port->regs->tx_control[0]); | |
dac2f83f | 395 | |
2098c18d KH |
396 | printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n", |
397 | dev->name, port->speed, port->duplex ? "full" : "half"); | |
dac2f83f KH |
398 | } |
399 | ||
400 | ||
401 | static inline void debug_pkt(struct net_device *dev, const char *func, | |
402 | u8 *data, int len) | |
403 | { | |
404 | #if DEBUG_PKT_BYTES | |
405 | int i; | |
406 | ||
407 | printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len); | |
408 | for (i = 0; i < len; i++) { | |
409 | if (i >= DEBUG_PKT_BYTES) | |
410 | break; | |
411 | printk("%s%02X", | |
412 | ((i == 6) || (i == 12) || (i >= 14)) ? " " : "", | |
413 | data[i]); | |
414 | } | |
415 | printk("\n"); | |
416 | #endif | |
417 | } | |
418 | ||
419 | ||
420 | static inline void debug_desc(u32 phys, struct desc *desc) | |
421 | { | |
422 | #if DEBUG_DESC | |
423 | printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X" | |
424 | " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n", | |
425 | phys, desc->next, desc->buf_len, desc->pkt_len, | |
426 | desc->data, desc->dest_id, desc->src_id, desc->flags, | |
427 | desc->qos, desc->padlen, desc->vlan_tci, | |
428 | desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2, | |
429 | desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5, | |
430 | desc->src_mac_0, desc->src_mac_1, desc->src_mac_2, | |
431 | desc->src_mac_3, desc->src_mac_4, desc->src_mac_5); | |
432 | #endif | |
433 | } | |
434 | ||
dac2f83f KH |
435 | static inline int queue_get_desc(unsigned int queue, struct port *port, |
436 | int is_tx) | |
437 | { | |
438 | u32 phys, tab_phys, n_desc; | |
439 | struct desc *tab; | |
440 | ||
e6da96ac | 441 | if (!(phys = qmgr_get_entry(queue))) |
dac2f83f KH |
442 | return -1; |
443 | ||
444 | phys &= ~0x1F; /* mask out non-address bits */ | |
445 | tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0); | |
446 | tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0); | |
447 | n_desc = (phys - tab_phys) / sizeof(struct desc); | |
448 | BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS)); | |
449 | debug_desc(phys, &tab[n_desc]); | |
450 | BUG_ON(tab[n_desc].next); | |
451 | return n_desc; | |
452 | } | |
453 | ||
454 | static inline void queue_put_desc(unsigned int queue, u32 phys, | |
455 | struct desc *desc) | |
456 | { | |
dac2f83f KH |
457 | debug_desc(phys, desc); |
458 | BUG_ON(phys & 0x1F); | |
459 | qmgr_put_entry(queue, phys); | |
6a68afe3 KH |
460 | /* Don't check for queue overflow here, we've allocated sufficient |
461 | length and queues >= 32 don't support this check anyway. */ | |
dac2f83f KH |
462 | } |
463 | ||
464 | ||
465 | static inline void dma_unmap_tx(struct port *port, struct desc *desc) | |
466 | { | |
467 | #ifdef __ARMEB__ | |
468 | dma_unmap_single(&port->netdev->dev, desc->data, | |
469 | desc->buf_len, DMA_TO_DEVICE); | |
470 | #else | |
471 | dma_unmap_single(&port->netdev->dev, desc->data & ~3, | |
472 | ALIGN((desc->data & 3) + desc->buf_len, 4), | |
473 | DMA_TO_DEVICE); | |
474 | #endif | |
475 | } | |
476 | ||
477 | ||
478 | static void eth_rx_irq(void *pdev) | |
479 | { | |
480 | struct net_device *dev = pdev; | |
481 | struct port *port = netdev_priv(dev); | |
482 | ||
483 | #if DEBUG_RX | |
484 | printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name); | |
485 | #endif | |
486 | qmgr_disable_irq(port->plat->rxq); | |
288379f0 | 487 | napi_schedule(&port->napi); |
dac2f83f KH |
488 | } |
489 | ||
490 | static int eth_poll(struct napi_struct *napi, int budget) | |
491 | { | |
492 | struct port *port = container_of(napi, struct port, napi); | |
493 | struct net_device *dev = port->netdev; | |
494 | unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id); | |
495 | int received = 0; | |
496 | ||
497 | #if DEBUG_RX | |
498 | printk(KERN_DEBUG "%s: eth_poll\n", dev->name); | |
499 | #endif | |
500 | ||
501 | while (received < budget) { | |
502 | struct sk_buff *skb; | |
503 | struct desc *desc; | |
504 | int n; | |
505 | #ifdef __ARMEB__ | |
506 | struct sk_buff *temp; | |
507 | u32 phys; | |
508 | #endif | |
509 | ||
510 | if ((n = queue_get_desc(rxq, port, 0)) < 0) { | |
dac2f83f | 511 | #if DEBUG_RX |
288379f0 | 512 | printk(KERN_DEBUG "%s: eth_poll napi_complete\n", |
dac2f83f KH |
513 | dev->name); |
514 | #endif | |
288379f0 | 515 | napi_complete(napi); |
dac2f83f | 516 | qmgr_enable_irq(rxq); |
9733bb8e KH |
517 | if (!qmgr_stat_below_low_watermark(rxq) && |
518 | napi_reschedule(napi)) { /* not empty again */ | |
dac2f83f KH |
519 | #if DEBUG_RX |
520 | printk(KERN_DEBUG "%s: eth_poll" | |
288379f0 | 521 | " napi_reschedule successed\n", |
dac2f83f KH |
522 | dev->name); |
523 | #endif | |
524 | qmgr_disable_irq(rxq); | |
525 | continue; | |
526 | } | |
527 | #if DEBUG_RX | |
528 | printk(KERN_DEBUG "%s: eth_poll all done\n", | |
529 | dev->name); | |
530 | #endif | |
9076689a | 531 | return received; /* all work done */ |
dac2f83f KH |
532 | } |
533 | ||
534 | desc = rx_desc_ptr(port, n); | |
535 | ||
536 | #ifdef __ARMEB__ | |
537 | if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) { | |
538 | phys = dma_map_single(&dev->dev, skb->data, | |
539 | RX_BUFF_SIZE, DMA_FROM_DEVICE); | |
7144decb | 540 | if (dma_mapping_error(&dev->dev, phys)) { |
dac2f83f KH |
541 | dev_kfree_skb(skb); |
542 | skb = NULL; | |
543 | } | |
544 | } | |
545 | #else | |
546 | skb = netdev_alloc_skb(dev, | |
547 | ALIGN(NET_IP_ALIGN + desc->pkt_len, 4)); | |
548 | #endif | |
549 | ||
550 | if (!skb) { | |
b4c7d3b0 | 551 | dev->stats.rx_dropped++; |
dac2f83f KH |
552 | /* put the desc back on RX-ready queue */ |
553 | desc->buf_len = MAX_MRU; | |
554 | desc->pkt_len = 0; | |
555 | queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); | |
556 | continue; | |
557 | } | |
558 | ||
559 | /* process received frame */ | |
560 | #ifdef __ARMEB__ | |
561 | temp = skb; | |
562 | skb = port->rx_buff_tab[n]; | |
563 | dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN, | |
564 | RX_BUFF_SIZE, DMA_FROM_DEVICE); | |
565 | #else | |
5d23a1d2 FT |
566 | dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN, |
567 | RX_BUFF_SIZE, DMA_FROM_DEVICE); | |
dac2f83f KH |
568 | memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n], |
569 | ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4); | |
570 | #endif | |
571 | skb_reserve(skb, NET_IP_ALIGN); | |
572 | skb_put(skb, desc->pkt_len); | |
573 | ||
574 | debug_pkt(dev, "eth_poll", skb->data, skb->len); | |
575 | ||
576 | skb->protocol = eth_type_trans(skb, dev); | |
b4c7d3b0 KH |
577 | dev->stats.rx_packets++; |
578 | dev->stats.rx_bytes += skb->len; | |
dac2f83f KH |
579 | netif_receive_skb(skb); |
580 | ||
581 | /* put the new buffer on RX-free queue */ | |
582 | #ifdef __ARMEB__ | |
583 | port->rx_buff_tab[n] = temp; | |
584 | desc->data = phys + NET_IP_ALIGN; | |
585 | #endif | |
586 | desc->buf_len = MAX_MRU; | |
587 | desc->pkt_len = 0; | |
588 | queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); | |
589 | received++; | |
590 | } | |
591 | ||
592 | #if DEBUG_RX | |
593 | printk(KERN_DEBUG "eth_poll(): end, not all work done\n"); | |
594 | #endif | |
595 | return received; /* not all work done */ | |
596 | } | |
597 | ||
598 | ||
599 | static void eth_txdone_irq(void *unused) | |
600 | { | |
601 | u32 phys; | |
602 | ||
603 | #if DEBUG_TX | |
604 | printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n"); | |
605 | #endif | |
e6da96ac | 606 | while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) { |
dac2f83f KH |
607 | u32 npe_id, n_desc; |
608 | struct port *port; | |
609 | struct desc *desc; | |
610 | int start; | |
611 | ||
612 | npe_id = phys & 3; | |
613 | BUG_ON(npe_id >= MAX_NPES); | |
614 | port = npe_port_tab[npe_id]; | |
615 | BUG_ON(!port); | |
616 | phys &= ~0x1F; /* mask out non-address bits */ | |
617 | n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc); | |
618 | BUG_ON(n_desc >= TX_DESCS); | |
619 | desc = tx_desc_ptr(port, n_desc); | |
620 | debug_desc(phys, desc); | |
621 | ||
622 | if (port->tx_buff_tab[n_desc]) { /* not the draining packet */ | |
b4c7d3b0 KH |
623 | port->netdev->stats.tx_packets++; |
624 | port->netdev->stats.tx_bytes += desc->pkt_len; | |
dac2f83f KH |
625 | |
626 | dma_unmap_tx(port, desc); | |
627 | #if DEBUG_TX | |
628 | printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n", | |
629 | port->netdev->name, port->tx_buff_tab[n_desc]); | |
630 | #endif | |
631 | free_buffer_irq(port->tx_buff_tab[n_desc]); | |
632 | port->tx_buff_tab[n_desc] = NULL; | |
633 | } | |
634 | ||
9733bb8e | 635 | start = qmgr_stat_below_low_watermark(port->plat->txreadyq); |
dac2f83f | 636 | queue_put_desc(port->plat->txreadyq, phys, desc); |
9733bb8e | 637 | if (start) { /* TX-ready queue was empty */ |
dac2f83f KH |
638 | #if DEBUG_TX |
639 | printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n", | |
640 | port->netdev->name); | |
641 | #endif | |
642 | netif_wake_queue(port->netdev); | |
643 | } | |
644 | } | |
645 | } | |
646 | ||
647 | static int eth_xmit(struct sk_buff *skb, struct net_device *dev) | |
648 | { | |
649 | struct port *port = netdev_priv(dev); | |
650 | unsigned int txreadyq = port->plat->txreadyq; | |
651 | int len, offset, bytes, n; | |
652 | void *mem; | |
653 | u32 phys; | |
654 | struct desc *desc; | |
655 | ||
656 | #if DEBUG_TX | |
657 | printk(KERN_DEBUG "%s: eth_xmit\n", dev->name); | |
658 | #endif | |
659 | ||
660 | if (unlikely(skb->len > MAX_MRU)) { | |
661 | dev_kfree_skb(skb); | |
b4c7d3b0 | 662 | dev->stats.tx_errors++; |
dac2f83f KH |
663 | return NETDEV_TX_OK; |
664 | } | |
665 | ||
666 | debug_pkt(dev, "eth_xmit", skb->data, skb->len); | |
667 | ||
668 | len = skb->len; | |
669 | #ifdef __ARMEB__ | |
670 | offset = 0; /* no need to keep alignment */ | |
671 | bytes = len; | |
672 | mem = skb->data; | |
673 | #else | |
674 | offset = (int)skb->data & 3; /* keep 32-bit alignment */ | |
675 | bytes = ALIGN(offset + len, 4); | |
676 | if (!(mem = kmalloc(bytes, GFP_ATOMIC))) { | |
677 | dev_kfree_skb(skb); | |
b4c7d3b0 | 678 | dev->stats.tx_dropped++; |
dac2f83f KH |
679 | return NETDEV_TX_OK; |
680 | } | |
681 | memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4); | |
682 | dev_kfree_skb(skb); | |
683 | #endif | |
684 | ||
685 | phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); | |
7144decb | 686 | if (dma_mapping_error(&dev->dev, phys)) { |
dac2f83f KH |
687 | #ifdef __ARMEB__ |
688 | dev_kfree_skb(skb); | |
689 | #else | |
690 | kfree(mem); | |
691 | #endif | |
b4c7d3b0 | 692 | dev->stats.tx_dropped++; |
dac2f83f KH |
693 | return NETDEV_TX_OK; |
694 | } | |
695 | ||
696 | n = queue_get_desc(txreadyq, port, 1); | |
697 | BUG_ON(n < 0); | |
698 | desc = tx_desc_ptr(port, n); | |
699 | ||
700 | #ifdef __ARMEB__ | |
701 | port->tx_buff_tab[n] = skb; | |
702 | #else | |
703 | port->tx_buff_tab[n] = mem; | |
704 | #endif | |
705 | desc->data = phys + offset; | |
706 | desc->buf_len = desc->pkt_len = len; | |
707 | ||
708 | /* NPE firmware pads short frames with zeros internally */ | |
709 | wmb(); | |
710 | queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc); | |
dac2f83f | 711 | |
9733bb8e | 712 | if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */ |
dac2f83f KH |
713 | #if DEBUG_TX |
714 | printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name); | |
715 | #endif | |
716 | netif_stop_queue(dev); | |
717 | /* we could miss TX ready interrupt */ | |
6a68afe3 | 718 | /* really empty in fact */ |
9733bb8e | 719 | if (!qmgr_stat_below_low_watermark(txreadyq)) { |
dac2f83f KH |
720 | #if DEBUG_TX |
721 | printk(KERN_DEBUG "%s: eth_xmit ready again\n", | |
722 | dev->name); | |
723 | #endif | |
724 | netif_wake_queue(dev); | |
725 | } | |
726 | } | |
727 | ||
728 | #if DEBUG_TX | |
729 | printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name); | |
730 | #endif | |
731 | return NETDEV_TX_OK; | |
732 | } | |
733 | ||
734 | ||
dac2f83f KH |
735 | static void eth_set_mcast_list(struct net_device *dev) |
736 | { | |
737 | struct port *port = netdev_priv(dev); | |
22bedad3 | 738 | struct netdev_hw_addr *ha; |
dac2f83f | 739 | u8 diffs[ETH_ALEN], *addr; |
3b9a7728 | 740 | int i; |
dac2f83f | 741 | |
3b9a7728 | 742 | if ((dev->flags & IFF_PROMISC) || netdev_mc_empty(dev)) { |
dac2f83f KH |
743 | __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN, |
744 | &port->regs->rx_control[0]); | |
745 | return; | |
746 | } | |
747 | ||
748 | memset(diffs, 0, ETH_ALEN); | |
dac2f83f | 749 | |
3b9a7728 | 750 | addr = NULL; |
22bedad3 | 751 | netdev_for_each_mc_addr(ha, dev) { |
3b9a7728 | 752 | if (!addr) |
22bedad3 | 753 | addr = ha->addr; /* first MAC address */ |
dac2f83f | 754 | for (i = 0; i < ETH_ALEN; i++) |
22bedad3 | 755 | diffs[i] |= addr[i] ^ ha->addr[i]; |
3b9a7728 | 756 | } |
dac2f83f KH |
757 | |
758 | for (i = 0; i < ETH_ALEN; i++) { | |
759 | __raw_writel(addr[i], &port->regs->mcast_addr[i]); | |
760 | __raw_writel(~diffs[i], &port->regs->mcast_mask[i]); | |
761 | } | |
762 | ||
763 | __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN, | |
764 | &port->regs->rx_control[0]); | |
765 | } | |
766 | ||
767 | ||
768 | static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd) | |
769 | { | |
770 | struct port *port = netdev_priv(dev); | |
dac2f83f KH |
771 | |
772 | if (!netif_running(dev)) | |
773 | return -EINVAL; | |
4954936e | 774 | return phy_mii_ioctl(port->phydev, if_mii(req), cmd); |
dac2f83f KH |
775 | } |
776 | ||
490b7722 KH |
777 | /* ethtool support */ |
778 | ||
779 | static void ixp4xx_get_drvinfo(struct net_device *dev, | |
780 | struct ethtool_drvinfo *info) | |
781 | { | |
782 | struct port *port = netdev_priv(dev); | |
783 | strcpy(info->driver, DRV_NAME); | |
784 | snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u", | |
785 | port->firmware[0], port->firmware[1], | |
786 | port->firmware[2], port->firmware[3]); | |
787 | strcpy(info->bus_info, "internal"); | |
dac2f83f KH |
788 | } |
789 | ||
490b7722 KH |
790 | static int ixp4xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
791 | { | |
792 | struct port *port = netdev_priv(dev); | |
793 | return phy_ethtool_gset(port->phydev, cmd); | |
794 | } | |
795 | ||
796 | static int ixp4xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
797 | { | |
798 | struct port *port = netdev_priv(dev); | |
799 | return phy_ethtool_sset(port->phydev, cmd); | |
800 | } | |
801 | ||
802 | static int ixp4xx_nway_reset(struct net_device *dev) | |
803 | { | |
804 | struct port *port = netdev_priv(dev); | |
805 | return phy_start_aneg(port->phydev); | |
806 | } | |
807 | ||
0fc0b732 | 808 | static const struct ethtool_ops ixp4xx_ethtool_ops = { |
490b7722 KH |
809 | .get_drvinfo = ixp4xx_get_drvinfo, |
810 | .get_settings = ixp4xx_get_settings, | |
811 | .set_settings = ixp4xx_set_settings, | |
812 | .nway_reset = ixp4xx_nway_reset, | |
813 | .get_link = ethtool_op_get_link, | |
814 | }; | |
815 | ||
dac2f83f KH |
816 | |
817 | static int request_queues(struct port *port) | |
818 | { | |
819 | int err; | |
820 | ||
e6da96ac | 821 | err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0, |
2e418400 | 822 | "%s:RX-free", port->netdev->name); |
dac2f83f KH |
823 | if (err) |
824 | return err; | |
825 | ||
e6da96ac | 826 | err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0, |
2e418400 | 827 | "%s:RX", port->netdev->name); |
dac2f83f KH |
828 | if (err) |
829 | goto rel_rxfree; | |
830 | ||
e6da96ac | 831 | err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0, |
2e418400 | 832 | "%s:TX", port->netdev->name); |
dac2f83f KH |
833 | if (err) |
834 | goto rel_rx; | |
835 | ||
e6da96ac | 836 | err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0, |
2e418400 | 837 | "%s:TX-ready", port->netdev->name); |
dac2f83f KH |
838 | if (err) |
839 | goto rel_tx; | |
840 | ||
841 | /* TX-done queue handles skbs sent out by the NPEs */ | |
842 | if (!ports_open) { | |
e6da96ac | 843 | err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0, |
2e418400 | 844 | "%s:TX-done", DRV_NAME); |
dac2f83f KH |
845 | if (err) |
846 | goto rel_txready; | |
847 | } | |
848 | return 0; | |
849 | ||
850 | rel_txready: | |
851 | qmgr_release_queue(port->plat->txreadyq); | |
852 | rel_tx: | |
853 | qmgr_release_queue(TX_QUEUE(port->id)); | |
854 | rel_rx: | |
855 | qmgr_release_queue(port->plat->rxq); | |
856 | rel_rxfree: | |
857 | qmgr_release_queue(RXFREE_QUEUE(port->id)); | |
858 | printk(KERN_DEBUG "%s: unable to request hardware queues\n", | |
859 | port->netdev->name); | |
860 | return err; | |
861 | } | |
862 | ||
863 | static void release_queues(struct port *port) | |
864 | { | |
865 | qmgr_release_queue(RXFREE_QUEUE(port->id)); | |
866 | qmgr_release_queue(port->plat->rxq); | |
867 | qmgr_release_queue(TX_QUEUE(port->id)); | |
868 | qmgr_release_queue(port->plat->txreadyq); | |
869 | ||
870 | if (!ports_open) | |
871 | qmgr_release_queue(TXDONE_QUEUE); | |
872 | } | |
873 | ||
874 | static int init_queues(struct port *port) | |
875 | { | |
876 | int i; | |
877 | ||
878 | if (!ports_open) | |
879 | if (!(dma_pool = dma_pool_create(DRV_NAME, NULL, | |
880 | POOL_ALLOC_SIZE, 32, 0))) | |
881 | return -ENOMEM; | |
882 | ||
883 | if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL, | |
884 | &port->desc_tab_phys))) | |
885 | return -ENOMEM; | |
886 | memset(port->desc_tab, 0, POOL_ALLOC_SIZE); | |
887 | memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */ | |
888 | memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab)); | |
889 | ||
890 | /* Setup RX buffers */ | |
891 | for (i = 0; i < RX_DESCS; i++) { | |
892 | struct desc *desc = rx_desc_ptr(port, i); | |
893 | buffer_t *buff; /* skb or kmalloc()ated memory */ | |
894 | void *data; | |
895 | #ifdef __ARMEB__ | |
896 | if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE))) | |
897 | return -ENOMEM; | |
898 | data = buff->data; | |
899 | #else | |
900 | if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL))) | |
901 | return -ENOMEM; | |
902 | data = buff; | |
903 | #endif | |
904 | desc->buf_len = MAX_MRU; | |
905 | desc->data = dma_map_single(&port->netdev->dev, data, | |
906 | RX_BUFF_SIZE, DMA_FROM_DEVICE); | |
7144decb | 907 | if (dma_mapping_error(&port->netdev->dev, desc->data)) { |
dac2f83f KH |
908 | free_buffer(buff); |
909 | return -EIO; | |
910 | } | |
911 | desc->data += NET_IP_ALIGN; | |
912 | port->rx_buff_tab[i] = buff; | |
913 | } | |
914 | ||
915 | return 0; | |
916 | } | |
917 | ||
918 | static void destroy_queues(struct port *port) | |
919 | { | |
920 | int i; | |
921 | ||
922 | if (port->desc_tab) { | |
923 | for (i = 0; i < RX_DESCS; i++) { | |
924 | struct desc *desc = rx_desc_ptr(port, i); | |
925 | buffer_t *buff = port->rx_buff_tab[i]; | |
926 | if (buff) { | |
927 | dma_unmap_single(&port->netdev->dev, | |
928 | desc->data - NET_IP_ALIGN, | |
929 | RX_BUFF_SIZE, DMA_FROM_DEVICE); | |
930 | free_buffer(buff); | |
931 | } | |
932 | } | |
933 | for (i = 0; i < TX_DESCS; i++) { | |
934 | struct desc *desc = tx_desc_ptr(port, i); | |
935 | buffer_t *buff = port->tx_buff_tab[i]; | |
936 | if (buff) { | |
937 | dma_unmap_tx(port, desc); | |
938 | free_buffer(buff); | |
939 | } | |
940 | } | |
941 | dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys); | |
942 | port->desc_tab = NULL; | |
943 | } | |
944 | ||
945 | if (!ports_open && dma_pool) { | |
946 | dma_pool_destroy(dma_pool); | |
947 | dma_pool = NULL; | |
948 | } | |
949 | } | |
950 | ||
951 | static int eth_open(struct net_device *dev) | |
952 | { | |
953 | struct port *port = netdev_priv(dev); | |
954 | struct npe *npe = port->npe; | |
955 | struct msg msg; | |
956 | int i, err; | |
957 | ||
958 | if (!npe_running(npe)) { | |
959 | err = npe_load_firmware(npe, npe_name(npe), &dev->dev); | |
960 | if (err) | |
961 | return err; | |
962 | ||
963 | if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) { | |
964 | printk(KERN_ERR "%s: %s not responding\n", dev->name, | |
965 | npe_name(npe)); | |
966 | return -EIO; | |
967 | } | |
490b7722 KH |
968 | port->firmware[0] = msg.byte4; |
969 | port->firmware[1] = msg.byte5; | |
970 | port->firmware[2] = msg.byte6; | |
971 | port->firmware[3] = msg.byte7; | |
dac2f83f KH |
972 | } |
973 | ||
dac2f83f KH |
974 | memset(&msg, 0, sizeof(msg)); |
975 | msg.cmd = NPE_VLAN_SETRXQOSENTRY; | |
976 | msg.eth_id = port->id; | |
977 | msg.byte5 = port->plat->rxq | 0x80; | |
978 | msg.byte7 = port->plat->rxq << 4; | |
979 | for (i = 0; i < 8; i++) { | |
980 | msg.byte3 = i; | |
981 | if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ")) | |
982 | return -EIO; | |
983 | } | |
984 | ||
985 | msg.cmd = NPE_EDB_SETPORTADDRESS; | |
986 | msg.eth_id = PHYSICAL_ID(port->id); | |
987 | msg.byte2 = dev->dev_addr[0]; | |
988 | msg.byte3 = dev->dev_addr[1]; | |
989 | msg.byte4 = dev->dev_addr[2]; | |
990 | msg.byte5 = dev->dev_addr[3]; | |
991 | msg.byte6 = dev->dev_addr[4]; | |
992 | msg.byte7 = dev->dev_addr[5]; | |
993 | if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC")) | |
994 | return -EIO; | |
995 | ||
996 | memset(&msg, 0, sizeof(msg)); | |
997 | msg.cmd = NPE_FW_SETFIREWALLMODE; | |
998 | msg.eth_id = port->id; | |
999 | if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE")) | |
1000 | return -EIO; | |
1001 | ||
1002 | if ((err = request_queues(port)) != 0) | |
1003 | return err; | |
1004 | ||
1005 | if ((err = init_queues(port)) != 0) { | |
1006 | destroy_queues(port); | |
1007 | release_queues(port); | |
1008 | return err; | |
1009 | } | |
1010 | ||
2098c18d KH |
1011 | port->speed = 0; /* force "link up" message */ |
1012 | phy_start(port->phydev); | |
1013 | ||
dac2f83f KH |
1014 | for (i = 0; i < ETH_ALEN; i++) |
1015 | __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]); | |
1016 | __raw_writel(0x08, &port->regs->random_seed); | |
1017 | __raw_writel(0x12, &port->regs->partial_empty_threshold); | |
1018 | __raw_writel(0x30, &port->regs->partial_full_threshold); | |
1019 | __raw_writel(0x08, &port->regs->tx_start_bytes); | |
1020 | __raw_writel(0x15, &port->regs->tx_deferral); | |
1021 | __raw_writel(0x08, &port->regs->tx_2part_deferral[0]); | |
1022 | __raw_writel(0x07, &port->regs->tx_2part_deferral[1]); | |
1023 | __raw_writel(0x80, &port->regs->slot_time); | |
1024 | __raw_writel(0x01, &port->regs->int_clock_threshold); | |
1025 | ||
1026 | /* Populate queues with buffers, no failure after this point */ | |
1027 | for (i = 0; i < TX_DESCS; i++) | |
1028 | queue_put_desc(port->plat->txreadyq, | |
1029 | tx_desc_phys(port, i), tx_desc_ptr(port, i)); | |
1030 | ||
1031 | for (i = 0; i < RX_DESCS; i++) | |
1032 | queue_put_desc(RXFREE_QUEUE(port->id), | |
1033 | rx_desc_phys(port, i), rx_desc_ptr(port, i)); | |
1034 | ||
1035 | __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]); | |
1036 | __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]); | |
1037 | __raw_writel(0, &port->regs->rx_control[1]); | |
1038 | __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]); | |
1039 | ||
1040 | napi_enable(&port->napi); | |
dac2f83f KH |
1041 | eth_set_mcast_list(dev); |
1042 | netif_start_queue(dev); | |
dac2f83f KH |
1043 | |
1044 | qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY, | |
1045 | eth_rx_irq, dev); | |
1046 | if (!ports_open) { | |
1047 | qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY, | |
1048 | eth_txdone_irq, NULL); | |
1049 | qmgr_enable_irq(TXDONE_QUEUE); | |
1050 | } | |
1051 | ports_open++; | |
1052 | /* we may already have RX data, enables IRQ */ | |
288379f0 | 1053 | napi_schedule(&port->napi); |
dac2f83f KH |
1054 | return 0; |
1055 | } | |
1056 | ||
1057 | static int eth_close(struct net_device *dev) | |
1058 | { | |
1059 | struct port *port = netdev_priv(dev); | |
1060 | struct msg msg; | |
1061 | int buffs = RX_DESCS; /* allocated RX buffers */ | |
1062 | int i; | |
1063 | ||
1064 | ports_open--; | |
1065 | qmgr_disable_irq(port->plat->rxq); | |
1066 | napi_disable(&port->napi); | |
1067 | netif_stop_queue(dev); | |
1068 | ||
1069 | while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0) | |
1070 | buffs--; | |
1071 | ||
1072 | memset(&msg, 0, sizeof(msg)); | |
1073 | msg.cmd = NPE_SETLOOPBACK_MODE; | |
1074 | msg.eth_id = port->id; | |
1075 | msg.byte3 = 1; | |
1076 | if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK")) | |
1077 | printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name); | |
1078 | ||
1079 | i = 0; | |
1080 | do { /* drain RX buffers */ | |
1081 | while (queue_get_desc(port->plat->rxq, port, 0) >= 0) | |
1082 | buffs--; | |
1083 | if (!buffs) | |
1084 | break; | |
1085 | if (qmgr_stat_empty(TX_QUEUE(port->id))) { | |
1086 | /* we have to inject some packet */ | |
1087 | struct desc *desc; | |
1088 | u32 phys; | |
1089 | int n = queue_get_desc(port->plat->txreadyq, port, 1); | |
1090 | BUG_ON(n < 0); | |
1091 | desc = tx_desc_ptr(port, n); | |
1092 | phys = tx_desc_phys(port, n); | |
1093 | desc->buf_len = desc->pkt_len = 1; | |
1094 | wmb(); | |
1095 | queue_put_desc(TX_QUEUE(port->id), phys, desc); | |
1096 | } | |
1097 | udelay(1); | |
1098 | } while (++i < MAX_CLOSE_WAIT); | |
1099 | ||
1100 | if (buffs) | |
1101 | printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)" | |
1102 | " left in NPE\n", dev->name, buffs); | |
1103 | #if DEBUG_CLOSE | |
1104 | if (!buffs) | |
1105 | printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i); | |
1106 | #endif | |
1107 | ||
1108 | buffs = TX_DESCS; | |
1109 | while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0) | |
1110 | buffs--; /* cancel TX */ | |
1111 | ||
1112 | i = 0; | |
1113 | do { | |
1114 | while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0) | |
1115 | buffs--; | |
1116 | if (!buffs) | |
1117 | break; | |
1118 | } while (++i < MAX_CLOSE_WAIT); | |
1119 | ||
1120 | if (buffs) | |
1121 | printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) " | |
1122 | "left in NPE\n", dev->name, buffs); | |
1123 | #if DEBUG_CLOSE | |
1124 | if (!buffs) | |
1125 | printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i); | |
1126 | #endif | |
1127 | ||
1128 | msg.byte3 = 0; | |
1129 | if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK")) | |
1130 | printk(KERN_CRIT "%s: unable to disable loopback\n", | |
1131 | dev->name); | |
1132 | ||
2098c18d | 1133 | phy_stop(port->phydev); |
dac2f83f KH |
1134 | |
1135 | if (!ports_open) | |
1136 | qmgr_disable_irq(TXDONE_QUEUE); | |
dac2f83f KH |
1137 | destroy_queues(port); |
1138 | release_queues(port); | |
1139 | return 0; | |
1140 | } | |
1141 | ||
59f8500e KH |
1142 | static const struct net_device_ops ixp4xx_netdev_ops = { |
1143 | .ndo_open = eth_open, | |
1144 | .ndo_stop = eth_close, | |
1145 | .ndo_start_xmit = eth_xmit, | |
1146 | .ndo_set_multicast_list = eth_set_mcast_list, | |
1147 | .ndo_do_ioctl = eth_ioctl, | |
635ecaa7 | 1148 | .ndo_change_mtu = eth_change_mtu, |
240c102d BH |
1149 | .ndo_set_mac_address = eth_mac_addr, |
1150 | .ndo_validate_addr = eth_validate_addr, | |
59f8500e KH |
1151 | }; |
1152 | ||
dac2f83f KH |
1153 | static int __devinit eth_init_one(struct platform_device *pdev) |
1154 | { | |
1155 | struct port *port; | |
1156 | struct net_device *dev; | |
1157 | struct eth_plat_info *plat = pdev->dev.platform_data; | |
1158 | u32 regs_phys; | |
0e53c7f9 | 1159 | char phy_id[MII_BUS_ID_SIZE + 3]; |
dac2f83f KH |
1160 | int err; |
1161 | ||
1162 | if (!(dev = alloc_etherdev(sizeof(struct port)))) | |
1163 | return -ENOMEM; | |
1164 | ||
1165 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1166 | port = netdev_priv(dev); | |
1167 | port->netdev = dev; | |
1168 | port->id = pdev->id; | |
1169 | ||
1170 | switch (port->id) { | |
1171 | case IXP4XX_ETH_NPEA: | |
1172 | port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT; | |
1173 | regs_phys = IXP4XX_EthA_BASE_PHYS; | |
1174 | break; | |
1175 | case IXP4XX_ETH_NPEB: | |
1176 | port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT; | |
1177 | regs_phys = IXP4XX_EthB_BASE_PHYS; | |
1178 | break; | |
1179 | case IXP4XX_ETH_NPEC: | |
1180 | port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT; | |
1181 | regs_phys = IXP4XX_EthC_BASE_PHYS; | |
1182 | break; | |
1183 | default: | |
3ba8c792 | 1184 | err = -ENODEV; |
dac2f83f KH |
1185 | goto err_free; |
1186 | } | |
1187 | ||
59f8500e | 1188 | dev->netdev_ops = &ixp4xx_netdev_ops; |
490b7722 | 1189 | dev->ethtool_ops = &ixp4xx_ethtool_ops; |
dac2f83f KH |
1190 | dev->tx_queue_len = 100; |
1191 | ||
1192 | netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT); | |
1193 | ||
1194 | if (!(port->npe = npe_request(NPE_ID(port->id)))) { | |
1195 | err = -EIO; | |
1196 | goto err_free; | |
1197 | } | |
1198 | ||
dac2f83f KH |
1199 | port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name); |
1200 | if (!port->mem_res) { | |
1201 | err = -EBUSY; | |
7aa6a478 | 1202 | goto err_npe_rel; |
dac2f83f KH |
1203 | } |
1204 | ||
1205 | port->plat = plat; | |
1206 | npe_port_tab[NPE_ID(port->id)] = port; | |
1207 | memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN); | |
1208 | ||
1209 | platform_set_drvdata(pdev, dev); | |
1210 | ||
1211 | __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET, | |
1212 | &port->regs->core_control); | |
1213 | udelay(50); | |
1214 | __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control); | |
1215 | udelay(50); | |
1216 | ||
0e53c7f9 | 1217 | snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, "0", plat->phy); |
2098c18d KH |
1218 | port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link, 0, |
1219 | PHY_INTERFACE_MODE_MII); | |
7aa6a478 KH |
1220 | if ((err = IS_ERR(port->phydev))) |
1221 | goto err_free_mem; | |
2098c18d KH |
1222 | |
1223 | port->phydev->irq = PHY_POLL; | |
dac2f83f | 1224 | |
7aa6a478 KH |
1225 | if ((err = register_netdev(dev))) |
1226 | goto err_phy_dis; | |
1227 | ||
dac2f83f KH |
1228 | printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy, |
1229 | npe_name(port->npe)); | |
1230 | ||
dac2f83f KH |
1231 | return 0; |
1232 | ||
7aa6a478 KH |
1233 | err_phy_dis: |
1234 | phy_disconnect(port->phydev); | |
1235 | err_free_mem: | |
1236 | npe_port_tab[NPE_ID(port->id)] = NULL; | |
1237 | platform_set_drvdata(pdev, NULL); | |
1238 | release_resource(port->mem_res); | |
dac2f83f KH |
1239 | err_npe_rel: |
1240 | npe_release(port->npe); | |
1241 | err_free: | |
1242 | free_netdev(dev); | |
1243 | return err; | |
1244 | } | |
1245 | ||
1246 | static int __devexit eth_remove_one(struct platform_device *pdev) | |
1247 | { | |
1248 | struct net_device *dev = platform_get_drvdata(pdev); | |
1249 | struct port *port = netdev_priv(dev); | |
1250 | ||
1251 | unregister_netdev(dev); | |
7aa6a478 | 1252 | phy_disconnect(port->phydev); |
dac2f83f KH |
1253 | npe_port_tab[NPE_ID(port->id)] = NULL; |
1254 | platform_set_drvdata(pdev, NULL); | |
1255 | npe_release(port->npe); | |
1256 | release_resource(port->mem_res); | |
1257 | free_netdev(dev); | |
1258 | return 0; | |
1259 | } | |
1260 | ||
3c36a837 | 1261 | static struct platform_driver ixp4xx_eth_driver = { |
dac2f83f KH |
1262 | .driver.name = DRV_NAME, |
1263 | .probe = eth_init_one, | |
1264 | .remove = eth_remove_one, | |
1265 | }; | |
1266 | ||
1267 | static int __init eth_init_module(void) | |
1268 | { | |
2098c18d | 1269 | int err; |
2098c18d KH |
1270 | if ((err = ixp4xx_mdio_register())) |
1271 | return err; | |
3c36a837 | 1272 | return platform_driver_register(&ixp4xx_eth_driver); |
dac2f83f KH |
1273 | } |
1274 | ||
1275 | static void __exit eth_cleanup_module(void) | |
1276 | { | |
3c36a837 | 1277 | platform_driver_unregister(&ixp4xx_eth_driver); |
2098c18d | 1278 | ixp4xx_mdio_remove(); |
dac2f83f KH |
1279 | } |
1280 | ||
1281 | MODULE_AUTHOR("Krzysztof Halasa"); | |
1282 | MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver"); | |
1283 | MODULE_LICENSE("GPL v2"); | |
1284 | MODULE_ALIAS("platform:ixp4xx_eth"); | |
1285 | module_init(eth_init_module); | |
1286 | module_exit(eth_cleanup_module); |