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atl1: remove unnecessary crc inversion
[mirror_ubuntu-artful-kernel.git] / drivers / net / atl1 / atl1_hw.c
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f3cc28c7
JC		 1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24#include <linux/types.h>
25#include <linux/pci.h>
26#include <linux/delay.h>
27#include <linux/if_vlan.h>
28#include <linux/etherdevice.h>
29#include <linux/crc32.h>
30#include <asm/byteorder.h>
31
32#include "atl1.h"
33
34/*
35 * Reset the transmit and receive units; mask and clear all interrupts.
36 * hw - Struct containing variables accessed by shared code
37 * return : ATL1_SUCCESS or idle status (if error)
38 */
39s32 atl1_reset_hw(struct atl1_hw *hw)
40{
41 u32 icr;
42 int i;
43
44 /*
45 * Clear Interrupt mask to stop board from generating
46 * interrupts & Clear any pending interrupt events
47 */
48 /*
49 * iowrite32(0, hw->hw_addr + REG_IMR);
50 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
51 */
52
53 /*
54 * Issue Soft Reset to the MAC. This will reset the chip's
55 * transmit, receive, DMA. It will not effect
56 * the current PCI configuration. The global reset bit is self-
57 * clearing, and should clear within a microsecond.
58 */
59 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
60 ioread32(hw->hw_addr + REG_MASTER_CTRL);
61
62 iowrite16(1, hw->hw_addr + REG_GPHY_ENABLE);
63 ioread16(hw->hw_addr + REG_GPHY_ENABLE);
64
65 msleep(1); /* delay about 1ms */
66
67 /* Wait at least 10ms for All module to be Idle */
68 for (i = 0; i < 10; i++) {
69 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
70 if (!icr)
71 break;
72 msleep(1); /* delay 1 ms */
73 cpu_relax(); /* FIXME: is this still the right way to do this? */
74 }
75
76 if (icr) {
77 printk (KERN_DEBUG "icr = %x\n", icr);
78 return icr;
79 }
80
81 return ATL1_SUCCESS;
82}
83
84/* function about EEPROM
85 *
86 * check_eeprom_exist
87 * return 0 if eeprom exist
88 */
89static int atl1_check_eeprom_exist(struct atl1_hw *hw)
90{
91 u32 value;
92 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
93 if (value & SPI_FLASH_CTRL_EN_VPD) {
94 value &= ~SPI_FLASH_CTRL_EN_VPD;
95 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
96 }
97
98 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
99 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
100}
101
102static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
103{
104 int i;
105 u32 control;
106
107 if (offset & 3)
108 return false; /* address do not align */
109
110 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
111 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
112 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
113 ioread32(hw->hw_addr + REG_VPD_CAP);
114
115 for (i = 0; i < 10; i++) {
116 msleep(2);
117 control = ioread32(hw->hw_addr + REG_VPD_CAP);
118 if (control & VPD_CAP_VPD_FLAG)
119 break;
120 }
121 if (control & VPD_CAP_VPD_FLAG) {
122 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
123 return true;
124 }
125 return false; /* timeout */
126}
127
128/*
129 * Reads the value from a PHY register
130 * hw - Struct containing variables accessed by shared code
131 * reg_addr - address of the PHY register to read
132 */
133s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
134{
135 u32 val;
136 int i;
137
138 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
139 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
140 MDIO_CLK_SEL_SHIFT;
141 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
142 ioread32(hw->hw_addr + REG_MDIO_CTRL);
143
144 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
145 udelay(2);
146 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
147 if (!(val & (MDIO_START | MDIO_BUSY)))
148 break;
149 }
150 if (!(val & (MDIO_START | MDIO_BUSY))) {
151 *phy_data = (u16) val;
152 return ATL1_SUCCESS;
153 }
154 return ATL1_ERR_PHY;
155}
156
157#define CUSTOM_SPI_CS_SETUP 2
158#define CUSTOM_SPI_CLK_HI 2
159#define CUSTOM_SPI_CLK_LO 2
160#define CUSTOM_SPI_CS_HOLD 2
161#define CUSTOM_SPI_CS_HI 3
162
163static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
164{
165 int i;
166 u32 value;
167
168 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
169 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
170
171 value = SPI_FLASH_CTRL_WAIT_READY |
172 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
173 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
174 SPI_FLASH_CTRL_CLK_HI_MASK) <<
175 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
176 SPI_FLASH_CTRL_CLK_LO_MASK) <<
177 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
178 SPI_FLASH_CTRL_CS_HOLD_MASK) <<
179 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
180 SPI_FLASH_CTRL_CS_HI_MASK) <<
181 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
182 SPI_FLASH_CTRL_INS_SHIFT;
183
184 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
185
186 value |= SPI_FLASH_CTRL_START;
187 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
188 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
189
190 for (i = 0; i < 10; i++) {
191 msleep(1); /* 1ms */
192 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
193 if (!(value & SPI_FLASH_CTRL_START))
194 break;
195 }
196
197 if (value & SPI_FLASH_CTRL_START)
198 return false;
199
200 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
201
202 return true;
203}
204
205/*
206 * get_permanent_address
207 * return 0 if get valid mac address,
208 */
209static int atl1_get_permanent_address(struct atl1_hw *hw)
210{
211 u32 addr[2];
212 u32 i, control;
213 u16 reg;
214 u8 eth_addr[ETH_ALEN];
215 bool key_valid;
216
217 if (is_valid_ether_addr(hw->perm_mac_addr))
218 return 0;
219
220 /* init */
221 addr[0] = addr[1] = 0;
222
223 if (!atl1_check_eeprom_exist(hw)) { /* eeprom exist */
224 reg = 0;
225 key_valid = false;
226 /* Read out all EEPROM content */
227 i = 0;
228 while (1) {
229 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
230 if (key_valid) {
231 if (reg == REG_MAC_STA_ADDR)
232 addr[0] = control;
233 else if (reg == (REG_MAC_STA_ADDR + 4))
234 addr[1] = control;
235 key_valid = false;
236 } else if ((control & 0xff) == 0x5A) {
237 key_valid = true;
238 reg = (u16) (control >> 16);
239 } else
240 break; /* assume data end while encount an invalid KEYWORD */
241 } else
242 break; /* read error */
243 i += 4;
244 }
245
fd8c5a7d
JC		 246 *(u32 *) &eth_addr[2] = swab32(addr[0]);
247 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
f3cc28c7
JC		 248 if (is_valid_ether_addr(eth_addr)) {
249 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
250 return 0;
251 }
252 return 1;
253 }
254
255 /* see if SPI FLAGS exist ? */
256 addr[0] = addr[1] = 0;
257 reg = 0;
258 key_valid = false;
259 i = 0;
260 while (1) {
261 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
262 if (key_valid) {
263 if (reg == REG_MAC_STA_ADDR)
264 addr[0] = control;
265 else if (reg == (REG_MAC_STA_ADDR + 4))
266 addr[1] = control;
267 key_valid = false;
268 } else if ((control & 0xff) == 0x5A) {
269 key_valid = true;
270 reg = (u16) (control >> 16);
271 } else
272 break; /* data end */
273 } else
274 break; /* read error */
275 i += 4;
276 }
277
fd8c5a7d
JC		 278 *(u32 *) &eth_addr[2] = swab32(addr[0]);
279 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
f3cc28c7
JC		 280 if (is_valid_ether_addr(eth_addr)) {
281 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
282 return 0;
283 }
fd8c5a7d
JC		 284
285 /*
286 * On some motherboards, the MAC address is written by the
287 * BIOS directly to the MAC register during POST, and is
288 * not stored in eeprom. If all else thus far has failed
289 * to fetch the permanent MAC address, try reading it directly.
290 */
291 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
292 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
293 *(u32 *) &eth_addr[2] = swab32(addr[0]);
294 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
295 if (is_valid_ether_addr(eth_addr)) {
296 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
297 return 0;
298 }
299
f3cc28c7
JC		 300 return 1;
301}
302
303/*
304 * Reads the adapter's MAC address from the EEPROM
305 * hw - Struct containing variables accessed by shared code
306 */
307s32 atl1_read_mac_addr(struct atl1_hw *hw)
308{
309 u16 i;
310
311 if (atl1_get_permanent_address(hw))
312 random_ether_addr(hw->perm_mac_addr);
313
314 for (i = 0; i < ETH_ALEN; i++)
315 hw->mac_addr[i] = hw->perm_mac_addr[i];
316 return ATL1_SUCCESS;
317}
318
319/*
320 * Hashes an address to determine its location in the multicast table
321 * hw - Struct containing variables accessed by shared code
322 * mc_addr - the multicast address to hash
323 *
324 * atl1_hash_mc_addr
325 * purpose
326 * set hash value for a multicast address
327 * hash calcu processing :
328 * 1. calcu 32bit CRC for multicast address
329 * 2. reverse crc with MSB to LSB
330 */
331u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
332{
333 u32 crc32, value = 0;
334 int i;
335
336 crc32 = ether_crc_le(6, mc_addr);
f3cc28c7
JC		 337 for (i = 0; i < 32; i++)
338 value |= (((crc32 >> i) & 1) << (31 - i));
339
340 return value;
341}
342
343/*
344 * Sets the bit in the multicast table corresponding to the hash value.
345 * hw - Struct containing variables accessed by shared code
346 * hash_value - Multicast address hash value
347 */
348void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
349{
350 u32 hash_bit, hash_reg;
351 u32 mta;
352
353 /*
354 * The HASH Table is a register array of 2 32-bit registers.
355 * It is treated like an array of 64 bits. We want to set
356 * bit BitArray[hash_value]. So we figure out what register
357 * the bit is in, read it, OR in the new bit, then write
358 * back the new value. The register is determined by the
359 * upper 7 bits of the hash value and the bit within that
360 * register are determined by the lower 5 bits of the value.
361 */
362 hash_reg = (hash_value >> 31) & 0x1;
363 hash_bit = (hash_value >> 26) & 0x1F;
a62daa4c 364 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
f3cc28c7
JC		 365 mta |= (1 << hash_bit);
366 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
367}
368
369/*
370 * Writes a value to a PHY register
371 * hw - Struct containing variables accessed by shared code
372 * reg_addr - address of the PHY register to write
373 * data - data to write to the PHY
374 */
375s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
376{
377 int i;
378 u32 val;
379
380 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
381 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
382 MDIO_SUP_PREAMBLE |
383 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
384 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
385 ioread32(hw->hw_addr + REG_MDIO_CTRL);
386
387 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
388 udelay(2);
389 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
390 if (!(val & (MDIO_START | MDIO_BUSY)))
391 break;
392 }
393
394 if (!(val & (MDIO_START | MDIO_BUSY)))
395 return ATL1_SUCCESS;
396
397 return ATL1_ERR_PHY;
398}
399
400/*
401 * Make L001's PHY out of Power Saving State (bug)
402 * hw - Struct containing variables accessed by shared code
403 * when power on, L001's PHY always on Power saving State
404 * (Gigabit Link forbidden)
405 */
406static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
407{
408 s32 ret;
409 ret = atl1_write_phy_reg(hw, 29, 0x0029);
410 if (ret)
411 return ret;
412 return atl1_write_phy_reg(hw, 30, 0);
413}
414
415/*
416 *TODO: do something or get rid of this
417 */
418s32 atl1_phy_enter_power_saving(struct atl1_hw *hw)
419{
420/* s32 ret_val;
421 * u16 phy_data;
422 */
423
424/*
425 ret_val = atl1_write_phy_reg(hw, ...);
426 ret_val = atl1_write_phy_reg(hw, ...);
427 ....
428*/
429 return ATL1_SUCCESS;
430}
431
432/*
433 * Resets the PHY and make all config validate
434 * hw - Struct containing variables accessed by shared code
435 *
436 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
437 */
438static s32 atl1_phy_reset(struct atl1_hw *hw)
439{
440 s32 ret_val;
441 u16 phy_data;
442
443 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
444 hw->media_type == MEDIA_TYPE_1000M_FULL)
445 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
446 else {
447 switch (hw->media_type) {
448 case MEDIA_TYPE_100M_FULL:
449 phy_data =
450 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
451 MII_CR_RESET;
452 break;
453 case MEDIA_TYPE_100M_HALF:
454 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
455 break;
456 case MEDIA_TYPE_10M_FULL:
457 phy_data =
458 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
459 break;
460 default: /* MEDIA_TYPE_10M_HALF: */
461 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
462 break;
463 }
464 }
465
466 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
467 if (ret_val) {
468 u32 val;
469 int i;
470 /* pcie serdes link may be down! */
471 printk(KERN_DEBUG "%s: autoneg caused pcie phy link down\n",
472 atl1_driver_name);
473
474 for (i = 0; i < 25; i++) {
475 msleep(1);
476 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
477 if (!(val & (MDIO_START | MDIO_BUSY)))
478 break;
479 }
480
481 if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
482 printk(KERN_WARNING
483 "%s: pcie link down at least for 25ms\n",
484 atl1_driver_name);
485 return ret_val;
486 }
487 }
488 return ATL1_SUCCESS;
489}
490
491/*
492 * Configures PHY autoneg and flow control advertisement settings
493 * hw - Struct containing variables accessed by shared code
494 */
495s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
496{
497 s32 ret_val;
498 s16 mii_autoneg_adv_reg;
499 s16 mii_1000t_ctrl_reg;
500
501 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
502 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
503
504 /* Read the MII 1000Base-T Control Register (Address 9). */
505 mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK;
506
507 /*
508 * First we clear all the 10/100 mb speed bits in the Auto-Neg
509 * Advertisement Register (Address 4) and the 1000 mb speed bits in
510 * the 1000Base-T Control Register (Address 9).
511 */
512 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
513 mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK;
514
515 /*
516 * Need to parse media_type and set up
517 * the appropriate PHY registers.
518 */
519 switch (hw->media_type) {
520 case MEDIA_TYPE_AUTO_SENSOR:
521 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
522 MII_AR_10T_FD_CAPS |
523 MII_AR_100TX_HD_CAPS |
524 MII_AR_100TX_FD_CAPS);
525 mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
526 break;
527
528 case MEDIA_TYPE_1000M_FULL:
529 mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
530 break;
531
532 case MEDIA_TYPE_100M_FULL:
533 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
534 break;
535
536 case MEDIA_TYPE_100M_HALF:
537 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
538 break;
539
540 case MEDIA_TYPE_10M_FULL:
541 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
542 break;
543
544 default:
545 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
546 break;
547 }
548
549 /* flow control fixed to enable all */
550 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
551
552 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
553 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
554
555 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
556 if (ret_val)
557 return ret_val;
558
559 ret_val = atl1_write_phy_reg(hw, MII_AT001_CR, mii_1000t_ctrl_reg);
560 if (ret_val)
561 return ret_val;
562
563 return ATL1_SUCCESS;
564}
565
566/*
567 * Configures link settings.
568 * hw - Struct containing variables accessed by shared code
569 * Assumes the hardware has previously been reset and the
570 * transmitter and receiver are not enabled.
571 */
572static s32 atl1_setup_link(struct atl1_hw *hw)
573{
574 s32 ret_val;
575
576 /*
577 * Options:
578 * PHY will advertise value(s) parsed from
579 * autoneg_advertised and fc
580 * no matter what autoneg is , We will not wait link result.
581 */
582 ret_val = atl1_phy_setup_autoneg_adv(hw);
583 if (ret_val) {
584 printk(KERN_DEBUG "%s: error setting up autonegotiation\n",
585 atl1_driver_name);
586 return ret_val;
587 }
588 /* SW.Reset , En-Auto-Neg if needed */
589 ret_val = atl1_phy_reset(hw);
590 if (ret_val) {
591 printk(KERN_DEBUG "%s: error resetting the phy\n",
592 atl1_driver_name);
593 return ret_val;
594 }
595 hw->phy_configured = true;
596 return ret_val;
597}
598
599static struct atl1_spi_flash_dev flash_table[] = {
600/* MFR_NAME WRSR READ PRGM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
601 {"Atmel", 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62},
602 {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60},
603 {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7},
604};
605
606static void atl1_init_flash_opcode(struct atl1_hw *hw)
607{
608 if (hw->flash_vendor >= sizeof(flash_table) / sizeof(flash_table[0]))
609 hw->flash_vendor = 0; /* ATMEL */
610
611 /* Init OP table */
612 iowrite8(flash_table[hw->flash_vendor].cmd_program,
613 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
614 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
615 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
616 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
617 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
618 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
619 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
620 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
621 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
622 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
623 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
624 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
625 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
626 iowrite8(flash_table[hw->flash_vendor].cmd_read,
627 hw->hw_addr + REG_SPI_FLASH_OP_READ);
628}
629
630/*
631 * Performs basic configuration of the adapter.
632 * hw - Struct containing variables accessed by shared code
633 * Assumes that the controller has previously been reset and is in a
634 * post-reset uninitialized state. Initializes multicast table,
635 * and Calls routines to setup link
636 * Leaves the transmit and receive units disabled and uninitialized.
637 */
638s32 atl1_init_hw(struct atl1_hw *hw)
639{
640 u32 ret_val = 0;
641
642 /* Zero out the Multicast HASH table */
643 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
644 /* clear the old settings from the multicast hash table */
645 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
646
647 atl1_init_flash_opcode(hw);
648
649 if (!hw->phy_configured) {
650 /* enable GPHY LinkChange Interrrupt */
651 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
652 if (ret_val)
653 return ret_val;
654 /* make PHY out of power-saving state */
655 ret_val = atl1_phy_leave_power_saving(hw);
656 if (ret_val)
657 return ret_val;
658 /* Call a subroutine to configure the link */
659 ret_val = atl1_setup_link(hw);
660 }
661 return ret_val;
662}
663
664/*
665 * Detects the current speed and duplex settings of the hardware.
666 * hw - Struct containing variables accessed by shared code
667 * speed - Speed of the connection
668 * duplex - Duplex setting of the connection
669 */
670s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
671{
672 s32 ret_val;
673 u16 phy_data;
674
675 /* ; --- Read PHY Specific Status Register (17) */
676 ret_val = atl1_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
677 if (ret_val)
678 return ret_val;
679
680 if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
681 return ATL1_ERR_PHY_RES;
682
683 switch (phy_data & MII_AT001_PSSR_SPEED) {
684 case MII_AT001_PSSR_1000MBS:
685 *speed = SPEED_1000;
686 break;
687 case MII_AT001_PSSR_100MBS:
688 *speed = SPEED_100;
689 break;
690 case MII_AT001_PSSR_10MBS:
691 *speed = SPEED_10;
692 break;
693 default:
694 printk(KERN_DEBUG "%s: error getting speed\n",
695 atl1_driver_name);
696 return ATL1_ERR_PHY_SPEED;
697 break;
698 }
699 if (phy_data & MII_AT001_PSSR_DPLX)
700 *duplex = FULL_DUPLEX;
701 else
702 *duplex = HALF_DUPLEX;
703
704 return ATL1_SUCCESS;
705}
706
707void atl1_set_mac_addr(struct atl1_hw *hw)
708{
709 u32 value;
710 /*
711 * 00-0B-6A-F6-00-DC
712 * 0: 6AF600DC 1: 000B
713 * low dword
714 */
715 value = (((u32) hw->mac_addr[2]) << 24) |
716 (((u32) hw->mac_addr[3]) << 16) |
717 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
718 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
719 /* high dword */
720 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
721 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
722}
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