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f3cc28c7 JC |
1 | /* |
2 | * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved. | |
305282ba | 3 | * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com> |
e8f720fd | 4 | * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com> |
f3cc28c7 JC |
5 | * |
6 | * Derived from Intel e1000 driver | |
7 | * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the Free | |
11 | * Software Foundation; either version 2 of the License, or (at your option) | |
12 | * any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
21 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
22 | * | |
23 | * The full GNU General Public License is included in this distribution in the | |
24 | * file called COPYING. | |
25 | * | |
26 | * Contact Information: | |
c8f2d9bc JC |
27 | * Xiong Huang <xiong.huang@atheros.com> |
28 | * Jie Yang <jie.yang@atheros.com> | |
f3cc28c7 JC |
29 | * Chris Snook <csnook@redhat.com> |
30 | * Jay Cliburn <jcliburn@gmail.com> | |
31 | * | |
c8f2d9bc | 32 | * This version is adapted from the Attansic reference driver. |
f3cc28c7 JC |
33 | * |
34 | * TODO: | |
53ffb42c | 35 | * Add more ethtool functions. |
f3cc28c7 JC |
36 | * Fix abstruse irq enable/disable condition described here: |
37 | * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2 | |
38 | * | |
39 | * NEEDS TESTING: | |
40 | * VLAN | |
41 | * multicast | |
42 | * promiscuous mode | |
43 | * interrupt coalescing | |
44 | * SMP torture testing | |
45 | */ | |
46 | ||
305282ba JC |
47 | #include <asm/atomic.h> |
48 | #include <asm/byteorder.h> | |
49 | ||
50 | #include <linux/compiler.h> | |
51 | #include <linux/crc32.h> | |
52 | #include <linux/delay.h> | |
53 | #include <linux/dma-mapping.h> | |
f3cc28c7 | 54 | #include <linux/etherdevice.h> |
f3cc28c7 | 55 | #include <linux/hardirq.h> |
305282ba JC |
56 | #include <linux/if_ether.h> |
57 | #include <linux/if_vlan.h> | |
58 | #include <linux/in.h> | |
f3cc28c7 | 59 | #include <linux/interrupt.h> |
305282ba | 60 | #include <linux/ip.h> |
f3cc28c7 | 61 | #include <linux/irqflags.h> |
305282ba JC |
62 | #include <linux/irqreturn.h> |
63 | #include <linux/jiffies.h> | |
64 | #include <linux/mii.h> | |
65 | #include <linux/module.h> | |
66 | #include <linux/moduleparam.h> | |
f3cc28c7 | 67 | #include <linux/net.h> |
305282ba JC |
68 | #include <linux/netdevice.h> |
69 | #include <linux/pci.h> | |
70 | #include <linux/pci_ids.h> | |
f3cc28c7 | 71 | #include <linux/pm.h> |
305282ba JC |
72 | #include <linux/skbuff.h> |
73 | #include <linux/slab.h> | |
74 | #include <linux/spinlock.h> | |
75 | #include <linux/string.h> | |
f3cc28c7 | 76 | #include <linux/tcp.h> |
305282ba JC |
77 | #include <linux/timer.h> |
78 | #include <linux/types.h> | |
79 | #include <linux/workqueue.h> | |
f3cc28c7 | 80 | |
f3cc28c7 JC |
81 | #include <net/checksum.h> |
82 | ||
f3cc28c7 JC |
83 | #include "atl1.h" |
84 | ||
305282ba JC |
85 | /* Temporary hack for merging atl1 and atl2 */ |
86 | #include "atlx.c" | |
f3cc28c7 | 87 | |
8ec7226a CS |
88 | /* |
89 | * This is the only thing that needs to be changed to adjust the | |
90 | * maximum number of ports that the driver can manage. | |
91 | */ | |
92 | #define ATL1_MAX_NIC 4 | |
93 | ||
94 | #define OPTION_UNSET -1 | |
95 | #define OPTION_DISABLED 0 | |
96 | #define OPTION_ENABLED 1 | |
97 | ||
98 | #define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET } | |
99 | ||
100 | /* | |
101 | * Interrupt Moderate Timer in units of 2 us | |
102 | * | |
103 | * Valid Range: 10-65535 | |
104 | * | |
105 | * Default Value: 100 (200us) | |
106 | */ | |
107 | static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT; | |
b79d8fff | 108 | static unsigned int num_int_mod_timer; |
8ec7226a CS |
109 | module_param_array_named(int_mod_timer, int_mod_timer, int, |
110 | &num_int_mod_timer, 0); | |
111 | MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer"); | |
112 | ||
113 | #define DEFAULT_INT_MOD_CNT 100 /* 200us */ | |
114 | #define MAX_INT_MOD_CNT 65000 | |
115 | #define MIN_INT_MOD_CNT 50 | |
116 | ||
117 | struct atl1_option { | |
118 | enum { enable_option, range_option, list_option } type; | |
119 | char *name; | |
120 | char *err; | |
121 | int def; | |
122 | union { | |
123 | struct { /* range_option info */ | |
124 | int min; | |
125 | int max; | |
126 | } r; | |
127 | struct { /* list_option info */ | |
128 | int nr; | |
129 | struct atl1_opt_list { | |
130 | int i; | |
131 | char *str; | |
132 | } *p; | |
133 | } l; | |
134 | } arg; | |
135 | }; | |
136 | ||
137 | static int __devinit atl1_validate_option(int *value, struct atl1_option *opt, | |
138 | struct pci_dev *pdev) | |
139 | { | |
140 | if (*value == OPTION_UNSET) { | |
141 | *value = opt->def; | |
142 | return 0; | |
143 | } | |
144 | ||
145 | switch (opt->type) { | |
146 | case enable_option: | |
147 | switch (*value) { | |
148 | case OPTION_ENABLED: | |
149 | dev_info(&pdev->dev, "%s enabled\n", opt->name); | |
150 | return 0; | |
151 | case OPTION_DISABLED: | |
152 | dev_info(&pdev->dev, "%s disabled\n", opt->name); | |
153 | return 0; | |
154 | } | |
155 | break; | |
156 | case range_option: | |
157 | if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { | |
158 | dev_info(&pdev->dev, "%s set to %i\n", opt->name, | |
159 | *value); | |
160 | return 0; | |
161 | } | |
162 | break; | |
163 | case list_option:{ | |
164 | int i; | |
165 | struct atl1_opt_list *ent; | |
166 | ||
167 | for (i = 0; i < opt->arg.l.nr; i++) { | |
168 | ent = &opt->arg.l.p[i]; | |
169 | if (*value == ent->i) { | |
170 | if (ent->str[0] != '\0') | |
171 | dev_info(&pdev->dev, "%s\n", | |
172 | ent->str); | |
173 | return 0; | |
174 | } | |
175 | } | |
176 | } | |
177 | break; | |
178 | ||
179 | default: | |
180 | break; | |
181 | } | |
182 | ||
183 | dev_info(&pdev->dev, "invalid %s specified (%i) %s\n", | |
184 | opt->name, *value, opt->err); | |
185 | *value = opt->def; | |
186 | return -1; | |
187 | } | |
188 | ||
189 | /* | |
190 | * atl1_check_options - Range Checking for Command Line Parameters | |
191 | * @adapter: board private structure | |
192 | * | |
193 | * This routine checks all command line parameters for valid user | |
194 | * input. If an invalid value is given, or if no user specified | |
195 | * value exists, a default value is used. The final value is stored | |
196 | * in a variable in the adapter structure. | |
197 | */ | |
9dc20f55 | 198 | static void __devinit atl1_check_options(struct atl1_adapter *adapter) |
8ec7226a CS |
199 | { |
200 | struct pci_dev *pdev = adapter->pdev; | |
201 | int bd = adapter->bd_number; | |
202 | if (bd >= ATL1_MAX_NIC) { | |
203 | dev_notice(&pdev->dev, "no configuration for board#%i\n", bd); | |
204 | dev_notice(&pdev->dev, "using defaults for all values\n"); | |
205 | } | |
206 | { /* Interrupt Moderate Timer */ | |
207 | struct atl1_option opt = { | |
208 | .type = range_option, | |
209 | .name = "Interrupt Moderator Timer", | |
210 | .err = "using default of " | |
211 | __MODULE_STRING(DEFAULT_INT_MOD_CNT), | |
212 | .def = DEFAULT_INT_MOD_CNT, | |
213 | .arg = {.r = {.min = MIN_INT_MOD_CNT, | |
214 | .max = MAX_INT_MOD_CNT} } | |
215 | }; | |
216 | int val; | |
217 | if (num_int_mod_timer > bd) { | |
218 | val = int_mod_timer[bd]; | |
219 | atl1_validate_option(&val, &opt, pdev); | |
220 | adapter->imt = (u16) val; | |
221 | } else | |
222 | adapter->imt = (u16) (opt.def); | |
223 | } | |
224 | } | |
225 | ||
f3cc28c7 JC |
226 | /* |
227 | * atl1_pci_tbl - PCI Device ID Table | |
228 | */ | |
229 | static const struct pci_device_id atl1_pci_tbl[] = { | |
e81e557a | 230 | {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1)}, |
f3cc28c7 JC |
231 | /* required last entry */ |
232 | {0,} | |
233 | }; | |
f3cc28c7 JC |
234 | MODULE_DEVICE_TABLE(pci, atl1_pci_tbl); |
235 | ||
460578bf JC |
236 | static const u32 atl1_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE | |
237 | NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP; | |
238 | ||
239 | static int debug = -1; | |
240 | module_param(debug, int, 0); | |
241 | MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)"); | |
242 | ||
f3cc28c7 | 243 | /* |
6446a860 JC |
244 | * Reset the transmit and receive units; mask and clear all interrupts. |
245 | * hw - Struct containing variables accessed by shared code | |
246 | * return : 0 or idle status (if error) | |
f3cc28c7 | 247 | */ |
6446a860 | 248 | static s32 atl1_reset_hw(struct atl1_hw *hw) |
f3cc28c7 | 249 | { |
6446a860 JC |
250 | struct pci_dev *pdev = hw->back->pdev; |
251 | struct atl1_adapter *adapter = hw->back; | |
252 | u32 icr; | |
253 | int i; | |
f3cc28c7 | 254 | |
6446a860 JC |
255 | /* |
256 | * Clear Interrupt mask to stop board from generating | |
257 | * interrupts & Clear any pending interrupt events | |
258 | */ | |
259 | /* | |
260 | * iowrite32(0, hw->hw_addr + REG_IMR); | |
261 | * iowrite32(0xffffffff, hw->hw_addr + REG_ISR); | |
262 | */ | |
f3cc28c7 | 263 | |
6446a860 JC |
264 | /* |
265 | * Issue Soft Reset to the MAC. This will reset the chip's | |
266 | * transmit, receive, DMA. It will not effect | |
267 | * the current PCI configuration. The global reset bit is self- | |
268 | * clearing, and should clear within a microsecond. | |
269 | */ | |
270 | iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL); | |
271 | ioread32(hw->hw_addr + REG_MASTER_CTRL); | |
f3cc28c7 | 272 | |
6446a860 JC |
273 | iowrite16(1, hw->hw_addr + REG_PHY_ENABLE); |
274 | ioread16(hw->hw_addr + REG_PHY_ENABLE); | |
f3cc28c7 | 275 | |
6446a860 JC |
276 | /* delay about 1ms */ |
277 | msleep(1); | |
f3cc28c7 | 278 | |
6446a860 JC |
279 | /* Wait at least 10ms for All module to be Idle */ |
280 | for (i = 0; i < 10; i++) { | |
281 | icr = ioread32(hw->hw_addr + REG_IDLE_STATUS); | |
282 | if (!icr) | |
283 | break; | |
284 | /* delay 1 ms */ | |
285 | msleep(1); | |
286 | /* FIXME: still the right way to do this? */ | |
287 | cpu_relax(); | |
288 | } | |
05ffdd7b | 289 | |
6446a860 JC |
290 | if (icr) { |
291 | if (netif_msg_hw(adapter)) | |
292 | dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr); | |
293 | return icr; | |
294 | } | |
05ffdd7b | 295 | |
6446a860 | 296 | return 0; |
05ffdd7b JC |
297 | } |
298 | ||
6446a860 JC |
299 | /* function about EEPROM |
300 | * | |
301 | * check_eeprom_exist | |
302 | * return 0 if eeprom exist | |
303 | */ | |
304 | static int atl1_check_eeprom_exist(struct atl1_hw *hw) | |
05ffdd7b | 305 | { |
6446a860 JC |
306 | u32 value; |
307 | value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); | |
308 | if (value & SPI_FLASH_CTRL_EN_VPD) { | |
309 | value &= ~SPI_FLASH_CTRL_EN_VPD; | |
310 | iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); | |
311 | } | |
05ffdd7b | 312 | |
6446a860 JC |
313 | value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST); |
314 | return ((value & 0xFF00) == 0x6C00) ? 0 : 1; | |
05ffdd7b JC |
315 | } |
316 | ||
6446a860 | 317 | static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value) |
05ffdd7b | 318 | { |
6446a860 JC |
319 | int i; |
320 | u32 control; | |
05ffdd7b | 321 | |
6446a860 JC |
322 | if (offset & 3) |
323 | /* address do not align */ | |
324 | return false; | |
05ffdd7b | 325 | |
6446a860 JC |
326 | iowrite32(0, hw->hw_addr + REG_VPD_DATA); |
327 | control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; | |
328 | iowrite32(control, hw->hw_addr + REG_VPD_CAP); | |
329 | ioread32(hw->hw_addr + REG_VPD_CAP); | |
05ffdd7b | 330 | |
6446a860 JC |
331 | for (i = 0; i < 10; i++) { |
332 | msleep(2); | |
333 | control = ioread32(hw->hw_addr + REG_VPD_CAP); | |
334 | if (control & VPD_CAP_VPD_FLAG) | |
335 | break; | |
336 | } | |
337 | if (control & VPD_CAP_VPD_FLAG) { | |
338 | *p_value = ioread32(hw->hw_addr + REG_VPD_DATA); | |
339 | return true; | |
340 | } | |
341 | /* timeout */ | |
342 | return false; | |
05ffdd7b JC |
343 | } |
344 | ||
f3cc28c7 | 345 | /* |
6446a860 JC |
346 | * Reads the value from a PHY register |
347 | * hw - Struct containing variables accessed by shared code | |
348 | * reg_addr - address of the PHY register to read | |
f3cc28c7 | 349 | */ |
6446a860 | 350 | s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data) |
f3cc28c7 | 351 | { |
6446a860 JC |
352 | u32 val; |
353 | int i; | |
f3cc28c7 | 354 | |
6446a860 JC |
355 | val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | |
356 | MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 << | |
357 | MDIO_CLK_SEL_SHIFT; | |
358 | iowrite32(val, hw->hw_addr + REG_MDIO_CTRL); | |
359 | ioread32(hw->hw_addr + REG_MDIO_CTRL); | |
f3cc28c7 | 360 | |
6446a860 JC |
361 | for (i = 0; i < MDIO_WAIT_TIMES; i++) { |
362 | udelay(2); | |
363 | val = ioread32(hw->hw_addr + REG_MDIO_CTRL); | |
364 | if (!(val & (MDIO_START | MDIO_BUSY))) | |
365 | break; | |
366 | } | |
367 | if (!(val & (MDIO_START | MDIO_BUSY))) { | |
368 | *phy_data = (u16) val; | |
369 | return 0; | |
f3cc28c7 | 370 | } |
6446a860 JC |
371 | return ATLX_ERR_PHY; |
372 | } | |
f3cc28c7 | 373 | |
6446a860 JC |
374 | #define CUSTOM_SPI_CS_SETUP 2 |
375 | #define CUSTOM_SPI_CLK_HI 2 | |
376 | #define CUSTOM_SPI_CLK_LO 2 | |
377 | #define CUSTOM_SPI_CS_HOLD 2 | |
378 | #define CUSTOM_SPI_CS_HI 3 | |
f3cc28c7 | 379 | |
6446a860 JC |
380 | static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf) |
381 | { | |
382 | int i; | |
383 | u32 value; | |
f3cc28c7 | 384 | |
6446a860 JC |
385 | iowrite32(0, hw->hw_addr + REG_SPI_DATA); |
386 | iowrite32(addr, hw->hw_addr + REG_SPI_ADDR); | |
2ca13da7 | 387 | |
6446a860 JC |
388 | value = SPI_FLASH_CTRL_WAIT_READY | |
389 | (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) << | |
390 | SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI & | |
391 | SPI_FLASH_CTRL_CLK_HI_MASK) << | |
392 | SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO & | |
393 | SPI_FLASH_CTRL_CLK_LO_MASK) << | |
394 | SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD & | |
395 | SPI_FLASH_CTRL_CS_HOLD_MASK) << | |
396 | SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI & | |
397 | SPI_FLASH_CTRL_CS_HI_MASK) << | |
398 | SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) << | |
399 | SPI_FLASH_CTRL_INS_SHIFT; | |
f3cc28c7 | 400 | |
6446a860 | 401 | iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); |
f3cc28c7 | 402 | |
6446a860 JC |
403 | value |= SPI_FLASH_CTRL_START; |
404 | iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); | |
405 | ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); | |
f3cc28c7 | 406 | |
6446a860 JC |
407 | for (i = 0; i < 10; i++) { |
408 | msleep(1); | |
409 | value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); | |
410 | if (!(value & SPI_FLASH_CTRL_START)) | |
411 | break; | |
412 | } | |
f3cc28c7 | 413 | |
6446a860 JC |
414 | if (value & SPI_FLASH_CTRL_START) |
415 | return false; | |
f3cc28c7 | 416 | |
6446a860 | 417 | *buf = ioread32(hw->hw_addr + REG_SPI_DATA); |
2ca13da7 | 418 | |
6446a860 | 419 | return true; |
f3cc28c7 JC |
420 | } |
421 | ||
f3cc28c7 | 422 | /* |
6446a860 JC |
423 | * get_permanent_address |
424 | * return 0 if get valid mac address, | |
f3cc28c7 | 425 | */ |
6446a860 | 426 | static int atl1_get_permanent_address(struct atl1_hw *hw) |
f3cc28c7 | 427 | { |
6446a860 JC |
428 | u32 addr[2]; |
429 | u32 i, control; | |
430 | u16 reg; | |
431 | u8 eth_addr[ETH_ALEN]; | |
432 | bool key_valid; | |
f3cc28c7 | 433 | |
6446a860 JC |
434 | if (is_valid_ether_addr(hw->perm_mac_addr)) |
435 | return 0; | |
436 | ||
437 | /* init */ | |
438 | addr[0] = addr[1] = 0; | |
439 | ||
440 | if (!atl1_check_eeprom_exist(hw)) { | |
441 | reg = 0; | |
442 | key_valid = false; | |
443 | /* Read out all EEPROM content */ | |
444 | i = 0; | |
445 | while (1) { | |
446 | if (atl1_read_eeprom(hw, i + 0x100, &control)) { | |
447 | if (key_valid) { | |
448 | if (reg == REG_MAC_STA_ADDR) | |
449 | addr[0] = control; | |
450 | else if (reg == (REG_MAC_STA_ADDR + 4)) | |
451 | addr[1] = control; | |
452 | key_valid = false; | |
453 | } else if ((control & 0xff) == 0x5A) { | |
454 | key_valid = true; | |
455 | reg = (u16) (control >> 16); | |
456 | } else | |
457 | break; | |
458 | } else | |
459 | /* read error */ | |
460 | break; | |
461 | i += 4; | |
05ffdd7b | 462 | } |
6446a860 JC |
463 | |
464 | *(u32 *) ð_addr[2] = swab32(addr[0]); | |
465 | *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]); | |
466 | if (is_valid_ether_addr(eth_addr)) { | |
467 | memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); | |
468 | return 0; | |
05ffdd7b JC |
469 | } |
470 | } | |
f3cc28c7 | 471 | |
6446a860 JC |
472 | /* see if SPI FLAGS exist ? */ |
473 | addr[0] = addr[1] = 0; | |
474 | reg = 0; | |
475 | key_valid = false; | |
476 | i = 0; | |
477 | while (1) { | |
478 | if (atl1_spi_read(hw, i + 0x1f000, &control)) { | |
479 | if (key_valid) { | |
480 | if (reg == REG_MAC_STA_ADDR) | |
481 | addr[0] = control; | |
482 | else if (reg == (REG_MAC_STA_ADDR + 4)) | |
483 | addr[1] = control; | |
484 | key_valid = false; | |
485 | } else if ((control & 0xff) == 0x5A) { | |
486 | key_valid = true; | |
487 | reg = (u16) (control >> 16); | |
488 | } else | |
489 | /* data end */ | |
490 | break; | |
491 | } else | |
492 | /* read error */ | |
493 | break; | |
494 | i += 4; | |
495 | } | |
f3cc28c7 | 496 | |
6446a860 JC |
497 | *(u32 *) ð_addr[2] = swab32(addr[0]); |
498 | *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]); | |
499 | if (is_valid_ether_addr(eth_addr)) { | |
500 | memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); | |
501 | return 0; | |
502 | } | |
f3cc28c7 | 503 | |
6446a860 JC |
504 | /* |
505 | * On some motherboards, the MAC address is written by the | |
506 | * BIOS directly to the MAC register during POST, and is | |
507 | * not stored in eeprom. If all else thus far has failed | |
508 | * to fetch the permanent MAC address, try reading it directly. | |
509 | */ | |
510 | addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR); | |
511 | addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4)); | |
512 | *(u32 *) ð_addr[2] = swab32(addr[0]); | |
513 | *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]); | |
514 | if (is_valid_ether_addr(eth_addr)) { | |
515 | memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); | |
516 | return 0; | |
517 | } | |
f3cc28c7 | 518 | |
6446a860 | 519 | return 1; |
f3cc28c7 JC |
520 | } |
521 | ||
05ffdd7b | 522 | /* |
6446a860 JC |
523 | * Reads the adapter's MAC address from the EEPROM |
524 | * hw - Struct containing variables accessed by shared code | |
05ffdd7b | 525 | */ |
9dc20f55 | 526 | static s32 atl1_read_mac_addr(struct atl1_hw *hw) |
f3cc28c7 | 527 | { |
6446a860 | 528 | u16 i; |
f3cc28c7 | 529 | |
6446a860 JC |
530 | if (atl1_get_permanent_address(hw)) |
531 | random_ether_addr(hw->perm_mac_addr); | |
f3cc28c7 | 532 | |
6446a860 JC |
533 | for (i = 0; i < ETH_ALEN; i++) |
534 | hw->mac_addr[i] = hw->perm_mac_addr[i]; | |
535 | return 0; | |
f3cc28c7 JC |
536 | } |
537 | ||
538 | /* | |
6446a860 JC |
539 | * Hashes an address to determine its location in the multicast table |
540 | * hw - Struct containing variables accessed by shared code | |
541 | * mc_addr - the multicast address to hash | |
05ffdd7b | 542 | * |
6446a860 JC |
543 | * atl1_hash_mc_addr |
544 | * purpose | |
545 | * set hash value for a multicast address | |
546 | * hash calcu processing : | |
547 | * 1. calcu 32bit CRC for multicast address | |
548 | * 2. reverse crc with MSB to LSB | |
f3cc28c7 | 549 | */ |
6446a860 | 550 | u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr) |
f3cc28c7 | 551 | { |
6446a860 JC |
552 | u32 crc32, value = 0; |
553 | int i; | |
f3cc28c7 | 554 | |
6446a860 JC |
555 | crc32 = ether_crc_le(6, mc_addr); |
556 | for (i = 0; i < 32; i++) | |
557 | value |= (((crc32 >> i) & 1) << (31 - i)); | |
f3cc28c7 | 558 | |
6446a860 | 559 | return value; |
f3cc28c7 JC |
560 | } |
561 | ||
6446a860 JC |
562 | /* |
563 | * Sets the bit in the multicast table corresponding to the hash value. | |
564 | * hw - Struct containing variables accessed by shared code | |
565 | * hash_value - Multicast address hash value | |
566 | */ | |
567 | void atl1_hash_set(struct atl1_hw *hw, u32 hash_value) | |
f3cc28c7 | 568 | { |
6446a860 JC |
569 | u32 hash_bit, hash_reg; |
570 | u32 mta; | |
571 | ||
572 | /* | |
573 | * The HASH Table is a register array of 2 32-bit registers. | |
574 | * It is treated like an array of 64 bits. We want to set | |
575 | * bit BitArray[hash_value]. So we figure out what register | |
576 | * the bit is in, read it, OR in the new bit, then write | |
577 | * back the new value. The register is determined by the | |
578 | * upper 7 bits of the hash value and the bit within that | |
579 | * register are determined by the lower 5 bits of the value. | |
05ffdd7b | 580 | */ |
6446a860 JC |
581 | hash_reg = (hash_value >> 31) & 0x1; |
582 | hash_bit = (hash_value >> 26) & 0x1F; | |
583 | mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2)); | |
584 | mta |= (1 << hash_bit); | |
585 | iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2)); | |
05ffdd7b | 586 | } |
f3cc28c7 | 587 | |
6446a860 JC |
588 | /* |
589 | * Writes a value to a PHY register | |
590 | * hw - Struct containing variables accessed by shared code | |
591 | * reg_addr - address of the PHY register to write | |
592 | * data - data to write to the PHY | |
593 | */ | |
594 | static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data) | |
05ffdd7b | 595 | { |
6446a860 JC |
596 | int i; |
597 | u32 val; | |
f3cc28c7 | 598 | |
6446a860 JC |
599 | val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | |
600 | (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | | |
601 | MDIO_SUP_PREAMBLE | | |
602 | MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; | |
603 | iowrite32(val, hw->hw_addr + REG_MDIO_CTRL); | |
604 | ioread32(hw->hw_addr + REG_MDIO_CTRL); | |
f3cc28c7 | 605 | |
6446a860 JC |
606 | for (i = 0; i < MDIO_WAIT_TIMES; i++) { |
607 | udelay(2); | |
608 | val = ioread32(hw->hw_addr + REG_MDIO_CTRL); | |
609 | if (!(val & (MDIO_START | MDIO_BUSY))) | |
610 | break; | |
05ffdd7b | 611 | } |
f3cc28c7 | 612 | |
6446a860 | 613 | if (!(val & (MDIO_START | MDIO_BUSY))) |
305282ba | 614 | return 0; |
f3cc28c7 | 615 | |
6446a860 JC |
616 | return ATLX_ERR_PHY; |
617 | } | |
f3cc28c7 | 618 | |
6446a860 JC |
619 | /* |
620 | * Make L001's PHY out of Power Saving State (bug) | |
621 | * hw - Struct containing variables accessed by shared code | |
622 | * when power on, L001's PHY always on Power saving State | |
623 | * (Gigabit Link forbidden) | |
624 | */ | |
625 | static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw) | |
626 | { | |
627 | s32 ret; | |
628 | ret = atl1_write_phy_reg(hw, 29, 0x0029); | |
629 | if (ret) | |
630 | return ret; | |
631 | return atl1_write_phy_reg(hw, 30, 0); | |
632 | } | |
633 | ||
6446a860 JC |
634 | /* |
635 | * Resets the PHY and make all config validate | |
636 | * hw - Struct containing variables accessed by shared code | |
637 | * | |
638 | * Sets bit 15 and 12 of the MII Control regiser (for F001 bug) | |
639 | */ | |
640 | static s32 atl1_phy_reset(struct atl1_hw *hw) | |
641 | { | |
642 | struct pci_dev *pdev = hw->back->pdev; | |
643 | struct atl1_adapter *adapter = hw->back; | |
644 | s32 ret_val; | |
645 | u16 phy_data; | |
646 | ||
647 | if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || | |
648 | hw->media_type == MEDIA_TYPE_1000M_FULL) | |
649 | phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; | |
650 | else { | |
05ffdd7b JC |
651 | switch (hw->media_type) { |
652 | case MEDIA_TYPE_100M_FULL: | |
6446a860 JC |
653 | phy_data = |
654 | MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 | | |
655 | MII_CR_RESET; | |
05ffdd7b JC |
656 | break; |
657 | case MEDIA_TYPE_100M_HALF: | |
658 | phy_data = MII_CR_SPEED_100 | MII_CR_RESET; | |
659 | break; | |
660 | case MEDIA_TYPE_10M_FULL: | |
661 | phy_data = | |
662 | MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET; | |
663 | break; | |
305282ba JC |
664 | default: |
665 | /* MEDIA_TYPE_10M_HALF: */ | |
05ffdd7b JC |
666 | phy_data = MII_CR_SPEED_10 | MII_CR_RESET; |
667 | break; | |
f3cc28c7 | 668 | } |
f3cc28c7 | 669 | } |
f3cc28c7 | 670 | |
6446a860 JC |
671 | ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data); |
672 | if (ret_val) { | |
673 | u32 val; | |
674 | int i; | |
675 | /* pcie serdes link may be down! */ | |
676 | if (netif_msg_hw(adapter)) | |
677 | dev_dbg(&pdev->dev, "pcie phy link down\n"); | |
678 | ||
679 | for (i = 0; i < 25; i++) { | |
680 | msleep(1); | |
681 | val = ioread32(hw->hw_addr + REG_MDIO_CTRL); | |
682 | if (!(val & (MDIO_START | MDIO_BUSY))) | |
683 | break; | |
684 | } | |
f3cc28c7 | 685 | |
6446a860 JC |
686 | if ((val & (MDIO_START | MDIO_BUSY)) != 0) { |
687 | if (netif_msg_hw(adapter)) | |
688 | dev_warn(&pdev->dev, | |
689 | "pcie link down at least 25ms\n"); | |
690 | return ret_val; | |
691 | } | |
692 | } | |
305282ba | 693 | return 0; |
2ca13da7 JC |
694 | } |
695 | ||
6446a860 JC |
696 | /* |
697 | * Configures PHY autoneg and flow control advertisement settings | |
698 | * hw - Struct containing variables accessed by shared code | |
699 | */ | |
700 | static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw) | |
05ffdd7b | 701 | { |
6446a860 JC |
702 | s32 ret_val; |
703 | s16 mii_autoneg_adv_reg; | |
704 | s16 mii_1000t_ctrl_reg; | |
f3cc28c7 | 705 | |
6446a860 JC |
706 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ |
707 | mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; | |
f3cc28c7 | 708 | |
6446a860 JC |
709 | /* Read the MII 1000Base-T Control Register (Address 9). */ |
710 | mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK; | |
f3cc28c7 | 711 | |
6446a860 JC |
712 | /* |
713 | * First we clear all the 10/100 mb speed bits in the Auto-Neg | |
714 | * Advertisement Register (Address 4) and the 1000 mb speed bits in | |
715 | * the 1000Base-T Control Register (Address 9). | |
716 | */ | |
717 | mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; | |
718 | mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK; | |
f3cc28c7 | 719 | |
6446a860 JC |
720 | /* |
721 | * Need to parse media_type and set up | |
722 | * the appropriate PHY registers. | |
723 | */ | |
724 | switch (hw->media_type) { | |
725 | case MEDIA_TYPE_AUTO_SENSOR: | |
726 | mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS | | |
727 | MII_AR_10T_FD_CAPS | | |
728 | MII_AR_100TX_HD_CAPS | | |
729 | MII_AR_100TX_FD_CAPS); | |
730 | mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS; | |
731 | break; | |
f3cc28c7 | 732 | |
6446a860 JC |
733 | case MEDIA_TYPE_1000M_FULL: |
734 | mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS; | |
735 | break; | |
f3cc28c7 | 736 | |
6446a860 JC |
737 | case MEDIA_TYPE_100M_FULL: |
738 | mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS; | |
739 | break; | |
f3cc28c7 | 740 | |
6446a860 JC |
741 | case MEDIA_TYPE_100M_HALF: |
742 | mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS; | |
743 | break; | |
f3cc28c7 | 744 | |
6446a860 JC |
745 | case MEDIA_TYPE_10M_FULL: |
746 | mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS; | |
05ffdd7b | 747 | break; |
6446a860 | 748 | |
05ffdd7b | 749 | default: |
6446a860 | 750 | mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS; |
05ffdd7b | 751 | break; |
f3cc28c7 | 752 | } |
f3cc28c7 | 753 | |
6446a860 JC |
754 | /* flow control fixed to enable all */ |
755 | mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); | |
f3cc28c7 | 756 | |
6446a860 JC |
757 | hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; |
758 | hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg; | |
f3cc28c7 | 759 | |
6446a860 JC |
760 | ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); |
761 | if (ret_val) | |
762 | return ret_val; | |
f3cc28c7 | 763 | |
6446a860 JC |
764 | ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg); |
765 | if (ret_val) | |
766 | return ret_val; | |
f3cc28c7 | 767 | |
6446a860 | 768 | return 0; |
f3cc28c7 | 769 | } |
f3cc28c7 | 770 | |
05ffdd7b | 771 | /* |
6446a860 JC |
772 | * Configures link settings. |
773 | * hw - Struct containing variables accessed by shared code | |
774 | * Assumes the hardware has previously been reset and the | |
775 | * transmitter and receiver are not enabled. | |
05ffdd7b | 776 | */ |
6446a860 | 777 | static s32 atl1_setup_link(struct atl1_hw *hw) |
f3cc28c7 | 778 | { |
6446a860 JC |
779 | struct pci_dev *pdev = hw->back->pdev; |
780 | struct atl1_adapter *adapter = hw->back; | |
781 | s32 ret_val; | |
f3cc28c7 | 782 | |
6446a860 JC |
783 | /* |
784 | * Options: | |
785 | * PHY will advertise value(s) parsed from | |
786 | * autoneg_advertised and fc | |
787 | * no matter what autoneg is , We will not wait link result. | |
788 | */ | |
789 | ret_val = atl1_phy_setup_autoneg_adv(hw); | |
790 | if (ret_val) { | |
791 | if (netif_msg_link(adapter)) | |
792 | dev_dbg(&pdev->dev, | |
793 | "error setting up autonegotiation\n"); | |
794 | return ret_val; | |
795 | } | |
796 | /* SW.Reset , En-Auto-Neg if needed */ | |
797 | ret_val = atl1_phy_reset(hw); | |
798 | if (ret_val) { | |
799 | if (netif_msg_link(adapter)) | |
800 | dev_dbg(&pdev->dev, "error resetting phy\n"); | |
801 | return ret_val; | |
802 | } | |
803 | hw->phy_configured = true; | |
804 | return ret_val; | |
805 | } | |
f3cc28c7 | 806 | |
6446a860 | 807 | static void atl1_init_flash_opcode(struct atl1_hw *hw) |
f3cc28c7 | 808 | { |
6446a860 JC |
809 | if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) |
810 | /* Atmel */ | |
811 | hw->flash_vendor = 0; | |
f3cc28c7 | 812 | |
6446a860 JC |
813 | /* Init OP table */ |
814 | iowrite8(flash_table[hw->flash_vendor].cmd_program, | |
815 | hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM); | |
816 | iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase, | |
817 | hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE); | |
818 | iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase, | |
819 | hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE); | |
820 | iowrite8(flash_table[hw->flash_vendor].cmd_rdid, | |
821 | hw->hw_addr + REG_SPI_FLASH_OP_RDID); | |
822 | iowrite8(flash_table[hw->flash_vendor].cmd_wren, | |
823 | hw->hw_addr + REG_SPI_FLASH_OP_WREN); | |
824 | iowrite8(flash_table[hw->flash_vendor].cmd_rdsr, | |
825 | hw->hw_addr + REG_SPI_FLASH_OP_RDSR); | |
826 | iowrite8(flash_table[hw->flash_vendor].cmd_wrsr, | |
827 | hw->hw_addr + REG_SPI_FLASH_OP_WRSR); | |
828 | iowrite8(flash_table[hw->flash_vendor].cmd_read, | |
829 | hw->hw_addr + REG_SPI_FLASH_OP_READ); | |
f3cc28c7 | 830 | } |
f3cc28c7 | 831 | |
6446a860 JC |
832 | /* |
833 | * Performs basic configuration of the adapter. | |
834 | * hw - Struct containing variables accessed by shared code | |
835 | * Assumes that the controller has previously been reset and is in a | |
836 | * post-reset uninitialized state. Initializes multicast table, | |
837 | * and Calls routines to setup link | |
838 | * Leaves the transmit and receive units disabled and uninitialized. | |
839 | */ | |
840 | static s32 atl1_init_hw(struct atl1_hw *hw) | |
05ffdd7b | 841 | { |
6446a860 | 842 | u32 ret_val = 0; |
f3cc28c7 | 843 | |
6446a860 JC |
844 | /* Zero out the Multicast HASH table */ |
845 | iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE); | |
846 | /* clear the old settings from the multicast hash table */ | |
847 | iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2)); | |
f3cc28c7 | 848 | |
6446a860 | 849 | atl1_init_flash_opcode(hw); |
f3cc28c7 | 850 | |
6446a860 JC |
851 | if (!hw->phy_configured) { |
852 | /* enable GPHY LinkChange Interrrupt */ | |
853 | ret_val = atl1_write_phy_reg(hw, 18, 0xC00); | |
854 | if (ret_val) | |
855 | return ret_val; | |
856 | /* make PHY out of power-saving state */ | |
857 | ret_val = atl1_phy_leave_power_saving(hw); | |
858 | if (ret_val) | |
859 | return ret_val; | |
860 | /* Call a subroutine to configure the link */ | |
861 | ret_val = atl1_setup_link(hw); | |
862 | } | |
863 | return ret_val; | |
f3cc28c7 | 864 | } |
f3cc28c7 JC |
865 | |
866 | /* | |
6446a860 JC |
867 | * Detects the current speed and duplex settings of the hardware. |
868 | * hw - Struct containing variables accessed by shared code | |
869 | * speed - Speed of the connection | |
870 | * duplex - Duplex setting of the connection | |
f3cc28c7 | 871 | */ |
6446a860 | 872 | static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex) |
f3cc28c7 | 873 | { |
6446a860 JC |
874 | struct pci_dev *pdev = hw->back->pdev; |
875 | struct atl1_adapter *adapter = hw->back; | |
876 | s32 ret_val; | |
877 | u16 phy_data; | |
f3cc28c7 | 878 | |
6446a860 JC |
879 | /* ; --- Read PHY Specific Status Register (17) */ |
880 | ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data); | |
881 | if (ret_val) | |
882 | return ret_val; | |
f3cc28c7 | 883 | |
6446a860 JC |
884 | if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED)) |
885 | return ATLX_ERR_PHY_RES; | |
f3cc28c7 | 886 | |
6446a860 JC |
887 | switch (phy_data & MII_ATLX_PSSR_SPEED) { |
888 | case MII_ATLX_PSSR_1000MBS: | |
889 | *speed = SPEED_1000; | |
890 | break; | |
891 | case MII_ATLX_PSSR_100MBS: | |
892 | *speed = SPEED_100; | |
893 | break; | |
894 | case MII_ATLX_PSSR_10MBS: | |
895 | *speed = SPEED_10; | |
896 | break; | |
897 | default: | |
898 | if (netif_msg_hw(adapter)) | |
899 | dev_dbg(&pdev->dev, "error getting speed\n"); | |
900 | return ATLX_ERR_PHY_SPEED; | |
901 | break; | |
f3cc28c7 | 902 | } |
6446a860 JC |
903 | if (phy_data & MII_ATLX_PSSR_DPLX) |
904 | *duplex = FULL_DUPLEX; | |
905 | else | |
906 | *duplex = HALF_DUPLEX; | |
907 | ||
908 | return 0; | |
05ffdd7b | 909 | } |
f3cc28c7 | 910 | |
6446a860 | 911 | void atl1_set_mac_addr(struct atl1_hw *hw) |
05ffdd7b | 912 | { |
6446a860 JC |
913 | u32 value; |
914 | /* | |
915 | * 00-0B-6A-F6-00-DC | |
916 | * 0: 6AF600DC 1: 000B | |
917 | * low dword | |
918 | */ | |
919 | value = (((u32) hw->mac_addr[2]) << 24) | | |
920 | (((u32) hw->mac_addr[3]) << 16) | | |
921 | (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5])); | |
922 | iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR); | |
923 | /* high dword */ | |
924 | value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1])); | |
925 | iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2)); | |
05ffdd7b | 926 | } |
f3cc28c7 JC |
927 | |
928 | /* | |
929 | * atl1_sw_init - Initialize general software structures (struct atl1_adapter) | |
930 | * @adapter: board private structure to initialize | |
931 | * | |
932 | * atl1_sw_init initializes the Adapter private data structure. | |
933 | * Fields are initialized based on PCI device information and | |
934 | * OS network device settings (MTU size). | |
935 | */ | |
936 | static int __devinit atl1_sw_init(struct atl1_adapter *adapter) | |
937 | { | |
938 | struct atl1_hw *hw = &adapter->hw; | |
939 | struct net_device *netdev = adapter->netdev; | |
f3cc28c7 | 940 | |
2a49128f | 941 | hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; |
a3093d9b | 942 | hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; |
f3cc28c7 JC |
943 | |
944 | adapter->wol = 0; | |
945 | adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7; | |
6446a860 | 946 | adapter->ict = 50000; /* 100ms */ |
f3cc28c7 JC |
947 | adapter->link_speed = SPEED_0; /* hardware init */ |
948 | adapter->link_duplex = FULL_DUPLEX; | |
949 | ||
950 | hw->phy_configured = false; | |
951 | hw->preamble_len = 7; | |
952 | hw->ipgt = 0x60; | |
953 | hw->min_ifg = 0x50; | |
954 | hw->ipgr1 = 0x40; | |
955 | hw->ipgr2 = 0x60; | |
956 | hw->max_retry = 0xf; | |
957 | hw->lcol = 0x37; | |
958 | hw->jam_ipg = 7; | |
959 | hw->rfd_burst = 8; | |
960 | hw->rrd_burst = 8; | |
961 | hw->rfd_fetch_gap = 1; | |
962 | hw->rx_jumbo_th = adapter->rx_buffer_len / 8; | |
963 | hw->rx_jumbo_lkah = 1; | |
964 | hw->rrd_ret_timer = 16; | |
965 | hw->tpd_burst = 4; | |
966 | hw->tpd_fetch_th = 16; | |
967 | hw->txf_burst = 0x100; | |
968 | hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3; | |
969 | hw->tpd_fetch_gap = 1; | |
970 | hw->rcb_value = atl1_rcb_64; | |
971 | hw->dma_ord = atl1_dma_ord_enh; | |
972 | hw->dmar_block = atl1_dma_req_256; | |
973 | hw->dmaw_block = atl1_dma_req_256; | |
974 | hw->cmb_rrd = 4; | |
975 | hw->cmb_tpd = 4; | |
976 | hw->cmb_rx_timer = 1; /* about 2us */ | |
977 | hw->cmb_tx_timer = 1; /* about 2us */ | |
978 | hw->smb_timer = 100000; /* about 200ms */ | |
979 | ||
f3cc28c7 JC |
980 | spin_lock_init(&adapter->lock); |
981 | spin_lock_init(&adapter->mb_lock); | |
982 | ||
983 | return 0; | |
984 | } | |
985 | ||
05ffdd7b JC |
986 | static int mdio_read(struct net_device *netdev, int phy_id, int reg_num) |
987 | { | |
988 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
989 | u16 result; | |
990 | ||
991 | atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result); | |
992 | ||
993 | return result; | |
994 | } | |
995 | ||
996 | static void mdio_write(struct net_device *netdev, int phy_id, int reg_num, | |
997 | int val) | |
998 | { | |
999 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
1000 | ||
1001 | atl1_write_phy_reg(&adapter->hw, reg_num, val); | |
1002 | } | |
1003 | ||
1004 | /* | |
1005 | * atl1_mii_ioctl - | |
1006 | * @netdev: | |
1007 | * @ifreq: | |
1008 | * @cmd: | |
1009 | */ | |
1010 | static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
1011 | { | |
1012 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
1013 | unsigned long flags; | |
1014 | int retval; | |
1015 | ||
1016 | if (!netif_running(netdev)) | |
1017 | return -EINVAL; | |
1018 | ||
1019 | spin_lock_irqsave(&adapter->lock, flags); | |
1020 | retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL); | |
1021 | spin_unlock_irqrestore(&adapter->lock, flags); | |
1022 | ||
1023 | return retval; | |
1024 | } | |
1025 | ||
f3cc28c7 JC |
1026 | /* |
1027 | * atl1_setup_mem_resources - allocate Tx / RX descriptor resources | |
1028 | * @adapter: board private structure | |
1029 | * | |
1030 | * Return 0 on success, negative on failure | |
1031 | */ | |
6446a860 | 1032 | static s32 atl1_setup_ring_resources(struct atl1_adapter *adapter) |
f3cc28c7 JC |
1033 | { |
1034 | struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; | |
1035 | struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; | |
1036 | struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; | |
1037 | struct atl1_ring_header *ring_header = &adapter->ring_header; | |
1038 | struct pci_dev *pdev = adapter->pdev; | |
1039 | int size; | |
1040 | u8 offset = 0; | |
1041 | ||
1042 | size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count); | |
1043 | tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL); | |
1044 | if (unlikely(!tpd_ring->buffer_info)) { | |
6446a860 JC |
1045 | if (netif_msg_drv(adapter)) |
1046 | dev_err(&pdev->dev, "kzalloc failed , size = D%d\n", | |
1047 | size); | |
f3cc28c7 JC |
1048 | goto err_nomem; |
1049 | } | |
1050 | rfd_ring->buffer_info = | |
53ffb42c | 1051 | (struct atl1_buffer *)(tpd_ring->buffer_info + tpd_ring->count); |
f3cc28c7 | 1052 | |
6446a860 JC |
1053 | /* |
1054 | * real ring DMA buffer | |
53ffb42c JC |
1055 | * each ring/block may need up to 8 bytes for alignment, hence the |
1056 | * additional 40 bytes tacked onto the end. | |
1057 | */ | |
1058 | ring_header->size = size = | |
1059 | sizeof(struct tx_packet_desc) * tpd_ring->count | |
1060 | + sizeof(struct rx_free_desc) * rfd_ring->count | |
1061 | + sizeof(struct rx_return_desc) * rrd_ring->count | |
1062 | + sizeof(struct coals_msg_block) | |
1063 | + sizeof(struct stats_msg_block) | |
1064 | + 40; | |
f3cc28c7 JC |
1065 | |
1066 | ring_header->desc = pci_alloc_consistent(pdev, ring_header->size, | |
53ffb42c | 1067 | &ring_header->dma); |
f3cc28c7 | 1068 | if (unlikely(!ring_header->desc)) { |
6446a860 JC |
1069 | if (netif_msg_drv(adapter)) |
1070 | dev_err(&pdev->dev, "pci_alloc_consistent failed\n"); | |
f3cc28c7 JC |
1071 | goto err_nomem; |
1072 | } | |
1073 | ||
1074 | memset(ring_header->desc, 0, ring_header->size); | |
1075 | ||
1076 | /* init TPD ring */ | |
1077 | tpd_ring->dma = ring_header->dma; | |
1078 | offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0; | |
1079 | tpd_ring->dma += offset; | |
1080 | tpd_ring->desc = (u8 *) ring_header->desc + offset; | |
1081 | tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count; | |
f3cc28c7 JC |
1082 | |
1083 | /* init RFD ring */ | |
1084 | rfd_ring->dma = tpd_ring->dma + tpd_ring->size; | |
1085 | offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0; | |
1086 | rfd_ring->dma += offset; | |
1087 | rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset); | |
1088 | rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count; | |
2ca13da7 | 1089 | |
f3cc28c7 JC |
1090 | |
1091 | /* init RRD ring */ | |
1092 | rrd_ring->dma = rfd_ring->dma + rfd_ring->size; | |
1093 | offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0; | |
1094 | rrd_ring->dma += offset; | |
1095 | rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset); | |
1096 | rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count; | |
2ca13da7 | 1097 | |
f3cc28c7 JC |
1098 | |
1099 | /* init CMB */ | |
1100 | adapter->cmb.dma = rrd_ring->dma + rrd_ring->size; | |
1101 | offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0; | |
1102 | adapter->cmb.dma += offset; | |
53ffb42c JC |
1103 | adapter->cmb.cmb = (struct coals_msg_block *) |
1104 | ((u8 *) rrd_ring->desc + (rrd_ring->size + offset)); | |
f3cc28c7 JC |
1105 | |
1106 | /* init SMB */ | |
1107 | adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block); | |
1108 | offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0; | |
1109 | adapter->smb.dma += offset; | |
1110 | adapter->smb.smb = (struct stats_msg_block *) | |
53ffb42c JC |
1111 | ((u8 *) adapter->cmb.cmb + |
1112 | (sizeof(struct coals_msg_block) + offset)); | |
f3cc28c7 | 1113 | |
6446a860 | 1114 | return 0; |
f3cc28c7 JC |
1115 | |
1116 | err_nomem: | |
1117 | kfree(tpd_ring->buffer_info); | |
1118 | return -ENOMEM; | |
1119 | } | |
1120 | ||
3d2557f6 | 1121 | static void atl1_init_ring_ptrs(struct atl1_adapter *adapter) |
f3cc28c7 | 1122 | { |
2ca13da7 JC |
1123 | struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; |
1124 | struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; | |
1125 | struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; | |
f3cc28c7 | 1126 | |
2ca13da7 JC |
1127 | atomic_set(&tpd_ring->next_to_use, 0); |
1128 | atomic_set(&tpd_ring->next_to_clean, 0); | |
f3cc28c7 | 1129 | |
2ca13da7 JC |
1130 | rfd_ring->next_to_clean = 0; |
1131 | atomic_set(&rfd_ring->next_to_use, 0); | |
1132 | ||
1133 | rrd_ring->next_to_use = 0; | |
1134 | atomic_set(&rrd_ring->next_to_clean, 0); | |
f3cc28c7 JC |
1135 | } |
1136 | ||
f3cc28c7 | 1137 | /* |
05ffdd7b | 1138 | * atl1_clean_rx_ring - Free RFD Buffers |
f3cc28c7 JC |
1139 | * @adapter: board private structure |
1140 | */ | |
05ffdd7b | 1141 | static void atl1_clean_rx_ring(struct atl1_adapter *adapter) |
f3cc28c7 | 1142 | { |
05ffdd7b JC |
1143 | struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; |
1144 | struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; | |
1145 | struct atl1_buffer *buffer_info; | |
1146 | struct pci_dev *pdev = adapter->pdev; | |
1147 | unsigned long size; | |
1148 | unsigned int i; | |
f3cc28c7 | 1149 | |
05ffdd7b JC |
1150 | /* Free all the Rx ring sk_buffs */ |
1151 | for (i = 0; i < rfd_ring->count; i++) { | |
1152 | buffer_info = &rfd_ring->buffer_info[i]; | |
1153 | if (buffer_info->dma) { | |
1154 | pci_unmap_page(pdev, buffer_info->dma, | |
1155 | buffer_info->length, PCI_DMA_FROMDEVICE); | |
1156 | buffer_info->dma = 0; | |
1157 | } | |
1158 | if (buffer_info->skb) { | |
1159 | dev_kfree_skb(buffer_info->skb); | |
1160 | buffer_info->skb = NULL; | |
1161 | } | |
1162 | } | |
f3cc28c7 | 1163 | |
05ffdd7b JC |
1164 | size = sizeof(struct atl1_buffer) * rfd_ring->count; |
1165 | memset(rfd_ring->buffer_info, 0, size); | |
f3cc28c7 | 1166 | |
05ffdd7b JC |
1167 | /* Zero out the descriptor ring */ |
1168 | memset(rfd_ring->desc, 0, rfd_ring->size); | |
f3cc28c7 | 1169 | |
05ffdd7b JC |
1170 | rfd_ring->next_to_clean = 0; |
1171 | atomic_set(&rfd_ring->next_to_use, 0); | |
f3cc28c7 | 1172 | |
05ffdd7b JC |
1173 | rrd_ring->next_to_use = 0; |
1174 | atomic_set(&rrd_ring->next_to_clean, 0); | |
f3cc28c7 JC |
1175 | } |
1176 | ||
05ffdd7b JC |
1177 | /* |
1178 | * atl1_clean_tx_ring - Free Tx Buffers | |
1179 | * @adapter: board private structure | |
1180 | */ | |
1181 | static void atl1_clean_tx_ring(struct atl1_adapter *adapter) | |
f3cc28c7 | 1182 | { |
05ffdd7b JC |
1183 | struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; |
1184 | struct atl1_buffer *buffer_info; | |
53ffb42c | 1185 | struct pci_dev *pdev = adapter->pdev; |
05ffdd7b JC |
1186 | unsigned long size; |
1187 | unsigned int i; | |
f3cc28c7 | 1188 | |
05ffdd7b JC |
1189 | /* Free all the Tx ring sk_buffs */ |
1190 | for (i = 0; i < tpd_ring->count; i++) { | |
1191 | buffer_info = &tpd_ring->buffer_info[i]; | |
1192 | if (buffer_info->dma) { | |
1193 | pci_unmap_page(pdev, buffer_info->dma, | |
1194 | buffer_info->length, PCI_DMA_TODEVICE); | |
1195 | buffer_info->dma = 0; | |
f3cc28c7 JC |
1196 | } |
1197 | } | |
1198 | ||
05ffdd7b JC |
1199 | for (i = 0; i < tpd_ring->count; i++) { |
1200 | buffer_info = &tpd_ring->buffer_info[i]; | |
1201 | if (buffer_info->skb) { | |
1202 | dev_kfree_skb_any(buffer_info->skb); | |
1203 | buffer_info->skb = NULL; | |
f3cc28c7 | 1204 | } |
f3cc28c7 JC |
1205 | } |
1206 | ||
05ffdd7b JC |
1207 | size = sizeof(struct atl1_buffer) * tpd_ring->count; |
1208 | memset(tpd_ring->buffer_info, 0, size); | |
f3cc28c7 | 1209 | |
05ffdd7b JC |
1210 | /* Zero out the descriptor ring */ |
1211 | memset(tpd_ring->desc, 0, tpd_ring->size); | |
f3cc28c7 | 1212 | |
05ffdd7b JC |
1213 | atomic_set(&tpd_ring->next_to_use, 0); |
1214 | atomic_set(&tpd_ring->next_to_clean, 0); | |
f3cc28c7 JC |
1215 | } |
1216 | ||
1217 | /* | |
05ffdd7b JC |
1218 | * atl1_free_ring_resources - Free Tx / RX descriptor Resources |
1219 | * @adapter: board private structure | |
1220 | * | |
1221 | * Free all transmit software resources | |
f3cc28c7 | 1222 | */ |
6446a860 | 1223 | static void atl1_free_ring_resources(struct atl1_adapter *adapter) |
f3cc28c7 | 1224 | { |
f3cc28c7 | 1225 | struct pci_dev *pdev = adapter->pdev; |
05ffdd7b JC |
1226 | struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; |
1227 | struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; | |
1228 | struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; | |
1229 | struct atl1_ring_header *ring_header = &adapter->ring_header; | |
f3cc28c7 | 1230 | |
05ffdd7b JC |
1231 | atl1_clean_tx_ring(adapter); |
1232 | atl1_clean_rx_ring(adapter); | |
f3cc28c7 | 1233 | |
05ffdd7b JC |
1234 | kfree(tpd_ring->buffer_info); |
1235 | pci_free_consistent(pdev, ring_header->size, ring_header->desc, | |
1236 | ring_header->dma); | |
f3cc28c7 | 1237 | |
05ffdd7b JC |
1238 | tpd_ring->buffer_info = NULL; |
1239 | tpd_ring->desc = NULL; | |
1240 | tpd_ring->dma = 0; | |
f3cc28c7 | 1241 | |
05ffdd7b JC |
1242 | rfd_ring->buffer_info = NULL; |
1243 | rfd_ring->desc = NULL; | |
1244 | rfd_ring->dma = 0; | |
f3cc28c7 | 1245 | |
05ffdd7b JC |
1246 | rrd_ring->desc = NULL; |
1247 | rrd_ring->dma = 0; | |
f3cc28c7 JC |
1248 | } |
1249 | ||
05ffdd7b | 1250 | static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter) |
f3cc28c7 | 1251 | { |
f3cc28c7 | 1252 | u32 value; |
05ffdd7b JC |
1253 | struct atl1_hw *hw = &adapter->hw; |
1254 | struct net_device *netdev = adapter->netdev; | |
1255 | /* Config MAC CTRL Register */ | |
1256 | value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN; | |
1257 | /* duplex */ | |
1258 | if (FULL_DUPLEX == adapter->link_duplex) | |
1259 | value |= MAC_CTRL_DUPLX; | |
1260 | /* speed */ | |
1261 | value |= ((u32) ((SPEED_1000 == adapter->link_speed) ? | |
1262 | MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) << | |
1263 | MAC_CTRL_SPEED_SHIFT); | |
1264 | /* flow control */ | |
1265 | value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); | |
1266 | /* PAD & CRC */ | |
1267 | value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); | |
1268 | /* preamble length */ | |
1269 | value |= (((u32) adapter->hw.preamble_len | |
1270 | & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); | |
1271 | /* vlan */ | |
1272 | if (adapter->vlgrp) | |
1273 | value |= MAC_CTRL_RMV_VLAN; | |
1274 | /* rx checksum | |
1275 | if (adapter->rx_csum) | |
1276 | value |= MAC_CTRL_RX_CHKSUM_EN; | |
1277 | */ | |
1278 | /* filter mode */ | |
1279 | value |= MAC_CTRL_BC_EN; | |
1280 | if (netdev->flags & IFF_PROMISC) | |
1281 | value |= MAC_CTRL_PROMIS_EN; | |
1282 | else if (netdev->flags & IFF_ALLMULTI) | |
1283 | value |= MAC_CTRL_MC_ALL_EN; | |
1284 | /* value |= MAC_CTRL_LOOPBACK; */ | |
1285 | iowrite32(value, hw->hw_addr + REG_MAC_CTRL); | |
1286 | } | |
f3cc28c7 | 1287 | |
05ffdd7b JC |
1288 | static u32 atl1_check_link(struct atl1_adapter *adapter) |
1289 | { | |
1290 | struct atl1_hw *hw = &adapter->hw; | |
1291 | struct net_device *netdev = adapter->netdev; | |
1292 | u32 ret_val; | |
1293 | u16 speed, duplex, phy_data; | |
1294 | int reconfig = 0; | |
f3cc28c7 | 1295 | |
05ffdd7b JC |
1296 | /* MII_BMSR must read twice */ |
1297 | atl1_read_phy_reg(hw, MII_BMSR, &phy_data); | |
1298 | atl1_read_phy_reg(hw, MII_BMSR, &phy_data); | |
6446a860 JC |
1299 | if (!(phy_data & BMSR_LSTATUS)) { |
1300 | /* link down */ | |
1301 | if (netif_carrier_ok(netdev)) { | |
1302 | /* old link state: Up */ | |
1303 | if (netif_msg_link(adapter)) | |
1304 | dev_info(&adapter->pdev->dev, "link is down\n"); | |
05ffdd7b JC |
1305 | adapter->link_speed = SPEED_0; |
1306 | netif_carrier_off(netdev); | |
f3cc28c7 | 1307 | } |
6446a860 | 1308 | return 0; |
f3cc28c7 JC |
1309 | } |
1310 | ||
05ffdd7b JC |
1311 | /* Link Up */ |
1312 | ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex); | |
1313 | if (ret_val) | |
1314 | return ret_val; | |
f3cc28c7 | 1315 | |
05ffdd7b JC |
1316 | switch (hw->media_type) { |
1317 | case MEDIA_TYPE_1000M_FULL: | |
1318 | if (speed != SPEED_1000 || duplex != FULL_DUPLEX) | |
1319 | reconfig = 1; | |
1320 | break; | |
1321 | case MEDIA_TYPE_100M_FULL: | |
1322 | if (speed != SPEED_100 || duplex != FULL_DUPLEX) | |
1323 | reconfig = 1; | |
1324 | break; | |
1325 | case MEDIA_TYPE_100M_HALF: | |
1326 | if (speed != SPEED_100 || duplex != HALF_DUPLEX) | |
1327 | reconfig = 1; | |
1328 | break; | |
1329 | case MEDIA_TYPE_10M_FULL: | |
1330 | if (speed != SPEED_10 || duplex != FULL_DUPLEX) | |
1331 | reconfig = 1; | |
1332 | break; | |
1333 | case MEDIA_TYPE_10M_HALF: | |
1334 | if (speed != SPEED_10 || duplex != HALF_DUPLEX) | |
1335 | reconfig = 1; | |
1336 | break; | |
1337 | } | |
f3cc28c7 | 1338 | |
05ffdd7b JC |
1339 | /* link result is our setting */ |
1340 | if (!reconfig) { | |
1341 | if (adapter->link_speed != speed | |
1342 | || adapter->link_duplex != duplex) { | |
1343 | adapter->link_speed = speed; | |
1344 | adapter->link_duplex = duplex; | |
1345 | atl1_setup_mac_ctrl(adapter); | |
6446a860 JC |
1346 | if (netif_msg_link(adapter)) |
1347 | dev_info(&adapter->pdev->dev, | |
1348 | "%s link is up %d Mbps %s\n", | |
1349 | netdev->name, adapter->link_speed, | |
1350 | adapter->link_duplex == FULL_DUPLEX ? | |
1351 | "full duplex" : "half duplex"); | |
05ffdd7b | 1352 | } |
6446a860 JC |
1353 | if (!netif_carrier_ok(netdev)) { |
1354 | /* Link down -> Up */ | |
05ffdd7b | 1355 | netif_carrier_on(netdev); |
05ffdd7b | 1356 | } |
6446a860 | 1357 | return 0; |
f3cc28c7 | 1358 | } |
f3cc28c7 | 1359 | |
6446a860 | 1360 | /* change original link status */ |
05ffdd7b JC |
1361 | if (netif_carrier_ok(netdev)) { |
1362 | adapter->link_speed = SPEED_0; | |
1363 | netif_carrier_off(netdev); | |
1364 | netif_stop_queue(netdev); | |
f3cc28c7 | 1365 | } |
f3cc28c7 | 1366 | |
05ffdd7b JC |
1367 | if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR && |
1368 | hw->media_type != MEDIA_TYPE_1000M_FULL) { | |
1369 | switch (hw->media_type) { | |
1370 | case MEDIA_TYPE_100M_FULL: | |
1371 | phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 | | |
1372 | MII_CR_RESET; | |
1373 | break; | |
1374 | case MEDIA_TYPE_100M_HALF: | |
1375 | phy_data = MII_CR_SPEED_100 | MII_CR_RESET; | |
1376 | break; | |
1377 | case MEDIA_TYPE_10M_FULL: | |
1378 | phy_data = | |
1379 | MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET; | |
1380 | break; | |
6446a860 JC |
1381 | default: |
1382 | /* MEDIA_TYPE_10M_HALF: */ | |
05ffdd7b JC |
1383 | phy_data = MII_CR_SPEED_10 | MII_CR_RESET; |
1384 | break; | |
f3cc28c7 | 1385 | } |
05ffdd7b | 1386 | atl1_write_phy_reg(hw, MII_BMCR, phy_data); |
6446a860 | 1387 | return 0; |
f3cc28c7 | 1388 | } |
f3cc28c7 | 1389 | |
05ffdd7b JC |
1390 | /* auto-neg, insert timer to re-config phy */ |
1391 | if (!adapter->phy_timer_pending) { | |
1392 | adapter->phy_timer_pending = true; | |
e053b628 SH |
1393 | mod_timer(&adapter->phy_config_timer, |
1394 | round_jiffies(jiffies + 3 * HZ)); | |
f3cc28c7 | 1395 | } |
f3cc28c7 | 1396 | |
05ffdd7b JC |
1397 | return 0; |
1398 | } | |
f3cc28c7 | 1399 | |
05ffdd7b JC |
1400 | static void set_flow_ctrl_old(struct atl1_adapter *adapter) |
1401 | { | |
1402 | u32 hi, lo, value; | |
f3cc28c7 | 1403 | |
05ffdd7b JC |
1404 | /* RFD Flow Control */ |
1405 | value = adapter->rfd_ring.count; | |
1406 | hi = value / 16; | |
1407 | if (hi < 2) | |
1408 | hi = 2; | |
1409 | lo = value * 7 / 8; | |
f3cc28c7 | 1410 | |
05ffdd7b JC |
1411 | value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) | |
1412 | ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT); | |
1413 | iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH); | |
f3cc28c7 | 1414 | |
05ffdd7b JC |
1415 | /* RRD Flow Control */ |
1416 | value = adapter->rrd_ring.count; | |
1417 | lo = value / 16; | |
1418 | hi = value * 7 / 8; | |
1419 | if (lo < 2) | |
1420 | lo = 2; | |
1421 | value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) | | |
1422 | ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT); | |
1423 | iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH); | |
1424 | } | |
f3cc28c7 | 1425 | |
05ffdd7b JC |
1426 | static void set_flow_ctrl_new(struct atl1_hw *hw) |
1427 | { | |
1428 | u32 hi, lo, value; | |
1429 | ||
1430 | /* RXF Flow Control */ | |
1431 | value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN); | |
1432 | lo = value / 16; | |
1433 | if (lo < 192) | |
1434 | lo = 192; | |
1435 | hi = value * 7 / 8; | |
1436 | if (hi < lo) | |
1437 | hi = lo + 16; | |
1438 | value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) | | |
1439 | ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT); | |
1440 | iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH); | |
1441 | ||
1442 | /* RRD Flow Control */ | |
1443 | value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN); | |
1444 | lo = value / 8; | |
1445 | hi = value * 7 / 8; | |
1446 | if (lo < 2) | |
1447 | lo = 2; | |
1448 | if (hi < lo) | |
1449 | hi = lo + 3; | |
1450 | value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) | | |
1451 | ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT); | |
1452 | iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH); | |
1453 | } | |
1454 | ||
1455 | /* | |
1456 | * atl1_configure - Configure Transmit&Receive Unit after Reset | |
1457 | * @adapter: board private structure | |
1458 | * | |
1459 | * Configure the Tx /Rx unit of the MAC after a reset. | |
1460 | */ | |
1461 | static u32 atl1_configure(struct atl1_adapter *adapter) | |
1462 | { | |
1463 | struct atl1_hw *hw = &adapter->hw; | |
1464 | u32 value; | |
1465 | ||
1466 | /* clear interrupt status */ | |
1467 | iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR); | |
1468 | ||
1469 | /* set MAC Address */ | |
1470 | value = (((u32) hw->mac_addr[2]) << 24) | | |
1471 | (((u32) hw->mac_addr[3]) << 16) | | |
1472 | (((u32) hw->mac_addr[4]) << 8) | | |
1473 | (((u32) hw->mac_addr[5])); | |
1474 | iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR); | |
1475 | value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1])); | |
1476 | iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4)); | |
1477 | ||
1478 | /* tx / rx ring */ | |
f3cc28c7 | 1479 | |
05ffdd7b JC |
1480 | /* HI base address */ |
1481 | iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32), | |
1482 | hw->hw_addr + REG_DESC_BASE_ADDR_HI); | |
1483 | /* LO base address */ | |
1484 | iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL), | |
1485 | hw->hw_addr + REG_DESC_RFD_ADDR_LO); | |
1486 | iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL), | |
1487 | hw->hw_addr + REG_DESC_RRD_ADDR_LO); | |
1488 | iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL), | |
1489 | hw->hw_addr + REG_DESC_TPD_ADDR_LO); | |
1490 | iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL), | |
1491 | hw->hw_addr + REG_DESC_CMB_ADDR_LO); | |
1492 | iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL), | |
1493 | hw->hw_addr + REG_DESC_SMB_ADDR_LO); | |
f3cc28c7 | 1494 | |
05ffdd7b JC |
1495 | /* element count */ |
1496 | value = adapter->rrd_ring.count; | |
1497 | value <<= 16; | |
1498 | value += adapter->rfd_ring.count; | |
1499 | iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE); | |
1500 | iowrite32(adapter->tpd_ring.count, hw->hw_addr + | |
1501 | REG_DESC_TPD_RING_SIZE); | |
f3cc28c7 | 1502 | |
05ffdd7b JC |
1503 | /* Load Ptr */ |
1504 | iowrite32(1, hw->hw_addr + REG_LOAD_PTR); | |
f3cc28c7 | 1505 | |
05ffdd7b JC |
1506 | /* config Mailbox */ |
1507 | value = ((atomic_read(&adapter->tpd_ring.next_to_use) | |
1508 | & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) | | |
1509 | ((atomic_read(&adapter->rrd_ring.next_to_clean) | |
1510 | & MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) | | |
1511 | ((atomic_read(&adapter->rfd_ring.next_to_use) | |
1512 | & MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT); | |
1513 | iowrite32(value, hw->hw_addr + REG_MAILBOX); | |
f3cc28c7 | 1514 | |
05ffdd7b JC |
1515 | /* config IPG/IFG */ |
1516 | value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK) | |
1517 | << MAC_IPG_IFG_IPGT_SHIFT) | | |
1518 | (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) | |
1519 | << MAC_IPG_IFG_MIFG_SHIFT) | | |
1520 | (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) | |
1521 | << MAC_IPG_IFG_IPGR1_SHIFT) | | |
1522 | (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) | |
1523 | << MAC_IPG_IFG_IPGR2_SHIFT); | |
1524 | iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG); | |
f3cc28c7 | 1525 | |
05ffdd7b JC |
1526 | /* config Half-Duplex Control */ |
1527 | value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | | |
1528 | (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) | |
1529 | << MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) | | |
1530 | MAC_HALF_DUPLX_CTRL_EXC_DEF_EN | | |
1531 | (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) | | |
1532 | (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) | |
1533 | << MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT); | |
1534 | iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL); | |
f3cc28c7 | 1535 | |
05ffdd7b JC |
1536 | /* set Interrupt Moderator Timer */ |
1537 | iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT); | |
1538 | iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL); | |
f3cc28c7 | 1539 | |
05ffdd7b JC |
1540 | /* set Interrupt Clear Timer */ |
1541 | iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER); | |
f3cc28c7 | 1542 | |
2a49128f JC |
1543 | /* set max frame size hw will accept */ |
1544 | iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU); | |
f3cc28c7 | 1545 | |
05ffdd7b JC |
1546 | /* jumbo size & rrd retirement timer */ |
1547 | value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK) | |
1548 | << RXQ_JMBOSZ_TH_SHIFT) | | |
1549 | (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK) | |
1550 | << RXQ_JMBO_LKAH_SHIFT) | | |
1551 | (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK) | |
1552 | << RXQ_RRD_TIMER_SHIFT); | |
1553 | iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM); | |
f3cc28c7 | 1554 | |
05ffdd7b JC |
1555 | /* Flow Control */ |
1556 | switch (hw->dev_rev) { | |
1557 | case 0x8001: | |
1558 | case 0x9001: | |
1559 | case 0x9002: | |
1560 | case 0x9003: | |
1561 | set_flow_ctrl_old(adapter); | |
1562 | break; | |
1563 | default: | |
1564 | set_flow_ctrl_new(hw); | |
1565 | break; | |
f3cc28c7 | 1566 | } |
f3cc28c7 | 1567 | |
05ffdd7b JC |
1568 | /* config TXQ */ |
1569 | value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK) | |
1570 | << TXQ_CTRL_TPD_BURST_NUM_SHIFT) | | |
1571 | (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK) | |
1572 | << TXQ_CTRL_TXF_BURST_NUM_SHIFT) | | |
1573 | (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK) | |
1574 | << TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE | | |
1575 | TXQ_CTRL_EN; | |
1576 | iowrite32(value, hw->hw_addr + REG_TXQ_CTRL); | |
f3cc28c7 | 1577 | |
05ffdd7b JC |
1578 | /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */ |
1579 | value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK) | |
1580 | << TX_JUMBO_TASK_TH_SHIFT) | | |
1581 | (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK) | |
1582 | << TX_TPD_MIN_IPG_SHIFT); | |
1583 | iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG); | |
f3cc28c7 | 1584 | |
05ffdd7b JC |
1585 | /* config RXQ */ |
1586 | value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK) | |
1587 | << RXQ_CTRL_RFD_BURST_NUM_SHIFT) | | |
1588 | (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK) | |
1589 | << RXQ_CTRL_RRD_BURST_THRESH_SHIFT) | | |
1590 | (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK) | |
1591 | << RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN | | |
1592 | RXQ_CTRL_EN; | |
1593 | iowrite32(value, hw->hw_addr + REG_RXQ_CTRL); | |
f3cc28c7 | 1594 | |
05ffdd7b JC |
1595 | /* config DMA Engine */ |
1596 | value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK) | |
1597 | << DMA_CTRL_DMAR_BURST_LEN_SHIFT) | | |
3f516c00 JC |
1598 | ((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK) |
1599 | << DMA_CTRL_DMAW_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN | | |
05ffdd7b JC |
1600 | DMA_CTRL_DMAW_EN; |
1601 | value |= (u32) hw->dma_ord; | |
1602 | if (atl1_rcb_128 == hw->rcb_value) | |
1603 | value |= DMA_CTRL_RCB_VALUE; | |
1604 | iowrite32(value, hw->hw_addr + REG_DMA_CTRL); | |
f3cc28c7 | 1605 | |
05ffdd7b | 1606 | /* config CMB / SMB */ |
91a500ac JC |
1607 | value = (hw->cmb_tpd > adapter->tpd_ring.count) ? |
1608 | hw->cmb_tpd : adapter->tpd_ring.count; | |
1609 | value <<= 16; | |
1610 | value |= hw->cmb_rrd; | |
05ffdd7b JC |
1611 | iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH); |
1612 | value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16); | |
1613 | iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER); | |
1614 | iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER); | |
f3cc28c7 | 1615 | |
05ffdd7b JC |
1616 | /* --- enable CMB / SMB */ |
1617 | value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN; | |
1618 | iowrite32(value, hw->hw_addr + REG_CSMB_CTRL); | |
f3cc28c7 | 1619 | |
05ffdd7b JC |
1620 | value = ioread32(adapter->hw.hw_addr + REG_ISR); |
1621 | if (unlikely((value & ISR_PHY_LINKDOWN) != 0)) | |
1622 | value = 1; /* config failed */ | |
1623 | else | |
1624 | value = 0; | |
f3cc28c7 | 1625 | |
05ffdd7b JC |
1626 | /* clear all interrupt status */ |
1627 | iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR); | |
1628 | iowrite32(0, adapter->hw.hw_addr + REG_ISR); | |
1629 | return value; | |
f3cc28c7 | 1630 | } |
f3cc28c7 | 1631 | |
05ffdd7b JC |
1632 | /* |
1633 | * atl1_pcie_patch - Patch for PCIE module | |
1634 | */ | |
1635 | static void atl1_pcie_patch(struct atl1_adapter *adapter) | |
f3cc28c7 | 1636 | { |
05ffdd7b | 1637 | u32 value; |
f3cc28c7 | 1638 | |
05ffdd7b JC |
1639 | /* much vendor magic here */ |
1640 | value = 0x6500; | |
1641 | iowrite32(value, adapter->hw.hw_addr + 0x12FC); | |
1642 | /* pcie flow control mode change */ | |
1643 | value = ioread32(adapter->hw.hw_addr + 0x1008); | |
1644 | value |= 0x8000; | |
1645 | iowrite32(value, adapter->hw.hw_addr + 0x1008); | |
f3cc28c7 | 1646 | } |
f3cc28c7 | 1647 | |
f3cc28c7 | 1648 | /* |
05ffdd7b JC |
1649 | * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400 |
1650 | * on PCI Command register is disable. | |
1651 | * The function enable this bit. | |
1652 | * Brackett, 2006/03/15 | |
f3cc28c7 | 1653 | */ |
05ffdd7b | 1654 | static void atl1_via_workaround(struct atl1_adapter *adapter) |
f3cc28c7 | 1655 | { |
05ffdd7b | 1656 | unsigned long value; |
f3cc28c7 | 1657 | |
05ffdd7b JC |
1658 | value = ioread16(adapter->hw.hw_addr + PCI_COMMAND); |
1659 | if (value & PCI_COMMAND_INTX_DISABLE) | |
1660 | value &= ~PCI_COMMAND_INTX_DISABLE; | |
1661 | iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND); | |
f3cc28c7 JC |
1662 | } |
1663 | ||
05ffdd7b JC |
1664 | static void atl1_inc_smb(struct atl1_adapter *adapter) |
1665 | { | |
02e71731 | 1666 | struct net_device *netdev = adapter->netdev; |
05ffdd7b | 1667 | struct stats_msg_block *smb = adapter->smb.smb; |
f3cc28c7 | 1668 | |
05ffdd7b JC |
1669 | /* Fill out the OS statistics structure */ |
1670 | adapter->soft_stats.rx_packets += smb->rx_ok; | |
1671 | adapter->soft_stats.tx_packets += smb->tx_ok; | |
1672 | adapter->soft_stats.rx_bytes += smb->rx_byte_cnt; | |
1673 | adapter->soft_stats.tx_bytes += smb->tx_byte_cnt; | |
1674 | adapter->soft_stats.multicast += smb->rx_mcast; | |
1675 | adapter->soft_stats.collisions += (smb->tx_1_col + smb->tx_2_col * 2 + | |
1676 | smb->tx_late_col + smb->tx_abort_col * adapter->hw.max_retry); | |
f3cc28c7 | 1677 | |
05ffdd7b JC |
1678 | /* Rx Errors */ |
1679 | adapter->soft_stats.rx_errors += (smb->rx_frag + smb->rx_fcs_err + | |
1680 | smb->rx_len_err + smb->rx_sz_ov + smb->rx_rxf_ov + | |
1681 | smb->rx_rrd_ov + smb->rx_align_err); | |
1682 | adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov; | |
1683 | adapter->soft_stats.rx_length_errors += smb->rx_len_err; | |
1684 | adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err; | |
1685 | adapter->soft_stats.rx_frame_errors += smb->rx_align_err; | |
1686 | adapter->soft_stats.rx_missed_errors += (smb->rx_rrd_ov + | |
1687 | smb->rx_rxf_ov); | |
f3cc28c7 | 1688 | |
05ffdd7b JC |
1689 | adapter->soft_stats.rx_pause += smb->rx_pause; |
1690 | adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov; | |
1691 | adapter->soft_stats.rx_trunc += smb->rx_sz_ov; | |
f3cc28c7 | 1692 | |
05ffdd7b JC |
1693 | /* Tx Errors */ |
1694 | adapter->soft_stats.tx_errors += (smb->tx_late_col + | |
1695 | smb->tx_abort_col + smb->tx_underrun + smb->tx_trunc); | |
1696 | adapter->soft_stats.tx_fifo_errors += smb->tx_underrun; | |
1697 | adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col; | |
1698 | adapter->soft_stats.tx_window_errors += smb->tx_late_col; | |
f3cc28c7 | 1699 | |
05ffdd7b JC |
1700 | adapter->soft_stats.excecol += smb->tx_abort_col; |
1701 | adapter->soft_stats.deffer += smb->tx_defer; | |
1702 | adapter->soft_stats.scc += smb->tx_1_col; | |
1703 | adapter->soft_stats.mcc += smb->tx_2_col; | |
1704 | adapter->soft_stats.latecol += smb->tx_late_col; | |
1705 | adapter->soft_stats.tx_underun += smb->tx_underrun; | |
1706 | adapter->soft_stats.tx_trunc += smb->tx_trunc; | |
1707 | adapter->soft_stats.tx_pause += smb->tx_pause; | |
f3cc28c7 | 1708 | |
02e71731 SH |
1709 | netdev->stats.rx_packets = adapter->soft_stats.rx_packets; |
1710 | netdev->stats.tx_packets = adapter->soft_stats.tx_packets; | |
1711 | netdev->stats.rx_bytes = adapter->soft_stats.rx_bytes; | |
1712 | netdev->stats.tx_bytes = adapter->soft_stats.tx_bytes; | |
1713 | netdev->stats.multicast = adapter->soft_stats.multicast; | |
1714 | netdev->stats.collisions = adapter->soft_stats.collisions; | |
1715 | netdev->stats.rx_errors = adapter->soft_stats.rx_errors; | |
1716 | netdev->stats.rx_over_errors = | |
05ffdd7b | 1717 | adapter->soft_stats.rx_missed_errors; |
02e71731 | 1718 | netdev->stats.rx_length_errors = |
05ffdd7b | 1719 | adapter->soft_stats.rx_length_errors; |
02e71731 SH |
1720 | netdev->stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors; |
1721 | netdev->stats.rx_frame_errors = | |
05ffdd7b | 1722 | adapter->soft_stats.rx_frame_errors; |
02e71731 SH |
1723 | netdev->stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors; |
1724 | netdev->stats.rx_missed_errors = | |
05ffdd7b | 1725 | adapter->soft_stats.rx_missed_errors; |
02e71731 SH |
1726 | netdev->stats.tx_errors = adapter->soft_stats.tx_errors; |
1727 | netdev->stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors; | |
1728 | netdev->stats.tx_aborted_errors = | |
05ffdd7b | 1729 | adapter->soft_stats.tx_aborted_errors; |
02e71731 | 1730 | netdev->stats.tx_window_errors = |
05ffdd7b | 1731 | adapter->soft_stats.tx_window_errors; |
02e71731 | 1732 | netdev->stats.tx_carrier_errors = |
05ffdd7b | 1733 | adapter->soft_stats.tx_carrier_errors; |
f3cc28c7 JC |
1734 | } |
1735 | ||
05ffdd7b | 1736 | static void atl1_update_mailbox(struct atl1_adapter *adapter) |
f3cc28c7 | 1737 | { |
05ffdd7b JC |
1738 | unsigned long flags; |
1739 | u32 tpd_next_to_use; | |
1740 | u32 rfd_next_to_use; | |
1741 | u32 rrd_next_to_clean; | |
f3cc28c7 | 1742 | u32 value; |
f3cc28c7 | 1743 | |
05ffdd7b | 1744 | spin_lock_irqsave(&adapter->mb_lock, flags); |
f3cc28c7 | 1745 | |
05ffdd7b JC |
1746 | tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use); |
1747 | rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use); | |
1748 | rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean); | |
f3cc28c7 | 1749 | |
05ffdd7b JC |
1750 | value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) << |
1751 | MB_RFD_PROD_INDX_SHIFT) | | |
1752 | ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) << | |
1753 | MB_RRD_CONS_INDX_SHIFT) | | |
1754 | ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) << | |
1755 | MB_TPD_PROD_INDX_SHIFT); | |
1756 | iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX); | |
f3cc28c7 | 1757 | |
05ffdd7b | 1758 | spin_unlock_irqrestore(&adapter->mb_lock, flags); |
f3cc28c7 JC |
1759 | } |
1760 | ||
05ffdd7b JC |
1761 | static void atl1_clean_alloc_flag(struct atl1_adapter *adapter, |
1762 | struct rx_return_desc *rrd, u16 offset) | |
f3cc28c7 | 1763 | { |
05ffdd7b | 1764 | struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; |
f3cc28c7 | 1765 | |
05ffdd7b JC |
1766 | while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) { |
1767 | rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0; | |
1768 | if (++rfd_ring->next_to_clean == rfd_ring->count) { | |
1769 | rfd_ring->next_to_clean = 0; | |
f3cc28c7 | 1770 | } |
f3cc28c7 | 1771 | } |
05ffdd7b | 1772 | } |
f3cc28c7 | 1773 | |
05ffdd7b JC |
1774 | static void atl1_update_rfd_index(struct atl1_adapter *adapter, |
1775 | struct rx_return_desc *rrd) | |
1776 | { | |
1777 | u16 num_buf; | |
f3cc28c7 | 1778 | |
05ffdd7b JC |
1779 | num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) / |
1780 | adapter->rx_buffer_len; | |
1781 | if (rrd->num_buf == num_buf) | |
1782 | /* clean alloc flag for bad rrd */ | |
1783 | atl1_clean_alloc_flag(adapter, rrd, num_buf); | |
1784 | } | |
f3cc28c7 | 1785 | |
05ffdd7b JC |
1786 | static void atl1_rx_checksum(struct atl1_adapter *adapter, |
1787 | struct rx_return_desc *rrd, struct sk_buff *skb) | |
1788 | { | |
1789 | struct pci_dev *pdev = adapter->pdev; | |
f3cc28c7 | 1790 | |
c2ac3ef3 JC |
1791 | /* |
1792 | * The L1 hardware contains a bug that erroneously sets the | |
1793 | * PACKET_FLAG_ERR and ERR_FLAG_L4_CHKSUM bits whenever a | |
1794 | * fragmented IP packet is received, even though the packet | |
1795 | * is perfectly valid and its checksum is correct. There's | |
1796 | * no way to distinguish between one of these good packets | |
1797 | * and a packet that actually contains a TCP/UDP checksum | |
1798 | * error, so all we can do is allow it to be handed up to | |
1799 | * the higher layers and let it be sorted out there. | |
1800 | */ | |
1801 | ||
05ffdd7b | 1802 | skb->ip_summed = CHECKSUM_NONE; |
f3cc28c7 | 1803 | |
05ffdd7b JC |
1804 | if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) { |
1805 | if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC | | |
1806 | ERR_FLAG_CODE | ERR_FLAG_OV)) { | |
1807 | adapter->hw_csum_err++; | |
6446a860 JC |
1808 | if (netif_msg_rx_err(adapter)) |
1809 | dev_printk(KERN_DEBUG, &pdev->dev, | |
1810 | "rx checksum error\n"); | |
05ffdd7b | 1811 | return; |
f3cc28c7 | 1812 | } |
f3cc28c7 JC |
1813 | } |
1814 | ||
05ffdd7b JC |
1815 | /* not IPv4 */ |
1816 | if (!(rrd->pkt_flg & PACKET_FLAG_IPV4)) | |
1817 | /* checksum is invalid, but it's not an IPv4 pkt, so ok */ | |
1818 | return; | |
1819 | ||
1820 | /* IPv4 packet */ | |
1821 | if (likely(!(rrd->err_flg & | |
1822 | (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) { | |
1823 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1824 | adapter->hw_csum_good++; | |
1825 | return; | |
f3cc28c7 JC |
1826 | } |
1827 | ||
05ffdd7b | 1828 | return; |
f3cc28c7 JC |
1829 | } |
1830 | ||
05ffdd7b JC |
1831 | /* |
1832 | * atl1_alloc_rx_buffers - Replace used receive buffers | |
1833 | * @adapter: address of board private structure | |
1834 | */ | |
1835 | static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter) | |
f3cc28c7 | 1836 | { |
05ffdd7b JC |
1837 | struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; |
1838 | struct pci_dev *pdev = adapter->pdev; | |
1839 | struct page *page; | |
1840 | unsigned long offset; | |
1841 | struct atl1_buffer *buffer_info, *next_info; | |
1842 | struct sk_buff *skb; | |
1843 | u16 num_alloc = 0; | |
1844 | u16 rfd_next_to_use, next_next; | |
1845 | struct rx_free_desc *rfd_desc; | |
f3cc28c7 | 1846 | |
05ffdd7b JC |
1847 | next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use); |
1848 | if (++next_next == rfd_ring->count) | |
1849 | next_next = 0; | |
1850 | buffer_info = &rfd_ring->buffer_info[rfd_next_to_use]; | |
1851 | next_info = &rfd_ring->buffer_info[next_next]; | |
f3cc28c7 | 1852 | |
05ffdd7b JC |
1853 | while (!buffer_info->alloced && !next_info->alloced) { |
1854 | if (buffer_info->skb) { | |
1855 | buffer_info->alloced = 1; | |
1856 | goto next; | |
1857 | } | |
f3cc28c7 | 1858 | |
05ffdd7b | 1859 | rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use); |
f3cc28c7 | 1860 | |
b102df14 SH |
1861 | skb = netdev_alloc_skb(adapter->netdev, |
1862 | adapter->rx_buffer_len + NET_IP_ALIGN); | |
6446a860 JC |
1863 | if (unlikely(!skb)) { |
1864 | /* Better luck next round */ | |
02e71731 | 1865 | adapter->netdev->stats.rx_dropped++; |
05ffdd7b JC |
1866 | break; |
1867 | } | |
f3cc28c7 | 1868 | |
05ffdd7b JC |
1869 | /* |
1870 | * Make buffer alignment 2 beyond a 16 byte boundary | |
1871 | * this will result in a 16 byte aligned IP header after | |
1872 | * the 14 byte MAC header is removed | |
1873 | */ | |
1874 | skb_reserve(skb, NET_IP_ALIGN); | |
f3cc28c7 | 1875 | |
05ffdd7b JC |
1876 | buffer_info->alloced = 1; |
1877 | buffer_info->skb = skb; | |
1878 | buffer_info->length = (u16) adapter->rx_buffer_len; | |
1879 | page = virt_to_page(skb->data); | |
1880 | offset = (unsigned long)skb->data & ~PAGE_MASK; | |
1881 | buffer_info->dma = pci_map_page(pdev, page, offset, | |
1882 | adapter->rx_buffer_len, | |
1883 | PCI_DMA_FROMDEVICE); | |
1884 | rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma); | |
1885 | rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len); | |
1886 | rfd_desc->coalese = 0; | |
f3cc28c7 | 1887 | |
05ffdd7b JC |
1888 | next: |
1889 | rfd_next_to_use = next_next; | |
1890 | if (unlikely(++next_next == rfd_ring->count)) | |
1891 | next_next = 0; | |
f3cc28c7 | 1892 | |
05ffdd7b JC |
1893 | buffer_info = &rfd_ring->buffer_info[rfd_next_to_use]; |
1894 | next_info = &rfd_ring->buffer_info[next_next]; | |
1895 | num_alloc++; | |
1896 | } | |
f3cc28c7 | 1897 | |
05ffdd7b JC |
1898 | if (num_alloc) { |
1899 | /* | |
1900 | * Force memory writes to complete before letting h/w | |
1901 | * know there are new descriptors to fetch. (Only | |
1902 | * applicable for weak-ordered memory model archs, | |
1903 | * such as IA-64). | |
1904 | */ | |
1905 | wmb(); | |
1906 | atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use); | |
1907 | } | |
1908 | return num_alloc; | |
f3cc28c7 JC |
1909 | } |
1910 | ||
05ffdd7b | 1911 | static void atl1_intr_rx(struct atl1_adapter *adapter) |
f3cc28c7 | 1912 | { |
05ffdd7b JC |
1913 | int i, count; |
1914 | u16 length; | |
1915 | u16 rrd_next_to_clean; | |
f3cc28c7 | 1916 | u32 value; |
05ffdd7b JC |
1917 | struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; |
1918 | struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring; | |
1919 | struct atl1_buffer *buffer_info; | |
1920 | struct rx_return_desc *rrd; | |
1921 | struct sk_buff *skb; | |
f3cc28c7 | 1922 | |
05ffdd7b | 1923 | count = 0; |
f3cc28c7 | 1924 | |
05ffdd7b | 1925 | rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean); |
f3cc28c7 | 1926 | |
05ffdd7b JC |
1927 | while (1) { |
1928 | rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean); | |
1929 | i = 1; | |
1930 | if (likely(rrd->xsz.valid)) { /* packet valid */ | |
1931 | chk_rrd: | |
1932 | /* check rrd status */ | |
1933 | if (likely(rrd->num_buf == 1)) | |
1934 | goto rrd_ok; | |
6446a860 JC |
1935 | else if (netif_msg_rx_err(adapter)) { |
1936 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
1937 | "unexpected RRD buffer count\n"); | |
1938 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
1939 | "rx_buf_len = %d\n", | |
1940 | adapter->rx_buffer_len); | |
1941 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
1942 | "RRD num_buf = %d\n", | |
1943 | rrd->num_buf); | |
1944 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
1945 | "RRD pkt_len = %d\n", | |
1946 | rrd->xsz.xsum_sz.pkt_size); | |
1947 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
1948 | "RRD pkt_flg = 0x%08X\n", | |
1949 | rrd->pkt_flg); | |
1950 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
1951 | "RRD err_flg = 0x%08X\n", | |
1952 | rrd->err_flg); | |
1953 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
1954 | "RRD vlan_tag = 0x%08X\n", | |
1955 | rrd->vlan_tag); | |
1956 | } | |
f3cc28c7 | 1957 | |
05ffdd7b JC |
1958 | /* rrd seems to be bad */ |
1959 | if (unlikely(i-- > 0)) { | |
1960 | /* rrd may not be DMAed completely */ | |
05ffdd7b JC |
1961 | udelay(1); |
1962 | goto chk_rrd; | |
1963 | } | |
1964 | /* bad rrd */ | |
6446a860 JC |
1965 | if (netif_msg_rx_err(adapter)) |
1966 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
1967 | "bad RRD\n"); | |
05ffdd7b JC |
1968 | /* see if update RFD index */ |
1969 | if (rrd->num_buf > 1) | |
1970 | atl1_update_rfd_index(adapter, rrd); | |
f3cc28c7 | 1971 | |
05ffdd7b JC |
1972 | /* update rrd */ |
1973 | rrd->xsz.valid = 0; | |
1974 | if (++rrd_next_to_clean == rrd_ring->count) | |
1975 | rrd_next_to_clean = 0; | |
1976 | count++; | |
1977 | continue; | |
1978 | } else { /* current rrd still not be updated */ | |
f3cc28c7 | 1979 | |
05ffdd7b JC |
1980 | break; |
1981 | } | |
1982 | rrd_ok: | |
1983 | /* clean alloc flag for bad rrd */ | |
1984 | atl1_clean_alloc_flag(adapter, rrd, 0); | |
f3cc28c7 | 1985 | |
05ffdd7b JC |
1986 | buffer_info = &rfd_ring->buffer_info[rrd->buf_indx]; |
1987 | if (++rfd_ring->next_to_clean == rfd_ring->count) | |
1988 | rfd_ring->next_to_clean = 0; | |
f3cc28c7 | 1989 | |
05ffdd7b JC |
1990 | /* update rrd next to clean */ |
1991 | if (++rrd_next_to_clean == rrd_ring->count) | |
1992 | rrd_next_to_clean = 0; | |
1993 | count++; | |
f3cc28c7 | 1994 | |
05ffdd7b JC |
1995 | if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) { |
1996 | if (!(rrd->err_flg & | |
1997 | (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM | |
1998 | | ERR_FLAG_LEN))) { | |
1999 | /* packet error, don't need upstream */ | |
2000 | buffer_info->alloced = 0; | |
2001 | rrd->xsz.valid = 0; | |
2002 | continue; | |
2003 | } | |
2004 | } | |
f3cc28c7 | 2005 | |
05ffdd7b JC |
2006 | /* Good Receive */ |
2007 | pci_unmap_page(adapter->pdev, buffer_info->dma, | |
2008 | buffer_info->length, PCI_DMA_FROMDEVICE); | |
aefdbf1a | 2009 | buffer_info->dma = 0; |
05ffdd7b JC |
2010 | skb = buffer_info->skb; |
2011 | length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size); | |
f3cc28c7 | 2012 | |
a3093d9b | 2013 | skb_put(skb, length - ETH_FCS_LEN); |
f3cc28c7 | 2014 | |
05ffdd7b JC |
2015 | /* Receive Checksum Offload */ |
2016 | atl1_rx_checksum(adapter, rrd, skb); | |
2017 | skb->protocol = eth_type_trans(skb, adapter->netdev); | |
f3cc28c7 | 2018 | |
05ffdd7b JC |
2019 | if (adapter->vlgrp && (rrd->pkt_flg & PACKET_FLAG_VLAN_INS)) { |
2020 | u16 vlan_tag = (rrd->vlan_tag >> 4) | | |
2021 | ((rrd->vlan_tag & 7) << 13) | | |
2022 | ((rrd->vlan_tag & 8) << 9); | |
2023 | vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag); | |
2024 | } else | |
2025 | netif_rx(skb); | |
f3cc28c7 | 2026 | |
05ffdd7b JC |
2027 | /* let protocol layer free skb */ |
2028 | buffer_info->skb = NULL; | |
2029 | buffer_info->alloced = 0; | |
2030 | rrd->xsz.valid = 0; | |
05ffdd7b | 2031 | } |
f3cc28c7 | 2032 | |
05ffdd7b | 2033 | atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean); |
f3cc28c7 | 2034 | |
05ffdd7b | 2035 | atl1_alloc_rx_buffers(adapter); |
f3cc28c7 | 2036 | |
05ffdd7b JC |
2037 | /* update mailbox ? */ |
2038 | if (count) { | |
2039 | u32 tpd_next_to_use; | |
2040 | u32 rfd_next_to_use; | |
f3cc28c7 | 2041 | |
05ffdd7b | 2042 | spin_lock(&adapter->mb_lock); |
f3cc28c7 | 2043 | |
05ffdd7b JC |
2044 | tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use); |
2045 | rfd_next_to_use = | |
2046 | atomic_read(&adapter->rfd_ring.next_to_use); | |
2047 | rrd_next_to_clean = | |
2048 | atomic_read(&adapter->rrd_ring.next_to_clean); | |
2049 | value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) << | |
2050 | MB_RFD_PROD_INDX_SHIFT) | | |
2051 | ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) << | |
2052 | MB_RRD_CONS_INDX_SHIFT) | | |
2053 | ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) << | |
2054 | MB_TPD_PROD_INDX_SHIFT); | |
2055 | iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX); | |
2056 | spin_unlock(&adapter->mb_lock); | |
2057 | } | |
f3cc28c7 JC |
2058 | } |
2059 | ||
05ffdd7b | 2060 | static void atl1_intr_tx(struct atl1_adapter *adapter) |
f3cc28c7 | 2061 | { |
05ffdd7b JC |
2062 | struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; |
2063 | struct atl1_buffer *buffer_info; | |
2064 | u16 sw_tpd_next_to_clean; | |
2065 | u16 cmb_tpd_next_to_clean; | |
f3cc28c7 | 2066 | |
05ffdd7b JC |
2067 | sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean); |
2068 | cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx); | |
f3cc28c7 | 2069 | |
05ffdd7b JC |
2070 | while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) { |
2071 | struct tx_packet_desc *tpd; | |
f3cc28c7 | 2072 | |
05ffdd7b JC |
2073 | tpd = ATL1_TPD_DESC(tpd_ring, sw_tpd_next_to_clean); |
2074 | buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean]; | |
2075 | if (buffer_info->dma) { | |
2076 | pci_unmap_page(adapter->pdev, buffer_info->dma, | |
2077 | buffer_info->length, PCI_DMA_TODEVICE); | |
2078 | buffer_info->dma = 0; | |
2079 | } | |
f3cc28c7 | 2080 | |
05ffdd7b JC |
2081 | if (buffer_info->skb) { |
2082 | dev_kfree_skb_irq(buffer_info->skb); | |
2083 | buffer_info->skb = NULL; | |
2084 | } | |
f3cc28c7 | 2085 | |
05ffdd7b JC |
2086 | if (++sw_tpd_next_to_clean == tpd_ring->count) |
2087 | sw_tpd_next_to_clean = 0; | |
2088 | } | |
2089 | atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean); | |
2090 | ||
2091 | if (netif_queue_stopped(adapter->netdev) | |
2092 | && netif_carrier_ok(adapter->netdev)) | |
2093 | netif_wake_queue(adapter->netdev); | |
f3cc28c7 JC |
2094 | } |
2095 | ||
e6a7ff4a | 2096 | static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring) |
f3cc28c7 JC |
2097 | { |
2098 | u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean); | |
2099 | u16 next_to_use = atomic_read(&tpd_ring->next_to_use); | |
53ffb42c JC |
2100 | return ((next_to_clean > next_to_use) ? |
2101 | next_to_clean - next_to_use - 1 : | |
2102 | tpd_ring->count + next_to_clean - next_to_use - 1); | |
f3cc28c7 JC |
2103 | } |
2104 | ||
2105 | static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb, | |
6446a860 | 2106 | struct tx_packet_desc *ptpd) |
f3cc28c7 | 2107 | { |
6446a860 JC |
2108 | u8 hdr_len, ip_off; |
2109 | u32 real_len; | |
f3cc28c7 JC |
2110 | int err; |
2111 | ||
2112 | if (skb_shinfo(skb)->gso_size) { | |
2113 | if (skb_header_cloned(skb)) { | |
2114 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
2115 | if (unlikely(err)) | |
6446a860 | 2116 | return -1; |
f3cc28c7 JC |
2117 | } |
2118 | ||
d63ddcec | 2119 | if (skb->protocol == htons(ETH_P_IP)) { |
eddc9ec5 ACM |
2120 | struct iphdr *iph = ip_hdr(skb); |
2121 | ||
6446a860 JC |
2122 | real_len = (((unsigned char *)iph - skb->data) + |
2123 | ntohs(iph->tot_len)); | |
2124 | if (real_len < skb->len) | |
2125 | pskb_trim(skb, real_len); | |
2126 | hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb)); | |
2127 | if (skb->len == hdr_len) { | |
2128 | iph->check = 0; | |
2129 | tcp_hdr(skb)->check = | |
2130 | ~csum_tcpudp_magic(iph->saddr, | |
2131 | iph->daddr, tcp_hdrlen(skb), | |
2132 | IPPROTO_TCP, 0); | |
2133 | ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) << | |
2134 | TPD_IPHL_SHIFT; | |
2135 | ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) & | |
2136 | TPD_TCPHDRLEN_MASK) << | |
2137 | TPD_TCPHDRLEN_SHIFT; | |
2138 | ptpd->word3 |= 1 << TPD_IP_CSUM_SHIFT; | |
2139 | ptpd->word3 |= 1 << TPD_TCP_CSUM_SHIFT; | |
2140 | return 1; | |
2141 | } | |
2142 | ||
eddc9ec5 | 2143 | iph->check = 0; |
aa8223c7 | 2144 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, |
6446a860 JC |
2145 | iph->daddr, 0, IPPROTO_TCP, 0); |
2146 | ip_off = (unsigned char *)iph - | |
2147 | (unsigned char *) skb_network_header(skb); | |
2148 | if (ip_off == 8) /* 802.3-SNAP frame */ | |
2149 | ptpd->word3 |= 1 << TPD_ETHTYPE_SHIFT; | |
2150 | else if (ip_off != 0) | |
2151 | return -2; | |
2152 | ||
2153 | ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) << | |
2154 | TPD_IPHL_SHIFT; | |
2155 | ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) & | |
2156 | TPD_TCPHDRLEN_MASK) << TPD_TCPHDRLEN_SHIFT; | |
2157 | ptpd->word3 |= (skb_shinfo(skb)->gso_size & | |
2158 | TPD_MSS_MASK) << TPD_MSS_SHIFT; | |
2159 | ptpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT; | |
2160 | return 3; | |
f3cc28c7 JC |
2161 | } |
2162 | } | |
2163 | return false; | |
2164 | } | |
2165 | ||
2166 | static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb, | |
6446a860 | 2167 | struct tx_packet_desc *ptpd) |
f3cc28c7 JC |
2168 | { |
2169 | u8 css, cso; | |
2170 | ||
2171 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { | |
6446a860 JC |
2172 | css = (u8) (skb->csum_start - skb_headroom(skb)); |
2173 | cso = css + (u8) skb->csum_offset; | |
2174 | if (unlikely(css & 0x1)) { | |
2175 | /* L1 hardware requires an even number here */ | |
2176 | if (netif_msg_tx_err(adapter)) | |
2177 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
2178 | "payload offset not an even number\n"); | |
f3cc28c7 JC |
2179 | return -1; |
2180 | } | |
6446a860 JC |
2181 | ptpd->word3 |= (css & TPD_PLOADOFFSET_MASK) << |
2182 | TPD_PLOADOFFSET_SHIFT; | |
2183 | ptpd->word3 |= (cso & TPD_CCSUMOFFSET_MASK) << | |
2184 | TPD_CCSUMOFFSET_SHIFT; | |
2185 | ptpd->word3 |= 1 << TPD_CUST_CSUM_EN_SHIFT; | |
f3cc28c7 JC |
2186 | return true; |
2187 | } | |
6446a860 | 2188 | return 0; |
f3cc28c7 JC |
2189 | } |
2190 | ||
53ffb42c | 2191 | static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb, |
6446a860 | 2192 | struct tx_packet_desc *ptpd) |
f3cc28c7 | 2193 | { |
f3cc28c7 JC |
2194 | struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; |
2195 | struct atl1_buffer *buffer_info; | |
6446a860 | 2196 | u16 buf_len = skb->len; |
f3cc28c7 | 2197 | struct page *page; |
f3cc28c7 JC |
2198 | unsigned long offset; |
2199 | unsigned int nr_frags; | |
2200 | unsigned int f; | |
6446a860 JC |
2201 | int retval; |
2202 | u16 next_to_use; | |
2203 | u16 data_len; | |
2204 | u8 hdr_len; | |
f3cc28c7 | 2205 | |
6446a860 | 2206 | buf_len -= skb->data_len; |
f3cc28c7 | 2207 | nr_frags = skb_shinfo(skb)->nr_frags; |
6446a860 JC |
2208 | next_to_use = atomic_read(&tpd_ring->next_to_use); |
2209 | buffer_info = &tpd_ring->buffer_info[next_to_use]; | |
f3cc28c7 JC |
2210 | if (unlikely(buffer_info->skb)) |
2211 | BUG(); | |
6446a860 JC |
2212 | /* put skb in last TPD */ |
2213 | buffer_info->skb = NULL; | |
f3cc28c7 | 2214 | |
6446a860 JC |
2215 | retval = (ptpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK; |
2216 | if (retval) { | |
2217 | /* TSO */ | |
2218 | hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
2219 | buffer_info->length = hdr_len; | |
f3cc28c7 JC |
2220 | page = virt_to_page(skb->data); |
2221 | offset = (unsigned long)skb->data & ~PAGE_MASK; | |
2222 | buffer_info->dma = pci_map_page(adapter->pdev, page, | |
6446a860 | 2223 | offset, hdr_len, |
f3cc28c7 JC |
2224 | PCI_DMA_TODEVICE); |
2225 | ||
6446a860 JC |
2226 | if (++next_to_use == tpd_ring->count) |
2227 | next_to_use = 0; | |
f3cc28c7 | 2228 | |
6446a860 JC |
2229 | if (buf_len > hdr_len) { |
2230 | int i, nseg; | |
ddfce6bb | 2231 | |
6446a860 JC |
2232 | data_len = buf_len - hdr_len; |
2233 | nseg = (data_len + ATL1_MAX_TX_BUF_LEN - 1) / | |
53ffb42c | 2234 | ATL1_MAX_TX_BUF_LEN; |
6446a860 | 2235 | for (i = 0; i < nseg; i++) { |
f3cc28c7 | 2236 | buffer_info = |
6446a860 | 2237 | &tpd_ring->buffer_info[next_to_use]; |
f3cc28c7 JC |
2238 | buffer_info->skb = NULL; |
2239 | buffer_info->length = | |
2b116145 | 2240 | (ATL1_MAX_TX_BUF_LEN >= |
6446a860 JC |
2241 | data_len) ? ATL1_MAX_TX_BUF_LEN : data_len; |
2242 | data_len -= buffer_info->length; | |
f3cc28c7 | 2243 | page = virt_to_page(skb->data + |
6446a860 | 2244 | (hdr_len + i * ATL1_MAX_TX_BUF_LEN)); |
f3cc28c7 | 2245 | offset = (unsigned long)(skb->data + |
6446a860 JC |
2246 | (hdr_len + i * ATL1_MAX_TX_BUF_LEN)) & |
2247 | ~PAGE_MASK; | |
53ffb42c JC |
2248 | buffer_info->dma = pci_map_page(adapter->pdev, |
2249 | page, offset, buffer_info->length, | |
2250 | PCI_DMA_TODEVICE); | |
6446a860 JC |
2251 | if (++next_to_use == tpd_ring->count) |
2252 | next_to_use = 0; | |
f3cc28c7 JC |
2253 | } |
2254 | } | |
2255 | } else { | |
6446a860 JC |
2256 | /* not TSO */ |
2257 | buffer_info->length = buf_len; | |
f3cc28c7 JC |
2258 | page = virt_to_page(skb->data); |
2259 | offset = (unsigned long)skb->data & ~PAGE_MASK; | |
2260 | buffer_info->dma = pci_map_page(adapter->pdev, page, | |
6446a860 JC |
2261 | offset, buf_len, PCI_DMA_TODEVICE); |
2262 | if (++next_to_use == tpd_ring->count) | |
2263 | next_to_use = 0; | |
f3cc28c7 JC |
2264 | } |
2265 | ||
2266 | for (f = 0; f < nr_frags; f++) { | |
2267 | struct skb_frag_struct *frag; | |
6446a860 | 2268 | u16 i, nseg; |
f3cc28c7 JC |
2269 | |
2270 | frag = &skb_shinfo(skb)->frags[f]; | |
6446a860 | 2271 | buf_len = frag->size; |
f3cc28c7 | 2272 | |
6446a860 JC |
2273 | nseg = (buf_len + ATL1_MAX_TX_BUF_LEN - 1) / |
2274 | ATL1_MAX_TX_BUF_LEN; | |
2275 | for (i = 0; i < nseg; i++) { | |
2276 | buffer_info = &tpd_ring->buffer_info[next_to_use]; | |
f3cc28c7 JC |
2277 | if (unlikely(buffer_info->skb)) |
2278 | BUG(); | |
2279 | buffer_info->skb = NULL; | |
6446a860 JC |
2280 | buffer_info->length = (buf_len > ATL1_MAX_TX_BUF_LEN) ? |
2281 | ATL1_MAX_TX_BUF_LEN : buf_len; | |
2282 | buf_len -= buffer_info->length; | |
53ffb42c JC |
2283 | buffer_info->dma = pci_map_page(adapter->pdev, |
2284 | frag->page, | |
2285 | frag->page_offset + (i * ATL1_MAX_TX_BUF_LEN), | |
2286 | buffer_info->length, PCI_DMA_TODEVICE); | |
f3cc28c7 | 2287 | |
6446a860 JC |
2288 | if (++next_to_use == tpd_ring->count) |
2289 | next_to_use = 0; | |
f3cc28c7 JC |
2290 | } |
2291 | } | |
2292 | ||
2293 | /* last tpd's buffer-info */ | |
2294 | buffer_info->skb = skb; | |
2295 | } | |
2296 | ||
6446a860 JC |
2297 | static void atl1_tx_queue(struct atl1_adapter *adapter, u16 count, |
2298 | struct tx_packet_desc *ptpd) | |
f3cc28c7 | 2299 | { |
f3cc28c7 | 2300 | struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; |
f3cc28c7 JC |
2301 | struct atl1_buffer *buffer_info; |
2302 | struct tx_packet_desc *tpd; | |
6446a860 JC |
2303 | u16 j; |
2304 | u32 val; | |
2305 | u16 next_to_use = (u16) atomic_read(&tpd_ring->next_to_use); | |
f3cc28c7 JC |
2306 | |
2307 | for (j = 0; j < count; j++) { | |
6446a860 JC |
2308 | buffer_info = &tpd_ring->buffer_info[next_to_use]; |
2309 | tpd = ATL1_TPD_DESC(&adapter->tpd_ring, next_to_use); | |
2310 | if (tpd != ptpd) | |
2311 | memcpy(tpd, ptpd, sizeof(struct tx_packet_desc)); | |
f3cc28c7 | 2312 | tpd->buffer_addr = cpu_to_le64(buffer_info->dma); |
dc5596d9 JC |
2313 | tpd->word2 &= ~(TPD_BUFLEN_MASK << TPD_BUFLEN_SHIFT); |
2314 | tpd->word2 |= (cpu_to_le16(buffer_info->length) & | |
6446a860 | 2315 | TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT; |
f3cc28c7 | 2316 | |
6446a860 JC |
2317 | /* |
2318 | * if this is the first packet in a TSO chain, set | |
2319 | * TPD_HDRFLAG, otherwise, clear it. | |
2320 | */ | |
2321 | val = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & | |
2322 | TPD_SEGMENT_EN_MASK; | |
2323 | if (val) { | |
2324 | if (!j) | |
2325 | tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT; | |
2326 | else | |
2327 | tpd->word3 &= ~(1 << TPD_HDRFLAG_SHIFT); | |
2328 | } | |
f3cc28c7 JC |
2329 | |
2330 | if (j == (count - 1)) | |
6446a860 | 2331 | tpd->word3 |= 1 << TPD_EOP_SHIFT; |
f3cc28c7 | 2332 | |
6446a860 JC |
2333 | if (++next_to_use == tpd_ring->count) |
2334 | next_to_use = 0; | |
f3cc28c7 JC |
2335 | } |
2336 | /* | |
2337 | * Force memory writes to complete before letting h/w | |
2338 | * know there are new descriptors to fetch. (Only | |
2339 | * applicable for weak-ordered memory model archs, | |
2340 | * such as IA-64). | |
2341 | */ | |
2342 | wmb(); | |
2343 | ||
6446a860 | 2344 | atomic_set(&tpd_ring->next_to_use, next_to_use); |
f3cc28c7 JC |
2345 | } |
2346 | ||
f3cc28c7 JC |
2347 | static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev) |
2348 | { | |
2349 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
6446a860 | 2350 | struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; |
f3cc28c7 JC |
2351 | int len = skb->len; |
2352 | int tso; | |
2353 | int count = 1; | |
2354 | int ret_val; | |
6446a860 | 2355 | struct tx_packet_desc *ptpd; |
f3cc28c7 JC |
2356 | u16 frag_size; |
2357 | u16 vlan_tag; | |
f3cc28c7 JC |
2358 | unsigned int nr_frags = 0; |
2359 | unsigned int mss = 0; | |
2360 | unsigned int f; | |
2361 | unsigned int proto_hdr_len; | |
2362 | ||
2363 | len -= skb->data_len; | |
2364 | ||
6446a860 | 2365 | if (unlikely(skb->len <= 0)) { |
f3cc28c7 JC |
2366 | dev_kfree_skb_any(skb); |
2367 | return NETDEV_TX_OK; | |
2368 | } | |
2369 | ||
f3cc28c7 JC |
2370 | nr_frags = skb_shinfo(skb)->nr_frags; |
2371 | for (f = 0; f < nr_frags; f++) { | |
2372 | frag_size = skb_shinfo(skb)->frags[f].size; | |
2373 | if (frag_size) | |
53ffb42c JC |
2374 | count += (frag_size + ATL1_MAX_TX_BUF_LEN - 1) / |
2375 | ATL1_MAX_TX_BUF_LEN; | |
f3cc28c7 JC |
2376 | } |
2377 | ||
f3cc28c7 JC |
2378 | mss = skb_shinfo(skb)->gso_size; |
2379 | if (mss) { | |
6446a860 | 2380 | if (skb->protocol == ntohs(ETH_P_IP)) { |
ea2ae17d | 2381 | proto_hdr_len = (skb_transport_offset(skb) + |
ab6a5bb6 | 2382 | tcp_hdrlen(skb)); |
f3cc28c7 JC |
2383 | if (unlikely(proto_hdr_len > len)) { |
2384 | dev_kfree_skb_any(skb); | |
2385 | return NETDEV_TX_OK; | |
2386 | } | |
2387 | /* need additional TPD ? */ | |
2388 | if (proto_hdr_len != len) | |
2389 | count += (len - proto_hdr_len + | |
53ffb42c JC |
2390 | ATL1_MAX_TX_BUF_LEN - 1) / |
2391 | ATL1_MAX_TX_BUF_LEN; | |
f3cc28c7 JC |
2392 | } |
2393 | } | |
2394 | ||
e6a7ff4a | 2395 | if (atl1_tpd_avail(&adapter->tpd_ring) < count) { |
f3cc28c7 JC |
2396 | /* not enough descriptors */ |
2397 | netif_stop_queue(netdev); | |
6446a860 JC |
2398 | if (netif_msg_tx_queued(adapter)) |
2399 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
2400 | "tx busy\n"); | |
f3cc28c7 JC |
2401 | return NETDEV_TX_BUSY; |
2402 | } | |
2403 | ||
6446a860 JC |
2404 | ptpd = ATL1_TPD_DESC(tpd_ring, |
2405 | (u16) atomic_read(&tpd_ring->next_to_use)); | |
2406 | memset(ptpd, 0, sizeof(struct tx_packet_desc)); | |
f3cc28c7 JC |
2407 | |
2408 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { | |
2409 | vlan_tag = vlan_tx_tag_get(skb); | |
2410 | vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) | | |
2411 | ((vlan_tag >> 9) & 0x8); | |
6446a860 | 2412 | ptpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT; |
dc5596d9 JC |
2413 | ptpd->word2 |= (vlan_tag & TPD_VLANTAG_MASK) << |
2414 | TPD_VLANTAG_SHIFT; | |
f3cc28c7 JC |
2415 | } |
2416 | ||
6446a860 | 2417 | tso = atl1_tso(adapter, skb, ptpd); |
f3cc28c7 | 2418 | if (tso < 0) { |
f3cc28c7 JC |
2419 | dev_kfree_skb_any(skb); |
2420 | return NETDEV_TX_OK; | |
2421 | } | |
2422 | ||
2423 | if (!tso) { | |
6446a860 | 2424 | ret_val = atl1_tx_csum(adapter, skb, ptpd); |
f3cc28c7 | 2425 | if (ret_val < 0) { |
f3cc28c7 JC |
2426 | dev_kfree_skb_any(skb); |
2427 | return NETDEV_TX_OK; | |
2428 | } | |
2429 | } | |
2430 | ||
6446a860 JC |
2431 | atl1_tx_map(adapter, skb, ptpd); |
2432 | atl1_tx_queue(adapter, count, ptpd); | |
f3cc28c7 | 2433 | atl1_update_mailbox(adapter); |
e1098328 | 2434 | mmiowb(); |
6446a860 | 2435 | netdev->trans_start = jiffies; |
f3cc28c7 JC |
2436 | return NETDEV_TX_OK; |
2437 | } | |
2438 | ||
2439 | /* | |
05ffdd7b JC |
2440 | * atl1_intr - Interrupt Handler |
2441 | * @irq: interrupt number | |
2442 | * @data: pointer to a network interface device structure | |
2443 | * @pt_regs: CPU registers structure | |
f3cc28c7 | 2444 | */ |
05ffdd7b | 2445 | static irqreturn_t atl1_intr(int irq, void *data) |
f3cc28c7 | 2446 | { |
05ffdd7b JC |
2447 | struct atl1_adapter *adapter = netdev_priv(data); |
2448 | u32 status; | |
05ffdd7b | 2449 | int max_ints = 10; |
f3cc28c7 | 2450 | |
05ffdd7b JC |
2451 | status = adapter->cmb.cmb->int_stats; |
2452 | if (!status) | |
2453 | return IRQ_NONE; | |
f3cc28c7 | 2454 | |
05ffdd7b JC |
2455 | do { |
2456 | /* clear CMB interrupt status at once */ | |
2457 | adapter->cmb.cmb->int_stats = 0; | |
2458 | ||
2459 | if (status & ISR_GPHY) /* clear phy status */ | |
6446a860 | 2460 | atlx_clear_phy_int(adapter); |
05ffdd7b JC |
2461 | |
2462 | /* clear ISR status, and Enable CMB DMA/Disable Interrupt */ | |
2463 | iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR); | |
2464 | ||
2465 | /* check if SMB intr */ | |
2466 | if (status & ISR_SMB) | |
2467 | atl1_inc_smb(adapter); | |
2468 | ||
2469 | /* check if PCIE PHY Link down */ | |
2470 | if (status & ISR_PHY_LINKDOWN) { | |
6446a860 JC |
2471 | if (netif_msg_intr(adapter)) |
2472 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
2473 | "pcie phy link down %x\n", status); | |
05ffdd7b JC |
2474 | if (netif_running(adapter->netdev)) { /* reset MAC */ |
2475 | iowrite32(0, adapter->hw.hw_addr + REG_IMR); | |
2476 | schedule_work(&adapter->pcie_dma_to_rst_task); | |
2477 | return IRQ_HANDLED; | |
2478 | } | |
f3cc28c7 | 2479 | } |
05ffdd7b JC |
2480 | |
2481 | /* check if DMA read/write error ? */ | |
2482 | if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) { | |
6446a860 JC |
2483 | if (netif_msg_intr(adapter)) |
2484 | dev_printk(KERN_DEBUG, &adapter->pdev->dev, | |
2485 | "pcie DMA r/w error (status = 0x%x)\n", | |
2486 | status); | |
05ffdd7b JC |
2487 | iowrite32(0, adapter->hw.hw_addr + REG_IMR); |
2488 | schedule_work(&adapter->pcie_dma_to_rst_task); | |
2489 | return IRQ_HANDLED; | |
f3cc28c7 | 2490 | } |
f3cc28c7 | 2491 | |
05ffdd7b JC |
2492 | /* link event */ |
2493 | if (status & ISR_GPHY) { | |
2494 | adapter->soft_stats.tx_carrier_errors++; | |
2495 | atl1_check_for_link(adapter); | |
2496 | } | |
f3cc28c7 | 2497 | |
05ffdd7b JC |
2498 | /* transmit event */ |
2499 | if (status & ISR_CMB_TX) | |
2500 | atl1_intr_tx(adapter); | |
f3cc28c7 | 2501 | |
05ffdd7b JC |
2502 | /* rx exception */ |
2503 | if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN | | |
2504 | ISR_RRD_OV | ISR_HOST_RFD_UNRUN | | |
2505 | ISR_HOST_RRD_OV | ISR_CMB_RX))) { | |
2506 | if (status & (ISR_RXF_OV | ISR_RFD_UNRUN | | |
2507 | ISR_RRD_OV | ISR_HOST_RFD_UNRUN | | |
2508 | ISR_HOST_RRD_OV)) | |
6446a860 JC |
2509 | if (netif_msg_intr(adapter)) |
2510 | dev_printk(KERN_DEBUG, | |
2511 | &adapter->pdev->dev, | |
2512 | "rx exception, ISR = 0x%x\n", | |
2513 | status); | |
05ffdd7b JC |
2514 | atl1_intr_rx(adapter); |
2515 | } | |
f3cc28c7 | 2516 | |
05ffdd7b JC |
2517 | if (--max_ints < 0) |
2518 | break; | |
2519 | ||
2520 | } while ((status = adapter->cmb.cmb->int_stats)); | |
2521 | ||
2522 | /* re-enable Interrupt */ | |
2523 | iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR); | |
2524 | return IRQ_HANDLED; | |
f3cc28c7 JC |
2525 | } |
2526 | ||
f3cc28c7 | 2527 | |
05ffdd7b JC |
2528 | /* |
2529 | * atl1_phy_config - Timer Call-back | |
2530 | * @data: pointer to netdev cast into an unsigned long | |
2531 | */ | |
2532 | static void atl1_phy_config(unsigned long data) | |
2533 | { | |
6446a860 JC |
2534 | struct atl1_adapter *adapter = (struct atl1_adapter *)data; |
2535 | struct atl1_hw *hw = &adapter->hw; | |
05ffdd7b | 2536 | unsigned long flags; |
f3cc28c7 | 2537 | |
05ffdd7b | 2538 | spin_lock_irqsave(&adapter->lock, flags); |
6446a860 JC |
2539 | adapter->phy_timer_pending = false; |
2540 | atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); | |
2541 | atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg); | |
2542 | atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN); | |
05ffdd7b JC |
2543 | spin_unlock_irqrestore(&adapter->lock, flags); |
2544 | } | |
2545 | ||
6446a860 JC |
2546 | /* |
2547 | * Orphaned vendor comment left intact here: | |
2548 | * <vendor comment> | |
2549 | * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT | |
2550 | * will assert. We do soft reset <0x1400=1> according | |
2551 | * with the SPEC. BUT, it seemes that PCIE or DMA | |
2552 | * state-machine will not be reset. DMAR_TO_INT will | |
2553 | * assert again and again. | |
2554 | * </vendor comment> | |
2555 | */ | |
05ffdd7b | 2556 | |
6446a860 | 2557 | static int atl1_reset(struct atl1_adapter *adapter) |
05ffdd7b JC |
2558 | { |
2559 | int ret; | |
05ffdd7b | 2560 | ret = atl1_reset_hw(&adapter->hw); |
6446a860 | 2561 | if (ret) |
05ffdd7b JC |
2562 | return ret; |
2563 | return atl1_init_hw(&adapter->hw); | |
f3cc28c7 JC |
2564 | } |
2565 | ||
6446a860 | 2566 | static s32 atl1_up(struct atl1_adapter *adapter) |
f3cc28c7 JC |
2567 | { |
2568 | struct net_device *netdev = adapter->netdev; | |
2569 | int err; | |
2570 | int irq_flags = IRQF_SAMPLE_RANDOM; | |
2571 | ||
2572 | /* hardware has been reset, we need to reload some things */ | |
6446a860 | 2573 | atlx_set_multi(netdev); |
2ca13da7 | 2574 | atl1_init_ring_ptrs(adapter); |
6446a860 | 2575 | atlx_restore_vlan(adapter); |
f3cc28c7 | 2576 | err = atl1_alloc_rx_buffers(adapter); |
6446a860 JC |
2577 | if (unlikely(!err)) |
2578 | /* no RX BUFFER allocated */ | |
f3cc28c7 JC |
2579 | return -ENOMEM; |
2580 | ||
2581 | if (unlikely(atl1_configure(adapter))) { | |
2582 | err = -EIO; | |
2583 | goto err_up; | |
2584 | } | |
2585 | ||
2586 | err = pci_enable_msi(adapter->pdev); | |
2587 | if (err) { | |
6446a860 JC |
2588 | if (netif_msg_ifup(adapter)) |
2589 | dev_info(&adapter->pdev->dev, | |
2590 | "Unable to enable MSI: %d\n", err); | |
f3cc28c7 JC |
2591 | irq_flags |= IRQF_SHARED; |
2592 | } | |
2593 | ||
2594 | err = request_irq(adapter->pdev->irq, &atl1_intr, irq_flags, | |
2595 | netdev->name, netdev); | |
2596 | if (unlikely(err)) | |
2597 | goto err_up; | |
2598 | ||
6446a860 | 2599 | atlx_irq_enable(adapter); |
f3cc28c7 | 2600 | atl1_check_link(adapter); |
39d48157 | 2601 | netif_start_queue(netdev); |
f3cc28c7 JC |
2602 | return 0; |
2603 | ||
f3cc28c7 JC |
2604 | err_up: |
2605 | pci_disable_msi(adapter->pdev); | |
2606 | /* free rx_buffers */ | |
2607 | atl1_clean_rx_ring(adapter); | |
2608 | return err; | |
2609 | } | |
2610 | ||
6446a860 | 2611 | static void atl1_down(struct atl1_adapter *adapter) |
f3cc28c7 JC |
2612 | { |
2613 | struct net_device *netdev = adapter->netdev; | |
2614 | ||
b29be6d3 | 2615 | netif_stop_queue(netdev); |
f3cc28c7 JC |
2616 | del_timer_sync(&adapter->phy_config_timer); |
2617 | adapter->phy_timer_pending = false; | |
2618 | ||
6446a860 | 2619 | atlx_irq_disable(adapter); |
f3cc28c7 JC |
2620 | free_irq(adapter->pdev->irq, netdev); |
2621 | pci_disable_msi(adapter->pdev); | |
2622 | atl1_reset_hw(&adapter->hw); | |
2623 | adapter->cmb.cmb->int_stats = 0; | |
2624 | ||
2625 | adapter->link_speed = SPEED_0; | |
2626 | adapter->link_duplex = -1; | |
2627 | netif_carrier_off(netdev); | |
f3cc28c7 | 2628 | |
f3cc28c7 JC |
2629 | atl1_clean_tx_ring(adapter); |
2630 | atl1_clean_rx_ring(adapter); | |
f3cc28c7 JC |
2631 | } |
2632 | ||
6446a860 JC |
2633 | static void atl1_tx_timeout_task(struct work_struct *work) |
2634 | { | |
2635 | struct atl1_adapter *adapter = | |
2636 | container_of(work, struct atl1_adapter, tx_timeout_task); | |
2637 | struct net_device *netdev = adapter->netdev; | |
2638 | ||
2639 | netif_device_detach(netdev); | |
2640 | atl1_down(adapter); | |
305282ba | 2641 | atl1_up(adapter); |
6446a860 | 2642 | netif_device_attach(netdev); |
305282ba JC |
2643 | } |
2644 | ||
6446a860 JC |
2645 | /* |
2646 | * atl1_change_mtu - Change the Maximum Transfer Unit | |
2647 | * @netdev: network interface device structure | |
2648 | * @new_mtu: new value for maximum frame size | |
2649 | * | |
2650 | * Returns 0 on success, negative on failure | |
2651 | */ | |
2652 | static int atl1_change_mtu(struct net_device *netdev, int new_mtu) | |
305282ba JC |
2653 | { |
2654 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
6446a860 JC |
2655 | int old_mtu = netdev->mtu; |
2656 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; | |
305282ba | 2657 | |
6446a860 JC |
2658 | if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) || |
2659 | (max_frame > MAX_JUMBO_FRAME_SIZE)) { | |
2660 | if (netif_msg_link(adapter)) | |
2661 | dev_warn(&adapter->pdev->dev, "invalid MTU setting\n"); | |
2662 | return -EINVAL; | |
305282ba | 2663 | } |
6446a860 JC |
2664 | |
2665 | adapter->hw.max_frame_size = max_frame; | |
2666 | adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3; | |
2667 | adapter->rx_buffer_len = (max_frame + 7) & ~7; | |
2668 | adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8; | |
2669 | ||
2670 | netdev->mtu = new_mtu; | |
2671 | if ((old_mtu != new_mtu) && netif_running(netdev)) { | |
2672 | atl1_down(adapter); | |
2673 | atl1_up(adapter); | |
2674 | } | |
2675 | ||
2676 | return 0; | |
305282ba JC |
2677 | } |
2678 | ||
f3cc28c7 JC |
2679 | /* |
2680 | * atl1_open - Called when a network interface is made active | |
2681 | * @netdev: network interface device structure | |
2682 | * | |
2683 | * Returns 0 on success, negative value on failure | |
2684 | * | |
2685 | * The open entry point is called when a network interface is made | |
2686 | * active by the system (IFF_UP). At this point all resources needed | |
2687 | * for transmit and receive operations are allocated, the interrupt | |
2688 | * handler is registered with the OS, the watchdog timer is started, | |
2689 | * and the stack is notified that the interface is ready. | |
2690 | */ | |
2691 | static int atl1_open(struct net_device *netdev) | |
2692 | { | |
2693 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
2694 | int err; | |
2695 | ||
b29be6d3 JC |
2696 | netif_carrier_off(netdev); |
2697 | ||
f3cc28c7 JC |
2698 | /* allocate transmit descriptors */ |
2699 | err = atl1_setup_ring_resources(adapter); | |
2700 | if (err) | |
2701 | return err; | |
2702 | ||
2703 | err = atl1_up(adapter); | |
2704 | if (err) | |
2705 | goto err_up; | |
2706 | ||
2707 | return 0; | |
2708 | ||
2709 | err_up: | |
2710 | atl1_reset(adapter); | |
2711 | return err; | |
2712 | } | |
2713 | ||
2714 | /* | |
2715 | * atl1_close - Disables a network interface | |
2716 | * @netdev: network interface device structure | |
2717 | * | |
2718 | * Returns 0, this is not allowed to fail | |
2719 | * | |
2720 | * The close entry point is called when an interface is de-activated | |
2721 | * by the OS. The hardware is still under the drivers control, but | |
2722 | * needs to be disabled. A global MAC reset is issued to stop the | |
2723 | * hardware, and all transmit and receive resources are freed. | |
2724 | */ | |
2725 | static int atl1_close(struct net_device *netdev) | |
2726 | { | |
2727 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
2728 | atl1_down(adapter); | |
2729 | atl1_free_ring_resources(adapter); | |
2730 | return 0; | |
2731 | } | |
2732 | ||
05ffdd7b JC |
2733 | #ifdef CONFIG_PM |
2734 | static int atl1_suspend(struct pci_dev *pdev, pm_message_t state) | |
f3cc28c7 | 2735 | { |
05ffdd7b JC |
2736 | struct net_device *netdev = pci_get_drvdata(pdev); |
2737 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
2738 | struct atl1_hw *hw = &adapter->hw; | |
2739 | u32 ctrl = 0; | |
2740 | u32 wufc = adapter->wol; | |
08e0f1dc JC |
2741 | u32 val; |
2742 | int retval; | |
2743 | u16 speed; | |
2744 | u16 duplex; | |
f3cc28c7 JC |
2745 | |
2746 | netif_device_detach(netdev); | |
05ffdd7b JC |
2747 | if (netif_running(netdev)) |
2748 | atl1_down(adapter); | |
f3cc28c7 | 2749 | |
08e0f1dc JC |
2750 | retval = pci_save_state(pdev); |
2751 | if (retval) | |
2752 | return retval; | |
2753 | ||
05ffdd7b JC |
2754 | atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl); |
2755 | atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl); | |
08e0f1dc JC |
2756 | val = ctrl & BMSR_LSTATUS; |
2757 | if (val) | |
6446a860 | 2758 | wufc &= ~ATLX_WUFC_LNKC; |
f3cc28c7 | 2759 | |
08e0f1dc JC |
2760 | if (val && wufc) { |
2761 | val = atl1_get_speed_and_duplex(hw, &speed, &duplex); | |
2762 | if (val) { | |
2763 | if (netif_msg_ifdown(adapter)) | |
2764 | dev_printk(KERN_DEBUG, &pdev->dev, | |
2765 | "error getting speed/duplex\n"); | |
2766 | goto disable_wol; | |
2767 | } | |
05ffdd7b JC |
2768 | |
2769 | ctrl = 0; | |
05ffdd7b | 2770 | |
08e0f1dc JC |
2771 | /* enable magic packet WOL */ |
2772 | if (wufc & ATLX_WUFC_MAG) | |
2773 | ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN); | |
05ffdd7b | 2774 | iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL); |
08e0f1dc JC |
2775 | ioread32(hw->hw_addr + REG_WOL_CTRL); |
2776 | ||
2777 | /* configure the mac */ | |
2778 | ctrl = MAC_CTRL_RX_EN; | |
2779 | ctrl |= ((u32)((speed == SPEED_1000) ? MAC_CTRL_SPEED_1000 : | |
2780 | MAC_CTRL_SPEED_10_100) << MAC_CTRL_SPEED_SHIFT); | |
2781 | if (duplex == FULL_DUPLEX) | |
2782 | ctrl |= MAC_CTRL_DUPLX; | |
2783 | ctrl |= (((u32)adapter->hw.preamble_len & | |
2784 | MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); | |
2785 | if (adapter->vlgrp) | |
2786 | ctrl |= MAC_CTRL_RMV_VLAN; | |
2787 | if (wufc & ATLX_WUFC_MAG) | |
05ffdd7b | 2788 | ctrl |= MAC_CTRL_BC_EN; |
05ffdd7b | 2789 | iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL); |
08e0f1dc JC |
2790 | ioread32(hw->hw_addr + REG_MAC_CTRL); |
2791 | ||
2792 | /* poke the PHY */ | |
2793 | ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC); | |
2794 | ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; | |
2795 | iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC); | |
2796 | ioread32(hw->hw_addr + REG_PCIE_PHYMISC); | |
2797 | ||
2798 | pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); | |
2799 | goto exit; | |
05ffdd7b JC |
2800 | } |
2801 | ||
08e0f1dc JC |
2802 | if (!val && wufc) { |
2803 | ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN); | |
2804 | iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL); | |
2805 | ioread32(hw->hw_addr + REG_WOL_CTRL); | |
2806 | iowrite32(0, hw->hw_addr + REG_MAC_CTRL); | |
2807 | ioread32(hw->hw_addr + REG_MAC_CTRL); | |
2808 | hw->phy_configured = false; | |
2809 | pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); | |
2810 | goto exit; | |
2811 | } | |
05ffdd7b | 2812 | |
08e0f1dc JC |
2813 | disable_wol: |
2814 | iowrite32(0, hw->hw_addr + REG_WOL_CTRL); | |
2815 | ioread32(hw->hw_addr + REG_WOL_CTRL); | |
2816 | ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC); | |
2817 | ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; | |
2818 | iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC); | |
2819 | ioread32(hw->hw_addr + REG_PCIE_PHYMISC); | |
08e0f1dc JC |
2820 | hw->phy_configured = false; |
2821 | pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); | |
2822 | exit: | |
2823 | if (netif_running(netdev)) | |
2824 | pci_disable_msi(adapter->pdev); | |
2825 | pci_disable_device(pdev); | |
2826 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
05ffdd7b JC |
2827 | |
2828 | return 0; | |
f3cc28c7 JC |
2829 | } |
2830 | ||
05ffdd7b | 2831 | static int atl1_resume(struct pci_dev *pdev) |
f3cc28c7 | 2832 | { |
05ffdd7b JC |
2833 | struct net_device *netdev = pci_get_drvdata(pdev); |
2834 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
6446a860 | 2835 | u32 err; |
53ffb42c | 2836 | |
6446a860 | 2837 | pci_set_power_state(pdev, PCI_D0); |
05ffdd7b JC |
2838 | pci_restore_state(pdev); |
2839 | ||
6446a860 | 2840 | err = pci_enable_device(pdev); |
08e0f1dc JC |
2841 | if (err) { |
2842 | if (netif_msg_ifup(adapter)) | |
2843 | dev_printk(KERN_DEBUG, &pdev->dev, | |
2844 | "error enabling pci device\n"); | |
2845 | return err; | |
2846 | } | |
2847 | ||
2848 | pci_set_master(pdev); | |
2849 | iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL); | |
05ffdd7b JC |
2850 | pci_enable_wake(pdev, PCI_D3hot, 0); |
2851 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
2852 | ||
08e0f1dc JC |
2853 | atl1_reset_hw(&adapter->hw); |
2854 | adapter->cmb.cmb->int_stats = 0; | |
05ffdd7b JC |
2855 | |
2856 | if (netif_running(netdev)) | |
2857 | atl1_up(adapter); | |
2858 | netif_device_attach(netdev); | |
05ffdd7b JC |
2859 | |
2860 | return 0; | |
f3cc28c7 | 2861 | } |
05ffdd7b JC |
2862 | #else |
2863 | #define atl1_suspend NULL | |
2864 | #define atl1_resume NULL | |
2865 | #endif | |
f3cc28c7 | 2866 | |
bf455a22 JC |
2867 | static void atl1_shutdown(struct pci_dev *pdev) |
2868 | { | |
2869 | #ifdef CONFIG_PM | |
2870 | atl1_suspend(pdev, PMSG_SUSPEND); | |
2871 | #endif | |
2872 | } | |
2873 | ||
05ffdd7b JC |
2874 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2875 | static void atl1_poll_controller(struct net_device *netdev) | |
f3cc28c7 | 2876 | { |
05ffdd7b JC |
2877 | disable_irq(netdev->irq); |
2878 | atl1_intr(netdev->irq, netdev); | |
2879 | enable_irq(netdev->irq); | |
f3cc28c7 | 2880 | } |
05ffdd7b | 2881 | #endif |
f3cc28c7 | 2882 | |
825a84d1 SH |
2883 | static const struct net_device_ops atl1_netdev_ops = { |
2884 | .ndo_open = atl1_open, | |
2885 | .ndo_stop = atl1_close, | |
00829823 | 2886 | .ndo_start_xmit = atl1_xmit_frame, |
825a84d1 SH |
2887 | .ndo_set_multicast_list = atlx_set_multi, |
2888 | .ndo_validate_addr = eth_validate_addr, | |
2889 | .ndo_set_mac_address = atl1_set_mac, | |
2890 | .ndo_change_mtu = atl1_change_mtu, | |
2891 | .ndo_do_ioctl = atlx_ioctl, | |
00829823 | 2892 | .ndo_tx_timeout = atlx_tx_timeout, |
825a84d1 SH |
2893 | .ndo_vlan_rx_register = atlx_vlan_rx_register, |
2894 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2895 | .ndo_poll_controller = atl1_poll_controller, | |
2896 | #endif | |
2897 | }; | |
2898 | ||
f3cc28c7 JC |
2899 | /* |
2900 | * atl1_probe - Device Initialization Routine | |
2901 | * @pdev: PCI device information struct | |
2902 | * @ent: entry in atl1_pci_tbl | |
2903 | * | |
2904 | * Returns 0 on success, negative on failure | |
2905 | * | |
2906 | * atl1_probe initializes an adapter identified by a pci_dev structure. | |
2907 | * The OS initialization, configuring of the adapter private structure, | |
2908 | * and a hardware reset occur. | |
2909 | */ | |
2910 | static int __devinit atl1_probe(struct pci_dev *pdev, | |
53ffb42c | 2911 | const struct pci_device_id *ent) |
f3cc28c7 JC |
2912 | { |
2913 | struct net_device *netdev; | |
2914 | struct atl1_adapter *adapter; | |
2915 | static int cards_found = 0; | |
f3cc28c7 JC |
2916 | int err; |
2917 | ||
2918 | err = pci_enable_device(pdev); | |
2919 | if (err) | |
2920 | return err; | |
2921 | ||
5f08e46b | 2922 | /* |
cdcc520d CS |
2923 | * The atl1 chip can DMA to 64-bit addresses, but it uses a single |
2924 | * shared register for the high 32 bits, so only a single, aligned, | |
2925 | * 4 GB physical address range can be used at a time. | |
2926 | * | |
2927 | * Supporting 64-bit DMA on this hardware is more trouble than it's | |
2928 | * worth. It is far easier to limit to 32-bit DMA than update | |
2929 | * various kernel subsystems to support the mechanics required by a | |
2930 | * fixed-high-32-bit system. | |
5f08e46b | 2931 | */ |
284901a9 | 2932 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
f3cc28c7 | 2933 | if (err) { |
5f08e46b LT |
2934 | dev_err(&pdev->dev, "no usable DMA configuration\n"); |
2935 | goto err_dma; | |
f3cc28c7 | 2936 | } |
6446a860 JC |
2937 | /* |
2938 | * Mark all PCI regions associated with PCI device | |
f3cc28c7 JC |
2939 | * pdev as being reserved by owner atl1_driver_name |
2940 | */ | |
6446a860 | 2941 | err = pci_request_regions(pdev, ATLX_DRIVER_NAME); |
f3cc28c7 JC |
2942 | if (err) |
2943 | goto err_request_regions; | |
2944 | ||
6446a860 JC |
2945 | /* |
2946 | * Enables bus-mastering on the device and calls | |
f3cc28c7 JC |
2947 | * pcibios_set_master to do the needed arch specific settings |
2948 | */ | |
2949 | pci_set_master(pdev); | |
2950 | ||
2951 | netdev = alloc_etherdev(sizeof(struct atl1_adapter)); | |
2952 | if (!netdev) { | |
2953 | err = -ENOMEM; | |
2954 | goto err_alloc_etherdev; | |
2955 | } | |
f3cc28c7 JC |
2956 | SET_NETDEV_DEV(netdev, &pdev->dev); |
2957 | ||
2958 | pci_set_drvdata(pdev, netdev); | |
2959 | adapter = netdev_priv(netdev); | |
2960 | adapter->netdev = netdev; | |
2961 | adapter->pdev = pdev; | |
2962 | adapter->hw.back = adapter; | |
6446a860 | 2963 | adapter->msg_enable = netif_msg_init(debug, atl1_default_msg); |
f3cc28c7 JC |
2964 | |
2965 | adapter->hw.hw_addr = pci_iomap(pdev, 0, 0); | |
2966 | if (!adapter->hw.hw_addr) { | |
2967 | err = -EIO; | |
2968 | goto err_pci_iomap; | |
2969 | } | |
2970 | /* get device revision number */ | |
1e006364 | 2971 | adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr + |
53ffb42c | 2972 | (REG_MASTER_CTRL + 2)); |
6446a860 JC |
2973 | if (netif_msg_probe(adapter)) |
2974 | dev_info(&pdev->dev, "version %s\n", ATLX_DRIVER_VERSION); | |
f3cc28c7 JC |
2975 | |
2976 | /* set default ring resource counts */ | |
2977 | adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD; | |
2978 | adapter->tpd_ring.count = ATL1_DEFAULT_TPD; | |
2979 | ||
2980 | adapter->mii.dev = netdev; | |
2981 | adapter->mii.mdio_read = mdio_read; | |
2982 | adapter->mii.mdio_write = mdio_write; | |
2983 | adapter->mii.phy_id_mask = 0x1f; | |
2984 | adapter->mii.reg_num_mask = 0x1f; | |
2985 | ||
825a84d1 | 2986 | netdev->netdev_ops = &atl1_netdev_ops; |
f3cc28c7 | 2987 | netdev->watchdog_timeo = 5 * HZ; |
cb434e38 | 2988 | |
f3cc28c7 JC |
2989 | netdev->ethtool_ops = &atl1_ethtool_ops; |
2990 | adapter->bd_number = cards_found; | |
f3cc28c7 JC |
2991 | |
2992 | /* setup the private structure */ | |
2993 | err = atl1_sw_init(adapter); | |
2994 | if (err) | |
2995 | goto err_common; | |
2996 | ||
2997 | netdev->features = NETIF_F_HW_CSUM; | |
2998 | netdev->features |= NETIF_F_SG; | |
2999 | netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX); | |
f3cc28c7 JC |
3000 | |
3001 | /* | |
3002 | * patch for some L1 of old version, | |
3003 | * the final version of L1 may not need these | |
3004 | * patches | |
3005 | */ | |
3006 | /* atl1_pcie_patch(adapter); */ | |
3007 | ||
3008 | /* really reset GPHY core */ | |
6446a860 | 3009 | iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE); |
f3cc28c7 JC |
3010 | |
3011 | /* | |
3012 | * reset the controller to | |
3013 | * put the device in a known good starting state | |
3014 | */ | |
3015 | if (atl1_reset_hw(&adapter->hw)) { | |
3016 | err = -EIO; | |
3017 | goto err_common; | |
3018 | } | |
3019 | ||
3020 | /* copy the MAC address out of the EEPROM */ | |
3021 | atl1_read_mac_addr(&adapter->hw); | |
3022 | memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); | |
3023 | ||
3024 | if (!is_valid_ether_addr(netdev->dev_addr)) { | |
3025 | err = -EIO; | |
3026 | goto err_common; | |
3027 | } | |
3028 | ||
3029 | atl1_check_options(adapter); | |
3030 | ||
3031 | /* pre-init the MAC, and setup link */ | |
3032 | err = atl1_init_hw(&adapter->hw); | |
3033 | if (err) { | |
3034 | err = -EIO; | |
3035 | goto err_common; | |
3036 | } | |
3037 | ||
3038 | atl1_pcie_patch(adapter); | |
3039 | /* assume we have no link for now */ | |
3040 | netif_carrier_off(netdev); | |
3041 | netif_stop_queue(netdev); | |
3042 | ||
e053b628 SH |
3043 | setup_timer(&adapter->phy_config_timer, &atl1_phy_config, |
3044 | (unsigned long)adapter); | |
f3cc28c7 JC |
3045 | adapter->phy_timer_pending = false; |
3046 | ||
3047 | INIT_WORK(&adapter->tx_timeout_task, atl1_tx_timeout_task); | |
3048 | ||
6446a860 | 3049 | INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task); |
f3cc28c7 JC |
3050 | |
3051 | INIT_WORK(&adapter->pcie_dma_to_rst_task, atl1_tx_timeout_task); | |
3052 | ||
3053 | err = register_netdev(netdev); | |
3054 | if (err) | |
3055 | goto err_common; | |
3056 | ||
3057 | cards_found++; | |
3058 | atl1_via_workaround(adapter); | |
3059 | return 0; | |
3060 | ||
3061 | err_common: | |
3062 | pci_iounmap(pdev, adapter->hw.hw_addr); | |
3063 | err_pci_iomap: | |
3064 | free_netdev(netdev); | |
3065 | err_alloc_etherdev: | |
3066 | pci_release_regions(pdev); | |
3067 | err_dma: | |
3068 | err_request_regions: | |
3069 | pci_disable_device(pdev); | |
3070 | return err; | |
3071 | } | |
3072 | ||
3073 | /* | |
3074 | * atl1_remove - Device Removal Routine | |
3075 | * @pdev: PCI device information struct | |
3076 | * | |
3077 | * atl1_remove is called by the PCI subsystem to alert the driver | |
3078 | * that it should release a PCI device. The could be caused by a | |
3079 | * Hot-Plug event, or because the driver is going to be removed from | |
3080 | * memory. | |
3081 | */ | |
3082 | static void __devexit atl1_remove(struct pci_dev *pdev) | |
3083 | { | |
3084 | struct net_device *netdev = pci_get_drvdata(pdev); | |
3085 | struct atl1_adapter *adapter; | |
3086 | /* Device not available. Return. */ | |
3087 | if (!netdev) | |
3088 | return; | |
3089 | ||
3090 | adapter = netdev_priv(netdev); | |
8c754a04 | 3091 | |
6446a860 JC |
3092 | /* |
3093 | * Some atl1 boards lack persistent storage for their MAC, and get it | |
8c754a04 CS |
3094 | * from the BIOS during POST. If we've been messing with the MAC |
3095 | * address, we need to save the permanent one. | |
3096 | */ | |
3097 | if (memcmp(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, ETH_ALEN)) { | |
53ffb42c JC |
3098 | memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, |
3099 | ETH_ALEN); | |
8c754a04 CS |
3100 | atl1_set_mac_addr(&adapter->hw); |
3101 | } | |
3102 | ||
6446a860 | 3103 | iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE); |
f3cc28c7 JC |
3104 | unregister_netdev(netdev); |
3105 | pci_iounmap(pdev, adapter->hw.hw_addr); | |
3106 | pci_release_regions(pdev); | |
3107 | free_netdev(netdev); | |
3108 | pci_disable_device(pdev); | |
3109 | } | |
3110 | ||
f3cc28c7 | 3111 | static struct pci_driver atl1_driver = { |
6446a860 | 3112 | .name = ATLX_DRIVER_NAME, |
f3cc28c7 JC |
3113 | .id_table = atl1_pci_tbl, |
3114 | .probe = atl1_probe, | |
3115 | .remove = __devexit_p(atl1_remove), | |
f3cc28c7 | 3116 | .suspend = atl1_suspend, |
bf455a22 JC |
3117 | .resume = atl1_resume, |
3118 | .shutdown = atl1_shutdown | |
f3cc28c7 JC |
3119 | }; |
3120 | ||
3121 | /* | |
3122 | * atl1_exit_module - Driver Exit Cleanup Routine | |
3123 | * | |
3124 | * atl1_exit_module is called just before the driver is removed | |
3125 | * from memory. | |
3126 | */ | |
3127 | static void __exit atl1_exit_module(void) | |
3128 | { | |
3129 | pci_unregister_driver(&atl1_driver); | |
3130 | } | |
3131 | ||
3132 | /* | |
3133 | * atl1_init_module - Driver Registration Routine | |
3134 | * | |
3135 | * atl1_init_module is the first routine called when the driver is | |
3136 | * loaded. All it does is register with the PCI subsystem. | |
3137 | */ | |
3138 | static int __init atl1_init_module(void) | |
3139 | { | |
f3cc28c7 JC |
3140 | return pci_register_driver(&atl1_driver); |
3141 | } | |
3142 | ||
3143 | module_init(atl1_init_module); | |
3144 | module_exit(atl1_exit_module); | |
6446a860 JC |
3145 | |
3146 | struct atl1_stats { | |
3147 | char stat_string[ETH_GSTRING_LEN]; | |
3148 | int sizeof_stat; | |
3149 | int stat_offset; | |
3150 | }; | |
3151 | ||
3152 | #define ATL1_STAT(m) \ | |
3153 | sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m) | |
3154 | ||
3155 | static struct atl1_stats atl1_gstrings_stats[] = { | |
3156 | {"rx_packets", ATL1_STAT(soft_stats.rx_packets)}, | |
3157 | {"tx_packets", ATL1_STAT(soft_stats.tx_packets)}, | |
3158 | {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)}, | |
3159 | {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)}, | |
3160 | {"rx_errors", ATL1_STAT(soft_stats.rx_errors)}, | |
3161 | {"tx_errors", ATL1_STAT(soft_stats.tx_errors)}, | |
6446a860 JC |
3162 | {"multicast", ATL1_STAT(soft_stats.multicast)}, |
3163 | {"collisions", ATL1_STAT(soft_stats.collisions)}, | |
3164 | {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)}, | |
3165 | {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)}, | |
3166 | {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)}, | |
3167 | {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)}, | |
3168 | {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)}, | |
3169 | {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)}, | |
3170 | {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)}, | |
3171 | {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)}, | |
3172 | {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)}, | |
3173 | {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)}, | |
3174 | {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)}, | |
3175 | {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)}, | |
3176 | {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)}, | |
3177 | {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)}, | |
3178 | {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)}, | |
3179 | {"tx_underun", ATL1_STAT(soft_stats.tx_underun)}, | |
3180 | {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)}, | |
3181 | {"tx_pause", ATL1_STAT(soft_stats.tx_pause)}, | |
3182 | {"rx_pause", ATL1_STAT(soft_stats.rx_pause)}, | |
3183 | {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)}, | |
3184 | {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)} | |
3185 | }; | |
3186 | ||
3187 | static void atl1_get_ethtool_stats(struct net_device *netdev, | |
3188 | struct ethtool_stats *stats, u64 *data) | |
305282ba | 3189 | { |
6446a860 | 3190 | struct atl1_adapter *adapter = netdev_priv(netdev); |
305282ba | 3191 | int i; |
6446a860 | 3192 | char *p; |
305282ba | 3193 | |
6446a860 JC |
3194 | for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) { |
3195 | p = (char *)adapter+atl1_gstrings_stats[i].stat_offset; | |
3196 | data[i] = (atl1_gstrings_stats[i].sizeof_stat == | |
3197 | sizeof(u64)) ? *(u64 *)p : *(u32 *)p; | |
305282ba JC |
3198 | } |
3199 | ||
305282ba JC |
3200 | } |
3201 | ||
6446a860 | 3202 | static int atl1_get_sset_count(struct net_device *netdev, int sset) |
305282ba | 3203 | { |
6446a860 JC |
3204 | switch (sset) { |
3205 | case ETH_SS_STATS: | |
3206 | return ARRAY_SIZE(atl1_gstrings_stats); | |
3207 | default: | |
3208 | return -EOPNOTSUPP; | |
3209 | } | |
305282ba JC |
3210 | } |
3211 | ||
6446a860 JC |
3212 | static int atl1_get_settings(struct net_device *netdev, |
3213 | struct ethtool_cmd *ecmd) | |
305282ba | 3214 | { |
6446a860 JC |
3215 | struct atl1_adapter *adapter = netdev_priv(netdev); |
3216 | struct atl1_hw *hw = &adapter->hw; | |
3217 | ||
3218 | ecmd->supported = (SUPPORTED_10baseT_Half | | |
3219 | SUPPORTED_10baseT_Full | | |
3220 | SUPPORTED_100baseT_Half | | |
3221 | SUPPORTED_100baseT_Full | | |
3222 | SUPPORTED_1000baseT_Full | | |
3223 | SUPPORTED_Autoneg | SUPPORTED_TP); | |
3224 | ecmd->advertising = ADVERTISED_TP; | |
3225 | if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || | |
3226 | hw->media_type == MEDIA_TYPE_1000M_FULL) { | |
3227 | ecmd->advertising |= ADVERTISED_Autoneg; | |
3228 | if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) { | |
3229 | ecmd->advertising |= ADVERTISED_Autoneg; | |
3230 | ecmd->advertising |= | |
3231 | (ADVERTISED_10baseT_Half | | |
3232 | ADVERTISED_10baseT_Full | | |
3233 | ADVERTISED_100baseT_Half | | |
3234 | ADVERTISED_100baseT_Full | | |
3235 | ADVERTISED_1000baseT_Full); | |
3236 | } else | |
3237 | ecmd->advertising |= (ADVERTISED_1000baseT_Full); | |
3238 | } | |
3239 | ecmd->port = PORT_TP; | |
3240 | ecmd->phy_address = 0; | |
3241 | ecmd->transceiver = XCVR_INTERNAL; | |
3242 | ||
3243 | if (netif_carrier_ok(adapter->netdev)) { | |
3244 | u16 link_speed, link_duplex; | |
3245 | atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex); | |
3246 | ecmd->speed = link_speed; | |
3247 | if (link_duplex == FULL_DUPLEX) | |
3248 | ecmd->duplex = DUPLEX_FULL; | |
3249 | else | |
3250 | ecmd->duplex = DUPLEX_HALF; | |
3251 | } else { | |
3252 | ecmd->speed = -1; | |
3253 | ecmd->duplex = -1; | |
3254 | } | |
3255 | if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || | |
3256 | hw->media_type == MEDIA_TYPE_1000M_FULL) | |
3257 | ecmd->autoneg = AUTONEG_ENABLE; | |
3258 | else | |
3259 | ecmd->autoneg = AUTONEG_DISABLE; | |
305282ba | 3260 | |
305282ba JC |
3261 | return 0; |
3262 | } | |
3263 | ||
6446a860 JC |
3264 | static int atl1_set_settings(struct net_device *netdev, |
3265 | struct ethtool_cmd *ecmd) | |
305282ba | 3266 | { |
6446a860 JC |
3267 | struct atl1_adapter *adapter = netdev_priv(netdev); |
3268 | struct atl1_hw *hw = &adapter->hw; | |
305282ba | 3269 | u16 phy_data; |
6446a860 JC |
3270 | int ret_val = 0; |
3271 | u16 old_media_type = hw->media_type; | |
305282ba | 3272 | |
6446a860 JC |
3273 | if (netif_running(adapter->netdev)) { |
3274 | if (netif_msg_link(adapter)) | |
3275 | dev_dbg(&adapter->pdev->dev, | |
3276 | "ethtool shutting down adapter\n"); | |
3277 | atl1_down(adapter); | |
3278 | } | |
3279 | ||
3280 | if (ecmd->autoneg == AUTONEG_ENABLE) | |
3281 | hw->media_type = MEDIA_TYPE_AUTO_SENSOR; | |
3282 | else { | |
3283 | if (ecmd->speed == SPEED_1000) { | |
3284 | if (ecmd->duplex != DUPLEX_FULL) { | |
3285 | if (netif_msg_link(adapter)) | |
3286 | dev_warn(&adapter->pdev->dev, | |
3287 | "1000M half is invalid\n"); | |
3288 | ret_val = -EINVAL; | |
3289 | goto exit_sset; | |
3290 | } | |
3291 | hw->media_type = MEDIA_TYPE_1000M_FULL; | |
3292 | } else if (ecmd->speed == SPEED_100) { | |
3293 | if (ecmd->duplex == DUPLEX_FULL) | |
3294 | hw->media_type = MEDIA_TYPE_100M_FULL; | |
3295 | else | |
3296 | hw->media_type = MEDIA_TYPE_100M_HALF; | |
3297 | } else { | |
3298 | if (ecmd->duplex == DUPLEX_FULL) | |
3299 | hw->media_type = MEDIA_TYPE_10M_FULL; | |
3300 | else | |
3301 | hw->media_type = MEDIA_TYPE_10M_HALF; | |
3302 | } | |
3303 | } | |
3304 | switch (hw->media_type) { | |
3305 | case MEDIA_TYPE_AUTO_SENSOR: | |
3306 | ecmd->advertising = | |
3307 | ADVERTISED_10baseT_Half | | |
3308 | ADVERTISED_10baseT_Full | | |
3309 | ADVERTISED_100baseT_Half | | |
3310 | ADVERTISED_100baseT_Full | | |
3311 | ADVERTISED_1000baseT_Full | | |
3312 | ADVERTISED_Autoneg | ADVERTISED_TP; | |
3313 | break; | |
3314 | case MEDIA_TYPE_1000M_FULL: | |
3315 | ecmd->advertising = | |
3316 | ADVERTISED_1000baseT_Full | | |
3317 | ADVERTISED_Autoneg | ADVERTISED_TP; | |
3318 | break; | |
3319 | default: | |
3320 | ecmd->advertising = 0; | |
3321 | break; | |
3322 | } | |
3323 | if (atl1_phy_setup_autoneg_adv(hw)) { | |
3324 | ret_val = -EINVAL; | |
3325 | if (netif_msg_link(adapter)) | |
3326 | dev_warn(&adapter->pdev->dev, | |
3327 | "invalid ethtool speed/duplex setting\n"); | |
3328 | goto exit_sset; | |
3329 | } | |
305282ba JC |
3330 | if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || |
3331 | hw->media_type == MEDIA_TYPE_1000M_FULL) | |
3332 | phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; | |
3333 | else { | |
3334 | switch (hw->media_type) { | |
3335 | case MEDIA_TYPE_100M_FULL: | |
3336 | phy_data = | |
3337 | MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 | | |
3338 | MII_CR_RESET; | |
3339 | break; | |
3340 | case MEDIA_TYPE_100M_HALF: | |
3341 | phy_data = MII_CR_SPEED_100 | MII_CR_RESET; | |
3342 | break; | |
3343 | case MEDIA_TYPE_10M_FULL: | |
3344 | phy_data = | |
3345 | MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET; | |
3346 | break; | |
3347 | default: | |
3348 | /* MEDIA_TYPE_10M_HALF: */ | |
3349 | phy_data = MII_CR_SPEED_10 | MII_CR_RESET; | |
3350 | break; | |
3351 | } | |
3352 | } | |
6446a860 JC |
3353 | atl1_write_phy_reg(hw, MII_BMCR, phy_data); |
3354 | exit_sset: | |
3355 | if (ret_val) | |
3356 | hw->media_type = old_media_type; | |
305282ba | 3357 | |
6446a860 JC |
3358 | if (netif_running(adapter->netdev)) { |
3359 | if (netif_msg_link(adapter)) | |
3360 | dev_dbg(&adapter->pdev->dev, | |
3361 | "ethtool starting adapter\n"); | |
3362 | atl1_up(adapter); | |
3363 | } else if (!ret_val) { | |
3364 | if (netif_msg_link(adapter)) | |
3365 | dev_dbg(&adapter->pdev->dev, | |
3366 | "ethtool resetting adapter\n"); | |
3367 | atl1_reset(adapter); | |
3368 | } | |
3369 | return ret_val; | |
3370 | } | |
305282ba | 3371 | |
6446a860 JC |
3372 | static void atl1_get_drvinfo(struct net_device *netdev, |
3373 | struct ethtool_drvinfo *drvinfo) | |
3374 | { | |
3375 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
305282ba | 3376 | |
6446a860 JC |
3377 | strncpy(drvinfo->driver, ATLX_DRIVER_NAME, sizeof(drvinfo->driver)); |
3378 | strncpy(drvinfo->version, ATLX_DRIVER_VERSION, | |
3379 | sizeof(drvinfo->version)); | |
3380 | strncpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); | |
3381 | strncpy(drvinfo->bus_info, pci_name(adapter->pdev), | |
3382 | sizeof(drvinfo->bus_info)); | |
3383 | drvinfo->eedump_len = ATL1_EEDUMP_LEN; | |
3384 | } | |
3385 | ||
3386 | static void atl1_get_wol(struct net_device *netdev, | |
3387 | struct ethtool_wolinfo *wol) | |
3388 | { | |
3389 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
3390 | ||
3b259e36 | 3391 | wol->supported = WAKE_MAGIC; |
6446a860 | 3392 | wol->wolopts = 0; |
6446a860 JC |
3393 | if (adapter->wol & ATLX_WUFC_MAG) |
3394 | wol->wolopts |= WAKE_MAGIC; | |
3395 | return; | |
3396 | } | |
3397 | ||
3398 | static int atl1_set_wol(struct net_device *netdev, | |
3399 | struct ethtool_wolinfo *wol) | |
3400 | { | |
3401 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
3402 | ||
3b259e36 C |
3403 | if (wol->wolopts & (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | |
3404 | WAKE_ARP | WAKE_MAGICSECURE)) | |
6446a860 JC |
3405 | return -EOPNOTSUPP; |
3406 | adapter->wol = 0; | |
6446a860 JC |
3407 | if (wol->wolopts & WAKE_MAGIC) |
3408 | adapter->wol |= ATLX_WUFC_MAG; | |
305282ba JC |
3409 | return 0; |
3410 | } | |
3411 | ||
6446a860 | 3412 | static u32 atl1_get_msglevel(struct net_device *netdev) |
305282ba | 3413 | { |
6446a860 JC |
3414 | struct atl1_adapter *adapter = netdev_priv(netdev); |
3415 | return adapter->msg_enable; | |
3416 | } | |
305282ba | 3417 | |
6446a860 JC |
3418 | static void atl1_set_msglevel(struct net_device *netdev, u32 value) |
3419 | { | |
3420 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
3421 | adapter->msg_enable = value; | |
3422 | } | |
305282ba | 3423 | |
6446a860 JC |
3424 | static int atl1_get_regs_len(struct net_device *netdev) |
3425 | { | |
3426 | return ATL1_REG_COUNT * sizeof(u32); | |
3427 | } | |
305282ba | 3428 | |
6446a860 JC |
3429 | static void atl1_get_regs(struct net_device *netdev, struct ethtool_regs *regs, |
3430 | void *p) | |
3431 | { | |
3432 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
3433 | struct atl1_hw *hw = &adapter->hw; | |
3434 | unsigned int i; | |
3435 | u32 *regbuf = p; | |
305282ba | 3436 | |
6446a860 JC |
3437 | for (i = 0; i < ATL1_REG_COUNT; i++) { |
3438 | /* | |
3439 | * This switch statement avoids reserved regions | |
3440 | * of register space. | |
3441 | */ | |
3442 | switch (i) { | |
3443 | case 6 ... 9: | |
3444 | case 14: | |
3445 | case 29 ... 31: | |
3446 | case 34 ... 63: | |
3447 | case 75 ... 127: | |
3448 | case 136 ... 1023: | |
3449 | case 1027 ... 1087: | |
3450 | case 1091 ... 1151: | |
3451 | case 1194 ... 1195: | |
3452 | case 1200 ... 1201: | |
3453 | case 1206 ... 1213: | |
3454 | case 1216 ... 1279: | |
3455 | case 1290 ... 1311: | |
3456 | case 1323 ... 1343: | |
3457 | case 1358 ... 1359: | |
3458 | case 1368 ... 1375: | |
3459 | case 1378 ... 1383: | |
3460 | case 1388 ... 1391: | |
3461 | case 1393 ... 1395: | |
3462 | case 1402 ... 1403: | |
3463 | case 1410 ... 1471: | |
3464 | case 1522 ... 1535: | |
3465 | /* reserved region; don't read it */ | |
3466 | regbuf[i] = 0; | |
3467 | break; | |
3468 | default: | |
3469 | /* unreserved region */ | |
3470 | regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32))); | |
3471 | } | |
3472 | } | |
3473 | } | |
305282ba | 3474 | |
6446a860 JC |
3475 | static void atl1_get_ringparam(struct net_device *netdev, |
3476 | struct ethtool_ringparam *ring) | |
3477 | { | |
3478 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
3479 | struct atl1_tpd_ring *txdr = &adapter->tpd_ring; | |
3480 | struct atl1_rfd_ring *rxdr = &adapter->rfd_ring; | |
305282ba | 3481 | |
6446a860 JC |
3482 | ring->rx_max_pending = ATL1_MAX_RFD; |
3483 | ring->tx_max_pending = ATL1_MAX_TPD; | |
3484 | ring->rx_mini_max_pending = 0; | |
3485 | ring->rx_jumbo_max_pending = 0; | |
3486 | ring->rx_pending = rxdr->count; | |
3487 | ring->tx_pending = txdr->count; | |
3488 | ring->rx_mini_pending = 0; | |
3489 | ring->rx_jumbo_pending = 0; | |
3490 | } | |
305282ba | 3491 | |
6446a860 JC |
3492 | static int atl1_set_ringparam(struct net_device *netdev, |
3493 | struct ethtool_ringparam *ring) | |
3494 | { | |
3495 | struct atl1_adapter *adapter = netdev_priv(netdev); | |
3496 | struct atl1_tpd_ring *tpdr = &adapter->tpd_ring; | |
3497 | struct atl1_rrd_ring *rrdr = &adapter->rrd_ring; | |
3498 | struct atl1_rfd_ring *rfdr = &adapter->rfd_ring; | |
305282ba | 3499 | |
6446a860 JC |
3500 | struct atl1_tpd_ring tpd_old, tpd_new; |
3501 | struct atl1_rfd_ring rfd_old, rfd_new; | |
3502 | struct atl1_rrd_ring rrd_old, rrd_new; | |
3503 | struct atl1_ring_header rhdr_old, rhdr_new; | |
3504 | int err; | |
305282ba | 3505 | |
6446a860 JC |
3506 | tpd_old = adapter->tpd_ring; |
3507 | rfd_old = adapter->rfd_ring; | |
3508 | rrd_old = adapter->rrd_ring; | |
3509 | rhdr_old = adapter->ring_header; | |
305282ba | 3510 | |
6446a860 JC |
3511 | if (netif_running(adapter->netdev)) |
3512 | atl1_down(adapter); | |
305282ba | 3513 | |
6446a860 JC |
3514 | rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD); |
3515 | rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD : | |
3516 | rfdr->count; | |
3517 | rfdr->count = (rfdr->count + 3) & ~3; | |
3518 | rrdr->count = rfdr->count; | |
305282ba | 3519 | |
6446a860 JC |
3520 | tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD); |
3521 | tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD : | |
3522 | tpdr->count; | |
3523 | tpdr->count = (tpdr->count + 3) & ~3; | |
3524 | ||
3525 | if (netif_running(adapter->netdev)) { | |
3526 | /* try to get new resources before deleting old */ | |
3527 | err = atl1_setup_ring_resources(adapter); | |
3528 | if (err) | |
3529 | goto err_setup_ring; | |
3530 | ||
3531 | /* | |
3532 | * save the new, restore the old in order to free it, | |
3533 | * then restore the new back again | |
3534 | */ | |
305282ba | 3535 | |
6446a860 JC |
3536 | rfd_new = adapter->rfd_ring; |
3537 | rrd_new = adapter->rrd_ring; | |
3538 | tpd_new = adapter->tpd_ring; | |
3539 | rhdr_new = adapter->ring_header; | |
3540 | adapter->rfd_ring = rfd_old; | |
3541 | adapter->rrd_ring = rrd_old; | |
3542 | adapter->tpd_ring = tpd_old; | |
3543 | adapter->ring_header = rhdr_old; | |
3544 | atl1_free_ring_resources(adapter); | |
3545 | adapter->rfd_ring = rfd_new; | |
3546 | adapter->rrd_ring = rrd_new; | |
3547 | adapter->tpd_ring = tpd_new; | |
3548 | adapter->ring_header = rhdr_new; | |
305282ba | 3549 | |
6446a860 JC |
3550 | err = atl1_up(adapter); |
3551 | if (err) | |
3552 | return err; | |
3553 | } | |
305282ba | 3554 | return 0; |
6446a860 JC |
3555 | |
3556 | err_setup_ring: | |
3557 | adapter->rfd_ring = rfd_old; | |
3558 | adapter->rrd_ring = rrd_old; | |
3559 | adapter->tpd_ring = tpd_old; | |
3560 | adapter->ring_header = rhdr_old; | |
3561 | atl1_up(adapter); | |
3562 | return err; | |
305282ba JC |
3563 | } |
3564 | ||
6446a860 JC |
3565 | static void atl1_get_pauseparam(struct net_device *netdev, |
3566 | struct ethtool_pauseparam *epause) | |
305282ba | 3567 | { |
6446a860 JC |
3568 | struct atl1_adapter *adapter = netdev_priv(netdev); |
3569 | struct atl1_hw *hw = &adapter->hw; | |
305282ba | 3570 | |
6446a860 JC |
3571 | if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || |
3572 | hw->media_type == MEDIA_TYPE_1000M_FULL) { | |
3573 | epause->autoneg = AUTONEG_ENABLE; | |
3574 | } else { | |
3575 | epause->autoneg = AUTONEG_DISABLE; | |
305282ba | 3576 | } |
6446a860 JC |
3577 | epause->rx_pause = 1; |
3578 | epause->tx_pause = 1; | |
305282ba JC |
3579 | } |
3580 | ||
6446a860 JC |
3581 | static int atl1_set_pauseparam(struct net_device *netdev, |
3582 | struct ethtool_pauseparam *epause) | |
305282ba | 3583 | { |
6446a860 JC |
3584 | struct atl1_adapter *adapter = netdev_priv(netdev); |
3585 | struct atl1_hw *hw = &adapter->hw; | |
305282ba | 3586 | |
6446a860 JC |
3587 | if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || |
3588 | hw->media_type == MEDIA_TYPE_1000M_FULL) { | |
3589 | epause->autoneg = AUTONEG_ENABLE; | |
3590 | } else { | |
3591 | epause->autoneg = AUTONEG_DISABLE; | |
3592 | } | |
3593 | ||
3594 | epause->rx_pause = 1; | |
3595 | epause->tx_pause = 1; | |
3596 | ||
3597 | return 0; | |
305282ba JC |
3598 | } |
3599 | ||
6446a860 JC |
3600 | /* FIXME: is this right? -- CHS */ |
3601 | static u32 atl1_get_rx_csum(struct net_device *netdev) | |
305282ba | 3602 | { |
6446a860 JC |
3603 | return 1; |
3604 | } | |
305282ba | 3605 | |
6446a860 JC |
3606 | static void atl1_get_strings(struct net_device *netdev, u32 stringset, |
3607 | u8 *data) | |
3608 | { | |
3609 | u8 *p = data; | |
3610 | int i; | |
305282ba | 3611 | |
6446a860 JC |
3612 | switch (stringset) { |
3613 | case ETH_SS_STATS: | |
3614 | for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) { | |
3615 | memcpy(p, atl1_gstrings_stats[i].stat_string, | |
3616 | ETH_GSTRING_LEN); | |
3617 | p += ETH_GSTRING_LEN; | |
3618 | } | |
3619 | break; | |
305282ba | 3620 | } |
305282ba JC |
3621 | } |
3622 | ||
6446a860 | 3623 | static int atl1_nway_reset(struct net_device *netdev) |
305282ba | 3624 | { |
6446a860 JC |
3625 | struct atl1_adapter *adapter = netdev_priv(netdev); |
3626 | struct atl1_hw *hw = &adapter->hw; | |
305282ba | 3627 | |
6446a860 JC |
3628 | if (netif_running(netdev)) { |
3629 | u16 phy_data; | |
3630 | atl1_down(adapter); | |
305282ba | 3631 | |
6446a860 JC |
3632 | if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR || |
3633 | hw->media_type == MEDIA_TYPE_1000M_FULL) { | |
3634 | phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN; | |
3635 | } else { | |
3636 | switch (hw->media_type) { | |
3637 | case MEDIA_TYPE_100M_FULL: | |
3638 | phy_data = MII_CR_FULL_DUPLEX | | |
3639 | MII_CR_SPEED_100 | MII_CR_RESET; | |
3640 | break; | |
3641 | case MEDIA_TYPE_100M_HALF: | |
3642 | phy_data = MII_CR_SPEED_100 | MII_CR_RESET; | |
3643 | break; | |
3644 | case MEDIA_TYPE_10M_FULL: | |
3645 | phy_data = MII_CR_FULL_DUPLEX | | |
3646 | MII_CR_SPEED_10 | MII_CR_RESET; | |
3647 | break; | |
3648 | default: | |
3649 | /* MEDIA_TYPE_10M_HALF */ | |
3650 | phy_data = MII_CR_SPEED_10 | MII_CR_RESET; | |
3651 | } | |
3652 | } | |
3653 | atl1_write_phy_reg(hw, MII_BMCR, phy_data); | |
3654 | atl1_up(adapter); | |
305282ba | 3655 | } |
305282ba JC |
3656 | return 0; |
3657 | } | |
3658 | ||
6446a860 JC |
3659 | const struct ethtool_ops atl1_ethtool_ops = { |
3660 | .get_settings = atl1_get_settings, | |
3661 | .set_settings = atl1_set_settings, | |
3662 | .get_drvinfo = atl1_get_drvinfo, | |
3663 | .get_wol = atl1_get_wol, | |
3664 | .set_wol = atl1_set_wol, | |
3665 | .get_msglevel = atl1_get_msglevel, | |
3666 | .set_msglevel = atl1_set_msglevel, | |
3667 | .get_regs_len = atl1_get_regs_len, | |
3668 | .get_regs = atl1_get_regs, | |
3669 | .get_ringparam = atl1_get_ringparam, | |
3670 | .set_ringparam = atl1_set_ringparam, | |
3671 | .get_pauseparam = atl1_get_pauseparam, | |
3672 | .set_pauseparam = atl1_set_pauseparam, | |
3673 | .get_rx_csum = atl1_get_rx_csum, | |
3674 | .set_tx_csum = ethtool_op_set_tx_hw_csum, | |
3675 | .get_link = ethtool_op_get_link, | |
3676 | .set_sg = ethtool_op_set_sg, | |
3677 | .get_strings = atl1_get_strings, | |
3678 | .nway_reset = atl1_nway_reset, | |
3679 | .get_ethtool_stats = atl1_get_ethtool_stats, | |
3680 | .get_sset_count = atl1_get_sset_count, | |
3681 | .set_tso = ethtool_op_set_tso, | |
3682 | }; |